-#define CFG_BR0_PRELIM 0xFE001801 /* flash */
-#define CFG_OR0_PRELIM 0xFE000836
-#define CFG_BR1_PRELIM (CFG_BCSR | 0x1801) /* BCSR */
-#define CFG_OR1_PRELIM 0xFFFF8010
-#define CFG_BR4_PRELIM 0xF8300801 /* EEPROM */
-#define CFG_OR4_PRELIM 0xFFFF8846
-#define CFG_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */
-#define CFG_OR5_PRELIM 0xFFFF8E36
-#define CFG_BR8_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */
-#define CFG_OR8_PRELIM 0xFFFF8010
-
-#define CFG_RMR 0x0001
-#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CFG_RCCR 0
-#define CFG_MPTPR 0x00001900
-#define CFG_PSRT 0x00000021
+#define CONFIG_SYS_BR0_PRELIM 0xFE001801 /* flash */
+#define CONFIG_SYS_OR0_PRELIM 0xFE000836
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x1801) /* BCSR */
+#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
+#define CONFIG_SYS_BR4_PRELIM 0xF8300801 /* EEPROM */
+#define CONFIG_SYS_OR4_PRELIM 0xFFFF8846
+#define CONFIG_SYS_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */
+#define CONFIG_SYS_OR5_PRELIM 0xFFFF8E36
+#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
+#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
+
+#define CONFIG_SYS_RMR 0x0001
+#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR 0
+#define CONFIG_SYS_MPTPR 0x00001900
+#define CONFIG_SYS_PSRT 0x00000021