+/* ECCX CS settings */
+#define SED13806_OR 0xFFC00108 /* - 4 Mo
+ - Burst inhibit
+ - external TA */
+#define SED13806_REG_ADDR 0xa0000000
+#define SED13806_ACCES 0x801 /* 16 bit access */
+
+
+/* Global definitions for the ECCX board */
+#define ECCX_CSR_ADDR (0xfac00000)
+#define ECCX_CSR8_OFFSET (0x8)
+#define ECCX_CSR11_OFFSET (0xB)
+#define ECCX_CSR12_OFFSET (0xC)
+
+#define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)
+#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)
+#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)
+
+
+#define REG_GPIO_CTRL 0x008
+
+/* Definitions for CSR8 */
+#define ECCX_ENEPSON 0x80 /* Bit 0:
+ 0= disable and reset SED1386
+ 1= enable SED1386 */
+/* Bit 1: 0= SED1386 in Big Endian mode */
+/* 1= SED1386 in little endian mode */
+#define ECCX_LE 0x40
+#define ECCX_BE 0x00
+
+/* Bit 2,3: Selection */
+/* 00 = Disabled */
+/* 01 = CS2 is used for the SED1386 */
+/* 10 = CS5 is used for the SED1386 */
+/* 11 = reserved */
+#define ECCX_CS2 0x10
+#define ECCX_CS5 0x20
+
+/* Definitions for CSR12 */
+#define ECCX_ID 0x02
+#define ECCX_860 0x01
+