-#define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A6 |\
- ORxS_NUMR_13)
-
-#define CFG_LSDMR_9COL (PSDMR_PBI |\
- PSDMR_SDAM_A16_IS_A5 |\
- PSDMR_BSMA_A13_A15 |\
- PSDMR_SDA10_PBI1_A8 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_BL |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_2C |\
- PSDMR_CL_2)
-
-#endif /* CFG_INIT_LOCAL_SDRAM */
-
-#endif /* CFG_RAMBOOT */
-
-#define CFG_CAN0_BASE 0xc0000000
-#define CFG_CAN1_BASE 0xc0008000
-#define CFG_FIOX_BASE 0xc0010000
-#define CFG_FDOHM_BASE 0xc0018000
-#define CFG_EXTPROM_BASE 0xc2000000
-
-#define CFG_CAN_SIZE 0x00000100
-#define CFG_FIOX_SIZE 0x00000020
-#define CFG_FDOHM_SIZE 0x00002000
-#define CFG_EXTPROM_BANK_SIZE 0x01000000
+#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI1_A6 |\
+ ORxS_NUMR_13)
+
+#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\
+ PSDMR_SDAM_A16_IS_A5 |\
+ PSDMR_BSMA_A13_A15 |\
+ PSDMR_SDA10_PBI1_A8 |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_2W |\
+ PSDMR_BL |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_2C |\
+ PSDMR_CL_2)
+
+#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+#define CONFIG_SYS_CAN0_BASE 0xc0000000
+#define CONFIG_SYS_CAN1_BASE 0xc0008000
+#define CONFIG_SYS_FIOX_BASE 0xc0010000
+#define CONFIG_SYS_FDOHM_BASE 0xc0018000
+#define CONFIG_SYS_EXTPROM_BASE 0xc2000000
+
+#define CONFIG_SYS_CAN_SIZE 0x00000100
+#define CONFIG_SYS_FIOX_SIZE 0x00000020
+#define CONFIG_SYS_FDOHM_SIZE 0x00002000
+#define CONFIG_SYS_EXTPROM_BANK_SIZE 0x01000000