-
-SYS_CFG:
- [31:31] MDDRC Soft Reset: Diabled
- [30:30] DRAM CKE pin: Enabled
- [29:29] DRAM CLK: Enabled
- [28:28] Command Mode: Enabled (For initialization only)
- [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
- [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
- [20:19] Read Test: DON'T USE
- [18:18] Self Refresh: Enabled
- [17:17] 16bit Mode: Disabled
- [16:13] Ready Delay: 2
- [12:12] Half DQS Delay: Disabled
- [11:11] Quarter DQS Delay: Disabled
- [10:08] Write Delay: 2
- [07:07] Early ODT: Disabled
- [06:06] On DIE Termination: Disabled
- [05:05] FIFO Overflow Clear: DON'T USE here
- [04:04] FIFO Underflow Clear: DON'T USE here
- [03:03] FIFO Overflow Pending: DON'T USE here
- [02:02] FIFO Underlfow Pending: DON'T USE here
- [01:01] FIFO Overlfow Enabled: Enabled
- [00:00] FIFO Underflow Enabled: Enabled
- TIME_CFG0
- [31:16] DRAM Refresh Time: 0 CSB clocks
- [15:8] DRAM Command Time: 0 CSB clocks
- [07:00] DRAM Precharge Time: 0 CSB clocks
- TIME_CFG1
- [31:26] DRAM tRFC:
- [25:21] DRAM tWR1:
- [20:17] DRAM tWRT1:
- [16:11] DRAM tDRR:
- [10:05] DRAM tRC:
- [04:00] DRAM tRAS:
- TIME_CFG2
- [31:28] DRAM tRCD:
- [27:23] DRAM tFAW:
- [22:19] DRAM tRTW1:
- [18:15] DRAM tCCD:
- [14:10] DRAM tRTP:
- [09:05] DRAM tRP:
- [04:00] DRAM tRPA */
+ *
+ * SYS_CFG:
+ * [31:31] MDDRC Soft Reset: Diabled
+ * [30:30] DRAM CKE pin: Enabled
+ * [29:29] DRAM CLK: Enabled
+ * [28:28] Command Mode: Enabled (For initialization only)
+ * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
+ * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
+ * [20:19] Read Test: DON'T USE
+ * [18:18] Self Refresh: Enabled
+ * [17:17] 16bit Mode: Disabled
+ * [16:13] Ready Delay: 2
+ * [12:12] Half DQS Delay: Disabled
+ * [11:11] Quarter DQS Delay: Disabled
+ * [10:08] Write Delay: 2
+ * [07:07] Early ODT: Disabled
+ * [06:06] On DIE Termination: Disabled
+ * [05:05] FIFO Overflow Clear: DON'T USE here
+ * [04:04] FIFO Underflow Clear: DON'T USE here
+ * [03:03] FIFO Overflow Pending: DON'T USE here
+ * [02:02] FIFO Underlfow Pending: DON'T USE here
+ * [01:01] FIFO Overlfow Enabled: Enabled
+ * [00:00] FIFO Underflow Enabled: Enabled
+ * TIME_CFG0
+ * [31:16] DRAM Refresh Time: 0 CSB clocks
+ * [15:8] DRAM Command Time: 0 CSB clocks
+ * [07:00] DRAM Precharge Time: 0 CSB clocks
+ * TIME_CFG1
+ * [31:26] DRAM tRFC:
+ * [25:21] DRAM tWR1:
+ * [20:17] DRAM tWRT1:
+ * [16:11] DRAM tDRR:
+ * [10:05] DRAM tRC:
+ * [04:00] DRAM tRAS:
+ * TIME_CFG2
+ * [31:28] DRAM tRCD:
+ * [27:23] DRAM tFAW:
+ * [22:19] DRAM tRTW1:
+ * [18:15] DRAM tCCD:
+ * [14:10] DRAM tRTP:
+ * [09:05] DRAM tRP:
+ * [04:00] DRAM tRPA
+ */