-#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
-#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
-#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
-/* Define the boot mode */
-#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
-/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */
-
-#define CONFIG_PANIC_HANG 1
-
-#define ADSP_BF531 0x31
-#define ADSP_BF532 0x32
-#define ADSP_BF533 0x33
-#define BFIN_CPU ADSP_BF533
-
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
-
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 27000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
-/* 1=CLKIN/2 */
-#define CONFIG_CLKIN_HALF 0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
-/* 1=bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
-/* Values can range from 1-64 */
-#define CONFIG_VCO_MULT 22
-/* CONFIG_CCLK_DIV controls what the core clock divider is */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
-/* Values can range from 2-65535 */
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
-#define CONFIG_SPI_BAUD 2
-#define CONFIG_SPI_BAUD_INITBLOCK 4
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-#endif
-
-#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
-#define CONFIG_MEM_MT48LC16M16A2TG_75 1
-
-#define CONFIG_LOADS_ECHO 1
-