#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
#undef CONFIG_SYS_INIT_RAM_DCACHE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
#undef CONFIG_SYS_INIT_RAM_DCACHE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */