-/* ----------------------------------------------------------------------------
- * Supported U-Boot commands
- * ----------------------------------------------------------------------------
- */
-
-#define CONFIG_CMD_JFFS2
-
-#define CONFIG_CMD_NAND
-
-/* ----------------------------------------------------------------------------
- * Supported U-Boot features
- * ----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_LONGHELP
-
-/* Allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Add auto-completion support */
-#define CONFIG_AUTO_COMPLETE
-
-/* ----------------------------------------------------------------------------
- * Supported hardware
- * ----------------------------------------------------------------------------
- */
-
-/* MMC */
-#define CONFIG_GENERIC_MMC
-
-/* SPL */
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-/* Partition tables */
-#define CONFIG_EFI_PARTITION
-
-/* USB
- *
- * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
- * Enable CONFIG_USB_MUSB_UDD for Device functionalities.
- */
-#define CONFIG_USB_OMAP3
-#define CONFIG_USB_MUSB_HCD
-/* #define CONFIG_USB_MUSB_UDC */
-
-/* NAND SPL */
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-
-/*
- * High level configuration options
- */
-#define CONFIG_OMAP /* This is TI OMAP core */
-#define CONFIG_OMAP_GPIO
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
-
-#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
-#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
-
-/*
- * Clock related definitions
- */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/* Size of environment - 128KB */
-#define CONFIG_ENV_SIZE (128 << 10)
-
-/* Size of malloc pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-
-/*
- * Physical Memory Map
- * Note 1: CS1 may or may not be populated
- * Note 2: SDRAM size is expected to be at least 32MB
- */
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/* Limits for memtest */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
-
-/* -----------------------------------------------------------------------------
- * Hardware drivers
- * -----------------------------------------------------------------------------
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/*
- * PISMO support
- */
-/* Monitor at start of flash - Reserve 2 sectors */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-
-/* Start location & size of environment */
-#define ONENAND_ENV_OFFSET 0x260000
-#define SMNAND_ENV_OFFSET 0x260000
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-
-/*
- * NAND
- */
-/* Physical address to access NAND */
-#define CONFIG_SYS_NAND_ADDR NAND_BASE
-
-/* Physical address to access NAND at CS0 */
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-
-/* Max number of NAND devices */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
-/* Timeout values (in ticks) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
- CONFIG_SYS_MAX_NAND_DEVICE)
-
-#define CONFIG_SYS_JFFS2_MEM_NAND
-#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* Start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-/* Size of jffs2 partition */
-#define CONFIG_JFFS2_PART_SIZE 0xf980000