-#define CFG_BANK0_START 0x00000000
-#define CFG_BANK0_END (CFG_MAX_RAM_SIZE/2 - 1)
-#define CFG_BANK0_ENABLE 1
-#define CFG_BANK1_START CFG_MAX_RAM_SIZE/2
-#define CFG_BANK1_END (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK1_ENABLE 1
-#define CFG_BANK2_START 0x3ff00000 /* not available in this design */
-#define CFG_BANK2_END 0x3fffffff
-#define CFG_BANK2_ENABLE 0
-#define CFG_BANK3_START 0x3ff00000
-#define CFG_BANK3_END 0x3fffffff
-#define CFG_BANK3_ENABLE 0
-#define CFG_BANK4_START 0x3ff00000
-#define CFG_BANK4_END 0x3fffffff
-#define CFG_BANK4_ENABLE 0
-#define CFG_BANK5_START 0x3ff00000
-#define CFG_BANK5_END 0x3fffffff
-#define CFG_BANK5_ENABLE 0
-#define CFG_BANK6_START 0x3ff00000
-#define CFG_BANK6_END 0x3fffffff
-#define CFG_BANK6_ENABLE 0
-#define CFG_BANK7_START 0x3ff00000
-#define CFG_BANK7_END 0x3fffffff
-#define CFG_BANK7_ENABLE 0
-
-/*--------------------------------------------------------------------
- * 4.4 - Output Driver Control Register
- *------------------------------------------------------------------*/
-#define CFG_ODCR 0xe5
-
-/*--------------------------------------------------------------------
- * 4.8 - Error Handling Registers
- *------------------------------------------------------------------*/
-#define CFG_ERRENR1 0x11 /* enable SDRAM refresh overflow error */
+#define CONFIG_SYS_BANK0_START 0x00000000
+#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE/2 - 1)
+#define CONFIG_SYS_BANK0_ENABLE 1
+#define CONFIG_SYS_BANK1_START CONFIG_SYS_MAX_RAM_SIZE/2
+#define CONFIG_SYS_BANK1_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK1_ENABLE 1
+#define CONFIG_SYS_BANK2_START 0x3ff00000 /* not available in this design */
+#define CONFIG_SYS_BANK2_END 0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE 0
+#define CONFIG_SYS_BANK3_START 0x3ff00000
+#define CONFIG_SYS_BANK3_END 0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE 0
+#define CONFIG_SYS_BANK4_START 0x3ff00000
+#define CONFIG_SYS_BANK4_END 0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE 0
+#define CONFIG_SYS_BANK5_START 0x3ff00000
+#define CONFIG_SYS_BANK5_END 0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE 0
+#define CONFIG_SYS_BANK6_START 0x3ff00000
+#define CONFIG_SYS_BANK6_END 0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE 0
+#define CONFIG_SYS_BANK7_START 0x3ff00000
+#define CONFIG_SYS_BANK7_END 0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE 0
+
+/*--------------------------------------------------------------------*/
+/* 4.4 - Output Driver Control Register */
+/*--------------------------------------------------------------------*/
+#define CONFIG_SYS_ODCR 0xe5
+
+/*--------------------------------------------------------------------*/
+/* 4.8 - Error Handling Registers */
+/*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/
+#define CONFIG_SYS_ERRENR1 0x11 /* enable SDRAM refresh overflow error */