-// DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161
-
-#define DM9161_BMCR 0 // Basic Mode Control Register
-#define DM9161_BMSR 1 // Basic Mode Status Register
-#define DM9161_PHYID1 2 // PHY Idendifier Register 1
-#define DM9161_PHYID2 3 // PHY Idendifier Register 2
-#define DM9161_ANAR 4 // Auto_Negotiation Advertisement Register
-#define DM9161_ANLPAR 5 // Auto_negotiation Link Partner Ability Register
-#define DM9161_ANER 6 // Auto-negotiation Expansion Register
-#define DM9161_DSCR 16 // Specified Configuration Register
-#define DM9161_DSCSR 17 // Specified Configuration and Status Register
-#define DM9161_10BTCSR 18 // 10BASE-T Configuration and Satus Register
-#define DM9161_MDINTR 21 // Specified Interrupt Register
-#define DM9161_RECR 22 // Specified Receive Error Counter Register
-#define DM9161_DISCR 23 // Specified Disconnect Counter Register
-#define DM9161_RLSR 24 // Hardware Reset Latch State Register
-
-
-// --Bit definitions: DM9161_BMCR
-#define DM9161_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
-#define DM9161_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
-#define DM9161_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps
+/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */
+
+#define DM9161_BMCR 0 /* Basic Mode Control Register */
+#define DM9161_BMSR 1 /* Basic Mode Status Register */
+#define DM9161_PHYID1 2 /* PHY Idendifier Register 1 */
+#define DM9161_PHYID2 3 /* PHY Idendifier Register 2 */
+#define DM9161_ANAR 4 /* Auto_Negotiation Advertisement Register */
+#define DM9161_ANLPAR 5 /* Auto_negotiation Link Partner Ability Register */
+#define DM9161_ANER 6 /* Auto-negotiation Expansion Register */
+#define DM9161_DSCR 16 /* Specified Configuration Register */
+#define DM9161_DSCSR 17 /* Specified Configuration and Status Register */
+#define DM9161_10BTCSR 18 /* 10BASE-T Configuration and Satus Register */
+#define DM9161_MDINTR 21 /* Specified Interrupt Register */
+#define DM9161_RECR 22 /* Specified Receive Error Counter Register */
+#define DM9161_DISCR 23 /* Specified Disconnect Counter Register */
+#define DM9161_RLSR 24 /* Hardware Reset Latch State Register */
+
+
+/* --Bit definitions: DM9161_BMCR */
+#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
+#define DM9161_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */
+#define DM9161_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */