+
+#define SCCR_USBMPHCM 0x00c00000
+#define SCCR_USBMPHCM_SHIFT 22
+#define SCCR_USBDRCM 0x00300000
+#define SCCR_USBDRCM_SHIFT 20
+
+#define SCCR_USBCM_0 0x00000000
+#define SCCR_USBCM_1 0x00500000
+#define SCCR_USBCM_2 0x00A00000
+#define SCCR_USBCM_3 0x00F00000
+
+/* CSn_BDNS - Chip Select memory Bounds Register
+ */
+#define CSBNDS_SA 0x00FF0000
+#define CSBNDS_SA_SHIFT 8
+#define CSBNDS_EA 0x000000FF
+#define CSBNDS_EA_SHIFT 24
+
+/* CSn_CONFIG - Chip Select Configuration Register
+ */
+#define CSCONFIG_EN 0x80000000
+#define CSCONFIG_AP 0x00800000
+#define CSCONFIG_ROW_BIT 0x00000700
+#define CSCONFIG_ROW_BIT_12 0x00000000
+#define CSCONFIG_ROW_BIT_13 0x00000100
+#define CSCONFIG_ROW_BIT_14 0x00000200
+#define CSCONFIG_COL_BIT 0x00000007
+#define CSCONFIG_COL_BIT_8 0x00000000
+#define CSCONFIG_COL_BIT_9 0x00000001
+#define CSCONFIG_COL_BIT_10 0x00000002
+#define CSCONFIG_COL_BIT_11 0x00000003
+
+/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
+ */
+#define TIMING_CFG1_PRETOACT 0x70000000
+#define TIMING_CFG1_PRETOACT_SHIFT 28
+#define TIMING_CFG1_ACTTOPRE 0x0F000000
+#define TIMING_CFG1_ACTTOPRE_SHIFT 24
+#define TIMING_CFG1_ACTTORW 0x00700000
+#define TIMING_CFG1_ACTTORW_SHIFT 20
+#define TIMING_CFG1_CASLAT 0x00070000
+#define TIMING_CFG1_CASLAT_SHIFT 16
+#define TIMING_CFG1_REFREC 0x0000F000
+#define TIMING_CFG1_REFREC_SHIFT 12
+#define TIMING_CFG1_WRREC 0x00000700
+#define TIMING_CFG1_WRREC_SHIFT 8
+#define TIMING_CFG1_ACTTOACT 0x00000070
+#define TIMING_CFG1_ACTTOACT_SHIFT 4
+#define TIMING_CFG1_WRTORD 0x00000007
+#define TIMING_CFG1_WRTORD_SHIFT 0
+#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
+#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
+
+/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
+ */
+#define TIMING_CFG2_CPO 0x0F800000
+#define TIMING_CFG2_CPO_SHIFT 23
+#define TIMING_CFG2_ACSM 0x00080000
+#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
+#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
+#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
+
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN 0x80000000
+#define SDRAM_CFG_SREN 0x40000000
+#define SDRAM_CFG_ECC_EN 0x20000000
+#define SDRAM_CFG_RD_EN 0x10000000
+#define SDRAM_CFG_SDRAM_TYPE 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
+#define SDRAM_CFG_DYN_PWR 0x00200000
+#define SDRAM_CFG_32_BE 0x00080000
+#define SDRAM_CFG_8_BE 0x00040000
+#define SDRAM_CFG_NCAP 0x00020000
+#define SDRAM_CFG_2T_EN 0x00008000
+#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
+
+/* DDR_SDRAM_MODE - DDR SDRAM Mode Register
+ */
+#define SDRAM_MODE_ESD 0xFFFF0000
+#define SDRAM_MODE_ESD_SHIFT 16
+#define SDRAM_MODE_SD 0x0000FFFF
+#define SDRAM_MODE_SD_SHIFT 0
+#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
+#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
+#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
+#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
+#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
+#define DDR_MODE_WEAK 0x0002 /* weak drivers */
+#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
+#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
+#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
+#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
+#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
+#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
+#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
+#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
+#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
+#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
+#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */
+#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
+#define DDR_MODE_MODEREG 0x0000 /* select mode register */
+
+/* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
+ */
+#define SDRAM_INTERVAL_REFINT 0x3FFF0000
+#define SDRAM_INTERVAL_REFINT_SHIFT 16
+#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
+#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
+
+/* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
+ */
+#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
+
+/* ECC_ERR_INJECT - Memory data path error injection mask ECC
+ */
+#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */
+#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */
+#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */
+#define ECC_ERR_INJECT_EEIM_SHIFT 0
+
+/* CAPTURE_ECC - Memory data path read capture ECC
+ */
+#define CAPTURE_ECC_ECE (0xff000000>>24)
+#define CAPTURE_ECC_ECE_SHIFT 0
+
+/* ERR_DETECT - Memory error detect
+ */
+#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */
+#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */
+#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */
+#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */
+
+/* ERR_DISABLE - Memory error disable
+ */
+#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */
+#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */
+#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */
+#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
+ ECC_ERROR_DISABLE_MBED)
+/* ERR_INT_EN - Memory error interrupt enable
+ */
+#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */
+#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
+ ECC_ERR_INT_EN_MSEE)
+/* CAPTURE_ATTRIBUTES - Memory error attributes capture
+ */
+#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */
+#define ECC_CAPT_ATTR_BNUM_SHIFT 28
+#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */
+#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
+#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
+#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
+#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
+#define ECC_CAPT_ATTR_TSIZ_SHIFT 24
+#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
+#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
+#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
+#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
+#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
+#define ECC_CAPT_ATTR_TSRC_I2C 0x9
+#define ECC_CAPT_ATTR_TSRC_JTAG 0xA
+#define ECC_CAPT_ATTR_TSRC_PCI1 0xD
+#define ECC_CAPT_ATTR_TSRC_PCI2 0xE
+#define ECC_CAPT_ATTR_TSRC_DMA 0xF
+#define ECC_CAPT_ATTR_TSRC_SHIFT 16
+#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */
+#define ECC_CAPT_ATTR_TTYP_WRITE 0x1
+#define ECC_CAPT_ATTR_TTYP_READ 0x2
+#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
+#define ECC_CAPT_ATTR_TTYP_SHIFT 12
+#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */
+
+/* ERR_SBE - Single bit ECC memory error management
+ */
+#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */
+#define ECC_ERROR_MAN_SBET_SHIFT 16
+#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */
+#define ECC_ERROR_MAN_SBEC_SHIFT 0
+
+/* BR - Base Registers
+ */
+#define BR0 0x5000 /* Register offset to immr */
+#define BR1 0x5008
+#define BR2 0x5010
+#define BR3 0x5018
+#define BR4 0x5020
+#define BR5 0x5028
+#define BR6 0x5030
+#define BR7 0x5038
+
+#define BR_BA 0xFFFF8000
+#define BR_BA_SHIFT 15
+#define BR_PS 0x00001800
+#define BR_PS_SHIFT 11
+#define BR_PS_8 0x00000800 /* Port Size 8 bit */
+#define BR_PS_16 0x00001000 /* Port Size 16 bit */
+#define BR_PS_32 0x00001800 /* Port Size 32 bit */
+#define BR_DECC 0x00000600
+#define BR_DECC_SHIFT 9
+#define BR_WP 0x00000100
+#define BR_WP_SHIFT 8
+#define BR_MSEL 0x000000E0
+#define BR_MSEL_SHIFT 5
+#define BR_MS_GPCM 0x00000000 /* GPCM */
+#define BR_MS_SDRAM 0x00000060 /* SDRAM */
+#define BR_MS_UPMA 0x00000080 /* UPMA */
+#define BR_MS_UPMB 0x000000A0 /* UPMB */
+#define BR_MS_UPMC 0x000000C0 /* UPMC */
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#define BR_ATOM 0x0000000C
+#define BR_ATOM_SHIFT 2