} Xilinx_Spartan3_Slave_Serial_fns;
/* Device Image Sizes
*********************************************************************/
/* Spartan-III (1.2V) */
} Xilinx_Spartan3_Slave_Serial_fns;
/* Device Image Sizes
*********************************************************************/
/* Spartan-III (1.2V) */
-#define XILINX_XC3S50_SIZE 439264/8
-#define XILINX_XC3S200_SIZE 1047616/8
-#define XILINX_XC3S400_SIZE 1699136/8
-#define XILINX_XC3S1000_SIZE 3223488/8
-#define XILINX_XC3S1500_SIZE 5214784/8
-#define XILINX_XC3S2000_SIZE 7673024/8
-#define XILINX_XC3S4000_SIZE 11316864/8
-#define XILINX_XC3S5000_SIZE 13271936/8
+#define XILINX_XC3S50_SIZE 439264/8
+#define XILINX_XC3S200_SIZE 1047616/8
+#define XILINX_XC3S400_SIZE 1699136/8
+#define XILINX_XC3S1000_SIZE 3223488/8
+#define XILINX_XC3S1500_SIZE 5214784/8
+#define XILINX_XC3S2000_SIZE 7673024/8
+#define XILINX_XC3S4000_SIZE 11316864/8
+#define XILINX_XC3S5000_SIZE 13271936/8
#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S5000E_SIZE, fn_table, cookie }
#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S5000E_SIZE, fn_table, cookie }
/* Spartan-3E devices */
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
/* Spartan-3E devices */
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }