+/* we cover everything with 4 meg pages, and need an extra for L1 */
+unsigned int icplb_table[page_descriptor_table_size][2];
+unsigned int dcplb_table[page_descriptor_table_size][2];
+
+void init_cplbtables(void)
+{
+ int i, j;
+
+ j = 0;
+ icplb_table[j][0] = 0xFFA00000;
+ icplb_table[j][1] = L1_IMEMORY;
+ j++;
+
+ for (i = 0; i < CONFIG_MEM_SIZE / 4; i++) {
+ icplb_table[j][0] = (i * 4 * 1024 * 1024);
+ if (i * 4 * 1024 * 1024 <= CFG_MONITOR_BASE
+ && (i + 1) * 4 * 1024 * 1024 >= CFG_MONITOR_BASE) {
+ icplb_table[j][1] = SDRAM_IKERNEL;
+ } else {
+ icplb_table[j][1] = SDRAM_IGENERIC;
+ }
+ j++;
+ }
+#if defined(CONFIG_BF561)
+ /* MAC space */
+ icplb_table[j][0] = 0x2C000000;
+ icplb_table[j][1] = SDRAM_INON_CHBL;
+ j++;
+ /* Async Memory space */
+ for (i = 0; i < 3; i++) {
+ icplb_table[j][0] = 0x20000000 + i * 4 * 1024 * 1024;
+ icplb_table[j][1] = SDRAM_INON_CHBL;
+ j++;
+ }
+#else
+ icplb_table[j][0] = 0x20000000;
+ icplb_table[j][1] = SDRAM_INON_CHBL;
+#endif
+ j = 0;
+ dcplb_table[j][0] = 0xFF800000;
+ dcplb_table[j][1] = L1_DMEMORY;
+ j++;
+
+ for (i = 0; i < CONFIG_MEM_SIZE / 4; i++) {
+ dcplb_table[j][0] = (i * 4 * 1024 * 1024);
+ if (i * 4 * 1024 * 1024 <= CFG_MONITOR_BASE
+ && (i + 1) * 4 * 1024 * 1024 >= CFG_MONITOR_BASE) {
+ dcplb_table[j][1] = SDRAM_DKERNEL;
+ } else {
+ dcplb_table[j][1] = SDRAM_DGENERIC;
+ }
+ j++;
+ }
+
+#if defined(CONFIG_BF561)
+ /* MAC space */
+ dcplb_table[j][0] = 0x2C000000;
+ dcplb_table[j][1] = SDRAM_EBIU;
+ j++;
+
+ /* Flash space */
+ for (i = 0; i < 3; i++) {
+ dcplb_table[j][0] = 0x20000000 + i * 4 * 1024 * 1024;
+ dcplb_table[j][1] = SDRAM_EBIU;
+ j++;
+ }
+#else
+ dcplb_table[j][0] = 0x20000000;
+ dcplb_table[j][1] = SDRAM_EBIU;
+#endif
+}
+