+ this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[28:25] */
+#endif
+ /* Latch in address */
+ this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+ /*
+ * Wait a while for the data to be ready
+ */
+ if (this->dev_ready)
+ while (!this->dev_ready(mtd))
+ ;
+ else
+ CFG_NAND_READ_DELAY;
+
+ return 0;
+}
+#else
+/*
+ * NAND command for large page NAND devices (2k)
+ */
+static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
+{
+ struct nand_chip *this = mtd->priv;
+ int page_addr = page + block * CFG_NAND_PAGE_COUNT;
+
+ if (this->dev_ready)
+ while (!this->dev_ready(mtd))
+ ;
+ else
+ CFG_NAND_READ_DELAY;
+
+ /* Emulate NAND_CMD_READOOB */
+ if (cmd == NAND_CMD_READOOB) {
+ offs += CFG_NAND_PAGE_SIZE;
+ cmd = NAND_CMD_READ0;
+ }
+
+ /* Begin command latch cycle */
+ this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ /* Set ALE and clear CLE to start address cycle */
+ /* Column address */
+ this->cmd_ctrl(mtd, offs & 0xff,
+ NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
+ this->cmd_ctrl(mtd, (offs >> 8) & 0xff, 0); /* A[11:9] */
+ /* Row address */
+ this->cmd_ctrl(mtd, (page_addr & 0xff), 0); /* A[19:12] */
+ this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff), 0); /* A[27:20] */
+#ifdef CFG_NAND_5_ADDR_CYCLE
+ /* One more address cycle for devices > 128MiB */
+ this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[31:28] */