- MTREG(UART0_SDR, reg);
-#if defined(UART1_SDR)
- MTREG(UART1_SDR, reg);
-#endif
-#if defined(UART2_SDR)
- MTREG(UART2_SDR, reg);
-#endif
-#if defined(UART3_SDR)
- MTREG(UART3_SDR, reg);
-#endif
-
- out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
- out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
- out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
- out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
- out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
- out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
- val = in8(dev_base + UART_LSR); /* clear line status */
- val = in8(dev_base + UART_RBR); /* read receive buffer */
- out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
- out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
-
- return 0;
-}
-
-#else /* CONFIG_440 */
-
-static int uart_post_init (unsigned long dev_base)
-{
- unsigned long reg;
- unsigned long tmp;
- unsigned long clk;
- unsigned long udiv;
- unsigned short bdiv;
- volatile char val;
- int i;
-
- for (i = 0; i < 3500; i++) {
- if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
- break;
- udelay (100);
- }
-
-#if defined(CONFIG_405EZ)
- serial_divs(gd->baudrate, &udiv, &bdiv);
- clk = tmp = reg = 0;
-#else
-#ifdef CONFIG_405EP
- reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
- clk = gd->cpu_clk;
- tmp = CFG_BASE_BAUD * 16;
- udiv = (clk + tmp / 2) / tmp;
- if (udiv > UDIV_MAX) /* max. n bits for udiv */
- udiv = UDIV_MAX;
- reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
- reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
- mtdcr (cpc0_ucr, reg);
-#else /* CONFIG_405EP */
- reg = mfdcr(cntrl0) & ~CR0_MASK;
-#ifdef CFG_EXT_SERIAL_CLOCK
- clk = CFG_EXT_SERIAL_CLOCK;
- udiv = 1;
- reg |= CR0_EXTCLK_ENA;
-#else
- clk = gd->cpu_clk;
-#ifdef CFG_405_UART_ERRATA_59
- udiv = 31; /* Errata 59: stuck at 31 */
-#else
- tmp = CFG_BASE_BAUD * 16;
- udiv = (clk + tmp / 2) / tmp;
- if (udiv > UDIV_MAX) /* max. n bits for udiv */
- udiv = UDIV_MAX;
-#endif
-#endif
- reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
- mtdcr (cntrl0, reg);
-#endif /* CONFIG_405EP */
- tmp = gd->baudrate * udiv * 16;
- bdiv = (clk + tmp / 2) / tmp;
-#endif /* CONFIG_405EZ */
-
- out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
- out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
- out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
- out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
- out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
- out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
- val = in8(dev_base + UART_LSR); /* clear line status */
- val = in8(dev_base + UART_RBR); /* read receive buffer */
- out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
- out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
-
- return (0);
-}
-#endif /* CONFIG_440 */