#define DID0_VER(did0) ((did0>>28)&0x07)
static int stellaris_register_commands(struct command_context_s *cmd_ctx);
#define DID0_VER(did0) ((did0>>28)&0x07)
static int stellaris_register_commands(struct command_context_s *cmd_ctx);
static void stellaris_set_flash_mode(flash_bank_t *bank,int mode);
//static u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
static void stellaris_set_flash_mode(flash_bank_t *bank,int mode);
//static u32 stellaris_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
static int stellaris_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
static int stellaris_mass_erase(struct flash_bank_s *bank);
static int stellaris_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
static int stellaris_mass_erase(struct flash_bank_s *bank);
static int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
{
stellaris_flash_bank_t *stellaris_info;
static int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
{
stellaris_flash_bank_t *stellaris_info;
stellaris_info = calloc(sizeof(stellaris_flash_bank_t), 1);
bank->base = 0x0;
bank->driver_priv = stellaris_info;
stellaris_info = calloc(sizeof(stellaris_flash_bank_t), 1);
bank->base = 0x0;
bank->driver_priv = stellaris_info;
return ERROR_OK;
}
static int stellaris_register_commands(struct command_context_s *cmd_ctx)
{
command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stellaris", NULL, COMMAND_ANY, "stellaris flash specific commands");
return ERROR_OK;
}
static int stellaris_register_commands(struct command_context_s *cmd_ctx)
{
command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stellaris", NULL, COMMAND_ANY, "stellaris flash specific commands");
register_command(cmd_ctx, stm32x_cmd, "mass_erase", stellaris_handle_mass_erase_command, COMMAND_EXEC, "mass erase device");
return ERROR_OK;
}
register_command(cmd_ctx, stm32x_cmd, "mass_erase", stellaris_handle_mass_erase_command, COMMAND_EXEC, "mass erase device");
return ERROR_OK;
}
{
int printed, device_class;
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
{
int printed, device_class;
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
printed = snprintf(buf, buf_size, "\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n",
device_class, StellarisClassname[device_class], stellaris_info->target_name,
'A' + ((stellaris_info->did0>>8) & 0xFF), (stellaris_info->did0) & 0xFF);
buf += printed;
buf_size -= printed;
printed = snprintf(buf, buf_size, "\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n",
device_class, StellarisClassname[device_class], stellaris_info->target_name,
'A' + ((stellaris_info->did0>>8) & 0xFF), (stellaris_info->did0) & 0xFF);
buf += printed;
buf_size -= printed;
- printed = snprintf(buf, buf_size, "did1: 0x%8.8x, arch: 0x%4.4x, eproc: %s, ramsize:%ik, flashsize: %ik\n",
+ printed = snprintf(buf, buf_size, "did1: 0x%8.8x, arch: 0x%4.4x, eproc: %s, ramsize:%ik, flashsize: %ik\n",
stellaris_info->did1, stellaris_info->did1, "ARMV7M", (1+((stellaris_info->dc0>>16) & 0xFFFF))/4, (1+(stellaris_info->dc0 & 0xFFFF))*2);
buf += printed;
buf_size -= printed;
stellaris_info->did1, stellaris_info->did1, "ARMV7M", (1+((stellaris_info->dc0>>16) & 0xFFFF))/4, (1+(stellaris_info->dc0 & 0xFFFF))*2);
buf += printed;
buf_size -= printed;
static void stellaris_read_clock_info(flash_bank_t *bank)
{
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
static void stellaris_read_clock_info(flash_bank_t *bank)
{
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
target_read_u32(target, SCB_BASE|PLLCFG, &pllcfg);
LOG_DEBUG("Stellaris PLLCFG %x", pllcfg);
stellaris_info->rcc = rcc;
target_read_u32(target, SCB_BASE|PLLCFG, &pllcfg);
LOG_DEBUG("Stellaris PLLCFG %x", pllcfg);
stellaris_info->rcc = rcc;
sysdiv = (rcc>>23) & 0xF;
usesysdiv = (rcc>>22) & 0x1;
bypass = (rcc>>11) & 0x1;
sysdiv = (rcc>>23) & 0xF;
usesysdiv = (rcc>>22) & 0x1;
bypass = (rcc>>11) & 0x1;
/* Forget old flash timing */
stellaris_set_flash_mode(bank, 0);
}
/* Forget old flash timing */
stellaris_set_flash_mode(bank, 0);
}
/* Stellaris waits for cmdbit to clear */
while (((status = stellaris_get_flash_status(bank)) & waitbits) && (timeout-- > 0))
{
LOG_DEBUG("status: 0x%x", status);
alive_sleep(1);
}
/* Stellaris waits for cmdbit to clear */
while (((status = stellaris_get_flash_status(bank)) & waitbits) && (timeout-- > 0))
{
LOG_DEBUG("status: 0x%x", status);
alive_sleep(1);
}
/* Flash errors are reflected in the FLASH_CRIS register */
return status;
}
/* Send one command to the flash controller */
/* Flash errors are reflected in the FLASH_CRIS register */
return status;
}
/* Send one command to the flash controller */
target_write_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, fmc);
LOG_DEBUG("Flash command: 0x%x", fmc);
target_write_u32(target, FLASH_CONTROL_BASE|FLASH_FMC, fmc);
LOG_DEBUG("Flash command: 0x%x", fmc);
target_t *target = bank->target;
u32 did0, did1, ver, fam, status;
int i;
target_t *target = bank->target;
u32 did0, did1, ver, fam, status;
int i;
/* Read and parse chip identification register */
target_read_u32(target, SCB_BASE|DID0, &did0);
target_read_u32(target, SCB_BASE|DID1, &did1);
/* Read and parse chip identification register */
target_read_u32(target, SCB_BASE|DID0, &did0);
target_read_u32(target, SCB_BASE|DID1, &did1);
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
if (bank->target->state != TARGET_HALTED)
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
if (bank->target->state != TARGET_HALTED)
u32 flash_fmc, flash_cris;
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
target_t *target = bank->target;
u32 flash_fmc, flash_cris;
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
target_t *target = bank->target;
stellaris_set_flash_mode(bank,0);
/* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC|AMISC);
stellaris_set_flash_mode(bank,0);
/* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC|AMISC);
target_write_u32(target, FLASH_CRIS, 0);
return ERROR_FLASH_OPERATION_FAILED;
}
target_write_u32(target, FLASH_CRIS, 0);
return ERROR_FLASH_OPERATION_FAILED;
}
if (bank->target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (bank->target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if ((first < 0) || (last < first) || (last >= stellaris_info->num_lockbits))
{
return ERROR_FLASH_SECTOR_INVALID;
}
if ((first < 0) || (last < first) || (last >= stellaris_info->num_lockbits))
{
return ERROR_FLASH_SECTOR_INVALID;
}
/* Configure the flash controller timing */
stellaris_read_clock_info(bank);
stellaris_set_flash_mode(bank, 0);
/* Configure the flash controller timing */
stellaris_read_clock_info(bank);
stellaris_set_flash_mode(bank, 0);
}
/* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC|AMISC);
}
/* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC|AMISC);
LOG_DEBUG("fmppe 0x%x",fmppe);
target_write_u32(target, SCB_BASE|FMPPE, fmppe);
/* Commit FMPPE */
LOG_DEBUG("fmppe 0x%x",fmppe);
target_write_u32(target, SCB_BASE|FMPPE, fmppe);
/* Commit FMPPE */
target_write_u32(target, FLASH_CRIS, 0);
return ERROR_FLASH_OPERATION_FAILED;
}
target_write_u32(target, FLASH_CRIS, 0);
return ERROR_FLASH_OPERATION_FAILED;
}
LOG_DEBUG("(bank=%p buffer=%p offset=%08X wcount=%08X)",
bank, buffer, offset, wcount);
LOG_DEBUG("(bank=%p buffer=%p offset=%08X wcount=%08X)",
bank, buffer, offset, wcount);
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
{
LOG_DEBUG("called target_alloc_working_area(target=%p buffer_size=%08X source=%p)",
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
{
LOG_DEBUG("called target_alloc_working_area(target=%p buffer_size=%08X source=%p)",
buffer_size /= 2;
if (buffer_size <= 256)
{
/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
if (write_algorithm)
target_free_working_area(target, write_algorithm);
buffer_size /= 2;
if (buffer_size <= 256)
{
/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
if (write_algorithm)
target_free_working_area(target, write_algorithm);
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
};
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
};
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
target_write_buffer(target, source->address, thisrun_count * 4, buffer);
target_write_buffer(target, source->address, thisrun_count * 4, buffer);
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
LOG_INFO("Algorithm flash write %i words to 0x%x, %i remaining", thisrun_count, address, wcount);
LOG_DEBUG("Algorithm flash write %i words to 0x%x, %i remaining", thisrun_count, address, wcount);
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
LOG_INFO("Algorithm flash write %i words to 0x%x, %i remaining", thisrun_count, address, wcount);
LOG_DEBUG("Algorithm flash write %i words to 0x%x, %i remaining", thisrun_count, address, wcount);
- if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)
+ if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)
target_free_working_area(target, write_algorithm);
target_free_working_area(target, source);
target_free_working_area(target, write_algorithm);
target_free_working_area(target, source);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
/* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC|AMISC);
/* multiple words to be programmed? */
/* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC|AMISC);
/* multiple words to be programmed? */
{
/* try using a block write */
if ((retval = stellaris_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
{
/* try using a block write */
if ((retval = stellaris_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
{
/* if block write failed (no sufficient working area),
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
{
/* if block write failed (no sufficient working area),
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
}
else if (retval == ERROR_FLASH_OPERATION_FAILED)
{
/* if an error occured, we examine the reason, and quit */
target_read_u32(target, FLASH_CRIS, &flash_cris);
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
}
else if (retval == ERROR_FLASH_OPERATION_FAILED)
{
/* if an error occured, we examine the reason, and quit */
target_read_u32(target, FLASH_CRIS, &flash_cris);
LOG_ERROR("flash writing failed with CRIS: 0x%x", flash_cris);
return ERROR_FLASH_OPERATION_FAILED;
}
LOG_ERROR("flash writing failed with CRIS: 0x%x", flash_cris);
return ERROR_FLASH_OPERATION_FAILED;
}
while (words_remaining > 0)
{
if (!(address & 0xff))
LOG_DEBUG("0x%x", address);
while (words_remaining > 0)
{
if (!(address & 0xff))
LOG_DEBUG("0x%x", address);
/* Program one word */
target_write_u32(target, FLASH_FMA, address);
target_write_buffer(target, FLASH_FMD, 4, buffer);
/* Program one word */
target_write_u32(target, FLASH_FMA, address);
target_write_buffer(target, FLASH_FMD, 4, buffer);
{
target_read_u32(target, FLASH_FMC, &flash_fmc);
} while (flash_fmc & FMC_WRITE);
{
target_read_u32(target, FLASH_FMC, &flash_fmc);
} while (flash_fmc & FMC_WRITE);
if (bytes_remaining)
{
u8 last_word[4] = {0xff, 0xff, 0xff, 0xff};
int i = 0;
if (bytes_remaining)
{
u8 last_word[4] = {0xff, 0xff, 0xff, 0xff};
int i = 0;
/* Program one word */
target_write_u32(target, FLASH_FMA, address);
target_write_buffer(target, FLASH_FMD, 4, last_word);
/* Program one word */
target_write_u32(target, FLASH_FMA, address);
target_write_buffer(target, FLASH_FMD, 4, last_word);
target_read_u32(target, FLASH_FMC, &flash_fmc);
} while (flash_fmc & FMC_WRITE);
}
target_read_u32(target, FLASH_FMC, &flash_fmc);
} while (flash_fmc & FMC_WRITE);
}
/* Check access violations */
target_read_u32(target, FLASH_CRIS, &flash_cris);
if (flash_cris & (AMASK))
/* Check access violations */
target_read_u32(target, FLASH_CRIS, &flash_cris);
if (flash_cris & (AMASK))
/* we can't probe on an stellaris
* if this is an stellaris, it has the configured flash
*/
/* we can't probe on an stellaris
* if this is an stellaris, it has the configured flash
*/
if (target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (stellaris_info->did1 == 0)
{
LOG_WARNING("Cannot identify target as Stellaris");
return ERROR_FLASH_OPERATION_FAILED;
}
if (stellaris_info->did1 == 0)
{
LOG_WARNING("Cannot identify target as Stellaris");
return ERROR_FLASH_OPERATION_FAILED;
}
stellaris_set_flash_mode(bank, 0);
/* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC|AMISC);
stellaris_set_flash_mode(bank, 0);
/* Clear and disable flash programming interrupts */
target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC|AMISC);
target_write_u32(target, FLASH_FMA, 0);
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
/* Wait until erase complete */
target_write_u32(target, FLASH_FMA, 0);
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
/* Wait until erase complete */
target_read_u32(target, FLASH_FMC, &flash_fmc);
}
while (flash_fmc & FMC_MERASE);
target_read_u32(target, FLASH_FMC, &flash_fmc);
}
while (flash_fmc & FMC_MERASE);
/* if device has > 128k, then second erase cycle is needed
* this is only valid for older devices, but will not hurt */
if (stellaris_info->num_pages * stellaris_info->pagesize > 0x20000)
/* if device has > 128k, then second erase cycle is needed
* this is only valid for older devices, but will not hurt */
if (stellaris_info->num_pages * stellaris_info->pagesize > 0x20000)
bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
if (!bank)
{
command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
return ERROR_OK;
}
bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
if (!bank)
{
command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
return ERROR_OK;
}
command_print(cmd_ctx, "stellaris mass erase complete");
}
else
{
command_print(cmd_ctx, "stellaris mass erase failed");
}
command_print(cmd_ctx, "stellaris mass erase complete");
}
else
{
command_print(cmd_ctx, "stellaris mass erase failed");
}