+#define CSW_HPROT (1UL << 25) /* ? */
+#define CSW_MASTER_DEBUG (1UL << 29) /* ? */
+#define CSW_SPROT (1UL << 30)
+#define CSW_DBGSWENABLE (1UL << 31)
+
+/* Fields of the MEM-AP's IDR register */
+#define IDR_REV (0xFUL << 28)
+#define IDR_JEP106 (0x7FFUL << 17)
+#define IDR_CLASS (0xFUL << 13)
+#define IDR_VARIANT (0xFUL << 4)
+#define IDR_TYPE (0xFUL << 0)
+
+#define IDR_JEP106_ARM 0x04760000
+
+#define DP_SELECT_APSEL 0xFF000000
+#define DP_SELECT_APBANK 0x000000F0
+#define DP_SELECT_DPBANK 0x0000000F
+#define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
+
+/**
+ * This represents an ARM Debug Interface (v5) Access Port (AP).
+ * Most common is a MEM-AP, for memory access.
+ */
+struct adiv5_ap {
+ /**
+ * DAP this AP belongs to.
+ */
+ struct adiv5_dap *dap;
+
+ /**
+ * Number of this AP.
+ */
+ uint8_t ap_num;
+
+ /**
+ * Default value for (MEM-AP) AP_REG_CSW register.
+ */
+ uint32_t csw_default;
+
+ /**
+ * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
+ * configure an access mode, such as autoincrementing AP_REG_TAR during
+ * word access. "-1" indicates no cached value.
+ */
+ uint32_t csw_value;
+
+ /**
+ * Cache for (MEM-AP) AP_REG_TAR register value This is written to
+ * configure the address being read or written
+ * "-1" indicates no cached value.
+ */
+ uint32_t tar_value;
+
+ /**
+ * Configures how many extra tck clocks are added after starting a
+ * MEM-AP access before we try to read its status (and/or result).
+ */
+ uint32_t memaccess_tck;
+
+ /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
+ uint32_t tar_autoincr_block;
+
+ /* true if packed transfers are supported by the MEM-AP */
+ bool packed_transfers;
+
+ /* true if unaligned memory access is not supported by the MEM-AP */
+ bool unaligned_access_bad;
+
+ /* true if tar_value is in sync with TAR register */
+ bool tar_valid;
+};
+