+ struct reg_cache *cache = armv4_5->core_cache;
+ uint32_t cpsr = 0;
+ unsigned cookie = num;
+
+ /* avoid some needless mode changes
+ * FIXME move some of these to shared ARM code...
+ */
+ if (mode != armv4_5->core_mode) {
+ if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
+ && (mode == ARMV4_5_MODE_USR))
+ mode = ARMV4_5_MODE_ANY;
+ else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
+ mode = ARMV4_5_MODE_ANY;
+
+ if (mode != ARMV4_5_MODE_ANY) {
+ cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
+ .value, 0, 32);
+ cortex_a8_write_core_reg(target, 16,
+ ARMV4_5_MODE_ANY, mode);
+ }
+ }