-/*
- * Cortex-A8 Core register functions
- */
-
-int cortex_a8_load_core_reg_u32(struct target_s *target, int num,
- armv4_5_mode_t mode, uint32_t * value)
-{
- int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
-
- if ((num <= ARM_CPSR))
- {
- /* read a normal core register */
- retval = cortex_a8_dap_read_coreregister_u32(target, value, num);
-
- if (retval != ERROR_OK)
- {
- LOG_ERROR("JTAG failure %i", retval);
- return ERROR_JTAG_DEVICE_ERROR;
- }
- LOG_DEBUG("load from core reg %i value 0x%" PRIx32, num, *value);
- }
- else
- {
- return ERROR_INVALID_ARGUMENTS;
- }
-
- /* Register other than r0 - r14 uses r0 for access */
- if (num > 14)
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 0).dirty =
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 0).valid;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).dirty =
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).valid;
-
- return ERROR_OK;
-}
-
-int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
- armv4_5_mode_t mode, uint32_t value)
-{
- int retval;
-// uint32_t reg;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
-
-#ifdef ARMV7_GDB_HACKS
- /* If the LR register is being modified, make sure it will put us
- * in "thumb" mode, or an INVSTATE exception will occur. This is a
- * hack to deal with the fact that gdb will sometimes "forge"
- * return addresses, and doesn't set the LSB correctly (i.e., when
- * printing expressions containing function calls, it sets LR=0.) */
-
- if (num == 14)
- value |= 0x01;
-#endif
-
- if ((num <= ARM_CPSR))
- {
- retval = cortex_a8_dap_write_coreregister_u32(target, value, num);
- if (retval != ERROR_OK)
- {
- LOG_ERROR("JTAG failure %i", retval);
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, num).dirty =
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, num).valid;
- return ERROR_JTAG_DEVICE_ERROR;
- }
- LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, value);
- }
- else
- {
- return ERROR_INVALID_ARGUMENTS;
- }
-
- return ERROR_OK;
-}
-
-
-int cortex_a8_read_core_reg(struct target_s *target, int num,
- enum armv4_5_mode mode)
-{
- uint32_t value;
- int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
- cortex_a8_dap_read_coreregister_u32(target, &value, num);
-
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
-
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
- buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- mode, num).value, 0, 32, value);
-
- return ERROR_OK;
-}
-
-int cortex_a8_write_core_reg(struct target_s *target, int num,
- enum armv4_5_mode mode, uint32_t value)
-{
- int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
-
- cortex_a8_dap_write_coreregister_u32(target, value, num);
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
-
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
-
- return ERROR_OK;
-}
-
-