+
+ return ERROR_OK;
+}
+
+int mips32_enable_interrupts(struct target *target, int enable)
+{
+ int retval;
+ int update = 0;
+ uint32_t dcr;
+
+ /* read debug control register */
+ if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
+ return retval;
+
+ if (enable)
+ {
+ if (!(dcr & (1 << 4)))
+ {
+ /* enable interrupts */
+ dcr |= (1 << 4);
+ update = 1;
+ }
+ }
+ else
+ {
+ if (dcr & (1 << 4))
+ {
+ /* disable interrupts */
+ dcr &= ~(1 << 4);
+ update = 1;
+ }
+ }
+
+ if (update)
+ {
+ if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
+ return retval;
+ }
+