Add SAMA5D2 Xplained IAR demo.

[freertos] / FreeRTOS / Demo / CORTEX_A5_SAMA5D2x_Xplained_IAR / AtmelFiles / drivers / peripherals / qspi.h

diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/drivers/peripherals/qspi.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/drivers/peripherals/qspi.h
new file mode 100644 (file)
index 0000000..8ea3e75
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/drivers/peripherals/qspi.h
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------------\r
+ *         SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for Quad Serial Peripheral Interface (QSPI) controller.\r
+ *\r
+ */\r
+\r
+#ifndef _QSPI_H_\r
+#define _QSPI_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ *        Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** QSPI Command structure */\r
+struct _qspi_cmd {\r
+       /** Data Transfer Type (QSPI_IFR_TFRTYP_TRSFR_xxx) */\r
+       uint32_t ifr_type;\r
+\r
+       /** Width of Instruction Code, Address, Option Code and Data\r
+        * (QSPI_IFR_WIDTH_xxx) */\r
+       uint32_t ifr_width;\r
+\r
+       /** Flags to select which information is included in the command */\r
+       struct {\r
+               /** 0: don't send instruction code, 1: send instuction code */\r
+               uint32_t instruction:1;\r
+               /** 0: don't send address, 3: send 3-byte address, 4: send\r
+                * 4-byte address */\r
+               uint32_t address:3;\r
+               /** 0: don't send mode bits, 1: send mode bits */\r
+               uint32_t mode:1;\r
+               /** 0: don't send dummy bits, 1: send dummy bits */\r
+               uint32_t dummy:1;\r
+               /** 0: don't send/recieve data, 1: send/recieve data */\r
+               uint32_t data:1;\r
+               /** reserved, not used */\r
+               uint32_t reserved:25;\r
+       } enable;\r
+\r
+       /** Instruction code */\r
+       uint8_t instruction;\r
+\r
+       /** Mode bits */\r
+       uint8_t mode;\r
+\r
+       /** Number of mode cycles */\r
+       uint8_t num_mode_cycles;\r
+\r
+       /** Number of dummy cycles */\r
+       uint8_t num_dummy_cycles;\r
+\r
+       /** QSPI address */\r
+       uint32_t address;\r
+\r
+       /** Address of the TX buffer */\r
+       const void *tx_buffer;\r
+\r
+       /** Address of the RX buffer */\r
+       void *rx_buffer;\r
+\r
+       /** Size of the RX/TX buffer */\r
+       uint32_t buffer_len;\r
+\r
+       /** Timeout for the command execution, in timer ticks */\r
+       uint32_t timeout;\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ *        Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \brief Reset and initialize a QSPI instance.\r
+ *\r
+ * \param qspi the QSPI instance\r
+ */\r
+void qspi_initialize(Qspi *qspi);\r
+\r
+/**\r
+ * \brief Configure the baudrate for a QSPI instance.\r
+ *\r
+ * \param qspi the QSPI instance\r
+ * \param baudrate the requested baudrate\r
+ * \return the actual baudrate configured (can be lower than requested)\r
+ */\r
+uint32_t qspi_set_baudrate(Qspi *qspi, uint32_t baudrate);\r
+\r
+/**\r
+ * \brief Perform a QSPI command.\r
+ *\r
+ * Note that if enable.data is set in the command, data will be sent/recieved:\r
+ * - if tx_buffer is not NULL, data will be sent\r
+ * - if rx_buffer is not NULL, data will be recieved\r
+ * - if both tx_buffer and rx_buffer are NULL, QSPI will be configured in\r
+ * "Continuous Read" mode and random read access can be done at the address\r
+ * returned by get_qspi_mem_from_addr\r
+ *\r
+ * \param qspi the QSPI instance\r
+ * \param cmd the QSPI command to perform\r
+ * \return true if the command was succesfully issued, false otherwise\r
+ */\r
+bool qspi_perform_command(Qspi *qspi, const struct _qspi_cmd *cmd);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _QSPI_H_ */\r