Add SAMA5D2 Xplained IAR demo.

[freertos] / FreeRTOS / Demo / CORTEX_A5_SAMA5D2x_Xplained_IAR / AtmelFiles / target / sama5d2 / component / component_rstc.h

diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/target/sama5d2/component/component_rstc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/target/sama5d2/component/component_rstc.h
new file mode 100644 (file)
index 0000000..946b3aa
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+++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/target/sama5d2/component/component_rstc.h
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+/* ---------------------------------------------------------------------------- */\r
+/*                  Atmel Microcontroller Software Support                      */\r
+/*                       SAM Software Package License                           */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation                                        */\r
+/*                                                                              */\r
+/* All rights reserved.                                                         */\r
+/*                                                                              */\r
+/* Redistribution and use in source and binary forms, with or without           */\r
+/* modification, are permitted provided that the following condition is met:    */\r
+/*                                                                              */\r
+/* - Redistributions of source code must retain the above copyright notice,     */\r
+/* this list of conditions and the disclaimer below.                            */\r
+/*                                                                              */\r
+/* Atmel's name may not be used to endorse or promote products derived from     */\r
+/* this software without specific prior written permission.                     */\r
+/*                                                                              */\r
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_RSTC_COMPONENT_\r
+#define _SAMA5D2_RSTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/**  SOFTWARE API DEFINITION FOR Reset Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_RSTC Reset Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rstc hardware registers */\r
+typedef struct {\r
+  __O  uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */\r
+  __I  uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */\r
+  __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */\r
+} Rstc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */\r
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */\r
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */\r
+#define RSTC_CR_KEY_Pos 24\r
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Write Access Password */\r
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))\r
+#define   RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation.Always reads as 0. */\r
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */\r
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */\r
+#define RSTC_SR_RSTTYP_Pos 8\r
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */\r
+#define   RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) Both VDDCORE and VDDBU rising */\r
+#define   RSTC_SR_RSTTYP_WKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) VDDCORE rising */\r
+#define   RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */\r
+#define   RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */\r
+#define   RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */\r
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */\r
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */\r
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */\r
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */\r
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */\r
+#define RSTC_MR_KEY_Pos 24\r
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */\r
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))\r
+#define   RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_RSTC_COMPONENT_ */\r