Add SAMA5D2 Xplained IAR demo.

[freertos] / FreeRTOS / Demo / CORTEX_A5_SAMA5D2x_Xplained_IAR / AtmelFiles / target / sama5d2 / component / component_sfc.h

diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/target/sama5d2/component/component_sfc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/target/sama5d2/component/component_sfc.h
new file mode 100644 (file)
index 0000000..c4614c3
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+++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/target/sama5d2/component/component_sfc.h
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+/* ---------------------------------------------------------------------------- */\r
+/*                  Atmel Microcontroller Software Support                      */\r
+/*                       SAM Software Package License                           */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation                                        */\r
+/*                                                                              */\r
+/* All rights reserved.                                                         */\r
+/*                                                                              */\r
+/* Redistribution and use in source and binary forms, with or without           */\r
+/* modification, are permitted provided that the following condition is met:    */\r
+/*                                                                              */\r
+/* - Redistributions of source code must retain the above copyright notice,     */\r
+/* this list of conditions and the disclaimer below.                            */\r
+/*                                                                              */\r
+/* Atmel's name may not be used to endorse or promote products derived from     */\r
+/* this software without specific prior written permission.                     */\r
+/*                                                                              */\r
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_SFC_COMPONENT_\r
+#define _SAMA5D2_SFC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/**  SOFTWARE API DEFINITION FOR Secure Fuse Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_SFC Secure Fuse Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Sfc hardware registers */\r
+typedef struct {\r
+  __O  uint32_t SFC_KR;        /**< \brief (Sfc Offset: 0x00) SFC Key Register */\r
+  __IO uint32_t SFC_MR;        /**< \brief (Sfc Offset: 0X04) SFC Mode Register */\r
+  __I  uint32_t Reserved1[2];\r
+  __IO uint32_t SFC_IER;       /**< \brief (Sfc Offset: 0x10) SFC Interrupt Enable Register */\r
+  __IO uint32_t SFC_IDR;       /**< \brief (Sfc Offset: 0x14) SFC Interrupt Disable Register */\r
+  __I  uint32_t SFC_IMR;       /**< \brief (Sfc Offset: 0x18) SFC Interrupt Mask Register */\r
+  __I  uint32_t SFC_SR;        /**< \brief (Sfc Offset: 0x1C) SFC Status Register */\r
+  __IO uint32_t SFC_DR[24];    /**< \brief (Sfc Offset: 0x20) SFC Data Register */\r
+  __I  uint32_t Reserved2[31];\r
+  __I  uint32_t SFC_VERSION;   /**< \brief (Sfc Offset: 0xFC) Version Register */\r
+} Sfc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SFC_KR : (SFC Offset: 0x00) SFC Key Register -------- */\r
+#define SFC_KR_KEY_Pos 0\r
+#define SFC_KR_KEY_Msk (0xffu << SFC_KR_KEY_Pos) /**< \brief (SFC_KR) Key Code */\r
+#define SFC_KR_KEY(value) ((SFC_KR_KEY_Msk & ((value) << SFC_KR_KEY_Pos)))\r
+/* -------- SFC_MR : (SFC Offset: 0X04) SFC Mode Register -------- */\r
+#define SFC_MR_MSK (0x1u << 0) /**< \brief (SFC_MR) Mask Data Registers */\r
+#define SFC_MR_SASEL (0x1u << 4) /**< \brief (SFC_MR) Sense Amplifier Selection */\r
+/* -------- SFC_IER : (SFC Offset: 0x10) SFC Interrupt Enable Register -------- */\r
+#define SFC_IER_PGMC (0x1u << 0) /**< \brief (SFC_IER) Programming Sequence Completed Interrupt Enable */\r
+#define SFC_IER_PGMF (0x1u << 1) /**< \brief (SFC_IER) Programming Sequence Failed Interrupt Enable */\r
+#define SFC_IER_LCHECK (0x1u << 4) /**< \brief (SFC_IER) Live Integrity Check Error Interrupt Enable */\r
+#define SFC_IER_APLE (0x1u << 16) /**< \brief (SFC_IER) Atmel Programming Lock Error Interrupt Enable */\r
+#define SFC_IER_ACE (0x1u << 17) /**< \brief (SFC_IER) Atmel Check Error Interrupt Enable */\r
+/* -------- SFC_IDR : (SFC Offset: 0x14) SFC Interrupt Disable Register -------- */\r
+#define SFC_IDR_PGMC (0x1u << 0) /**< \brief (SFC_IDR) Programming Sequence Completed Interrupt Disable */\r
+#define SFC_IDR_PGMF (0x1u << 1) /**< \brief (SFC_IDR) Programming Sequence Failed Interrupt Disable */\r
+#define SFC_IDR_LCHECK (0x1u << 4) /**< \brief (SFC_IDR) Live Integrity Check Error Interrupt Disable */\r
+#define SFC_IDR_APLE (0x1u << 16) /**< \brief (SFC_IDR) Atmel Programming Lock Error Interrupt Disable */\r
+#define SFC_IDR_ACE (0x1u << 17) /**< \brief (SFC_IDR) Atmel Check Error Interrupt Disable */\r
+/* -------- SFC_IMR : (SFC Offset: 0x18) SFC Interrupt Mask Register -------- */\r
+#define SFC_IMR_PGMC (0x1u << 0) /**< \brief (SFC_IMR) Programming Sequence Completed Interrupt Mask */\r
+#define SFC_IMR_PGMF (0x1u << 1) /**< \brief (SFC_IMR) Programming Sequence Failed Interrupt Mask */\r
+#define SFC_IMR_LCHECK (0x1u << 4) /**< \brief (SFC_IMR) Live Integrity Checking Error Interrupt Mask */\r
+#define SFC_IMR_APLE (0x1u << 16) /**< \brief (SFC_IMR) Atmel Programming Lock Error Interrupt Mask */\r
+#define SFC_IMR_ACE (0x1u << 17) /**< \brief (SFC_IMR) Atmel Check Error Interrupt Mask */\r
+/* -------- SFC_SR : (SFC Offset: 0x1C) SFC Status Register -------- */\r
+#define SFC_SR_PGMC (0x1u << 0) /**< \brief (SFC_SR) Programming Sequence Completed (cleared on read) */\r
+#define SFC_SR_PGMF (0x1u << 1) /**< \brief (SFC_SR) Programming Sequence Failed (cleared on read) */\r
+#define SFC_SR_LCHECK (0x1u << 4) /**< \brief (SFC_SR) Live Integrity Checking Error (cleared on read) */\r
+#define SFC_SR_APLE (0x1u << 16) /**< \brief (SFC_SR) Atmel Programming Lock Error (cleared on read) */\r
+#define SFC_SR_ACE (0x1u << 17) /**< \brief (SFC_SR) Atmel Check Error (cleared on read) */\r
+/* -------- SFC_DR[24] : (SFC Offset: 0x20) SFC Data Register -------- */\r
+#define SFC_DR_DATA_Pos 0\r
+#define SFC_DR_DATA_Msk (0xffffffffu << SFC_DR_DATA_Pos) /**< \brief (SFC_DR[24]) Fuse Data */\r
+#define SFC_DR_DATA(value) ((SFC_DR_DATA_Msk & ((value) << SFC_DR_DATA_Pos)))\r
+/* -------- SFC_VERSION : (SFC Offset: 0xFC) Version Register -------- */\r
+#define SFC_VERSION_VERSION_Pos 0\r
+#define SFC_VERSION_VERSION_Msk (0xfffu << SFC_VERSION_VERSION_Pos) /**< \brief (SFC_VERSION) Hardware Module Version */\r
+#define SFC_VERSION_MFN_Pos 16\r
+#define SFC_VERSION_MFN_Msk (0x7u << SFC_VERSION_MFN_Pos) /**< \brief (SFC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_SFC_COMPONENT_ */\r