--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D21_\r
+#define _SAMA5D21_\r
+\r
+/** \addtogroup SAMA5D21_definitions SAMA5D21 definitions\r
+ This file defines all structures and symbols for SAMA5D21:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "compiler.h"\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D21_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_aesb.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_aic.h"\r
+#include "component/component_aximx.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_classd.h"\r
+#include "component/component_flexcom.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_i2sc.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isc.h"\r
+#include "component/component_l2cc.h"\r
+#include "component/component_lcdc.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_mpddrc.h"\r
+#include "component/component_pdmic.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pit.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rxlp.h"\r
+#include "component/component_sckc.h"\r
+#include "component/component_sdmmc.h"\r
+#include "component/component_sfc.h"\r
+#include "component/component_sfr.h"\r
+#include "component/component_sfrbu.h"\r
+#include "component/component_sha.h"\r
+#include "component/component_shdwc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_tdes.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_udphs.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMA5D21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D21_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#define AXIMX ((Aximx *)0x00600000U) /**< \brief (AXIMX ) Base Address */\r
+#define L2CC ((L2cc *)0x00A00000U) /**< \brief (L2CC ) Base Address */\r
+#define SDMMC0 ((Sdmmc *)0xB0000000U) /**< \brief (SDMMC0 ) Base Address */\r
+#define LCDC ((Lcdc *)0xF0000000U) /**< \brief (LCDC ) Base Address */\r
+#define XDMAC1 ((Xdmac *)0xF0004000U) /**< \brief (XDMAC1 ) Base Address */\r
+#define ISC ((Isc *)0xF0008000U) /**< \brief (ISC ) Base Address */\r
+#define MPDDRC ((Mpddrc *)0xF000C000U) /**< \brief (MPDDRC ) Base Address */\r
+#define XDMAC0 ((Xdmac *)0xF0010000U) /**< \brief (XDMAC0 ) Base Address */\r
+#define PMC ((Pmc *)0xF0014000U) /**< \brief (PMC ) Base Address */\r
+#define MATRIX0 ((Matrix *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */\r
+#define AESB ((Aesb *)0xF001C000U) /**< \brief (AESB ) Base Address */\r
+#define QSPI0 ((Qspi *)0xF0020000U) /**< \brief (QSPI0 ) Base Address */\r
+#define QSPI1 ((Qspi *)0xF0024000U) /**< \brief (QSPI1 ) Base Address */\r
+#define SHA ((Sha *)0xF0028000U) /**< \brief (SHA ) Base Address */\r
+#define AES ((Aes *)0xF002C000U) /**< \brief (AES ) Base Address */\r
+#define SPI0 ((Spi *)0xF8000000U) /**< \brief (SPI0 ) Base Address */\r
+#define SSC0 ((Ssc *)0xF8004000U) /**< \brief (SSC0 ) Base Address */\r
+#define GMAC0 ((Gmac *)0xF8008000U) /**< \brief (GMAC0 ) Base Address */\r
+#define TC0 ((Tc *)0xF800C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0xF8010000U) /**< \brief (TC1 ) Base Address */\r
+#define HSMC ((Smc *)0xF8014000U) /**< \brief (HSMC ) Base Address */\r
+#define PDMIC ((Pdmic *)0xF8018000U) /**< \brief (PDMIC ) Base Address */\r
+#define UART0 ((Uart *)0xF801C000U) /**< \brief (UART0 ) Base Address */\r
+#define UART1 ((Uart *)0xF8020000U) /**< \brief (UART1 ) Base Address */\r
+#define UART2 ((Uart *)0xF8024000U) /**< \brief (UART2 ) Base Address */\r
+#define TWIHS0 ((Twihs *)0xF8028000U) /**< \brief (TWIHS0 ) Base Address */\r
+#define PWM ((Pwm *)0xF802C000U) /**< \brief (PWM ) Base Address */\r
+#define SFR ((Sfr *)0xF8030000U) /**< \brief (SFR ) Base Address */\r
+#define FLEXCOM0 ((Flexcom *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */\r
+#define USART0 ((Usart *)0xF8034200U) /**< \brief (FLEXCOM0_USART) Base Address */\r
+#define FCOMSPI0 ((Spi *)0xF8034400U) /**< \brief (FLEXCOM0_SPI) Base Address */\r
+#define TWI0 ((Twi *)0xF8034600U) /**< \brief (FLEXCOM0_TWI) Base Address */\r
+#define FLEXCOM1 ((Flexcom *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */\r
+#define USART1 ((Usart *)0xF8038200U) /**< \brief (FLEXCOM1_USART) Base Address */\r
+#define FCOMSPI1 ((Spi *)0xF8038400U) /**< \brief (FLEXCOM1_SPI) Base Address */\r
+#define TWI1 ((Twi *)0xF8038600U) /**< \brief (FLEXCOM1_TWI) Base Address */\r
+#define SAIC ((Aic *)0xF803C000U) /**< \brief (SAIC ) Base Address */\r
+#define ICM ((Icm *)0xF8040000U) /**< \brief (ICM ) Base Address */\r
+#define RSTC ((Rstc *)0xF8048000U) /**< \brief (RSTC ) Base Address */\r
+#define SHDWC ((Shdwc *)0xF8048010U) /**< \brief (SHDWC ) Base Address */\r
+#define PIT ((Pit *)0xF8048030U) /**< \brief (PIT ) Base Address */\r
+#define WDT ((Wdt *)0xF8048040U) /**< \brief (WDT ) Base Address */\r
+#define SCKC ((Sckc *)0xF8048050U) /**< \brief (SCKC ) Base Address */\r
+#define RTC ((Rtc *)0xF80480B0U) /**< \brief (RTC ) Base Address */\r
+#define RXLP ((Rxlp *)0xF8049000U) /**< \brief (RXLP ) Base Address */\r
+#define ACC ((Acc *)0xF804A000U) /**< \brief (ACC ) Base Address */\r
+#define SFC ((Sfc *)0xF804C000U) /**< \brief (SFC ) Base Address */\r
+#define I2SC0 ((I2sc *)0xF8050000U) /**< \brief (I2SC0 ) Base Address */\r
+#define SPI1 ((Spi *)0xFC000000U) /**< \brief (SPI1 ) Base Address */\r
+#define SSC1 ((Ssc *)0xFC004000U) /**< \brief (SSC1 ) Base Address */\r
+#define UART3 ((Uart *)0xFC008000U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0xFC00C000U) /**< \brief (UART4 ) Base Address */\r
+#define FLEXCOM3 ((Flexcom *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */\r
+#define USART3 ((Usart *)0xFC014200U) /**< \brief (FLEXCOM3_USART) Base Address */\r
+#define FCOMSPI3 ((Spi *)0xFC014400U) /**< \brief (FLEXCOM3_SPI) Base Address */\r
+#define TWI3 ((Twi *)0xFC014600U) /**< \brief (FLEXCOM3_TWI) Base Address */\r
+#define FLEXCOM4 ((Flexcom *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */\r
+#define USART4 ((Usart *)0xFC018200U) /**< \brief (FLEXCOM4_USART) Base Address */\r
+#define FCOMSPI4 ((Spi *)0xFC018400U) /**< \brief (FLEXCOM4_SPI) Base Address */\r
+#define TWI4 ((Twi *)0xFC018600U) /**< \brief (FLEXCOM4_TWI) Base Address */\r
+#define TRNG ((Trng *)0xFC01C000U) /**< \brief (TRNG ) Base Address */\r
+#define AIC ((Aic *)0xFC020000U) /**< \brief (AIC ) Base Address */\r
+#define TWIHS1 ((Twihs *)0xFC028000U) /**< \brief (TWIHS1 ) Base Address */\r
+#define UDPHS ((Udphs *)0xFC02C000U) /**< \brief (UDPHS ) Base Address */\r
+#define ADC ((Adc *)0xFC030000U) /**< \brief (ADC ) Base Address */\r
+#define PIOA ((Pio *)0xFC038000U) /**< \brief (PIOA ) Base Address */\r
+#define MATRIX1 ((Matrix *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */\r
+#define TDES ((Tdes *)0xFC044000U) /**< \brief (TDES ) Base Address */\r
+#define CLASSD ((Classd *)0xFC048000U) /**< \brief (CLASSD ) Base Address */\r
+#define I2SC1 ((I2sc *)0xFC04C000U) /**< \brief (I2SC1 ) Base Address */\r
+#define SFRBU ((Sfrbu *)0xFC05C000U) /**< \brief (SFRBU ) Base Address */\r
+#define CHIPID ((Chipid *)0xFC069000U) /**< \brief (CHIPID ) Base Address */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMA5D21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D21_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sama5d21.h"\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMA5D21 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#define EBI_CS0_ADDR (0x10000000u) /**< EBI Chip Select 0 base address */\r
+#define DDR_CS_ADDR (0x20000000u) /**< DDR Chip Select base address */\r
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */\r
+#define EBI_CS1_ADDR (0x60000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x70000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x80000000u) /**< EBI Chip Select 3 base address */\r
+#define QSPI_AES0_ADDR (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */\r
+#define QSPI_AES1_ADDR (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */\r
+#define SDMMC0_ADDR (0xB0000000u) /**< SDMMC 0 base address */\r
+#define NFC_ADDR (0xC0000000u) /**< NAND Flash Controller Command base address */\r
+#define QSPIMEM0_ADDR (0xD0000000u) /**< QSPI Memory 0 base address */\r
+#define QSPIMEM1_ADDR (0xD8000000u) /**< QSPI Memory 1 base address */\r
+#define IROM_ADDR (0x00000000u) /**< Internal ROM base address */\r
+#define ECC_ROM_ADDR (0x00040000u) /**< ECC ROM base address */\r
+#define NFC_RAM_ADDR (0x00100000u) /**< NAND Flash Controller RAM base address */\r
+#define IRAM0_ADDR (0x00200000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x00220000u) /**< Internal RAM 1 base address */\r
+#define UDPHS_RAM_ADDR (0x00300000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */\r
+#define AXIMX_ADDR (0x00600000u) /**< AXI Bus Matrix base address */\r
+#define DAP_ADDR (0x00700000u) /**< Debug Access Port base address */\r
+#define PTCMEM_ADDR (0x00800000u) /**< PTC Memory base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMA5D21 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3F03FUL)\r
+#define CHIP_CIDR (0x8A5C08C0UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMA5D21 */\r
+/* ************************************************************************** */\r
+\r
+/* %ATMEL_ELECTRICAL% */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMA5D21_ */\r
projects / freertos / blobdiff