Add SAMA5D2 Xplained IAR demo.

[freertos] / FreeRTOS / Demo / CORTEX_A5_SAMA5D2x_Xplained_IAR / AtmelFiles / target / sama5d2 / toolchain / gnu / common.gdb

diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/target/sama5d2/toolchain/gnu/common.gdb b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/target/sama5d2/toolchain/gnu/common.gdb
new file mode 100644 (file)
index 0000000..47ec2dc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/target/sama5d2/toolchain/gnu/common.gdb
@@ -0,0 +1,102 @@
+# Connect to the J-Link gdb server\r
+define jlink_connect\r
+  target remote localhost:2331\r
+end\r
+\r
+define reset_peripherals\r
+  # Disable all interrupts and go to supervisor mode\r
+  mon reg cpsr = 0xd3\r
+\r
+  # Reset the chip to get to a known state\r
+  #monitor reset\r
+\r
+  # Reset peripherals (using RSTC_CR)\r
+  set *0xF8048000 = 0xA5000004\r
+\r
+  # Reset L2 Cache controller\r
+  set *0x00A00100 = 0x0\r
+\r
+  # Disable Watchdog (using WDT_MR)\r
+  set *0xF8048044 = 0x00008000\r
+\r
+  # Disable D-Cache, I-Cache and MMU\r
+  mon cp15 1 0 0 0 = 0x00C50078\r
+end\r
+\r
+# Disable DDR clock and MPDDRC controller\r
+# to avoid corrupted RAM data on soft reset.\r
+define disable_ddr\r
+  set *0xF0014004 = 0x4\r
+  set *0xF0014014 = (1 << 13)  \r
+end\r
+\r
+define reset_registers\r
+  # Zero registers (cannot reset core because it will disable JTAG)\r
+  mon reg r8_fiq = 0\r
+  mon reg r9_fiq = 0\r
+  mon reg r10_fiq = 0\r
+  mon reg r11_fiq = 0\r
+  mon reg r12_fiq = 0\r
+  mon reg sp_fiq = 0\r
+  mon reg lr_fiq = 0\r
+  mon reg spsr_fiq = 0\r
+  mon reg sp_irq = 0\r
+  mon reg lr_irq = 0\r
+  mon reg spsr_irq = 0\r
+  mon reg sp_abt = 0\r
+  mon reg lr_abt = 0\r
+  mon reg spsr_abt = 0\r
+  mon reg sp_und = 0\r
+  mon reg lr_und = 0\r
+  mon reg spsr_und = 0\r
+  mon reg sp_svc = 0\r
+  mon reg lr_svc = 0\r
+  mon reg spsr_svc = 0\r
+  mon reg r0 = 0\r
+  mon reg r1 = 0\r
+  mon reg r2 = 0\r
+  mon reg r3 = 0\r
+  mon reg r4 = 0\r
+  mon reg r5 = 0\r
+  mon reg r6 = 0\r
+  mon reg r7 = 0\r
+  mon reg r8_usr = 0\r
+  mon reg r9_usr = 0\r
+  mon reg r10_usr = 0\r
+  mon reg r11_usr = 0\r
+  mon reg r12_usr = 0\r
+  mon reg sp_usr = 0\r
+  mon reg lr_usr = 0  \r
+end\r
+\r
+define init_ddr  \r
+\r
+  reset_registers\r
+  \r
+  load target/bootstrap.elf\r
+  \r
+  # Initialize PC\r
+  mon reg pc = 0x00200000\r
+  mon reg pc = 0x00200000\r
+\r
+  continue\r
+end\r
+\r
+define load_in_ddr\r
+\r
+  reset_registers\r
+\r
+  load\r
+  \r
+  # Initialize PC\r
+  mon reg pc = 0x20000000\r
+end\r
+\r
+define load_in_sram\r
+  reset_registers\r
+\r
+  load\r
+\r
+  # Initialize PC\r
+  mon reg pc = 0x00200000\r
+end\r