--- /dev/null
+/*********************************************************************\r
+* execUserReset()\r
+*********************************************************************/\r
+execUserReset()\r
+{\r
+ __message "------------------------------ execUserReset ---------------------------------";\r
+\r
+ /* Reset peripherals (using RSTC_CR) */\r
+ __writeMemory32(0xA5000004, 0xF8048000, "Memory");\r
+\r
+ /* Disable Watchdog (using WDT_MR) */\r
+ __writeMemory32(0x00008000, 0xF8048044, "Memory");\r
+\r
+ /* Disable D-Cache, I-Cache and MMU */\r
+ __jtagCP15WriteReg(1, 0, 0, 0, 0x00C50078);\r
+\r
+ /* Reset L2 Cache controller */\r
+ __writeMemory32(0x0, 0x00A00100, "Memory");\r
+\r
+ /* Disable DDR clock and MPDDRC controller to avoid */\r
+ /* corrupted RAM data on soft reset. */\r
+ __writeMemory32(0x00000004, 0xF0014004, "Memory");\r
+ __writeMemory32(0x00002000, 0xF0014014, "Memory");\r
+\r
+ /* Disable all interrupts and go to supervisor mode */\r
+ #CPSR = 0xD3;\r
+\r
+ /* Zero registers (cannot reset core because it will disable JTAG) */\r
+ #R8_fiq = 0;\r
+ #R9_fiq = 0;\r
+ #R10_fiq = 0;\r
+ #R11_fiq = 0;\r
+ #R12_fiq = 0;\r
+ #SP_fiq = 0;\r
+ #LR_fiq = 0;\r
+ #SPSR_fiq = 0;\r
+ #SP_irq = 0;\r
+ #LR_irq = 0;\r
+ #SPSR_irq = 0;\r
+ #SP_abt = 0;\r
+ #LR_abt = 0;\r
+ #SPSR_abt = 0;\r
+ #SP_und = 0;\r
+ #LR_und = 0;\r
+ #SPSR_und = 0;\r
+ #SP_svc = 0;\r
+ #LR_svc = 0;\r
+ #SPSR_svc = 0;\r
+ #R0 = 0;\r
+ #R1 = 0;\r
+ #R2 = 0;\r
+ #R3 = 0;\r
+ #R4 = 0;\r
+ #R5 = 0;\r
+ #R6 = 0;\r
+ #R7 = 0;\r
+ #R8_usr = 0;\r
+ #R9_usr = 0;\r
+ #R10_usr = 0;\r
+ #R11_usr = 0;\r
+ #R12_usr = 0;\r
+ #SP_usr = 0;\r
+ #LR_usr = 0;\r
+\r
+ /* Initialize PC */\r
+ #PC = 0x200000;\r
+}\r
+\r
+/*********************************************************************\r
+* execUserPreload()\r
+*********************************************************************/\r
+execUserPreload()\r
+{\r
+ __message "------------------------------ execUserPreload ---------------------------------";\r
+}\r