--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+ IAR startup file for AT91SAMA5D3X microcontrollers.\r
+ */\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION IRQ_STACK:DATA:NOROOT(2)\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+//#define __ASSEMBLY__\r
+//#include "board.h"\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+#define ARM_MODE_ABT 0x17\r
+#define ARM_MODE_FIQ 0x11\r
+#define ARM_MODE_IRQ 0x12\r
+#define ARM_MODE_SVC 0x13\r
+#define ARM_MODE_SYS 0x1F\r
+\r
+#define I_BIT 0x80\r
+#define F_BIT 0x40\r
+\r
+//------------------------------------------------------------------------------\r
+// Startup routine\r
+//------------------------------------------------------------------------------\r
+\r
+/*\r
+ Exception vectors\r
+ */\r
+ SECTION .vectors:CODE:NOROOT(2)\r
+\r
+ PUBLIC resetVector\r
+\r
+ EXTERN FreeRTOS_IRQ_Handler\r
+ EXTERN Undefined_Handler\r
+ EXTERN FreeRTOS_SWI_Handler\r
+ EXTERN Prefetch_Handler\r
+ EXTERN Abort_Handler\r
+ EXTERN FIQ_Handler\r
+\r
+ ARM\r
+\r
+__iar_init$$done: ; The interrupt vector is not needed\r
+ ; until after copy initialization is done\r
+\r
+resetVector:\r
+ ; All default exception handlers (except reset) are\r
+ ; defined as weak symbol definitions.\r
+ ; If a handler is defined by the application it will take precedence.\r
+ LDR pc, =resetHandler ; Reset\r
+ LDR pc, Undefined_Addr ; Undefined instructions\r
+ LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)\r
+ LDR pc, Prefetch_Addr ; Prefetch abort\r
+ LDR pc, Abort_Addr ; Data abort\r
+ B . ; RESERVED\r
+ LDR pc, IRQ_Addr ; IRQ\r
+ LDR pc, FIQ_Addr ; FIQ\r
+\r
+IRQ_Addr: DCD FreeRTOS_IRQ_Handler\r
+Undefined_Addr: DCD Undefined_Handler\r
+SWI_Addr: DCD FreeRTOS_SWI_Handler\r
+Prefetch_Addr: DCD Prefetch_Handler\r
+Abort_Addr: DCD Abort_Handler\r
+FIQ_Addr: DCD FIQ_Handler\r
+\r
+\r
+/*\r
+ After a reset, execution starts here, the mode is ARM, supervisor\r
+ with interrupts disabled.\r
+ Initializes the chip and branches to the main() function.\r
+ */\r
+ SECTION .cstartup:CODE:NOROOT(2)\r
+\r
+ PUBLIC resetHandler\r
+ EXTERN low_level_init\r
+ EXTERN ?main\r
+ REQUIRE resetVector\r
+ ARM\r
+\r
+resetHandler:\r
+ CPSIE A\r
+ /* Enable VFP */\r
+ /* - Enable access to CP10 and CP11 in CP15.CACR */\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ orr r0, r0, #0xf00000\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ /* - Enable access to CP10 and CP11 in CP15.NSACR */\r
+ /* - Set FPEXC.EN (B30) */\r
+ fmrx r0, fpexc\r
+ orr r0, r0, #0x40000000\r
+ fmxr fpexc, r0\r
+ /* Set pc to actual code location (i.e. not in remap zone) */\r
+ LDR pc, =label\r
+\r
+ /* Perform low-level initialization of the chip using LowLevelInit() */\r
+label:\r
+ /* Sets up Supervisor stack before running LowLevelInit. The supervisor\r
+ stack is reused by interrupts, which switch from IRQ mode to SVC mode. */\r
+ LDR r0, =low_level_init\r
+ LDR r4, =SFE(CSTACK)\r
+ MOV sp, r4\r
+ BLX r0\r
+\r
+ /* Set up the interrupt stack pointer. */\r
+ MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode\r
+ LDR sp, =SFE(IRQ_STACK)\r
+\r
+ /* No need to set up stacks for any other mode as that stack used by\r
+ tasks is allocated by FreeRTOS. */\r
+\r
+ /* Back to Supervisor mode bfore calling main(). The schduduler should\r
+ be started from Supervisor mode. */\r
+ MSR cpsr_c, #ARM_MODE_SVC | F_BIT ; Change the mode\r
+\r
+ /* Branch to main() */\r
+ LDR r0, =?main\r
+ BLX r0\r
+\r
+ /* Loop indefinitely when program is finished */\r
+loop4:\r
+ B loop4\r
+ END\r
projects / freertos / blobdiff