+++ /dev/null
-/* ----------------------------------------------------------------------------\r
- * SAM Software Package License\r
- * ----------------------------------------------------------------------------\r
- * Copyright (c) 2012, Atmel Corporation\r
- *\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the disclaimer below.\r
- *\r
- * Atmel's name may not be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * ----------------------------------------------------------------------------\r
- */\r
-\r
-\r
-//------------------------------------------------------------------------------\r
-// Definitions\r
-//------------------------------------------------------------------------------\r
-\r
-\r
-#define AIC 0xFFFFF000\r
-#define AIC_IVR 0x10\r
-#define AIC_EOICR 0x38\r
-\r
-#define IRQ_STACK_SIZE 8*3*4\r
-\r
-#define ARM_MODE_ABT 0x17\r
-#define ARM_MODE_FIQ 0x11\r
-#define ARM_MODE_IRQ 0x12\r
-#define ARM_MODE_SVC 0x13\r
-#define ARM_MODE_SYS 0x1F\r
-\r
-#define I_BIT 0x80\r
-#define F_BIT 0x40\r
-\r
-//------------------------------------------------------------------------------\r
-// Startup routine\r
-//------------------------------------------------------------------------------\r
-\r
- .align 4\r
- .arm\r
- \r
-/* Exception vectors\r
- *******************/\r
- .section .vectors, "a", %progbits\r
-\r
-resetVector:\r
- ldr pc, =resetHandler /* Reset */\r
-undefVector:\r
- b undefVector /* Undefined instruction */\r
-swiVector:\r
- b swiVector /* Software interrupt */\r
-prefetchAbortVector:\r
- b prefetchAbortVector /* Prefetch abort */\r
-dataAbortVector:\r
- b dataAbortVector /* Data abort */\r
-reservedVector:\r
- b reservedVector /* Reserved for future use */\r
-irqVector:\r
- b irqHandler /* Interrupt */\r
-fiqVector:\r
- /* Fast interrupt */\r
-//------------------------------------------------------------------------------\r
-/// Handles a fast interrupt request by branching to the address defined in the\r
-/// AIC.\r
-//------------------------------------------------------------------------------\r
-fiqHandler:\r
- b fiqHandler\r
-\r
-//------------------------------------------------------------------------------\r
-/// Handles incoming interrupt requests by branching to the corresponding\r
-/// handler, as defined in the AIC. Supports interrupt nesting.\r
-//------------------------------------------------------------------------------\r
-irqHandler:\r
- /* Save interrupt context on the stack to allow nesting */\r
- SUB lr, lr, #4\r
- STMFD sp!, {lr}\r
- MRS lr, SPSR\r
- STMFD sp!, {r0, lr}\r
-\r
- /* Write in the IVR to support Protect Mode */\r
- LDR lr, =AIC\r
- LDR r0, [r14, #AIC_IVR]\r
- STR lr, [r14, #AIC_IVR]\r
-\r
- /* Branch to interrupt handler in Supervisor mode */\r
- MSR CPSR_c, #ARM_MODE_SVC\r
- STMFD sp!, {r1-r3, r4, r12, lr}\r
-\r
- /* Check for 8-byte alignment and save lr plus a */\r
- /* word to indicate the stack adjustment used (0 or 4) */\r
- AND r1, sp, #4\r
- SUB sp, sp, r1\r
- STMFD sp!, {r1, lr}\r
-\r
- BLX r0\r
-\r
- LDMIA sp!, {r1, lr}\r
- ADD sp, sp, r1\r
-\r
- LDMIA sp!, {r1-r3, r4, r12, lr}\r
- MSR CPSR_c, #ARM_MODE_IRQ | I_BIT\r
-\r
- /* Acknowledge interrupt */\r
- LDR lr, =AIC\r
- STR lr, [r14, #AIC_EOICR]\r
-\r
- /* Restore interrupt context and branch back to calling code */\r
- LDMIA sp!, {r0, lr}\r
- MSR SPSR_cxsf, lr\r
- LDMIA sp!, {pc}^\r
-\r
-\r
-//------------------------------------------------------------------------------\r
-/// Initializes the chip and branches to the main() function.\r
-//------------------------------------------------------------------------------\r
- .section .textEntry\r
- .global entry\r
-\r
-entry:\r
-resetHandler:\r
- \r
- CPSIE A \r
-\r
-/* Enable VFP */\r
- /* - Enable access to CP10 and CP11 in CP15.CACR */\r
- mrc p15, 0, r0, c1, c0, 2\r
- orr r0, r0, #0xf00000\r
- mcr p15, 0, r0, c1, c0, 2\r
-/* - Enable access to CP10 and CP11 in CP15.NSACR */\r
-/* - Set FPEXC.EN (B30) */\r
- fmrx r0, fpexc\r
- orr r0, r0, #0x40000000\r
- fmxr fpexc, r0\r
-\r
-/* Useless instruction for referencing the .vectors section */\r
- ldr r0, =resetVector\r
-\r
-/* Set pc to actual code location (i.e. not in remap zone) */\r
- ldr pc, =1f\r
-\r
-/* Initialize the prerelocate segment */\r
-1:\r
- ldr r0, =_efixed\r
- ldr r1, =_sprerelocate\r
- ldr r2, =_eprerelocate\r
-1:\r
- cmp r1, r2\r
- ldrcc r3, [r0], #4\r
- strcc r3, [r1], #4\r
- bcc 1b\r
-\r
-/* Perform low-level initialization of the chip using LowLevelInit() */\r
- ldr sp, =_sstack\r
- stmfd sp!, {r0}\r
- ldr r0, =LowLevelInit\r
- blx r0\r
-\r
-/* Initialize the postrelocate segment */\r
-\r
- ldmfd sp!, {r0}\r
- ldr r1, =_spostrelocate\r
- ldr r2, =_epostrelocate\r
-1:\r
- cmp r1, r2\r
- ldrcc r3, [r0], #4\r
- strcc r3, [r1], #4\r
- bcc 1b\r
-\r
-/* Clear the zero segment */\r
- ldr r0, =_szero\r
- ldr r1, =_ezero\r
- mov r2, #0\r
-1:\r
- cmp r0, r1\r
- strcc r2, [r0], #4\r
- bcc 1b\r
-\r
-/* Setup stacks\r
- **************/\r
-/* IRQ mode */\r
- msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT\r
- ldr sp, =_sstack\r
- sub r4, sp, #IRQ_STACK_SIZE\r
-\r
-/* Supervisor mode (interrupts enabled) */\r
- msr CPSR_c, #ARM_MODE_SVC | F_BIT\r
- mov sp, r4\r
-\r
-/*Initialize the C library */\r
- ldr r3, =__libc_init_array\r
- mov lr, pc\r
- bx r3\r
-\r
-/* Branch to main()\r
- ******************/\r
- ldr r0, =main\r
- blx r0\r
-\r
-/* Loop indefinitely when program is finished */\r
-1:\r
- b 1b\r
-\r
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