+++ /dev/null
-/* ----------------------------------------------------------------------------\r
- * SAM Software Package License\r
- * ----------------------------------------------------------------------------\r
- * Copyright (c) 2012, Atmel Corporation\r
- *\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the disclaimer below.\r
- *\r
- * Atmel's name may not be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * ----------------------------------------------------------------------------\r
- */\r
-\r
-\r
-//------------------------------------------------------------------------------\r
-// Definitions\r
-//------------------------------------------------------------------------------\r
-\r
-\r
-#define AIC 0xFFFFF000\r
-#define AIC_IVR 0x10\r
-#define AIC_EOICR 0x38\r
-\r
-#define IRQ_STACK_SIZE 8*3*4\r
-\r
-#define ARM_MODE_ABT 0x17\r
-#define ARM_MODE_FIQ 0x11\r
-#define ARM_MODE_IRQ 0x12\r
-#define ARM_MODE_SVC 0x13\r
-#define ARM_MODE_SYS 0x1F\r
-\r
-#define I_BIT 0x80\r
-#define F_BIT 0x40\r
-\r
-//------------------------------------------------------------------------------\r
-// Startup routine\r
-//------------------------------------------------------------------------------\r
-\r
- .align 4\r
- .arm\r
- \r
-/* Exception vectors\r
- *******************/\r
- .section .vectors, "a", %progbits\r
-\r
-resetVector:\r
- ldr pc, =resetHandler /* Reset */\r
-undefVector:\r
- b undefVector /* Undefined instruction */\r
-swiVector:\r
- b swiVector /* Software interrupt */\r
-prefetchAbortVector:\r
- b prefetchAbortVector /* Prefetch abort */\r
-dataAbortVector:\r
- b dataAbortVector /* Data abort */\r
-reservedVector:\r
- b reservedVector /* Reserved for future use */\r
-irqVector:\r
- b irqHandler /* Interrupt */\r
-fiqVector:\r
- /* Fast interrupt */\r
-//------------------------------------------------------------------------------\r
-/// Handles a fast interrupt request by branching to the address defined in the\r
-/// AIC.\r
-//------------------------------------------------------------------------------\r
-fiqHandler:\r
- b fiqHandler\r
-\r
-//------------------------------------------------------------------------------\r
-/// Handles incoming interrupt requests by branching to the corresponding\r
-/// handler, as defined in the AIC. Supports interrupt nesting.\r
-//------------------------------------------------------------------------------\r
-irqHandler:\r
- /* Save interrupt context on the stack to allow nesting */\r
- SUB lr, lr, #4\r
- STMFD sp!, {lr}\r
- MRS lr, SPSR\r
- STMFD sp!, {r0, lr}\r
-\r
- /* Write in the IVR to support Protect Mode */\r
- LDR lr, =AIC\r
- LDR r0, [r14, #AIC_IVR]\r
- STR lr, [r14, #AIC_IVR]\r
-\r
- /* Branch to interrupt handler in Supervisor mode */\r
- MSR CPSR_c, #ARM_MODE_SVC\r
- STMFD sp!, {r1-r3, r4, r12, lr}\r
-\r
- /* Check for 8-byte alignment and save lr plus a */\r
- /* word to indicate the stack adjustment used (0 or 4) */\r
- AND r1, sp, #4\r
- SUB sp, sp, r1\r
- STMFD sp!, {r1, lr}\r
-\r
- BLX r0\r
-\r
- LDMIA sp!, {r1, lr}\r
- ADD sp, sp, r1\r
-\r
- LDMIA sp!, {r1-r3, r4, r12, lr}\r
- MSR CPSR_c, #ARM_MODE_IRQ | I_BIT\r
-\r
- /* Acknowledge interrupt */\r
- LDR lr, =AIC\r
- STR lr, [r14, #AIC_EOICR]\r
-\r
- /* Restore interrupt context and branch back to calling code */\r
- LDMIA sp!, {r0, lr}\r
- MSR SPSR_cxsf, lr\r
- LDMIA sp!, {pc}^\r
-\r
-\r
-//------------------------------------------------------------------------------\r
-/// Initializes the chip and branches to the main() function.\r
-//------------------------------------------------------------------------------\r
- .section .textEntry\r
- .global entry\r
-\r
-entry:\r
-resetHandler:\r
- \r
- CPSIE A \r
-\r
-/* Enable VFP */\r
- /* - Enable access to CP10 and CP11 in CP15.CACR */\r
- mrc p15, 0, r0, c1, c0, 2\r
- orr r0, r0, #0xf00000\r
- mcr p15, 0, r0, c1, c0, 2\r
-/* - Enable access to CP10 and CP11 in CP15.NSACR */\r
-/* - Set FPEXC.EN (B30) */\r
- fmrx r0, fpexc\r
- orr r0, r0, #0x40000000\r
- fmxr fpexc, r0\r
-\r
-/* Useless instruction for referencing the .vectors section */\r
- ldr r0, =resetVector\r
-\r
-/* Set pc to actual code location (i.e. not in remap zone) */\r
- ldr pc, =1f\r
-\r
-/* Initialize the prerelocate segment */\r
-1:\r
- ldr r0, =_efixed\r
- ldr r1, =_sprerelocate\r
- ldr r2, =_eprerelocate\r
-1:\r
- cmp r1, r2\r
- ldrcc r3, [r0], #4\r
- strcc r3, [r1], #4\r
- bcc 1b\r
-\r
-/* Perform low-level initialization of the chip using LowLevelInit() */\r
- ldr sp, =_sstack\r
- stmfd sp!, {r0}\r
- ldr r0, =LowLevelInit\r
- blx r0\r
-\r
-/* Initialize the postrelocate segment */\r
-\r
- ldmfd sp!, {r0}\r
- ldr r1, =_spostrelocate\r
- ldr r2, =_epostrelocate\r
-1:\r
- cmp r1, r2\r
- ldrcc r3, [r0], #4\r
- strcc r3, [r1], #4\r
- bcc 1b\r
-\r
-/* Clear the zero segment */\r
- ldr r0, =_szero\r
- ldr r1, =_ezero\r
- mov r2, #0\r
-1:\r
- cmp r0, r1\r
- strcc r2, [r0], #4\r
- bcc 1b\r
-\r
-/* Setup stacks\r
- **************/\r
-/* IRQ mode */\r
- msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT\r
- ldr sp, =_sstack\r
- sub r4, sp, #IRQ_STACK_SIZE\r
-\r
-/* Supervisor mode (interrupts enabled) */\r
- msr CPSR_c, #ARM_MODE_SVC | F_BIT\r
- mov sp, r4\r
-\r
-/*Initialize the C library */\r
- ldr r3, =__libc_init_array\r
- mov lr, pc\r
- bx r3\r
-\r
-/* Branch to main()\r
- ******************/\r
- ldr r0, =main\r
- blx r0\r
-\r
-/* Loop indefinitely when program is finished */\r
-1:\r
- b 1b\r
-\r
+++ /dev/null
-/* ----------------------------------------------------------------------------\r
- * SAM Software Package License\r
- * ----------------------------------------------------------------------------\r
- * Copyright (c) 2011, Atmel Corporation\r
- *\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are met:\r
- *\r
- * - Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the disclaimer below.\r
- *\r
- * Atmel's name may not be used to endorse or promote products derived from\r
- * this software without specific prior written permission.\r
- *\r
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- * ----------------------------------------------------------------------------\r
- */\r
-\r
-/*\r
- IAR startup file for AT91SAMA5D3X microcontrollers.\r
- */\r
-\r
- MODULE ?cstartup\r
-\r
- ;; Forward declaration of sections.\r
- SECTION IRQ_STACK:DATA:NOROOT(2)\r
- SECTION CSTACK:DATA:NOROOT(3)\r
-\r
-//------------------------------------------------------------------------------\r
-// Headers\r
-//------------------------------------------------------------------------------\r
-\r
-//#define __ASSEMBLY__\r
-//#include "board.h"\r
-\r
-//------------------------------------------------------------------------------\r
-// Definitions\r
-//------------------------------------------------------------------------------\r
-\r
-#define AIC 0xFFFFF000\r
-#define AIC_IVR 0x10\r
-#define AIC_EOICR 0x38\r
-\r
-#define ARM_MODE_ABT 0x17\r
-#define ARM_MODE_FIQ 0x11\r
-#define ARM_MODE_IRQ 0x12\r
-#define ARM_MODE_SVC 0x13\r
-#define ARM_MODE_SYS 0x1F\r
-\r
-#define I_BIT 0x80\r
-#define F_BIT 0x40\r
-\r
-//------------------------------------------------------------------------------\r
-// Startup routine\r
-//------------------------------------------------------------------------------\r
-\r
-/*\r
- Exception vectors\r
- */\r
- SECTION .vectors:CODE:NOROOT(2)\r
-\r
- PUBLIC resetVector\r
- PUBLIC irqHandler\r
-\r
- EXTERN Undefined_Handler\r
- EXTERN SWI_Handler\r
- EXTERN Prefetch_Handler\r
- EXTERN Abort_Handler\r
- EXTERN FIQ_Handler\r
-\r
- ARM\r
-\r
-__iar_init$$done: ; The interrupt vector is not needed\r
- ; until after copy initialization is done\r
-\r
-resetVector:\r
- ; All default exception handlers (except reset) are\r
- ; defined as weak symbol definitions.\r
- ; If a handler is defined by the application it will take precedence.\r
- LDR pc, =resetHandler ; Reset\r
- LDR pc, Undefined_Addr ; Undefined instructions\r
- LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)\r
- LDR pc, Prefetch_Addr ; Prefetch abort\r
- LDR pc, Abort_Addr ; Data abort\r
- B . ; RESERVED\r
- LDR pc, =irqHandler ; IRQ\r
- LDR pc, FIQ_Addr ; FIQ\r
-\r
-Undefined_Addr: DCD Undefined_Handler\r
-SWI_Addr: DCD SWI_Handler\r
-Prefetch_Addr: DCD Prefetch_Handler\r
-Abort_Addr: DCD Abort_Handler\r
-FIQ_Addr: DCD FIQ_Handler\r
-\r
-/*\r
- Handles incoming interrupt requests by branching to the corresponding\r
- handler, as defined in the AIC. Supports interrupt nesting.\r
- */\r
-irqHandler:\r
- /* Save interrupt context on the stack to allow nesting */\r
- SUB lr, lr, #4\r
- STMFD sp!, {lr}\r
- MRS lr, SPSR\r
- STMFD sp!, {r0, lr}\r
-\r
- /* Write in the IVR to support Protect Mode */\r
- LDR lr, =AIC\r
- LDR r0, [r14, #AIC_IVR]\r
- STR lr, [r14, #AIC_IVR]\r
-\r
- /* Branch to interrupt handler in Supervisor mode */\r
- MSR CPSR_c, #ARM_MODE_SYS\r
- STMFD sp!, {r1-r3, r4, r12, lr}\r
-\r
- /* Check for 8-byte alignment and save lr plus a */\r
- /* word to indicate the stack adjustment used (0 or 4) */\r
- AND r1, sp, #4\r
- SUB sp, sp, r1\r
- STMFD sp!, {r1, lr}\r
-\r
- BLX r0\r
-\r
- LDMIA sp!, {r1, lr}\r
- ADD sp, sp, r1\r
-\r
- LDMIA sp!, {r1-r3, r4, r12, lr}\r
- MSR CPSR_c, #ARM_MODE_IRQ | I_BIT\r
-\r
- /* Acknowledge interrupt */\r
- LDR lr, =AIC\r
- STR lr, [r14, #AIC_EOICR]\r
-\r
- /* Restore interrupt context and branch back to calling code */\r
- LDMIA sp!, {r0, lr}\r
- MSR SPSR_cxsf, lr\r
- LDMIA sp!, {pc}^\r
-\r
-\r
-/*\r
- After a reset, execution starts here, the mode is ARM, supervisor\r
- with interrupts disabled.\r
- Initializes the chip and branches to the main() function.\r
- */\r
- SECTION .cstartup:CODE:NOROOT(2)\r
-\r
- PUBLIC resetHandler\r
- EXTERN LowLevelInit\r
- EXTERN ?main\r
- REQUIRE resetVector\r
- ARM\r
-\r
-resetHandler:\r
- CPSIE A\r
- /* Enable VFP */\r
- /* - Enable access to CP10 and CP11 in CP15.CACR */\r
- mrc p15, 0, r0, c1, c0, 2\r
- orr r0, r0, #0xf00000\r
- mcr p15, 0, r0, c1, c0, 2\r
- /* - Enable access to CP10 and CP11 in CP15.NSACR */\r
- /* - Set FPEXC.EN (B30) */\r
- fmrx r0, fpexc\r
- orr r0, r0, #0x40000000\r
- fmxr fpexc, r0\r
- /* Set pc to actual code location (i.e. not in remap zone) */\r
- LDR pc, =label\r
-\r
- /* Perform low-level initialization of the chip using LowLevelInit() */\r
-label:\r
- LDR r0, =LowLevelInit\r
- LDR r4, =SFE(CSTACK)\r
- MOV sp, r4\r
- BLX r0\r
-\r
- /* Set up the interrupt stack pointer. */\r
- MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode\r
- LDR sp, =SFE(IRQ_STACK)\r
-\r
- /* Set up the SYS stack pointer. */\r
- MSR cpsr_c, #ARM_MODE_SYS | F_BIT ; Change the mode\r
- LDR sp, =SFE(CSTACK)\r
-\r
- /* Branch to main() */\r
- LDR r0, =?main\r
- BLX r0\r
-\r
- /* Loop indefinitely when program is finished */\r
-loop4:\r
- B loop4\r
- END\r
* See http://www.freertos.org/a00110.html.\r
*----------------------------------------------------------*/\r
\r
-/*\r
- * The FreeRTOS Cortex-A port implements a full interrupt nesting model.\r
- *\r
- * Interrupts that are assigned a priority at or below\r
- * configMAX_API_CALL_INTERRUPT_PRIORITY (which counter-intuitively in the ARM\r
- * generic interrupt controller [GIC] means a priority that has a numerical\r
- * value above configMAX_API_CALL_INTERRUPT_PRIORITY) can call FreeRTOS safe API\r
- * functions and will nest.\r
- *\r
- * Interrupts that are assigned a priority above\r
- * configMAX_API_CALL_INTERRUPT_PRIORITY (which in the GIC means a numerical\r
- * value below configMAX_API_CALL_INTERRUPT_PRIORITY) cannot call any FreeRTOS\r
- * API functions, will nest, and will not be masked by FreeRTOS critical\r
- * sections (although it is necessary for interrupts to be globally disabled\r
- * extremely briefly as the interrupt mask is updated in the GIC).\r
- *\r
- * FreeRTOS functions that can be called from an interrupt are those that end in\r
- * "FromISR". FreeRTOS maintains a separate interrupt safe API to enable\r
- * interrupt entry to be shorter, faster, simpler and smaller.\r
- */\r
-#define configMAX_API_CALL_INTERRUPT_PRIORITY 25\r
-\r
-\r
#define configCPU_CLOCK_HZ 100000000UL\r
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
#define configUSE_TICKLESS_IDLE 0\r
void vInitialiseRunTimeStats( void );\r
\r
#define configGENERATE_RUN_TIME_STATS 0\r
-// #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vInitialiseRunTimeStats()\r
-// #define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()\r
+//_RB_ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vInitialiseRunTimeStats()\r
+//_RB_ #define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()\r
\r
/* The size of the global output buffer that is available for use when there\r
are multiple command interpreters running at once (for example, one on a UART\r
*/\r
void vConfigureTickInterrupt( void );\r
#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()\r
+ \r
+ #define configPIT_PIVR ( *( ( volatile uint32_t * ) 0xFFFFFE38UL ) )\r
+ #define configCLEAR_TICK_INTERRUPT() ( void ) configPIT_PIVR /* Read PIT_PIVR to clear interrupt. */\r
#endif /* __IASMARM__ */\r
\r
-/* The following constants describe the hardware, and are correct for the\r
-Atmel SAMA5 MPU. */\r
-#define configINTERRUPT_CONTROLLER_BASE_ADDRESS 0xE8201000\r
-#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET 0x1000\r
-#define configUNIQUE_INTERRUPT_PRIORITIES 32\r
-\r
-/* Map the FreeRTOS IRQ and SVC/SWI handlers to the names used in the C startup\r
-code (which is where the vector table is defined). */\r
-#define FreeRTOS_IRQ_Handler IRQ_Handler\r
-#define FreeRTOS_SWI_Handler SWI_Handler\r
-\r
#endif /* FREERTOS_CONFIG_H */\r
\r
#include "FreeRTOS.h"\r
#include "Task.h"\r
\r
+/* Library includes. */\r
+#include "board.h"\r
+\r
/*\r
* The application must provide a function that configures a peripheral to\r
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()\r
*/\r
void vConfigureTickInterrupt( void )\r
{\r
-#warning Needs implementing.\r
-}\r
-/*-----------------------------------------------------------*/\r
-void vApplicationIRQHandler( uint32_t ulICCIAR );\r
-void vApplicationIRQHandler( uint32_t ulICCIAR )\r
-{\r
-uint32_t ulInterruptID;\r
+extern void FreeRTOS_Tick_Handler( void );\r
\r
- /* Re-enable interrupts. */\r
- __asm ( "cpsie i" );\r
+ /* NOTE: The PIT interrupt is cleared by the configCLEAR_TICK_INTERRUPT()\r
+ macro in FreeRTOSConfig.h. */\r
\r
- /* The ID of the interrupt is obtained by bitwise anding the ICCIAR value\r
- with 0x3FF. */\r
- ulInterruptID = ulICCIAR & 0x3FFUL;\r
+ /* Enable the PIT clock. */\r
+ PMC->PMC_PCER0 = 1 << ID_PIT;\r
\r
-#warning Needs implementing.\r
+ /* Initialize the PIT to the desired frequency - specified in uS. */\r
+ PIT_Init( 1000000UL / configTICK_RATE_HZ, BOARD_MCK / 1000000 );\r
+ \r
+ /* Configure interrupt on PIT */\r
+#warning This is on the system interrupt and other interrupts may need processing to.\r
+ IRQ_ConfigureIT( ID_PIT, 0, FreeRTOS_Tick_Handler );\r
+ IRQ_EnableIT( ID_PIT );\r
+ PIT_EnableIT();\r
+ \r
+ /* Enable the pit. */\r
+ PIT_Enable();\r
}\r
+/*-----------------------------------------------------------*/\r
\r
\r
\r
/* Demo includes. */\r
#include "partest.h"\r
\r
+/* Library includes. */\r
+#include "board.h"\r
+\r
/*-----------------------------------------------------------*/\r
\r
void vParTestInitialise( void )\r
{\r
+ LED_Configure( 0 );\r
+ LED_Configure( 1 );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vParTestSetLED( UBaseType_t uxLED, BaseType_t xValue )\r
{\r
+ if( xValue == pdTRUE )\r
+ {\r
+ LED_Set( uxLED );\r
+ }\r
+ else\r
+ {\r
+ LED_Clear( uxLED );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
{\r
+ LED_Toggle( uxLED );\r
}\r
\r
\r
</option>\r
<option>\r
<name>MemFile</name>\r
- <state>$TOOLKIT_DIR$\CONFIG\debugger\Atmel\ATSAMA5D35.ddf</state>\r
+ <state></state>\r
</option>\r
<option>\r
<name>RunToEnable</name>\r
<option>\r
<name>CCJLinkResetList</name>\r
<version>6</version>\r
- <state>5</state>\r
+ <state>0</state>\r
</option>\r
<option>\r
<name>CCJLinkInterfaceCmdLine</name>\r
</option>\r
<option>\r
<name>OGCoreOrChip</name>\r
- <state>1</state>\r
+ <state>0</state>\r
</option>\r
<option>\r
<name>GRuntimeLibSelect</name>\r
<state>$PROJ_DIR$/AtmelFiles/libchip_sama5d3x/include</state>\r
<state>$PROJ_DIR$/.</state>\r
<state>$PROJ_DIR$\..\..\Source\include</state>\r
- <state>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA9</state>\r
+ <state>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA5_No_GIC</state>\r
<state>$PROJ_DIR$\..\Common\include</state>\r
</option>\r
<option>\r
<name>Atmel Files</name>\r
<group>\r
<name>libboard_sama5d3x-ek</name>\r
- <file>\r
- <name>$PROJ_DIR$\AtmelFiles\libboard_sama5d3x-ek\source\board_cstartup_iar.s</name>\r
- </file>\r
<file>\r
<name>$PROJ_DIR$\AtmelFiles\libboard_sama5d3x-ek\source\board_lowlevel.c</name>\r
</file>\r
</file>\r
</group>\r
</group>\r
+ <group>\r
+ <name>Blinky Demo</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\blinky_demo\main_blinky.c</name>\r
+ </file>\r
+ </group>\r
<group>\r
<name>FreeRTOS Source</name>\r
<group>\r
</file>\r
</group>\r
<file>\r
- <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA9\port.c</name>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA5_No_GIC\port.c</name>\r
</file>\r
<file>\r
- <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA9\portASM.s</name>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA5_No_GIC\portASM.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA5_No_GIC\portASM.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA5_No_GIC\portmacro.h</name>\r
</file>\r
</group>\r
<file>\r
<file>\r
<name>$PROJ_DIR$\atmel_main.c</name>\r
</file>\r
+ <file>\r
+ <name>$PROJ_DIR$\cstartup_with_FreeRTOS_vectors.s</name>\r
+ </file>\r
<file>\r
<name>$PROJ_DIR$\FreeRTOS_tick_config.c</name>\r
</file>\r
<file>\r
<name>$PROJ_DIR$\main.c</name>\r
</file>\r
- <file>\r
- <name>$PROJ_DIR$\main_blinky.c</name>\r
- </file>\r
</project>\r
\r
\r
/**\r
* \brief Handler for Sysc interrupts.\r
*/\r
-static void _Sysc_Handler( void )\r
+void _Sysc_Handler( void );\r
+void _Sysc_Handler( void )\r
{\r
_Pit_Handler( ) ;\r
#ifdef NO_PUSHBUTTON\r
--- /dev/null
+/*\r
+ FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds...and so on.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles an LED. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes. */\r
+#include "partest.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* The LED toggled by the Rx task. */\r
+#define mainTASK_LED ( 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in\r
+ * main.c.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static QueueHandle_t xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ NULL, /* The parameter passed to the task - not used in this case. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+TickType_t xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+const unsigned long ulExpectedValue = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == ulExpectedValue )\r
+ {\r
+ vParTestToggleLED( mainTASK_LED );\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+ IAR startup file for AT91SAMA5D3X microcontrollers.\r
+ */\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION IRQ_STACK:DATA:NOROOT(2)\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+//#define __ASSEMBLY__\r
+//#include "board.h"\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+//_RB_ These definitions can go.\r
+#define AIC 0xFFFFF000\r
+#define AIC_IVR 0x10\r
+#define AIC_EOICR 0x38\r
+\r
+#define ARM_MODE_ABT 0x17\r
+#define ARM_MODE_FIQ 0x11\r
+#define ARM_MODE_IRQ 0x12\r
+#define ARM_MODE_SVC 0x13\r
+#define ARM_MODE_SYS 0x1F\r
+\r
+#define I_BIT 0x80\r
+#define F_BIT 0x40\r
+\r
+//------------------------------------------------------------------------------\r
+// Startup routine\r
+//------------------------------------------------------------------------------\r
+\r
+/*\r
+ Exception vectors\r
+ */\r
+ SECTION .vectors:CODE:NOROOT(2)\r
+\r
+ PUBLIC resetVector\r
+\r
+ EXTERN FreeRTOS_IRQ_Handler\r
+ EXTERN Undefined_Handler\r
+ EXTERN FreeRTOS_SWI_Handler\r
+ EXTERN Prefetch_Handler\r
+ EXTERN Abort_Handler\r
+ EXTERN FIQ_Handler\r
+\r
+ ARM\r
+\r
+__iar_init$$done: ; The interrupt vector is not needed\r
+ ; until after copy initialization is done\r
+\r
+resetVector:\r
+ ; All default exception handlers (except reset) are\r
+ ; defined as weak symbol definitions.\r
+ ; If a handler is defined by the application it will take precedence.\r
+ LDR pc, =resetHandler ; Reset\r
+ LDR pc, Undefined_Addr ; Undefined instructions\r
+ LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)\r
+ LDR pc, Prefetch_Addr ; Prefetch abort\r
+ LDR pc, Abort_Addr ; Data abort\r
+ B . ; RESERVED\r
+ LDR pc, IRQ_Addr ; IRQ\r
+ LDR pc, FIQ_Addr ; FIQ\r
+\r
+IRQ_Addr: DCD FreeRTOS_IRQ_Handler\r
+Undefined_Addr: DCD Undefined_Handler\r
+SWI_Addr: DCD FreeRTOS_SWI_Handler\r
+Prefetch_Addr: DCD Prefetch_Handler\r
+Abort_Addr: DCD Abort_Handler\r
+FIQ_Addr: DCD FIQ_Handler\r
+\r
+\r
+/*\r
+ After a reset, execution starts here, the mode is ARM, supervisor\r
+ with interrupts disabled.\r
+ Initializes the chip and branches to the main() function.\r
+ */\r
+ SECTION .cstartup:CODE:NOROOT(2)\r
+\r
+ PUBLIC resetHandler\r
+ EXTERN LowLevelInit\r
+ EXTERN ?main\r
+ REQUIRE resetVector\r
+ ARM\r
+\r
+resetHandler:\r
+ CPSIE A\r
+ /* Enable VFP */\r
+ /* - Enable access to CP10 and CP11 in CP15.CACR */\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ orr r0, r0, #0xf00000\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ /* - Enable access to CP10 and CP11 in CP15.NSACR */\r
+ /* - Set FPEXC.EN (B30) */\r
+ fmrx r0, fpexc\r
+ orr r0, r0, #0x40000000\r
+ fmxr fpexc, r0\r
+ /* Set pc to actual code location (i.e. not in remap zone) */\r
+ LDR pc, =label\r
+\r
+ /* Perform low-level initialization of the chip using LowLevelInit() */\r
+label:\r
+ LDR r0, =LowLevelInit\r
+ LDR r4, =SFE(CSTACK)\r
+ MOV sp, r4\r
+ BLX r0\r
+\r
+ /* Set up the interrupt stack pointer. */\r
+ MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode\r
+ LDR sp, =SFE(IRQ_STACK)\r
+\r
+ /* Set up the SYS stack pointer. */\r
+ MSR cpsr_c, #ARM_MODE_SYS | F_BIT ; Change the mode\r
+ LDR sp, =SFE(CSTACK)\r
+\r
+ /* Branch to main() */\r
+ LDR r0, =?main\r
+ BLX r0\r
+\r
+ /* Loop indefinitely when program is finished */\r
+loop4:\r
+ B loop4\r
+ END\r
*\r
*/\r
\r
+#warning Remove unused libary files.\r
+\r
/* Scheduler include files. */\r
#include "FreeRTOS.h"\r
#include "task.h"\r
#include "TimerDemo.h"\r
#include "QueueOverwrite.h"\r
\r
+/* Library includes. */\r
+#include "chip.h"\r
+\r
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
or 0 to run the more comprehensive test and demo application. */\r
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1\r
\r
/*-----------------------------------------------------------*/\r
extern int atmel_main( void );\r
+extern void vConfigureTickInterrupt( void );\r
int main( void )\r
-{\r
- atmel_main();\r
- \r
+{ \r
/* Configure the hardware ready to run the demo. */\r
prvSetupHardware();\r
\r
\r
static void prvSetupHardware( void )\r
{\r
+ /* Set protect mode in the AIC for easier debugging. */\r
+ AIC->AIC_DCR != AIC_DCR_PROT;\r
+ \r
+ /* Configure ports used by LEDs. */\r
+ vParTestInitialise();\r
}\r
/*-----------------------------------------------------------*/\r
\r
+++ /dev/null
-/*\r
- FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * NOTE 1: This project provides three demo applications. A simple blinky\r
- * style project, a more comprehensive test and demo application, and an\r
- * lwIP example. The mainSELECTED_APPLICATION setting in main.c is used to\r
- * select between the three. See the notes on using mainSELECTED_APPLICATION\r
- * in main.c. This file implements the simply blinky style version.\r
- *\r
- * NOTE 2: This file only contains the source code that is specific to the\r
- * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
- * required to configure the hardware are defined in main.c.\r
- ******************************************************************************\r
- *\r
- * main_blinky() creates one queue, and two tasks. It then starts the\r
- * scheduler.\r
- *\r
- * The Queue Send Task:\r
- * The queue send task is implemented by the prvQueueSendTask() function in\r
- * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
- * block for 200 milliseconds, before sending the value 100 to the queue that\r
- * was created within main_blinky(). Once the value is sent, the task loops\r
- * back around to block for another 200 milliseconds...and so on.\r
- *\r
- * The Queue Receive Task:\r
- * The queue receive task is implemented by the prvQueueReceiveTask() function\r
- * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
- * blocks on attempts to read data from the queue that was created within\r
- * main_blinky(). When data is received, the task checks the value of the\r
- * data, and if the value equals the expected 100, toggles an LED. The 'block\r
- * time' parameter passed to the queue receive function specifies that the\r
- * task should be held in the Blocked state indefinitely to wait for data to\r
- * be available on the queue. The queue receive task will only leave the\r
- * Blocked state when the queue send task writes to the queue. As the queue\r
- * send task writes to the queue every 200 milliseconds, the queue receive\r
- * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
- * the LED every 200 milliseconds.\r
- */\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "semphr.h"\r
-\r
-/* Standard demo includes. */\r
-#include "partest.h"\r
-\r
-/* Priorities at which the tasks are created. */\r
-#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-\r
-/* The rate at which data is sent to the queue. The 200ms value is converted\r
-to ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
-\r
-/* The number of items the queue can hold. This is 1 as the receive task\r
-will remove items as they are added, meaning the send task should always find\r
-the queue empty. */\r
-#define mainQUEUE_LENGTH ( 1 )\r
-\r
-/* The LED toggled by the Rx task. */\r
-#define mainTASK_LED ( 0 )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* \r
- * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in\r
- * main.c.\r
- */\r
-void main_blinky( void );\r
- \r
-/*\r
- * The tasks as described in the comments at the top of this file.\r
- */\r
-static void prvQueueReceiveTask( void *pvParameters );\r
-static void prvQueueSendTask( void *pvParameters );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The queue used by both tasks. */\r
-static QueueHandle_t xQueue = NULL;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void main_blinky( void )\r
-{\r
- /* Create the queue. */\r
- xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
-\r
- if( xQueue != NULL )\r
- {\r
- /* Start the two tasks as described in the comments at the top of this\r
- file. */\r
- xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
- "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
- configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
- NULL, /* The parameter passed to the task - not used in this case. */\r
- mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
- NULL ); /* The task handle is not required, so NULL is passed. */\r
-\r
- xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
-\r
- /* Start the tasks and timer running. */\r
- vTaskStartScheduler();\r
- }\r
-\r
- /* If all is well, the scheduler will now be running, and the following\r
- line will never be reached. If the following line does execute, then\r
- there was either insufficient FreeRTOS heap memory available for the idle\r
- and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
- User mode. See the memory management section on the FreeRTOS web site for\r
- more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
- mode from which main() is called is set in the C start up code and must be\r
- a privileged mode (not user mode). */\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueSendTask( void *pvParameters )\r
-{\r
-TickType_t xNextWakeTime;\r
-const unsigned long ulValueToSend = 100UL;\r
-\r
- /* Remove compiler warning about unused parameter. */\r
- ( void ) pvParameters;\r
-\r
- /* Initialise xNextWakeTime - this only needs to be done once. */\r
- xNextWakeTime = xTaskGetTickCount();\r
-\r
- for( ;; )\r
- {\r
- /* Place this task in the blocked state until it is time to run again. */\r
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Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0\r
CStepIntDis=_ 0\r
[DebugChecksum]\r
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[Exceptions]\r
StopOnUncaught=_ 0\r
StopOnThrow=_ 0\r
ShowArgs=0\r
[Disassembly]\r
MixedMode=1\r
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LogFile=_ ""\r
mode=0\r
[Breakpoints2]\r
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<Windows>\r
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</Desktop>\r
</Workspace>\r
\r
[MainWindow]\r
-WindowPlacement=_ 66 66 1326 815 3\r
+WindowPlacement=_ 67 68 1327 817 3\r
projects / freertos / commitdiff