+++ /dev/null
-/*******************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-********************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-$File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/MEC1322.h $\r
-********************************************************************************\r
-$Revision: #1 $\r
-$DateTime: 2015/12/23 15:37:58 $\r
-$Author: akrishnan $\r
- Change Description: Initial revision for MEC1322\r
-******************************************************************************/\r
-/** @file smscmmcr.h\r
-* brief the mmcr definitions\r
-* \r
-******************************************************************************/\r
-#ifndef SMSCMMCR_H_\r
-#define SMSCMMCR_H_\r
-\r
-//NOTE: Please Don't edit this File, this is extrated from the Spread sheet \r
-// : //depotAE/projects/MEC1322/docs/MMCRs/MEC1322_FPGA1_Query_All_Addressing_ResultSet.csv\r
-typedef volatile unsigned char VUINT8;\r
-typedef volatile unsigned short int VUINT16;\r
-typedef volatile unsigned long int VUINT32;\r
-\r
-/***************************************************************\r
-* PWM\r
-***************************************************************/\r
-#define ADDR_PWM_0_COUNTER_ON_TIME 0x40005800\r
-#define MMCR_PWM_0_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_ON_TIME))\r
-\r
-#define ADDR_PWM_0_COUNTER_OFF_TIME 0x40005804\r
-#define MMCR_PWM_0_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_OFF_TIME))\r
-\r
-#define ADDR_PWM_0_CONFIGURATION 0x40005808\r
-#define MMCR_PWM_0_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_0_CONFIGURATION))\r
-\r
-#define ADDR_PWM_1_COUNTER_ON_TIME 0x40005810\r
-#define MMCR_PWM_1_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_ON_TIME))\r
-\r
-#define ADDR_PWM_1_COUNTER_OFF_TIME 0x40005814\r
-#define MMCR_PWM_1_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_OFF_TIME))\r
-\r
-#define ADDR_PWM_1_CONFIGURATION 0x40005818\r
-#define MMCR_PWM_1_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_1_CONFIGURATION))\r
-\r
-#define ADDR_PWM_2_COUNTER_ON_TIME 0x40005820\r
-#define MMCR_PWM_2_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_ON_TIME))\r
-\r
-#define ADDR_PWM_2_COUNTER_OFF_TIME 0x40005824\r
-#define MMCR_PWM_2_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_OFF_TIME))\r
-\r
-#define ADDR_PWM_2_CONFIGURATION 0x40005828\r
-#define MMCR_PWM_2_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_2_CONFIGURATION))\r
-\r
-#define ADDR_PWM_3_COUNTER_ON_TIME 0x40005830\r
-#define MMCR_PWM_3_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_ON_TIME))\r
-\r
-#define ADDR_PWM_3_COUNTER_OFF_TIME 0x40005834\r
-#define MMCR_PWM_3_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_OFF_TIME))\r
-\r
-#define ADDR_PWM_3_CONFIGURATION 0x40005838\r
-#define MMCR_PWM_3_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_3_CONFIGURATION))\r
-\r
-/***************************************************************\r
-* PECI\r
-***************************************************************/\r
-#define ADDR_PECI_WRITE_DATA 0x40006400\r
-#define MMCR_PECI_WRITE_DATA (*(VUINT32 *)(ADDR_PECI_WRITE_DATA))\r
-\r
-#define ADDR_PECI_READ_DATA 0x40006404\r
-#define MMCR_PECI_READ_DATA (*(VUINT32 *)(ADDR_PECI_READ_DATA))\r
-\r
-#define ADDR_PECI_CONTROL 0x40006408\r
-#define MMCR_PECI_CONTROL (*(VUINT32 *)(ADDR_PECI_CONTROL))\r
-\r
-#define ADDR_PECI_STATUS_1 0x4000640C\r
-#define MMCR_PECI_STATUS_1 (*(VUINT32 *)(ADDR_PECI_STATUS_1))\r
-\r
-#define ADDR_PECI_STATUS_2 0x40006410\r
-#define MMCR_PECI_STATUS_2 (*(VUINT32 *)(ADDR_PECI_STATUS_2))\r
-\r
-#define ADDR_PECI_ERROR 0x40006414\r
-#define MMCR_PECI_ERROR (*(VUINT32 *)(ADDR_PECI_ERROR))\r
-\r
-#define ADDR_PECI_INTERRUPT_ENABLE_1 0x40006418\r
-#define MMCR_PECI_INTERRUPT_ENABLE_1 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_1))\r
-\r
-#define ADDR_PECI_INTERRUPT_ENABLE_2 0x4000641C\r
-#define MMCR_PECI_INTERRUPT_ENABLE_2 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_2))\r
-\r
-#define ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE 0x40006420\r
-#define MMCR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE))\r
-\r
-#define ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE 0x40006424\r
-#define MMCR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE))\r
-\r
-#define ADDR_PECI_REQUEST_TIMER_LOW_BYTE 0x40006428\r
-#define MMCR_PECI_REQUEST_TIMER_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_LOW_BYTE))\r
-\r
-#define ADDR_PECI_REQUEST_TIMER_HIGH_BYTE 0x4000642C\r
-#define MMCR_PECI_REQUEST_TIMER_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_HIGH_BYTE))\r
-\r
-#define ADDR_PECI_BLOCK_ID 0x40006440\r
-#define MMCR_PECI_BLOCK_ID (*(VUINT32 *)(ADDR_PECI_BLOCK_ID))\r
-\r
-#define ADDR_PECI_BLOCK_REVISION 0x40006444\r
-#define MMCR_PECI_BLOCK_REVISION (*(VUINT32 *)(ADDR_PECI_BLOCK_REVISION))\r
-\r
-/***************************************************************\r
-* ACPI EC Interface \r
-***************************************************************/\r
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0 0x400F0D00\r
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1 0x400F0D01\r
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1))\r
-\r
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2 0x400F0D02\r
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2))\r
-\r
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3 0x400F0D03\r
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3))\r
-\r
-#define ADDR_ACPI_0_STATUS_EC 0x400F0D04\r
-#define MMCR_ACPI_0_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_0_STATUS_EC))\r
-\r
-#define ADDR_ACPI_0_BYTE_CONTROL_EC 0x400F0D05\r
-#define MMCR_ACPI_0_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_0_BYTE_CONTROL_EC))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1 0x400F0D09\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2 0x400F0D0A\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3 0x400F0D0B\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3))\r
-\r
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0 0x400F1100\r
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1 0x400F1101\r
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1))\r
-\r
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2 0x400F1102\r
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2))\r
-\r
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3 0x400F1103\r
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3))\r
-\r
-#define ADDR_ACPI_1_STATUS_EC 0x400F1104\r
-#define MMCR_ACPI_1_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_1_STATUS_EC))\r
-\r
-#define ADDR_ACPI_1_BYTE_CONTROL_EC 0x400F1105\r
-#define MMCR_ACPI_1_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_1_BYTE_CONTROL_EC))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1 0x400F1109\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2 0x400F110A\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3 0x400F110B\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3))\r
-\r
-/***************************************************************\r
-* Keyboard Matrix Scan Support\r
-***************************************************************/\r
-#define ADDR_KEYBOARD_KSO_SELECT 0x40009C04\r
-#define MMCR_KEYBOARD_KSO_SELECT (*(VUINT32 *)(ADDR_KEYBOARD_KSO_SELECT))\r
-\r
-#define ADDR_KEYBOARD_KSI_INPUT 0x40009C08\r
-#define MMCR_KEYBOARD_KSI_INPUT (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INPUT))\r
-\r
-#define ADDR_KEYBOARD_KSI_STATUS 0x40009C0C\r
-#define MMCR_KEYBOARD_KSI_STATUS (*(VUINT32 *)(ADDR_KEYBOARD_KSI_STATUS))\r
-\r
-#define ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE 0x40009C10\r
-#define MMCR_KEYBOARD_KSI_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL 0x40009C14\r
-#define MMCR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL (*(VUINT32 *)(ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL))\r
-\r
-/***************************************************************\r
-* PS/2 Device Interface\r
-***************************************************************/\r
-#define ADDR_PS2_3_STATUS 0x400090C8\r
-#define MMCR_PS2_3_STATUS (*(VUINT8 *)(ADDR_PS2_3_STATUS))\r
-\r
-#define ADDR_PS2_3_CONTROL 0x400090C4\r
-#define MMCR_PS2_3_CONTROL (*(VUINT8 *)(ADDR_PS2_3_CONTROL))\r
-\r
-#define ADDR_PS2_3_RECEIVE_BUFFER 0x400090C0\r
-#define MMCR_PS2_3_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_3_RECEIVE_BUFFER))\r
-\r
-#define ADDR_PS2_3_TRANSMIT_BUFFER 0x400090C0\r
-#define MMCR_PS2_3_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_3_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_PS2_0_TRANSMIT_BUFFER 0x40009000\r
-#define MMCR_PS2_0_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_0_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_PS2_0_RECEIVE_BUFFER 0x40009000\r
-#define MMCR_PS2_0_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_0_RECEIVE_BUFFER))\r
-\r
-#define ADDR_PS2_0_CONTROL 0x40009004\r
-#define MMCR_PS2_0_CONTROL (*(VUINT8 *)(ADDR_PS2_0_CONTROL))\r
-\r
-#define ADDR_PS2_0_STATUS 0x40009008\r
-#define MMCR_PS2_0_STATUS (*(VUINT8 *)(ADDR_PS2_0_STATUS))\r
-\r
-#define ADDR_PS2_1_TRANSMIT_BUFFER 0x40009040\r
-#define MMCR_PS2_1_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_1_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_PS2_1_RECEIVE_BUFFER 0x40009040\r
-#define MMCR_PS2_1_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_1_RECEIVE_BUFFER))\r
-\r
-#define ADDR_PS2_1_CONTROL 0x40009044\r
-#define MMCR_PS2_1_CONTROL (*(VUINT8 *)(ADDR_PS2_1_CONTROL))\r
-\r
-#define ADDR_PS2_1_STATUS 0x40009048\r
-#define MMCR_PS2_1_STATUS (*(VUINT8 *)(ADDR_PS2_1_STATUS))\r
-\r
-#define ADDR_PS2_2_RECEIVE_BUFFER 0x40009080\r
-#define MMCR_PS2_2_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_2_RECEIVE_BUFFER))\r
-\r
-#define ADDR_PS2_2_TRANSMIT_BUFFER 0x40009080\r
-#define MMCR_PS2_2_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_2_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_PS2_2_CONTROL 0x40009084\r
-#define MMCR_PS2_2_CONTROL (*(VUINT8 *)(ADDR_PS2_2_CONTROL))\r
-\r
-#define ADDR_PS2_2_STATUS 0x40009088\r
-#define MMCR_PS2_2_STATUS (*(VUINT8 *)(ADDR_PS2_2_STATUS))\r
-\r
-/***************************************************************\r
-* 8042 Host Interface\r
-***************************************************************/\r
-#define ADDR_8042_ACTIVATE 0x400F0730\r
-#define MMCR_8042_ACTIVATE (*(VUINT8 *)(ADDR_8042_ACTIVATE))\r
-\r
-#define ADDR_8042_HOST_EC_DATACMD 0x400F0500\r
-#define MMCR_8042_HOST_EC_DATACMD (*(VUINT8 *)(ADDR_8042_HOST_EC_DATACMD))\r
-\r
-#define ADDR_8042_EC_HOST_DATA 0x400F0500\r
-#define MMCR_8042_EC_HOST_DATA (*(VUINT8 *)(ADDR_8042_EC_HOST_DATA))\r
-\r
-#define ADDR_8042_KEYBOARD_STATUS_READ 0x400F0504\r
-#define MMCR_8042_KEYBOARD_STATUS_READ (*(VUINT8 *)(ADDR_8042_KEYBOARD_STATUS_READ))\r
-\r
-#define ADDR_8042_KEYBOARD_CONTROL 0x400F0508\r
-#define MMCR_8042_KEYBOARD_CONTROL (*(VUINT8 *)(ADDR_8042_KEYBOARD_CONTROL))\r
-\r
-#define ADDR_8042_EC_HOST_AUX 0x400F050C\r
-#define MMCR_8042_EC_HOST_AUX (*(VUINT8 *)(ADDR_8042_EC_HOST_AUX))\r
-\r
-#define ADDR_8042_PCOBF 0x400F0514\r
-#define MMCR_8042_PCOBF (*(VUINT8 *)(ADDR_8042_PCOBF))\r
-\r
-#define ADDR_8042_PORT92_ENABLE 0x400F1B30\r
-#define MMCR_8042_PORT92_ENABLE (*(VUINT8 *)(ADDR_8042_PORT92_ENABLE))\r
-\r
-#define ADDR_8042_GATEA20_CONTROL 0x400F1900\r
-#define MMCR_8042_GATEA20_CONTROL (*(VUINT8 *)(ADDR_8042_GATEA20_CONTROL))\r
-\r
-#define ADDR_8042_SETGA20L 0x400F1908\r
-#define MMCR_8042_SETGA20L (*(VUINT8 *)(ADDR_8042_SETGA20L))\r
-\r
-#define ADDR_8042_RSTGA20L 0x400F190C\r
-#define MMCR_8042_RSTGA20L (*(VUINT8 *)(ADDR_8042_RSTGA20L))\r
-\r
-/***************************************************************\r
-* SMBus\r
-***************************************************************/\r
-#define ADDR_SMB_3_DEBUG_FSM_SMB 0x4000B45C\r
-#define MMCR_SMB_3_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_SMB))\r
-\r
-#define ADDR_SMB_3_DEBUG_FSM_I2C 0x4000B458\r
-#define MMCR_SMB_3_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_I2C))\r
-\r
-#define ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER 0x4000B454\r
-#define MMCR_SMBUS_3_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER 0x4000B450\r
-#define MMCR_SMBUS_3_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER))\r
-\r
-#define ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER 0x4000B44C\r
-#define MMCR_SMBUS_3_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER 0x4000B448\r
-#define MMCR_SMBUS_3_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_SMB_3_TIME_OUT_SCALING 0x4000B444\r
-#define MMCR_SMB_3_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_3_TIME_OUT_SCALING))\r
-\r
-#define ADDR_SMB_3_DATA_TIMING 0x4000B440\r
-#define MMCR_SMB_3_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_3_DATA_TIMING))\r
-\r
-#define ADDR_SMB_3_CLOCK_SYNC 0x4000B43C\r
-#define MMCR_SMB_3_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_3_CLOCK_SYNC))\r
-\r
-#define ADDR_SMB_3_BIT_BANG_CONTROL 0x4000B438\r
-#define MMCR_SMB_3_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_3_BIT_BANG_CONTROL))\r
-\r
-#define ADDR_SMB_3_REVISION 0x4000B434\r
-#define MMCR_SMB_3_REVISION (*(VUINT8 *)(ADDR_SMB_3_REVISION))\r
-\r
-#define ADDR_SMB_3_BLOCK_ID 0x4000B430\r
-#define MMCR_SMB_3_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_3_BLOCK_ID))\r
-\r
-#define ADDR_SMB_3_BUS_CLOCK 0x4000B42C\r
-#define MMCR_SMB_3_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_3_BUS_CLOCK))\r
-\r
-#define ADDR_SMB_3_CONFIGURATION 0x4000B428\r
-#define MMCR_SMB_3_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_3_CONFIGURATION))\r
-\r
-#define ADDR_SMB_3_IDLE_SCALING 0x4000B424\r
-#define MMCR_SMB_3_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_3_IDLE_SCALING))\r
-\r
-#define ADDR_SMB_3_COMPLETION 0x4000B420\r
-#define MMCR_SMB_3_COMPLETION (*(VUINT32 *)(ADDR_SMB_3_COMPLETION))\r
-\r
-#define ADDR_SMB_3_DATA_TIMING2 0x4000B418\r
-#define MMCR_SMB_3_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_3_DATA_TIMING2))\r
-\r
-#define ADDR_SMB_3_PEC 0x4000B414\r
-#define MMCR_SMB_3_PEC (*(VUINT8 *)(ADDR_SMB_3_PEC))\r
-\r
-#define ADDR_SMBUS_3_SLAVE_COMMAND 0x4000B410\r
-#define MMCR_SMBUS_3_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_SLAVE_COMMAND))\r
-\r
-#define ADDR_SMBUS_3_MASTER_COMMAND 0x4000B40C\r
-#define MMCR_SMBUS_3_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_MASTER_COMMAND))\r
-\r
-#define ADDR_SMB_3_DATA 0x4000B408\r
-#define MMCR_SMB_3_DATA (*(VUINT8 *)(ADDR_SMB_3_DATA))\r
-\r
-#define ADDR_SMB_3_OWN_ADDRESS 0x4000B404\r
-#define MMCR_SMB_3_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_3_OWN_ADDRESS))\r
-\r
-#define ADDR_SMB_3_STATUS 0x4000B400\r
-#define MMCR_SMB_3_STATUS (*(VUINT8 *)(ADDR_SMB_3_STATUS))\r
-\r
-#define ADDR_SMB_3_CONTROL 0x4000B400\r
-#define MMCR_SMB_3_CONTROL (*(VUINT8 *)(ADDR_SMB_3_CONTROL))\r
-\r
-#define ADDR_SMB_2_CONTROL 0x4000B000\r
-#define MMCR_SMB_2_CONTROL (*(VUINT8 *)(ADDR_SMB_2_CONTROL))\r
-\r
-#define ADDR_SMB_2_STATUS 0x4000B000\r
-#define MMCR_SMB_2_STATUS (*(VUINT8 *)(ADDR_SMB_2_STATUS))\r
-\r
-#define ADDR_SMB_2_OWN_ADDRESS 0x4000B004\r
-#define MMCR_SMB_2_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_2_OWN_ADDRESS))\r
-\r
-#define ADDR_SMB_2_DATA 0x4000B008\r
-#define MMCR_SMB_2_DATA (*(VUINT8 *)(ADDR_SMB_2_DATA))\r
-\r
-#define ADDR_SMBUS_2_MASTER_COMMAND 0x4000B00C\r
-#define MMCR_SMBUS_2_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_MASTER_COMMAND))\r
-\r
-#define ADDR_SMBUS_2_SLAVE_COMMAND 0x4000B010\r
-#define MMCR_SMBUS_2_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_SLAVE_COMMAND))\r
-\r
-#define ADDR_SMB_2_PEC 0x4000B014\r
-#define MMCR_SMB_2_PEC (*(VUINT8 *)(ADDR_SMB_2_PEC))\r
-\r
-#define ADDR_SMB_2_DATA_TIMING2 0x4000B018\r
-#define MMCR_SMB_2_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_2_DATA_TIMING2))\r
-\r
-#define ADDR_SMB_2_COMPLETION 0x4000B020\r
-#define MMCR_SMB_2_COMPLETION (*(VUINT32 *)(ADDR_SMB_2_COMPLETION))\r
-\r
-#define ADDR_SMB_2_IDLE_SCALING 0x4000B024\r
-#define MMCR_SMB_2_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_2_IDLE_SCALING))\r
-\r
-#define ADDR_SMB_2_CONFIGURATION 0x4000B028\r
-#define MMCR_SMB_2_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_2_CONFIGURATION))\r
-\r
-#define ADDR_SMB_2_BUS_CLOCK 0x4000B02C\r
-#define MMCR_SMB_2_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_2_BUS_CLOCK))\r
-\r
-#define ADDR_SMB_2_BLOCK_ID 0x4000B030\r
-#define MMCR_SMB_2_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_2_BLOCK_ID))\r
-\r
-#define ADDR_SMB_2_REVISION 0x4000B034\r
-#define MMCR_SMB_2_REVISION (*(VUINT8 *)(ADDR_SMB_2_REVISION))\r
-\r
-#define ADDR_SMB_2_BIT_BANG_CONTROL 0x4000B038\r
-#define MMCR_SMB_2_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_2_BIT_BANG_CONTROL))\r
-\r
-#define ADDR_SMB_2_CLOCK_SYNC 0x4000B03C\r
-#define MMCR_SMB_2_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_2_CLOCK_SYNC))\r
-\r
-#define ADDR_SMB_2_DATA_TIMING 0x4000B040\r
-#define MMCR_SMB_2_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_2_DATA_TIMING))\r
-\r
-#define ADDR_SMB_2_TIME_OUT_SCALING 0x4000B044\r
-#define MMCR_SMB_2_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_2_TIME_OUT_SCALING))\r
-\r
-#define ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER 0x4000B048\r
-#define MMCR_SMBUS_2_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER 0x4000B04C\r
-#define MMCR_SMBUS_2_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER 0x4000B050\r
-#define MMCR_SMBUS_2_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER))\r
-\r
-#define ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER 0x4000B054\r
-#define MMCR_SMBUS_2_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMB_2_DEBUG_FSM_I2C 0x4000B058\r
-#define MMCR_SMB_2_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_I2C))\r
-\r
-#define ADDR_SMB_2_DEBUG_FSM_SMB 0x4000B05C\r
-#define MMCR_SMB_2_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_SMB))\r
-\r
-#define ADDR_SMB_1_CONTROL 0x4000AC00\r
-#define MMCR_SMB_1_CONTROL (*(VUINT8 *)(ADDR_SMB_1_CONTROL))\r
-\r
-#define ADDR_SMB_1_STATUS 0x4000AC00\r
-#define MMCR_SMB_1_STATUS (*(VUINT8 *)(ADDR_SMB_1_STATUS))\r
-\r
-#define ADDR_SMB_1_OWN_ADDRESS 0x4000AC04\r
-#define MMCR_SMB_1_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_1_OWN_ADDRESS))\r
-\r
-#define ADDR_SMB_1_DATA 0x4000AC08\r
-#define MMCR_SMB_1_DATA (*(VUINT8 *)(ADDR_SMB_1_DATA))\r
-\r
-#define ADDR_SMBUS_1_MASTER_COMMAND 0x4000AC0C\r
-#define MMCR_SMBUS_1_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_MASTER_COMMAND))\r
-\r
-#define ADDR_SMBUS_1_SLAVE_COMMAND 0x4000AC10\r
-#define MMCR_SMBUS_1_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_SLAVE_COMMAND))\r
-\r
-#define ADDR_SMB_1_PEC 0x4000AC14\r
-#define MMCR_SMB_1_PEC (*(VUINT8 *)(ADDR_SMB_1_PEC))\r
-\r
-#define ADDR_SMB_1_DATA_TIMING2 0x4000AC18\r
-#define MMCR_SMB_1_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_1_DATA_TIMING2))\r
-\r
-#define ADDR_SMB_1_COMPLETION 0x4000AC20\r
-#define MMCR_SMB_1_COMPLETION (*(VUINT32 *)(ADDR_SMB_1_COMPLETION))\r
-\r
-#define ADDR_SMB_1_IDLE_SCALING 0x4000AC24\r
-#define MMCR_SMB_1_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_1_IDLE_SCALING))\r
-\r
-#define ADDR_SMB_1_CONFIGURATION 0x4000AC28\r
-#define MMCR_SMB_1_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_1_CONFIGURATION))\r
-\r
-#define ADDR_SMB_1_BUS_CLOCK 0x4000AC2C\r
-#define MMCR_SMB_1_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_1_BUS_CLOCK))\r
-\r
-#define ADDR_SMB_1_BLOCK_ID 0x4000AC30\r
-#define MMCR_SMB_1_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_1_BLOCK_ID))\r
-\r
-#define ADDR_SMB_1_REVISION 0x4000AC34\r
-#define MMCR_SMB_1_REVISION (*(VUINT8 *)(ADDR_SMB_1_REVISION))\r
-\r
-#define ADDR_SMB_1_BIT_BANG_CONTROL 0x4000AC38\r
-#define MMCR_SMB_1_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_1_BIT_BANG_CONTROL))\r
-\r
-#define ADDR_SMB_1_CLOCK_SYNC 0x4000AC3C\r
-#define MMCR_SMB_1_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_1_CLOCK_SYNC))\r
-\r
-#define ADDR_SMB_1_DATA_TIMING 0x4000AC40\r
-#define MMCR_SMB_1_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_1_DATA_TIMING))\r
-\r
-#define ADDR_SMB_1_TIME_OUT_SCALING 0x4000AC44\r
-#define MMCR_SMB_1_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_1_TIME_OUT_SCALING))\r
-\r
-#define ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER 0x4000AC48\r
-#define MMCR_SMBUS_1_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER 0x4000AC4C\r
-#define MMCR_SMBUS_1_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER 0x4000AC50\r
-#define MMCR_SMBUS_1_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER))\r
-\r
-#define ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER 0x4000AC54\r
-#define MMCR_SMBUS_1_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMB_1_DEBUG_FSM_I2C 0x4000AC58\r
-#define MMCR_SMB_1_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_I2C))\r
-\r
-#define ADDR_SMB_1_DEBUG_FSM_SMB 0x4000AC5C\r
-#define MMCR_SMB_1_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_SMB))\r
-\r
-#define ADDR_SMB_0_STATUS 0x40001800\r
-#define MMCR_SMB_0_STATUS (*(VUINT8 *)(ADDR_SMB_0_STATUS))\r
-\r
-#define ADDR_SMB_0_CONTROL 0x40001800\r
-#define MMCR_SMB_0_CONTROL (*(VUINT8 *)(ADDR_SMB_0_CONTROL))\r
-\r
-#define ADDR_SMB_0_OWN_ADDRESS 0x40001804\r
-#define MMCR_SMB_0_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_0_OWN_ADDRESS))\r
-\r
-#define ADDR_SMB_0_DATA 0x40001808\r
-#define MMCR_SMB_0_DATA (*(VUINT8 *)(ADDR_SMB_0_DATA))\r
-\r
-#define ADDR_SMBUS_0_MASTER_COMMAND 0x4000180C\r
-#define MMCR_SMBUS_0_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_MASTER_COMMAND))\r
-\r
-#define ADDR_SMBUS_0_SLAVE_COMMAND 0x40001810\r
-#define MMCR_SMBUS_0_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_SLAVE_COMMAND))\r
-\r
-#define ADDR_SMB_0_PEC 0x40001814\r
-#define MMCR_SMB_0_PEC (*(VUINT8 *)(ADDR_SMB_0_PEC))\r
-\r
-#define ADDR_SMB_0_DATA_TIMING2 0x40001818\r
-#define MMCR_SMB_0_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_0_DATA_TIMING2))\r
-\r
-#define ADDR_SMB_0_COMPLETION 0x40001820\r
-#define MMCR_SMB_0_COMPLETION (*(VUINT32 *)(ADDR_SMB_0_COMPLETION))\r
-\r
-#define ADDR_SMB_0_IDLE_SCALING 0x40001824\r
-#define MMCR_SMB_0_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_0_IDLE_SCALING))\r
-\r
-#define ADDR_SMB_0_CONFIGURATION 0x40001828\r
-#define MMCR_SMB_0_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_0_CONFIGURATION))\r
-\r
-#define ADDR_SMB_0_BUS_CLOCK 0x4000182C\r
-#define MMCR_SMB_0_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_0_BUS_CLOCK))\r
-\r
-#define ADDR_SMB_0_BLOCK_ID 0x40001830\r
-#define MMCR_SMB_0_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_0_BLOCK_ID))\r
-\r
-#define ADDR_SMB_0_REVISION 0x40001834\r
-#define MMCR_SMB_0_REVISION (*(VUINT8 *)(ADDR_SMB_0_REVISION))\r
-\r
-#define ADDR_SMB_0_BIT_BANG_CONTROL 0x40001838\r
-#define MMCR_SMB_0_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_0_BIT_BANG_CONTROL))\r
-\r
-#define ADDR_SMB_0_CLOCK_SYNC 0x4000183C\r
-#define MMCR_SMB_0_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_0_CLOCK_SYNC))\r
-\r
-#define ADDR_SMB_0_DATA_TIMING 0x40001840\r
-#define MMCR_SMB_0_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_0_DATA_TIMING))\r
-\r
-#define ADDR_SMB_0_TIME_OUT_SCALING 0x40001844\r
-#define MMCR_SMB_0_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_0_TIME_OUT_SCALING))\r
-\r
-#define ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER 0x40001848\r
-#define MMCR_SMBUS_0_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER 0x4000184C\r
-#define MMCR_SMBUS_0_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER 0x40001850\r
-#define MMCR_SMBUS_0_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER))\r
-\r
-#define ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER 0x40001854\r
-#define MMCR_SMBUS_0_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMB_0_DEBUG_FSM_I2C 0x40001858\r
-#define MMCR_SMB_0_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_I2C))\r
-\r
-#define ADDR_SMB_0_DEBUG_FSM_SMB 0x4000185C\r
-#define MMCR_SMB_0_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_SMB))\r
-\r
-/***************************************************************\r
-* Watchdog Timer Interface\r
-***************************************************************/\r
-#define ADDR_WATCHDOG_WDT_LOAD 0x40000400\r
-#define MMCR_WATCHDOG_WDT_LOAD (*(VUINT16 *)(ADDR_WATCHDOG_WDT_LOAD))\r
-\r
-#define ADDR_WATCHDOG_WDT_CONTROL 0x40000404\r
-#define MMCR_WATCHDOG_WDT_CONTROL (*(VUINT8 *)(ADDR_WATCHDOG_WDT_CONTROL))\r
-\r
-#define ADDR_WATCHDOG_WDT_KICK 0x40000408\r
-#define MMCR_WATCHDOG_WDT_KICK (*(VUINT8 *)(ADDR_WATCHDOG_WDT_KICK))\r
-\r
-#define ADDR_WATCHDOG_WDT_COUNT 0x4000040C\r
-#define MMCR_WATCHDOG_WDT_COUNT (*(VUINT16 *)(ADDR_WATCHDOG_WDT_COUNT))\r
-\r
-/***************************************************************\r
-* ACPI PM1\r
-***************************************************************/\r
-#define ADDR_ACPI_0_PM1_STATUS_1 0x400F1500\r
-#define MMCR_ACPI_0_PM1_STATUS_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_1))\r
-\r
-#define ADDR_ACPI_0_PM1_STATUS_2 0x400F1501\r
-#define MMCR_ACPI_0_PM1_STATUS_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_2))\r
-\r
-#define ADDR_ACPI_0_PM1_ENABLE_1 0x400F1502\r
-#define MMCR_ACPI_0_PM1_ENABLE_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_1))\r
-\r
-#define ADDR_ACPI_0_PM1_ENABLE_2 0x400F1503\r
-#define MMCR_ACPI_0_PM1_ENABLE_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_2))\r
-\r
-#define ADDR_ACPI_0_PM1_CONTROL_1 0x400F1504\r
-#define MMCR_ACPI_0_PM1_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_1))\r
-\r
-#define ADDR_ACPI_0_PM1_CONTROL_2 0x400F1505\r
-#define MMCR_ACPI_0_PM1_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_2))\r
-\r
-#define ADDR_ACPI_0_PM2_CONTROL_1 0x400F1506\r
-#define MMCR_ACPI_0_PM2_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_1))\r
-\r
-#define ADDR_ACPI_0_PM2_CONTROL_2 0x400F1507\r
-#define MMCR_ACPI_0_PM2_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_2))\r
-\r
-#define ADDR_ACPI_0_PM1_EC_PM_STATUS 0x400F1510\r
-#define MMCR_ACPI_0_PM1_EC_PM_STATUS (*(VUINT8 *)(ADDR_ACPI_0_PM1_EC_PM_STATUS))\r
-\r
-/***************************************************************\r
-* EC GP-SPI\r
-***************************************************************/\r
-#define ADDR_EC_1_SPI_CLOCK_GENERATOR 0x40009498\r
-#define MMCR_EC_1_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_GENERATOR))\r
-\r
-#define ADDR_EC_1_SPI_CLOCK_CONTROL 0x40009494\r
-#define MMCR_EC_1_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_CONTROL))\r
-\r
-#define ADDR_EC_1_SPI_RX_DATA 0x40009490\r
-#define MMCR_EC_1_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_RX_DATA))\r
-\r
-#define ADDR_EC_1_SPI_TX_DATA 0x4000948C\r
-#define MMCR_EC_1_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_TX_DATA))\r
-\r
-#define ADDR_EC_1_SPI_STATUS 0x40009488\r
-#define MMCR_EC_1_SPI_STATUS (*(VUINT32 *)(ADDR_EC_1_SPI_STATUS))\r
-\r
-#define ADDR_EC_1_SPI_CONTROL 0x40009484\r
-#define MMCR_EC_1_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CONTROL))\r
-\r
-#define ADDR_EC_1_SPI_ENABLE 0x40009480\r
-#define MMCR_EC_1_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_1_SPI_ENABLE))\r
-\r
-#define ADDR_EC_0_SPI_ENABLE 0x40009400\r
-#define MMCR_EC_0_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_0_SPI_ENABLE))\r
-\r
-#define ADDR_EC_0_SPI_CONTROL 0x40009404\r
-#define MMCR_EC_0_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CONTROL))\r
-\r
-#define ADDR_EC_0_SPI_STATUS 0x40009408\r
-#define MMCR_EC_0_SPI_STATUS (*(VUINT32 *)(ADDR_EC_0_SPI_STATUS))\r
-\r
-#define ADDR_EC_0_SPI_TX_DATA 0x4000940C\r
-#define MMCR_EC_0_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_TX_DATA))\r
-\r
-#define ADDR_EC_0_SPI_RX_DATA 0x40009410\r
-#define MMCR_EC_0_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_RX_DATA))\r
-\r
-#define ADDR_EC_0_SPI_CLOCK_CONTROL 0x40009414\r
-#define MMCR_EC_0_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_CONTROL))\r
-\r
-#define ADDR_EC_0_SPI_CLOCK_GENERATOR 0x40009418\r
-#define MMCR_EC_0_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_GENERATOR))\r
-\r
-/***************************************************************\r
-* Mailbox Registers Interface\r
-***************************************************************/\r
-#define ADDR_MAILBOX_HOST_TO_EC_MAILBOX 0x400F2500\r
-#define MMCR_MAILBOX_HOST_TO_EC_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_HOST_TO_EC_MAILBOX))\r
-\r
-#define ADDR_MAILBOX_EC_TO_HOST_MAILBOX 0x400F2504\r
-#define MMCR_MAILBOX_EC_TO_HOST_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_EC_TO_HOST_MAILBOX))\r
-\r
-#define ADDR_MAILBOX_SMI_INTERRUPT_SOURCE 0x400F2508\r
-#define MMCR_MAILBOX_SMI_INTERRUPT_SOURCE (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_SOURCE))\r
-\r
-#define ADDR_MAILBOX_SMI_INTERRUPT_MASK 0x400F250C\r
-#define MMCR_MAILBOX_SMI_INTERRUPT_MASK (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_MASK))\r
-\r
-#define ADDR_MAILBOX_3_0 0x400F2510\r
-#define MMCR_MAILBOX_3_0 (*(VUINT32 *)(ADDR_MAILBOX_3_0))\r
-\r
-#define ADDR_MAILBOX_7_4 0x400F2514\r
-#define MMCR_MAILBOX_7_4 (*(VUINT32 *)(ADDR_MAILBOX_7_4))\r
-\r
-#define ADDR_MAILBOX_BH_8 0x400F2518\r
-#define MMCR_MAILBOX_BH_8 (*(VUINT32 *)(ADDR_MAILBOX_BH_8))\r
-\r
-#define ADDR_MAILBOX_FH_CH 0x400F251C\r
-#define MMCR_MAILBOX_FH_CH (*(VUINT32 *)(ADDR_MAILBOX_FH_CH))\r
-\r
-#define ADDR_MAILBOX_13H_10H 0x400F2520\r
-#define MMCR_MAILBOX_13H_10H (*(VUINT32 *)(ADDR_MAILBOX_13H_10H))\r
-\r
-#define ADDR_MAILBOX_17H_14H 0x400F2524\r
-#define MMCR_MAILBOX_17H_14H (*(VUINT32 *)(ADDR_MAILBOX_17H_14H))\r
-\r
-#define ADDR_MAILBOX_1BH_18H 0x400F2528\r
-#define MMCR_MAILBOX_1BH_18H (*(VUINT32 *)(ADDR_MAILBOX_1BH_18H))\r
-\r
-#define ADDR_MAILBOX_1FH_1CH 0x400F252C\r
-#define MMCR_MAILBOX_1FH_1CH (*(VUINT32 *)(ADDR_MAILBOX_1FH_1CH))\r
-\r
-/***************************************************************\r
-* Hibernation Timer\r
-***************************************************************/\r
-#define ADDR_HIBERNATION_0_HTIMER_X_PRELOAD 0x40009800\r
-#define MMCR_HIBERNATION_0_HTIMER_X_PRELOAD (*(VUINT16 *)(ADDR_HIBERNATION_0_HTIMER_X_PRELOAD))\r
-\r
-#define ADDR_HIBERNATION_0_TIMER_X_CONTROL 0x40009804\r
-#define MMCR_HIBERNATION_0_TIMER_X_CONTROL (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_CONTROL))\r
-\r
-#define ADDR_HIBERNATION_0_TIMER_X_COUNT 0x40009808\r
-#define MMCR_HIBERNATION_0_TIMER_X_COUNT (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_COUNT))\r
-\r
-/***************************************************************\r
-* UART\r
-***************************************************************/\r
-#define ADDR_M16C550A_UART_ACTIVATE 0x400F1F30\r
-#define MMCR_M16C550A_UART_ACTIVATE (*(VUINT8 *)(ADDR_M16C550A_UART_ACTIVATE))\r
-\r
-#define ADDR_M16C550A_UART_CONFIG_SELECT 0x400F1FF0\r
-#define MMCR_M16C550A_UART_CONFIG_SELECT (*(VUINT8 *)(ADDR_M16C550A_UART_CONFIG_SELECT))\r
-\r
-#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB 0x400F1D00\r
-#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB))\r
-\r
-#define ADDR_M16C550A_UART_RECEIVE_BUFFER 0x400F1D00\r
-#define MMCR_M16C550A_UART_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_RECEIVE_BUFFER))\r
-\r
-#define ADDR_M16C550A_UART_TRANSMIT_BUFFER 0x400F1D00\r
-#define MMCR_M16C550A_UART_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB 0x400F1D01\r
-#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB))\r
-\r
-#define ADDR_M16C550A_UART_INTERRUPT_ENABLE 0x400F1D01\r
-#define MMCR_M16C550A_UART_INTERRUPT_ENABLE (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_M16C550A_UART_FIFO_CONTROL 0x400F1D02\r
-#define MMCR_M16C550A_UART_FIFO_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_FIFO_CONTROL))\r
-\r
-#define ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION 0x400F1D02\r
-#define MMCR_M16C550A_UART_INTERRUPT_IDENTIFICATION (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION))\r
-\r
-#define ADDR_M16C550A_UART_LINE_CONTROL 0x400F1D03\r
-#define MMCR_M16C550A_UART_LINE_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_CONTROL))\r
-\r
-#define ADDR_M16C550A_UART_MODEM_CONTROL 0x400F1D04\r
-#define MMCR_M16C550A_UART_MODEM_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_CONTROL))\r
-\r
-#define ADDR_M16C550A_UART_LINE_STATUS 0x400F1D05\r
-#define MMCR_M16C550A_UART_LINE_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_STATUS))\r
-\r
-#define ADDR_M16C550A_UART_MODEM_STATUS 0x400F1D06\r
-#define MMCR_M16C550A_UART_MODEM_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_STATUS))\r
-\r
-#define ADDR_M16C550A_UART_SCRATCHPAD 0x400F1D07\r
-#define MMCR_M16C550A_UART_SCRATCHPAD (*(VUINT8 *)(ADDR_M16C550A_UART_SCRATCHPAD))\r
-\r
-/***************************************************************\r
-* TACH\r
-***************************************************************/\r
-#define ADDR_TACH_0_CONTROL 0x40006000\r
-#define MMCR_TACH_0_CONTROL (*(VUINT32 *)(ADDR_TACH_0_CONTROL))\r
-\r
-#define ADDR_TACH_0_STATUS 0x40006004\r
-#define MMCR_TACH_0_STATUS (*(VUINT32 *)(ADDR_TACH_0_STATUS))\r
-\r
-#define ADDR_TACH_0_HIGH_LIMIT 0x40006008\r
-#define MMCR_TACH_0_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_0_HIGH_LIMIT))\r
-\r
-#define ADDR_TACH_0_LOW_LIMIT 0x4000600C\r
-#define MMCR_TACH_0_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_0_LOW_LIMIT))\r
-\r
-#define ADDR_TACH_1_CONTROL 0x40006010\r
-#define MMCR_TACH_1_CONTROL (*(VUINT32 *)(ADDR_TACH_1_CONTROL))\r
-\r
-#define ADDR_TACH_1_STATUS 0x40006014\r
-#define MMCR_TACH_1_STATUS (*(VUINT32 *)(ADDR_TACH_1_STATUS))\r
-\r
-#define ADDR_TACH_1_HIGH_LIMIT 0x40006018\r
-#define MMCR_TACH_1_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_1_HIGH_LIMIT))\r
-\r
-#define ADDR_TACH_1_LOW_LIMIT 0x4000601C\r
-#define MMCR_TACH_1_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_1_LOW_LIMIT))\r
-\r
-/***************************************************************\r
-* Global Config Regs Basic\r
-***************************************************************/\r
-#define ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER 0x400FFF07\r
-#define MMCR_GLOBAL_LOGICAL_DEVICE_NUMBER (*(VUINT8 *)(ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER))\r
-\r
-#define ADDR_GLOBAL_DEVICE_ID 0x400FFF20\r
-#define MMCR_GLOBAL_DEVICE_ID (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_ID))\r
-\r
-#define ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED 0x400FFF21\r
-#define MMCR_GLOBAL_DEVICE_REVISION_HARD_WIRED (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED))\r
-\r
-#define ADDR_GLOBAL_GCR_BUILD 0x400FFF28\r
-#define MMCR_GLOBAL_GCR_BUILD (*(VUINT16 *)(ADDR_GLOBAL_GCR_BUILD))\r
-\r
-#define ADDR_GLOBAL_GCR_SCRATCH 0x400FFF2C\r
-#define MMCR_GLOBAL_GCR_SCRATCH (*(VUINT32 *)(ADDR_GLOBAL_GCR_SCRATCH))\r
-\r
-/***************************************************************\r
-* Trace FIFO Debug Port\r
-***************************************************************/\r
-#define ADDR_TRACE_DATA 0x40008C00\r
-#define MMCR_TRACE_DATA (*(VUINT32 *)(ADDR_TRACE_DATA))\r
-\r
-#define ADDR_TRACE_CONTROL 0x40008C04\r
-#define MMCR_TRACE_CONTROL (*(VUINT32 *)(ADDR_TRACE_CONTROL))\r
-\r
-/***************************************************************\r
-* STAP\r
-***************************************************************/\r
-#define ADDR_STAP_MESSAGE_OBF 0x40080000\r
-#define MMCR_STAP_MESSAGE_OBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_OBF))\r
-\r
-#define ADDR_STAP_MESSAGE_IBF 0x40080004\r
-#define MMCR_STAP_MESSAGE_IBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_IBF))\r
-\r
-#define ADDR_STAP_OBF_STATUS 0x40080008\r
-#define MMCR_STAP_OBF_STATUS (*(VUINT8 *)(ADDR_STAP_OBF_STATUS))\r
-\r
-#define ADDR_STAP_IBF_STATUS 0x40080009\r
-#define MMCR_STAP_IBF_STATUS (*(VUINT8 *)(ADDR_STAP_IBF_STATUS))\r
-\r
-#define ADDR_STAP_DBG_CTRL 0x4008000C\r
-#define MMCR_STAP_DBG_CTRL (*(VUINT8 *)(ADDR_STAP_DBG_CTRL))\r
-\r
-/***************************************************************\r
-* EMI\r
-***************************************************************/\r
-#define ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX 0x400F0100\r
-#define MMCR_IMAP_EMI_HOST_TO_EC_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX))\r
-\r
-#define ADDR_IMAP_EC_TO_HOST_MAILBOX 0x400F0101\r
-#define MMCR_IMAP_EC_TO_HOST_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EC_TO_HOST_MAILBOX))\r
-\r
-#define ADDR_IMAP_MEMORY_BASE_ADDRESS_0 0x400F0104\r
-#define MMCR_IMAP_MEMORY_BASE_ADDRESS_0 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_0))\r
-\r
-#define ADDR_IMAP_MEMORY_READ_LIMIT_0 0x400F0108\r
-#define MMCR_IMAP_MEMORY_READ_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_0))\r
-\r
-#define ADDR_IMAP_MEMORY_WRITE_LIMIT_0 0x400F010A\r
-#define MMCR_IMAP_MEMORY_WRITE_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_0))\r
-\r
-#define ADDR_IMAP_MEMORY_BASE_ADDRESS_1 0x400F010C\r
-#define MMCR_IMAP_MEMORY_BASE_ADDRESS_1 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_1))\r
-\r
-#define ADDR_IMAP_MEMORY_READ_LIMIT_1 0x400F0110\r
-#define MMCR_IMAP_MEMORY_READ_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_1))\r
-\r
-#define ADDR_IMAP_MEMORY_WRITE_LIMIT_1 0x400F0112\r
-#define MMCR_IMAP_MEMORY_WRITE_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_1))\r
-\r
-#define ADDR_IMAP_INTERRUPT_SET 0x400F0114\r
-#define MMCR_IMAP_INTERRUPT_SET (*(VUINT16 *)(ADDR_IMAP_INTERRUPT_SET))\r
-\r
-#define ADDR_IMAP_HOST_CLEAR_ENABLE 0x400F0116\r
-#define MMCR_IMAP_HOST_CLEAR_ENABLE (*(VUINT16 *)(ADDR_IMAP_HOST_CLEAR_ENABLE))\r
-\r
-/***************************************************************\r
-* Blinking/Breathing PWM\r
-***************************************************************/\r
-#define ADDR_LED_3_UPDATE_INTERVAL 0x4000BB10\r
-#define MMCR_LED_3_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_3_UPDATE_INTERVAL))\r
-\r
-#define ADDR_LED_3_UPDATE_STEPSIZE 0x4000BB0C\r
-#define MMCR_LED_3_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_3_UPDATE_STEPSIZE))\r
-\r
-#define ADDR_LED_3_DELAY 0x4000BB08\r
-#define MMCR_LED_3_DELAY (*(VUINT32 *)(ADDR_LED_3_DELAY))\r
-\r
-#define ADDR_LED_3_LIMITS 0x4000BB04\r
-#define MMCR_LED_3_LIMITS (*(VUINT32 *)(ADDR_LED_3_LIMITS))\r
-\r
-#define ADDR_LED_3_CONFIGURATION 0x4000BB00\r
-#define MMCR_LED_3_CONFIGURATION (*(VUINT32 *)(ADDR_LED_3_CONFIGURATION))\r
-\r
-#define ADDR_LED_2_UPDATE_INTERVAL 0x4000BA10\r
-#define MMCR_LED_2_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_2_UPDATE_INTERVAL))\r
-\r
-#define ADDR_LED_2_UPDATE_STEPSIZE 0x4000BA0C\r
-#define MMCR_LED_2_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_2_UPDATE_STEPSIZE))\r
-\r
-#define ADDR_LED_2_DELAY 0x4000BA08\r
-#define MMCR_LED_2_DELAY (*(VUINT32 *)(ADDR_LED_2_DELAY))\r
-\r
-#define ADDR_LED_2_LIMITS 0x4000BA04\r
-#define MMCR_LED_2_LIMITS (*(VUINT32 *)(ADDR_LED_2_LIMITS))\r
-\r
-#define ADDR_LED_2_CONFIGURATION 0x4000BA00\r
-#define MMCR_LED_2_CONFIGURATION (*(VUINT32 *)(ADDR_LED_2_CONFIGURATION))\r
-\r
-#define ADDR_LED_1_CONFIGURATION 0x4000B900\r
-#define MMCR_LED_1_CONFIGURATION (*(VUINT32 *)(ADDR_LED_1_CONFIGURATION))\r
-\r
-#define ADDR_LED_1_LIMITS 0x4000B904\r
-#define MMCR_LED_1_LIMITS (*(VUINT32 *)(ADDR_LED_1_LIMITS))\r
-\r
-#define ADDR_LED_1_DELAY 0x4000B908\r
-#define MMCR_LED_1_DELAY (*(VUINT32 *)(ADDR_LED_1_DELAY))\r
-\r
-#define ADDR_LED_1_UPDATE_STEPSIZE 0x4000B90C\r
-#define MMCR_LED_1_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_1_UPDATE_STEPSIZE))\r
-\r
-#define ADDR_LED_1_UPDATE_INTERVAL 0x4000B910\r
-#define MMCR_LED_1_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_1_UPDATE_INTERVAL))\r
-\r
-#define ADDR_LED_0_CONFIGURATION 0x4000B800\r
-#define MMCR_LED_0_CONFIGURATION (*(VUINT32 *)(ADDR_LED_0_CONFIGURATION))\r
-\r
-#define ADDR_LED_0_LIMITS 0x4000B804\r
-#define MMCR_LED_0_LIMITS (*(VUINT32 *)(ADDR_LED_0_LIMITS))\r
-\r
-#define ADDR_LED_0_DELAY 0x4000B808\r
-#define MMCR_LED_0_DELAY (*(VUINT32 *)(ADDR_LED_0_DELAY))\r
-\r
-#define ADDR_LED_0_UPDATE_STEPSIZE 0x4000B80C\r
-#define MMCR_LED_0_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_0_UPDATE_STEPSIZE))\r
-\r
-#define ADDR_LED_0_UPDATE_INTERVAL 0x4000B810\r
-#define MMCR_LED_0_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_0_UPDATE_INTERVAL))\r
-\r
-/***************************************************************\r
-* SMSC BC-Link Master\r
-***************************************************************/\r
-#define ADDR_BC_LINK_STATUS 0x4000BC00\r
-#define MMCR_BC_LINK_STATUS (*(VUINT8 *)(ADDR_BC_LINK_STATUS))\r
-\r
-#define ADDR_BC_LINK_ADDRESS 0x4000BC04\r
-#define MMCR_BC_LINK_ADDRESS (*(VUINT8 *)(ADDR_BC_LINK_ADDRESS))\r
-\r
-#define ADDR_BC_LINK_DATA 0x4000BC08\r
-#define MMCR_BC_LINK_DATA (*(VUINT8 *)(ADDR_BC_LINK_DATA))\r
-\r
-#define ADDR_BC_LINK_CLOCK_SELECT 0x4000BC0C\r
-#define MMCR_BC_LINK_CLOCK_SELECT (*(VUINT8 *)(ADDR_BC_LINK_CLOCK_SELECT))\r
-\r
-/***************************************************************\r
-* Basic Timer\r
-***************************************************************/\r
-#define ADDR_BASIC_0_TIMER_COUNT 0x40000C00\r
-#define MMCR_BASIC_0_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_0_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_0_TIMER_PRELOAD 0x40000C04\r
-#define MMCR_BASIC_0_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_0_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_0_TIMER_STATUS 0x40000C08\r
-#define MMCR_BASIC_0_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_0_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE 0x40000C0C\r
-#define MMCR_BASIC_0_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_0_TIMER_CONTROL 0x40000C10\r
-#define MMCR_BASIC_0_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_0_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_1_TIMER_COUNT 0x40000C20\r
-#define MMCR_BASIC_1_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_1_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_1_TIMER_PRELOAD 0x40000C24\r
-#define MMCR_BASIC_1_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_1_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_1_TIMER_STATUS 0x40000C28\r
-#define MMCR_BASIC_1_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_1_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE 0x40000C2C\r
-#define MMCR_BASIC_1_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_1_TIMER_CONTROL 0x40000C30\r
-#define MMCR_BASIC_1_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_1_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_2_TIMER_COUNT 0x40000C40\r
-#define MMCR_BASIC_2_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_2_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_2_TIMER_PRELOAD 0x40000C44\r
-#define MMCR_BASIC_2_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_2_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_2_TIMER_STATUS 0x40000C48\r
-#define MMCR_BASIC_2_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_2_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE 0x40000C4C\r
-#define MMCR_BASIC_2_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_2_TIMER_CONTROL 0x40000C50\r
-#define MMCR_BASIC_2_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_2_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_3_TIMER_COUNT 0x40000C60\r
-#define MMCR_BASIC_3_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_3_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_3_TIMER_PRELOAD 0x40000C64\r
-#define MMCR_BASIC_3_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_3_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_3_TIMER_STATUS 0x40000C68\r
-#define MMCR_BASIC_3_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_3_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE 0x40000C6C\r
-#define MMCR_BASIC_3_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_3_TIMER_CONTROL 0x40000C70\r
-#define MMCR_BASIC_3_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_3_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_4_TIMER_COUNT 0x40000C80\r
-#define MMCR_BASIC_4_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_4_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_4_TIMER_PRELOAD 0x40000C84\r
-#define MMCR_BASIC_4_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_4_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_4_TIMER_STATUS 0x40000C88\r
-#define MMCR_BASIC_4_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_4_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE 0x40000C8C\r
-#define MMCR_BASIC_4_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_4_TIMER_CONTROL 0x40000C90\r
-#define MMCR_BASIC_4_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_4_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_5_TIMER_COUNT 0x40000CA0\r
-#define MMCR_BASIC_5_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_5_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_5_TIMER_PRELOAD 0x40000CA4\r
-#define MMCR_BASIC_5_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_5_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_5_TIMER_STATUS 0x40000CA8\r
-#define MMCR_BASIC_5_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_5_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE 0x40000CAC\r
-#define MMCR_BASIC_5_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_5_TIMER_CONTROL 0x40000CB0\r
-#define MMCR_BASIC_5_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_5_TIMER_CONTROL))\r
-\r
-/***************************************************************\r
-* INTS\r
-***************************************************************/\r
-#define ADDR_EC_GIRQ8_SOURCE 0x4000C000\r
-#define MMCR_EC_GIRQ8_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ8_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ8_ENABLE_SET 0x4000C004\r
-#define MMCR_EC_GIRQ8_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ8_RESULT 0x4000C008\r
-#define MMCR_EC_GIRQ8_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ8_RESULT))\r
-\r
-#define ADDR_EC_GIRQ8_ENABLE_CLEAR 0x4000C00C\r
-#define MMCR_EC_GIRQ8_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ9_SOURCE 0x4000C014\r
-#define MMCR_EC_GIRQ9_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ9_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ9_ENABLE_SET 0x4000C018\r
-#define MMCR_EC_GIRQ9_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ9_RESULT 0x4000C01C\r
-#define MMCR_EC_GIRQ9_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ9_RESULT))\r
-\r
-#define ADDR_EC_GIRQ9_ENABLE_CLEAR 0x4000C020\r
-#define MMCR_EC_GIRQ9_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ10_SOURCE 0x4000C028\r
-#define MMCR_EC_GIRQ10_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ10_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ10_ENABLE_SET 0x4000C02C\r
-#define MMCR_EC_GIRQ10_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ10_RESULT 0x4000C030\r
-#define MMCR_EC_GIRQ10_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ10_RESULT))\r
-\r
-#define ADDR_EC_GIRQ10_ENABLE_CLEAR 0x4000C034\r
-#define MMCR_EC_GIRQ10_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ11_SOURCE 0x4000C03C\r
-#define MMCR_EC_GIRQ11_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ11_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ11_ENABLE_SET 0x4000C040\r
-#define MMCR_EC_GIRQ11_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ11_RESULT 0x4000C044\r
-#define MMCR_EC_GIRQ11_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ11_RESULT))\r
-\r
-#define ADDR_EC_GIRQ11_ENABLE_CLEAR 0x4000C048\r
-#define MMCR_EC_GIRQ11_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ12_SOURCE 0x4000C050\r
-#define MMCR_EC_GIRQ12_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ12_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ12_ENABLE_SET 0x4000C054\r
-#define MMCR_EC_GIRQ12_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ12_RESULT 0x4000C058\r
-#define MMCR_EC_GIRQ12_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ12_RESULT))\r
-\r
-#define ADDR_EC_GIRQ12_ENABLE_CLEAR 0x4000C05C\r
-#define MMCR_EC_GIRQ12_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ13_SOURCE 0x4000C064\r
-#define MMCR_EC_GIRQ13_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ13_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ13_ENABLE_SET 0x4000C068\r
-#define MMCR_EC_GIRQ13_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ13_RESULT 0x4000C06C\r
-#define MMCR_EC_GIRQ13_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ13_RESULT))\r
-\r
-#define ADDR_EC_GIRQ13_ENABLE_CLEAR 0x4000C070\r
-#define MMCR_EC_GIRQ13_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ14_SOURCE 0x4000C078\r
-#define MMCR_EC_GIRQ14_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ14_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ14_ENABLE_SET 0x4000C07C\r
-#define MMCR_EC_GIRQ14_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ14_RESULT 0x4000C080\r
-#define MMCR_EC_GIRQ14_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ14_RESULT))\r
-\r
-#define ADDR_EC_GIRQ14_ENABLE_CLEAR 0x4000C084\r
-#define MMCR_EC_GIRQ14_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ15_SOURCE 0x4000C08C\r
-#define MMCR_EC_GIRQ15_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ15_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ15_ENABLE_SET 0x4000C090\r
-#define MMCR_EC_GIRQ15_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ15_RESULT 0x4000C094\r
-#define MMCR_EC_GIRQ15_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ15_RESULT))\r
-\r
-#define ADDR_EC_GIRQ15_ENABLE_CLEAR 0x4000C098\r
-#define MMCR_EC_GIRQ15_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ16_SOURCE 0x4000C0A0\r
-#define MMCR_EC_GIRQ16_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ16_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ16_ENABLE_SET 0x4000C0A4\r
-#define MMCR_EC_GIRQ16_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ16_RESULT 0x4000C0A8\r
-#define MMCR_EC_GIRQ16_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ16_RESULT))\r
-\r
-#define ADDR_EC_GIRQ16_ENABLE_CLEAR 0x4000C0AC\r
-#define MMCR_EC_GIRQ16_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ17_SOURCE 0x4000C0B4\r
-#define MMCR_EC_GIRQ17_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ17_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ17_ENABLE_SET 0x4000C0B8\r
-#define MMCR_EC_GIRQ17_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ17_RESULT 0x4000C0BC\r
-#define MMCR_EC_GIRQ17_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ17_RESULT))\r
-\r
-#define ADDR_EC_GIRQ17_ENABLE_CLEAR 0x4000C0C0\r
-#define MMCR_EC_GIRQ17_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ18_SOURCE 0x4000C0C8\r
-#define MMCR_EC_GIRQ18_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ18_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ18_ENABLE_SET 0x4000C0CC\r
-#define MMCR_EC_GIRQ18_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ18_RESULT 0x4000C0D0\r
-#define MMCR_EC_GIRQ18_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ18_RESULT))\r
-\r
-#define ADDR_EC_GIRQ18_ENABLE_CLEAR 0x4000C0D4\r
-#define MMCR_EC_GIRQ18_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ19_SOURCE 0x4000C0DC\r
-#define MMCR_EC_GIRQ19_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ19_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ19_ENABLE_SET 0x4000C0E0\r
-#define MMCR_EC_GIRQ19_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ19_RESULT 0x4000C0E4\r
-#define MMCR_EC_GIRQ19_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ19_RESULT))\r
-\r
-#define ADDR_EC_GIRQ19_ENABLE_CLEAR 0x4000C0E8\r
-#define MMCR_EC_GIRQ19_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ20_SOURCE 0x4000C0F0\r
-#define MMCR_EC_GIRQ20_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ20_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ20_ENABLE_SET 0x4000C0F4\r
-#define MMCR_EC_GIRQ20_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ20_RESULT 0x4000C0F8\r
-#define MMCR_EC_GIRQ20_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ20_RESULT))\r
-\r
-#define ADDR_EC_GIRQ20_ENABLE_CLEAR 0x4000C0FC\r
-#define MMCR_EC_GIRQ20_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ21_SOURCE 0x4000C104\r
-#define MMCR_EC_GIRQ21_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ21_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ21_ENABLE_SET 0x4000C108\r
-#define MMCR_EC_GIRQ21_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ21_RESULT 0x4000C10C\r
-#define MMCR_EC_GIRQ21_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ21_RESULT))\r
-\r
-#define ADDR_EC_GIRQ21_ENABLE_CLEAR 0x4000C110\r
-#define MMCR_EC_GIRQ21_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ22_SOURCE 0x4000C118\r
-#define MMCR_EC_GIRQ22_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ22_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ22_ENABLE_SET 0x4000C11C\r
-#define MMCR_EC_GIRQ22_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ22_RESULT 0x4000C120\r
-#define MMCR_EC_GIRQ22_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ22_RESULT))\r
-\r
-#define ADDR_EC_GIRQ22_ENABLE_CLEAR 0x4000C124\r
-#define MMCR_EC_GIRQ22_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ23_SOURCE 0x4000C12C\r
-#define MMCR_EC_GIRQ23_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ23_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ23_ENABLE_SET 0x4000C130\r
-#define MMCR_EC_GIRQ23_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ23_RESULT 0x4000C134\r
-#define MMCR_EC_GIRQ23_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ23_RESULT))\r
-\r
-#define ADDR_EC_GIRQ23_ENABLE_CLEAR 0x4000C138\r
-#define MMCR_EC_GIRQ23_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_BLOCK_ENABLE_SET 0x4000C200\r
-#define MMCR_EC_BLOCK_ENABLE_SET (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_SET))\r
-\r
-#define ADDR_EC_BLOCK_ENABLE_CLEAR 0x4000C204\r
-#define MMCR_EC_BLOCK_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_BLOCK_IRQ_VECTOR 0x4000C208\r
-#define MMCR_EC_BLOCK_IRQ_VECTOR (*(VUINT32 *)(ADDR_EC_BLOCK_IRQ_VECTOR))\r
-\r
-/***************************************************************\r
-* RPM Fan Control\r
-***************************************************************/\r
-#define ADDR_RPM_FAN_SETTING 0x4000A000\r
-#define MMCR_RPM_FAN_SETTING (*(VUINT8 *)(ADDR_RPM_FAN_SETTING))\r
-\r
-#define ADDR_RPM_PWM_DIVIDE 0x4000A001\r
-#define MMCR_RPM_PWM_DIVIDE (*(VUINT8 *)(ADDR_RPM_PWM_DIVIDE))\r
-\r
-#define ADDR_RPM_FAN_CONFIGURATION_1 0x4000A002\r
-#define MMCR_RPM_FAN_CONFIGURATION_1 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_1))\r
-\r
-#define ADDR_RPM_FAN_CONFIGURATION_2 0x4000A003\r
-#define MMCR_RPM_FAN_CONFIGURATION_2 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_2))\r
-\r
-#define ADDR_RPM_GAIN 0x4000A005\r
-#define MMCR_RPM_GAIN (*(VUINT8 *)(ADDR_RPM_GAIN))\r
-\r
-#define ADDR_RPM_FAN_SPIN_UP_CONFIGURATION 0x4000A006\r
-#define MMCR_RPM_FAN_SPIN_UP_CONFIGURATION (*(VUINT8 *)(ADDR_RPM_FAN_SPIN_UP_CONFIGURATION))\r
-\r
-#define ADDR_RPM_FAN_STEP 0x4000A007\r
-#define MMCR_RPM_FAN_STEP (*(VUINT8 *)(ADDR_RPM_FAN_STEP))\r
-\r
-#define ADDR_RPM_FAN_MINIMUM_DRIVE 0x4000A008\r
-#define MMCR_RPM_FAN_MINIMUM_DRIVE (*(VUINT8 *)(ADDR_RPM_FAN_MINIMUM_DRIVE))\r
-\r
-#define ADDR_RPM_VALID_TACH_COUNT 0x4000A009\r
-#define MMCR_RPM_VALID_TACH_COUNT (*(VUINT8 *)(ADDR_RPM_VALID_TACH_COUNT))\r
-\r
-#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE 0x4000A00A\r
-#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE))\r
-\r
-#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE 0x4000A00B\r
-#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE))\r
-\r
-#define ADDR_RPM_TACH_TARGET_LOW_BYTE 0x4000A00C\r
-#define MMCR_RPM_TACH_TARGET_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_LOW_BYTE))\r
-\r
-#define ADDR_RPM_TACH_TARGET_HIGH_BYTE 0x4000A00D\r
-#define MMCR_RPM_TACH_TARGET_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_HIGH_BYTE))\r
-\r
-#define ADDR_RPM_TACH_READING_LOW_BYTE 0x4000A00E\r
-#define MMCR_RPM_TACH_READING_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_LOW_BYTE))\r
-\r
-#define ADDR_RPM_TACH_READING_HIGH_BYTE 0x4000A00F\r
-#define MMCR_RPM_TACH_READING_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_HIGH_BYTE))\r
-\r
-#define ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY 0x4000A010\r
-#define MMCR_RPM_PWM_DRIVER_BASE_FREQUENCY (*(VUINT8 *)(ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY))\r
-\r
-#define ADDR_RPM_FAN_STATUS 0x4000A011\r
-#define MMCR_RPM_FAN_STATUS (*(VUINT8 *)(ADDR_RPM_FAN_STATUS))\r
-\r
-#define ADDR_RPM_FAN_TEST 0x4000A014\r
-#define MMCR_RPM_FAN_TEST (*(VUINT8 *)(ADDR_RPM_FAN_TEST))\r
-\r
-#define ADDR_RPM_FAN_TEST1 0x4000A015\r
-#define MMCR_RPM_FAN_TEST1 (*(VUINT8 *)(ADDR_RPM_FAN_TEST1))\r
-\r
-#define ADDR_RPM_FAN_TEST2 0x4000A016\r
-#define MMCR_RPM_FAN_TEST2 (*(VUINT8 *)(ADDR_RPM_FAN_TEST2))\r
-\r
-#define ADDR_RPM_FAN_TEST3 0x4000A017\r
-#define MMCR_RPM_FAN_TEST3 (*(VUINT8 *)(ADDR_RPM_FAN_TEST3))\r
-\r
-/***************************************************************\r
-* V2P (HP ckt#1) 32bit_aligned\r
-***************************************************************/\r
-#define ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY 0x40007C80\r
-#define MMCR_V2P_ADC2PWM_OUTPUT_FREQUENCY (*(VUINT32 *)(ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY))\r
-\r
-#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW 0x40007C84\r
-#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW))\r
-\r
-#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH 0x40007C88\r
-#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH))\r
-\r
-#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA 0x40007C8C\r
-#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA))\r
-\r
-#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS 0x40007C90\r
-#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_STATUS (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS))\r
-\r
-#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 0x40007C94\r
-#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1))\r
-\r
-#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 0x40007C98\r
-#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2))\r
-\r
-#define ADDR_V2P_ADC2PWM_CONTROL 0x40007C9C\r
-#define MMCR_V2P_ADC2PWM_CONTROL (*(VUINT32 *)(ADDR_V2P_ADC2PWM_CONTROL))\r
-\r
-#define ADDR_V2P_LPF_CUT_OFF_FREQUENCY 0x40007CA0\r
-#define MMCR_V2P_LPF_CUT_OFF_FREQUENCY (*(VUINT32 *)(ADDR_V2P_LPF_CUT_OFF_FREQUENCY))\r
-\r
-#define ADDR_V2P_TEST 0x40007CA4\r
-#define MMCR_V2P_TEST (*(VUINT32 *)(ADDR_V2P_TEST))\r
-\r
-#define ADDR_V2P_NOTICE_DATA 0x40007CA8\r
-#define MMCR_V2P_NOTICE_DATA (*(VUINT32 *)(ADDR_V2P_NOTICE_DATA))\r
-\r
-#define ADDR_V2P_TEST_DATA 0x40007CAC\r
-#define MMCR_V2P_TEST_DATA (*(VUINT32 *)(ADDR_V2P_TEST_DATA))\r
-\r
-#define ADDR_V2P_COUNTER_START 0x40007CB0\r
-#define MMCR_V2P_COUNTER_START (*(VUINT32 *)(ADDR_V2P_COUNTER_START))\r
-\r
-#define ADDR_V2P_HYSTERESIS 0x40007CB4\r
-#define MMCR_V2P_HYSTERESIS (*(VUINT32 *)(ADDR_V2P_HYSTERESIS))\r
-\r
-#define ADDR_V2P_BIAS 0x40007CB8\r
-#define MMCR_V2P_BIAS (*(VUINT32 *)(ADDR_V2P_BIAS))\r
-\r
-#define ADDR_V2P_INTERRUPT_CONTROL 0x40007CBC\r
-#define MMCR_V2P_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_V2P_INTERRUPT_CONTROL))\r
-\r
-/***************************************************************\r
-* VBAT_REGS (1322)\r
-***************************************************************/\r
-#define ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS 0x4000A400\r
-#define MMCR_VBAT_POWER_FAIL_AND_RESET_STATUS (*(VUINT8 *)(ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS))\r
-\r
-#define ADDR_VBAT_CONTROL 0x4000A404\r
-#define MMCR_VBAT_CONTROL (*(VUINT8 *)(ADDR_VBAT_CONTROL))\r
-\r
-#define ADDR_VBAT_CLOCK_ENABLE 0x4000A408\r
-#define MMCR_VBAT_CLOCK_ENABLE (*(VUINT8 *)(ADDR_VBAT_CLOCK_ENABLE))\r
-\r
-/***************************************************************\r
-* EC_REG_BANK (1322)\r
-***************************************************************/\r
-#define ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS 0x4000FC04\r
-#define MMCR_EC_REG_BANK_AHB_ERROR_ADDRESS (*(VUINT32 *)(ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS))\r
-\r
-#define ADDR_EC_REG_BANK_INPUT_MUX0 0x4000FC08\r
-#define MMCR_EC_REG_BANK_INPUT_MUX0 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX0))\r
-\r
-#define ADDR_EC_REG_BANK_INPUT_MUX1 0x4000FC0C\r
-#define MMCR_EC_REG_BANK_INPUT_MUX1 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX1))\r
-\r
-#define ADDR_EC_REG_BANK_ID 0x4000FC10\r
-#define MMCR_EC_REG_BANK_ID (*(VUINT8 *)(ADDR_EC_REG_BANK_ID))\r
-\r
-#define ADDR_EC_REG_BANK_AHB_ERROR_CONTROL 0x4000FC14\r
-#define MMCR_EC_REG_BANK_AHB_ERROR_CONTROL (*(VUINT8 *)(ADDR_EC_REG_BANK_AHB_ERROR_CONTROL))\r
-\r
-#define ADDR_EC_REG_BANK_INTERRUPT_CONTROL 0x4000FC18\r
-#define MMCR_EC_REG_BANK_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_INTERRUPT_CONTROL))\r
-\r
-#define ADDR_EC_REG_BANK_ETM_TRACE 0x4000FC1C\r
-#define MMCR_EC_REG_BANK_ETM_TRACE (*(VUINT32 *)(ADDR_EC_REG_BANK_ETM_TRACE))\r
-\r
-#define ADDR_EC_REG_BANK_JTAG_ENABLE 0x4000FC20\r
-#define MMCR_EC_REG_BANK_JTAG_ENABLE (*(VUINT32 *)(ADDR_EC_REG_BANK_JTAG_ENABLE))\r
-\r
-#define ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK 0x4000FC24\r
-#define MMCR_EC_REG_BANK_PRIVATE_KEY_LOCK (*(VUINT32 *)(ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK))\r
-\r
-#define ADDR_EC_REG_BANK_WDT_COUNT 0x4000FC28\r
-#define MMCR_EC_REG_BANK_WDT_COUNT (*(VUINT32 *)(ADDR_EC_REG_BANK_WDT_COUNT))\r
-\r
-#define ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL 0x4000FC2C\r
-#define MMCR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL))\r
-\r
-#define ADDR_EC_REG_BANK_ADC_VREF_TRIM 0x4000FC30\r
-#define MMCR_EC_REG_BANK_ADC_VREF_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_TRIM))\r
-\r
-#define ADDR_EC_REG_BANK_REGULATOR_TRIM 0x4000FC34\r
-#define MMCR_EC_REG_BANK_REGULATOR_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_REGULATOR_TRIM))\r
-\r
-#define ADDR_EC_REG_BANK_ADC_VREF_PD 0x4000FC38\r
-#define MMCR_EC_REG_BANK_ADC_VREF_PD (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_PD))\r
-\r
-#define ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST 0x4000FC3C\r
-#define MMCR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST))\r
-\r
-#define ADDR_EC_REG_BANK_MISC_TRIM 0x4000FC40\r
-#define MMCR_EC_REG_BANK_MISC_TRIM (*(VUINT8 *)(ADDR_EC_REG_BANK_MISC_TRIM))\r
-\r
-/***************************************************************\r
-* PCR\r
-***************************************************************/\r
-#define ADDR_PCR_CHIP_SLEEP_ENABLE 0x40080100\r
-#define MMCR_PCR_CHIP_SLEEP_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_SLEEP_ENABLE))\r
-\r
-#define ADDR_PCR_CHIP_CLOCK_REQUIRED 0x40080104\r
-#define MMCR_PCR_CHIP_CLOCK_REQUIRED (*(VUINT32 *)(ADDR_PCR_CHIP_CLOCK_REQUIRED))\r
-\r
-#define ADDR_PCR_EC_SLEEP_ENABLES 0x40080108\r
-#define MMCR_PCR_EC_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLES))\r
-\r
-#define ADDR_PCR_EC_CLOCK_REQUIRED_STATUS 0x4008010C\r
-#define MMCR_PCR_EC_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_STATUS))\r
-\r
-#define ADDR_PCR_HOST_SLEEP_ENABLES 0x40080110\r
-#define MMCR_PCR_HOST_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_HOST_SLEEP_ENABLES))\r
-\r
-#define ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS 0x40080114\r
-#define MMCR_PCR_HOST_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS))\r
-\r
-#define ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 0x40080118\r
-#define MMCR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 (*(VUINT32 *)(ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0))\r
-\r
-#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120\r
-#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))\r
-\r
-#define ADDR_PCR_EC_SLEEP_ENABLE_2 0x40080124\r
-#define MMCR_PCR_EC_SLEEP_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLE_2))\r
-\r
-#define ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS 0x40080128\r
-#define MMCR_PCR_EC_CLOCK_REQUIRED_2_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS))\r
-\r
-#define ADDR_PCR_SLOW_CLOCK_CONTROL 0x4008012C\r
-#define MMCR_PCR_SLOW_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_SLOW_CLOCK_CONTROL))\r
-\r
-#define ADDR_PCR_OSCILLATOR_ID 0x40080130\r
-#define MMCR_PCR_OSCILLATOR_ID (*(VUINT32 *)(ADDR_PCR_OSCILLATOR_ID))\r
-\r
-#define ADDR_PCR_CHIP_RESET_ENABLE 0x40080138\r
-#define MMCR_PCR_CHIP_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_RESET_ENABLE))\r
-\r
-#define ADDR_PCR_HOST_RESET_ENABLE 0x4008013C\r
-#define MMCR_PCR_HOST_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_HOST_RESET_ENABLE))\r
-\r
-#define ADDR_PCR_EC_RESET_ENABLE 0x40080140\r
-#define MMCR_PCR_EC_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE))\r
-\r
-#define ADDR_PCR_EC_RESET_ENABLE_2 0x40080144\r
-#define MMCR_PCR_EC_RESET_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE_2))\r
-\r
-#define ADDR_PCR_CLOCK_RESET_CONTROL 0x40080148\r
-#define MMCR_PCR_CLOCK_RESET_CONTROL (*(VUINT32 *)(ADDR_PCR_CLOCK_RESET_CONTROL))\r
-\r
-/***************************************************************\r
-* Public Key Crypto Engine\r
-***************************************************************/\r
-#define ADDR_PUBLIC_PK_CONFIGREG 0x4000BD00\r
-#define MMCR_PUBLIC_PK_CONFIGREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONFIGREG))\r
-\r
-#define ADDR_PUBLIC_PK_COMMANDREG 0x4000BD04\r
-#define MMCR_PUBLIC_PK_COMMANDREG (*(VUINT32 *)(ADDR_PUBLIC_PK_COMMANDREG))\r
-\r
-#define ADDR_PUBLIC_PK_CONTROLREG 0x4000BD08\r
-#define MMCR_PUBLIC_PK_CONTROLREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONTROLREG))\r
-\r
-#define ADDR_PUBLIC_PK_STATUSREG 0x4000BD0C\r
-#define MMCR_PUBLIC_PK_STATUSREG (*(VUINT32 *)(ADDR_PUBLIC_PK_STATUSREG))\r
-\r
-#define ADDR_PUBLIC_PK_VERSIONREG 0x4000BD10\r
-#define MMCR_PUBLIC_PK_VERSIONREG (*(VUINT32 *)(ADDR_PUBLIC_PK_VERSIONREG))\r
-\r
-#define ADDR_PUBLIC_PK_LOADMICROCODEREG 0x4000BD14\r
-#define MMCR_PUBLIC_PK_LOADMICROCODEREG (*(VUINT32 *)(ADDR_PUBLIC_PK_LOADMICROCODEREG))\r
-\r
-/***************************************************************\r
-* Non Deterministic Random Number Generator\r
-***************************************************************/\r
-#define ADDR_NON_CONTROLREG 0x4000BE00\r
-#define MMCR_NON_CONTROLREG (*(VUINT32 *)(ADDR_NON_CONTROLREG))\r
-\r
-#define ADDR_NON_FIFOLEVELREG 0x4000BE04\r
-#define MMCR_NON_FIFOLEVELREG (*(VUINT32 *)(ADDR_NON_FIFOLEVELREG))\r
-\r
-#define ADDR_NON_VERSIONREG 0x4000BE08\r
-#define MMCR_NON_VERSIONREG (*(VUINT32 *)(ADDR_NON_VERSIONREG))\r
-\r
-/***************************************************************\r
-* RTC\r
-***************************************************************/\r
-#define ADDR_RTC_SECONDS 0x400F2800\r
-#define MMCR_RTC_SECONDS (*(VUINT8 *)(ADDR_RTC_SECONDS))\r
-\r
-#define ADDR_RTC_SECONDS_ALARM 0x400F2801\r
-#define MMCR_RTC_SECONDS_ALARM (*(VUINT8 *)(ADDR_RTC_SECONDS_ALARM))\r
-\r
-#define ADDR_RTC_MINUTES 0x400F2802\r
-#define MMCR_RTC_MINUTES (*(VUINT8 *)(ADDR_RTC_MINUTES))\r
-\r
-#define ADDR_RTC_MINUTES_ALARM 0x400F2803\r
-#define MMCR_RTC_MINUTES_ALARM (*(VUINT8 *)(ADDR_RTC_MINUTES_ALARM))\r
-\r
-#define ADDR_RTC_HOURS 0x400F2804\r
-#define MMCR_RTC_HOURS (*(VUINT8 *)(ADDR_RTC_HOURS))\r
-\r
-#define ADDR_RTC_HOURS_ALARM 0x400F2805\r
-#define MMCR_RTC_HOURS_ALARM (*(VUINT8 *)(ADDR_RTC_HOURS_ALARM))\r
-\r
-#define ADDR_RTC_DAY_OF_WEEK 0x400F2806\r
-#define MMCR_RTC_DAY_OF_WEEK (*(VUINT8 *)(ADDR_RTC_DAY_OF_WEEK))\r
-\r
-#define ADDR_RTC_DAY_OF_MONTH 0x400F2807\r
-#define MMCR_RTC_DAY_OF_MONTH (*(VUINT8 *)(ADDR_RTC_DAY_OF_MONTH))\r
-\r
-#define ADDR_RTC_MONTH 0x400F2808\r
-#define MMCR_RTC_MONTH (*(VUINT8 *)(ADDR_RTC_MONTH))\r
-\r
-#define ADDR_RTC_YEAR 0x400F2809\r
-#define MMCR_RTC_YEAR (*(VUINT8 *)(ADDR_RTC_YEAR))\r
-\r
-#define ADDR_RTC_A 0x400F280A\r
-#define MMCR_RTC_A (*(VUINT8 *)(ADDR_RTC_A))\r
-\r
-#define ADDR_RTC_B 0x400F280B\r
-#define MMCR_RTC_B (*(VUINT8 *)(ADDR_RTC_B))\r
-\r
-#define ADDR_RTC_C 0x400F280C\r
-#define MMCR_RTC_C (*(VUINT8 *)(ADDR_RTC_C))\r
-\r
-#define ADDR_RTC_D 0x400F280D\r
-#define MMCR_RTC_D (*(VUINT8 *)(ADDR_RTC_D))\r
-\r
-#define ADDR_RTC_CONTROL 0x400F2810\r
-#define MMCR_RTC_CONTROL (*(VUINT8 *)(ADDR_RTC_CONTROL))\r
-\r
-#define ADDR_RTC_WEEK_ALARM 0x400F2814\r
-#define MMCR_RTC_WEEK_ALARM (*(VUINT8 *)(ADDR_RTC_WEEK_ALARM))\r
-\r
-#define ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD 0x400F2818\r
-#define MMCR_RTC_DAYLIGHT_SAVINGS_FORWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD))\r
-\r
-#define ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD 0x400F281C\r
-#define MMCR_RTC_DAYLIGHT_SAVINGS_BACKWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD))\r
-\r
-#define ADDR_RTC_TEST_MODE 0x400F2820\r
-#define MMCR_RTC_TEST_MODE (*(VUINT8 *)(ADDR_RTC_TEST_MODE))\r
-\r
-/***************************************************************\r
-* Analog to Digital Converter (ADC)\r
-***************************************************************/\r
-#define ADDR_ADC_CONTROL 0x40007C00\r
-#define MMCR_ADC_CONTROL (*(VUINT32 *)(ADDR_ADC_CONTROL))\r
-\r
-#define ADDR_ADC_DELAY 0x40007C04\r
-#define MMCR_ADC_DELAY (*(VUINT32 *)(ADDR_ADC_DELAY))\r
-\r
-#define ADDR_ADC_STATUS 0x40007C08\r
-#define MMCR_ADC_STATUS (*(VUINT32 *)(ADDR_ADC_STATUS))\r
-\r
-#define ADDR_ADC_SINGLE 0x40007C0C\r
-#define MMCR_ADC_SINGLE (*(VUINT32 *)(ADDR_ADC_SINGLE))\r
-\r
-#define ADDR_ADC_REPEAT 0x40007C10\r
-#define MMCR_ADC_REPEAT (*(VUINT32 *)(ADDR_ADC_REPEAT))\r
-\r
-#define ADDR_ADC_CHANNEL_0_READINGS 0x40007C14\r
-#define MMCR_ADC_CHANNEL_0_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_0_READINGS))\r
-\r
-#define ADDR_ADC_CHANNEL_1_READINGS 0x40007C18\r
-#define MMCR_ADC_CHANNEL_1_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_1_READINGS))\r
-\r
-#define ADDR_ADC_CHANNEL_2_READINGS 0x40007C1C\r
-#define MMCR_ADC_CHANNEL_2_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_2_READINGS))\r
-\r
-#define ADDR_ADC_CHANNEL_3_READINGS 0x40007C20\r
-#define MMCR_ADC_CHANNEL_3_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_3_READINGS))\r
-\r
-#define ADDR_ADC_CHANNEL_4_READINGS 0x40007C24\r
-#define MMCR_ADC_CHANNEL_4_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_4_READINGS))\r
-\r
-#define ADDR_ADC_DEBUG_FPGA_TEST_MODE 0x40007C54\r
-#define MMCR_ADC_DEBUG_FPGA_TEST_MODE (*(VUINT32 *)(ADDR_ADC_DEBUG_FPGA_TEST_MODE))\r
-\r
-#define ADDR_ADC_TEST 0x40007C78\r
-#define MMCR_ADC_TEST (*(VUINT32 *)(ADDR_ADC_TEST))\r
-\r
-#define ADDR_ADC_CONFIGURATION 0x40007C7C\r
-#define MMCR_ADC_CONFIGURATION (*(VUINT32 *)(ADDR_ADC_CONFIGURATION))\r
-\r
-/***************************************************************\r
-* eFUSE\r
-***************************************************************/\r
-#define ADDR_EFUSE_CONTROL 0x40082000\r
-#define MMCR_EFUSE_CONTROL (*(VUINT8 *)(ADDR_EFUSE_CONTROL))\r
-\r
-#define ADDR_EFUSE_MANUAL_CONTROL 0x40082004\r
-#define MMCR_EFUSE_MANUAL_CONTROL (*(VUINT8 *)(ADDR_EFUSE_MANUAL_CONTROL))\r
-\r
-#define ADDR_EFUSE_MANUAL_MODE_ADDRESS 0x40082006\r
-#define MMCR_EFUSE_MANUAL_MODE_ADDRESS (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_ADDRESS))\r
-\r
-#define ADDR_EFUSE_MANUAL_MODE_DATA 0x4008200C\r
-#define MMCR_EFUSE_MANUAL_MODE_DATA (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_DATA))\r
-\r
-/***************************************************************\r
-* AES Crypto Engine & Hash Function\r
-***************************************************************/\r
-#define ADDR_AES_CONFIGREG 0x4000D200\r
-#define MMCR_AES_CONFIGREG (*(VUINT32 *)(ADDR_AES_CONFIGREG))\r
-\r
-#define ADDR_AES_COMMANDREG 0x4000D204\r
-#define MMCR_AES_COMMANDREG (*(VUINT32 *)(ADDR_AES_COMMANDREG))\r
-\r
-#define ADDR_AES_CONTROLREG 0x4000D208\r
-#define MMCR_AES_CONTROLREG (*(VUINT32 *)(ADDR_AES_CONTROLREG))\r
-\r
-#define ADDR_AES_STATUSREG 0x4000D20C\r
-#define MMCR_AES_STATUSREG (*(VUINT32 *)(ADDR_AES_STATUSREG))\r
-\r
-#define ADDR_AES_VERSIONREG 0x4000D210\r
-#define MMCR_AES_VERSIONREG (*(VUINT32 *)(ADDR_AES_VERSIONREG))\r
-\r
-#define ADDR_AES_NBHEADERREG 0x4000D214\r
-#define MMCR_AES_NBHEADERREG (*(VUINT32 *)(ADDR_AES_NBHEADERREG))\r
-\r
-#define ADDR_AES_LASTHEADERREG 0x4000D218\r
-#define MMCR_AES_LASTHEADERREG (*(VUINT32 *)(ADDR_AES_LASTHEADERREG))\r
-\r
-#define ADDR_AES_NBBLOCKREG 0x4000D21C\r
-#define MMCR_AES_NBBLOCKREG (*(VUINT32 *)(ADDR_AES_NBBLOCKREG))\r
-\r
-#define ADDR_AES_LASTBLOCKREG 0x4000D220\r
-#define MMCR_AES_LASTBLOCKREG (*(VUINT32 *)(ADDR_AES_LASTBLOCKREG))\r
-\r
-#define ADDR_AES_DMAINREG 0x4000D224\r
-#define MMCR_AES_DMAINREG (*(VUINT32 *)(ADDR_AES_DMAINREG))\r
-\r
-#define ADDR_AES_DMAOUTREG 0x4000D228\r
-#define MMCR_AES_DMAOUTREG (*(VUINT32 *)(ADDR_AES_DMAOUTREG))\r
-\r
-#define ADDR_AES_SHAMODE_REGISTER 0x4000D000\r
-#define MMCR_AES_SHAMODE_REGISTER (*(VUINT32 *)(ADDR_AES_SHAMODE_REGISTER))\r
-\r
-#define ADDR_AES_NBBLOCK_REGISTER 0x4000D004\r
-#define MMCR_AES_NBBLOCK_REGISTER (*(VUINT32 *)(ADDR_AES_NBBLOCK_REGISTER))\r
-\r
-#define ADDR_AES_CONTROL 0x4000D008\r
-#define MMCR_AES_CONTROL (*(VUINT32 *)(ADDR_AES_CONTROL))\r
-\r
-#define ADDR_AES_STATUS 0x4000D00C\r
-#define MMCR_AES_STATUS (*(VUINT32 *)(ADDR_AES_STATUS))\r
-\r
-#define ADDR_AES_VERSION 0x4000D010\r
-#define MMCR_AES_VERSION (*(VUINT32 *)(ADDR_AES_VERSION))\r
-\r
-#define ADDR_AES_GENERICVALUE_REGISTER 0x4000D014\r
-#define MMCR_AES_GENERICVALUE_REGISTER (*(VUINT32 *)(ADDR_AES_GENERICVALUE_REGISTER))\r
-\r
-#define ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS 0x4000D018\r
-#define MMCR_AES_INITIAL_HASH_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS))\r
-\r
-#define ADDR_AES_DATA_SOURCE_ADDRESS 0x4000D01C\r
-#define MMCR_AES_DATA_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_DATA_SOURCE_ADDRESS))\r
-\r
-#define ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS 0x4000D020\r
-#define MMCR_AES_HASH_RESULT_DESTINATION_ADDRESS (*(VUINT32 *)(ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS))\r
-\r
-/***************************************************************\r
-* LPC\r
-***************************************************************/\r
-#define ADDR_LPC_ACTIVATE 0x400F3330\r
-#define MMCR_LPC_ACTIVATE (*(VUINT8 *)(ADDR_LPC_ACTIVATE))\r
-\r
-#define ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION 0x400F3340\r
-#define MMCR_LPC_SIRQ0_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION 0x400F3341\r
-#define MMCR_LPC_SIRQ1_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION 0x400F3342\r
-#define MMCR_LPC_SIRQ2_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION 0x400F3343\r
-#define MMCR_LPC_SIRQ3_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION 0x400F3344\r
-#define MMCR_LPC_SIRQ4_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION 0x400F3345\r
-#define MMCR_LPC_SIRQ5_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION 0x400F3346\r
-#define MMCR_LPC_SIRQ6_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION 0x400F3347\r
-#define MMCR_LPC_SIRQ7_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION 0x400F3348\r
-#define MMCR_LPC_SIRQ8_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION 0x400F3349\r
-#define MMCR_LPC_SIRQ9_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION 0x400F334A\r
-#define MMCR_LPC_SIRQ10_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION 0x400F334B\r
-#define MMCR_LPC_SIRQ11_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION 0x400F334C\r
-#define MMCR_LPC_SIRQ12_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION 0x400F334D\r
-#define MMCR_LPC_SIRQ13_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION 0x400F334E\r
-#define MMCR_LPC_SIRQ14_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION 0x400F334F\r
-#define MMCR_LPC_SIRQ15_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_INTERFACE_BAR 0x400F3360\r
-#define MMCR_LPC_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_INTERFACE_BAR))\r
-\r
-#define ADDR_LPC_EM_INTERFACE_0_BAR 0x400F3364\r
-#define MMCR_LPC_EM_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_EM_INTERFACE_0_BAR))\r
-\r
-#define ADDR_LPC_UART_0_BAR 0x400F3368\r
-#define MMCR_LPC_UART_0_BAR (*(VUINT32 *)(ADDR_LPC_UART_0_BAR))\r
-\r
-#define ADDR_LPC_KEYBOARD_CONTROLLER_BAR 0x400F3378\r
-#define MMCR_LPC_KEYBOARD_CONTROLLER_BAR (*(VUINT32 *)(ADDR_LPC_KEYBOARD_CONTROLLER_BAR))\r
-\r
-#define ADDR_LPC_ACPI_EC_INTERFACE_0_BAR 0x400F3388\r
-#define MMCR_LPC_ACPI_EC_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_0_BAR))\r
-\r
-#define ADDR_LPC_ACPI_EC_INTERFACE_1_BAR 0x400F338C\r
-#define MMCR_LPC_ACPI_EC_INTERFACE_1_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_1_BAR))\r
-\r
-#define ADDR_LPC_ACPI_PM1_INTERFACE_BAR 0x400F3390\r
-#define MMCR_LPC_ACPI_PM1_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_PM1_INTERFACE_BAR))\r
-\r
-#define ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR 0x400F3394\r
-#define MMCR_LPC_LEGACY_GATEA20_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR))\r
-\r
-#define ADDR_LPC_MAILBOXS_INTERFACE_BAR 0x400F3398\r
-#define MMCR_LPC_MAILBOXS_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_MAILBOXS_INTERFACE_BAR))\r
-\r
-#define ADDR_LPC_BUS_MONITOR 0x400F3104\r
-#define MMCR_LPC_BUS_MONITOR (*(VUINT32 *)(ADDR_LPC_BUS_MONITOR))\r
-\r
-#define ADDR_LPC_HOST_BUS_ERROR 0x400F3108\r
-#define MMCR_LPC_HOST_BUS_ERROR (*(VUINT32 *)(ADDR_LPC_HOST_BUS_ERROR))\r
-\r
-#define ADDR_LPC_EC_SERIRQ 0x400F310C\r
-#define MMCR_LPC_EC_SERIRQ (*(VUINT32 *)(ADDR_LPC_EC_SERIRQ))\r
-\r
-#define ADDR_LPC_EC_CLOCK_CONTROL 0x400F3110\r
-#define MMCR_LPC_EC_CLOCK_CONTROL (*(VUINT32 *)(ADDR_LPC_EC_CLOCK_CONTROL))\r
-\r
-#define ADDR_LPC_BAR_INHIBIT 0x400F3120\r
-#define MMCR_LPC_BAR_INHIBIT (*(VUINT32 *)(ADDR_LPC_BAR_INHIBIT))\r
-\r
-#define ADDR_LPC_BAR_INIT 0x400F3130\r
-#define MMCR_LPC_BAR_INIT (*(VUINT16 *)(ADDR_LPC_BAR_INIT))\r
-\r
-#define ADDR_LPC_MEMORY_HOST_CONFIGURATION 0x400F31FC\r
-#define MMCR_LPC_MEMORY_HOST_CONFIGURATION (*(VUINT32 *)(ADDR_LPC_MEMORY_HOST_CONFIGURATION))\r
-\r
-/***************************************************************\r
-* GPIO\r
-***************************************************************/\r
-#define ADDR_GPIO000_PIN_CONTROL 0x40081000\r
-#define MMCR_GPIO000_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO001_PIN_CONTROL 0x40081004\r
-#define MMCR_GPIO001_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO002_PIN_CONTROL 0x40081008\r
-#define MMCR_GPIO002_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO003_PIN_CONTROL 0x4008100C\r
-#define MMCR_GPIO003_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO004_PIN_CONTROL 0x40081010\r
-#define MMCR_GPIO004_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO005_PIN_CONTROL 0x40081014\r
-#define MMCR_GPIO005_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO006_PIN_CONTROL 0x40081018\r
-#define MMCR_GPIO006_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO007_PIN_CONTROL 0x4008101C\r
-#define MMCR_GPIO007_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO010_PIN_CONTROL 0x40081020\r
-#define MMCR_GPIO010_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO011_PIN_CONTROL 0x40081024\r
-#define MMCR_GPIO011_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO012_PIN_CONTROL 0x40081028\r
-#define MMCR_GPIO012_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO013_PIN_CONTROL 0x4008102C\r
-#define MMCR_GPIO013_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO014_PIN_CONTROL 0x40081030\r
-#define MMCR_GPIO014_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO015_PIN_CONTROL 0x40081034\r
-#define MMCR_GPIO015_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO016_PIN_CONTROL 0x40081038\r
-#define MMCR_GPIO016_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO017_PIN_CONTROL 0x4008103C\r
-#define MMCR_GPIO017_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO020_PIN_CONTROL 0x40081040\r
-#define MMCR_GPIO020_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO021_PIN_CONTROL 0x40081044\r
-#define MMCR_GPIO021_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO022_PIN_CONTROL 0x40081048\r
-#define MMCR_GPIO022_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO023_PIN_CONTROL 0x4008104C\r
-#define MMCR_GPIO023_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO024_PIN_CONTROL 0x40081050\r
-#define MMCR_GPIO024_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO025_PIN_CONTROL 0x40081054\r
-#define MMCR_GPIO025_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO026_PIN_CONTROL 0x40081058\r
-#define MMCR_GPIO026_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO027_PIN_CONTROL 0x4008105C\r
-#define MMCR_GPIO027_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO030_PIN_CONTROL 0x40081060\r
-#define MMCR_GPIO030_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO031_PIN_CONTROL 0x40081064\r
-#define MMCR_GPIO031_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO032_PIN_CONTROL 0x40081068\r
-#define MMCR_GPIO032_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO033_PIN_CONTROL 0x4008106C\r
-#define MMCR_GPIO033_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO034_PIN_CONTROL 0x40081070\r
-#define MMCR_GPIO034_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO035_PIN_CONTROL 0x40081074\r
-#define MMCR_GPIO035_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO036_PIN_CONTROL 0x40081078\r
-#define MMCR_GPIO036_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO040_PIN_CONTROL 0x40081080\r
-#define MMCR_GPIO040_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO041_PIN_CONTROL 0x40081084\r
-#define MMCR_GPIO041_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO042_PIN_CONTROL 0x40081088\r
-#define MMCR_GPIO042_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO043_PIN_CONTROL 0x4008108C\r
-#define MMCR_GPIO043_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO044_PIN_CONTROL 0x40081090\r
-#define MMCR_GPIO044_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO045_PIN_CONTROL 0x40081094\r
-#define MMCR_GPIO045_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO046_PIN_CONTROL 0x40081098\r
-#define MMCR_GPIO046_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO047_PIN_CONTROL 0x4008109C\r
-#define MMCR_GPIO047_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO050_PIN_CONTROL 0x400810A0\r
-#define MMCR_GPIO050_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO051_PIN_CONTROL 0x400810A4\r
-#define MMCR_GPIO051_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO052_PIN_CONTROL 0x400810A8\r
-#define MMCR_GPIO052_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO053_PIN_CONTROL 0x400810AC\r
-#define MMCR_GPIO053_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO054_PIN_CONTROL 0x400810B0\r
-#define MMCR_GPIO054_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO055_PIN_CONTROL 0x400810B4\r
-#define MMCR_GPIO055_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO056_PIN_CONTROL 0x400810B8\r
-#define MMCR_GPIO056_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO057_PIN_CONTROL 0x400810BC\r
-#define MMCR_GPIO057_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO060_PIN_CONTROL 0x400810C0\r
-#define MMCR_GPIO060_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO061_PIN_CONTROL 0x400810C4\r
-#define MMCR_GPIO061_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO062_PIN_CONTROL 0x400810C8\r
-#define MMCR_GPIO062_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO063_PIN_CONTROL 0x400810CC\r
-#define MMCR_GPIO063_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO064_PIN_CONTROL 0x400810D0\r
-#define MMCR_GPIO064_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO065_PIN_CONTROL 0x400810D4\r
-#define MMCR_GPIO065_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO066_PIN_CONTROL 0x400810D8\r
-#define MMCR_GPIO066_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO067_PIN_CONTROL 0x400810DC\r
-#define MMCR_GPIO067_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO100_PIN_CONTROL 0x40081100\r
-#define MMCR_GPIO100_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO101_PIN_CONTROL 0x40081104\r
-#define MMCR_GPIO101_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO102_PIN_CONTROL 0x40081108\r
-#define MMCR_GPIO102_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO103_PIN_CONTROL 0x4008110C\r
-#define MMCR_GPIO103_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO104_PIN_CONTROL 0x40081110\r
-#define MMCR_GPIO104_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO105_PIN_CONTROL 0x40081114\r
-#define MMCR_GPIO105_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO106_PIN_CONTROL 0x40081118\r
-#define MMCR_GPIO106_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO107_PIN_CONTROL 0x4008111C\r
-#define MMCR_GPIO107_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO110_PIN_CONTROL 0x40081120\r
-#define MMCR_GPIO110_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO111_PIN_CONTROL 0x40081124\r
-#define MMCR_GPIO111_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO112_PIN_CONTROL 0x40081128\r
-#define MMCR_GPIO112_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO113_PIN_CONTROL 0x4008112C\r
-#define MMCR_GPIO113_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO114_PIN_CONTROL 0x40081130\r
-#define MMCR_GPIO114_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO115_PIN_CONTROL 0x40081134\r
-#define MMCR_GPIO115_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO116_PIN_CONTROL 0x40081138\r
-#define MMCR_GPIO116_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO117_PIN_CONTROL 0x4008113C\r
-#define MMCR_GPIO117_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO120_PIN_CONTROL 0x40081140\r
-#define MMCR_GPIO120_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO121_PIN_CONTROL 0x40081144\r
-#define MMCR_GPIO121_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO122_PIN_CONTROL 0x40081148\r
-#define MMCR_GPIO122_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO123_PIN_CONTROL 0x4008114C\r
-#define MMCR_GPIO123_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO124_PIN_CONTROL 0x40081150\r
-#define MMCR_GPIO124_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO125_PIN_CONTROL 0x40081154\r
-#define MMCR_GPIO125_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO126_PIN_CONTROL 0x40081158\r
-#define MMCR_GPIO126_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO127_PIN_CONTROL 0x4008115C\r
-#define MMCR_GPIO127_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO130_PIN_CONTROL 0x40081160\r
-#define MMCR_GPIO130_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO131_PIN_CONTROL 0x40081164\r
-#define MMCR_GPIO131_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO132_PIN_CONTROL 0x40081168\r
-#define MMCR_GPIO132_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO133_PIN_CONTROL 0x4008116C\r
-#define MMCR_GPIO133_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO134_PIN_CONTROL 0x40081170\r
-#define MMCR_GPIO134_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO135_PIN_CONTROL 0x40081174\r
-#define MMCR_GPIO135_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO136_PIN_CONTROL 0x40081178\r
-#define MMCR_GPIO136_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO140_PIN_CONTROL 0x40081180\r
-#define MMCR_GPIO140_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO141_PIN_CONTROL 0x40081184\r
-#define MMCR_GPIO141_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO142_PIN_CONTROL 0x40081188\r
-#define MMCR_GPIO142_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO143_PIN_CONTROL 0x4008118C\r
-#define MMCR_GPIO143_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO144_PIN_CONTROL 0x40081190\r
-#define MMCR_GPIO144_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO145_PIN_CONTROL 0x40081194\r
-#define MMCR_GPIO145_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO146_PIN_CONTROL 0x40081198\r
-#define MMCR_GPIO146_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO147_PIN_CONTROL 0x4008119C\r
-#define MMCR_GPIO147_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO150_PIN_CONTROL 0x400811A0\r
-#define MMCR_GPIO150_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO151_PIN_CONTROL 0x400811A4\r
-#define MMCR_GPIO151_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO152_PIN_CONTROL 0x400811A8\r
-#define MMCR_GPIO152_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO153_PIN_CONTROL 0x400811AC\r
-#define MMCR_GPIO153_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO154_PIN_CONTROL 0x400811B0\r
-#define MMCR_GPIO154_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO155_PIN_CONTROL 0x400811B4\r
-#define MMCR_GPIO155_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO156_PIN_CONTROL 0x400811B8\r
-#define MMCR_GPIO156_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO157_PIN_CONTROL 0x400811BC\r
-#define MMCR_GPIO157_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO160_PIN_CONTROL 0x400811C0\r
-#define MMCR_GPIO160_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO161_PIN_CONTROL 0x400811C4\r
-#define MMCR_GPIO161_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO162_PIN_CONTROL 0x400811C8\r
-#define MMCR_GPIO162_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO163_PIN_CONTROL 0x400811CC\r
-#define MMCR_GPIO163_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO164_PIN_CONTROL 0x400811D0\r
-#define MMCR_GPIO164_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO165_PIN_CONTROL 0x400811D4\r
-#define MMCR_GPIO165_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO200_PIN_CONTROL 0x40081200\r
-#define MMCR_GPIO200_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO201_PIN_CONTROL 0x40081204\r
-#define MMCR_GPIO201_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO202_PIN_CONTROL 0x40081208\r
-#define MMCR_GPIO202_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO203_PIN_CONTROL 0x4008120C\r
-#define MMCR_GPIO203_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO204_PIN_CONTROL 0x40081210\r
-#define MMCR_GPIO204_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO206_PIN_CONTROL 0x40081218\r
-#define MMCR_GPIO206_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO210_PIN_CONTROL 0x40081220\r
-#define MMCR_GPIO210_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO211_PIN_CONTROL 0x40081224\r
-#define MMCR_GPIO211_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO212_PIN_CONTROL 0x40081228\r
-#define MMCR_GPIO212_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO213_PIN_CONTROL 0x4008122C\r
-#define MMCR_GPIO213_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_000_036 0x40081280\r
-#define MMCR_GPIO_OUTPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_000_036))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_040_076 0x40081284\r
-#define MMCR_GPIO_OUTPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_040_076))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_100_136 0x40081288\r
-#define MMCR_GPIO_OUTPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_100_136))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_140_176 0x4008128C\r
-#define MMCR_GPIO_OUTPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_140_176))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_200_236 0x40081290\r
-#define MMCR_GPIO_OUTPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_200_236))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_000_036 0x40081300\r
-#define MMCR_GPIO_INPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_000_036))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_040_076 0x40081304\r
-#define MMCR_GPIO_INPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_040_076))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_100_136 0x40081308\r
-#define MMCR_GPIO_INPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_100_136))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_140_176 0x4008130C\r
-#define MMCR_GPIO_INPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_140_176))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_200_236 0x40081310\r
-#define MMCR_GPIO_INPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_200_236))\r
-\r
-#define ADDR_GPIO_LOCK_4 0x400813EC\r
-#define MMCR_GPIO_LOCK_4 (*(VUINT32 *)(ADDR_GPIO_LOCK_4))\r
-\r
-#define ADDR_GPIO_LOCK_3 0x400813F0\r
-#define MMCR_GPIO_LOCK_3 (*(VUINT32 *)(ADDR_GPIO_LOCK_3))\r
-\r
-#define ADDR_GPIO_LOCK_2 0x400813F4\r
-#define MMCR_GPIO_LOCK_2 (*(VUINT32 *)(ADDR_GPIO_LOCK_2))\r
-\r
-#define ADDR_GPIO_LOCK_1 0x400813F8\r
-#define MMCR_GPIO_LOCK_1 (*(VUINT32 *)(ADDR_GPIO_LOCK_1))\r
-\r
-#define ADDR_GPIO_LOCK_0 0x400813FC\r
-#define MMCR_GPIO_LOCK_0 (*(VUINT32 *)(ADDR_GPIO_LOCK_0))\r
-\r
-#define ADDR_GPIO000_PIN_CONTROL_2 0x40081500\r
-#define MMCR_GPIO000_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO001_PIN_CONTROL_2 0x40081504\r
-#define MMCR_GPIO001_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO002_PIN_CONTROL_2 0x40081508\r
-#define MMCR_GPIO002_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO003_PIN_CONTROL_2 0x4008150C\r
-#define MMCR_GPIO003_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO004_PIN_CONTROL_2 0x40081510\r
-#define MMCR_GPIO004_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO005_PIN_CONTROL_2 0x40081514\r
-#define MMCR_GPIO005_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO006_PIN_CONTROL_2 0x40081518\r
-#define MMCR_GPIO006_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO007_PIN_CONTROL_2 0x4008151C\r
-#define MMCR_GPIO007_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO010_PIN_CONTROL_2 0x40081520\r
-#define MMCR_GPIO010_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO011_PIN_CONTROL_2 0x40081524\r
-#define MMCR_GPIO011_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO012_PIN_CONTROL_2 0x40081528\r
-#define MMCR_GPIO012_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO013_PIN_CONTROL_2 0x4008152C\r
-#define MMCR_GPIO013_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO014_PIN_CONTROL_2 0x40081530\r
-#define MMCR_GPIO014_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO015_PIN_CONTROL_2 0x40081534\r
-#define MMCR_GPIO015_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO016_PIN_CONTROL_2 0x40081538\r
-#define MMCR_GPIO016_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO017_PIN_CONTROL_2 0x4008153C\r
-#define MMCR_GPIO017_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO020_PIN_CONTROL_2 0x40081540\r
-#define MMCR_GPIO020_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO021_PIN_CONTROL_2 0x40081544\r
-#define MMCR_GPIO021_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO022_PIN_CONTROL_2 0x40081548\r
-#define MMCR_GPIO022_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO023_PIN_CONTROL_2 0x4008154C\r
-#define MMCR_GPIO023_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO024_PIN_CONTROL_2 0x40081550\r
-#define MMCR_GPIO024_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO025_PIN_CONTROL_2 0x40081554\r
-#define MMCR_GPIO025_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO026_PIN_CONTROL_2 0x40081558\r
-#define MMCR_GPIO026_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO027_PIN_CONTROL_2 0x4008155C\r
-#define MMCR_GPIO027_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO030_PIN_CONTROL_2 0x40081560\r
-#define MMCR_GPIO030_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO031_PIN_CONTROL_2 0x40081564\r
-#define MMCR_GPIO031_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO032_PIN_CONTROL_2 0x40081568\r
-#define MMCR_GPIO032_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO033_PIN_CONTROL_2 0x4008156C\r
-#define MMCR_GPIO033_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO034_PIN_CONTROL_2 0x40081570\r
-#define MMCR_GPIO034_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO035_PIN_CONTROL_2 0x40081574\r
-#define MMCR_GPIO035_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO036_PIN_CONTROL_2 0x40081578\r
-#define MMCR_GPIO036_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO040_PIN_CONTROL_2 0x40081580\r
-#define MMCR_GPIO040_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO041_PIN_CONTROL_2 0x40081584\r
-#define MMCR_GPIO041_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO042_PIN_CONTROL_2 0x40081588\r
-#define MMCR_GPIO042_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO043_PIN_CONTROL_2 0x4008158C\r
-#define MMCR_GPIO043_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO044_PIN_CONTROL_2 0x40081590\r
-#define MMCR_GPIO044_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO045_PIN_CONTROL_2 0x40081594\r
-#define MMCR_GPIO045_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO046_PIN_CONTROL_2 0x40081598\r
-#define MMCR_GPIO046_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO047_PIN_CONTROL_2 0x4008159C\r
-#define MMCR_GPIO047_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO050_PIN_CONTROL_2 0x400815A0\r
-#define MMCR_GPIO050_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO051_PIN_CONTROL_2 0x400815A4\r
-#define MMCR_GPIO051_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO052_PIN_CONTROL_2 0x400815A8\r
-#define MMCR_GPIO052_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO053_PIN_CONTROL_2 0x400815AC\r
-#define MMCR_GPIO053_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO054_PIN_CONTROL_2 0x400815B0\r
-#define MMCR_GPIO054_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO055_PIN_CONTROL_2 0x400815B4\r
-#define MMCR_GPIO055_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO056_PIN_CONTROL_2 0x400815B8\r
-#define MMCR_GPIO056_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO057_PIN_CONTROL_2 0x400815BC\r
-#define MMCR_GPIO057_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO060_PIN_CONTROL_2 0x400815C0\r
-#define MMCR_GPIO060_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO061_PIN_CONTROL_2 0x400815C4\r
-#define MMCR_GPIO061_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO062_PIN_CONTROL_2 0x400815C8\r
-#define MMCR_GPIO062_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO063_PIN_CONTROL_2 0x400815CC\r
-#define MMCR_GPIO063_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO064_PIN_CONTROL_2 0x400815D0\r
-#define MMCR_GPIO064_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO065_PIN_CONTROL_2 0x400815D4\r
-#define MMCR_GPIO065_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO066_PIN_CONTROL_2 0x400815D8\r
-#define MMCR_GPIO066_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO067_PIN_CONTROL_2 0x400815DC\r
-#define MMCR_GPIO067_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO100_PIN_CONTROL_2 0x400815E0\r
-#define MMCR_GPIO100_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO101_PIN_CONTROL_2 0x400815E4\r
-#define MMCR_GPIO101_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO102_PIN_CONTROL_2 0x400815E8\r
-#define MMCR_GPIO102_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO103_PIN_CONTROL_2 0x400815EC\r
-#define MMCR_GPIO103_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO104_PIN_CONTROL_2 0x400815F0\r
-#define MMCR_GPIO104_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO105_PIN_CONTROL_2 0x400815F4\r
-#define MMCR_GPIO105_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO106_PIN_CONTROL_2 0x400815F8\r
-#define MMCR_GPIO106_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO107_PIN_CONTROL_2 0x400815FC\r
-#define MMCR_GPIO107_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO110_PIN_CONTROL_2 0x40081600\r
-#define MMCR_GPIO110_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO111_PIN_CONTROL_2 0x40081604\r
-#define MMCR_GPIO111_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO112_PIN_CONTROL_2 0x40081608\r
-#define MMCR_GPIO112_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO113_PIN_CONTROL_2 0x4008160C\r
-#define MMCR_GPIO113_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO114_PIN_CONTROL_2 0x40081610\r
-#define MMCR_GPIO114_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO115_PIN_CONTROL_2 0x40081614\r
-#define MMCR_GPIO115_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO116_PIN_CONTROL_2 0x40081618\r
-#define MMCR_GPIO116_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO117_PIN_CONTROL_2 0x4008161C\r
-#define MMCR_GPIO117_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO120_PIN_CONTROL_2 0x40081620\r
-#define MMCR_GPIO120_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO121_PIN_CONTROL_2 0x40081624\r
-#define MMCR_GPIO121_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO122_PIN_CONTROL_2 0x40081628\r
-#define MMCR_GPIO122_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO123_PIN_CONTROL_2 0x4008162C\r
-#define MMCR_GPIO123_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO124_PIN_CONTROL_2 0x40081630\r
-#define MMCR_GPIO124_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO125_PIN_CONTROL_2 0x40081634\r
-#define MMCR_GPIO125_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO126_PIN_CONTROL_2 0x40081638\r
-#define MMCR_GPIO126_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO127_PIN_CONTROL_2 0x4008163C\r
-#define MMCR_GPIO127_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO130_PIN_CONTROL_2 0x40081640\r
-#define MMCR_GPIO130_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO131_PIN_CONTROL_2 0x40081644\r
-#define MMCR_GPIO131_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO132_PIN_CONTROL_2 0x40081648\r
-#define MMCR_GPIO132_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO133_PIN_CONTROL_2 0x4008164C\r
-#define MMCR_GPIO133_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO134_PIN_CONTROL_2 0x40081650\r
-#define MMCR_GPIO134_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO135_PIN_CONTROL_2 0x40081654\r
-#define MMCR_GPIO135_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO136_PIN_CONTROL_2 0x40081658\r
-#define MMCR_GPIO136_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO140_PIN_CONTROL_2 0x40081660\r
-#define MMCR_GPIO140_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO141_PIN_CONTROL_2 0x40081664\r
-#define MMCR_GPIO141_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO142_PIN_CONTROL_2 0x40081668\r
-#define MMCR_GPIO142_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO143_PIN_CONTROL_2 0x4008166C\r
-#define MMCR_GPIO143_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO144_PIN_CONTROL_2 0x40081670\r
-#define MMCR_GPIO144_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO145_PIN_CONTROL_2 0x40081674\r
-#define MMCR_GPIO145_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO146_PIN_CONTROL_2 0x40081678\r
-#define MMCR_GPIO146_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO147_PIN_CONTROL_2 0x4008167C\r
-#define MMCR_GPIO147_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO150_PIN_CONTROL_2 0x40081680\r
-#define MMCR_GPIO150_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO151_PIN_CONTROL_2 0x40081684\r
-#define MMCR_GPIO151_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO152_PIN_CONTROL_2 0x40081688\r
-#define MMCR_GPIO152_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO153_PIN_CONTROL_2 0x4008168C\r
-#define MMCR_GPIO153_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO154_PIN_CONTROL_2 0x40081690\r
-#define MMCR_GPIO154_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO155_PIN_CONTROL_2 0x40081694\r
-#define MMCR_GPIO155_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO156_PIN_CONTROL_2 0x40081698\r
-#define MMCR_GPIO156_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO157_PIN_CONTROL_2 0x4008169C\r
-#define MMCR_GPIO157_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO160_PIN_CONTROL_2 0x400816A0\r
-#define MMCR_GPIO160_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO161_PIN_CONTROL_2 0x400816A4\r
-#define MMCR_GPIO161_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO162_PIN_CONTROL_2 0x400816A8\r
-#define MMCR_GPIO162_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO163_PIN_CONTROL_2 0x400816AC\r
-#define MMCR_GPIO163_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO164_PIN_CONTROL_2 0x400816B0\r
-#define MMCR_GPIO164_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO165_PIN_CONTROL_2 0x400816B4\r
-#define MMCR_GPIO165_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO200_PIN_CONTROL_2 0x40081720\r
-#define MMCR_GPIO200_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO201_PIN_CONTROL_2 0x40081724\r
-#define MMCR_GPIO201_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO202_PIN_CONTROL_2 0x40081728\r
-#define MMCR_GPIO202_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO203_PIN_CONTROL_2 0x4008172C\r
-#define MMCR_GPIO203_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO204_PIN_CONTROL_2 0x40081730\r
-#define MMCR_GPIO204_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO206_PIN_CONTROL_2 0x40081738\r
-#define MMCR_GPIO206_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO210_PIN_CONTROL_2 0x40081740\r
-#define MMCR_GPIO210_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO211_PIN_CONTROL_2 0x40081744\r
-#define MMCR_GPIO211_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO212_PIN_CONTROL_2 0x40081748\r
-#define MMCR_GPIO212_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO213_PIN_CONTROL_2 0x4008174C\r
-#define MMCR_GPIO213_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL_2))\r
-\r
-/***************************************************************\r
-* DMA\r
-***************************************************************/\r
-#define ADDR_DMA_MAIN_CONTROL 0x40002400\r
-#define MMCR_DMA_MAIN_CONTROL (*(VUINT8 *)(ADDR_DMA_MAIN_CONTROL))\r
-\r
-#define ADDR_DMA_AFIFO_DATA 0x40002404\r
-#define MMCR_DMA_AFIFO_DATA (*(VUINT32 *)(ADDR_DMA_AFIFO_DATA))\r
-\r
-#define ADDR_DMA_MAIN_DEBUG 0x40002408\r
-#define MMCR_DMA_MAIN_DEBUG (*(VUINT8 *)(ADDR_DMA_MAIN_DEBUG))\r
-\r
-#define ADDR_DMA_CH0_ACTIVATE 0x40002410\r
-#define MMCR_DMA_CH0_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH0_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH0_MEMORY_START_ADDRESS 0x40002414\r
-#define MMCR_DMA_CH0_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH0_MEMORY_END_ADDRESS 0x40002418\r
-#define MMCR_DMA_CH0_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH0_AHB_ADDRESS 0x4000241C\r
-#define MMCR_DMA_CH0_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH0_CONTROL 0x40002420\r
-#define MMCR_DMA_CH0_CONTROL (*(VUINT32 *)(ADDR_DMA_CH0_CONTROL))\r
-\r
-#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS 0x40002424\r
-#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE 0x40002428\r
-#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH0_TEST 0x4000242C\r
-#define MMCR_DMA_CH0_TEST (*(VUINT32 *)(ADDR_DMA_CH0_TEST))\r
-\r
-#define ADDR_DMA_CH1_ACTIVATE 0x40002430\r
-#define MMCR_DMA_CH1_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH1_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH1_MEMORY_START_ADDRESS 0x40002434\r
-#define MMCR_DMA_CH1_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH1_MEMORY_END_ADDRESS 0x40002438\r
-#define MMCR_DMA_CH1_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH1_AHB_ADDRESS 0x4000243C\r
-#define MMCR_DMA_CH1_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH1_CONTROL 0x40002440\r
-#define MMCR_DMA_CH1_CONTROL (*(VUINT32 *)(ADDR_DMA_CH1_CONTROL))\r
-\r
-#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS 0x40002444\r
-#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE 0x40002448\r
-#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH1_TEST 0x4000244C\r
-#define MMCR_DMA_CH1_TEST (*(VUINT32 *)(ADDR_DMA_CH1_TEST))\r
-\r
-#define ADDR_DMA_CH10_ACTIVATE 0x40002550\r
-#define MMCR_DMA_CH10_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH10_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH10_MEMORY_START_ADDRESS 0x40002554\r
-#define MMCR_DMA_CH10_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH10_MEMORY_END_ADDRESS 0x40002558\r
-#define MMCR_DMA_CH10_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH10_AHB_ADDRESS 0x4000255C\r
-#define MMCR_DMA_CH10_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH10_CONTROL 0x40002560\r
-#define MMCR_DMA_CH10_CONTROL (*(VUINT32 *)(ADDR_DMA_CH10_CONTROL))\r
-\r
-#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS 0x40002564\r
-#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE 0x40002568\r
-#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH10_TEST 0x4000256C\r
-#define MMCR_DMA_CH10_TEST (*(VUINT32 *)(ADDR_DMA_CH10_TEST))\r
-\r
-#define ADDR_DMA_CH11_ACTIVATE 0x40002570\r
-#define MMCR_DMA_CH11_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH11_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH11_MEMORY_START_ADDRESS 0x40002574\r
-#define MMCR_DMA_CH11_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH11_MEMORY_END_ADDRESS 0x40002578\r
-#define MMCR_DMA_CH11_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH11_AHB_ADDRESS 0x4000257C\r
-#define MMCR_DMA_CH11_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH11_CONTROL 0x40002580\r
-#define MMCR_DMA_CH11_CONTROL (*(VUINT32 *)(ADDR_DMA_CH11_CONTROL))\r
-\r
-#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS 0x40002584\r
-#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE 0x40002588\r
-#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH11_TEST 0x4000258C\r
-#define MMCR_DMA_CH11_TEST (*(VUINT32 *)(ADDR_DMA_CH11_TEST))\r
-\r
-#define ADDR_DMA_CH2_ACTIVATE 0x40002450\r
-#define MMCR_DMA_CH2_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH2_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH2_MEMORY_START_ADDRESS 0x40002454\r
-#define MMCR_DMA_CH2_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH2_MEMORY_END_ADDRESS 0x40002458\r
-#define MMCR_DMA_CH2_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH2_AHB_ADDRESS 0x4000245C\r
-#define MMCR_DMA_CH2_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH2_CONTROL 0x40002460\r
-#define MMCR_DMA_CH2_CONTROL (*(VUINT32 *)(ADDR_DMA_CH2_CONTROL))\r
-\r
-#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS 0x40002464\r
-#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE 0x40002468\r
-#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH2_TEST 0x4000246C\r
-#define MMCR_DMA_CH2_TEST (*(VUINT32 *)(ADDR_DMA_CH2_TEST))\r
-\r
-#define ADDR_DMA_CH3_ACTIVATE 0x40002470\r
-#define MMCR_DMA_CH3_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH3_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH3_MEMORY_START_ADDRESS 0x40002474\r
-#define MMCR_DMA_CH3_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH3_MEMORY_END_ADDRESS 0x40002478\r
-#define MMCR_DMA_CH3_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH3_AHB_ADDRESS 0x4000247C\r
-#define MMCR_DMA_CH3_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH3_CONTROL 0x40002480\r
-#define MMCR_DMA_CH3_CONTROL (*(VUINT32 *)(ADDR_DMA_CH3_CONTROL))\r
-\r
-#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS 0x40002484\r
-#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE 0x40002488\r
-#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH3_TEST 0x4000248C\r
-#define MMCR_DMA_CH3_TEST (*(VUINT32 *)(ADDR_DMA_CH3_TEST))\r
-\r
-#define ADDR_DMA_CH4_ACTIVATE 0x40002490\r
-#define MMCR_DMA_CH4_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH4_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH4_MEMORY_START_ADDRESS 0x40002494\r
-#define MMCR_DMA_CH4_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH4_MEMORY_END_ADDRESS 0x40002498\r
-#define MMCR_DMA_CH4_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH4_AHB_ADDRESS 0x4000249C\r
-#define MMCR_DMA_CH4_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH4_CONTROL 0x400024A0\r
-#define MMCR_DMA_CH4_CONTROL (*(VUINT32 *)(ADDR_DMA_CH4_CONTROL))\r
-\r
-#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS 0x400024A4\r
-#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE 0x400024A8\r
-#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH4_TEST 0x400024AC\r
-#define MMCR_DMA_CH4_TEST (*(VUINT32 *)(ADDR_DMA_CH4_TEST))\r
-\r
-#define ADDR_DMA_CH5_ACTIVATE 0x400024B0\r
-#define MMCR_DMA_CH5_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH5_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH5_MEMORY_START_ADDRESS 0x400024B4\r
-#define MMCR_DMA_CH5_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH5_MEMORY_END_ADDRESS 0x400024B8\r
-#define MMCR_DMA_CH5_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH5_AHB_ADDRESS 0x400024BC\r
-#define MMCR_DMA_CH5_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH5_CONTROL 0x400024C0\r
-#define MMCR_DMA_CH5_CONTROL (*(VUINT32 *)(ADDR_DMA_CH5_CONTROL))\r
-\r
-#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS 0x400024C4\r
-#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE 0x400024C8\r
-#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH5_TEST 0x400024CC\r
-#define MMCR_DMA_CH5_TEST (*(VUINT32 *)(ADDR_DMA_CH5_TEST))\r
-\r
-#define ADDR_DMA_CH6_ACTIVATE 0x400024D0\r
-#define MMCR_DMA_CH6_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH6_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH6_MEMORY_START_ADDRESS 0x400024D4\r
-#define MMCR_DMA_CH6_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH6_MEMORY_END_ADDRESS 0x400024D8\r
-#define MMCR_DMA_CH6_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH6_AHB_ADDRESS 0x400024DC\r
-#define MMCR_DMA_CH6_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH6_CONTROL 0x4.00E+05\r
-#define MMCR_DMA_CH6_CONTROL (*(VUINT32 *)(ADDR_DMA_CH6_CONTROL))\r
-\r
-#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS 0x4.00E+09\r
-#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE 0x4.00E+13\r
-#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH6_TEST 0x400024EC\r
-#define MMCR_DMA_CH6_TEST (*(VUINT32 *)(ADDR_DMA_CH6_TEST))\r
-\r
-#define ADDR_DMA_CH7_ACTIVATE 0x400024F0\r
-#define MMCR_DMA_CH7_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH7_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH7_MEMORY_START_ADDRESS 0x400024F4\r
-#define MMCR_DMA_CH7_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH7_MEMORY_END_ADDRESS 0x400024F8\r
-#define MMCR_DMA_CH7_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH7_AHB_ADDRESS 0x400024FC\r
-#define MMCR_DMA_CH7_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH7_CONTROL 0x40002500\r
-#define MMCR_DMA_CH7_CONTROL (*(VUINT32 *)(ADDR_DMA_CH7_CONTROL))\r
-\r
-#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS 0x40002504\r
-#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE 0x40002508\r
-#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH7_TEST 0x4000250C\r
-#define MMCR_DMA_CH7_TEST (*(VUINT32 *)(ADDR_DMA_CH7_TEST))\r
-\r
-#define ADDR_DMA_CH8_ACTIVATE 0x40002510\r
-#define MMCR_DMA_CH8_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH8_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH8_MEMORY_START_ADDRESS 0x40002514\r
-#define MMCR_DMA_CH8_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH8_MEMORY_END_ADDRESS 0x40002518\r
-#define MMCR_DMA_CH8_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH8_AHB_ADDRESS 0x4000251C\r
-#define MMCR_DMA_CH8_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH8_CONTROL 0x40002520\r
-#define MMCR_DMA_CH8_CONTROL (*(VUINT32 *)(ADDR_DMA_CH8_CONTROL))\r
-\r
-#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS 0x40002524\r
-#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE 0x40002528\r
-#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH8_TEST 0x4000252C\r
-#define MMCR_DMA_CH8_TEST (*(VUINT32 *)(ADDR_DMA_CH8_TEST))\r
-\r
-#define ADDR_DMA_CH9_ACTIVATE 0x40002530\r
-#define MMCR_DMA_CH9_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH9_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH9_MEMORY_START_ADDRESS 0x40002534\r
-#define MMCR_DMA_CH9_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH9_MEMORY_END_ADDRESS 0x40002538\r
-#define MMCR_DMA_CH9_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH9_AHB_ADDRESS 0x4000253C\r
-#define MMCR_DMA_CH9_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH9_CONTROL 0x40002540\r
-#define MMCR_DMA_CH9_CONTROL (*(VUINT32 *)(ADDR_DMA_CH9_CONTROL))\r
-\r
-#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS 0x40002544\r
-#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE 0x40002548\r
-#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH9_TEST 0x4000254C\r
-#define MMCR_DMA_CH9_TEST (*(VUINT32 *)(ADDR_DMA_CH9_TEST))\r
-\r
-#endif /*SMSCMMCR_H_*/\r
projects / freertos / blobdiff