--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific oscillator management functions\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#include <osc.h>\r
+\r
+#ifdef BOARD_OSC0_HZ\r
+void osc_priv_enable_osc0(void)\r
+{\r
+ irqflags_t flags;\r
+\r
+ flags = cpu_irq_save();\r
+ SCIF->SCIF_UNLOCK = SCIF_UNLOCK_KEY(0xAAu)\r
+ | SCIF_UNLOCK_ADDR((uint32_t)&SCIF->SCIF_OSCCTRL0 - (uint32_t)SCIF);\r
+ SCIF->SCIF_OSCCTRL0 =\r
+ OSC0_STARTUP_VALUE\r
+# if BOARD_OSC0_IS_XTAL == true\r
+ | OSC0_GAIN_VALUE\r
+#endif\r
+ | OSC0_MODE_VALUE\r
+ | SCIF_OSCCTRL0_OSCEN;\r
+ cpu_irq_restore(flags);\r
+}\r
+\r
+void osc_priv_disable_osc0(void)\r
+{\r
+ irqflags_t flags;\r
+\r
+ flags = cpu_irq_save();\r
+ SCIF->SCIF_UNLOCK = SCIF_UNLOCK_KEY(0xAAu)\r
+ | SCIF_UNLOCK_ADDR((uint32_t)&SCIF->SCIF_OSCCTRL0 - (uint32_t)SCIF);\r
+ SCIF->SCIF_OSCCTRL0 = 0;\r
+ cpu_irq_restore(flags);\r
+}\r
+#endif /* BOARD_OSC0_HZ */\r
+\r
+#ifdef BOARD_OSC32_HZ\r
+void osc_priv_enable_osc32(void)\r
+{\r
+ irqflags_t flags;\r
+\r
+ flags = cpu_irq_save();\r
+ BSCIF->BSCIF_UNLOCK = BSCIF_UNLOCK_KEY(0xAAu)\r
+ | BSCIF_UNLOCK_ADDR((uint32_t)&BSCIF->BSCIF_OSCCTRL32 - (uint32_t)BSCIF);\r
+ BSCIF->BSCIF_OSCCTRL32 =\r
+ OSC32_STARTUP_VALUE\r
+ | BOARD_OSC32_SELCURR\r
+ | OSC32_MODE_VALUE\r
+ | BSCIF_OSCCTRL32_EN1K\r
+ | BSCIF_OSCCTRL32_EN32K\r
+ | BSCIF_OSCCTRL32_OSC32EN;\r
+ cpu_irq_restore(flags);\r
+}\r
+\r
+void osc_priv_disable_osc32(void)\r
+{\r
+ irqflags_t flags;\r
+\r
+ flags = cpu_irq_save();\r
+ BSCIF->BSCIF_UNLOCK = BSCIF_UNLOCK_KEY(0xAAu)\r
+ | BSCIF_UNLOCK_ADDR((uint32_t)&BSCIF->BSCIF_OSCCTRL32 - (uint32_t)BSCIF);\r
+ BSCIF->BSCIF_OSCCTRL32 &= ~BSCIF_OSCCTRL32_OSC32EN;\r
+ // Wait until OSC32 RDY flag is cleared.\r
+ while (BSCIF->BSCIF_PCLKSR & BSCIF_PCLKSR_OSC32RDY);\r
+ cpu_irq_restore(flags);\r
+}\r
+#endif /* BOARD_OSC32_HZ */\r
+\r
+void osc_priv_enable_rc32k(void)\r
+{\r
+ irqflags_t flags;\r
+ uint32_t temp;\r
+\r
+ flags = cpu_irq_save();\r
+ temp = BSCIF->BSCIF_RC32KCR;\r
+ BSCIF->BSCIF_UNLOCK = BSCIF_UNLOCK_KEY(0xAAu)\r
+ | BSCIF_UNLOCK_ADDR((uint32_t)&BSCIF->BSCIF_RC32KCR - (uint32_t)BSCIF);\r
+ BSCIF->BSCIF_RC32KCR = temp | BSCIF_RC32KCR_EN32K | BSCIF_RC32KCR_EN;\r
+ cpu_irq_restore(flags);\r
+}\r
+\r
+void osc_priv_disable_rc32k(void)\r
+{\r
+ irqflags_t flags;\r
+ uint32_t temp;\r
+\r
+ flags = cpu_irq_save();\r
+ temp = BSCIF->BSCIF_RC32KCR;\r
+ temp &= ~BSCIF_RC32KCR_EN;\r
+ BSCIF->BSCIF_UNLOCK = BSCIF_UNLOCK_KEY(0xAAu)\r
+ | BSCIF_UNLOCK_ADDR((uint32_t)&BSCIF->BSCIF_RC32KCR - (uint32_t)BSCIF);\r
+ BSCIF->BSCIF_RC32KCR = temp;\r
+ cpu_irq_restore(flags);\r
+}\r
+\r
+void osc_priv_enable_rc1m(void)\r
+{\r
+ irqflags_t flags;\r
+ uint32_t temp;\r
+\r
+ flags = cpu_irq_save();\r
+ temp = BSCIF->BSCIF_RC1MCR;\r
+ BSCIF->BSCIF_UNLOCK = BSCIF_UNLOCK_KEY(0xAAu)\r
+ | BSCIF_UNLOCK_ADDR((uint32_t)&BSCIF->BSCIF_RC1MCR - (uint32_t)BSCIF);\r
+ BSCIF->BSCIF_RC1MCR = temp | BSCIF_RC1MCR_CLKOE;\r
+ cpu_irq_restore(flags);\r
+}\r
+\r
+void osc_priv_disable_rc1m(void)\r
+{\r
+ irqflags_t flags;\r
+ uint32_t temp;\r
+\r
+ flags = cpu_irq_save();\r
+ temp = BSCIF->BSCIF_RC1MCR;\r
+ temp &= ~BSCIF_RC1MCR_CLKOE;\r
+ BSCIF->BSCIF_UNLOCK = BSCIF_UNLOCK_KEY(0xAAu)\r
+ | BSCIF_UNLOCK_ADDR((uint32_t)&BSCIF->BSCIF_RC1MCR - (uint32_t)BSCIF);\r
+ BSCIF->BSCIF_RC1MCR = temp;\r
+ cpu_irq_restore(flags);\r
+}\r
+\r
+void osc_priv_enable_rc80m(void)\r
+{\r
+ irqflags_t flags;\r
+ uint32_t temp;\r
+\r
+ flags = cpu_irq_save();\r
+ temp = SCIF->SCIF_RC80MCR;\r
+ SCIF->SCIF_UNLOCK = SCIF_UNLOCK_KEY(0xAAu)\r
+ | SCIF_UNLOCK_ADDR((uint32_t)&SCIF->SCIF_RC80MCR - (uint32_t)SCIF);\r
+ SCIF->SCIF_RC80MCR = temp | SCIF_RC80MCR_EN;\r
+ cpu_irq_restore(flags);\r
+}\r
+\r
+void osc_priv_disable_rc80m(void)\r
+{\r
+ irqflags_t flags;\r
+ uint32_t temp;\r
+\r
+ flags = cpu_irq_save();\r
+ temp = SCIF->SCIF_RC80MCR;\r
+ temp &= ~SCIF_RC80MCR_EN ;\r
+ SCIF->SCIF_UNLOCK = SCIF_UNLOCK_KEY(0xAAu)\r
+ | SCIF_UNLOCK_ADDR((uint32_t)&SCIF->SCIF_RC80MCR - (uint32_t)SCIF);\r
+ SCIF->SCIF_RC80MCR = temp;\r
+ cpu_irq_restore(flags);\r
+}\r
+\r
+void osc_priv_enable_rcfast(void)\r
+{\r
+ irqflags_t flags;\r
+ uint32_t temp;\r
+\r
+ flags = cpu_irq_save();\r
+ // Let FCD and calibration value by default\r
+ temp = SCIF->SCIF_RCFASTCFG;\r
+ // Clear previous FRANGE value\r
+ temp &= ~SCIF_RCFASTCFG_FRANGE_Msk;\r
+\r
+ SCIF->SCIF_UNLOCK = SCIF_UNLOCK_KEY(0xAAu)\r
+ | SCIF_UNLOCK_ADDR((uint32_t)&SCIF->SCIF_RCFASTCFG - (uint32_t)SCIF);\r
+ SCIF->SCIF_RCFASTCFG = temp | SCIF_RCFASTCFG_EN\r
+ | SCIF_RCFASTCFG_FRANGE(CONFIG_RCFAST_FRANGE);\r
+ cpu_irq_restore(flags);\r
+}\r
+\r
+void osc_priv_disable_rcfast(void)\r
+{\r
+ irqflags_t flags;\r
+ uint32_t temp;\r
+ flags = cpu_irq_save();\r
+ // Let FCD and calibration value by default\r
+ temp = SCIF->SCIF_RCFASTCFG;\r
+ // Clear previous FRANGE value\r
+ temp &= ~SCIF_RCFASTCFG_FRANGE_Msk;\r
+ // Disalbe RCFAST\r
+ temp &= ~SCIF_RCFASTCFG_EN;\r
+ SCIF->SCIF_UNLOCK = SCIF_UNLOCK_KEY(0xAAu)\r
+ | SCIF_UNLOCK_ADDR((uint32_t)&SCIF->SCIF_RCFASTCFG - (uint32_t)SCIF);\r
+ SCIF->SCIF_RCFASTCFG = temp;\r
+ cpu_irq_restore(flags);\r
+}\r
+\r
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