--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SAM4L_H\r
+#define SAM4L_H\r
+\r
+/** \addtogroup SAM4L_definitions SAM4L definitions\r
+ This file defines all structures and symbols for SAM4L:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __ASSEMBLY__\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */\r
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */\r
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */\r
+#define CAST(type, value) ((type *)(value))\r
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */\r
+#else\r
+#define CAST(type, value) (value)\r
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM4L */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4L_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 Cortex-M4 Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+ /****** SAM4L specific Interrupt Numbers *********************************/\r
+ HFLASHC_IRQn = 0, /**< 0 SAM4L Flash Controller (HFLASHC) */\r
+ PDCA_0_IRQn = 1, /**< 1 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_1_IRQn = 2, /**< 2 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_2_IRQn = 3, /**< 3 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_3_IRQn = 4, /**< 4 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_4_IRQn = 5, /**< 5 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_5_IRQn = 6, /**< 6 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_6_IRQn = 7, /**< 7 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_7_IRQn = 8, /**< 8 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_8_IRQn = 9, /**< 9 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_9_IRQn = 10, /**< 10 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_10_IRQn = 11, /**< 11 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_11_IRQn = 12, /**< 12 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_12_IRQn = 13, /**< 13 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_13_IRQn = 14, /**< 14 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_14_IRQn = 15, /**< 15 SAM4L Peripheral DMA Controller (PDCA) */\r
+ PDCA_15_IRQn = 16, /**< 16 SAM4L Peripheral DMA Controller (PDCA) */\r
+ CRCCU_IRQn = 17, /**< 17 SAM4L CRC Calculation Unit (CRCCU) */\r
+ USBC_IRQn = 18, /**< 18 SAM4L USB 2.0 Interface (USBC) */\r
+ PEVC_TR_IRQn = 19, /**< 19 SAM4L Peripheral Event Controller (PEVC) */\r
+ PEVC_OV_IRQn = 20, /**< 20 SAM4L Peripheral Event Controller (PEVC) */\r
+ AESA_IRQn = 21, /**< 21 SAM4L Advanced Encryption Standard (AESA) */\r
+ PM_IRQn = 22, /**< 22 SAM4L Power Manager (PM) */\r
+ SCIF_IRQn = 23, /**< 23 SAM4L System Control Interface (SCIF) */\r
+ FREQM_IRQn = 24, /**< 24 SAM4L Frequency Meter (FREQM) */\r
+ GPIO_0_IRQn = 25, /**< 25 SAM4L General-Purpose Input/Output Controller (GPIO) */\r
+ GPIO_1_IRQn = 26, /**< 26 SAM4L General-Purpose Input/Output Controller (GPIO) */\r
+ GPIO_2_IRQn = 27, /**< 27 SAM4L General-Purpose Input/Output Controller (GPIO) */\r
+ GPIO_3_IRQn = 28, /**< 28 SAM4L General-Purpose Input/Output Controller (GPIO) */\r
+ GPIO_4_IRQn = 29, /**< 29 SAM4L General-Purpose Input/Output Controller (GPIO) */\r
+ GPIO_5_IRQn = 30, /**< 30 SAM4L General-Purpose Input/Output Controller (GPIO) */\r
+ GPIO_6_IRQn = 31, /**< 31 SAM4L General-Purpose Input/Output Controller (GPIO) */\r
+ GPIO_7_IRQn = 32, /**< 32 SAM4L General-Purpose Input/Output Controller (GPIO) */\r
+ GPIO_8_IRQn = 33, /**< 33 SAM4L General-Purpose Input/Output Controller (GPIO) */\r
+ GPIO_9_IRQn = 34, /**< 34 SAM4L General-Purpose Input/Output Controller (GPIO) */\r
+ GPIO_10_IRQn = 35, /**< 35 SAM4L General-Purpose Input/Output Controller (GPIO) */\r
+ GPIO_11_IRQn = 36, /**< 36 SAM4L General-Purpose Input/Output Controller (GPIO) */\r
+ BPM_IRQn = 37, /**< 37 SAM4L Backup Power Manager (BPM) */\r
+ BSCIF_IRQn = 38, /**< 38 SAM4L Backup System Control Interface (BSCIF) */\r
+ AST_ALARM_IRQn = 39, /**< 39 SAM4L Asynchronous Timer (AST) */\r
+ AST_PER_IRQn = 40, /**< 40 SAM4L Asynchronous Timer (AST) */\r
+ AST_OVF_IRQn = 41, /**< 41 SAM4L Asynchronous Timer (AST) */\r
+ AST_READY_IRQn = 42, /**< 42 SAM4L Asynchronous Timer (AST) */\r
+ AST_CLKREADY_IRQn = 43, /**< 43 SAM4L Asynchronous Timer (AST) */\r
+ WDT_IRQn = 44, /**< 44 SAM4L Watchdog Timer (WDT) */\r
+ EIC_1_IRQn = 45, /**< 45 SAM4L External Interrupt Controller (EIC) */\r
+ EIC_2_IRQn = 46, /**< 46 SAM4L External Interrupt Controller (EIC) */\r
+ EIC_3_IRQn = 47, /**< 47 SAM4L External Interrupt Controller (EIC) */\r
+ EIC_4_IRQn = 48, /**< 48 SAM4L External Interrupt Controller (EIC) */\r
+ EIC_5_IRQn = 49, /**< 49 SAM4L External Interrupt Controller (EIC) */\r
+ EIC_6_IRQn = 50, /**< 50 SAM4L External Interrupt Controller (EIC) */\r
+ EIC_7_IRQn = 51, /**< 51 SAM4L External Interrupt Controller (EIC) */\r
+ EIC_8_IRQn = 52, /**< 52 SAM4L External Interrupt Controller (EIC) */\r
+ IISC_IRQn = 53, /**< 53 SAM4L Inter-IC Sound (I2S) Controller (IISC) */\r
+ SPI_IRQn = 54, /**< 54 SAM4L Serial Peripheral Interface (SPI) */\r
+ TC00_IRQn = 55, /**< 55 SAM4L Timer/Counter 0 (TC0) */\r
+ TC01_IRQn = 56, /**< 56 SAM4L Timer/Counter 0 (TC0) */\r
+ TC02_IRQn = 57, /**< 57 SAM4L Timer/Counter 0 (TC0) */\r
+ TC10_IRQn = 58, /**< 58 SAM4L Timer/Counter 1 (TC1) */\r
+ TC11_IRQn = 59, /**< 59 SAM4L Timer/Counter 1 (TC1) */\r
+ TC12_IRQn = 60, /**< 60 SAM4L Timer/Counter 1 (TC1) */\r
+ TWIM0_IRQn = 61, /**< 61 SAM4L Two-wire Master Interface 0 (TWIM0) */\r
+ TWIS0_IRQn = 62, /**< 62 SAM4L Two-wire Slave Interface 0 (TWIS0) */\r
+ TWIM1_IRQn = 63, /**< 63 SAM4L Two-wire Master Interface 1 (TWIM1) */\r
+ TWIS1_IRQn = 64, /**< 64 SAM4L Two-wire Slave Interface 1 (TWIS1) */\r
+ USART0_IRQn = 65, /**< 65 SAM4L Universal Synchronous Asynchronous Receiver Transmitter 0 (USART0) */\r
+ USART1_IRQn = 66, /**< 66 SAM4L Universal Synchronous Asynchronous Receiver Transmitter 1 (USART1) */\r
+ USART2_IRQn = 67, /**< 67 SAM4L Universal Synchronous Asynchronous Receiver Transmitter 2 (USART2) */\r
+ USART3_IRQn = 68, /**< 68 SAM4L Universal Synchronous Asynchronous Receiver Transmitter 3 (USART3) */\r
+ ADCIFE_IRQn = 69, /**< 69 SAM4L ADC controller interface (ADCIFE) */\r
+ DACC_IRQn = 70, /**< 70 SAM4L DAC Controller (DACC) */\r
+ ACIFC_IRQn = 71, /**< 71 SAM4L Analog Comparator Interface (ACIFC) */\r
+ ABDACB_IRQn = 72, /**< 72 SAM4L Audio Bitstream DAC (ABDACB) */\r
+ TRNG_IRQn = 73, /**< 73 SAM4L True Random Number Generator (TRNG) */\r
+ PARC_IRQn = 74, /**< 74 SAM4L Parallel Capture (PARC) */\r
+ CATB_IRQn = 75, /**< 75 SAM4L Capacitive Touch Module B (CATB) */\r
+ TWIM2_IRQn = 77, /**< 77 SAM4L Two-wire Master Interface 2 (TWIM2) */\r
+ TWIM3_IRQn = 78, /**< 78 SAM4L Two-wire Master Interface 3 (TWIM3) */\r
+ LCDCA_IRQn = 79 /**< 79 SAM4L LCD Controller (LCDCA) */\r
+} IRQn_Type;\r
+\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+\r
+void HFLASHC_Handler( void );\r
+void PDCA_0_Handler( void );\r
+void PDCA_1_Handler( void );\r
+void PDCA_2_Handler( void );\r
+void PDCA_3_Handler( void );\r
+void PDCA_4_Handler( void );\r
+void PDCA_5_Handler( void );\r
+void PDCA_6_Handler( void );\r
+void PDCA_7_Handler( void );\r
+void PDCA_8_Handler( void );\r
+void PDCA_9_Handler( void );\r
+void PDCA_10_Handler( void );\r
+void PDCA_11_Handler( void );\r
+void PDCA_12_Handler( void );\r
+void PDCA_13_Handler( void );\r
+void PDCA_14_Handler( void );\r
+void PDCA_15_Handler( void );\r
+void CRCCU_Handler( void );\r
+void USBC_Handler( void );\r
+void PEVC_TR_Handler( void );\r
+void PEVC_OV_Handler( void );\r
+void AESA_Handler( void );\r
+void PM_Handler( void );\r
+void SCIF_Handler( void );\r
+void FREQM_Handler( void );\r
+void GPIO_0_Handler( void );\r
+void GPIO_1_Handler( void );\r
+void GPIO_2_Handler( void );\r
+void GPIO_3_Handler( void );\r
+void GPIO_4_Handler( void );\r
+void GPIO_5_Handler( void );\r
+void GPIO_6_Handler( void );\r
+void GPIO_7_Handler( void );\r
+void GPIO_8_Handler( void );\r
+void GPIO_9_Handler( void );\r
+void GPIO_10_Handler( void );\r
+void GPIO_11_Handler( void );\r
+void BPM_Handler( void );\r
+void BSCIF_Handler( void );\r
+void AST_ALARM_Handler( void );\r
+void AST_PER_Handler( void );\r
+void AST_OVF_Handler( void );\r
+void AST_READY_Handler( void );\r
+void AST_CLKREADY_Handler( void );\r
+void WDT_Handler( void );\r
+void EIC_1_Handler( void );\r
+void EIC_2_Handler( void );\r
+void EIC_3_Handler( void );\r
+void EIC_4_Handler( void );\r
+void EIC_5_Handler( void );\r
+void EIC_6_Handler( void );\r
+void EIC_7_Handler( void );\r
+void EIC_8_Handler( void );\r
+void IISC_Handler( void );\r
+void SPI_Handler( void );\r
+void TC00_Handler( void );\r
+void TC01_Handler( void );\r
+void TC02_Handler( void );\r
+void TC10_Handler( void );\r
+void TC11_Handler( void );\r
+void TC12_Handler( void );\r
+void TWIM0_Handler( void );\r
+void TWIS0_Handler( void );\r
+void TWIM1_Handler( void );\r
+void TWIS1_Handler( void );\r
+void USART0_Handler( void );\r
+void USART1_Handler( void );\r
+void USART2_Handler( void );\r
+void USART3_Handler( void );\r
+void ADCIFE_Handler( void );\r
+void DACC_Handler( void );\r
+void ACIFC_Handler( void );\r
+void ABDACB_Handler( void );\r
+void TRNG_Handler( void );\r
+void PARC_Handler( void );\r
+void CATB_Handler( void );\r
+void TWIM2_Handler( void );\r
+void TWIM3_Handler( void );\r
+void LCDCA_Handler( void );\r
+\r
+/*\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __MPU_PRESENT 1 /**< SAM4L does provide a MPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM4L uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 0 /**< SAM4L does not provide a FPU */\r
+\r
+/**\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4L */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4L_api Peripheral Software API */\r
+/*@{*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR ABDACB */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_ABDACB Audio Bitstream DAC */\r
+/*@{*/\r
+\r
+#define REV_ABDACB 0x100\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief ABDACB hardware registers */\r
+typedef struct {\r
+ RwReg ABDACB_CR; /**< \brief (ABDACB Offset: 0x00) Control Register */\r
+ RwReg ABDACB_SDR0; /**< \brief (ABDACB Offset: 0x04) Sample Data Register 0 */\r
+ RwReg ABDACB_SDR1; /**< \brief (ABDACB Offset: 0x08) Sample Data Register 1 */\r
+ RwReg ABDACB_VCR0; /**< \brief (ABDACB Offset: 0x0C) Volume Control Register 0 */\r
+ RwReg ABDACB_VCR1; /**< \brief (ABDACB Offset: 0x10) Volume Control Register 1 */\r
+ WoReg ABDACB_IER; /**< \brief (ABDACB Offset: 0x14) Interrupt Enable Register */\r
+ WoReg ABDACB_IDR; /**< \brief (ABDACB Offset: 0x18) Interupt Disable Register */\r
+ RoReg ABDACB_IMR; /**< \brief (ABDACB Offset: 0x1C) Interrupt Mask Register */\r
+ RoReg ABDACB_SR; /**< \brief (ABDACB Offset: 0x20) Status Register */\r
+ WoReg ABDACB_SCR; /**< \brief (ABDACB Offset: 0x24) Status Clear Register */\r
+ RoReg ABDACB_PARAMETER; /**< \brief (ABDACB Offset: 0x28) Parameter Register */\r
+ RoReg ABDACB_VERSION; /**< \brief (ABDACB Offset: 0x2C) Version Register */\r
+} Abdacb;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- ABDACB_CR : (ABDACB Offset: 0x00) Control Register -------- */\r
+#define ABDACB_CR_EN (0x1u << 0) /**< \brief (ABDACB_CR) Enable */\r
+#define ABDACB_CR_EN_0 (0x0u << 0) /**< \brief (ABDACB_CR) Audio DAC is disabled */\r
+#define ABDACB_CR_EN_1 (0x1u << 0) /**< \brief (ABDACB_CR) Audio DAC is enabled */\r
+#define ABDACB_CR_SWAP (0x1u << 1) /**< \brief (ABDACB_CR) Swap Channels */\r
+#define ABDACB_CR_SWAP_0 (0x0u << 1) /**< \brief (ABDACB_CR) The CHANNEL0 and CHANNEL1 samples will not be swapped when writing the Audio DAC Sample Data Register (SDR) */\r
+#define ABDACB_CR_SWAP_1 (0x1u << 1) /**< \brief (ABDACB_CR) The CHANNEL0 and CHANNEL1 samples will be swapped when writing the Audio DAC Sample Data Register (SDR) */\r
+#define ABDACB_CR_ALTUPR (0x1u << 3) /**< \brief (ABDACB_CR) Alternative up-sampling ratio */\r
+#define ABDACB_CR_CMOC (0x1u << 4) /**< \brief (ABDACB_CR) Common mode offset control */\r
+#define ABDACB_CR_MONO (0x1u << 5) /**< \brief (ABDACB_CR) Mono mode */\r
+#define ABDACB_CR_SWRST (0x1u << 7) /**< \brief (ABDACB_CR) Software reset */\r
+#define ABDACB_CR_DATAFORMAT_Pos 16\r
+#define ABDACB_CR_DATAFORMAT_Msk (0x7u << ABDACB_CR_DATAFORMAT_Pos) /**< \brief (ABDACB_CR) Data word format */\r
+#define ABDACB_CR_DATAFORMAT(value) ((ABDACB_CR_DATAFORMAT_Msk & ((value) << ABDACB_CR_DATAFORMAT_Pos)))\r
+#define ABDACB_CR_FS_Pos 24\r
+#define ABDACB_CR_FS_Msk (0xFu << ABDACB_CR_FS_Pos) /**< \brief (ABDACB_CR) Sampling frequency */\r
+#define ABDACB_CR_FS(value) ((ABDACB_CR_FS_Msk & ((value) << ABDACB_CR_FS_Pos)))\r
+/* -------- ABDACB_SDR0 : (ABDACB Offset: 0x04) Sample Data Register 0 -------- */\r
+#define ABDACB_SDR0_DATA_Pos 0\r
+#define ABDACB_SDR0_DATA_Msk (0xFFFFFFFFu << ABDACB_SDR0_DATA_Pos) /**< \brief (ABDACB_SDR0) Sample Data */\r
+#define ABDACB_SDR0_DATA(value) ((ABDACB_SDR0_DATA_Msk & ((value) << ABDACB_SDR0_DATA_Pos)))\r
+/* -------- ABDACB_SDR1 : (ABDACB Offset: 0x08) Sample Data Register 1 -------- */\r
+#define ABDACB_SDR1_DATA_Pos 0\r
+#define ABDACB_SDR1_DATA_Msk (0xFFFFFFFFu << ABDACB_SDR1_DATA_Pos) /**< \brief (ABDACB_SDR1) Sample Data */\r
+#define ABDACB_SDR1_DATA(value) ((ABDACB_SDR1_DATA_Msk & ((value) << ABDACB_SDR1_DATA_Pos)))\r
+/* -------- ABDACB_VCR0 : (ABDACB Offset: 0x0C) Volume Control Register 0 -------- */\r
+#define ABDACB_VCR0_VOLUME_Pos 0\r
+#define ABDACB_VCR0_VOLUME_Msk (0x7FFFu << ABDACB_VCR0_VOLUME_Pos) /**< \brief (ABDACB_VCR0) Volume Control */\r
+#define ABDACB_VCR0_VOLUME(value) ((ABDACB_VCR0_VOLUME_Msk & ((value) << ABDACB_VCR0_VOLUME_Pos)))\r
+#define ABDACB_VCR0_MUTE (0x1u << 31) /**< \brief (ABDACB_VCR0) Mute */\r
+/* -------- ABDACB_VCR1 : (ABDACB Offset: 0x10) Volume Control Register 1 -------- */\r
+#define ABDACB_VCR1_VOLUME_Pos 0\r
+#define ABDACB_VCR1_VOLUME_Msk (0x7FFFu << ABDACB_VCR1_VOLUME_Pos) /**< \brief (ABDACB_VCR1) Volume Control */\r
+#define ABDACB_VCR1_VOLUME(value) ((ABDACB_VCR1_VOLUME_Msk & ((value) << ABDACB_VCR1_VOLUME_Pos)))\r
+#define ABDACB_VCR1_MUTE (0x1u << 31) /**< \brief (ABDACB_VCR1) Mute */\r
+/* -------- ABDACB_IER : (ABDACB Offset: 0x14) Interrupt Enable Register -------- */\r
+#define ABDACB_IER_TXRDY (0x1u << 1) /**< \brief (ABDACB_IER) Transmit Ready Interrupt Enable */\r
+#define ABDACB_IER_TXRDY_0 (0x0u << 1) /**< \brief (ABDACB_IER) No effect */\r
+#define ABDACB_IER_TXRDY_1 (0x1u << 1) /**< \brief (ABDACB_IER) Enables the Audio DAC TX Ready interrupt */\r
+#define ABDACB_IER_TXUR (0x1u << 2) /**< \brief (ABDACB_IER) Transmit Underrun Interrupt Enable */\r
+#define ABDACB_IER_TXUR_0 (0x0u << 2) /**< \brief (ABDACB_IER) No effect */\r
+#define ABDACB_IER_TXUR_1 (0x1u << 2) /**< \brief (ABDACB_IER) Enables the Audio DAC Underrun interrupt */\r
+/* -------- ABDACB_IDR : (ABDACB Offset: 0x18) Interupt Disable Register -------- */\r
+#define ABDACB_IDR_TXRDY (0x1u << 1) /**< \brief (ABDACB_IDR) Transmit Ready Interrupt Disable */\r
+#define ABDACB_IDR_TXRDY_0 (0x0u << 1) /**< \brief (ABDACB_IDR) No effect */\r
+#define ABDACB_IDR_TXRDY_1 (0x1u << 1) /**< \brief (ABDACB_IDR) Disable the Audio DAC TX Ready interrupt */\r
+#define ABDACB_IDR_TXUR (0x1u << 2) /**< \brief (ABDACB_IDR) Transmit Underrun Interrupt Disable */\r
+#define ABDACB_IDR_TXUR_0 (0x0u << 2) /**< \brief (ABDACB_IDR) No effect */\r
+#define ABDACB_IDR_TXUR_1 (0x1u << 2) /**< \brief (ABDACB_IDR) Disable the Audio DAC Underrun interrupt */\r
+/* -------- ABDACB_IMR : (ABDACB Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define ABDACB_IMR_TXRDY (0x1u << 1) /**< \brief (ABDACB_IMR) Transmit Ready Interrupt Mask */\r
+#define ABDACB_IMR_TXRDY_0 (0x0u << 1) /**< \brief (ABDACB_IMR) The Audio DAC TX Ready interrupt is disabled */\r
+#define ABDACB_IMR_TXRDY_1 (0x1u << 1) /**< \brief (ABDACB_IMR) The Audio DAC TX Ready interrupt is enabled */\r
+#define ABDACB_IMR_TXUR (0x1u << 2) /**< \brief (ABDACB_IMR) Transmit Underrun Interrupt Mask */\r
+#define ABDACB_IMR_TXUR_0 (0x0u << 2) /**< \brief (ABDACB_IMR) The Audio DAC Underrun interrupt is disabled */\r
+#define ABDACB_IMR_TXUR_1 (0x1u << 2) /**< \brief (ABDACB_IMR) The Audio DAC Underrun interrupt is enabled */\r
+/* -------- ABDACB_SR : (ABDACB Offset: 0x20) Status Register -------- */\r
+#define ABDACB_SR_BUSY (0x1u << 0) /**< \brief (ABDACB_SR) ABDACB Busy */\r
+#define ABDACB_SR_TXRDY (0x1u << 1) /**< \brief (ABDACB_SR) Transmit Ready */\r
+#define ABDACB_SR_TXRDY_0 (0x0u << 1) /**< \brief (ABDACB_SR) No Audio DAC TX Ready has occured since the last time ISR was read or since reset */\r
+#define ABDACB_SR_TXRDY_1 (0x1u << 1) /**< \brief (ABDACB_SR) At least one Audio DAC TX Ready has occured since the last time ISR was read or since reset */\r
+#define ABDACB_SR_TXUR (0x1u << 2) /**< \brief (ABDACB_SR) Transmit Underrun */\r
+#define ABDACB_SR_TXUR_0 (0x0u << 2) /**< \brief (ABDACB_SR) No Audio DAC Underrun has occured since the last time ISR was read or since reset */\r
+#define ABDACB_SR_TXUR_1 (0x1u << 2) /**< \brief (ABDACB_SR) At least one Audio DAC Underrun has occured since the last time ISR was read or since reset */\r
+/* -------- ABDACB_SCR : (ABDACB Offset: 0x24) Status Clear Register -------- */\r
+#define ABDACB_SCR_TXRDY (0x1u << 1) /**< \brief (ABDACB_SCR) Transmit Ready Interrupt Clear */\r
+#define ABDACB_SCR_TXRDY_0 (0x0u << 1) /**< \brief (ABDACB_SCR) No effect */\r
+#define ABDACB_SCR_TXRDY_1 (0x1u << 1) /**< \brief (ABDACB_SCR) Clear the Audio DAC TX Ready interrupt */\r
+#define ABDACB_SCR_TXUR (0x1u << 2) /**< \brief (ABDACB_SCR) Transmit Underrun Interrupt Clear */\r
+#define ABDACB_SCR_TXUR_0 (0x0u << 2) /**< \brief (ABDACB_SCR) No effect */\r
+#define ABDACB_SCR_TXUR_1 (0x1u << 2) /**< \brief (ABDACB_SCR) Clear the Audio DAC Underrun interrupt */\r
+/* -------- ABDACB_VERSION : (ABDACB Offset: 0x2C) Version Register -------- */\r
+#define ABDACB_VERSION_VERSION_Pos 0\r
+#define ABDACB_VERSION_VERSION_Msk (0xFFFu << ABDACB_VERSION_VERSION_Pos) /**< \brief (ABDACB_VERSION) Version Number */\r
+#define ABDACB_VERSION_VERSION(value) ((ABDACB_VERSION_VERSION_Msk & ((value) << ABDACB_VERSION_VERSION_Pos)))\r
+#define ABDACB_VERSION_VARIANT_Pos 16\r
+#define ABDACB_VERSION_VARIANT_Msk (0xFu << ABDACB_VERSION_VARIANT_Pos) /**< \brief (ABDACB_VERSION) Variant Number */\r
+#define ABDACB_VERSION_VARIANT(value) ((ABDACB_VERSION_VARIANT_Msk & ((value) << ABDACB_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR ACIFC */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_ACIFC Analog Comparator Interface */\r
+/*@{*/\r
+\r
+#define REV_ACIFC 0x101\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief AcifcConf hardware registers */\r
+typedef struct {\r
+ RwReg ACIFC_CONF; /**< \brief (AcifcConf Offset: 0x00) AC Configuration Register */\r
+} AcifcConf;\r
+/** \brief AcifcConfw hardware registers */\r
+typedef struct {\r
+ RwReg ACIFC_CONFW; /**< \brief (AcifcConfw Offset: 0x00) Window configuration Register */\r
+} AcifcConfw;\r
+/** \brief ACIFC hardware registers */\r
+typedef struct {\r
+ RwReg ACIFC_CTRL; /**< \brief (ACIFC Offset: 0x00) Control Register */\r
+ RoReg ACIFC_SR; /**< \brief (ACIFC Offset: 0x04) Status Register */\r
+ RoReg Reserved1[2];\r
+ WoReg ACIFC_IER; /**< \brief (ACIFC Offset: 0x10) Interrupt Enable Register */\r
+ WoReg ACIFC_IDR; /**< \brief (ACIFC Offset: 0x14) Interrupt Disable Register */\r
+ RoReg ACIFC_IMR; /**< \brief (ACIFC Offset: 0x18) Interrupt Mask Register */\r
+ RoReg ACIFC_ISR; /**< \brief (ACIFC Offset: 0x1C) Interrupt Status Register */\r
+ WoReg ACIFC_ICR; /**< \brief (ACIFC Offset: 0x20) Interrupt Status Clear Register */\r
+ RwReg ACIFC_TR; /**< \brief (ACIFC Offset: 0x24) Test Register */\r
+ RoReg Reserved2[2];\r
+ RoReg ACIFC_PARAMETER; /**< \brief (ACIFC Offset: 0x30) Parameter Register */\r
+ RoReg ACIFC_VERSION; /**< \brief (ACIFC Offset: 0x34) Version Register */\r
+ RoReg Reserved3[18];\r
+ AcifcConfw ACIFC_CONFW[4]; /**< \brief (ACIFC Offset: 0x80) AcifcConfw groups */\r
+ RoReg Reserved4[16];\r
+ AcifcConf ACIFC_CONF[8]; /**< \brief (ACIFC Offset: 0xD0) AcifcConf groups */\r
+} Acifc;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- ACIFC_CTRL : (ACIFC Offset: 0x00) Control Register -------- */\r
+#define ACIFC_CTRL_EN (0x1u << 0) /**< \brief (ACIFC_CTRL) ACIFC Enable */\r
+#define ACIFC_CTRL_EVENTEN (0x1u << 1) /**< \brief (ACIFC_CTRL) Peripheral Event Trigger Enable */\r
+#define ACIFC_CTRL_USTART (0x1u << 4) /**< \brief (ACIFC_CTRL) User Start Single Comparison */\r
+#define ACIFC_CTRL_ESTART (0x1u << 5) /**< \brief (ACIFC_CTRL) Peripheral Event Start Single Comparison */\r
+#define ACIFC_CTRL_ACTEST (0x1u << 7) /**< \brief (ACIFC_CTRL) Analog Comparator Test Mode */\r
+/* -------- ACIFC_SR : (ACIFC Offset: 0x04) Status Register -------- */\r
+#define ACIFC_SR_ACCS0 (0x1u << 0) /**< \brief (ACIFC_SR) AC0 Current Comparison Status */\r
+#define ACIFC_SR_ACRDY0 (0x1u << 1) /**< \brief (ACIFC_SR) AC0 Ready */\r
+#define ACIFC_SR_ACCS1 (0x1u << 2) /**< \brief (ACIFC_SR) AC1 Current Comparison Status */\r
+#define ACIFC_SR_ACRDY1 (0x1u << 3) /**< \brief (ACIFC_SR) AC1 Ready */\r
+#define ACIFC_SR_ACCS2 (0x1u << 4) /**< \brief (ACIFC_SR) AC2 Current Comparison Status */\r
+#define ACIFC_SR_ACRDY2 (0x1u << 5) /**< \brief (ACIFC_SR) AC2 Ready */\r
+#define ACIFC_SR_ACCS3 (0x1u << 6) /**< \brief (ACIFC_SR) AC3 Current Comparison Status */\r
+#define ACIFC_SR_ACRDY3 (0x1u << 7) /**< \brief (ACIFC_SR) AC3 Ready */\r
+#define ACIFC_SR_ACCS4 (0x1u << 8) /**< \brief (ACIFC_SR) AC4 Current Comparison Status */\r
+#define ACIFC_SR_ACRDY4 (0x1u << 9) /**< \brief (ACIFC_SR) AC4 Ready */\r
+#define ACIFC_SR_ACCS5 (0x1u << 10) /**< \brief (ACIFC_SR) AC5 Current Comparison Status */\r
+#define ACIFC_SR_ACRDY5 (0x1u << 11) /**< \brief (ACIFC_SR) AC5 Ready */\r
+#define ACIFC_SR_ACCS6 (0x1u << 12) /**< \brief (ACIFC_SR) AC6 Current Comparison Status */\r
+#define ACIFC_SR_ACRDY6 (0x1u << 13) /**< \brief (ACIFC_SR) AC6 Ready */\r
+#define ACIFC_SR_ACCS7 (0x1u << 14) /**< \brief (ACIFC_SR) AC7 Current Comparison Status */\r
+#define ACIFC_SR_ACRDY7 (0x1u << 15) /**< \brief (ACIFC_SR) AC7 Ready */\r
+#define ACIFC_SR_WFCS0 (0x1u << 24) /**< \brief (ACIFC_SR) Window0 Mode Current Status */\r
+#define ACIFC_SR_WFCS1 (0x1u << 25) /**< \brief (ACIFC_SR) Window1 Mode Current Status */\r
+#define ACIFC_SR_WFCS2 (0x1u << 26) /**< \brief (ACIFC_SR) Window2 Mode Current Status */\r
+#define ACIFC_SR_WFCS3 (0x1u << 27) /**< \brief (ACIFC_SR) Window3 Mode Current Status */\r
+/* -------- ACIFC_IER : (ACIFC Offset: 0x10) Interrupt Enable Register -------- */\r
+#define ACIFC_IER_ACINT0 (0x1u << 0) /**< \brief (ACIFC_IER) AC0 Interrupt Enable */\r
+#define ACIFC_IER_SUTINT0 (0x1u << 1) /**< \brief (ACIFC_IER) AC0 Startup Time Interrupt Enable */\r
+#define ACIFC_IER_ACINT1 (0x1u << 2) /**< \brief (ACIFC_IER) AC1 Interrupt Enable */\r
+#define ACIFC_IER_SUTINT1 (0x1u << 3) /**< \brief (ACIFC_IER) AC1 Startup Time Interrupt Enable */\r
+#define ACIFC_IER_ACINT2 (0x1u << 4) /**< \brief (ACIFC_IER) AC2 Interrupt Enable */\r
+#define ACIFC_IER_SUTINT2 (0x1u << 5) /**< \brief (ACIFC_IER) AC2 Startup Time Interrupt Enable */\r
+#define ACIFC_IER_ACINT3 (0x1u << 6) /**< \brief (ACIFC_IER) AC3 Interrupt Enable */\r
+#define ACIFC_IER_SUTINT3 (0x1u << 7) /**< \brief (ACIFC_IER) AC3 Startup Time Interrupt Enable */\r
+#define ACIFC_IER_ACINT4 (0x1u << 8) /**< \brief (ACIFC_IER) AC4 Interrupt Enable */\r
+#define ACIFC_IER_SUTINT4 (0x1u << 9) /**< \brief (ACIFC_IER) AC4 Startup Time Interrupt Enable */\r
+#define ACIFC_IER_ACINT5 (0x1u << 10) /**< \brief (ACIFC_IER) AC5 Interrupt Enable */\r
+#define ACIFC_IER_SUTINT5 (0x1u << 11) /**< \brief (ACIFC_IER) AC5 Startup Time Interrupt Enable */\r
+#define ACIFC_IER_ACINT6 (0x1u << 12) /**< \brief (ACIFC_IER) AC6 Interrupt Enable */\r
+#define ACIFC_IER_SUTINT6 (0x1u << 13) /**< \brief (ACIFC_IER) AC6 Startup Time Interrupt Enable */\r
+#define ACIFC_IER_ACINT7 (0x1u << 14) /**< \brief (ACIFC_IER) AC7 Interrupt Enable */\r
+#define ACIFC_IER_SUTINT7 (0x1u << 15) /**< \brief (ACIFC_IER) AC7 Startup Time Interrupt Enable */\r
+#define ACIFC_IER_WFINT0 (0x1u << 24) /**< \brief (ACIFC_IER) Window0 Mode Interrupt Enable */\r
+#define ACIFC_IER_WFINT1 (0x1u << 25) /**< \brief (ACIFC_IER) Window1 Mode Interrupt Enable */\r
+#define ACIFC_IER_WFINT2 (0x1u << 26) /**< \brief (ACIFC_IER) Window2 Mode Interrupt Enable */\r
+#define ACIFC_IER_WFINT3 (0x1u << 27) /**< \brief (ACIFC_IER) Window3 Mode Interrupt Enable */\r
+/* -------- ACIFC_IDR : (ACIFC Offset: 0x14) Interrupt Disable Register -------- */\r
+#define ACIFC_IDR_ACINT0 (0x1u << 0) /**< \brief (ACIFC_IDR) AC0 Interrupt Disable */\r
+#define ACIFC_IDR_SUTINT0 (0x1u << 1) /**< \brief (ACIFC_IDR) AC0 Startup Time Interrupt Disable */\r
+#define ACIFC_IDR_ACINT1 (0x1u << 2) /**< \brief (ACIFC_IDR) AC1 Interrupt Disable */\r
+#define ACIFC_IDR_SUTINT1 (0x1u << 3) /**< \brief (ACIFC_IDR) AC1 Startup Time Interrupt Disable */\r
+#define ACIFC_IDR_ACINT2 (0x1u << 4) /**< \brief (ACIFC_IDR) AC2 Interrupt Disable */\r
+#define ACIFC_IDR_SUTINT2 (0x1u << 5) /**< \brief (ACIFC_IDR) AC2 Startup Time Interrupt Disable */\r
+#define ACIFC_IDR_ACINT3 (0x1u << 6) /**< \brief (ACIFC_IDR) AC3 Interrupt Disable */\r
+#define ACIFC_IDR_SUTINT3 (0x1u << 7) /**< \brief (ACIFC_IDR) AC3 Startup Time Interrupt Disable */\r
+#define ACIFC_IDR_ACINT4 (0x1u << 8) /**< \brief (ACIFC_IDR) AC4 Interrupt Disable */\r
+#define ACIFC_IDR_SUTINT4 (0x1u << 9) /**< \brief (ACIFC_IDR) AC4 Startup Time Interrupt Disable */\r
+#define ACIFC_IDR_ACINT5 (0x1u << 10) /**< \brief (ACIFC_IDR) AC5 Interrupt Disable */\r
+#define ACIFC_IDR_SUTINT5 (0x1u << 11) /**< \brief (ACIFC_IDR) AC5 Startup Time Interrupt Disable */\r
+#define ACIFC_IDR_ACINT6 (0x1u << 12) /**< \brief (ACIFC_IDR) AC6 Interrupt Disable */\r
+#define ACIFC_IDR_SUTINT6 (0x1u << 13) /**< \brief (ACIFC_IDR) AC6 Startup Time Interrupt Disable */\r
+#define ACIFC_IDR_ACINT7 (0x1u << 14) /**< \brief (ACIFC_IDR) AC7 Interrupt Disable */\r
+#define ACIFC_IDR_SUTINT7 (0x1u << 15) /**< \brief (ACIFC_IDR) AC7 Startup Time Interrupt Disable */\r
+#define ACIFC_IDR_WFINT0 (0x1u << 24) /**< \brief (ACIFC_IDR) Window0 Mode Interrupt Disable */\r
+#define ACIFC_IDR_WFINT1 (0x1u << 25) /**< \brief (ACIFC_IDR) Window1 Mode Interrupt Disable */\r
+#define ACIFC_IDR_WFINT2 (0x1u << 26) /**< \brief (ACIFC_IDR) Window2 Mode Interrupt Disable */\r
+#define ACIFC_IDR_WFINT3 (0x1u << 27) /**< \brief (ACIFC_IDR) Window3 Mode Interrupt Disable */\r
+/* -------- ACIFC_IMR : (ACIFC Offset: 0x18) Interrupt Mask Register -------- */\r
+#define ACIFC_IMR_ACINT0 (0x1u << 0) /**< \brief (ACIFC_IMR) AC0 Interrupt Mask */\r
+#define ACIFC_IMR_SUTINT0 (0x1u << 1) /**< \brief (ACIFC_IMR) AC0 Startup Time Interrupt Mask */\r
+#define ACIFC_IMR_ACINT1 (0x1u << 2) /**< \brief (ACIFC_IMR) AC1 Interrupt Mask */\r
+#define ACIFC_IMR_SUTINT1 (0x1u << 3) /**< \brief (ACIFC_IMR) AC1 Startup Time Interrupt Mask */\r
+#define ACIFC_IMR_ACINT2 (0x1u << 4) /**< \brief (ACIFC_IMR) AC2 Interrupt Mask */\r
+#define ACIFC_IMR_SUTINT2 (0x1u << 5) /**< \brief (ACIFC_IMR) AC2 Startup Time Interrupt Mask */\r
+#define ACIFC_IMR_ACINT3 (0x1u << 6) /**< \brief (ACIFC_IMR) AC3 Interrupt Mask */\r
+#define ACIFC_IMR_SUTINT3 (0x1u << 7) /**< \brief (ACIFC_IMR) AC3 Startup Time Interrupt Mask */\r
+#define ACIFC_IMR_ACINT4 (0x1u << 8) /**< \brief (ACIFC_IMR) AC4 Interrupt Mask */\r
+#define ACIFC_IMR_SUTINT4 (0x1u << 9) /**< \brief (ACIFC_IMR) AC4 Startup Time Interrupt Mask */\r
+#define ACIFC_IMR_ACINT5 (0x1u << 10) /**< \brief (ACIFC_IMR) AC5 Interrupt Mask */\r
+#define ACIFC_IMR_SUTINT5 (0x1u << 11) /**< \brief (ACIFC_IMR) AC5 Startup Time Interrupt Mask */\r
+#define ACIFC_IMR_ACINT6 (0x1u << 12) /**< \brief (ACIFC_IMR) AC6 Interrupt Mask */\r
+#define ACIFC_IMR_SUTINT6 (0x1u << 13) /**< \brief (ACIFC_IMR) AC6 Startup Time Interrupt Mask */\r
+#define ACIFC_IMR_ACINT7 (0x1u << 14) /**< \brief (ACIFC_IMR) AC7 Interrupt Mask */\r
+#define ACIFC_IMR_SUTINT7 (0x1u << 15) /**< \brief (ACIFC_IMR) AC7 Startup Time Interrupt Mask */\r
+#define ACIFC_IMR_WFINT0 (0x1u << 24) /**< \brief (ACIFC_IMR) Window0 Mode Interrupt Mask */\r
+#define ACIFC_IMR_WFINT1 (0x1u << 25) /**< \brief (ACIFC_IMR) Window1 Mode Interrupt Mask */\r
+#define ACIFC_IMR_WFINT2 (0x1u << 26) /**< \brief (ACIFC_IMR) Window2 Mode Interrupt Mask */\r
+#define ACIFC_IMR_WFINT3 (0x1u << 27) /**< \brief (ACIFC_IMR) Window3 Mode Interrupt Mask */\r
+/* -------- ACIFC_ISR : (ACIFC Offset: 0x1C) Interrupt Status Register -------- */\r
+#define ACIFC_ISR_ACINT0 (0x1u << 0) /**< \brief (ACIFC_ISR) AC0 Interrupt Status */\r
+#define ACIFC_ISR_SUTINT0 (0x1u << 1) /**< \brief (ACIFC_ISR) AC0 Startup Time Interrupt Status */\r
+#define ACIFC_ISR_ACINT1 (0x1u << 2) /**< \brief (ACIFC_ISR) AC1 Interrupt Status */\r
+#define ACIFC_ISR_SUTINT1 (0x1u << 3) /**< \brief (ACIFC_ISR) AC1 Startup Time Interrupt Status */\r
+#define ACIFC_ISR_ACINT2 (0x1u << 4) /**< \brief (ACIFC_ISR) AC2 Interrupt Status */\r
+#define ACIFC_ISR_SUTINT2 (0x1u << 5) /**< \brief (ACIFC_ISR) AC2 Startup Time Interrupt Status */\r
+#define ACIFC_ISR_ACINT3 (0x1u << 6) /**< \brief (ACIFC_ISR) AC3 Interrupt Status */\r
+#define ACIFC_ISR_SUTINT3 (0x1u << 7) /**< \brief (ACIFC_ISR) AC3 Startup Time Interrupt Status */\r
+#define ACIFC_ISR_ACINT4 (0x1u << 8) /**< \brief (ACIFC_ISR) AC4 Interrupt Status */\r
+#define ACIFC_ISR_SUTINT4 (0x1u << 9) /**< \brief (ACIFC_ISR) AC4 Startup Time Interrupt Status */\r
+#define ACIFC_ISR_ACINT5 (0x1u << 10) /**< \brief (ACIFC_ISR) AC5 Interrupt Status */\r
+#define ACIFC_ISR_SUTINT5 (0x1u << 11) /**< \brief (ACIFC_ISR) AC5 Startup Time Interrupt Status */\r
+#define ACIFC_ISR_ACINT6 (0x1u << 12) /**< \brief (ACIFC_ISR) AC6 Interrupt Status */\r
+#define ACIFC_ISR_SUTINT6 (0x1u << 13) /**< \brief (ACIFC_ISR) AC6 Startup Time Interrupt Status */\r
+#define ACIFC_ISR_ACINT7 (0x1u << 14) /**< \brief (ACIFC_ISR) AC7 Interrupt Status */\r
+#define ACIFC_ISR_SUTINT7 (0x1u << 15) /**< \brief (ACIFC_ISR) AC7 Startup Time Interrupt Status */\r
+#define ACIFC_ISR_WFINT0 (0x1u << 24) /**< \brief (ACIFC_ISR) Window0 Mode Interrupt Status */\r
+#define ACIFC_ISR_WFINT1 (0x1u << 25) /**< \brief (ACIFC_ISR) Window1 Mode Interrupt Status */\r
+#define ACIFC_ISR_WFINT2 (0x1u << 26) /**< \brief (ACIFC_ISR) Window2 Mode Interrupt Status */\r
+#define ACIFC_ISR_WFINT3 (0x1u << 27) /**< \brief (ACIFC_ISR) Window3 Mode Interrupt Status */\r
+/* -------- ACIFC_ICR : (ACIFC Offset: 0x20) Interrupt Status Clear Register -------- */\r
+#define ACIFC_ICR_ACINT0 (0x1u << 0) /**< \brief (ACIFC_ICR) AC0 Interrupt Status Clear */\r
+#define ACIFC_ICR_SUTINT0 (0x1u << 1) /**< \brief (ACIFC_ICR) AC0 Startup Time Interrupt Status Clear */\r
+#define ACIFC_ICR_ACINT1 (0x1u << 2) /**< \brief (ACIFC_ICR) AC1 Interrupt Status Clear */\r
+#define ACIFC_ICR_SUTINT1 (0x1u << 3) /**< \brief (ACIFC_ICR) AC1 Startup Time Interrupt Status Clear */\r
+#define ACIFC_ICR_ACINT2 (0x1u << 4) /**< \brief (ACIFC_ICR) AC2 Interrupt Status Clear */\r
+#define ACIFC_ICR_SUTINT2 (0x1u << 5) /**< \brief (ACIFC_ICR) AC2 Startup Time Interrupt Status Clear */\r
+#define ACIFC_ICR_ACINT3 (0x1u << 6) /**< \brief (ACIFC_ICR) AC3 Interrupt Status Clear */\r
+#define ACIFC_ICR_SUTINT3 (0x1u << 7) /**< \brief (ACIFC_ICR) AC3 Startup Time Interrupt Status Clear */\r
+#define ACIFC_ICR_ACINT4 (0x1u << 8) /**< \brief (ACIFC_ICR) AC4 Interrupt Status Clear */\r
+#define ACIFC_ICR_SUTINT4 (0x1u << 9) /**< \brief (ACIFC_ICR) AC4 Startup Time Interrupt Status Clear */\r
+#define ACIFC_ICR_ACINT5 (0x1u << 10) /**< \brief (ACIFC_ICR) AC5 Interrupt Status Clear */\r
+#define ACIFC_ICR_SUTINT5 (0x1u << 11) /**< \brief (ACIFC_ICR) AC5 Startup Time Interrupt Status Clear */\r
+#define ACIFC_ICR_ACINT6 (0x1u << 12) /**< \brief (ACIFC_ICR) AC6 Interrupt Status Clear */\r
+#define ACIFC_ICR_SUTINT6 (0x1u << 13) /**< \brief (ACIFC_ICR) AC6 Startup Time Interrupt Status Clear */\r
+#define ACIFC_ICR_ACINT7 (0x1u << 14) /**< \brief (ACIFC_ICR) AC7 Interrupt Status Clear */\r
+#define ACIFC_ICR_SUTINT7 (0x1u << 15) /**< \brief (ACIFC_ICR) AC7 Startup Time Interrupt Status Clear */\r
+#define ACIFC_ICR_WFINT0 (0x1u << 24) /**< \brief (ACIFC_ICR) Window0 Mode Interrupt Status Clear */\r
+#define ACIFC_ICR_WFINT1 (0x1u << 25) /**< \brief (ACIFC_ICR) Window1 Mode Interrupt Status Clear */\r
+#define ACIFC_ICR_WFINT2 (0x1u << 26) /**< \brief (ACIFC_ICR) Window2 Mode Interrupt Status Clear */\r
+#define ACIFC_ICR_WFINT3 (0x1u << 27) /**< \brief (ACIFC_ICR) Window3 Mode Interrupt Status Clear */\r
+/* -------- ACIFC_TR : (ACIFC Offset: 0x24) Test Register -------- */\r
+#define ACIFC_TR_ACTEST0 (0x1u << 0) /**< \brief (ACIFC_TR) AC0 Output Override Value */\r
+#define ACIFC_TR_ACTEST1 (0x1u << 1) /**< \brief (ACIFC_TR) AC1 Output Override Value */\r
+#define ACIFC_TR_ACTEST2 (0x1u << 2) /**< \brief (ACIFC_TR) AC2 Output Override Value */\r
+#define ACIFC_TR_ACTEST3 (0x1u << 3) /**< \brief (ACIFC_TR) AC3 Output Override Value */\r
+#define ACIFC_TR_ACTEST4 (0x1u << 4) /**< \brief (ACIFC_TR) AC4 Output Override Value */\r
+#define ACIFC_TR_ACTEST5 (0x1u << 5) /**< \brief (ACIFC_TR) AC5 Output Override Value */\r
+#define ACIFC_TR_ACTEST6 (0x1u << 6) /**< \brief (ACIFC_TR) AC6 Output Override Value */\r
+#define ACIFC_TR_ACTEST7 (0x1u << 7) /**< \brief (ACIFC_TR) AC7 Output Override Value */\r
+/* -------- ACIFC_PARAMETER : (ACIFC Offset: 0x30) Parameter Register -------- */\r
+#define ACIFC_PARAMETER_ACIMPL0 (0x1u << 0) /**< \brief (ACIFC_PARAMETER) Analog Comparator 0 Implemented */\r
+#define ACIFC_PARAMETER_ACIMPL1 (0x1u << 1) /**< \brief (ACIFC_PARAMETER) Analog Comparator 1 Implemented */\r
+#define ACIFC_PARAMETER_ACIMPL2 (0x1u << 2) /**< \brief (ACIFC_PARAMETER) Analog Comparator 2 Implemented */\r
+#define ACIFC_PARAMETER_ACIMPL3 (0x1u << 3) /**< \brief (ACIFC_PARAMETER) Analog Comparator 3 Implemented */\r
+#define ACIFC_PARAMETER_ACIMPL4 (0x1u << 4) /**< \brief (ACIFC_PARAMETER) Analog Comparator 4 Implemented */\r
+#define ACIFC_PARAMETER_ACIMPL5 (0x1u << 5) /**< \brief (ACIFC_PARAMETER) Analog Comparator 5 Implemented */\r
+#define ACIFC_PARAMETER_ACIMPL6 (0x1u << 6) /**< \brief (ACIFC_PARAMETER) Analog Comparator 6 Implemented */\r
+#define ACIFC_PARAMETER_ACIMPL7 (0x1u << 7) /**< \brief (ACIFC_PARAMETER) Analog Comparator 7 Implemented */\r
+#define ACIFC_PARAMETER_WIMPL0 (0x1u << 16) /**< \brief (ACIFC_PARAMETER) Window0 Mode Implemented */\r
+#define ACIFC_PARAMETER_WIMPL1 (0x1u << 17) /**< \brief (ACIFC_PARAMETER) Window1 Mode Implemented */\r
+#define ACIFC_PARAMETER_WIMPL2 (0x1u << 18) /**< \brief (ACIFC_PARAMETER) Window2 Mode Implemented */\r
+#define ACIFC_PARAMETER_WIMPL3 (0x1u << 19) /**< \brief (ACIFC_PARAMETER) Window3 Mode Implemented */\r
+/* -------- ACIFC_VERSION : (ACIFC Offset: 0x34) Version Register -------- */\r
+#define ACIFC_VERSION_VERSION_Pos 0\r
+#define ACIFC_VERSION_VERSION_Msk (0xFFFu << ACIFC_VERSION_VERSION_Pos) /**< \brief (ACIFC_VERSION) Version Number */\r
+#define ACIFC_VERSION_VERSION(value) ((ACIFC_VERSION_VERSION_Msk & ((value) << ACIFC_VERSION_VERSION_Pos)))\r
+#define ACIFC_VERSION_VARIANT_Pos 16\r
+#define ACIFC_VERSION_VARIANT_Msk (0xFu << ACIFC_VERSION_VARIANT_Pos) /**< \brief (ACIFC_VERSION) Variant Number */\r
+#define ACIFC_VERSION_VARIANT(value) ((ACIFC_VERSION_VARIANT_Msk & ((value) << ACIFC_VERSION_VARIANT_Pos)))\r
+/* -------- ACIFC_CONFW : (ACIFC Offset: 0x80) Confw Window configuration Register -------- */\r
+#define ACIFC_CONFW_WIS_Pos 0\r
+#define ACIFC_CONFW_WIS_Msk (0x7u << ACIFC_CONFW_WIS_Pos) /**< \brief (ACIFC_CONFW) Window Mode Interrupt Settings */\r
+#define ACIFC_CONFW_WIS(value) ((ACIFC_CONFW_WIS_Msk & ((value) << ACIFC_CONFW_WIS_Pos)))\r
+#define ACIFC_CONFW_WEVSRC_Pos 8\r
+#define ACIFC_CONFW_WEVSRC_Msk (0x7u << ACIFC_CONFW_WEVSRC_Pos) /**< \brief (ACIFC_CONFW) Peripheral Event Sourse Selection for Window Mode */\r
+#define ACIFC_CONFW_WEVSRC(value) ((ACIFC_CONFW_WEVSRC_Msk & ((value) << ACIFC_CONFW_WEVSRC_Pos)))\r
+#define ACIFC_CONFW_WEVEN (0x1u << 11) /**< \brief (ACIFC_CONFW) Window Peripheral Event Enable */\r
+#define ACIFC_CONFW_WFEN (0x1u << 16) /**< \brief (ACIFC_CONFW) Window Mode Enable */\r
+/* -------- ACIFC_CONF : (ACIFC Offset: 0xD0) Conf AC Configuration Register -------- */\r
+#define ACIFC_CONF_IS_Pos 0\r
+#define ACIFC_CONF_IS_Msk (0x3u << ACIFC_CONF_IS_Pos) /**< \brief (ACIFC_CONF) Interupt Settings */\r
+#define ACIFC_CONF_IS(value) ((ACIFC_CONF_IS_Msk & ((value) << ACIFC_CONF_IS_Pos)))\r
+#define ACIFC_CONF_MODE_Pos 4\r
+#define ACIFC_CONF_MODE_Msk (0x3u << ACIFC_CONF_MODE_Pos) /**< \brief (ACIFC_CONF) Analog Comparator Mode */\r
+#define ACIFC_CONF_MODE(value) ((ACIFC_CONF_MODE_Msk & ((value) << ACIFC_CONF_MODE_Pos)))\r
+#define ACIFC_CONF_INSELN_Pos 8\r
+#define ACIFC_CONF_INSELN_Msk (0x3u << ACIFC_CONF_INSELN_Pos) /**< \brief (ACIFC_CONF) Negative Input Select */\r
+#define ACIFC_CONF_INSELN(value) ((ACIFC_CONF_INSELN_Msk & ((value) << ACIFC_CONF_INSELN_Pos)))\r
+#define ACIFC_CONF_EVENN (0x1u << 16) /**< \brief (ACIFC_CONF) Peripheral Event Enable Negative */\r
+#define ACIFC_CONF_EVENP (0x1u << 17) /**< \brief (ACIFC_CONF) Peripheral Event Enable Positive */\r
+#define ACIFC_CONF_HYS_Pos 24\r
+#define ACIFC_CONF_HYS_Msk (0x3u << ACIFC_CONF_HYS_Pos) /**< \brief (ACIFC_CONF) Hysteresis Voltage Value */\r
+#define ACIFC_CONF_HYS(value) ((ACIFC_CONF_HYS_Msk & ((value) << ACIFC_CONF_HYS_Pos)))\r
+#define ACIFC_CONF_FAST (0x1u << 26) /**< \brief (ACIFC_CONF) Fast Mode Enable */\r
+#define ACIFC_CONF_ALWAYSON (0x1u << 27) /**< \brief (ACIFC_CONF) Always On */\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR ADCIFE */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_ADCIFE ADC controller interface */\r
+/*@{*/\r
+\r
+#define REV_ADCIFE 0x100\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief ADCIFE hardware registers */\r
+typedef struct {\r
+ WoReg ADCIFE_CR; /**< \brief (ADCIFE Offset: 0x00) Control Register */\r
+ RwReg ADCIFE_CFG; /**< \brief (ADCIFE Offset: 0x04) Configuration Register */\r
+ RoReg ADCIFE_SR; /**< \brief (ADCIFE Offset: 0x08) Status Register */\r
+ WoReg ADCIFE_SCR; /**< \brief (ADCIFE Offset: 0x0C) Status Clear Register */\r
+ RwReg ADCIFE_RTS; /**< \brief (ADCIFE Offset: 0x10) Resistive Touch Screen Register */\r
+ RwReg ADCIFE_SEQCFG; /**< \brief (ADCIFE Offset: 0x14) Sequencer Configuration Register */\r
+ WoReg ADCIFE_CDMA; /**< \brief (ADCIFE Offset: 0x18) Configuration Direct Memory Access Register */\r
+ RwReg ADCIFE_TIM; /**< \brief (ADCIFE Offset: 0x1C) Timing Configuration Register */\r
+ RwReg ADCIFE_ITIMER; /**< \brief (ADCIFE Offset: 0x20) Internal Timer Register */\r
+ RwReg ADCIFE_WCFG; /**< \brief (ADCIFE Offset: 0x24) Window Monitor Configuration Register */\r
+ RwReg ADCIFE_WTH; /**< \brief (ADCIFE Offset: 0x28) Window Monitor Threshold Configuration Register */\r
+ RoReg ADCIFE_LCV; /**< \brief (ADCIFE Offset: 0x2C) Sequencer Last Converted Value Register */\r
+ WoReg ADCIFE_IER; /**< \brief (ADCIFE Offset: 0x30) Interrupt Enable Register */\r
+ WoReg ADCIFE_IDR; /**< \brief (ADCIFE Offset: 0x34) Interrupt Disable Register */\r
+ RoReg ADCIFE_IMR; /**< \brief (ADCIFE Offset: 0x38) Interrupt Mask Register */\r
+ RwReg ADCIFE_CALIB; /**< \brief (ADCIFE Offset: 0x3C) Calibration Register */\r
+ RoReg ADCIFE_VERSION; /**< \brief (ADCIFE Offset: 0x40) Version Register */\r
+ RoReg ADCIFE_PARAMETER; /**< \brief (ADCIFE Offset: 0x44) Parameter Register */\r
+} Adcife;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- ADCIFE_CR : (ADCIFE Offset: 0x00) Control Register -------- */\r
+#define ADCIFE_CR_SWRST (0x1u << 0) /**< \brief (ADCIFE_CR) Software reset */\r
+#define ADCIFE_CR_TSTOP (0x1u << 1) /**< \brief (ADCIFE_CR) Internal timer stop bit */\r
+#define ADCIFE_CR_TSTART (0x1u << 2) /**< \brief (ADCIFE_CR) Internal timer start bit */\r
+#define ADCIFE_CR_STRIG (0x1u << 3) /**< \brief (ADCIFE_CR) Sequencer trigger */\r
+#define ADCIFE_CR_REFBUFEN (0x1u << 4) /**< \brief (ADCIFE_CR) Reference buffer enable */\r
+#define ADCIFE_CR_REFBUFDIS (0x1u << 5) /**< \brief (ADCIFE_CR) Reference buffer disable */\r
+#define ADCIFE_CR_EN (0x1u << 8) /**< \brief (ADCIFE_CR) ADCIFD enable */\r
+#define ADCIFE_CR_DIS (0x1u << 9) /**< \brief (ADCIFE_CR) ADCIFD disable */\r
+#define ADCIFE_CR_BGREQEN (0x1u << 10) /**< \brief (ADCIFE_CR) Bandgap buffer request enable */\r
+#define ADCIFE_CR_BGREQDIS (0x1u << 11) /**< \brief (ADCIFE_CR) Bandgap buffer request disable */\r
+/* -------- ADCIFE_CFG : (ADCIFE Offset: 0x04) Configuration Register -------- */\r
+#define ADCIFE_CFG_REFSEL_Pos 1\r
+#define ADCIFE_CFG_REFSEL_Msk (0x7u << ADCIFE_CFG_REFSEL_Pos) /**< \brief (ADCIFE_CFG) ADC Reference Selection */\r
+#define ADCIFE_CFG_REFSEL(value) ((ADCIFE_CFG_REFSEL_Msk & ((value) << ADCIFE_CFG_REFSEL_Pos)))\r
+#define ADCIFE_CFG_SPEED_Pos 4\r
+#define ADCIFE_CFG_SPEED_Msk (0x3u << ADCIFE_CFG_SPEED_Pos) /**< \brief (ADCIFE_CFG) ADC current reduction */\r
+#define ADCIFE_CFG_SPEED(value) ((ADCIFE_CFG_SPEED_Msk & ((value) << ADCIFE_CFG_SPEED_Pos)))\r
+#define ADCIFE_CFG_CLKSEL (0x1u << 6) /**< \brief (ADCIFE_CFG) Clock Selection for sequencer/ADC cell */\r
+#define ADCIFE_CFG_PRESCAL_Pos 8\r
+#define ADCIFE_CFG_PRESCAL_Msk (0x7u << ADCIFE_CFG_PRESCAL_Pos) /**< \brief (ADCIFE_CFG) Prescaler Rate Selection */\r
+#define ADCIFE_CFG_PRESCAL(value) ((ADCIFE_CFG_PRESCAL_Msk & ((value) << ADCIFE_CFG_PRESCAL_Pos)))\r
+/* -------- ADCIFE_SR : (ADCIFE Offset: 0x08) Status Register -------- */\r
+#define ADCIFE_SR_SEOC (0x1u << 0) /**< \brief (ADCIFE_SR) Sequencer end of conversion */\r
+#define ADCIFE_SR_LOVR (0x1u << 1) /**< \brief (ADCIFE_SR) Sequencer last converted value overrun */\r
+#define ADCIFE_SR_WM (0x1u << 2) /**< \brief (ADCIFE_SR) Window monitor */\r
+#define ADCIFE_SR_SMTRG (0x1u << 3) /**< \brief (ADCIFE_SR) Sequencer missed trigger event */\r
+#define ADCIFE_SR_SUTD (0x1u << 4) /**< \brief (ADCIFE_SR) Start-up time done */\r
+#define ADCIFE_SR_TTO (0x1u << 5) /**< \brief (ADCIFE_SR) Timer time-out */\r
+#define ADCIFE_SR_EN (0x1u << 24) /**< \brief (ADCIFE_SR) Enable Status */\r
+#define ADCIFE_SR_TBUSY (0x1u << 25) /**< \brief (ADCIFE_SR) Timer busy */\r
+#define ADCIFE_SR_SBUSY (0x1u << 26) /**< \brief (ADCIFE_SR) Sequencer busy */\r
+#define ADCIFE_SR_CBUSY (0x1u << 27) /**< \brief (ADCIFE_SR) Conversion busy */\r
+#define ADCIFE_SR_REFBUF (0x1u << 28) /**< \brief (ADCIFE_SR) Reference buffer status */\r
+/* -------- ADCIFE_SCR : (ADCIFE Offset: 0x0C) Status Clear Register -------- */\r
+#define ADCIFE_SCR_SEOC (0x1u << 0) /**< \brief (ADCIFE_SCR) Sequencer end of conversion */\r
+#define ADCIFE_SCR_LOVR (0x1u << 1) /**< \brief (ADCIFE_SCR) Sequencer last converted value overrun */\r
+#define ADCIFE_SCR_WM (0x1u << 2) /**< \brief (ADCIFE_SCR) Window monitor */\r
+#define ADCIFE_SCR_SMTRG (0x1u << 3) /**< \brief (ADCIFE_SCR) Sequencer missed trigger event */\r
+#define ADCIFE_SCR_SUTD (0x1u << 4) /**< \brief (ADCIFE_SCR) Start-up time done */\r
+#define ADCIFE_SCR_TTO (0x1u << 5) /**< \brief (ADCIFE_SCR) Timer time-out */\r
+/* -------- ADCIFE_RTS : (ADCIFE Offset: 0x10) Resistive Touch Screen Register -------- */\r
+/* -------- ADCIFE_SEQCFG : (ADCIFE Offset: 0x14) Sequencer Configuration Register -------- */\r
+#define ADCIFE_SEQCFG_HWLA (0x1u << 0) /**< \brief (ADCIFE_SEQCFG) Half word left adjust */\r
+#define ADCIFE_SEQCFG_BIPOLAR (0x1u << 2) /**< \brief (ADCIFE_SEQCFG) Bipolar Mode */\r
+#define ADCIFE_SEQCFG_GAIN_Pos 4\r
+#define ADCIFE_SEQCFG_GAIN_Msk (0x7u << ADCIFE_SEQCFG_GAIN_Pos) /**< \brief (ADCIFE_SEQCFG) Gain factor */\r
+#define ADCIFE_SEQCFG_GAIN(value) ((ADCIFE_SEQCFG_GAIN_Msk & ((value) << ADCIFE_SEQCFG_GAIN_Pos)))\r
+#define ADCIFE_SEQCFG_GCOMP (0x1u << 7) /**< \brief (ADCIFE_SEQCFG) Gain Compensation */\r
+#define ADCIFE_SEQCFG_TRGSEL_Pos 8\r
+#define ADCIFE_SEQCFG_TRGSEL_Msk (0x7u << ADCIFE_SEQCFG_TRGSEL_Pos) /**< \brief (ADCIFE_SEQCFG) Trigger selection */\r
+#define ADCIFE_SEQCFG_TRGSEL(value) ((ADCIFE_SEQCFG_TRGSEL_Msk & ((value) << ADCIFE_SEQCFG_TRGSEL_Pos)))\r
+#define ADCIFE_SEQCFG_RES (0x1u << 12) /**< \brief (ADCIFE_SEQCFG) Resolution */\r
+#define ADCIFE_SEQCFG_INTERNAL_Pos 14\r
+#define ADCIFE_SEQCFG_INTERNAL_Msk (0x3u << ADCIFE_SEQCFG_INTERNAL_Pos) /**< \brief (ADCIFE_SEQCFG) Internal Voltage Source Selection */\r
+#define ADCIFE_SEQCFG_INTERNAL(value) ((ADCIFE_SEQCFG_INTERNAL_Msk & ((value) << ADCIFE_SEQCFG_INTERNAL_Pos)))\r
+#define ADCIFE_SEQCFG_MUXPOS_Pos 16\r
+#define ADCIFE_SEQCFG_MUXPOS_Msk (0xFu << ADCIFE_SEQCFG_MUXPOS_Pos) /**< \brief (ADCIFE_SEQCFG) MUX selection on Positive ADC input channel */\r
+#define ADCIFE_SEQCFG_MUXPOS(value) ((ADCIFE_SEQCFG_MUXPOS_Msk & ((value) << ADCIFE_SEQCFG_MUXPOS_Pos)))\r
+#define ADCIFE_SEQCFG_MUXNEG_Pos 20\r
+#define ADCIFE_SEQCFG_MUXNEG_Msk (0x7u << ADCIFE_SEQCFG_MUXNEG_Pos) /**< \brief (ADCIFE_SEQCFG) MUX selection on Negative ADC input channel */\r
+#define ADCIFE_SEQCFG_MUXNEG(value) ((ADCIFE_SEQCFG_MUXNEG_Msk & ((value) << ADCIFE_SEQCFG_MUXNEG_Pos)))\r
+#define ADCIFE_SEQCFG_ZOOMRANGE_Pos 28\r
+#define ADCIFE_SEQCFG_ZOOMRANGE_Msk (0x7u << ADCIFE_SEQCFG_ZOOMRANGE_Pos) /**< \brief (ADCIFE_SEQCFG) Zoom shift/unipolar reference source selection */\r
+#define ADCIFE_SEQCFG_ZOOMRANGE(value) ((ADCIFE_SEQCFG_ZOOMRANGE_Msk & ((value) << ADCIFE_SEQCFG_ZOOMRANGE_Pos)))\r
+/* -------- ADCIFE_FIRST_DMA_WORD_CDMA : (ADCIFE Offset: 0x18) Configuration Direct Memory Access Register -------- */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_HWLA (0x1u << 0) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_BIPOLAR (0x1u << 2) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_STRIG (0x1u << 3) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_GAIN_Pos 4\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_GAIN_Msk (0x7u << ADCIFE_FIRST_DMA_WORD_CDMA_GAIN_Pos) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_GAIN(value) ((ADCIFE_FIRST_DMA_WORD_CDMA_GAIN_Msk & ((value) << ADCIFE_FIRST_DMA_WORD_CDMA_GAIN_Pos)))\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_GCOMP (0x1u << 7) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_ENSTUP (0x1u << 8) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_RES (0x1u << 12) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_TSS (0x1u << 13) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) Internal timer start or stop bit */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_INTERNAL_Pos 14\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_INTERNAL_Msk (0x3u << ADCIFE_FIRST_DMA_WORD_CDMA_INTERNAL_Pos) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_INTERNAL(value) ((ADCIFE_FIRST_DMA_WORD_CDMA_INTERNAL_Msk & ((value) << ADCIFE_FIRST_DMA_WORD_CDMA_INTERNAL_Pos)))\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_MUXPOS_Pos 16\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_MUXPOS_Msk (0xFu << ADCIFE_FIRST_DMA_WORD_CDMA_MUXPOS_Pos) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_MUXPOS(value) ((ADCIFE_FIRST_DMA_WORD_CDMA_MUXPOS_Msk & ((value) << ADCIFE_FIRST_DMA_WORD_CDMA_MUXPOS_Pos)))\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_MUXNEG_Pos 20\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_MUXNEG_Msk (0x7u << ADCIFE_FIRST_DMA_WORD_CDMA_MUXNEG_Pos) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_MUXNEG(value) ((ADCIFE_FIRST_DMA_WORD_CDMA_MUXNEG_Msk & ((value) << ADCIFE_FIRST_DMA_WORD_CDMA_MUXNEG_Pos)))\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_ZOOMRANGE_Pos 28\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_ZOOMRANGE_Msk (0x7u << ADCIFE_FIRST_DMA_WORD_CDMA_ZOOMRANGE_Pos) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) */\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_ZOOMRANGE(value) ((ADCIFE_FIRST_DMA_WORD_CDMA_ZOOMRANGE_Msk & ((value) << ADCIFE_FIRST_DMA_WORD_CDMA_ZOOMRANGE_Pos)))\r
+#define ADCIFE_FIRST_DMA_WORD_CDMA_DW (0x1u << 31) /**< \brief (ADCIFE_FIRST_DMA_WORD_CDMA) Double Word transmitting */\r
+/* -------- ADCIFE_SECOND_DMA_WORD_CDMA : (ADCIFE Offset: 0x18) Configuration Direct Memory Access Register -------- */\r
+#define ADCIFE_SECOND_DMA_WORD_CDMA_LT_Pos 0\r
+#define ADCIFE_SECOND_DMA_WORD_CDMA_LT_Msk (0xFFFu << ADCIFE_SECOND_DMA_WORD_CDMA_LT_Pos) /**< \brief (ADCIFE_SECOND_DMA_WORD_CDMA) */\r
+#define ADCIFE_SECOND_DMA_WORD_CDMA_LT(value) ((ADCIFE_SECOND_DMA_WORD_CDMA_LT_Msk & ((value) << ADCIFE_SECOND_DMA_WORD_CDMA_LT_Pos)))\r
+#define ADCIFE_SECOND_DMA_WORD_CDMA_WM_Pos 12\r
+#define ADCIFE_SECOND_DMA_WORD_CDMA_WM_Msk (0x7u << ADCIFE_SECOND_DMA_WORD_CDMA_WM_Pos) /**< \brief (ADCIFE_SECOND_DMA_WORD_CDMA) */\r
+#define ADCIFE_SECOND_DMA_WORD_CDMA_WM(value) ((ADCIFE_SECOND_DMA_WORD_CDMA_WM_Msk & ((value) << ADCIFE_SECOND_DMA_WORD_CDMA_WM_Pos)))\r
+#define ADCIFE_SECOND_DMA_WORD_CDMA_HT_Pos 16\r
+#define ADCIFE_SECOND_DMA_WORD_CDMA_HT_Msk (0xFFFu << ADCIFE_SECOND_DMA_WORD_CDMA_HT_Pos) /**< \brief (ADCIFE_SECOND_DMA_WORD_CDMA) */\r
+#define ADCIFE_SECOND_DMA_WORD_CDMA_HT(value) ((ADCIFE_SECOND_DMA_WORD_CDMA_HT_Msk & ((value) << ADCIFE_SECOND_DMA_WORD_CDMA_HT_Pos)))\r
+#define ADCIFE_SECOND_DMA_WORD_CDMA_DW (0x1u << 31) /**< \brief (ADCIFE_SECOND_DMA_WORD_CDMA) */\r
+/* -------- ADCIFE_CDMA : (ADCIFE Offset: 0x18) Configuration Direct Memory Access Register -------- */\r
+#define ADCIFE_CDMA_HWLA (0x1u << 0) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_LT_Pos 0\r
+#define ADCIFE_CDMA_LT_Msk (0xFFFu << ADCIFE_CDMA_LT_Pos) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_LT(value) ((ADCIFE_CDMA_LT_Msk & ((value) << ADCIFE_CDMA_LT_Pos)))\r
+#define ADCIFE_CDMA_BIPOLAR (0x1u << 2) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_STRIG (0x1u << 3) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_GAIN_Pos 4\r
+#define ADCIFE_CDMA_GAIN_Msk (0x7u << ADCIFE_CDMA_GAIN_Pos) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_GAIN(value) ((ADCIFE_CDMA_GAIN_Msk & ((value) << ADCIFE_CDMA_GAIN_Pos)))\r
+#define ADCIFE_CDMA_GCOMP (0x1u << 7) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_ENSTUP (0x1u << 8) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_RES (0x1u << 12) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_WM_Pos 12\r
+#define ADCIFE_CDMA_WM_Msk (0x7u << ADCIFE_CDMA_WM_Pos) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_WM(value) ((ADCIFE_CDMA_WM_Msk & ((value) << ADCIFE_CDMA_WM_Pos)))\r
+#define ADCIFE_CDMA_TSS (0x1u << 13) /**< \brief (ADCIFE_CDMA) Internal timer start or stop bit */\r
+#define ADCIFE_CDMA_INTERNAL_Pos 14\r
+#define ADCIFE_CDMA_INTERNAL_Msk (0x3u << ADCIFE_CDMA_INTERNAL_Pos) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_INTERNAL(value) ((ADCIFE_CDMA_INTERNAL_Msk & ((value) << ADCIFE_CDMA_INTERNAL_Pos)))\r
+#define ADCIFE_CDMA_MUXPOS_Pos 16\r
+#define ADCIFE_CDMA_MUXPOS_Msk (0xFu << ADCIFE_CDMA_MUXPOS_Pos) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_MUXPOS(value) ((ADCIFE_CDMA_MUXPOS_Msk & ((value) << ADCIFE_CDMA_MUXPOS_Pos)))\r
+#define ADCIFE_CDMA_HT_Pos 16\r
+#define ADCIFE_CDMA_HT_Msk (0xFFFu << ADCIFE_CDMA_HT_Pos) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_HT(value) ((ADCIFE_CDMA_HT_Msk & ((value) << ADCIFE_CDMA_HT_Pos)))\r
+#define ADCIFE_CDMA_MUXNEG_Pos 20\r
+#define ADCIFE_CDMA_MUXNEG_Msk (0x7u << ADCIFE_CDMA_MUXNEG_Pos) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_MUXNEG(value) ((ADCIFE_CDMA_MUXNEG_Msk & ((value) << ADCIFE_CDMA_MUXNEG_Pos)))\r
+#define ADCIFE_CDMA_ZOOMRANGE_Pos 28\r
+#define ADCIFE_CDMA_ZOOMRANGE_Msk (0x7u << ADCIFE_CDMA_ZOOMRANGE_Pos) /**< \brief (ADCIFE_CDMA) */\r
+#define ADCIFE_CDMA_ZOOMRANGE(value) ((ADCIFE_CDMA_ZOOMRANGE_Msk & ((value) << ADCIFE_CDMA_ZOOMRANGE_Pos)))\r
+#define ADCIFE_CDMA_DW (0x1u << 31) /**< \brief (ADCIFE_CDMA) Double Word transmitting */\r
+\r
+/* -------- ADCIFE_TIM : (ADCIFE Offset: 0x1C) Timing Configuration Register -------- */\r
+#define ADCIFE_TIM_STARTUP_Pos 0\r
+#define ADCIFE_TIM_STARTUP_Msk (0x1Fu << ADCIFE_TIM_STARTUP_Pos) /**< \brief (ADCIFE_TIM) Startup time */\r
+#define ADCIFE_TIM_STARTUP(value) ((ADCIFE_TIM_STARTUP_Msk & ((value) << ADCIFE_TIM_STARTUP_Pos)))\r
+#define ADCIFE_TIM_ENSTUP (0x1u << 8) /**< \brief (ADCIFE_TIM) Enable Startup */\r
+/* -------- ADCIFE_ITIMER : (ADCIFE Offset: 0x20) Internal Timer Register -------- */\r
+#define ADCIFE_ITIMER_ITMC_Pos 0\r
+#define ADCIFE_ITIMER_ITMC_Msk (0xFFFFu << ADCIFE_ITIMER_ITMC_Pos) /**< \brief (ADCIFE_ITIMER) Internal timer max counter */\r
+#define ADCIFE_ITIMER_ITMC(value) ((ADCIFE_ITIMER_ITMC_Msk & ((value) << ADCIFE_ITIMER_ITMC_Pos)))\r
+/* -------- ADCIFE_WCFG : (ADCIFE Offset: 0x24) Window Monitor Configuration Register -------- */\r
+#define ADCIFE_WCFG_WM_Pos 12\r
+#define ADCIFE_WCFG_WM_Msk (0x7u << ADCIFE_WCFG_WM_Pos) /**< \brief (ADCIFE_WCFG) Window Monitor Mode */\r
+#define ADCIFE_WCFG_WM(value) ((ADCIFE_WCFG_WM_Msk & ((value) << ADCIFE_WCFG_WM_Pos)))\r
+/* -------- ADCIFE_WTH : (ADCIFE Offset: 0x28) Window Monitor Threshold Configuration Register -------- */\r
+#define ADCIFE_WTH_LT_Pos 0\r
+#define ADCIFE_WTH_LT_Msk (0xFFFu << ADCIFE_WTH_LT_Pos) /**< \brief (ADCIFE_WTH) Low threshold */\r
+#define ADCIFE_WTH_LT(value) ((ADCIFE_WTH_LT_Msk & ((value) << ADCIFE_WTH_LT_Pos)))\r
+#define ADCIFE_WTH_HT_Pos 16\r
+#define ADCIFE_WTH_HT_Msk (0xFFFu << ADCIFE_WTH_HT_Pos) /**< \brief (ADCIFE_WTH) High Threshold */\r
+#define ADCIFE_WTH_HT(value) ((ADCIFE_WTH_HT_Msk & ((value) << ADCIFE_WTH_HT_Pos)))\r
+/* -------- ADCIFE_LCV : (ADCIFE Offset: 0x2C) Sequencer Last Converted Value Register -------- */\r
+#define ADCIFE_LCV_LCV_Pos 0\r
+#define ADCIFE_LCV_LCV_Msk (0xFFFFu << ADCIFE_LCV_LCV_Pos) /**< \brief (ADCIFE_LCV) Last converted value */\r
+#define ADCIFE_LCV_LCV(value) ((ADCIFE_LCV_LCV_Msk & ((value) << ADCIFE_LCV_LCV_Pos)))\r
+#define ADCIFE_LCV_LCPC_Pos 16\r
+#define ADCIFE_LCV_LCPC_Msk (0xFu << ADCIFE_LCV_LCPC_Pos) /**< \brief (ADCIFE_LCV) Last converted positive channel */\r
+#define ADCIFE_LCV_LCPC(value) ((ADCIFE_LCV_LCPC_Msk & ((value) << ADCIFE_LCV_LCPC_Pos)))\r
+#define ADCIFE_LCV_LCNC_Pos 20\r
+#define ADCIFE_LCV_LCNC_Msk (0x7u << ADCIFE_LCV_LCNC_Pos) /**< \brief (ADCIFE_LCV) Last converted negative channel */\r
+#define ADCIFE_LCV_LCNC(value) ((ADCIFE_LCV_LCNC_Msk & ((value) << ADCIFE_LCV_LCNC_Pos)))\r
+/* -------- ADCIFE_IER : (ADCIFE Offset: 0x30) Interrupt Enable Register -------- */\r
+#define ADCIFE_IER_SEOC (0x1u << 0) /**< \brief (ADCIFE_IER) Sequencer end of conversion Interrupt Enable */\r
+#define ADCIFE_IER_LOVR (0x1u << 1) /**< \brief (ADCIFE_IER) Sequencer last converted value overrun Interrupt Enable */\r
+#define ADCIFE_IER_WM (0x1u << 2) /**< \brief (ADCIFE_IER) Window monitor Interrupt Enable */\r
+#define ADCIFE_IER_SMTRG (0x1u << 3) /**< \brief (ADCIFE_IER) Sequencer missed trigger event Interrupt Enable */\r
+#define ADCIFE_IER_TTO (0x1u << 5) /**< \brief (ADCIFE_IER) Timer time-out Interrupt Enable */\r
+/* -------- ADCIFE_IDR : (ADCIFE Offset: 0x34) Interrupt Disable Register -------- */\r
+#define ADCIFE_IDR_SEOC (0x1u << 0) /**< \brief (ADCIFE_IDR) Sequencer end of conversion Interrupt Disable */\r
+#define ADCIFE_IDR_LOVR (0x1u << 1) /**< \brief (ADCIFE_IDR) Sequencer last converted value overrun Interrupt Disable */\r
+#define ADCIFE_IDR_WM (0x1u << 2) /**< \brief (ADCIFE_IDR) Window monitor Interrupt Disable */\r
+#define ADCIFE_IDR_SMTRG (0x1u << 3) /**< \brief (ADCIFE_IDR) Sequencer missed trigger event Interrupt Disable */\r
+#define ADCIFE_IDR_TTO (0x1u << 5) /**< \brief (ADCIFE_IDR) Timer time-out Interrupt Disable */\r
+/* -------- ADCIFE_IMR : (ADCIFE Offset: 0x38) Interrupt Mask Register -------- */\r
+#define ADCIFE_IMR_SEOC (0x1u << 0) /**< \brief (ADCIFE_IMR) Sequencer end of conversion Interrupt Mask */\r
+#define ADCIFE_IMR_LOVR (0x1u << 1) /**< \brief (ADCIFE_IMR) Sequencer last converted value overrun Interrupt Mask */\r
+#define ADCIFE_IMR_WM (0x1u << 2) /**< \brief (ADCIFE_IMR) Window monitor Interrupt Mask */\r
+#define ADCIFE_IMR_SMTRG (0x1u << 3) /**< \brief (ADCIFE_IMR) Sequencer missed trigger event Interrupt Mask */\r
+#define ADCIFE_IMR_TTO (0x1u << 5) /**< \brief (ADCIFE_IMR) Timer time-out Interrupt Mask */\r
+/* -------- ADCIFE_CALIB : (ADCIFE Offset: 0x3C) Calibration Register -------- */\r
+#define ADCIFE_CALIB_CALIB_Pos 0\r
+#define ADCIFE_CALIB_CALIB_Msk (0xFFu << ADCIFE_CALIB_CALIB_Pos) /**< \brief (ADCIFE_CALIB) Calibration Value */\r
+#define ADCIFE_CALIB_CALIB(value) ((ADCIFE_CALIB_CALIB_Msk & ((value) << ADCIFE_CALIB_CALIB_Pos)))\r
+#define ADCIFE_CALIB_BIASSEL (0x1u << 8) /**< \brief (ADCIFE_CALIB) Select bias mode */\r
+#define ADCIFE_CALIB_BIASCAL_Pos 12\r
+#define ADCIFE_CALIB_BIASCAL_Msk (0xFu << ADCIFE_CALIB_BIASCAL_Pos) /**< \brief (ADCIFE_CALIB) Bias Calibration */\r
+#define ADCIFE_CALIB_BIASCAL(value) ((ADCIFE_CALIB_BIASCAL_Msk & ((value) << ADCIFE_CALIB_BIASCAL_Pos)))\r
+#define ADCIFE_CALIB_FCD (0x1u << 16) /**< \brief (ADCIFE_CALIB) Flash Calibration Done */\r
+/* -------- ADCIFE_VERSION : (ADCIFE Offset: 0x40) Version Register -------- */\r
+#define ADCIFE_VERSION_VERSION_Pos 0\r
+#define ADCIFE_VERSION_VERSION_Msk (0xFFFu << ADCIFE_VERSION_VERSION_Pos) /**< \brief (ADCIFE_VERSION) Version number */\r
+#define ADCIFE_VERSION_VERSION(value) ((ADCIFE_VERSION_VERSION_Msk & ((value) << ADCIFE_VERSION_VERSION_Pos)))\r
+#define ADCIFE_VERSION_VARIANT_Pos 16\r
+#define ADCIFE_VERSION_VARIANT_Msk (0xFu << ADCIFE_VERSION_VARIANT_Pos) /**< \brief (ADCIFE_VERSION) Variant number */\r
+#define ADCIFE_VERSION_VARIANT(value) ((ADCIFE_VERSION_VARIANT_Msk & ((value) << ADCIFE_VERSION_VARIANT_Pos)))\r
+/* -------- ADCIFE_PARAMETER : (ADCIFE Offset: 0x44) Parameter Register -------- */\r
+#define ADCIFE_PARAMETER_N_Pos 0\r
+#define ADCIFE_PARAMETER_N_Msk (0xFFu << ADCIFE_PARAMETER_N_Pos) /**< \brief (ADCIFE_PARAMETER) Number of channels */\r
+#define ADCIFE_PARAMETER_N(value) ((ADCIFE_PARAMETER_N_Msk & ((value) << ADCIFE_PARAMETER_N_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR AESA */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_AESA Advanced Encryption Standard */\r
+/*@{*/\r
+\r
+#define REV_AESA 0x102\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief AesaInitvect hardware registers */\r
+typedef struct {\r
+ WoReg AESA_INITVECT; /**< \brief (AesaInitvect Offset: 0x00) Initialization Vector Register 0 */\r
+} AesaInitvect;\r
+/** \brief AesaKey hardware registers */\r
+typedef struct {\r
+ WoReg AESA_KEY; /**< \brief (AesaKey Offset: 0x00) Key Register 0 */\r
+} AesaKey;\r
+/** \brief AESA hardware registers */\r
+typedef struct {\r
+ RwReg AESA_CTRL; /**< \brief (AESA Offset: 0x00) Control Register */\r
+ RwReg AESA_MODE; /**< \brief (AESA Offset: 0x04) Mode Register */\r
+ RwReg AESA_DATABUFPTR; /**< \brief (AESA Offset: 0x08) Data Buffer Pointer Register */\r
+ RoReg AESA_SR; /**< \brief (AESA Offset: 0x0C) Status Register */\r
+ WoReg AESA_IER; /**< \brief (AESA Offset: 0x10) Interrupt Enable Register */\r
+ WoReg AESA_IDR; /**< \brief (AESA Offset: 0x14) Interrupt Disable Register */\r
+ RoReg AESA_IMR; /**< \brief (AESA Offset: 0x18) Interrupt Mask Register */\r
+ RoReg Reserved1[1];\r
+ AesaKey AESA_KEY[8]; /**< \brief (AESA Offset: 0x20) AesaKey groups */\r
+ AesaInitvect AESA_INITVECT[4]; /**< \brief (AESA Offset: 0x40) AesaInitvect groups */\r
+ WoReg AESA_IDATA; /**< \brief (AESA Offset: 0x50) Input Data Register */\r
+ RoReg Reserved2[3];\r
+ RoReg AESA_ODATA; /**< \brief (AESA Offset: 0x60) Output Data Register */\r
+ RoReg Reserved3[3];\r
+ WoReg AESA_DRNGSEED; /**< \brief (AESA Offset: 0x70) DRNG Seed Register */\r
+ RoReg Reserved4[33];\r
+ RoReg AESA_PARAMETER; /**< \brief (AESA Offset: 0xF8) Parameter Register */\r
+ RoReg AESA_VERSION; /**< \brief (AESA Offset: 0xFC) Version Register */\r
+} Aesa;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- AESA_CTRL : (AESA Offset: 0x00) Control Register -------- */\r
+#define AESA_CTRL_ENABLE (0x1u << 0) /**< \brief (AESA_CTRL) Enable Module */\r
+#define AESA_CTRL_DKEYGEN (0x1u << 1) /**< \brief (AESA_CTRL) Decryption Key Generate */\r
+#define AESA_CTRL_NEWMSG (0x1u << 2) /**< \brief (AESA_CTRL) New Message */\r
+#define AESA_CTRL_SWRST (0x1u << 8) /**< \brief (AESA_CTRL) Software Reset */\r
+/* -------- AESA_MODE : (AESA Offset: 0x04) Mode Register -------- */\r
+#define AESA_MODE_ENCRYPT (0x1u << 0) /**< \brief (AESA_MODE) Encryption */\r
+#define AESA_MODE_KEYSIZE_Pos 1\r
+#define AESA_MODE_KEYSIZE_Msk (0x3u << AESA_MODE_KEYSIZE_Pos) /**< \brief (AESA_MODE) Key Size */\r
+#define AESA_MODE_KEYSIZE(value) ((AESA_MODE_KEYSIZE_Msk & ((value) << AESA_MODE_KEYSIZE_Pos)))\r
+#define AESA_MODE_DMA (0x1u << 3) /**< \brief (AESA_MODE) DMA Mode */\r
+#define AESA_MODE_OPMODE_Pos 4\r
+#define AESA_MODE_OPMODE_Msk (0x7u << AESA_MODE_OPMODE_Pos) /**< \brief (AESA_MODE) Confidentiality Mode of Operation */\r
+#define AESA_MODE_OPMODE(value) ((AESA_MODE_OPMODE_Msk & ((value) << AESA_MODE_OPMODE_Pos)))\r
+#define AESA_MODE_CFBS_Pos 8\r
+#define AESA_MODE_CFBS_Msk (0x7u << AESA_MODE_CFBS_Pos) /**< \brief (AESA_MODE) Cipher Feedback Data Segment Size */\r
+#define AESA_MODE_CFBS(value) ((AESA_MODE_CFBS_Msk & ((value) << AESA_MODE_CFBS_Pos)))\r
+#define AESA_MODE_CTYPE_Pos 16\r
+#define AESA_MODE_CTYPE_Msk (0xFu << AESA_MODE_CTYPE_Pos) /**< \brief (AESA_MODE) Countermeasure Type */\r
+#define AESA_MODE_CTYPE(value) ((AESA_MODE_CTYPE_Msk & ((value) << AESA_MODE_CTYPE_Pos)))\r
+/* -------- AESA_DATABUFPTR : (AESA Offset: 0x08) Data Buffer Pointer Register -------- */\r
+#define AESA_DATABUFPTR_IDATAW_Pos 0\r
+#define AESA_DATABUFPTR_IDATAW_Msk (0x3u << AESA_DATABUFPTR_IDATAW_Pos) /**< \brief (AESA_DATABUFPTR) Input Data Word */\r
+#define AESA_DATABUFPTR_IDATAW(value) ((AESA_DATABUFPTR_IDATAW_Msk & ((value) << AESA_DATABUFPTR_IDATAW_Pos)))\r
+#define AESA_DATABUFPTR_ODATAW_Pos 4\r
+#define AESA_DATABUFPTR_ODATAW_Msk (0x3u << AESA_DATABUFPTR_ODATAW_Pos) /**< \brief (AESA_DATABUFPTR) Output Data Word */\r
+#define AESA_DATABUFPTR_ODATAW(value) ((AESA_DATABUFPTR_ODATAW_Msk & ((value) << AESA_DATABUFPTR_ODATAW_Pos)))\r
+/* -------- AESA_SR : (AESA Offset: 0x0C) Status Register -------- */\r
+#define AESA_SR_ODATARDY (0x1u << 0) /**< \brief (AESA_SR) Output Data Ready */\r
+#define AESA_SR_IBUFRDY (0x1u << 16) /**< \brief (AESA_SR) Input Buffer Ready */\r
+/* -------- AESA_IER : (AESA Offset: 0x10) Interrupt Enable Register -------- */\r
+#define AESA_IER_ODATARDY (0x1u << 0) /**< \brief (AESA_IER) Output Data Ready Interrupt Enable */\r
+#define AESA_IER_IBUFRDY (0x1u << 16) /**< \brief (AESA_IER) Input Buffer Ready Interrupt Enable */\r
+/* -------- AESA_IDR : (AESA Offset: 0x14) Interrupt Disable Register -------- */\r
+#define AESA_IDR_ODATARDY (0x1u << 0) /**< \brief (AESA_IDR) Output Data Ready Interrupt Disable */\r
+#define AESA_IDR_IBUFRDY (0x1u << 16) /**< \brief (AESA_IDR) Input Buffer Ready Interrupt Disable */\r
+/* -------- AESA_IMR : (AESA Offset: 0x18) Interrupt Mask Register -------- */\r
+#define AESA_IMR_ODATARDY (0x1u << 0) /**< \brief (AESA_IMR) Output Data Ready Interrupt Mask */\r
+#define AESA_IMR_IBUFRDY (0x1u << 16) /**< \brief (AESA_IMR) Input Buffer Ready Interrupt Mask */\r
+/* -------- AESA_KEY : (AESA Offset: 0x20) Key Key Register 0 -------- */\r
+#define AESA_KEY_KEY0_Pos 0\r
+#define AESA_KEY_KEY0_Msk (0xFFFFFFFFu << AESA_KEY_KEY0_Pos) /**< \brief (AESA_KEY) Key Word 0 */\r
+#define AESA_KEY_KEY0(value) ((AESA_KEY_KEY0_Msk & ((value) << AESA_KEY_KEY0_Pos)))\r
+/* -------- AESA_INITVECT : (AESA Offset: 0x40) Initvect Initialization Vector Register 0 -------- */\r
+#define AESA_INITVECT_INITVECT0_Pos 0\r
+#define AESA_INITVECT_INITVECT0_Msk (0xFFFFFFFFu << AESA_INITVECT_INITVECT0_Pos) /**< \brief (AESA_INITVECT) Initialization Vector Word 0 */\r
+#define AESA_INITVECT_INITVECT0(value) ((AESA_INITVECT_INITVECT0_Msk & ((value) << AESA_INITVECT_INITVECT0_Pos)))\r
+/* -------- AESA_IDATA : (AESA Offset: 0x50) Input Data Register -------- */\r
+#define AESA_IDATA_IDATA_Pos 0\r
+#define AESA_IDATA_IDATA_Msk (0xFFFFFFFFu << AESA_IDATA_IDATA_Pos) /**< \brief (AESA_IDATA) Input Data */\r
+#define AESA_IDATA_IDATA(value) ((AESA_IDATA_IDATA_Msk & ((value) << AESA_IDATA_IDATA_Pos)))\r
+/* -------- AESA_ODATA : (AESA Offset: 0x60) Output Data Register -------- */\r
+#define AESA_ODATA_ODATA_Pos 0\r
+#define AESA_ODATA_ODATA_Msk (0xFFFFFFFFu << AESA_ODATA_ODATA_Pos) /**< \brief (AESA_ODATA) Output Data */\r
+#define AESA_ODATA_ODATA(value) ((AESA_ODATA_ODATA_Msk & ((value) << AESA_ODATA_ODATA_Pos)))\r
+/* -------- AESA_DRNGSEED : (AESA Offset: 0x70) DRNG Seed Register -------- */\r
+#define AESA_DRNGSEED_SEED_Pos 0\r
+#define AESA_DRNGSEED_SEED_Msk (0xFFFFFFFFu << AESA_DRNGSEED_SEED_Pos) /**< \brief (AESA_DRNGSEED) DRNG Seed */\r
+#define AESA_DRNGSEED_SEED(value) ((AESA_DRNGSEED_SEED_Msk & ((value) << AESA_DRNGSEED_SEED_Pos)))\r
+/* -------- AESA_PARAMETER : (AESA Offset: 0xF8) Parameter Register -------- */\r
+#define AESA_PARAMETER_KEYSIZE_Pos 0\r
+#define AESA_PARAMETER_KEYSIZE_Msk (0x3u << AESA_PARAMETER_KEYSIZE_Pos) /**< \brief (AESA_PARAMETER) Maximum Key Size */\r
+#define AESA_PARAMETER_KEYSIZE(value) ((AESA_PARAMETER_KEYSIZE_Msk & ((value) << AESA_PARAMETER_KEYSIZE_Pos)))\r
+#define AESA_PARAMETER_OPMODE_Pos 2\r
+#define AESA_PARAMETER_OPMODE_Msk (0x7u << AESA_PARAMETER_OPMODE_Pos) /**< \brief (AESA_PARAMETER) Maximum Number of Confidentiality Modes of Operation */\r
+#define AESA_PARAMETER_OPMODE(value) ((AESA_PARAMETER_OPMODE_Msk & ((value) << AESA_PARAMETER_OPMODE_Pos)))\r
+#define AESA_PARAMETER_CTRMEAS (0x1u << 8) /**< \brief (AESA_PARAMETER) Countermeasures */\r
+/* -------- AESA_VERSION : (AESA Offset: 0xFC) Version Register -------- */\r
+#define AESA_VERSION_VERSION_Pos 0\r
+#define AESA_VERSION_VERSION_Msk (0xFFFu << AESA_VERSION_VERSION_Pos) /**< \brief (AESA_VERSION) Version Number */\r
+#define AESA_VERSION_VERSION(value) ((AESA_VERSION_VERSION_Msk & ((value) << AESA_VERSION_VERSION_Pos)))\r
+#define AESA_VERSION_VARIANT_Pos 16\r
+#define AESA_VERSION_VARIANT_Msk (0xFu << AESA_VERSION_VARIANT_Pos) /**< \brief (AESA_VERSION) Variant Number */\r
+#define AESA_VERSION_VARIANT(value) ((AESA_VERSION_VARIANT_Msk & ((value) << AESA_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR AST */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_AST Asynchronous Timer */\r
+/*@{*/\r
+\r
+#define REV_AST 0x311\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief AST hardware registers */\r
+typedef struct {\r
+ RwReg AST_CR; /**< \brief (AST Offset: 0x00) Control Register */\r
+ RwReg AST_CV; /**< \brief (AST Offset: 0x04) Counter Value */\r
+ RoReg AST_SR; /**< \brief (AST Offset: 0x08) Status Register */\r
+ WoReg AST_SCR; /**< \brief (AST Offset: 0x0C) Status Clear Register */\r
+ WoReg AST_IER; /**< \brief (AST Offset: 0x10) Interrupt Enable Register */\r
+ WoReg AST_IDR; /**< \brief (AST Offset: 0x14) Interrupt Disable Register */\r
+ RoReg AST_IMR; /**< \brief (AST Offset: 0x18) Interrupt Mask Register */\r
+ RwReg AST_WER; /**< \brief (AST Offset: 0x1C) Wake Enable Register */\r
+ RwReg AST_AR0; /**< \brief (AST Offset: 0x20) Alarm Register 0 */\r
+ RwReg AST_AR1; /**< \brief (AST Offset: 0x24) Alarm Register 1 */\r
+ RoReg Reserved1[2];\r
+ RwReg AST_PIR0; /**< \brief (AST Offset: 0x30) Periodic Interval Register 0 */\r
+ RwReg AST_PIR1; /**< \brief (AST Offset: 0x34) Periodic Interval Register 1 */\r
+ RoReg Reserved2[2];\r
+ RwReg AST_CLOCK; /**< \brief (AST Offset: 0x40) Clock Control Register */\r
+ RwReg AST_DTR; /**< \brief (AST Offset: 0x44) Digital Tuner Register */\r
+ WoReg AST_EVE; /**< \brief (AST Offset: 0x48) Event Enable Register */\r
+ WoReg AST_EVD; /**< \brief (AST Offset: 0x4C) Event Disable Register */\r
+ RoReg AST_EVM; /**< \brief (AST Offset: 0x50) Event Mask Register */\r
+ RwReg AST_CALV; /**< \brief (AST Offset: 0x54) Calendar Value */\r
+ RoReg Reserved3[38];\r
+ RoReg AST_PARAMETER; /**< \brief (AST Offset: 0xF0) Parameter Register */\r
+ RoReg Reserved4[2];\r
+ RoReg AST_VERSION; /**< \brief (AST Offset: 0xFC) Version Register */\r
+} Ast;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- AST_CR : (AST Offset: 0x00) Control Register -------- */\r
+#define AST_CR_EN (0x1u << 0) /**< \brief (AST_CR) Enable */\r
+#define AST_CR_EN_0 (0x0u << 0) /**< \brief (AST_CR) The AST is disabled. */\r
+#define AST_CR_EN_1 (0x1u << 0) /**< \brief (AST_CR) The AST is enabled */\r
+#define AST_CR_PCLR (0x1u << 1) /**< \brief (AST_CR) Prescaler Clear */\r
+#define AST_CR_CAL (0x1u << 2) /**< \brief (AST_CR) Calendar mode */\r
+#define AST_CR_CA0 (0x1u << 8) /**< \brief (AST_CR) Clear on Alarm 0 */\r
+#define AST_CR_CA1 (0x1u << 9) /**< \brief (AST_CR) Clear on Alarm 1 */\r
+#define AST_CR_PSEL_Pos 16\r
+#define AST_CR_PSEL_Msk (0x1Fu << AST_CR_PSEL_Pos) /**< \brief (AST_CR) Prescaler Select */\r
+#define AST_CR_PSEL(value) ((AST_CR_PSEL_Msk & ((value) << AST_CR_PSEL_Pos)))\r
+/* -------- AST_CV : (AST Offset: 0x04) Counter Value -------- */\r
+#define AST_CV_VALUE_Pos 0\r
+#define AST_CV_VALUE_Msk (0xFFFFFFFFu << AST_CV_VALUE_Pos) /**< \brief (AST_CV) AST Value */\r
+#define AST_CV_VALUE(value) ((AST_CV_VALUE_Msk & ((value) << AST_CV_VALUE_Pos)))\r
+/* -------- AST_SR : (AST Offset: 0x08) Status Register -------- */\r
+#define AST_SR_OVF (0x1u << 0) /**< \brief (AST_SR) Overflow */\r
+#define AST_SR_ALARM0 (0x1u << 8) /**< \brief (AST_SR) Alarm 0 */\r
+#define AST_SR_ALARM1 (0x1u << 9) /**< \brief (AST_SR) Alarm 1 */\r
+#define AST_SR_PER0 (0x1u << 16) /**< \brief (AST_SR) Periodic 0 */\r
+#define AST_SR_PER1 (0x1u << 17) /**< \brief (AST_SR) Periodic 1 */\r
+#define AST_SR_BUSY (0x1u << 24) /**< \brief (AST_SR) AST Busy */\r
+#define AST_SR_BUSY_0 (0x0u << 24) /**< \brief (AST_SR) The AST accepts writes to CV, WER, DTR, SCR, AR, PIR and CR */\r
+#define AST_SR_BUSY_1 (0x1u << 24) /**< \brief (AST_SR) The AST is busy and will discard writes to CV, WER, DTR, SCR, AR, PIR and CR */\r
+#define AST_SR_READY (0x1u << 25) /**< \brief (AST_SR) AST Ready */\r
+#define AST_SR_CLKBUSY (0x1u << 28) /**< \brief (AST_SR) Clock Busy */\r
+#define AST_SR_CLKBUSY_0 (0x0u << 28) /**< \brief (AST_SR) The clock is ready and can be changed */\r
+#define AST_SR_CLKBUSY_1 (0x1u << 28) /**< \brief (AST_SR) CEN has been written and the clock is busy */\r
+#define AST_SR_CLKRDY (0x1u << 29) /**< \brief (AST_SR) Clock Ready */\r
+/* -------- AST_SCR : (AST Offset: 0x0C) Status Clear Register -------- */\r
+#define AST_SCR_OVF (0x1u << 0) /**< \brief (AST_SCR) Overflow */\r
+#define AST_SCR_ALARM0 (0x1u << 8) /**< \brief (AST_SCR) Alarm 0 */\r
+#define AST_SCR_ALARM1 (0x1u << 9) /**< \brief (AST_SCR) Alarm 1 */\r
+#define AST_SCR_PER0 (0x1u << 16) /**< \brief (AST_SCR) Periodic 0 */\r
+#define AST_SCR_PER1 (0x1u << 17) /**< \brief (AST_SCR) Periodic 1 */\r
+#define AST_SCR_READY (0x1u << 25) /**< \brief (AST_SCR) AST Ready */\r
+#define AST_SCR_CLKRDY (0x1u << 29) /**< \brief (AST_SCR) Clock Ready */\r
+/* -------- AST_IER : (AST Offset: 0x10) Interrupt Enable Register -------- */\r
+#define AST_IER_OVF (0x1u << 0) /**< \brief (AST_IER) Overflow */\r
+#define AST_IER_OVF_0 (0x0u << 0) /**< \brief (AST_IER) No effect */\r
+#define AST_IER_OVF_1 (0x1u << 0) /**< \brief (AST_IER) Enable Interrupt. */\r
+#define AST_IER_ALARM0 (0x1u << 8) /**< \brief (AST_IER) Alarm 0 */\r
+#define AST_IER_ALARM0_0 (0x0u << 8) /**< \brief (AST_IER) No effect */\r
+#define AST_IER_ALARM0_1 (0x1u << 8) /**< \brief (AST_IER) Enable interrupt */\r
+#define AST_IER_ALARM1 (0x1u << 9) /**< \brief (AST_IER) Alarm 1 */\r
+#define AST_IER_ALARM1_0 (0x0u << 9) /**< \brief (AST_IER) No effect */\r
+#define AST_IER_ALARM1_1 (0x1u << 9) /**< \brief (AST_IER) Enable interrupt */\r
+#define AST_IER_PER0 (0x1u << 16) /**< \brief (AST_IER) Periodic 0 */\r
+#define AST_IER_PER0_0 (0x0u << 16) /**< \brief (AST_IER) No effect */\r
+#define AST_IER_PER0_1 (0x1u << 16) /**< \brief (AST_IER) Enable interrupt */\r
+#define AST_IER_PER1 (0x1u << 17) /**< \brief (AST_IER) Periodic 1 */\r
+#define AST_IER_PER1_0 (0x0u << 17) /**< \brief (AST_IER) No effect */\r
+#define AST_IER_PER1_1 (0x1u << 17) /**< \brief (AST_IER) Enable interrupt */\r
+#define AST_IER_READY (0x1u << 25) /**< \brief (AST_IER) AST Ready */\r
+#define AST_IER_READY_0 (0x0u << 25) /**< \brief (AST_IER) No effect */\r
+#define AST_IER_READY_1 (0x1u << 25) /**< \brief (AST_IER) Enable interrupt */\r
+#define AST_IER_CLKRDY (0x1u << 29) /**< \brief (AST_IER) Clock Ready */\r
+#define AST_IER_CLKRDY_0 (0x0u << 29) /**< \brief (AST_IER) No effect */\r
+#define AST_IER_CLKRDY_1 (0x1u << 29) /**< \brief (AST_IER) Enable interrupt */\r
+/* -------- AST_IDR : (AST Offset: 0x14) Interrupt Disable Register -------- */\r
+#define AST_IDR_OVF (0x1u << 0) /**< \brief (AST_IDR) Overflow */\r
+#define AST_IDR_OVF_0 (0x0u << 0) /**< \brief (AST_IDR) No effect */\r
+#define AST_IDR_OVF_1 (0x1u << 0) /**< \brief (AST_IDR) Disable Interrupt. */\r
+#define AST_IDR_ALARM0 (0x1u << 8) /**< \brief (AST_IDR) Alarm 0 */\r
+#define AST_IDR_ALARM0_0 (0x0u << 8) /**< \brief (AST_IDR) No effect */\r
+#define AST_IDR_ALARM0_1 (0x1u << 8) /**< \brief (AST_IDR) Disable interrupt */\r
+#define AST_IDR_ALARM1 (0x1u << 9) /**< \brief (AST_IDR) Alarm 1 */\r
+#define AST_IDR_ALARM1_0 (0x0u << 9) /**< \brief (AST_IDR) No effect */\r
+#define AST_IDR_ALARM1_1 (0x1u << 9) /**< \brief (AST_IDR) Disable interrupt */\r
+#define AST_IDR_PER0 (0x1u << 16) /**< \brief (AST_IDR) Periodic 0 */\r
+#define AST_IDR_PER0_0 (0x0u << 16) /**< \brief (AST_IDR) No effet */\r
+#define AST_IDR_PER0_1 (0x1u << 16) /**< \brief (AST_IDR) Disalbe interrupt */\r
+#define AST_IDR_PER1 (0x1u << 17) /**< \brief (AST_IDR) Periodic 1 */\r
+#define AST_IDR_PER1_0 (0x0u << 17) /**< \brief (AST_IDR) No effect */\r
+#define AST_IDR_PER1_1 (0x1u << 17) /**< \brief (AST_IDR) Disable interrupt */\r
+#define AST_IDR_READY (0x1u << 25) /**< \brief (AST_IDR) AST Ready */\r
+#define AST_IDR_READY_0 (0x0u << 25) /**< \brief (AST_IDR) No effect */\r
+#define AST_IDR_READY_1 (0x1u << 25) /**< \brief (AST_IDR) Disable interrupt */\r
+#define AST_IDR_CLKRDY (0x1u << 29) /**< \brief (AST_IDR) Clock Ready */\r
+#define AST_IDR_CLKRDY_0 (0x0u << 29) /**< \brief (AST_IDR) No effect */\r
+#define AST_IDR_CLKRDY_1 (0x1u << 29) /**< \brief (AST_IDR) Disable interrupt */\r
+/* -------- AST_IMR : (AST Offset: 0x18) Interrupt Mask Register -------- */\r
+#define AST_IMR_OVF (0x1u << 0) /**< \brief (AST_IMR) Overflow */\r
+#define AST_IMR_OVF_0 (0x0u << 0) /**< \brief (AST_IMR) Interrupt is disabled */\r
+#define AST_IMR_OVF_1 (0x1u << 0) /**< \brief (AST_IMR) Interrupt is enabled. */\r
+#define AST_IMR_ALARM0 (0x1u << 8) /**< \brief (AST_IMR) Alarm 0 */\r
+#define AST_IMR_ALARM0_0 (0x0u << 8) /**< \brief (AST_IMR) Interupt is disabled */\r
+#define AST_IMR_ALARM0_1 (0x1u << 8) /**< \brief (AST_IMR) Interrupt is enabled */\r
+#define AST_IMR_ALARM1 (0x1u << 9) /**< \brief (AST_IMR) Alarm 1 */\r
+#define AST_IMR_ALARM1_0 (0x0u << 9) /**< \brief (AST_IMR) Interrupt is disabled */\r
+#define AST_IMR_ALARM1_1 (0x1u << 9) /**< \brief (AST_IMR) Interrupt is enabled */\r
+#define AST_IMR_PER0 (0x1u << 16) /**< \brief (AST_IMR) Periodic 0 */\r
+#define AST_IMR_PER0_0 (0x0u << 16) /**< \brief (AST_IMR) Interrupt is disabled */\r
+#define AST_IMR_PER0_1 (0x1u << 16) /**< \brief (AST_IMR) Interrupt is enabled */\r
+#define AST_IMR_PER1 (0x1u << 17) /**< \brief (AST_IMR) Periodic 1 */\r
+#define AST_IMR_PER1_0 (0x0u << 17) /**< \brief (AST_IMR) Interrupt is disabled */\r
+#define AST_IMR_PER1_1 (0x1u << 17) /**< \brief (AST_IMR) Interrupt is enabled */\r
+#define AST_IMR_READY (0x1u << 25) /**< \brief (AST_IMR) AST Ready */\r
+#define AST_IMR_READY_0 (0x0u << 25) /**< \brief (AST_IMR) Interrupt is disabled */\r
+#define AST_IMR_READY_1 (0x1u << 25) /**< \brief (AST_IMR) Interrupt is enabled */\r
+#define AST_IMR_CLKRDY (0x1u << 29) /**< \brief (AST_IMR) Clock Ready */\r
+#define AST_IMR_CLKRDY_0 (0x0u << 29) /**< \brief (AST_IMR) Interrupt is disabled */\r
+#define AST_IMR_CLKRDY_1 (0x1u << 29) /**< \brief (AST_IMR) Interrupt is enabled */\r
+/* -------- AST_WER : (AST Offset: 0x1C) Wake Enable Register -------- */\r
+#define AST_WER_OVF (0x1u << 0) /**< \brief (AST_WER) Overflow */\r
+#define AST_WER_OVF_0 (0x0u << 0) /**< \brief (AST_WER) The corresponing event will not wake up the CPU from sleep mode */\r
+#define AST_WER_OVF_1 (0x1u << 0) /**< \brief (AST_WER) The corresponding event will wake up the CPU from sleep mode */\r
+#define AST_WER_ALARM0 (0x1u << 8) /**< \brief (AST_WER) Alarm 0 */\r
+#define AST_WER_ALARM0_0 (0x0u << 8) /**< \brief (AST_WER) The corresponing event will not wake up the CPU from sleep mode */\r
+#define AST_WER_ALARM0_1 (0x1u << 8) /**< \brief (AST_WER) The corresponding event will wake up the CPU from sleep mode */\r
+#define AST_WER_ALARM1 (0x1u << 9) /**< \brief (AST_WER) Alarm 1 */\r
+#define AST_WER_ALARM1_0 (0x0u << 9) /**< \brief (AST_WER) The corresponing event will not wake up the CPU from sleep mode */\r
+#define AST_WER_ALARM1_1 (0x1u << 9) /**< \brief (AST_WER) The corresponding event will wake up the CPU from sleep mode */\r
+#define AST_WER_PER0 (0x1u << 16) /**< \brief (AST_WER) Periodic 0 */\r
+#define AST_WER_PER0_0 (0x0u << 16) /**< \brief (AST_WER) The corresponing event will not wake up the CPU from sleep mode */\r
+#define AST_WER_PER0_1 (0x1u << 16) /**< \brief (AST_WER) The corresponding event will wake up the CPU from sleep mode */\r
+#define AST_WER_PER1 (0x1u << 17) /**< \brief (AST_WER) Periodic 1 */\r
+#define AST_WER_PER1_0 (0x0u << 17) /**< \brief (AST_WER) The corresponing event will not wake up the CPU from sleep mode */\r
+#define AST_WER_PER1_1 (0x1u << 17) /**< \brief (AST_WER) The corresponding event will wake up the CPU from sleep mode */\r
+/* -------- AST_AR0 : (AST Offset: 0x20) Alarm Register 0 -------- */\r
+#define AST_AR0_VALUE_Pos 0\r
+#define AST_AR0_VALUE_Msk (0xFFFFFFFFu << AST_AR0_VALUE_Pos) /**< \brief (AST_AR0) Alarm Value */\r
+#define AST_AR0_VALUE(value) ((AST_AR0_VALUE_Msk & ((value) << AST_AR0_VALUE_Pos)))\r
+/* -------- AST_AR1 : (AST Offset: 0x24) Alarm Register 1 -------- */\r
+#define AST_AR1_VALUE_Pos 0\r
+#define AST_AR1_VALUE_Msk (0xFFFFFFFFu << AST_AR1_VALUE_Pos) /**< \brief (AST_AR1) Alarm Value */\r
+#define AST_AR1_VALUE(value) ((AST_AR1_VALUE_Msk & ((value) << AST_AR1_VALUE_Pos)))\r
+/* -------- AST_PIR0 : (AST Offset: 0x30) Periodic Interval Register 0 -------- */\r
+#define AST_PIR0_INSEL_Pos 0\r
+#define AST_PIR0_INSEL_Msk (0x1Fu << AST_PIR0_INSEL_Pos) /**< \brief (AST_PIR0) Interval Select */\r
+#define AST_PIR0_INSEL(value) ((AST_PIR0_INSEL_Msk & ((value) << AST_PIR0_INSEL_Pos)))\r
+/* -------- AST_PIR1 : (AST Offset: 0x34) Periodic Interval Register 1 -------- */\r
+#define AST_PIR1_INSEL_Pos 0\r
+#define AST_PIR1_INSEL_Msk (0x1Fu << AST_PIR1_INSEL_Pos) /**< \brief (AST_PIR1) Interval Select */\r
+#define AST_PIR1_INSEL(value) ((AST_PIR1_INSEL_Msk & ((value) << AST_PIR1_INSEL_Pos)))\r
+/* -------- AST_CLOCK : (AST Offset: 0x40) Clock Control Register -------- */\r
+#define AST_CLOCK_CEN (0x1u << 0) /**< \brief (AST_CLOCK) Clock Enable */\r
+#define AST_CLOCK_CEN_0 (0x0u << 0) /**< \brief (AST_CLOCK) The clock is disabled */\r
+#define AST_CLOCK_CEN_1 (0x1u << 0) /**< \brief (AST_CLOCK) The clock is enabled */\r
+#define AST_CLOCK_CSSEL_Pos 8\r
+#define AST_CLOCK_CSSEL_Msk (0x7u << AST_CLOCK_CSSEL_Pos) /**< \brief (AST_CLOCK) Clock Source Selection */\r
+#define AST_CLOCK_CSSEL(value) ((AST_CLOCK_CSSEL_Msk & ((value) << AST_CLOCK_CSSEL_Pos)))\r
+#define AST_CLOCK_CSSEL_SLOWCLOCK (0x0u << 8) /**< \brief (AST_CLOCK) Slow clock */\r
+#define AST_CLOCK_CSSEL_32KHZCLK (0x1u << 8) /**< \brief (AST_CLOCK) 32 kHz clock */\r
+#define AST_CLOCK_CSSEL_PBCLOCK (0x2u << 8) /**< \brief (AST_CLOCK) PB clock */\r
+#define AST_CLOCK_CSSEL_GCLK (0x3u << 8) /**< \brief (AST_CLOCK) Generic clock */\r
+#define AST_CLOCK_CSSEL_1KHZCLK (0x4u << 8) /**< \brief (AST_CLOCK) 1kHz clock from 32 kHz oscillator */\r
+/* -------- AST_DTR : (AST Offset: 0x44) Digital Tuner Register -------- */\r
+#define AST_DTR_EXP_Pos 0\r
+#define AST_DTR_EXP_Msk (0x1Fu << AST_DTR_EXP_Pos) /**< \brief (AST_DTR) EXP */\r
+#define AST_DTR_EXP(value) ((AST_DTR_EXP_Msk & ((value) << AST_DTR_EXP_Pos)))\r
+#define AST_DTR_ADD (0x1u << 5) /**< \brief (AST_DTR) ADD */\r
+#define AST_DTR_VALUE_Pos 8\r
+#define AST_DTR_VALUE_Msk (0xFFu << AST_DTR_VALUE_Pos) /**< \brief (AST_DTR) VALUE */\r
+#define AST_DTR_VALUE(value) ((AST_DTR_VALUE_Msk & ((value) << AST_DTR_VALUE_Pos)))\r
+/* -------- AST_EVE : (AST Offset: 0x48) Event Enable Register -------- */\r
+#define AST_EVE_OVF (0x1u << 0) /**< \brief (AST_EVE) Overflow */\r
+#define AST_EVE_ALARM0 (0x1u << 8) /**< \brief (AST_EVE) Alarm 0 */\r
+#define AST_EVE_ALARM1 (0x1u << 9) /**< \brief (AST_EVE) Alarm 1 */\r
+#define AST_EVE_PER0 (0x1u << 16) /**< \brief (AST_EVE) Perioidc 0 */\r
+#define AST_EVE_PER1 (0x1u << 17) /**< \brief (AST_EVE) Periodic 1 */\r
+/* -------- AST_EVD : (AST Offset: 0x4C) Event Disable Register -------- */\r
+#define AST_EVD_OVF (0x1u << 0) /**< \brief (AST_EVD) Overflow */\r
+#define AST_EVD_ALARM0 (0x1u << 8) /**< \brief (AST_EVD) Alarm 0 */\r
+#define AST_EVD_ALARM1 (0x1u << 9) /**< \brief (AST_EVD) Alarm 1 */\r
+#define AST_EVD_PER0 (0x1u << 16) /**< \brief (AST_EVD) Perioidc 0 */\r
+#define AST_EVD_PER1 (0x1u << 17) /**< \brief (AST_EVD) Periodic 1 */\r
+/* -------- AST_EVM : (AST Offset: 0x50) Event Mask Register -------- */\r
+#define AST_EVM_OVF (0x1u << 0) /**< \brief (AST_EVM) Overflow */\r
+#define AST_EVM_ALARM0 (0x1u << 8) /**< \brief (AST_EVM) Alarm 0 */\r
+#define AST_EVM_ALARM1 (0x1u << 9) /**< \brief (AST_EVM) Alarm 1 */\r
+#define AST_EVM_PER0 (0x1u << 16) /**< \brief (AST_EVM) Perioidc 0 */\r
+#define AST_EVM_PER1 (0x1u << 17) /**< \brief (AST_EVM) Periodic 1 */\r
+/* -------- AST_CALV : (AST Offset: 0x54) Calendar Value -------- */\r
+#define AST_CALV_SEC_Pos 0\r
+#define AST_CALV_SEC_Msk (0x3Fu << AST_CALV_SEC_Pos) /**< \brief (AST_CALV) Second */\r
+#define AST_CALV_SEC(value) ((AST_CALV_SEC_Msk & ((value) << AST_CALV_SEC_Pos)))\r
+#define AST_CALV_MIN_Pos 6\r
+#define AST_CALV_MIN_Msk (0x3Fu << AST_CALV_MIN_Pos) /**< \brief (AST_CALV) Minute */\r
+#define AST_CALV_MIN(value) ((AST_CALV_MIN_Msk & ((value) << AST_CALV_MIN_Pos)))\r
+#define AST_CALV_HOUR_Pos 12\r
+#define AST_CALV_HOUR_Msk (0x1Fu << AST_CALV_HOUR_Pos) /**< \brief (AST_CALV) Hour */\r
+#define AST_CALV_HOUR(value) ((AST_CALV_HOUR_Msk & ((value) << AST_CALV_HOUR_Pos)))\r
+#define AST_CALV_DAY_Pos 17\r
+#define AST_CALV_DAY_Msk (0x1Fu << AST_CALV_DAY_Pos) /**< \brief (AST_CALV) Day */\r
+#define AST_CALV_DAY(value) ((AST_CALV_DAY_Msk & ((value) << AST_CALV_DAY_Pos)))\r
+#define AST_CALV_MONTH_Pos 22\r
+#define AST_CALV_MONTH_Msk (0xFu << AST_CALV_MONTH_Pos) /**< \brief (AST_CALV) Month */\r
+#define AST_CALV_MONTH(value) ((AST_CALV_MONTH_Msk & ((value) << AST_CALV_MONTH_Pos)))\r
+#define AST_CALV_YEAR_Pos 26\r
+#define AST_CALV_YEAR_Msk (0x3Fu << AST_CALV_YEAR_Pos) /**< \brief (AST_CALV) Year */\r
+#define AST_CALV_YEAR(value) ((AST_CALV_YEAR_Msk & ((value) << AST_CALV_YEAR_Pos)))\r
+/* -------- AST_PARAMETER : (AST Offset: 0xF0) Parameter Register -------- */\r
+#define AST_PARAMETER_DT (0x1u << 0) /**< \brief (AST_PARAMETER) Digital Tuner */\r
+#define AST_PARAMETER_DT_OFF (0x0u << 0) /**< \brief (AST_PARAMETER) Digital tuner off */\r
+#define AST_PARAMETER_DT_ON (0x1u << 0) /**< \brief (AST_PARAMETER) Digital tuner on */\r
+#define AST_PARAMETER_DTEXPWA (0x1u << 1) /**< \brief (AST_PARAMETER) Digital Tuner Exponent Writeable */\r
+#define AST_PARAMETER_DTEXPWA_0 (0x0u << 1) /**< \brief (AST_PARAMETER) Digital tuner exponent is a constant value. Writes to EXP bitfield in DTR will be discarded. */\r
+#define AST_PARAMETER_DTEXPWA_1 (0x1u << 1) /**< \brief (AST_PARAMETER) Digital tuner exponent is chosen by writing to EXP bitfield in DTR */\r
+#define AST_PARAMETER_DTEXPVALUE_Pos 2\r
+#define AST_PARAMETER_DTEXPVALUE_Msk (0x1Fu << AST_PARAMETER_DTEXPVALUE_Pos) /**< \brief (AST_PARAMETER) Digital Tuner Exponent Value */\r
+#define AST_PARAMETER_DTEXPVALUE(value) ((AST_PARAMETER_DTEXPVALUE_Msk & ((value) << AST_PARAMETER_DTEXPVALUE_Pos)))\r
+#define AST_PARAMETER_NUMAR_Pos 8\r
+#define AST_PARAMETER_NUMAR_Msk (0x3u << AST_PARAMETER_NUMAR_Pos) /**< \brief (AST_PARAMETER) Number of alarm comparators */\r
+#define AST_PARAMETER_NUMAR(value) ((AST_PARAMETER_NUMAR_Msk & ((value) << AST_PARAMETER_NUMAR_Pos)))\r
+#define AST_PARAMETER_NUMAR_ZERO (0x0u << 8) /**< \brief (AST_PARAMETER) No alarm comparators */\r
+#define AST_PARAMETER_NUMAR_ONE (0x1u << 8) /**< \brief (AST_PARAMETER) One alarm comparator */\r
+#define AST_PARAMETER_NUMAR_TWO (0x2u << 8) /**< \brief (AST_PARAMETER) Two alarm comparators */\r
+#define AST_PARAMETER_NUMPIR (0x1u << 12) /**< \brief (AST_PARAMETER) Number of periodic comparators */\r
+#define AST_PARAMETER_NUMPIR_ONE (0x0u << 12) /**< \brief (AST_PARAMETER) One periodic comparator */\r
+#define AST_PARAMETER_NUMPIR_TWO (0x1u << 12) /**< \brief (AST_PARAMETER) Two periodic comparators */\r
+#define AST_PARAMETER_PIR0WA (0x1u << 14) /**< \brief (AST_PARAMETER) Periodic Interval 0 Writeable */\r
+#define AST_PARAMETER_PIR0WA_0 (0x0u << 14) /**< \brief (AST_PARAMETER) Periodic alarm prescaler 0 tapping is a constant value. Writes to INSEL bitfield in PIR0 will be discarded. */\r
+#define AST_PARAMETER_PIR0WA_1 (0x1u << 14) /**< \brief (AST_PARAMETER) Periodic alarm prescaler 0 tapping is chosen by writing to INSEL bitfield in PIR0 */\r
+#define AST_PARAMETER_PIR1WA (0x1u << 15) /**< \brief (AST_PARAMETER) Periodic Interval 1 Writeable */\r
+#define AST_PARAMETER_PIR1WA_0 (0x0u << 15) /**< \brief (AST_PARAMETER) Writes to PIR1 will be discarded */\r
+#define AST_PARAMETER_PIR1WA_1 (0x1u << 15) /**< \brief (AST_PARAMETER) PIR1 can be written */\r
+#define AST_PARAMETER_PER0VALUE_Pos 16\r
+#define AST_PARAMETER_PER0VALUE_Msk (0x1Fu << AST_PARAMETER_PER0VALUE_Pos) /**< \brief (AST_PARAMETER) Periodic Interval 0 Value */\r
+#define AST_PARAMETER_PER0VALUE(value) ((AST_PARAMETER_PER0VALUE_Msk & ((value) << AST_PARAMETER_PER0VALUE_Pos)))\r
+#define AST_PARAMETER_PER1VALUE_Pos 24\r
+#define AST_PARAMETER_PER1VALUE_Msk (0x1Fu << AST_PARAMETER_PER1VALUE_Pos) /**< \brief (AST_PARAMETER) Periodic Interval 1 Value */\r
+#define AST_PARAMETER_PER1VALUE(value) ((AST_PARAMETER_PER1VALUE_Msk & ((value) << AST_PARAMETER_PER1VALUE_Pos)))\r
+/* -------- AST_VERSION : (AST Offset: 0xFC) Version Register -------- */\r
+#define AST_VERSION_VERSION_Pos 0\r
+#define AST_VERSION_VERSION_Msk (0xFFFu << AST_VERSION_VERSION_Pos) /**< \brief (AST_VERSION) Version Number */\r
+#define AST_VERSION_VERSION(value) ((AST_VERSION_VERSION_Msk & ((value) << AST_VERSION_VERSION_Pos)))\r
+#define AST_VERSION_VARIANT_Pos 16\r
+#define AST_VERSION_VARIANT_Msk (0xFu << AST_VERSION_VARIANT_Pos) /**< \brief (AST_VERSION) Variant Number */\r
+#define AST_VERSION_VARIANT(value) ((AST_VERSION_VARIANT_Msk & ((value) << AST_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR BPM */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_BPM Backup Power Manager */\r
+/*@{*/\r
+\r
+#define REV_BPM 0x120\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief BPM hardware registers */\r
+typedef struct {\r
+ WoReg BPM_IER; /**< \brief (BPM Offset: 0x00) Interrupt Enable Register */\r
+ WoReg BPM_IDR; /**< \brief (BPM Offset: 0x04) Interrupt Disable Register */\r
+ RoReg BPM_IMR; /**< \brief (BPM Offset: 0x08) Interrupt Mask Register */\r
+ RoReg BPM_ISR; /**< \brief (BPM Offset: 0x0C) Interrupt Status Register */\r
+ WoReg BPM_ICR; /**< \brief (BPM Offset: 0x10) Interrupt Clear Register */\r
+ RoReg BPM_SR; /**< \brief (BPM Offset: 0x14) Status Register */\r
+ WoReg BPM_UNLOCK; /**< \brief (BPM Offset: 0x18) Unlock Register */\r
+ RwReg BPM_PMCON; /**< \brief (BPM Offset: 0x1C) Power Mode Control Register */\r
+ RoReg Reserved1[2];\r
+ RoReg BPM_BKUPWCAUSE; /**< \brief (BPM Offset: 0x28) Backup Wake up Cause Register */\r
+ RwReg BPM_BKUPWEN; /**< \brief (BPM Offset: 0x2C) Backup Wake up Enable Register */\r
+ RwReg BPM_BKUPPMUX; /**< \brief (BPM Offset: 0x30) Backup Pin Muxing Register */\r
+ RwReg BPM_IORET; /**< \brief (BPM Offset: 0x34) Input Output Retention Register */\r
+ RoReg Reserved2[2];\r
+ RwReg BPM_BPR; /**< \brief (BPM Offset: 0x40) Bypass Register */\r
+ RoReg BPM_FWRUNPS; /**< \brief (BPM Offset: 0x44) Factory Word Run PS Register */\r
+ RoReg BPM_FWPSAVEPS; /**< \brief (BPM Offset: 0x48) Factory Word Power Save PS Register */\r
+ RoReg Reserved3[44];\r
+ RoReg BPM_VERSION; /**< \brief (BPM Offset: 0xFC) Version Register */\r
+} Bpm;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- BPM_IER : (BPM Offset: 0x00) Interrupt Enable Register -------- */\r
+#define BPM_IER_PSOK (0x1u << 0) /**< \brief (BPM_IER) Power Scaling OK Interrupt Enable */\r
+#define BPM_IER_AE (0x1u << 31) /**< \brief (BPM_IER) Access Error Interrupt Enable */\r
+/* -------- BPM_IDR : (BPM Offset: 0x04) Interrupt Disable Register -------- */\r
+#define BPM_IDR_PSOK (0x1u << 0) /**< \brief (BPM_IDR) Power Scaling OK Interrupt Disable */\r
+#define BPM_IDR_AE (0x1u << 31) /**< \brief (BPM_IDR) Access Error Interrupt Disable */\r
+/* -------- BPM_IMR : (BPM Offset: 0x08) Interrupt Mask Register -------- */\r
+#define BPM_IMR_PSOK (0x1u << 0) /**< \brief (BPM_IMR) Power Scaling OK Interrupt Mask */\r
+#define BPM_IMR_AE (0x1u << 31) /**< \brief (BPM_IMR) Access Error Interrupt Mask */\r
+/* -------- BPM_ISR : (BPM Offset: 0x0C) Interrupt Status Register -------- */\r
+#define BPM_ISR_PSOK (0x1u << 0) /**< \brief (BPM_ISR) Power Scaling OK Interrupt Status */\r
+#define BPM_ISR_AE (0x1u << 31) /**< \brief (BPM_ISR) Access Error Interrupt Status */\r
+/* -------- BPM_ICR : (BPM Offset: 0x10) Interrupt Clear Register -------- */\r
+#define BPM_ICR_PSOK (0x1u << 0) /**< \brief (BPM_ICR) Power Scaling OK Interrupt Status Clear */\r
+#define BPM_ICR_AE (0x1u << 31) /**< \brief (BPM_ICR) Access Error Interrupt Status Clear */\r
+/* -------- BPM_SR : (BPM Offset: 0x14) Status Register -------- */\r
+#define BPM_SR_PSOK (0x1u << 0) /**< \brief (BPM_SR) Power Scaling OK Status */\r
+/* -------- BPM_UNLOCK : (BPM Offset: 0x18) Unlock Register -------- */\r
+#define BPM_UNLOCK_ADDR_Pos 0\r
+#define BPM_UNLOCK_ADDR_Msk (0x3FFu << BPM_UNLOCK_ADDR_Pos) /**< \brief (BPM_UNLOCK) Unlock Address */\r
+#define BPM_UNLOCK_ADDR(value) ((BPM_UNLOCK_ADDR_Msk & ((value) << BPM_UNLOCK_ADDR_Pos)))\r
+#define BPM_UNLOCK_KEY_Pos 24\r
+#define BPM_UNLOCK_KEY_Msk (0xFFu << BPM_UNLOCK_KEY_Pos) /**< \brief (BPM_UNLOCK) Unlock Key */\r
+#define BPM_UNLOCK_KEY(value) ((BPM_UNLOCK_KEY_Msk & ((value) << BPM_UNLOCK_KEY_Pos)))\r
+/* -------- BPM_PMCON : (BPM Offset: 0x1C) Power Mode Control Register -------- */\r
+#define BPM_PMCON_PS_Pos 0\r
+#define BPM_PMCON_PS_Msk (0x3u << BPM_PMCON_PS_Pos) /**< \brief (BPM_PMCON) Power Scaling Configuration Value */\r
+#define BPM_PMCON_PS(value) ((BPM_PMCON_PS_Msk & ((value) << BPM_PMCON_PS_Pos)))\r
+#define BPM_PMCON_PSCREQ (0x1u << 2) /**< \brief (BPM_PMCON) Power Scaling Change Request */\r
+#define BPM_PMCON_PSCM (0x1u << 3) /**< \brief (BPM_PMCON) Power Scaling Change Mode */\r
+#define BPM_PMCON_BKUP (0x1u << 8) /**< \brief (BPM_PMCON) BACKUP Mode */\r
+#define BPM_PMCON_RET (0x1u << 9) /**< \brief (BPM_PMCON) RETENTION Mode */\r
+#define BPM_PMCON_SLEEP_Pos 12\r
+#define BPM_PMCON_SLEEP_Msk (0x3u << BPM_PMCON_SLEEP_Pos) /**< \brief (BPM_PMCON) SLEEP mode Configuration */\r
+#define BPM_PMCON_SLEEP(value) ((BPM_PMCON_SLEEP_Msk & ((value) << BPM_PMCON_SLEEP_Pos)))\r
+#define BPM_PMCON_CK32S (0x1u << 16) /**< \brief (BPM_PMCON) 32Khz-1Khz Clock Source Selection */\r
+#define BPM_PMCON_FASTWKUP (0x1u << 24) /**< \brief (BPM_PMCON) Fast Wakeup */\r
+/* -------- BPM_BKUPPMUX : (BPM Offset: 0x30) Backup Pin Muxing Register -------- */\r
+#define BPM_BKUPPMUX_BKUPPMUX_Pos 0\r
+#define BPM_BKUPPMUX_BKUPPMUX_Msk (0x1FFu << BPM_BKUPPMUX_BKUPPMUX_Pos) /**< \brief (BPM_BKUPPMUX) Backup Pin Muxing */\r
+#define BPM_BKUPPMUX_BKUPPMUX(value) ((BPM_BKUPPMUX_BKUPPMUX_Msk & ((value) << BPM_BKUPPMUX_BKUPPMUX_Pos)))\r
+/* -------- BPM_IORET : (BPM Offset: 0x34) Input Output Retention Register -------- */\r
+#define BPM_IORET_RET (0x1u << 0) /**< \brief (BPM_IORET) Retention on I/O lines after waking up from the BACKUP mode */\r
+/* -------- BPM_BPR : (BPM Offset: 0x40) Bypass Register -------- */\r
+#define BPM_BPR_RUNPSPB (0x1u << 0) /**< \brief (BPM_BPR) Run Mode Power Scaling Preset Bypass */\r
+#define BPM_BPR_PSMPSPB (0x1u << 1) /**< \brief (BPM_BPR) Power Save Mode Power Scaling Preset Bypass */\r
+#define BPM_BPR_SEQSTN (0x1u << 2) /**< \brief (BPM_BPR) Sequencial Startup from ULP (Active Low) */\r
+#define BPM_BPR_PSBTD (0x1u << 3) /**< \brief (BPM_BPR) Power Scaling Bias Timing Disable */\r
+#define BPM_BPR_PSHFD (0x1u << 4) /**< \brief (BPM_BPR) Power Scaling Halt Flash Until VREGOK Disable */\r
+#define BPM_BPR_DLYRSTD (0x1u << 5) /**< \brief (BPM_BPR) Delaying Reset Disable */\r
+#define BPM_BPR_BIASSEN (0x1u << 6) /**< \brief (BPM_BPR) Bias Switch Enable */\r
+#define BPM_BPR_LATSEN (0x1u << 7) /**< \brief (BPM_BPR) Latdel Switch Enable */\r
+#define BPM_BPR_BOD18CONT (0x1u << 8) /**< \brief (BPM_BPR) BOD18 in continuous mode not disabled in WAIT/RET/BACKUP modes */\r
+#define BPM_BPR_POBS (0x1u << 9) /**< \brief (BPM_BPR) Pico Uart Observability */\r
+#define BPM_BPR_FFFW (0x1u << 10) /**< \brief (BPM_BPR) Force Flash Fast Wakeup */\r
+#define BPM_BPR_FBRDYEN (0x1u << 11) /**< \brief (BPM_BPR) Flash Bias Ready Enable */\r
+#define BPM_BPR_FVREFSEN (0x1u << 12) /**< \brief (BPM_BPR) Flash Vref Switch Enable */\r
+/* -------- BPM_FWRUNPS : (BPM Offset: 0x44) Factory Word Run PS Register -------- */\r
+#define BPM_FWRUNPS_REGLEVEL_Pos 0\r
+#define BPM_FWRUNPS_REGLEVEL_Msk (0xFu << BPM_FWRUNPS_REGLEVEL_Pos) /**< \brief (BPM_FWRUNPS) Regulator Voltage Level */\r
+#define BPM_FWRUNPS_REGLEVEL(value) ((BPM_FWRUNPS_REGLEVEL_Msk & ((value) << BPM_FWRUNPS_REGLEVEL_Pos)))\r
+#define BPM_FWRUNPS_REGTYPE_Pos 4\r
+#define BPM_FWRUNPS_REGTYPE_Msk (0x3u << BPM_FWRUNPS_REGTYPE_Pos) /**< \brief (BPM_FWRUNPS) Regulator Type */\r
+#define BPM_FWRUNPS_REGTYPE(value) ((BPM_FWRUNPS_REGTYPE_Msk & ((value) << BPM_FWRUNPS_REGTYPE_Pos)))\r
+#define BPM_FWRUNPS_REGTYPE_NORMAL (0x0u << 4) /**< \brief (BPM_FWRUNPS) */\r
+#define BPM_FWRUNPS_REGTYPE_LP (0x1u << 4) /**< \brief (BPM_FWRUNPS) */\r
+#define BPM_FWRUNPS_REGTYPE_XULP (0x2u << 4) /**< \brief (BPM_FWRUNPS) */\r
+#define BPM_FWRUNPS_REFTYPE_Pos 6\r
+#define BPM_FWRUNPS_REFTYPE_Msk (0x3u << BPM_FWRUNPS_REFTYPE_Pos) /**< \brief (BPM_FWRUNPS) Reference Type */\r
+#define BPM_FWRUNPS_REFTYPE(value) ((BPM_FWRUNPS_REFTYPE_Msk & ((value) << BPM_FWRUNPS_REFTYPE_Pos)))\r
+#define BPM_FWRUNPS_REFTYPE_BOTH (0x0u << 6) /**< \brief (BPM_FWRUNPS) */\r
+#define BPM_FWRUNPS_REFTYPE_BG (0x1u << 6) /**< \brief (BPM_FWRUNPS) */\r
+#define BPM_FWRUNPS_REFTYPE_LPBG (0x2u << 6) /**< \brief (BPM_FWRUNPS) */\r
+#define BPM_FWRUNPS_REFTYPE_INTERNAL (0x3u << 6) /**< \brief (BPM_FWRUNPS) */\r
+#define BPM_FWRUNPS_FLASHLATDEL_Pos 8\r
+#define BPM_FWRUNPS_FLASHLATDEL_Msk (0x1Fu << BPM_FWRUNPS_FLASHLATDEL_Pos) /**< \brief (BPM_FWRUNPS) Flash Latch Delay Value */\r
+#define BPM_FWRUNPS_FLASHLATDEL(value) ((BPM_FWRUNPS_FLASHLATDEL_Msk & ((value) << BPM_FWRUNPS_FLASHLATDEL_Pos)))\r
+#define BPM_FWRUNPS_FLASHBIAS_Pos 13\r
+#define BPM_FWRUNPS_FLASHBIAS_Msk (0xFu << BPM_FWRUNPS_FLASHBIAS_Pos) /**< \brief (BPM_FWRUNPS) Flash Bias Value */\r
+#define BPM_FWRUNPS_FLASHBIAS(value) ((BPM_FWRUNPS_FLASHBIAS_Msk & ((value) << BPM_FWRUNPS_FLASHBIAS_Pos)))\r
+#define BPM_FWRUNPS_FPPW (0x1u << 17) /**< \brief (BPM_FWRUNPS) Flash Pico Power Mode */\r
+#define BPM_FWRUNPS_RC115_Pos 18\r
+#define BPM_FWRUNPS_RC115_Msk (0x7Fu << BPM_FWRUNPS_RC115_Pos) /**< \brief (BPM_FWRUNPS) RC 115KHZ Calibration Value */\r
+#define BPM_FWRUNPS_RC115(value) ((BPM_FWRUNPS_RC115_Msk & ((value) << BPM_FWRUNPS_RC115_Pos)))\r
+#define BPM_FWRUNPS_RCFAST_Pos 25\r
+#define BPM_FWRUNPS_RCFAST_Msk (0x7Fu << BPM_FWRUNPS_RCFAST_Pos) /**< \brief (BPM_FWRUNPS) RCFAST Calibration Value */\r
+#define BPM_FWRUNPS_RCFAST(value) ((BPM_FWRUNPS_RCFAST_Msk & ((value) << BPM_FWRUNPS_RCFAST_Pos)))\r
+/* -------- BPM_FWPSAVEPS : (BPM Offset: 0x48) Factory Word Power Save PS Register -------- */\r
+#define BPM_FWPSAVEPS_WREGLEVEL_Pos 0\r
+#define BPM_FWPSAVEPS_WREGLEVEL_Msk (0xFu << BPM_FWPSAVEPS_WREGLEVEL_Pos) /**< \brief (BPM_FWPSAVEPS) Wait mode Regulator Level */\r
+#define BPM_FWPSAVEPS_WREGLEVEL(value) ((BPM_FWPSAVEPS_WREGLEVEL_Msk & ((value) << BPM_FWPSAVEPS_WREGLEVEL_Pos)))\r
+#define BPM_FWPSAVEPS_WBIAS_Pos 4\r
+#define BPM_FWPSAVEPS_WBIAS_Msk (0xFu << BPM_FWPSAVEPS_WBIAS_Pos) /**< \brief (BPM_FWPSAVEPS) Bias in wait mode */\r
+#define BPM_FWPSAVEPS_WBIAS(value) ((BPM_FWPSAVEPS_WBIAS_Msk & ((value) << BPM_FWPSAVEPS_WBIAS_Pos)))\r
+#define BPM_FWPSAVEPS_WLATDEL_Pos 8\r
+#define BPM_FWPSAVEPS_WLATDEL_Msk (0x1Fu << BPM_FWPSAVEPS_WLATDEL_Pos) /**< \brief (BPM_FWPSAVEPS) Flash Latdel in wait mode */\r
+#define BPM_FWPSAVEPS_WLATDEL(value) ((BPM_FWPSAVEPS_WLATDEL_Msk & ((value) << BPM_FWPSAVEPS_WLATDEL_Pos)))\r
+#define BPM_FWPSAVEPS_RREGLEVEL_Pos 13\r
+#define BPM_FWPSAVEPS_RREGLEVEL_Msk (0xFu << BPM_FWPSAVEPS_RREGLEVEL_Pos) /**< \brief (BPM_FWPSAVEPS) Retention mode Regulator Level */\r
+#define BPM_FWPSAVEPS_RREGLEVEL(value) ((BPM_FWPSAVEPS_RREGLEVEL_Msk & ((value) << BPM_FWPSAVEPS_RREGLEVEL_Pos)))\r
+#define BPM_FWPSAVEPS_RBIAS_Pos 17\r
+#define BPM_FWPSAVEPS_RBIAS_Msk (0xFu << BPM_FWPSAVEPS_RBIAS_Pos) /**< \brief (BPM_FWPSAVEPS) Bias in Retention mode */\r
+#define BPM_FWPSAVEPS_RBIAS(value) ((BPM_FWPSAVEPS_RBIAS_Msk & ((value) << BPM_FWPSAVEPS_RBIAS_Pos)))\r
+#define BPM_FWPSAVEPS_RLATDEL_Pos 21\r
+#define BPM_FWPSAVEPS_RLATDEL_Msk (0x1Fu << BPM_FWPSAVEPS_RLATDEL_Pos) /**< \brief (BPM_FWPSAVEPS) Flash Latdel in Retention mode */\r
+#define BPM_FWPSAVEPS_RLATDEL(value) ((BPM_FWPSAVEPS_RLATDEL_Msk & ((value) << BPM_FWPSAVEPS_RLATDEL_Pos)))\r
+#define BPM_FWPSAVEPS_BREGLEVEL_Pos 26\r
+#define BPM_FWPSAVEPS_BREGLEVEL_Msk (0xFu << BPM_FWPSAVEPS_BREGLEVEL_Pos) /**< \brief (BPM_FWPSAVEPS) Backup mode Regulator Level */\r
+#define BPM_FWPSAVEPS_BREGLEVEL(value) ((BPM_FWPSAVEPS_BREGLEVEL_Msk & ((value) << BPM_FWPSAVEPS_BREGLEVEL_Pos)))\r
+#define BPM_FWPSAVEPS_POR18DIS (0x1u << 30) /**< \brief (BPM_FWPSAVEPS) POR 18 Disable */\r
+#define BPM_FWPSAVEPS_FWSAS (0x1u << 31) /**< \brief (BPM_FWPSAVEPS) Flash Wait State Automatic Switching */\r
+/* -------- BPM_VERSION : (BPM Offset: 0xFC) Version Register -------- */\r
+#define BPM_VERSION_VERSION_Pos 0\r
+#define BPM_VERSION_VERSION_Msk (0xFFFu << BPM_VERSION_VERSION_Pos) /**< \brief (BPM_VERSION) Version Number */\r
+#define BPM_VERSION_VERSION(value) ((BPM_VERSION_VERSION_Msk & ((value) << BPM_VERSION_VERSION_Pos)))\r
+#define BPM_VERSION_VARIANT_Pos 16\r
+#define BPM_VERSION_VARIANT_Msk (0xFu << BPM_VERSION_VARIANT_Pos) /**< \brief (BPM_VERSION) Variant Number */\r
+#define BPM_VERSION_VARIANT(value) ((BPM_VERSION_VARIANT_Msk & ((value) << BPM_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR BSCIF */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_BSCIF Backup System Control Interface */\r
+/*@{*/\r
+\r
+#define REV_BSCIF 0x100\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief BscifBr hardware registers */\r
+typedef struct {\r
+ RwReg BSCIF_BR; /**< \brief (BscifBr Offset: 0x000) Backup Register */\r
+} BscifBr;\r
+/** \brief BSCIF hardware registers */\r
+typedef struct {\r
+ WoReg BSCIF_IER; /**< \brief (BSCIF Offset: 0x000) Interrupt Enable Register */\r
+ WoReg BSCIF_IDR; /**< \brief (BSCIF Offset: 0x004) Interrupt Disable Register */\r
+ RoReg BSCIF_IMR; /**< \brief (BSCIF Offset: 0x008) Interrupt Mask Register */\r
+ RoReg BSCIF_ISR; /**< \brief (BSCIF Offset: 0x00C) Interrupt Status Register */\r
+ WoReg BSCIF_ICR; /**< \brief (BSCIF Offset: 0x010) Interrupt Clear Register */\r
+ RoReg BSCIF_PCLKSR; /**< \brief (BSCIF Offset: 0x014) Power and Clocks Status Register */\r
+ WoReg BSCIF_UNLOCK; /**< \brief (BSCIF Offset: 0x018) Unlock Register */\r
+ RwReg BSCIF_CSCR; /**< \brief (BSCIF Offset: 0x01C) Chip Specific Configuration Register */\r
+ RwReg BSCIF_OSCCTRL32; /**< \brief (BSCIF Offset: 0x020) Oscillator 32 Control Register */\r
+ RwReg BSCIF_RC32KCR; /**< \brief (BSCIF Offset: 0x024) 32 kHz RC Oscillator Control Register */\r
+ RwReg BSCIF_RC32KTUNE; /**< \brief (BSCIF Offset: 0x028) 32kHz RC Oscillator Tuning Register */\r
+ RwReg BSCIF_BOD33CTRL; /**< \brief (BSCIF Offset: 0x02C) BOD33 Control Register */\r
+ RwReg BSCIF_BOD33LEVEL; /**< \brief (BSCIF Offset: 0x030) BOD33 Level Register */\r
+ RwReg BSCIF_BOD33SAMPLING; /**< \brief (BSCIF Offset: 0x034) BOD33 Sampling Control Register */\r
+ RwReg BSCIF_BOD18CTRL; /**< \brief (BSCIF Offset: 0x038) BOD18 Control Register */\r
+ RwReg BSCIF_BOD18LEVEL; /**< \brief (BSCIF Offset: 0x03C) BOD18 Level Register */\r
+ RoReg Reserved1[1];\r
+ RwReg BSCIF_VREGCR; /**< \brief (BSCIF Offset: 0x044) Voltage Regulator Configuration Register */\r
+ RoReg Reserved2[1];\r
+ RwReg BSCIF_VREGNCSR; /**< \brief (BSCIF Offset: 0x04C) Normal Mode Control and Status Register */\r
+ RwReg BSCIF_VREGLPCSR; /**< \brief (BSCIF Offset: 0x050) LP Mode Control and Status Register */\r
+ RoReg Reserved3[1];\r
+ RwReg BSCIF_RC1MCR; /**< \brief (BSCIF Offset: 0x058) 1MHz RC Clock Configuration Register */\r
+ RwReg BSCIF_BGCR; /**< \brief (BSCIF Offset: 0x05C) Bandgap Calibration Register */\r
+ RwReg BSCIF_BGCTRL; /**< \brief (BSCIF Offset: 0x060) Bandgap Control Register */\r
+ RoReg BSCIF_BGSR; /**< \brief (BSCIF Offset: 0x064) Bandgap Status Register */\r
+ RoReg Reserved4[4];\r
+ BscifBr BSCIF_BR[4]; /**< \brief (BSCIF Offset: 0x078) BscifBr groups */\r
+ RoReg Reserved5[215];\r
+ RoReg BSCIF_BRIFBVERSION; /**< \brief (BSCIF Offset: 0x3E4) Backup Register Interface Version Register */\r
+ RoReg BSCIF_BGREFIFBVERSION; /**< \brief (BSCIF Offset: 0x3E8) BGREFIFB Version Register */\r
+ RoReg BSCIF_VREGIFGVERSION; /**< \brief (BSCIF Offset: 0x3EC) VREGIFA Version Register */\r
+ RoReg BSCIF_BODIFCVERSION; /**< \brief (BSCIF Offset: 0x3F0) BODIFC Version Register */\r
+ RoReg BSCIF_RC32KIFBVERSION; /**< \brief (BSCIF Offset: 0x3F4) 32 kHz RC Oscillator Version Register */\r
+ RoReg BSCIF_OSC32IFAVERSION; /**< \brief (BSCIF Offset: 0x3F8) 32 KHz Oscillator Version Register */\r
+ RoReg BSCIF_VERSION; /**< \brief (BSCIF Offset: 0x3FC) BSCIF Version Register */\r
+} Bscif;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- BSCIF_IER : (BSCIF Offset: 0x000) Interrupt Enable Register -------- */\r
+#define BSCIF_IER_OSC32RDY (0x1u << 0) /**< \brief (BSCIF_IER) */\r
+#define BSCIF_IER_RC32KRDY (0x1u << 1) /**< \brief (BSCIF_IER) */\r
+#define BSCIF_IER_RC32KLOCK (0x1u << 2) /**< \brief (BSCIF_IER) */\r
+#define BSCIF_IER_RC32KREFE (0x1u << 3) /**< \brief (BSCIF_IER) */\r
+#define BSCIF_IER_RC32KSAT (0x1u << 4) /**< \brief (BSCIF_IER) */\r
+#define BSCIF_IER_BOD33DET (0x1u << 5) /**< \brief (BSCIF_IER) BOD33 Detected */\r
+#define BSCIF_IER_BOD18DET (0x1u << 6) /**< \brief (BSCIF_IER) BOD18 Detected */\r
+#define BSCIF_IER_BOD33SYNRDY (0x1u << 7) /**< \brief (BSCIF_IER) BOD33 Synchronization Ready */\r
+#define BSCIF_IER_BOD18SYNRDY (0x1u << 8) /**< \brief (BSCIF_IER) BOD18 Synchronization Ready */\r
+#define BSCIF_IER_SSWRDY (0x1u << 9) /**< \brief (BSCIF_IER) VREG Stop Switching Ready */\r
+#define BSCIF_IER_VREGOK (0x1u << 10) /**< \brief (BSCIF_IER) Main VREG OK */\r
+#define BSCIF_IER_LPBGRDY (0x1u << 12) /**< \brief (BSCIF_IER) Low Power Bandgap Voltage Reference Ready */\r
+#define BSCIF_IER_AE (0x1u << 31) /**< \brief (BSCIF_IER) Access Error */\r
+/* -------- BSCIF_IDR : (BSCIF Offset: 0x004) Interrupt Disable Register -------- */\r
+#define BSCIF_IDR_OSC32RDY (0x1u << 0) /**< \brief (BSCIF_IDR) */\r
+#define BSCIF_IDR_RC32KRDY (0x1u << 1) /**< \brief (BSCIF_IDR) */\r
+#define BSCIF_IDR_RC32KLOCK (0x1u << 2) /**< \brief (BSCIF_IDR) */\r
+#define BSCIF_IDR_RC32KREFE (0x1u << 3) /**< \brief (BSCIF_IDR) */\r
+#define BSCIF_IDR_RC32KSAT (0x1u << 4) /**< \brief (BSCIF_IDR) */\r
+#define BSCIF_IDR_BOD33DET (0x1u << 5) /**< \brief (BSCIF_IDR) BOD33 Detected */\r
+#define BSCIF_IDR_BOD18DET (0x1u << 6) /**< \brief (BSCIF_IDR) BOD18 Detected */\r
+#define BSCIF_IDR_BOD33SYNRDY (0x1u << 7) /**< \brief (BSCIF_IDR) BOD33 Synchronization Ready */\r
+#define BSCIF_IDR_BOD18SYNRDY (0x1u << 8) /**< \brief (BSCIF_IDR) BOD18 Synchronization Ready */\r
+#define BSCIF_IDR_SSWRDY (0x1u << 9) /**< \brief (BSCIF_IDR) VREG Stop Switching Ready */\r
+#define BSCIF_IDR_VREGOK (0x1u << 10) /**< \brief (BSCIF_IDR) Mai n VREG OK */\r
+#define BSCIF_IDR_LPBGRDY (0x1u << 12) /**< \brief (BSCIF_IDR) Low Power Bandgap Voltage Reference Ready */\r
+#define BSCIF_IDR_AE (0x1u << 31) /**< \brief (BSCIF_IDR) Access Error */\r
+/* -------- BSCIF_IMR : (BSCIF Offset: 0x008) Interrupt Mask Register -------- */\r
+#define BSCIF_IMR_OSC32RDY (0x1u << 0) /**< \brief (BSCIF_IMR) */\r
+#define BSCIF_IMR_RC32KRDY (0x1u << 1) /**< \brief (BSCIF_IMR) */\r
+#define BSCIF_IMR_RC32KLOCK (0x1u << 2) /**< \brief (BSCIF_IMR) */\r
+#define BSCIF_IMR_RC32KREFE (0x1u << 3) /**< \brief (BSCIF_IMR) */\r
+#define BSCIF_IMR_RC32KSAT (0x1u << 4) /**< \brief (BSCIF_IMR) */\r
+#define BSCIF_IMR_BOD33DET (0x1u << 5) /**< \brief (BSCIF_IMR) BOD33 Detected */\r
+#define BSCIF_IMR_BOD18DET (0x1u << 6) /**< \brief (BSCIF_IMR) BOD18 Detected */\r
+#define BSCIF_IMR_BOD33SYNRDY (0x1u << 7) /**< \brief (BSCIF_IMR) BOD33 Synchronization Ready */\r
+#define BSCIF_IMR_BOD18SYNRDY (0x1u << 8) /**< \brief (BSCIF_IMR) BOD18 Synchronization Ready */\r
+#define BSCIF_IMR_SSWRDY (0x1u << 9) /**< \brief (BSCIF_IMR) VREG Stop Switching Ready */\r
+#define BSCIF_IMR_VREGOK (0x1u << 10) /**< \brief (BSCIF_IMR) Main VREG OK */\r
+#define BSCIF_IMR_LPBGRDY (0x1u << 12) /**< \brief (BSCIF_IMR) Low Power Bandgap Voltage Reference Ready */\r
+#define BSCIF_IMR_AE (0x1u << 31) /**< \brief (BSCIF_IMR) Access Error */\r
+/* -------- BSCIF_ISR : (BSCIF Offset: 0x00C) Interrupt Status Register -------- */\r
+#define BSCIF_ISR_OSC32RDY (0x1u << 0) /**< \brief (BSCIF_ISR) */\r
+#define BSCIF_ISR_RC32KRDY (0x1u << 1) /**< \brief (BSCIF_ISR) */\r
+#define BSCIF_ISR_RC32KLOCK (0x1u << 2) /**< \brief (BSCIF_ISR) */\r
+#define BSCIF_ISR_RC32KREFE (0x1u << 3) /**< \brief (BSCIF_ISR) */\r
+#define BSCIF_ISR_RC32KSAT (0x1u << 4) /**< \brief (BSCIF_ISR) */\r
+#define BSCIF_ISR_BOD33DET (0x1u << 5) /**< \brief (BSCIF_ISR) BOD33 Detected */\r
+#define BSCIF_ISR_BOD18DET (0x1u << 6) /**< \brief (BSCIF_ISR) BOD18 Detected */\r
+#define BSCIF_ISR_BOD33SYNRDY (0x1u << 7) /**< \brief (BSCIF_ISR) BOD33 Synchronization Ready */\r
+#define BSCIF_ISR_BOD18SYNRDY (0x1u << 8) /**< \brief (BSCIF_ISR) BOD18 Synchronization Ready */\r
+#define BSCIF_ISR_SSWRDY (0x1u << 9) /**< \brief (BSCIF_ISR) VREG Stop Switching Ready */\r
+#define BSCIF_ISR_VREGOK (0x1u << 10) /**< \brief (BSCIF_ISR) Main VREG OK */\r
+#define BSCIF_ISR_LPBGRDY (0x1u << 12) /**< \brief (BSCIF_ISR) Low Power Bandgap Voltage Reference Ready */\r
+#define BSCIF_ISR_AE (0x1u << 31) /**< \brief (BSCIF_ISR) Access Error */\r
+/* -------- BSCIF_ICR : (BSCIF Offset: 0x010) Interrupt Clear Register -------- */\r
+#define BSCIF_ICR_OSC32RDY (0x1u << 0) /**< \brief (BSCIF_ICR) */\r
+#define BSCIF_ICR_RC32KRDY (0x1u << 1) /**< \brief (BSCIF_ICR) */\r
+#define BSCIF_ICR_RC32KLOCK (0x1u << 2) /**< \brief (BSCIF_ICR) */\r
+#define BSCIF_ICR_RC32KREFE (0x1u << 3) /**< \brief (BSCIF_ICR) */\r
+#define BSCIF_ICR_RC32KSAT (0x1u << 4) /**< \brief (BSCIF_ICR) */\r
+#define BSCIF_ICR_BOD33DET (0x1u << 5) /**< \brief (BSCIF_ICR) BOD33 Detected */\r
+#define BSCIF_ICR_BOD18DET (0x1u << 6) /**< \brief (BSCIF_ICR) BOD18 Detected */\r
+#define BSCIF_ICR_BOD33SYNRDY (0x1u << 7) /**< \brief (BSCIF_ICR) BOD33 Synchronization Ready */\r
+#define BSCIF_ICR_BOD18SYNRDY (0x1u << 8) /**< \brief (BSCIF_ICR) BOD18 Synchronization Ready */\r
+#define BSCIF_ICR_SSWRDY (0x1u << 9) /**< \brief (BSCIF_ICR) VREG Stop Switching Ready */\r
+#define BSCIF_ICR_VREGOK (0x1u << 10) /**< \brief (BSCIF_ICR) Main VREG OK */\r
+#define BSCIF_ICR_LPBGRDY (0x1u << 12) /**< \brief (BSCIF_ICR) Low Power Bandgap Voltage Reference Ready */\r
+#define BSCIF_ICR_AE (0x1u << 31) /**< \brief (BSCIF_ICR) Access Error */\r
+/* -------- BSCIF_PCLKSR : (BSCIF Offset: 0x014) Power and Clocks Status Register -------- */\r
+#define BSCIF_PCLKSR_OSC32RDY (0x1u << 0) /**< \brief (BSCIF_PCLKSR) */\r
+#define BSCIF_PCLKSR_RC32KRDY (0x1u << 1) /**< \brief (BSCIF_PCLKSR) */\r
+#define BSCIF_PCLKSR_RC32KLOCK (0x1u << 2) /**< \brief (BSCIF_PCLKSR) */\r
+#define BSCIF_PCLKSR_RC32KREFE (0x1u << 3) /**< \brief (BSCIF_PCLKSR) */\r
+#define BSCIF_PCLKSR_RC32KSAT (0x1u << 4) /**< \brief (BSCIF_PCLKSR) */\r
+#define BSCIF_PCLKSR_BOD33DET (0x1u << 5) /**< \brief (BSCIF_PCLKSR) BOD33 Detected */\r
+#define BSCIF_PCLKSR_BOD18DET (0x1u << 6) /**< \brief (BSCIF_PCLKSR) BOD18 Detected */\r
+#define BSCIF_PCLKSR_BOD33SYNRDY (0x1u << 7) /**< \brief (BSCIF_PCLKSR) BOD33 Synchronization Ready */\r
+#define BSCIF_PCLKSR_BOD18SYNRDY (0x1u << 8) /**< \brief (BSCIF_PCLKSR) BOD18 Synchronization Ready */\r
+#define BSCIF_PCLKSR_SSWRDY (0x1u << 9) /**< \brief (BSCIF_PCLKSR) VREG Stop Switching Ready */\r
+#define BSCIF_PCLKSR_VREGOK (0x1u << 10) /**< \brief (BSCIF_PCLKSR) Main VREG OK */\r
+#define BSCIF_PCLKSR_RC1MRDY (0x1u << 11) /**< \brief (BSCIF_PCLKSR) RC 1MHz Oscillator Ready */\r
+#define BSCIF_PCLKSR_LPBGRDY (0x1u << 12) /**< \brief (BSCIF_PCLKSR) Low Power Bandgap Voltage Reference Ready */\r
+/* -------- BSCIF_UNLOCK : (BSCIF Offset: 0x018) Unlock Register -------- */\r
+#define BSCIF_UNLOCK_ADDR_Pos 0\r
+#define BSCIF_UNLOCK_ADDR_Msk (0x3FFu << BSCIF_UNLOCK_ADDR_Pos) /**< \brief (BSCIF_UNLOCK) Unlock Address */\r
+#define BSCIF_UNLOCK_ADDR(value) ((BSCIF_UNLOCK_ADDR_Msk & ((value) << BSCIF_UNLOCK_ADDR_Pos)))\r
+#define BSCIF_UNLOCK_KEY_Pos 24\r
+#define BSCIF_UNLOCK_KEY_Msk (0xFFu << BSCIF_UNLOCK_KEY_Pos) /**< \brief (BSCIF_UNLOCK) Unlock Key */\r
+#define BSCIF_UNLOCK_KEY(value) ((BSCIF_UNLOCK_KEY_Msk & ((value) << BSCIF_UNLOCK_KEY_Pos)))\r
+#define BSCIF_UNLOCK_KEY_VALID (0xAAu << 24) /**< \brief (BSCIF_UNLOCK) Valid Key to Unlock register */\r
+/* -------- BSCIF_CSCR : (BSCIF Offset: 0x01C) Chip Specific Configuration Register -------- */\r
+/* -------- BSCIF_OSCCTRL32 : (BSCIF Offset: 0x020) Oscillator 32 Control Register -------- */\r
+#define BSCIF_OSCCTRL32_OSC32EN (0x1u << 0) /**< \brief (BSCIF_OSCCTRL32) 32 KHz Oscillator Enable */\r
+#define BSCIF_OSCCTRL32_PINSEL (0x1u << 1) /**< \brief (BSCIF_OSCCTRL32) Pins Select */\r
+#define BSCIF_OSCCTRL32_EN32K (0x1u << 2) /**< \brief (BSCIF_OSCCTRL32) 32 KHz output Enable */\r
+#define BSCIF_OSCCTRL32_EN1K (0x1u << 3) /**< \brief (BSCIF_OSCCTRL32) 1 KHz output Enable */\r
+#define BSCIF_OSCCTRL32_MODE_Pos 8\r
+#define BSCIF_OSCCTRL32_MODE_Msk (0x7u << BSCIF_OSCCTRL32_MODE_Pos) /**< \brief (BSCIF_OSCCTRL32) Oscillator Mode */\r
+#define BSCIF_OSCCTRL32_MODE(value) ((BSCIF_OSCCTRL32_MODE_Msk & ((value) << BSCIF_OSCCTRL32_MODE_Pos)))\r
+#define BSCIF_OSCCTRL32_SELCURR_Pos 12\r
+#define BSCIF_OSCCTRL32_SELCURR_Msk (0xFu << BSCIF_OSCCTRL32_SELCURR_Pos) /**< \brief (BSCIF_OSCCTRL32) Current selection */\r
+#define BSCIF_OSCCTRL32_SELCURR(value) ((BSCIF_OSCCTRL32_SELCURR_Msk & ((value) << BSCIF_OSCCTRL32_SELCURR_Pos)))\r
+#define BSCIF_OSCCTRL32_STARTUP_Pos 16\r
+#define BSCIF_OSCCTRL32_STARTUP_Msk (0x7u << BSCIF_OSCCTRL32_STARTUP_Pos) /**< \brief (BSCIF_OSCCTRL32) Oscillator Start-up Time */\r
+#define BSCIF_OSCCTRL32_STARTUP(value) ((BSCIF_OSCCTRL32_STARTUP_Msk & ((value) << BSCIF_OSCCTRL32_STARTUP_Pos)))\r
+/* -------- BSCIF_RC32KCR : (BSCIF Offset: 0x024) 32 kHz RC Oscillator Control Register -------- */\r
+#define BSCIF_RC32KCR_EN (0x1u << 0) /**< \brief (BSCIF_RC32KCR) Enable as Generic clock source */\r
+#define BSCIF_RC32KCR_TCEN (0x1u << 1) /**< \brief (BSCIF_RC32KCR) Temperature Compensation Enable */\r
+#define BSCIF_RC32KCR_EN32K (0x1u << 2) /**< \brief (BSCIF_RC32KCR) Enable 32 KHz output */\r
+#define BSCIF_RC32KCR_EN1K (0x1u << 3) /**< \brief (BSCIF_RC32KCR) Enable 1 kHz output */\r
+#define BSCIF_RC32KCR_MODE (0x1u << 4) /**< \brief (BSCIF_RC32KCR) Mode Selection */\r
+#define BSCIF_RC32KCR_REF (0x1u << 5) /**< \brief (BSCIF_RC32KCR) Reference select */\r
+#define BSCIF_RC32KCR_FCD (0x1u << 7) /**< \brief (BSCIF_RC32KCR) Flash calibration done */\r
+/* -------- BSCIF_RC32KTUNE : (BSCIF Offset: 0x028) 32kHz RC Oscillator Tuning Register -------- */\r
+#define BSCIF_RC32KTUNE_FINE_Pos 0\r
+#define BSCIF_RC32KTUNE_FINE_Msk (0x3Fu << BSCIF_RC32KTUNE_FINE_Pos) /**< \brief (BSCIF_RC32KTUNE) Fine value */\r
+#define BSCIF_RC32KTUNE_FINE(value) ((BSCIF_RC32KTUNE_FINE_Msk & ((value) << BSCIF_RC32KTUNE_FINE_Pos)))\r
+#define BSCIF_RC32KTUNE_COARSE_Pos 16\r
+#define BSCIF_RC32KTUNE_COARSE_Msk (0x7Fu << BSCIF_RC32KTUNE_COARSE_Pos) /**< \brief (BSCIF_RC32KTUNE) Coarse Value */\r
+#define BSCIF_RC32KTUNE_COARSE(value) ((BSCIF_RC32KTUNE_COARSE_Msk & ((value) << BSCIF_RC32KTUNE_COARSE_Pos)))\r
+/* -------- BSCIF_BOD33CTRL : (BSCIF Offset: 0x02C) BOD33 Control Register -------- */\r
+#define BSCIF_BOD33CTRL_EN (0x1u << 0) /**< \brief (BSCIF_BOD33CTRL) Enable */\r
+#define BSCIF_BOD33CTRL_HYST (0x1u << 1) /**< \brief (BSCIF_BOD33CTRL) BOD Hysteresis */\r
+#define BSCIF_BOD33CTRL_ACTION_Pos 8\r
+#define BSCIF_BOD33CTRL_ACTION_Msk (0x3u << BSCIF_BOD33CTRL_ACTION_Pos) /**< \brief (BSCIF_BOD33CTRL) Action */\r
+#define BSCIF_BOD33CTRL_ACTION(value) ((BSCIF_BOD33CTRL_ACTION_Msk & ((value) << BSCIF_BOD33CTRL_ACTION_Pos)))\r
+#define BSCIF_BOD33CTRL_MODE (0x1u << 16) /**< \brief (BSCIF_BOD33CTRL) Operation modes */\r
+#define BSCIF_BOD33CTRL_FCD (0x1u << 30) /**< \brief (BSCIF_BOD33CTRL) BOD Fuse Calibration Done */\r
+#define BSCIF_BOD33CTRL_SFV (0x1u << 31) /**< \brief (BSCIF_BOD33CTRL) BOD Control Register Store Final Value */\r
+/* -------- BSCIF_BOD33LEVEL : (BSCIF Offset: 0x030) BOD33 Level Register -------- */\r
+#define BSCIF_BOD33LEVEL_VAL_Pos 0\r
+#define BSCIF_BOD33LEVEL_VAL_Msk (0x3Fu << BSCIF_BOD33LEVEL_VAL_Pos) /**< \brief (BSCIF_BOD33LEVEL) BOD Value */\r
+#define BSCIF_BOD33LEVEL_VAL(value) ((BSCIF_BOD33LEVEL_VAL_Msk & ((value) << BSCIF_BOD33LEVEL_VAL_Pos)))\r
+/* -------- BSCIF_BOD33SAMPLING : (BSCIF Offset: 0x034) BOD33 Sampling Control Register -------- */\r
+#define BSCIF_BOD33SAMPLING_CEN (0x1u << 0) /**< \brief (BSCIF_BOD33SAMPLING) Clock Enable */\r
+#define BSCIF_BOD33SAMPLING_CSSEL (0x1u << 1) /**< \brief (BSCIF_BOD33SAMPLING) Clock Source Select */\r
+#define BSCIF_BOD33SAMPLING_PSEL_Pos 8\r
+#define BSCIF_BOD33SAMPLING_PSEL_Msk (0xFu << BSCIF_BOD33SAMPLING_PSEL_Pos) /**< \brief (BSCIF_BOD33SAMPLING) Prescaler Select */\r
+#define BSCIF_BOD33SAMPLING_PSEL(value) ((BSCIF_BOD33SAMPLING_PSEL_Msk & ((value) << BSCIF_BOD33SAMPLING_PSEL_Pos)))\r
+/* -------- BSCIF_BOD18CTRL : (BSCIF Offset: 0x038) BOD18 Control Register -------- */\r
+#define BSCIF_BOD18CTRL_EN (0x1u << 0) /**< \brief (BSCIF_BOD18CTRL) Enable */\r
+#define BSCIF_BOD18CTRL_HYST (0x1u << 1) /**< \brief (BSCIF_BOD18CTRL) BOD Hysteresis */\r
+#define BSCIF_BOD18CTRL_ACTION_Pos 8\r
+#define BSCIF_BOD18CTRL_ACTION_Msk (0x3u << BSCIF_BOD18CTRL_ACTION_Pos) /**< \brief (BSCIF_BOD18CTRL) Action */\r
+#define BSCIF_BOD18CTRL_ACTION(value) ((BSCIF_BOD18CTRL_ACTION_Msk & ((value) << BSCIF_BOD18CTRL_ACTION_Pos)))\r
+#define BSCIF_BOD18CTRL_MODE (0x1u << 16) /**< \brief (BSCIF_BOD18CTRL) Operation modes */\r
+#define BSCIF_BOD18CTRL_FCD (0x1u << 30) /**< \brief (BSCIF_BOD18CTRL) BOD Fuse Calibration Done */\r
+#define BSCIF_BOD18CTRL_SFV (0x1u << 31) /**< \brief (BSCIF_BOD18CTRL) BOD Control Register Store Final Value */\r
+/* -------- BSCIF_BOD18LEVEL : (BSCIF Offset: 0x03C) BOD18 Level Register -------- */\r
+#define BSCIF_BOD18LEVEL_VAL_Pos 0\r
+#define BSCIF_BOD18LEVEL_VAL_Msk (0x3Fu << BSCIF_BOD18LEVEL_VAL_Pos) /**< \brief (BSCIF_BOD18LEVEL) BOD Value */\r
+#define BSCIF_BOD18LEVEL_VAL(value) ((BSCIF_BOD18LEVEL_VAL_Msk & ((value) << BSCIF_BOD18LEVEL_VAL_Pos)))\r
+#define BSCIF_BOD18LEVEL_RANGE (0x1u << 31) /**< \brief (BSCIF_BOD18LEVEL) BOD Threshold Range */\r
+/* -------- BSCIF_VREGCR : (BSCIF Offset: 0x044) Voltage Regulator Configuration Register -------- */\r
+#define BSCIF_VREGCR_DIS (0x1u << 0) /**< \brief (BSCIF_VREGCR) Voltage Regulator disable */\r
+#define BSCIF_VREGCR_SSG (0x1u << 8) /**< \brief (BSCIF_VREGCR) Spread Spectrum Generator Enable */\r
+#define BSCIF_VREGCR_SSW (0x1u << 9) /**< \brief (BSCIF_VREGCR) Stop Switching */\r
+#define BSCIF_VREGCR_SSWEVT (0x1u << 10) /**< \brief (BSCIF_VREGCR) Stop Switching On Event Enable */\r
+#define BSCIF_VREGCR_SFV (0x1u << 31) /**< \brief (BSCIF_VREGCR) Store Final Value */\r
+/* -------- BSCIF_VREGNCSR : (BSCIF Offset: 0x04C) Normal Mode Control and Status Register -------- */\r
+/* -------- BSCIF_VREGLPCSR : (BSCIF Offset: 0x050) LP Mode Control and Status Register -------- */\r
+/* -------- BSCIF_RC1MCR : (BSCIF Offset: 0x058) 1MHz RC Clock Configuration Register -------- */\r
+#define BSCIF_RC1MCR_CLKOE (0x1u << 0) /**< \brief (BSCIF_RC1MCR) 1MHz RC Osc Clock Output Enable */\r
+#define BSCIF_RC1MCR_FCD (0x1u << 7) /**< \brief (BSCIF_RC1MCR) Flash Calibration Done */\r
+#define BSCIF_RC1MCR_CLKCAL_Pos 8\r
+#define BSCIF_RC1MCR_CLKCAL_Msk (0x1Fu << BSCIF_RC1MCR_CLKCAL_Pos) /**< \brief (BSCIF_RC1MCR) 1MHz RC Osc Calibration */\r
+#define BSCIF_RC1MCR_CLKCAL(value) ((BSCIF_RC1MCR_CLKCAL_Msk & ((value) << BSCIF_RC1MCR_CLKCAL_Pos)))\r
+/* -------- BSCIF_BGCR : (BSCIF Offset: 0x05C) Bandgap Calibration Register -------- */\r
+/* -------- BSCIF_BGCTRL : (BSCIF Offset: 0x060) Bandgap Control Register -------- */\r
+#define BSCIF_BGCTRL_ADCISEL_Pos 0\r
+#define BSCIF_BGCTRL_ADCISEL_Msk (0x3u << BSCIF_BGCTRL_ADCISEL_Pos) /**< \brief (BSCIF_BGCTRL) ADC Input Selection */\r
+#define BSCIF_BGCTRL_ADCISEL(value) ((BSCIF_BGCTRL_ADCISEL_Msk & ((value) << BSCIF_BGCTRL_ADCISEL_Pos)))\r
+#define BSCIF_BGCTRL_ADCISEL_DIS (0x0u << 0) /**< \brief (BSCIF_BGCTRL) */\r
+#define BSCIF_BGCTRL_ADCISEL_VTEMP (0x1u << 0) /**< \brief (BSCIF_BGCTRL) */\r
+#define BSCIF_BGCTRL_ADCISEL_VREF (0x2u << 0) /**< \brief (BSCIF_BGCTRL) */\r
+#define BSCIF_BGCTRL_TSEN (0x1u << 8) /**< \brief (BSCIF_BGCTRL) Temperature Sensor Enable */\r
+/* -------- BSCIF_BGSR : (BSCIF Offset: 0x064) Bandgap Status Register -------- */\r
+#define BSCIF_BGSR_BGBUFRDY_Pos 0\r
+#define BSCIF_BGSR_BGBUFRDY_Msk (0xFFu << BSCIF_BGSR_BGBUFRDY_Pos) /**< \brief (BSCIF_BGSR) Bandgap Buffer Ready */\r
+#define BSCIF_BGSR_BGBUFRDY(value) ((BSCIF_BGSR_BGBUFRDY_Msk & ((value) << BSCIF_BGSR_BGBUFRDY_Pos)))\r
+#define BSCIF_BGSR_BGBUFRDY_FLASH (0x1u << 0) /**< \brief (BSCIF_BGSR) */\r
+#define BSCIF_BGSR_BGBUFRDY_PLL (0x2u << 0) /**< \brief (BSCIF_BGSR) */\r
+#define BSCIF_BGSR_BGBUFRDY_VREG (0x4u << 0) /**< \brief (BSCIF_BGSR) */\r
+#define BSCIF_BGSR_BGBUFRDY_BUFRR (0x8u << 0) /**< \brief (BSCIF_BGSR) */\r
+#define BSCIF_BGSR_BGBUFRDY_ADC (0x10u << 0) /**< \brief (BSCIF_BGSR) */\r
+#define BSCIF_BGSR_BGBUFRDY_LCD (0x20u << 0) /**< \brief (BSCIF_BGSR) */\r
+#define BSCIF_BGSR_BGRDY (0x1u << 16) /**< \brief (BSCIF_BGSR) Bandgap Voltage Reference Ready */\r
+#define BSCIF_BGSR_LPBGRDY (0x1u << 17) /**< \brief (BSCIF_BGSR) Low Power Bandgap Voltage Reference Ready */\r
+#define BSCIF_BGSR_VREF_Pos 18\r
+#define BSCIF_BGSR_VREF_Msk (0x3u << BSCIF_BGSR_VREF_Pos) /**< \brief (BSCIF_BGSR) Voltage Reference Used by the System */\r
+#define BSCIF_BGSR_VREF(value) ((BSCIF_BGSR_VREF_Msk & ((value) << BSCIF_BGSR_VREF_Pos)))\r
+/* -------- BSCIF_BRIFBVERSION : (BSCIF Offset: 0x3E4) Backup Register Interface Version Register -------- */\r
+#define BSCIF_BRIFBVERSION_VERSION_Pos 0\r
+#define BSCIF_BRIFBVERSION_VERSION_Msk (0xFFFu << BSCIF_BRIFBVERSION_VERSION_Pos) /**< \brief (BSCIF_BRIFBVERSION) Version Number */\r
+#define BSCIF_BRIFBVERSION_VERSION(value) ((BSCIF_BRIFBVERSION_VERSION_Msk & ((value) << BSCIF_BRIFBVERSION_VERSION_Pos)))\r
+#define BSCIF_BRIFBVERSION_VARIANT_Pos 16\r
+#define BSCIF_BRIFBVERSION_VARIANT_Msk (0xFu << BSCIF_BRIFBVERSION_VARIANT_Pos) /**< \brief (BSCIF_BRIFBVERSION) Variant Number */\r
+#define BSCIF_BRIFBVERSION_VARIANT(value) ((BSCIF_BRIFBVERSION_VARIANT_Msk & ((value) << BSCIF_BRIFBVERSION_VARIANT_Pos)))\r
+/* -------- BSCIF_BGREFIFBVERSION : (BSCIF Offset: 0x3E8) BGREFIFB Version Register -------- */\r
+#define BSCIF_BGREFIFBVERSION_VERSION_Pos 0\r
+#define BSCIF_BGREFIFBVERSION_VERSION_Msk (0xFFFu << BSCIF_BGREFIFBVERSION_VERSION_Pos) /**< \brief (BSCIF_BGREFIFBVERSION) Version Number */\r
+#define BSCIF_BGREFIFBVERSION_VERSION(value) ((BSCIF_BGREFIFBVERSION_VERSION_Msk & ((value) << BSCIF_BGREFIFBVERSION_VERSION_Pos)))\r
+#define BSCIF_BGREFIFBVERSION_VARIANT_Pos 16\r
+#define BSCIF_BGREFIFBVERSION_VARIANT_Msk (0xFu << BSCIF_BGREFIFBVERSION_VARIANT_Pos) /**< \brief (BSCIF_BGREFIFBVERSION) Variant Number */\r
+#define BSCIF_BGREFIFBVERSION_VARIANT(value) ((BSCIF_BGREFIFBVERSION_VARIANT_Msk & ((value) << BSCIF_BGREFIFBVERSION_VARIANT_Pos)))\r
+/* -------- BSCIF_VREGIFGVERSION : (BSCIF Offset: 0x3EC) VREGIFA Version Register -------- */\r
+#define BSCIF_VREGIFGVERSION_VERSION_Pos 0\r
+#define BSCIF_VREGIFGVERSION_VERSION_Msk (0xFFFu << BSCIF_VREGIFGVERSION_VERSION_Pos) /**< \brief (BSCIF_VREGIFGVERSION) Version Number */\r
+#define BSCIF_VREGIFGVERSION_VERSION(value) ((BSCIF_VREGIFGVERSION_VERSION_Msk & ((value) << BSCIF_VREGIFGVERSION_VERSION_Pos)))\r
+#define BSCIF_VREGIFGVERSION_VARIANT_Pos 16\r
+#define BSCIF_VREGIFGVERSION_VARIANT_Msk (0xFu << BSCIF_VREGIFGVERSION_VARIANT_Pos) /**< \brief (BSCIF_VREGIFGVERSION) Variant Number */\r
+#define BSCIF_VREGIFGVERSION_VARIANT(value) ((BSCIF_VREGIFGVERSION_VARIANT_Msk & ((value) << BSCIF_VREGIFGVERSION_VARIANT_Pos)))\r
+/* -------- BSCIF_BODIFCVERSION : (BSCIF Offset: 0x3F0) BODIFC Version Register -------- */\r
+#define BSCIF_BODIFCVERSION_VERSION_Pos 0\r
+#define BSCIF_BODIFCVERSION_VERSION_Msk (0xFFFu << BSCIF_BODIFCVERSION_VERSION_Pos) /**< \brief (BSCIF_BODIFCVERSION) Version Number */\r
+#define BSCIF_BODIFCVERSION_VERSION(value) ((BSCIF_BODIFCVERSION_VERSION_Msk & ((value) << BSCIF_BODIFCVERSION_VERSION_Pos)))\r
+#define BSCIF_BODIFCVERSION_VARIANT_Pos 16\r
+#define BSCIF_BODIFCVERSION_VARIANT_Msk (0xFu << BSCIF_BODIFCVERSION_VARIANT_Pos) /**< \brief (BSCIF_BODIFCVERSION) Variant Number */\r
+#define BSCIF_BODIFCVERSION_VARIANT(value) ((BSCIF_BODIFCVERSION_VARIANT_Msk & ((value) << BSCIF_BODIFCVERSION_VARIANT_Pos)))\r
+/* -------- BSCIF_RC32KIFBVERSION : (BSCIF Offset: 0x3F4) 32 kHz RC Oscillator Version Register -------- */\r
+#define BSCIF_RC32KIFBVERSION_VERSION_Pos 0\r
+#define BSCIF_RC32KIFBVERSION_VERSION_Msk (0xFFFu << BSCIF_RC32KIFBVERSION_VERSION_Pos) /**< \brief (BSCIF_RC32KIFBVERSION) Version number */\r
+#define BSCIF_RC32KIFBVERSION_VERSION(value) ((BSCIF_RC32KIFBVERSION_VERSION_Msk & ((value) << BSCIF_RC32KIFBVERSION_VERSION_Pos)))\r
+#define BSCIF_RC32KIFBVERSION_VARIANT_Pos 16\r
+#define BSCIF_RC32KIFBVERSION_VARIANT_Msk (0xFu << BSCIF_RC32KIFBVERSION_VARIANT_Pos) /**< \brief (BSCIF_RC32KIFBVERSION) Variant number */\r
+#define BSCIF_RC32KIFBVERSION_VARIANT(value) ((BSCIF_RC32KIFBVERSION_VARIANT_Msk & ((value) << BSCIF_RC32KIFBVERSION_VARIANT_Pos)))\r
+/* -------- BSCIF_OSC32IFAVERSION : (BSCIF Offset: 0x3F8) 32 KHz Oscillator Version Register -------- */\r
+#define BSCIF_OSC32IFAVERSION_VERSION_Pos 0\r
+#define BSCIF_OSC32IFAVERSION_VERSION_Msk (0xFFFu << BSCIF_OSC32IFAVERSION_VERSION_Pos) /**< \brief (BSCIF_OSC32IFAVERSION) Version number */\r
+#define BSCIF_OSC32IFAVERSION_VERSION(value) ((BSCIF_OSC32IFAVERSION_VERSION_Msk & ((value) << BSCIF_OSC32IFAVERSION_VERSION_Pos)))\r
+#define BSCIF_OSC32IFAVERSION_VARIANT_Pos 16\r
+#define BSCIF_OSC32IFAVERSION_VARIANT_Msk (0xFu << BSCIF_OSC32IFAVERSION_VARIANT_Pos) /**< \brief (BSCIF_OSC32IFAVERSION) Variant nubmer */\r
+#define BSCIF_OSC32IFAVERSION_VARIANT(value) ((BSCIF_OSC32IFAVERSION_VARIANT_Msk & ((value) << BSCIF_OSC32IFAVERSION_VARIANT_Pos)))\r
+/* -------- BSCIF_VERSION : (BSCIF Offset: 0x3FC) BSCIF Version Register -------- */\r
+#define BSCIF_VERSION_VERSION_Pos 0\r
+#define BSCIF_VERSION_VERSION_Msk (0xFFFu << BSCIF_VERSION_VERSION_Pos) /**< \brief (BSCIF_VERSION) Version Number */\r
+#define BSCIF_VERSION_VERSION(value) ((BSCIF_VERSION_VERSION_Msk & ((value) << BSCIF_VERSION_VERSION_Pos)))\r
+#define BSCIF_VERSION_VARIANT_Pos 16\r
+#define BSCIF_VERSION_VARIANT_Msk (0xFu << BSCIF_VERSION_VARIANT_Pos) /**< \brief (BSCIF_VERSION) Variant Number */\r
+#define BSCIF_VERSION_VARIANT(value) ((BSCIF_VERSION_VARIANT_Msk & ((value) << BSCIF_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR CATB */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_CATB Capacitive Touch Module B */\r
+/*@{*/\r
+\r
+#define REV_CATB 0x100\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief CatbIntch hardware registers */\r
+typedef struct {\r
+ RoReg CATB_INTCH; /**< \brief (CatbIntch Offset: 0x00) In-Touch Status Register 0 */\r
+} CatbIntch;\r
+/** \brief CatbIntchclr hardware registers */\r
+typedef struct {\r
+ WoReg CATB_INTCHCLR; /**< \brief (CatbIntchclr Offset: 0x00) In-Touch Status Clear Register 0 */\r
+} CatbIntchclr;\r
+/** \brief CatbOuttch hardware registers */\r
+typedef struct {\r
+ RoReg CATB_OUTTCH; /**< \brief (CatbOuttch Offset: 0x00) Out-of-Touch Status Register 0 */\r
+} CatbOuttch;\r
+/** \brief CatbOuttchclr hardware registers */\r
+typedef struct {\r
+ WoReg CATB_OUTTCHCLR; /**< \brief (CatbOuttchclr Offset: 0x00) Out-of-Touch Status Clear Register 0 */\r
+} CatbOuttchclr;\r
+/** \brief CATB hardware registers */\r
+#define CATB_STATUS_REG_NUMBER 1\r
+typedef struct {\r
+ RwReg CATB_CR; /**< \brief (CATB Offset: 0x00) Control Register */\r
+ RwReg CATB_CNTCR; /**< \brief (CATB Offset: 0x04) Counter Control Register */\r
+ RwReg CATB_IDLE; /**< \brief (CATB Offset: 0x08) Sensor Idle Level */\r
+ RoReg CATB_LEVEL; /**< \brief (CATB Offset: 0x0C) Sensor Relative Level */\r
+ RoReg CATB_RAW; /**< \brief (CATB Offset: 0x10) Sensor Raw Value */\r
+ RwReg CATB_TIMING; /**< \brief (CATB Offset: 0x14) Filter Timing Register */\r
+ RwReg CATB_THRESH; /**< \brief (CATB Offset: 0x18) Threshold Register */\r
+ RwReg CATB_PINSEL; /**< \brief (CATB Offset: 0x1C) Pin Selection Register */\r
+ RwReg CATB_DMA; /**< \brief (CATB Offset: 0x20) Direct Memory Access Register */\r
+ RoReg CATB_ISR; /**< \brief (CATB Offset: 0x24) Interrupt Status Register */\r
+ WoReg CATB_IER; /**< \brief (CATB Offset: 0x28) Interrupt Enable Register */\r
+ WoReg CATB_IDR; /**< \brief (CATB Offset: 0x2C) Interrupt Disable Register */\r
+ RoReg CATB_IMR; /**< \brief (CATB Offset: 0x30) Interrupt Mask Register */\r
+ WoReg CATB_SCR; /**< \brief (CATB Offset: 0x34) Status Clear Register */\r
+ RoReg Reserved1[2];\r
+ CatbIntch CATB_INTCH[CATB_STATUS_REG_NUMBER]; /**< \brief (CATB Offset: 0x40) CatbIntch groups */\r
+ CatbIntch Reserved2[4 - CATB_STATUS_REG_NUMBER];\r
+ CatbIntchclr CATB_INTCHCLR[CATB_STATUS_REG_NUMBER]; /**< \brief (CATB Offset: 0x50) CatbIntchclr groups */\r
+ CatbIntchclr Reserved3[4 - CATB_STATUS_REG_NUMBER];\r
+ CatbOuttch CATB_OUTTCH[CATB_STATUS_REG_NUMBER]; /**< \brief (CATB Offset: 0x60) CatbOuttch groups */\r
+ CatbOuttch Reserved4[4 - CATB_STATUS_REG_NUMBER];\r
+ CatbOuttchclr CATB_OUTTCHCLR[CATB_STATUS_REG_NUMBER]; /**< \brief (CATB Offset: 0x70) CatbOuttchclr groups */\r
+ CatbOuttchclr Reserved5[4 - CATB_STATUS_REG_NUMBER];\r
+ RoReg Reserved6[30];\r
+ RoReg CATB_PARAMETER; /**< \brief (CATB Offset: 0xF8) Parameter Register */\r
+ RoReg CATB_VERSION; /**< \brief (CATB Offset: 0xFC) Version Register */\r
+} Catb;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- CATB_CR : (CATB Offset: 0x00) Control Register -------- */\r
+#define CATB_CR_EN (0x1u << 0) /**< \brief (CATB_CR) Module Enable */\r
+#define CATB_CR_RUN (0x1u << 1) /**< \brief (CATB_CR) Start Operation */\r
+#define CATB_CR_IIDLE (0x1u << 2) /**< \brief (CATB_CR) Initialize Idle Value */\r
+#define CATB_CR_ETRIG (0x1u << 3) /**< \brief (CATB_CR) Event Triggered Operation */\r
+#define CATB_CR_INTRES (0x1u << 4) /**< \brief (CATB_CR) Internal Resistors */\r
+#define CATB_CR_CKSEL (0x1u << 5) /**< \brief (CATB_CR) Clock Select */\r
+#define CATB_CR_DIFF (0x1u << 6) /**< \brief (CATB_CR) Differential Mode */\r
+#define CATB_CR_DMAEN (0x1u << 7) /**< \brief (CATB_CR) DMA Enable */\r
+#define CATB_CR_ESAMPLES_Pos 8\r
+#define CATB_CR_ESAMPLES_Msk (0x7Fu << CATB_CR_ESAMPLES_Pos) /**< \brief (CATB_CR) Number of Event Samples */\r
+#define CATB_CR_ESAMPLES(value) ((CATB_CR_ESAMPLES_Msk & ((value) << CATB_CR_ESAMPLES_Pos)))\r
+#define CATB_CR_CHARGET_Pos 16\r
+#define CATB_CR_CHARGET_Msk (0xFu << CATB_CR_CHARGET_Pos) /**< \brief (CATB_CR) Charge Time */\r
+#define CATB_CR_CHARGET(value) ((CATB_CR_CHARGET_Msk & ((value) << CATB_CR_CHARGET_Pos)))\r
+#define CATB_CR_SWRST (0x1u << 31) /**< \brief (CATB_CR) Software Reset */\r
+/* -------- CATB_CNTCR : (CATB Offset: 0x04) Counter Control Register -------- */\r
+#define CATB_CNTCR_TOP_Pos 0\r
+#define CATB_CNTCR_TOP_Msk (0xFFFFFFu << CATB_CNTCR_TOP_Pos) /**< \brief (CATB_CNTCR) Counter Top Value */\r
+#define CATB_CNTCR_TOP(value) ((CATB_CNTCR_TOP_Msk & ((value) << CATB_CNTCR_TOP_Pos)))\r
+#define CATB_CNTCR_SPREAD_Pos 24\r
+#define CATB_CNTCR_SPREAD_Msk (0xFu << CATB_CNTCR_SPREAD_Pos) /**< \brief (CATB_CNTCR) Spread Spectrum */\r
+#define CATB_CNTCR_SPREAD(value) ((CATB_CNTCR_SPREAD_Msk & ((value) << CATB_CNTCR_SPREAD_Pos)))\r
+#define CATB_CNTCR_REPEAT_Pos 28\r
+#define CATB_CNTCR_REPEAT_Msk (0x7u << CATB_CNTCR_REPEAT_Pos) /**< \brief (CATB_CNTCR) Repeat Measurements */\r
+#define CATB_CNTCR_REPEAT(value) ((CATB_CNTCR_REPEAT_Msk & ((value) << CATB_CNTCR_REPEAT_Pos)))\r
+/* -------- CATB_IDLE : (CATB Offset: 0x08) Sensor Idle Level -------- */\r
+#define CATB_IDLE_FIDLE_Pos 0\r
+#define CATB_IDLE_FIDLE_Msk (0xFFFu << CATB_IDLE_FIDLE_Pos) /**< \brief (CATB_IDLE) Fractional Sensor Idle */\r
+#define CATB_IDLE_FIDLE(value) ((CATB_IDLE_FIDLE_Msk & ((value) << CATB_IDLE_FIDLE_Pos)))\r
+#define CATB_IDLE_RIDLE_Pos 12\r
+#define CATB_IDLE_RIDLE_Msk (0xFFFFu << CATB_IDLE_RIDLE_Pos) /**< \brief (CATB_IDLE) Integer Sensor Idle */\r
+#define CATB_IDLE_RIDLE(value) ((CATB_IDLE_RIDLE_Msk & ((value) << CATB_IDLE_RIDLE_Pos)))\r
+/* -------- CATB_LEVEL : (CATB Offset: 0x0C) Sensor Relative Level -------- */\r
+#define CATB_LEVEL_FLEVEL_Pos 0\r
+#define CATB_LEVEL_FLEVEL_Msk (0xFFFu << CATB_LEVEL_FLEVEL_Pos) /**< \brief (CATB_LEVEL) Fractional Sensor Level */\r
+#define CATB_LEVEL_FLEVEL(value) ((CATB_LEVEL_FLEVEL_Msk & ((value) << CATB_LEVEL_FLEVEL_Pos)))\r
+#define CATB_LEVEL_RLEVEL_Pos 12\r
+#define CATB_LEVEL_RLEVEL_Msk (0xFFu << CATB_LEVEL_RLEVEL_Pos) /**< \brief (CATB_LEVEL) Integer Sensor Level */\r
+#define CATB_LEVEL_RLEVEL(value) ((CATB_LEVEL_RLEVEL_Msk & ((value) << CATB_LEVEL_RLEVEL_Pos)))\r
+/* -------- CATB_RAW : (CATB Offset: 0x10) Sensor Raw Value -------- */\r
+#define CATB_RAW_RAWA_Pos 16\r
+#define CATB_RAW_RAWA_Msk (0xFFu << CATB_RAW_RAWA_Pos) /**< \brief (CATB_RAW) Current Sensor Raw Value */\r
+#define CATB_RAW_RAWA(value) ((CATB_RAW_RAWA_Msk & ((value) << CATB_RAW_RAWA_Pos)))\r
+#define CATB_RAW_RAWB_Pos 24\r
+#define CATB_RAW_RAWB_Msk (0xFFu << CATB_RAW_RAWB_Pos) /**< \brief (CATB_RAW) Last Sensor Raw Value */\r
+#define CATB_RAW_RAWB(value) ((CATB_RAW_RAWB_Msk & ((value) << CATB_RAW_RAWB_Pos)))\r
+/* -------- CATB_TIMING : (CATB Offset: 0x14) Filter Timing Register -------- */\r
+#define CATB_TIMING_TLEVEL_Pos 0\r
+#define CATB_TIMING_TLEVEL_Msk (0xFFFu << CATB_TIMING_TLEVEL_Pos) /**< \brief (CATB_TIMING) Relative Level Smoothing */\r
+#define CATB_TIMING_TLEVEL(value) ((CATB_TIMING_TLEVEL_Msk & ((value) << CATB_TIMING_TLEVEL_Pos)))\r
+#define CATB_TIMING_TIDLE_Pos 16\r
+#define CATB_TIMING_TIDLE_Msk (0xFFFu << CATB_TIMING_TIDLE_Pos) /**< \brief (CATB_TIMING) Idle Smoothening */\r
+#define CATB_TIMING_TIDLE(value) ((CATB_TIMING_TIDLE_Msk & ((value) << CATB_TIMING_TIDLE_Pos)))\r
+/* -------- CATB_THRESH : (CATB Offset: 0x18) Threshold Register -------- */\r
+#define CATB_THRESH_FTHRESH_Pos 0\r
+#define CATB_THRESH_FTHRESH_Msk (0xFFFu << CATB_THRESH_FTHRESH_Pos) /**< \brief (CATB_THRESH) Fractional part of Threshold Value */\r
+#define CATB_THRESH_FTHRESH(value) ((CATB_THRESH_FTHRESH_Msk & ((value) << CATB_THRESH_FTHRESH_Pos)))\r
+#define CATB_THRESH_RTHRESH_Pos 12\r
+#define CATB_THRESH_RTHRESH_Msk (0xFFu << CATB_THRESH_RTHRESH_Pos) /**< \brief (CATB_THRESH) Rational part of Threshold Value */\r
+#define CATB_THRESH_RTHRESH(value) ((CATB_THRESH_RTHRESH_Msk & ((value) << CATB_THRESH_RTHRESH_Pos)))\r
+#define CATB_THRESH_DIR (0x1u << 23) /**< \brief (CATB_THRESH) Threshold Direction */\r
+#define CATB_THRESH_LENGTH_Pos 24\r
+#define CATB_THRESH_LENGTH_Msk (0x1Fu << CATB_THRESH_LENGTH_Pos) /**< \brief (CATB_THRESH) Threshold Length */\r
+#define CATB_THRESH_LENGTH(value) ((CATB_THRESH_LENGTH_Msk & ((value) << CATB_THRESH_LENGTH_Pos)))\r
+/* -------- CATB_PINSEL : (CATB Offset: 0x1C) Pin Selection Register -------- */\r
+#define CATB_PINSEL_PINSEL_Pos 0\r
+#define CATB_PINSEL_PINSEL_Msk (0xFFu << CATB_PINSEL_PINSEL_Pos) /**< \brief (CATB_PINSEL) Pin Select */\r
+#define CATB_PINSEL_PINSEL(value) ((CATB_PINSEL_PINSEL_Msk & ((value) << CATB_PINSEL_PINSEL_Pos)))\r
+/* -------- CATB_DMA : (CATB Offset: 0x20) Direct Memory Access Register -------- */\r
+#define CATB_DMA_DMA_Pos 0\r
+#define CATB_DMA_DMA_Msk (0xFFFFFFFFu << CATB_DMA_DMA_Pos) /**< \brief (CATB_DMA) Direct Memory Access */\r
+#define CATB_DMA_DMA(value) ((CATB_DMA_DMA_Msk & ((value) << CATB_DMA_DMA_Pos)))\r
+/* -------- CATB_ISR : (CATB Offset: 0x24) Interrupt Status Register -------- */\r
+#define CATB_ISR_SAMPLE (0x1u << 0) /**< \brief (CATB_ISR) Sample Ready Interrupt Status */\r
+#define CATB_ISR_INTCH (0x1u << 1) /**< \brief (CATB_ISR) In-touch Interrupt Status */\r
+#define CATB_ISR_OUTTCH (0x1u << 2) /**< \brief (CATB_ISR) Out-of-Touch Interrupt Status */\r
+/* -------- CATB_IER : (CATB Offset: 0x28) Interrupt Enable Register -------- */\r
+#define CATB_IER_SAMPLE (0x1u << 0) /**< \brief (CATB_IER) Sample Ready Interrupt Enable */\r
+#define CATB_IER_INTCH (0x1u << 1) /**< \brief (CATB_IER) In-touch Interrupt Enable */\r
+#define CATB_IER_OUTTCH (0x1u << 2) /**< \brief (CATB_IER) Out-of-Touch Interrupt Enable */\r
+/* -------- CATB_IDR : (CATB Offset: 0x2C) Interrupt Disable Register -------- */\r
+#define CATB_IDR_SAMPLE (0x1u << 0) /**< \brief (CATB_IDR) Sample Ready Interrupt Disable */\r
+#define CATB_IDR_INTCH (0x1u << 1) /**< \brief (CATB_IDR) In-touch Interrupt Disable */\r
+#define CATB_IDR_OUTTCH (0x1u << 2) /**< \brief (CATB_IDR) Out-of-Touch Interrupt Disable */\r
+/* -------- CATB_IMR : (CATB Offset: 0x30) Interrupt Mask Register -------- */\r
+#define CATB_IMR_SAMPLE (0x1u << 0) /**< \brief (CATB_IMR) Sample Ready Interrupt Mask */\r
+#define CATB_IMR_INTCH (0x1u << 1) /**< \brief (CATB_IMR) In-touch Interrupt Mask */\r
+#define CATB_IMR_OUTTCH (0x1u << 2) /**< \brief (CATB_IMR) Out-of-Touch Interrupt Mask */\r
+/* -------- CATB_SCR : (CATB Offset: 0x34) Status Clear Register -------- */\r
+#define CATB_SCR_SAMPLE (0x1u << 0) /**< \brief (CATB_SCR) Sample Ready */\r
+#define CATB_SCR_INTCH (0x1u << 1) /**< \brief (CATB_SCR) In-touch */\r
+#define CATB_SCR_OUTTCH (0x1u << 2) /**< \brief (CATB_SCR) Out-of-Touch */\r
+/* -------- CATB_INTCH : (CATB Offset: 0x40) Intch In-Touch Status Register 0 -------- */\r
+#define CATB_INTCH_INTCH_Pos 0\r
+#define CATB_INTCH_INTCH_Msk (0xFFFFFFFFu << CATB_INTCH_INTCH_Pos) /**< \brief (CATB_INTCH) In-Touch */\r
+#define CATB_INTCH_INTCH(value) ((CATB_INTCH_INTCH_Msk & ((value) << CATB_INTCH_INTCH_Pos)))\r
+/* -------- CATB_INTCHCLR : (CATB Offset: 0x50) Intchclr In-Touch Status Clear Register 0 -------- */\r
+#define CATB_INTCHCLR_INTCHCLR_Pos 0\r
+#define CATB_INTCHCLR_INTCHCLR_Msk (0xFFFFFFFFu << CATB_INTCHCLR_INTCHCLR_Pos) /**< \brief (CATB_INTCHCLR) In-Touch Clear */\r
+#define CATB_INTCHCLR_INTCHCLR(value) ((CATB_INTCHCLR_INTCHCLR_Msk & ((value) << CATB_INTCHCLR_INTCHCLR_Pos)))\r
+/* -------- CATB_OUTTCH : (CATB Offset: 0x60) Outtch Out-of-Touch Status Register 0 -------- */\r
+#define CATB_OUTTCH_OUTTCH_Pos 0\r
+#define CATB_OUTTCH_OUTTCH_Msk (0xFFFFFFFFu << CATB_OUTTCH_OUTTCH_Pos) /**< \brief (CATB_OUTTCH) Out-of-Touch */\r
+#define CATB_OUTTCH_OUTTCH(value) ((CATB_OUTTCH_OUTTCH_Msk & ((value) << CATB_OUTTCH_OUTTCH_Pos)))\r
+/* -------- CATB_OUTTCHCLR : (CATB Offset: 0x70) Outtchclr Out-of-Touch Status Clear Register 0 -------- */\r
+#define CATB_OUTTCHCLR_OUTTCHCLR_Pos 0\r
+#define CATB_OUTTCHCLR_OUTTCHCLR_Msk (0xFFFFFFFFu << CATB_OUTTCHCLR_OUTTCHCLR_Pos) /**< \brief (CATB_OUTTCHCLR) Out of Touch */\r
+#define CATB_OUTTCHCLR_OUTTCHCLR(value) ((CATB_OUTTCHCLR_OUTTCHCLR_Msk & ((value) << CATB_OUTTCHCLR_OUTTCHCLR_Pos)))\r
+/* -------- CATB_PARAMETER : (CATB Offset: 0xF8) Parameter Register -------- */\r
+#define CATB_PARAMETER_NPINS_Pos 0\r
+#define CATB_PARAMETER_NPINS_Msk (0xFFu << CATB_PARAMETER_NPINS_Pos) /**< \brief (CATB_PARAMETER) Number of Pins */\r
+#define CATB_PARAMETER_NPINS(value) ((CATB_PARAMETER_NPINS_Msk & ((value) << CATB_PARAMETER_NPINS_Pos)))\r
+#define CATB_PARAMETER_NSTATUS_Pos 8\r
+#define CATB_PARAMETER_NSTATUS_Msk (0xFFu << CATB_PARAMETER_NSTATUS_Pos) /**< \brief (CATB_PARAMETER) Number of Status bits */\r
+#define CATB_PARAMETER_NSTATUS(value) ((CATB_PARAMETER_NSTATUS_Msk & ((value) << CATB_PARAMETER_NSTATUS_Pos)))\r
+#define CATB_PARAMETER_FRACTIONAL_Pos 16\r
+#define CATB_PARAMETER_FRACTIONAL_Msk (0xFu << CATB_PARAMETER_FRACTIONAL_Pos) /**< \brief (CATB_PARAMETER) Number of Fractional bits */\r
+#define CATB_PARAMETER_FRACTIONAL(value) ((CATB_PARAMETER_FRACTIONAL_Msk & ((value) << CATB_PARAMETER_FRACTIONAL_Pos)))\r
+/* -------- CATB_VERSION : (CATB Offset: 0xFC) Version Register -------- */\r
+#define CATB_VERSION_VERSION_Pos 0\r
+#define CATB_VERSION_VERSION_Msk (0xFFFu << CATB_VERSION_VERSION_Pos) /**< \brief (CATB_VERSION) Version number */\r
+#define CATB_VERSION_VERSION(value) ((CATB_VERSION_VERSION_Msk & ((value) << CATB_VERSION_VERSION_Pos)))\r
+#define CATB_VERSION_VARIANT_Pos 16\r
+#define CATB_VERSION_VARIANT_Msk (0xFu << CATB_VERSION_VARIANT_Pos) /**< \brief (CATB_VERSION) Variant number */\r
+#define CATB_VERSION_VARIANT(value) ((CATB_VERSION_VARIANT_Msk & ((value) << CATB_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR CHIPID */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_CHIPID Chip ID Registers */\r
+/*@{*/\r
+\r
+#define REV_CHIPID 0x100\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief CHIPID hardware registers */\r
+typedef struct {\r
+ RoReg Reserved1[208];\r
+ RoReg CHIPID_CIDR; /**< \brief (CHIPID Offset: 0x340) Chip ID Register */\r
+ RoReg CHIPID_EXID; /**< \brief (CHIPID Offset: 0x344) Chip ID Extension Register */\r
+} Chipid;\r
+#endif /* __ASSEMBLY__ */\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR CRCCU */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_CRCCU CRC Calculation Unit */\r
+/*@{*/\r
+\r
+#define REV_CRCCU 0x202\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief CRCCU hardware registers */\r
+typedef struct {\r
+ RwReg CRCCU_DSCR; /**< \brief (CRCCU Offset: 0x00) Descriptor Base Register */\r
+ RoReg Reserved1[1];\r
+ WoReg CRCCU_DMAEN; /**< \brief (CRCCU Offset: 0x08) DMA Enable Register */\r
+ WoReg CRCCU_DMADIS; /**< \brief (CRCCU Offset: 0x0C) DMA Disable Register */\r
+ RoReg CRCCU_DMASR; /**< \brief (CRCCU Offset: 0x10) DMA Status Register */\r
+ WoReg CRCCU_DMAIER; /**< \brief (CRCCU Offset: 0x14) DMA Interrupt Enable Register */\r
+ WoReg CRCCU_DMAIDR; /**< \brief (CRCCU Offset: 0x18) DMA Interrupt Disable Register */\r
+ RoReg CRCCU_DMAIMR; /**< \brief (CRCCU Offset: 0x1C) DMA Interrupt Mask Register */\r
+ RoReg CRCCU_DMAISR; /**< \brief (CRCCU Offset: 0x20) DMA Interrupt Status Register */\r
+ RoReg Reserved2[4];\r
+ WoReg CRCCU_CR; /**< \brief (CRCCU Offset: 0x34) Control Register */\r
+ RwReg CRCCU_MR; /**< \brief (CRCCU Offset: 0x38) Mode Register */\r
+ RoReg CRCCU_SR; /**< \brief (CRCCU Offset: 0x3C) Status Register */\r
+ WoReg CRCCU_IER; /**< \brief (CRCCU Offset: 0x40) Interrupt Enable Register */\r
+ WoReg CRCCU_IDR; /**< \brief (CRCCU Offset: 0x44) Interrupt Disable Register */\r
+ RoReg CRCCU_IMR; /**< \brief (CRCCU Offset: 0x48) Interrupt Mask Register */\r
+ RoReg CRCCU_ISR; /**< \brief (CRCCU Offset: 0x4C) Interrupt Status Register */\r
+ RoReg Reserved3[43];\r
+ RoReg CRCCU_VERSION; /**< \brief (CRCCU Offset: 0xFC) Version Register */\r
+} Crccu;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00) Descriptor Base Register -------- */\r
+#define CRCCU_DSCR_DSCR_Pos 9\r
+#define CRCCU_DSCR_DSCR_Msk (0x7FFFFFu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Description Base Address */\r
+#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos)))\r
+/* -------- CRCCU_DMAEN : (CRCCU Offset: 0x08) DMA Enable Register -------- */\r
+#define CRCCU_DMAEN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMAEN) DMA Enable */\r
+/* -------- CRCCU_DMADIS : (CRCCU Offset: 0x0C) DMA Disable Register -------- */\r
+#define CRCCU_DMADIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMADIS) DMA Disable */\r
+/* -------- CRCCU_DMASR : (CRCCU Offset: 0x10) DMA Status Register -------- */\r
+#define CRCCU_DMASR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMASR) DMA Channel Status */\r
+/* -------- CRCCU_DMAIER : (CRCCU Offset: 0x14) DMA Interrupt Enable Register -------- */\r
+#define CRCCU_DMAIER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMAIER) DMA Interrupt Enable */\r
+/* -------- CRCCU_DMAIDR : (CRCCU Offset: 0x18) DMA Interrupt Disable Register -------- */\r
+#define CRCCU_DMAIDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMAIDR) DMA Interrupt Disable */\r
+/* -------- CRCCU_DMAIMR : (CRCCU Offset: 0x1C) DMA Interrupt Mask Register -------- */\r
+#define CRCCU_DMAIMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMAIMR) DMA Interrupt Mask */\r
+/* -------- CRCCU_DMAISR : (CRCCU Offset: 0x20) DMA Interrupt Status Register -------- */\r
+#define CRCCU_DMAISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMAISR) DMA Interrupt Status */\r
+/* -------- CRCCU_CR : (CRCCU Offset: 0x34) Control Register -------- */\r
+#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) Reset CRCComputation */\r
+/* -------- CRCCU_MR : (CRCCU Offset: 0x38) Mode Register -------- */\r
+#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Computation Enable */\r
+#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */\r
+#define CRCCU_MR_PTYPE_Pos 2\r
+#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Polynomial Type */\r
+#define CRCCU_MR_PTYPE(value) ((CRCCU_MR_PTYPE_Msk & ((value) << CRCCU_MR_PTYPE_Pos)))\r
+#define CRCCU_MR_DIVIDER_Pos 4\r
+#define CRCCU_MR_DIVIDER_Msk (0xFu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Bandwidth Divider */\r
+#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))\r
+/* -------- CRCCU_SR : (CRCCU Offset: 0x3C) Status Register -------- */\r
+#define CRCCU_SR_CRC_Pos 0\r
+#define CRCCU_SR_CRC_Msk (0xFFFFFFFFu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */\r
+#define CRCCU_SR_CRC(value) ((CRCCU_SR_CRC_Msk & ((value) << CRCCU_SR_CRC_Pos)))\r
+/* -------- CRCCU_IER : (CRCCU Offset: 0x40) Interrupt Enable Register -------- */\r
+#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */\r
+/* -------- CRCCU_IDR : (CRCCU Offset: 0x44) Interrupt Disable Register -------- */\r
+#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */\r
+/* -------- CRCCU_IMR : (CRCCU Offset: 0x48) Interrupt Mask Register -------- */\r
+#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */\r
+/* -------- CRCCU_ISR : (CRCCU Offset: 0x4C) Interrupt Status Register -------- */\r
+#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */\r
+/* -------- CRCCU_VERSION : (CRCCU Offset: 0xFC) Version Register -------- */\r
+#define CRCCU_VERSION_VERSION_Pos 0\r
+#define CRCCU_VERSION_VERSION_Msk (0xFFFu << CRCCU_VERSION_VERSION_Pos) /**< \brief (CRCCU_VERSION) Version Number */\r
+#define CRCCU_VERSION_VERSION(value) ((CRCCU_VERSION_VERSION_Msk & ((value) << CRCCU_VERSION_VERSION_Pos)))\r
+#define CRCCU_VERSION_VARIANT_Pos 16\r
+#define CRCCU_VERSION_VARIANT_Msk (0xFu << CRCCU_VERSION_VARIANT_Pos) /**< \brief (CRCCU_VERSION) Variant Number */\r
+#define CRCCU_VERSION_VARIANT(value) ((CRCCU_VERSION_VARIANT_Msk & ((value) << CRCCU_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR DACC */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_DACC DAC Controller */\r
+/*@{*/\r
+\r
+#define REV_DACC 0x111\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief DACC hardware registers */\r
+typedef struct {\r
+ WoReg DACC_CR; /**< \brief (DACC Offset: 0x00) Control Register */\r
+ RwReg DACC_MR; /**< \brief (DACC Offset: 0x04) Mode Register */\r
+ WoReg DACC_CDR; /**< \brief (DACC Offset: 0x08) Conversion Data Register */\r
+ WoReg DACC_IER; /**< \brief (DACC Offset: 0x0C) Interrupt Enable Register */\r
+ WoReg DACC_IDR; /**< \brief (DACC Offset: 0x10) Interrupt Disable Register */\r
+ RoReg DACC_IMR; /**< \brief (DACC Offset: 0x14) Interrupt Mask Register */\r
+ RoReg DACC_ISR; /**< \brief (DACC Offset: 0x18) Interrupt Status Register */\r
+ RoReg Reserved1[50];\r
+ RwReg DACC_WPMR; /**< \brief (DACC Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg DACC_WPSR; /**< \brief (DACC Offset: 0xE8) Write Protect Status Register */\r
+ RoReg Reserved2[4];\r
+ RoReg DACC_VERSION; /**< \brief (DACC Offset: 0xFC) Version Register */\r
+} Dacc;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */\r
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */\r
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */\r
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */\r
+#define DACC_MR_TRGSEL_Pos 1\r
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */\r
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))\r
+#define DACC_MR_DACEN (0x1u << 4) /**< \brief (DACC_MR) DAC Enable */\r
+#define DACC_MR_WORD (0x1u << 5) /**< \brief (DACC_MR) Word Transfer */\r
+#define DACC_MR_STARTUP_Pos 8\r
+#define DACC_MR_STARTUP_Msk (0xFFu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */\r
+#define DACC_MR_STARTUP(value) ((DACC_MR_STARTUP_Msk & ((value) << DACC_MR_STARTUP_Pos)))\r
+#define DACC_MR_CLKDIV_Pos 16\r
+#define DACC_MR_CLKDIV_Msk (0xFFFFu << DACC_MR_CLKDIV_Pos) /**< \brief (DACC_MR) Clock Divider for Internal Trigger */\r
+#define DACC_MR_CLKDIV(value) ((DACC_MR_CLKDIV_Msk & ((value) << DACC_MR_CLKDIV_Pos)))\r
+/* -------- DACC_CDR : (DACC Offset: 0x08) Conversion Data Register -------- */\r
+#define DACC_CDR_DATA_Pos 0\r
+#define DACC_CDR_DATA_Msk (0xFFFFFFFFu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */\r
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))\r
+/* -------- DACC_IER : (DACC Offset: 0x0C) Interrupt Enable Register -------- */\r
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */\r
+/* -------- DACC_IDR : (DACC Offset: 0x10) Interrupt Disable Register -------- */\r
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable */\r
+/* -------- DACC_IMR : (DACC Offset: 0x14) Interrupt Mask Register -------- */\r
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */\r
+/* -------- DACC_ISR : (DACC Offset: 0x18) Interrupt Status Register -------- */\r
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Status */\r
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */\r
+#define DACC_WPMR_WPKEY_Pos 8\r
+#define DACC_WPMR_WPKEY_Msk (0xFFFFFFu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */\r
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))\r
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status Register -------- */\r
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Error */\r
+#define DACC_WPSR_WPROTADDR_Pos 8\r
+#define DACC_WPSR_WPROTADDR_Msk (0xFFu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write Protection Error Address */\r
+#define DACC_WPSR_WPROTADDR(value) ((DACC_WPSR_WPROTADDR_Msk & ((value) << DACC_WPSR_WPROTADDR_Pos)))\r
+/* -------- DACC_VERSION : (DACC Offset: 0xFC) Version Register -------- */\r
+#define DACC_VERSION_VERSION_Pos 0\r
+#define DACC_VERSION_VERSION_Msk (0xFFFu << DACC_VERSION_VERSION_Pos) /**< \brief (DACC_VERSION) Version Number */\r
+#define DACC_VERSION_VERSION(value) ((DACC_VERSION_VERSION_Msk & ((value) << DACC_VERSION_VERSION_Pos)))\r
+#define DACC_VERSION_VARIANT_Pos 16\r
+#define DACC_VERSION_VARIANT_Msk (0x7u << DACC_VERSION_VARIANT_Pos) /**< \brief (DACC_VERSION) Variant Number */\r
+#define DACC_VERSION_VARIANT(value) ((DACC_VERSION_VARIANT_Msk & ((value) << DACC_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR EIC */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_EIC External Interrupt Controller */\r
+/*@{*/\r
+\r
+#define REV_EIC 0x302\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief EIC hardware registers */\r
+typedef struct {\r
+ WoReg EIC_IER; /**< \brief (EIC Offset: 0x000) Interrupt Enable Register */\r
+ WoReg EIC_IDR; /**< \brief (EIC Offset: 0x004) Interrupt Disable Register */\r
+ RoReg EIC_IMR; /**< \brief (EIC Offset: 0x008) Interrupt Mask Register */\r
+ RoReg EIC_ISR; /**< \brief (EIC Offset: 0x00C) Interrupt Status Register */\r
+ WoReg EIC_ICR; /**< \brief (EIC Offset: 0x010) Interrupt Clear Register */\r
+ RwReg EIC_MODE; /**< \brief (EIC Offset: 0x014) Mode Register */\r
+ RwReg EIC_EDGE; /**< \brief (EIC Offset: 0x018) Edge Register */\r
+ RwReg EIC_LEVEL; /**< \brief (EIC Offset: 0x01C) Level Register */\r
+ RwReg EIC_FILTER; /**< \brief (EIC Offset: 0x020) Filter Register */\r
+ RoReg Reserved1[1];\r
+ RwReg EIC_ASYNC; /**< \brief (EIC Offset: 0x028) Asynchronous Register */\r
+ RoReg Reserved2[1];\r
+ WoReg EIC_EN; /**< \brief (EIC Offset: 0x030) Enable Register */\r
+ WoReg EIC_DIS; /**< \brief (EIC Offset: 0x034) Disable Register */\r
+ RoReg EIC_CTRL; /**< \brief (EIC Offset: 0x038) Control Register */\r
+ RoReg Reserved3[240];\r
+ RoReg EIC_VERSION; /**< \brief (EIC Offset: 0x3FC) Version Register */\r
+} Eic;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- EIC_IER : (EIC Offset: 0x000) Interrupt Enable Register -------- */\r
+#define EIC_IER_NMI (0x1u << 0) /**< \brief (EIC_IER) External Non Maskable CPU interrupt */\r
+#define EIC_IER_INT1 (0x1u << 1) /**< \brief (EIC_IER) External Interrupt 1 */\r
+#define EIC_IER_INT1_0 (0x0u << 1) /**< \brief (EIC_IER) No effect */\r
+#define EIC_IER_INT1_1 (0x1u << 1) /**< \brief (EIC_IER) Enable Interrupt. */\r
+#define EIC_IER_INT2 (0x1u << 2) /**< \brief (EIC_IER) External Interrupt 2 */\r
+#define EIC_IER_INT2_0 (0x0u << 2) /**< \brief (EIC_IER) No effect */\r
+#define EIC_IER_INT2_1 (0x1u << 2) /**< \brief (EIC_IER) Enable Interrupt. */\r
+#define EIC_IER_INT3 (0x1u << 3) /**< \brief (EIC_IER) External Interrupt 3 */\r
+#define EIC_IER_INT3_0 (0x0u << 3) /**< \brief (EIC_IER) No effect */\r
+#define EIC_IER_INT3_1 (0x1u << 3) /**< \brief (EIC_IER) Enable Interrupt. */\r
+#define EIC_IER_INT4 (0x1u << 4) /**< \brief (EIC_IER) External Interrupt 4 */\r
+#define EIC_IER_INT4_0 (0x0u << 4) /**< \brief (EIC_IER) No effect */\r
+#define EIC_IER_INT4_1 (0x1u << 4) /**< \brief (EIC_IER) Enable Interrupt. */\r
+#define EIC_IER_INT5 (0x1u << 5) /**< \brief (EIC_IER) External Interrupt 5 */\r
+#define EIC_IER_INT6 (0x1u << 6) /**< \brief (EIC_IER) External Interrupt 6 */\r
+#define EIC_IER_INT7 (0x1u << 7) /**< \brief (EIC_IER) External Interrupt 7 */\r
+#define EIC_IER_INT8 (0x1u << 8) /**< \brief (EIC_IER) External Interrupt 8 */\r
+#define EIC_IER_INT9 (0x1u << 9) /**< \brief (EIC_IER) External Interrupt 9 */\r
+#define EIC_IER_INT10 (0x1u << 10) /**< \brief (EIC_IER) External Interrupt 10 */\r
+#define EIC_IER_INT11 (0x1u << 11) /**< \brief (EIC_IER) External Interrupt 11 */\r
+#define EIC_IER_INT12 (0x1u << 12) /**< \brief (EIC_IER) External Interrupt 12 */\r
+#define EIC_IER_INT13 (0x1u << 13) /**< \brief (EIC_IER) External Interrupt 13 */\r
+#define EIC_IER_INT14 (0x1u << 14) /**< \brief (EIC_IER) External Interrupt 14 */\r
+#define EIC_IER_INT15 (0x1u << 15) /**< \brief (EIC_IER) External Interrupt 15 */\r
+/* -------- EIC_IDR : (EIC Offset: 0x004) Interrupt Disable Register -------- */\r
+#define EIC_IDR_NMI (0x1u << 0) /**< \brief (EIC_IDR) External Non Maskable CPU interrupt */\r
+#define EIC_IDR_INT1 (0x1u << 1) /**< \brief (EIC_IDR) External Interrupt 1 */\r
+#define EIC_IDR_INT1_0 (0x0u << 1) /**< \brief (EIC_IDR) No effect */\r
+#define EIC_IDR_INT1_1 (0x1u << 1) /**< \brief (EIC_IDR) Disable Interrupt. */\r
+#define EIC_IDR_INT2 (0x1u << 2) /**< \brief (EIC_IDR) External Interrupt 2 */\r
+#define EIC_IDR_INT2_0 (0x0u << 2) /**< \brief (EIC_IDR) No effect */\r
+#define EIC_IDR_INT2_1 (0x1u << 2) /**< \brief (EIC_IDR) Disable Interrupt. */\r
+#define EIC_IDR_INT3 (0x1u << 3) /**< \brief (EIC_IDR) External Interrupt 3 */\r
+#define EIC_IDR_INT3_0 (0x0u << 3) /**< \brief (EIC_IDR) No effect */\r
+#define EIC_IDR_INT3_1 (0x1u << 3) /**< \brief (EIC_IDR) Disable Interrupt. */\r
+#define EIC_IDR_INT4 (0x1u << 4) /**< \brief (EIC_IDR) External Interrupt 4 */\r
+#define EIC_IDR_INT4_0 (0x0u << 4) /**< \brief (EIC_IDR) No effect */\r
+#define EIC_IDR_INT4_1 (0x1u << 4) /**< \brief (EIC_IDR) Disable Interrupt. */\r
+#define EIC_IDR_INT5 (0x1u << 5) /**< \brief (EIC_IDR) External Interrupt 5 */\r
+#define EIC_IDR_INT6 (0x1u << 6) /**< \brief (EIC_IDR) External Interrupt 6 */\r
+#define EIC_IDR_INT7 (0x1u << 7) /**< \brief (EIC_IDR) External Interrupt 7 */\r
+#define EIC_IDR_INT8 (0x1u << 8) /**< \brief (EIC_IDR) External Interrupt 8 */\r
+#define EIC_IDR_INT9 (0x1u << 9) /**< \brief (EIC_IDR) External Interrupt 9 */\r
+#define EIC_IDR_INT10 (0x1u << 10) /**< \brief (EIC_IDR) External Interrupt 10 */\r
+#define EIC_IDR_INT11 (0x1u << 11) /**< \brief (EIC_IDR) External Interrupt 11 */\r
+#define EIC_IDR_INT12 (0x1u << 12) /**< \brief (EIC_IDR) External Interrupt 12 */\r
+#define EIC_IDR_INT13 (0x1u << 13) /**< \brief (EIC_IDR) External Interrupt 13 */\r
+#define EIC_IDR_INT14 (0x1u << 14) /**< \brief (EIC_IDR) External Interrupt 14 */\r
+#define EIC_IDR_INT15 (0x1u << 15) /**< \brief (EIC_IDR) External Interrupt 15 */\r
+/* -------- EIC_IMR : (EIC Offset: 0x008) Interrupt Mask Register -------- */\r
+#define EIC_IMR_NMI (0x1u << 0) /**< \brief (EIC_IMR) External Non Maskable CPU interrupt */\r
+#define EIC_IMR_INT1 (0x1u << 1) /**< \brief (EIC_IMR) External Interrupt 1 */\r
+#define EIC_IMR_INT1_0 (0x0u << 1) /**< \brief (EIC_IMR) Interrupt is disabled */\r
+#define EIC_IMR_INT1_1 (0x1u << 1) /**< \brief (EIC_IMR) Interrupt is enabled. */\r
+#define EIC_IMR_INT2 (0x1u << 2) /**< \brief (EIC_IMR) External Interrupt 2 */\r
+#define EIC_IMR_INT2_0 (0x0u << 2) /**< \brief (EIC_IMR) Interrupt is disabled */\r
+#define EIC_IMR_INT2_1 (0x1u << 2) /**< \brief (EIC_IMR) Interrupt is enabled. */\r
+#define EIC_IMR_INT3 (0x1u << 3) /**< \brief (EIC_IMR) External Interrupt 3 */\r
+#define EIC_IMR_INT3_0 (0x0u << 3) /**< \brief (EIC_IMR) Interrupt is disabled */\r
+#define EIC_IMR_INT3_1 (0x1u << 3) /**< \brief (EIC_IMR) Interrupt is enabled. */\r
+#define EIC_IMR_INT4 (0x1u << 4) /**< \brief (EIC_IMR) External Interrupt 4 */\r
+#define EIC_IMR_INT4_0 (0x0u << 4) /**< \brief (EIC_IMR) Interrupt is disabled */\r
+#define EIC_IMR_INT4_1 (0x1u << 4) /**< \brief (EIC_IMR) Interrupt is enabled. */\r
+#define EIC_IMR_INT5 (0x1u << 5) /**< \brief (EIC_IMR) External Interrupt 5 */\r
+#define EIC_IMR_INT6 (0x1u << 6) /**< \brief (EIC_IMR) External Interrupt 6 */\r
+#define EIC_IMR_INT7 (0x1u << 7) /**< \brief (EIC_IMR) External Interrupt 7 */\r
+#define EIC_IMR_INT8 (0x1u << 8) /**< \brief (EIC_IMR) External Interrupt 8 */\r
+#define EIC_IMR_INT9 (0x1u << 9) /**< \brief (EIC_IMR) External Interrupt 9 */\r
+#define EIC_IMR_INT10 (0x1u << 10) /**< \brief (EIC_IMR) External Interrupt 10 */\r
+#define EIC_IMR_INT11 (0x1u << 11) /**< \brief (EIC_IMR) External Interrupt 11 */\r
+#define EIC_IMR_INT12 (0x1u << 12) /**< \brief (EIC_IMR) External Interrupt 12 */\r
+#define EIC_IMR_INT13 (0x1u << 13) /**< \brief (EIC_IMR) External Interrupt 13 */\r
+#define EIC_IMR_INT14 (0x1u << 14) /**< \brief (EIC_IMR) External Interrupt 14 */\r
+#define EIC_IMR_INT15 (0x1u << 15) /**< \brief (EIC_IMR) External Interrupt 15 */\r
+/* -------- EIC_ISR : (EIC Offset: 0x00C) Interrupt Status Register -------- */\r
+#define EIC_ISR_NMI (0x1u << 0) /**< \brief (EIC_ISR) External Non Maskable CPU interrupt */\r
+#define EIC_ISR_INT1 (0x1u << 1) /**< \brief (EIC_ISR) External Interrupt 1 */\r
+#define EIC_ISR_INT1_0 (0x0u << 1) /**< \brief (EIC_ISR) An interrupt event has not occurred */\r
+#define EIC_ISR_INT1_1 (0x1u << 1) /**< \brief (EIC_ISR) An interrupt event has occurred. */\r
+#define EIC_ISR_INT2 (0x1u << 2) /**< \brief (EIC_ISR) External Interrupt 2 */\r
+#define EIC_ISR_INT2_0 (0x0u << 2) /**< \brief (EIC_ISR) An interrupt event has not occurred */\r
+#define EIC_ISR_INT2_1 (0x1u << 2) /**< \brief (EIC_ISR) An interrupt event has occurred. */\r
+#define EIC_ISR_INT3 (0x1u << 3) /**< \brief (EIC_ISR) External Interrupt 3 */\r
+#define EIC_ISR_INT3_0 (0x0u << 3) /**< \brief (EIC_ISR) An interrupt event has not occurred */\r
+#define EIC_ISR_INT3_1 (0x1u << 3) /**< \brief (EIC_ISR) An interrupt event has occurred. */\r
+#define EIC_ISR_INT4 (0x1u << 4) /**< \brief (EIC_ISR) External Interrupt 4 */\r
+#define EIC_ISR_INT4_0 (0x0u << 4) /**< \brief (EIC_ISR) An interrupt event has not occurred */\r
+#define EIC_ISR_INT4_1 (0x1u << 4) /**< \brief (EIC_ISR) An interrupt event has occurred. */\r
+#define EIC_ISR_INT5 (0x1u << 5) /**< \brief (EIC_ISR) External Interrupt 5 */\r
+#define EIC_ISR_INT6 (0x1u << 6) /**< \brief (EIC_ISR) External Interrupt 6 */\r
+#define EIC_ISR_INT7 (0x1u << 7) /**< \brief (EIC_ISR) External Interrupt 7 */\r
+#define EIC_ISR_INT8 (0x1u << 8) /**< \brief (EIC_ISR) External Interrupt 8 */\r
+#define EIC_ISR_INT9 (0x1u << 9) /**< \brief (EIC_ISR) External Interrupt 9 */\r
+#define EIC_ISR_INT10 (0x1u << 10) /**< \brief (EIC_ISR) External Interrupt 10 */\r
+#define EIC_ISR_INT11 (0x1u << 11) /**< \brief (EIC_ISR) External Interrupt 11 */\r
+#define EIC_ISR_INT12 (0x1u << 12) /**< \brief (EIC_ISR) External Interrupt 12 */\r
+#define EIC_ISR_INT13 (0x1u << 13) /**< \brief (EIC_ISR) External Interrupt 13 */\r
+#define EIC_ISR_INT14 (0x1u << 14) /**< \brief (EIC_ISR) External Interrupt 14 */\r
+#define EIC_ISR_INT15 (0x1u << 15) /**< \brief (EIC_ISR) External Interrupt 15 */\r
+/* -------- EIC_ICR : (EIC Offset: 0x010) Interrupt Clear Register -------- */\r
+#define EIC_ICR_NMI (0x1u << 0) /**< \brief (EIC_ICR) External Non Maskable CPU interrupt */\r
+#define EIC_ICR_INT1 (0x1u << 1) /**< \brief (EIC_ICR) External Interrupt 1 */\r
+#define EIC_ICR_INT1_0 (0x0u << 1) /**< \brief (EIC_ICR) No effect */\r
+#define EIC_ICR_INT1_1 (0x1u << 1) /**< \brief (EIC_ICR) Clear Interrupt. */\r
+#define EIC_ICR_INT2 (0x1u << 2) /**< \brief (EIC_ICR) External Interrupt 2 */\r
+#define EIC_ICR_INT2_0 (0x0u << 2) /**< \brief (EIC_ICR) No effect */\r
+#define EIC_ICR_INT2_1 (0x1u << 2) /**< \brief (EIC_ICR) Clear Interrupt. */\r
+#define EIC_ICR_INT3 (0x1u << 3) /**< \brief (EIC_ICR) External Interrupt 3 */\r
+#define EIC_ICR_INT3_0 (0x0u << 3) /**< \brief (EIC_ICR) No effect */\r
+#define EIC_ICR_INT3_1 (0x1u << 3) /**< \brief (EIC_ICR) Clear Interrupt. */\r
+#define EIC_ICR_INT4 (0x1u << 4) /**< \brief (EIC_ICR) External Interrupt 4 */\r
+#define EIC_ICR_INT4_0 (0x0u << 4) /**< \brief (EIC_ICR) No effect */\r
+#define EIC_ICR_INT4_1 (0x1u << 4) /**< \brief (EIC_ICR) Clear Interrupt. */\r
+#define EIC_ICR_INT5 (0x1u << 5) /**< \brief (EIC_ICR) External Interrupt 5 */\r
+#define EIC_ICR_INT6 (0x1u << 6) /**< \brief (EIC_ICR) External Interrupt 6 */\r
+#define EIC_ICR_INT7 (0x1u << 7) /**< \brief (EIC_ICR) External Interrupt 7 */\r
+#define EIC_ICR_INT8 (0x1u << 8) /**< \brief (EIC_ICR) External Interrupt 8 */\r
+#define EIC_ICR_INT9 (0x1u << 9) /**< \brief (EIC_ICR) External Interrupt 9 */\r
+#define EIC_ICR_INT10 (0x1u << 10) /**< \brief (EIC_ICR) External Interrupt 10 */\r
+#define EIC_ICR_INT11 (0x1u << 11) /**< \brief (EIC_ICR) External Interrupt 11 */\r
+#define EIC_ICR_INT12 (0x1u << 12) /**< \brief (EIC_ICR) External Interrupt 12 */\r
+#define EIC_ICR_INT13 (0x1u << 13) /**< \brief (EIC_ICR) External Interrupt 13 */\r
+#define EIC_ICR_INT14 (0x1u << 14) /**< \brief (EIC_ICR) External Interrupt 14 */\r
+#define EIC_ICR_INT15 (0x1u << 15) /**< \brief (EIC_ICR) External Interrupt 15 */\r
+/* -------- EIC_MODE : (EIC Offset: 0x014) Mode Register -------- */\r
+#define EIC_MODE_NMI (0x1u << 0) /**< \brief (EIC_MODE) External Non Maskable CPU interrupt */\r
+#define EIC_MODE_INT1 (0x1u << 1) /**< \brief (EIC_MODE) External Interrupt 1 */\r
+#define EIC_MODE_INT1_0 (0x0u << 1) /**< \brief (EIC_MODE) Edge triggered interrupt */\r
+#define EIC_MODE_INT1_1 (0x1u << 1) /**< \brief (EIC_MODE) Level triggered interrupt */\r
+#define EIC_MODE_INT2 (0x1u << 2) /**< \brief (EIC_MODE) External Interrupt 2 */\r
+#define EIC_MODE_INT2_0 (0x0u << 2) /**< \brief (EIC_MODE) Edge triggered interrupt */\r
+#define EIC_MODE_INT2_1 (0x1u << 2) /**< \brief (EIC_MODE) Level triggered interrupt */\r
+#define EIC_MODE_INT3 (0x1u << 3) /**< \brief (EIC_MODE) External Interrupt 3 */\r
+#define EIC_MODE_INT3_0 (0x0u << 3) /**< \brief (EIC_MODE) Edge triggered interrupt */\r
+#define EIC_MODE_INT3_1 (0x1u << 3) /**< \brief (EIC_MODE) Level triggered interrupt */\r
+#define EIC_MODE_INT4 (0x1u << 4) /**< \brief (EIC_MODE) External Interrupt 4 */\r
+#define EIC_MODE_INT4_0 (0x0u << 4) /**< \brief (EIC_MODE) Edge triggered interrupt */\r
+#define EIC_MODE_INT4_1 (0x1u << 4) /**< \brief (EIC_MODE) Level triggered interrupt */\r
+#define EIC_MODE_INT5 (0x1u << 5) /**< \brief (EIC_MODE) External Interrupt 5 */\r
+#define EIC_MODE_INT6 (0x1u << 6) /**< \brief (EIC_MODE) External Interrupt 6 */\r
+#define EIC_MODE_INT7 (0x1u << 7) /**< \brief (EIC_MODE) External Interrupt 7 */\r
+#define EIC_MODE_INT8 (0x1u << 8) /**< \brief (EIC_MODE) External Interrupt 8 */\r
+#define EIC_MODE_INT9 (0x1u << 9) /**< \brief (EIC_MODE) External Interrupt 9 */\r
+#define EIC_MODE_INT10 (0x1u << 10) /**< \brief (EIC_MODE) External Interrupt 10 */\r
+#define EIC_MODE_INT11 (0x1u << 11) /**< \brief (EIC_MODE) External Interrupt 11 */\r
+#define EIC_MODE_INT12 (0x1u << 12) /**< \brief (EIC_MODE) External Interrupt 12 */\r
+#define EIC_MODE_INT13 (0x1u << 13) /**< \brief (EIC_MODE) External Interrupt 13 */\r
+#define EIC_MODE_INT14 (0x1u << 14) /**< \brief (EIC_MODE) External Interrupt 14 */\r
+#define EIC_MODE_INT15 (0x1u << 15) /**< \brief (EIC_MODE) External Interrupt 15 */\r
+/* -------- EIC_EDGE : (EIC Offset: 0x018) Edge Register -------- */\r
+#define EIC_EDGE_NMI (0x1u << 0) /**< \brief (EIC_EDGE) External Non Maskable CPU interrupt */\r
+#define EIC_EDGE_INT1 (0x1u << 1) /**< \brief (EIC_EDGE) External Interrupt 1 */\r
+#define EIC_EDGE_INT1_0 (0x0u << 1) /**< \brief (EIC_EDGE) Triggers on falling edge */\r
+#define EIC_EDGE_INT1_1 (0x1u << 1) /**< \brief (EIC_EDGE) Triggers on rising edge. */\r
+#define EIC_EDGE_INT2 (0x1u << 2) /**< \brief (EIC_EDGE) External Interrupt 2 */\r
+#define EIC_EDGE_INT2_0 (0x0u << 2) /**< \brief (EIC_EDGE) Triggers on falling edge */\r
+#define EIC_EDGE_INT2_1 (0x1u << 2) /**< \brief (EIC_EDGE) Triggers on rising edge. */\r
+#define EIC_EDGE_INT3 (0x1u << 3) /**< \brief (EIC_EDGE) External Interrupt 3 */\r
+#define EIC_EDGE_INT3_0 (0x0u << 3) /**< \brief (EIC_EDGE) Triggers on falling edge */\r
+#define EIC_EDGE_INT3_1 (0x1u << 3) /**< \brief (EIC_EDGE) Triggers on rising edge. */\r
+#define EIC_EDGE_INT4 (0x1u << 4) /**< \brief (EIC_EDGE) External Interrupt 4 */\r
+#define EIC_EDGE_INT4_0 (0x0u << 4) /**< \brief (EIC_EDGE) Triggers on falling edge */\r
+#define EIC_EDGE_INT4_1 (0x1u << 4) /**< \brief (EIC_EDGE) Triggers on rising edge. */\r
+#define EIC_EDGE_INT5 (0x1u << 5) /**< \brief (EIC_EDGE) External Interrupt 5 */\r
+#define EIC_EDGE_INT6 (0x1u << 6) /**< \brief (EIC_EDGE) External Interrupt 6 */\r
+#define EIC_EDGE_INT7 (0x1u << 7) /**< \brief (EIC_EDGE) External Interrupt 7 */\r
+#define EIC_EDGE_INT8 (0x1u << 8) /**< \brief (EIC_EDGE) External Interrupt 8 */\r
+#define EIC_EDGE_INT9 (0x1u << 9) /**< \brief (EIC_EDGE) External Interrupt 9 */\r
+#define EIC_EDGE_INT10 (0x1u << 10) /**< \brief (EIC_EDGE) External Interrupt 10 */\r
+#define EIC_EDGE_INT11 (0x1u << 11) /**< \brief (EIC_EDGE) External Interrupt 11 */\r
+#define EIC_EDGE_INT12 (0x1u << 12) /**< \brief (EIC_EDGE) External Interrupt 12 */\r
+#define EIC_EDGE_INT13 (0x1u << 13) /**< \brief (EIC_EDGE) External Interrupt 13 */\r
+#define EIC_EDGE_INT14 (0x1u << 14) /**< \brief (EIC_EDGE) External Interrupt 14 */\r
+#define EIC_EDGE_INT15 (0x1u << 15) /**< \brief (EIC_EDGE) External Interrupt 15 */\r
+/* -------- EIC_LEVEL : (EIC Offset: 0x01C) Level Register -------- */\r
+#define EIC_LEVEL_NMI (0x1u << 0) /**< \brief (EIC_LEVEL) External Non Maskable CPU interrupt */\r
+#define EIC_LEVEL_INT1 (0x1u << 1) /**< \brief (EIC_LEVEL) External Interrupt 1 */\r
+#define EIC_LEVEL_INT2 (0x1u << 2) /**< \brief (EIC_LEVEL) External Interrupt 2 */\r
+#define EIC_LEVEL_INT3 (0x1u << 3) /**< \brief (EIC_LEVEL) External Interrupt 3 */\r
+#define EIC_LEVEL_INT4 (0x1u << 4) /**< \brief (EIC_LEVEL) External Interrupt 4 */\r
+#define EIC_LEVEL_INT5 (0x1u << 5) /**< \brief (EIC_LEVEL) External Interrupt 5 */\r
+#define EIC_LEVEL_INT6 (0x1u << 6) /**< \brief (EIC_LEVEL) External Interrupt 6 */\r
+#define EIC_LEVEL_INT7 (0x1u << 7) /**< \brief (EIC_LEVEL) External Interrupt 7 */\r
+#define EIC_LEVEL_INT8 (0x1u << 8) /**< \brief (EIC_LEVEL) External Interrupt 8 */\r
+#define EIC_LEVEL_INT9 (0x1u << 9) /**< \brief (EIC_LEVEL) External Interrupt 9 */\r
+#define EIC_LEVEL_INT10 (0x1u << 10) /**< \brief (EIC_LEVEL) External Interrupt 10 */\r
+#define EIC_LEVEL_INT11 (0x1u << 11) /**< \brief (EIC_LEVEL) External Interrupt 11 */\r
+#define EIC_LEVEL_INT12 (0x1u << 12) /**< \brief (EIC_LEVEL) External Interrupt 12 */\r
+#define EIC_LEVEL_INT13 (0x1u << 13) /**< \brief (EIC_LEVEL) External Interrupt 13 */\r
+#define EIC_LEVEL_INT14 (0x1u << 14) /**< \brief (EIC_LEVEL) External Interrupt 14 */\r
+#define EIC_LEVEL_INT15 (0x1u << 15) /**< \brief (EIC_LEVEL) External Interrupt 15 */\r
+/* -------- EIC_FILTER : (EIC Offset: 0x020) Filter Register -------- */\r
+#define EIC_FILTER_NMI (0x1u << 0) /**< \brief (EIC_FILTER) External Non Maskable CPU interrupt */\r
+#define EIC_FILTER_INT1 (0x1u << 1) /**< \brief (EIC_FILTER) External Interrupt 1 */\r
+#define EIC_FILTER_INT2 (0x1u << 2) /**< \brief (EIC_FILTER) External Interrupt 2 */\r
+#define EIC_FILTER_INT3 (0x1u << 3) /**< \brief (EIC_FILTER) External Interrupt 3 */\r
+#define EIC_FILTER_INT4 (0x1u << 4) /**< \brief (EIC_FILTER) External Interrupt 4 */\r
+#define EIC_FILTER_INT5 (0x1u << 5) /**< \brief (EIC_FILTER) External Interrupt 5 */\r
+#define EIC_FILTER_INT6 (0x1u << 6) /**< \brief (EIC_FILTER) External Interrupt 6 */\r
+#define EIC_FILTER_INT7 (0x1u << 7) /**< \brief (EIC_FILTER) External Interrupt 7 */\r
+#define EIC_FILTER_INT8 (0x1u << 8) /**< \brief (EIC_FILTER) External Interrupt 8 */\r
+#define EIC_FILTER_INT9 (0x1u << 9) /**< \brief (EIC_FILTER) External Interrupt 9 */\r
+#define EIC_FILTER_INT10 (0x1u << 10) /**< \brief (EIC_FILTER) External Interrupt 10 */\r
+#define EIC_FILTER_INT11 (0x1u << 11) /**< \brief (EIC_FILTER) External Interrupt 11 */\r
+#define EIC_FILTER_INT12 (0x1u << 12) /**< \brief (EIC_FILTER) External Interrupt 12 */\r
+#define EIC_FILTER_INT13 (0x1u << 13) /**< \brief (EIC_FILTER) External Interrupt 13 */\r
+#define EIC_FILTER_INT14 (0x1u << 14) /**< \brief (EIC_FILTER) External Interrupt 14 */\r
+#define EIC_FILTER_INT15 (0x1u << 15) /**< \brief (EIC_FILTER) External Interrupt 15 */\r
+/* -------- EIC_ASYNC : (EIC Offset: 0x028) Asynchronous Register -------- */\r
+#define EIC_ASYNC_NMI (0x1u << 0) /**< \brief (EIC_ASYNC) External Non Maskable CPU interrupt */\r
+#define EIC_ASYNC_INT1 (0x1u << 1) /**< \brief (EIC_ASYNC) External Interrupt 1 */\r
+#define EIC_ASYNC_INT2 (0x1u << 2) /**< \brief (EIC_ASYNC) External Interrupt 2 */\r
+#define EIC_ASYNC_INT3 (0x1u << 3) /**< \brief (EIC_ASYNC) External Interrupt 3 */\r
+#define EIC_ASYNC_INT4 (0x1u << 4) /**< \brief (EIC_ASYNC) External Interrupt 4 */\r
+#define EIC_ASYNC_INT5 (0x1u << 5) /**< \brief (EIC_ASYNC) External Interrupt 5 */\r
+#define EIC_ASYNC_INT6 (0x1u << 6) /**< \brief (EIC_ASYNC) External Interrupt 6 */\r
+#define EIC_ASYNC_INT7 (0x1u << 7) /**< \brief (EIC_ASYNC) External Interrupt 7 */\r
+#define EIC_ASYNC_INT8 (0x1u << 8) /**< \brief (EIC_ASYNC) External Interrupt 8 */\r
+#define EIC_ASYNC_INT9 (0x1u << 9) /**< \brief (EIC_ASYNC) External Interrupt 9 */\r
+#define EIC_ASYNC_INT10 (0x1u << 10) /**< \brief (EIC_ASYNC) External Interrupt 10 */\r
+#define EIC_ASYNC_INT11 (0x1u << 11) /**< \brief (EIC_ASYNC) External Interrupt 11 */\r
+#define EIC_ASYNC_INT12 (0x1u << 12) /**< \brief (EIC_ASYNC) External Interrupt 12 */\r
+#define EIC_ASYNC_INT13 (0x1u << 13) /**< \brief (EIC_ASYNC) External Interrupt 13 */\r
+#define EIC_ASYNC_INT14 (0x1u << 14) /**< \brief (EIC_ASYNC) External Interrupt 14 */\r
+#define EIC_ASYNC_INT15 (0x1u << 15) /**< \brief (EIC_ASYNC) External Interrupt 15 */\r
+/* -------- EIC_EN : (EIC Offset: 0x030) Enable Register -------- */\r
+#define EIC_EN_NMI (0x1u << 0) /**< \brief (EIC_EN) External Non Maskable CPU interrupt */\r
+#define EIC_EN_INT1 (0x1u << 1) /**< \brief (EIC_EN) External Interrupt 1 */\r
+#define EIC_EN_INT2 (0x1u << 2) /**< \brief (EIC_EN) External Interrupt 2 */\r
+#define EIC_EN_INT3 (0x1u << 3) /**< \brief (EIC_EN) External Interrupt 3 */\r
+#define EIC_EN_INT4 (0x1u << 4) /**< \brief (EIC_EN) External Interrupt 4 */\r
+#define EIC_EN_INT5 (0x1u << 5) /**< \brief (EIC_EN) External Interrupt 5 */\r
+#define EIC_EN_INT6 (0x1u << 6) /**< \brief (EIC_EN) External Interrupt 6 */\r
+#define EIC_EN_INT7 (0x1u << 7) /**< \brief (EIC_EN) External Interrupt 7 */\r
+#define EIC_EN_INT8 (0x1u << 8) /**< \brief (EIC_EN) External Interrupt 8 */\r
+#define EIC_EN_INT9 (0x1u << 9) /**< \brief (EIC_EN) External Interrupt 9 */\r
+#define EIC_EN_INT10 (0x1u << 10) /**< \brief (EIC_EN) External Interrupt 10 */\r
+#define EIC_EN_INT11 (0x1u << 11) /**< \brief (EIC_EN) External Interrupt 11 */\r
+#define EIC_EN_INT12 (0x1u << 12) /**< \brief (EIC_EN) External Interrupt 12 */\r
+#define EIC_EN_INT13 (0x1u << 13) /**< \brief (EIC_EN) External Interrupt 13 */\r
+#define EIC_EN_INT14 (0x1u << 14) /**< \brief (EIC_EN) External Interrupt 14 */\r
+#define EIC_EN_INT15 (0x1u << 15) /**< \brief (EIC_EN) External Interrupt 15 */\r
+/* -------- EIC_DIS : (EIC Offset: 0x034) Disable Register -------- */\r
+#define EIC_DIS_NMI (0x1u << 0) /**< \brief (EIC_DIS) External Non Maskable CPU interrupt */\r
+#define EIC_DIS_INT1 (0x1u << 1) /**< \brief (EIC_DIS) External Interrupt 1 */\r
+#define EIC_DIS_INT2 (0x1u << 2) /**< \brief (EIC_DIS) External Interrupt 2 */\r
+#define EIC_DIS_INT3 (0x1u << 3) /**< \brief (EIC_DIS) External Interrupt 3 */\r
+#define EIC_DIS_INT4 (0x1u << 4) /**< \brief (EIC_DIS) External Interrupt 4 */\r
+#define EIC_DIS_INT5 (0x1u << 5) /**< \brief (EIC_DIS) External Interrupt 5 */\r
+#define EIC_DIS_INT6 (0x1u << 6) /**< \brief (EIC_DIS) External Interrupt 6 */\r
+#define EIC_DIS_INT7 (0x1u << 7) /**< \brief (EIC_DIS) External Interrupt 7 */\r
+#define EIC_DIS_INT8 (0x1u << 8) /**< \brief (EIC_DIS) External Interrupt 8 */\r
+#define EIC_DIS_INT9 (0x1u << 9) /**< \brief (EIC_DIS) External Interrupt 9 */\r
+#define EIC_DIS_INT10 (0x1u << 10) /**< \brief (EIC_DIS) External Interrupt 10 */\r
+#define EIC_DIS_INT11 (0x1u << 11) /**< \brief (EIC_DIS) External Interrupt 11 */\r
+#define EIC_DIS_INT12 (0x1u << 12) /**< \brief (EIC_DIS) External Interrupt 12 */\r
+#define EIC_DIS_INT13 (0x1u << 13) /**< \brief (EIC_DIS) External Interrupt 13 */\r
+#define EIC_DIS_INT14 (0x1u << 14) /**< \brief (EIC_DIS) External Interrupt 14 */\r
+#define EIC_DIS_INT15 (0x1u << 15) /**< \brief (EIC_DIS) External Interrupt 15 */\r
+/* -------- EIC_CTRL : (EIC Offset: 0x038) Control Register -------- */\r
+#define EIC_CTRL_NMI (0x1u << 0) /**< \brief (EIC_CTRL) External Non Maskable CPU interrupt */\r
+#define EIC_CTRL_INT1 (0x1u << 1) /**< \brief (EIC_CTRL) External Interrupt 1 */\r
+#define EIC_CTRL_INT2 (0x1u << 2) /**< \brief (EIC_CTRL) External Interrupt 2 */\r
+#define EIC_CTRL_INT3 (0x1u << 3) /**< \brief (EIC_CTRL) External Interrupt 3 */\r
+#define EIC_CTRL_INT4 (0x1u << 4) /**< \brief (EIC_CTRL) External Interrupt 4 */\r
+#define EIC_CTRL_INT5 (0x1u << 5) /**< \brief (EIC_CTRL) External Interrupt 5 */\r
+#define EIC_CTRL_INT6 (0x1u << 6) /**< \brief (EIC_CTRL) External Interrupt 6 */\r
+#define EIC_CTRL_INT7 (0x1u << 7) /**< \brief (EIC_CTRL) External Interrupt 7 */\r
+#define EIC_CTRL_INT8 (0x1u << 8) /**< \brief (EIC_CTRL) External Interrupt 8 */\r
+#define EIC_CTRL_INT9 (0x1u << 9) /**< \brief (EIC_CTRL) External Interrupt 9 */\r
+#define EIC_CTRL_INT10 (0x1u << 10) /**< \brief (EIC_CTRL) External Interrupt 10 */\r
+#define EIC_CTRL_INT11 (0x1u << 11) /**< \brief (EIC_CTRL) External Interrupt 11 */\r
+#define EIC_CTRL_INT12 (0x1u << 12) /**< \brief (EIC_CTRL) External Interrupt 12 */\r
+#define EIC_CTRL_INT13 (0x1u << 13) /**< \brief (EIC_CTRL) External Interrupt 13 */\r
+#define EIC_CTRL_INT14 (0x1u << 14) /**< \brief (EIC_CTRL) External Interrupt 14 */\r
+#define EIC_CTRL_INT15 (0x1u << 15) /**< \brief (EIC_CTRL) External Interrupt 15 */\r
+/* -------- EIC_VERSION : (EIC Offset: 0x3FC) Version Register -------- */\r
+#define EIC_VERSION_VERSION_Pos 0\r
+#define EIC_VERSION_VERSION_Msk (0xFFFu << EIC_VERSION_VERSION_Pos) /**< \brief (EIC_VERSION) Version bits */\r
+#define EIC_VERSION_VERSION(value) ((EIC_VERSION_VERSION_Msk & ((value) << EIC_VERSION_VERSION_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR FLASHCALW */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_FLASHCALW Flash Controller */\r
+/*@{*/\r
+\r
+#define REV_FLASHCALW 0x110\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief FLASHCALW hardware registers */\r
+typedef struct {\r
+ RwReg FLASHCALW_FCR; /**< \brief (FLASHCALW Offset: 0x00) Flash Controller Control Register */\r
+ RwReg FLASHCALW_FCMD; /**< \brief (FLASHCALW Offset: 0x04) Flash Controller Command Register */\r
+ RwReg FLASHCALW_FSR; /**< \brief (FLASHCALW Offset: 0x08) Flash Controller Status Register */\r
+ RoReg FLASHCALW_FPR; /**< \brief (FLASHCALW Offset: 0x0C) Flash Controller Parameter Register */\r
+ RoReg FLASHCALW_VERSION; /**< \brief (FLASHCALW Offset: 0x10) Flash Controller Version Register */\r
+ RwReg FLASHCALW_FGPFRHI; /**< \brief (FLASHCALW Offset: 0x14) Flash Controller General Purpose Fuse Register High */\r
+ RwReg FLASHCALW_FGPFRLO; /**< \brief (FLASHCALW Offset: 0x18) Flash Controller General Purpose Fuse Register Low */\r
+} Flashcalw;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- FLASHCALW_FCR : (FLASHCALW Offset: 0x00) Flash Controller Control Register -------- */\r
+#define FLASHCALW_FCR_FRDY (0x1u << 0) /**< \brief (FLASHCALW_FCR) Flash Ready Interrupt Enable */\r
+#define FLASHCALW_FCR_FRDY_0 (0x0u << 0) /**< \brief (FLASHCALW_FCR) Flash Ready does not generate an interrupt */\r
+#define FLASHCALW_FCR_FRDY_1 (0x1u << 0) /**< \brief (FLASHCALW_FCR) Flash Ready generates an interrupt */\r
+#define FLASHCALW_FCR_LOCKE (0x1u << 2) /**< \brief (FLASHCALW_FCR) Lock Error Interrupt Enable */\r
+#define FLASHCALW_FCR_LOCKE_0 (0x0u << 2) /**< \brief (FLASHCALW_FCR) Lock Error does not generate an interrupt */\r
+#define FLASHCALW_FCR_LOCKE_1 (0x1u << 2) /**< \brief (FLASHCALW_FCR) Lock Error generates an interrupt */\r
+#define FLASHCALW_FCR_PROGE (0x1u << 3) /**< \brief (FLASHCALW_FCR) Programming Error Interrupt Enable */\r
+#define FLASHCALW_FCR_PROGE_0 (0x0u << 3) /**< \brief (FLASHCALW_FCR) Programming Error does not generate an interrupt */\r
+#define FLASHCALW_FCR_PROGE_1 (0x1u << 3) /**< \brief (FLASHCALW_FCR) Programming Error generates an interrupt */\r
+#define FLASHCALW_FCR_FWS (0x1u << 6) /**< \brief (FLASHCALW_FCR) Flash Wait State */\r
+#define FLASHCALW_FCR_FWS_0 (0x0u << 6) /**< \brief (FLASHCALW_FCR) The flash is read with 0 wait states */\r
+#define FLASHCALW_FCR_FWS_1 (0x1u << 6) /**< \brief (FLASHCALW_FCR) The flash is read with 1 wait states */\r
+#define FLASHCALW_FCR_WS1OPT (0x1u << 7) /**< \brief (FLASHCALW_FCR) Wait State 1 Optimization */\r
+/* -------- FLASHCALW_FCMD : (FLASHCALW Offset: 0x04) Flash Controller Command Register -------- */\r
+#define FLASHCALW_FCMD_CMD_Pos 0\r
+#define FLASHCALW_FCMD_CMD_Msk (0x3Fu << FLASHCALW_FCMD_CMD_Pos) /**< \brief (FLASHCALW_FCMD) Command */\r
+#define FLASHCALW_FCMD_CMD(value) ((FLASHCALW_FCMD_CMD_Msk & ((value) << FLASHCALW_FCMD_CMD_Pos)))\r
+#define FLASHCALW_FCMD_CMD_NOP (0x0u << 0) /**< \brief (FLASHCALW_FCMD) No Operation */\r
+#define FLASHCALW_FCMD_CMD_WP (0x1u << 0) /**< \brief (FLASHCALW_FCMD) Write Page */\r
+#define FLASHCALW_FCMD_CMD_EP (0x2u << 0) /**< \brief (FLASHCALW_FCMD) Erase Page */\r
+#define FLASHCALW_FCMD_CMD_CPB (0x3u << 0) /**< \brief (FLASHCALW_FCMD) Clear Page Buffer */\r
+#define FLASHCALW_FCMD_CMD_LP (0x4u << 0) /**< \brief (FLASHCALW_FCMD) Lock Region containing page */\r
+#define FLASHCALW_FCMD_CMD_UP (0x5u << 0) /**< \brief (FLASHCALW_FCMD) Unlock Region containing page */\r
+#define FLASHCALW_FCMD_CMD_EA (0x6u << 0) /**< \brief (FLASHCALW_FCMD) Erase All, including secuity and fuse bits */\r
+#define FLASHCALW_FCMD_CMD_WGPB (0x7u << 0) /**< \brief (FLASHCALW_FCMD) Write General-Purpose fuse Bit */\r
+#define FLASHCALW_FCMD_CMD_EGPB (0x8u << 0) /**< \brief (FLASHCALW_FCMD) Erase General-Purpose fuse Bit */\r
+#define FLASHCALW_FCMD_CMD_SSB (0x9u << 0) /**< \brief (FLASHCALW_FCMD) Set Security Bit */\r
+#define FLASHCALW_FCMD_CMD_PGPFB (0xAu << 0) /**< \brief (FLASHCALW_FCMD) Program GPFuse Byte */\r
+#define FLASHCALW_FCMD_CMD_EAGPF (0xBu << 0) /**< \brief (FLASHCALW_FCMD) Erase All GP Fuses */\r
+#define FLASHCALW_FCMD_CMD_QPR (0xCu << 0) /**< \brief (FLASHCALW_FCMD) Quick Page Read */\r
+#define FLASHCALW_FCMD_CMD_WUP (0xDu << 0) /**< \brief (FLASHCALW_FCMD) Write User Page */\r
+#define FLASHCALW_FCMD_CMD_EUP (0xEu << 0) /**< \brief (FLASHCALW_FCMD) Erase User Page */\r
+#define FLASHCALW_FCMD_CMD_QPRUP (0xFu << 0) /**< \brief (FLASHCALW_FCMD) Quick Page Read User Page */\r
+#define FLASHCALW_FCMD_PAGEN_Pos 8\r
+#define FLASHCALW_FCMD_PAGEN_Msk (0xFFFFu << FLASHCALW_FCMD_PAGEN_Pos) /**< \brief (FLASHCALW_FCMD) Page number */\r
+#define FLASHCALW_FCMD_PAGEN(value) ((FLASHCALW_FCMD_PAGEN_Msk & ((value) << FLASHCALW_FCMD_PAGEN_Pos)))\r
+#define FLASHCALW_FCMD_KEY_Pos 24\r
+#define FLASHCALW_FCMD_KEY_Msk (0xFFu << FLASHCALW_FCMD_KEY_Pos) /**< \brief (FLASHCALW_FCMD) Write protection key */\r
+#define FLASHCALW_FCMD_KEY(value) ((FLASHCALW_FCMD_KEY_Msk & ((value) << FLASHCALW_FCMD_KEY_Pos)))\r
+#define FLASHCALW_FCMD_KEY_KEY (0xA5u << 24) /**< \brief (FLASHCALW_FCMD) */\r
+/* -------- FLASHCALW_FSR : (FLASHCALW Offset: 0x08) Flash Controller Status Register -------- */\r
+#define FLASHCALW_FSR_FRDY (0x1u << 0) /**< \brief (FLASHCALW_FSR) Flash Ready Status */\r
+#define FLASHCALW_FSR_LOCKE (0x1u << 2) /**< \brief (FLASHCALW_FSR) Lock Error Status */\r
+#define FLASHCALW_FSR_PROGE (0x1u << 3) /**< \brief (FLASHCALW_FSR) Programming Error Status */\r
+#define FLASHCALW_FSR_SECURITY (0x1u << 4) /**< \brief (FLASHCALW_FSR) Security Bit Status */\r
+#define FLASHCALW_FSR_QPRR (0x1u << 5) /**< \brief (FLASHCALW_FSR) Quick Page Read Result */\r
+#define FLASHCALW_FSR_HSMODE (0x1u << 6) /**< \brief (FLASHCALW_FSR) High Speed Mode */\r
+#define FLASHCALW_FSR_ECCERR_Pos 8\r
+#define FLASHCALW_FSR_ECCERR_Msk (0x3u << FLASHCALW_FSR_ECCERR_Pos) /**< \brief (FLASHCALW_FSR) ECC Error Status */\r
+#define FLASHCALW_FSR_ECCERR(value) ((FLASHCALW_FSR_ECCERR_Msk & ((value) << FLASHCALW_FSR_ECCERR_Pos)))\r
+#define FLASHCALW_FSR_ECCERR_NOERROR (0x0u << 8) /**< \brief (FLASHCALW_FSR) no error */\r
+#define FLASHCALW_FSR_ECCERR_ONEECCERR (0x1u << 8) /**< \brief (FLASHCALW_FSR) one ECC error detected */\r
+#define FLASHCALW_FSR_ECCERR_TWOECCERR (0x2u << 8) /**< \brief (FLASHCALW_FSR) two ECC errors detected */\r
+#define FLASHCALW_FSR_LOCK0 (0x1u << 16) /**< \brief (FLASHCALW_FSR) Lock Region 0 Lock Status */\r
+#define FLASHCALW_FSR_LOCK1 (0x1u << 17) /**< \brief (FLASHCALW_FSR) Lock Region 1 Lock Status */\r
+#define FLASHCALW_FSR_LOCK2 (0x1u << 18) /**< \brief (FLASHCALW_FSR) Lock Region 2 Lock Status */\r
+#define FLASHCALW_FSR_LOCK3 (0x1u << 19) /**< \brief (FLASHCALW_FSR) Lock Region 3 Lock Status */\r
+#define FLASHCALW_FSR_LOCK4 (0x1u << 20) /**< \brief (FLASHCALW_FSR) Lock Region 4 Lock Status */\r
+#define FLASHCALW_FSR_LOCK5 (0x1u << 21) /**< \brief (FLASHCALW_FSR) Lock Region 5 Lock Status */\r
+#define FLASHCALW_FSR_LOCK6 (0x1u << 22) /**< \brief (FLASHCALW_FSR) Lock Region 6 Lock Status */\r
+#define FLASHCALW_FSR_LOCK7 (0x1u << 23) /**< \brief (FLASHCALW_FSR) Lock Region 7 Lock Status */\r
+#define FLASHCALW_FSR_LOCK8 (0x1u << 24) /**< \brief (FLASHCALW_FSR) Lock Region 8 Lock Status */\r
+#define FLASHCALW_FSR_LOCK9 (0x1u << 25) /**< \brief (FLASHCALW_FSR) Lock Region 9 Lock Status */\r
+#define FLASHCALW_FSR_LOCK10 (0x1u << 26) /**< \brief (FLASHCALW_FSR) Lock Region 10 Lock Status */\r
+#define FLASHCALW_FSR_LOCK11 (0x1u << 27) /**< \brief (FLASHCALW_FSR) Lock Region 11 Lock Status */\r
+#define FLASHCALW_FSR_LOCK12 (0x1u << 28) /**< \brief (FLASHCALW_FSR) Lock Region 12 Lock Status */\r
+#define FLASHCALW_FSR_LOCK13 (0x1u << 29) /**< \brief (FLASHCALW_FSR) Lock Region 13 Lock Status */\r
+#define FLASHCALW_FSR_LOCK14 (0x1u << 30) /**< \brief (FLASHCALW_FSR) Lock Region 14 Lock Status */\r
+#define FLASHCALW_FSR_LOCK15 (0x1u << 31) /**< \brief (FLASHCALW_FSR) Lock Region 15 Lock Status */\r
+/* -------- FLASHCALW_FPR : (FLASHCALW Offset: 0x0C) Flash Controller Parameter Register -------- */\r
+#define FLASHCALW_FPR_FSZ_Pos 0\r
+#define FLASHCALW_FPR_FSZ_Msk (0xFu << FLASHCALW_FPR_FSZ_Pos) /**< \brief (FLASHCALW_FPR) Flash Size */\r
+#define FLASHCALW_FPR_FSZ(value) ((FLASHCALW_FPR_FSZ_Msk & ((value) << FLASHCALW_FPR_FSZ_Pos)))\r
+#define FLASHCALW_FPR_PSZ_Pos 8\r
+#define FLASHCALW_FPR_PSZ_Msk (0x7u << FLASHCALW_FPR_PSZ_Pos) /**< \brief (FLASHCALW_FPR) Page Size */\r
+#define FLASHCALW_FPR_PSZ(value) ((FLASHCALW_FPR_PSZ_Msk & ((value) << FLASHCALW_FPR_PSZ_Pos)))\r
+/* -------- FLASHCALW_VERSION : (FLASHCALW Offset: 0x10) Flash Controller Version Register -------- */\r
+#define FLASHCALW_VERSION_VERSION_Pos 0\r
+#define FLASHCALW_VERSION_VERSION_Msk (0xFFFu << FLASHCALW_VERSION_VERSION_Pos) /**< \brief (FLASHCALW_VERSION) Version Number */\r
+#define FLASHCALW_VERSION_VERSION(value) ((FLASHCALW_VERSION_VERSION_Msk & ((value) << FLASHCALW_VERSION_VERSION_Pos)))\r
+#define FLASHCALW_VERSION_VARIANT_Pos 16\r
+#define FLASHCALW_VERSION_VARIANT_Msk (0xFu << FLASHCALW_VERSION_VARIANT_Pos) /**< \brief (FLASHCALW_VERSION) Variant Number */\r
+#define FLASHCALW_VERSION_VARIANT(value) ((FLASHCALW_VERSION_VARIANT_Msk & ((value) << FLASHCALW_VERSION_VARIANT_Pos)))\r
+/* -------- FLASHCALW_FGPFRHI : (FLASHCALW Offset: 0x14) Flash Controller General Purpose Fuse Register High -------- */\r
+#define FLASHCALW_FGPFRHI_GPF32 (0x1u << 0) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 32 */\r
+#define FLASHCALW_FGPFRHI_GPF33 (0x1u << 1) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 33 */\r
+#define FLASHCALW_FGPFRHI_GPF34 (0x1u << 2) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 34 */\r
+#define FLASHCALW_FGPFRHI_GPF35 (0x1u << 3) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 35 */\r
+#define FLASHCALW_FGPFRHI_GPF36 (0x1u << 4) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 36 */\r
+#define FLASHCALW_FGPFRHI_GPF37 (0x1u << 5) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 37 */\r
+#define FLASHCALW_FGPFRHI_GPF38 (0x1u << 6) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 38 */\r
+#define FLASHCALW_FGPFRHI_GPF39 (0x1u << 7) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 39 */\r
+#define FLASHCALW_FGPFRHI_GPF40 (0x1u << 8) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 40 */\r
+#define FLASHCALW_FGPFRHI_GPF41 (0x1u << 9) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 41 */\r
+#define FLASHCALW_FGPFRHI_GPF42 (0x1u << 10) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 42 */\r
+#define FLASHCALW_FGPFRHI_GPF43 (0x1u << 11) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 43 */\r
+#define FLASHCALW_FGPFRHI_GPF44 (0x1u << 12) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 44 */\r
+#define FLASHCALW_FGPFRHI_GPF45 (0x1u << 13) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 45 */\r
+#define FLASHCALW_FGPFRHI_GPF46 (0x1u << 14) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 46 */\r
+#define FLASHCALW_FGPFRHI_GPF47 (0x1u << 15) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 47 */\r
+#define FLASHCALW_FGPFRHI_GPF48 (0x1u << 16) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 48 */\r
+#define FLASHCALW_FGPFRHI_GPF49 (0x1u << 17) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 49 */\r
+#define FLASHCALW_FGPFRHI_GPF50 (0x1u << 18) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 50 */\r
+#define FLASHCALW_FGPFRHI_GPF51 (0x1u << 19) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 51 */\r
+#define FLASHCALW_FGPFRHI_GPF52 (0x1u << 20) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 52 */\r
+#define FLASHCALW_FGPFRHI_GPF53 (0x1u << 21) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 53 */\r
+#define FLASHCALW_FGPFRHI_GPF54 (0x1u << 22) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 54 */\r
+#define FLASHCALW_FGPFRHI_GPF55 (0x1u << 23) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 55 */\r
+#define FLASHCALW_FGPFRHI_GPF56 (0x1u << 24) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 56 */\r
+#define FLASHCALW_FGPFRHI_GPF57 (0x1u << 25) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 57 */\r
+#define FLASHCALW_FGPFRHI_GPF58 (0x1u << 26) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 58 */\r
+#define FLASHCALW_FGPFRHI_GPF59 (0x1u << 27) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 59 */\r
+#define FLASHCALW_FGPFRHI_GPF60 (0x1u << 28) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 60 */\r
+#define FLASHCALW_FGPFRHI_GPF61 (0x1u << 29) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 61 */\r
+#define FLASHCALW_FGPFRHI_GPF62 (0x1u << 30) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 62 */\r
+#define FLASHCALW_FGPFRHI_GPF63 (0x1u << 31) /**< \brief (FLASHCALW_FGPFRHI) General Purpose Fuse 63 */\r
+/* -------- FLASHCALW_FGPFRLO : (FLASHCALW Offset: 0x18) Flash Controller General Purpose Fuse Register Low -------- */\r
+#define FLASHCALW_FGPFRLO_LOCK0 (0x1u << 0) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 0 */\r
+#define FLASHCALW_FGPFRLO_LOCK1 (0x1u << 1) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 1 */\r
+#define FLASHCALW_FGPFRLO_LOCK2 (0x1u << 2) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 2 */\r
+#define FLASHCALW_FGPFRLO_LOCK3 (0x1u << 3) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 3 */\r
+#define FLASHCALW_FGPFRLO_LOCK4 (0x1u << 4) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 4 */\r
+#define FLASHCALW_FGPFRLO_LOCK5 (0x1u << 5) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 5 */\r
+#define FLASHCALW_FGPFRLO_LOCK6 (0x1u << 6) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 6 */\r
+#define FLASHCALW_FGPFRLO_LOCK7 (0x1u << 7) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 7 */\r
+#define FLASHCALW_FGPFRLO_LOCK8 (0x1u << 8) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 8 */\r
+#define FLASHCALW_FGPFRLO_LOCK9 (0x1u << 9) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 9 */\r
+#define FLASHCALW_FGPFRLO_LOCK10 (0x1u << 10) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 10 */\r
+#define FLASHCALW_FGPFRLO_LOCK11 (0x1u << 11) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 11 */\r
+#define FLASHCALW_FGPFRLO_LOCK12 (0x1u << 12) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 12 */\r
+#define FLASHCALW_FGPFRLO_LOCK13 (0x1u << 13) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 13 */\r
+#define FLASHCALW_FGPFRLO_LOCK14 (0x1u << 14) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 14 */\r
+#define FLASHCALW_FGPFRLO_LOCK15 (0x1u << 15) /**< \brief (FLASHCALW_FGPFRLO) Lock Bit 15 */\r
+#define FLASHCALW_FGPFRLO_GPF16 (0x1u << 16) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 16 */\r
+#define FLASHCALW_FGPFRLO_GPF17 (0x1u << 17) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 17 */\r
+#define FLASHCALW_FGPFRLO_GPF18 (0x1u << 18) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 18 */\r
+#define FLASHCALW_FGPFRLO_GPF19 (0x1u << 19) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 19 */\r
+#define FLASHCALW_FGPFRLO_GPF20 (0x1u << 20) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 20 */\r
+#define FLASHCALW_FGPFRLO_GPF21 (0x1u << 21) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 21 */\r
+#define FLASHCALW_FGPFRLO_GPF22 (0x1u << 22) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 22 */\r
+#define FLASHCALW_FGPFRLO_GPF23 (0x1u << 23) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 23 */\r
+#define FLASHCALW_FGPFRLO_GPF24 (0x1u << 24) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 24 */\r
+#define FLASHCALW_FGPFRLO_GPF25 (0x1u << 25) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 25 */\r
+#define FLASHCALW_FGPFRLO_GPF26 (0x1u << 26) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 26 */\r
+#define FLASHCALW_FGPFRLO_GPF27 (0x1u << 27) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 27 */\r
+#define FLASHCALW_FGPFRLO_GPF28 (0x1u << 28) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 28 */\r
+#define FLASHCALW_FGPFRLO_GPF29 (0x1u << 29) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 29 */\r
+#define FLASHCALW_FGPFRLO_GPF30 (0x1u << 30) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 30 */\r
+#define FLASHCALW_FGPFRLO_GPF31 (0x1u << 31) /**< \brief (FLASHCALW_FGPFRLO) General Purpose Fuse 31 */\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR FREQM */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_FREQM Frequency Meter */\r
+/*@{*/\r
+\r
+#define REV_FREQM 0x311\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief FREQM hardware registers */\r
+typedef struct {\r
+ WoReg FREQM_CTRL; /**< \brief (FREQM Offset: 0x000) Control register */\r
+ RwReg FREQM_MODE; /**< \brief (FREQM Offset: 0x004) Mode register */\r
+ RoReg FREQM_STATUS; /**< \brief (FREQM Offset: 0x008) Status register */\r
+ RoReg FREQM_VALUE; /**< \brief (FREQM Offset: 0x00C) Value register */\r
+ WoReg FREQM_IER; /**< \brief (FREQM Offset: 0x010) Interrupt Enable Register */\r
+ WoReg FREQM_IDR; /**< \brief (FREQM Offset: 0x014) Interrupt Diable Register */\r
+ RoReg FREQM_IMR; /**< \brief (FREQM Offset: 0x018) Interrupt Mask Register */\r
+ RoReg FREQM_ISR; /**< \brief (FREQM Offset: 0x01C) Interrupt Status Register */\r
+ WoReg FREQM_ICR; /**< \brief (FREQM Offset: 0x020) Interrupt Clear Register */\r
+ RoReg Reserved1[246];\r
+ RoReg FREQM_VERSION; /**< \brief (FREQM Offset: 0x3FC) Version Register */\r
+} Freqm;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- FREQM_CTRL : (FREQM Offset: 0x000) Control register -------- */\r
+#define FREQM_CTRL_START (0x1u << 0) /**< \brief (FREQM_CTRL) Start frequency measurement */\r
+/* -------- FREQM_MODE : (FREQM Offset: 0x004) Mode register -------- */\r
+#define FREQM_MODE_REFSEL_Pos 0\r
+#define FREQM_MODE_REFSEL_Msk (0x3u << FREQM_MODE_REFSEL_Pos) /**< \brief (FREQM_MODE) Reference Clock Selection */\r
+#define FREQM_MODE_REFSEL(value) ((FREQM_MODE_REFSEL_Msk & ((value) << FREQM_MODE_REFSEL_Pos)))\r
+#define FREQM_MODE_REFNUM_Pos 8\r
+#define FREQM_MODE_REFNUM_Msk (0xFFu << FREQM_MODE_REFNUM_Pos) /**< \brief (FREQM_MODE) Number of Reference CLock Cycles */\r
+#define FREQM_MODE_REFNUM(value) ((FREQM_MODE_REFNUM_Msk & ((value) << FREQM_MODE_REFNUM_Pos)))\r
+#define FREQM_MODE_CLKSEL_Pos 16\r
+#define FREQM_MODE_CLKSEL_Msk (0x1Fu << FREQM_MODE_CLKSEL_Pos) /**< \brief (FREQM_MODE) Clock Source Selection */\r
+#define FREQM_MODE_CLKSEL(value) ((FREQM_MODE_CLKSEL_Msk & ((value) << FREQM_MODE_CLKSEL_Pos)))\r
+#define FREQM_MODE_REFCEN (0x1u << 31) /**< \brief (FREQM_MODE) Reference Clock Enable */\r
+/* -------- FREQM_STATUS : (FREQM Offset: 0x008) Status register -------- */\r
+#define FREQM_STATUS_BUSY (0x1u << 0) /**< \brief (FREQM_STATUS) Frequency measurement on-going */\r
+#define FREQM_STATUS_RCLKBUSY (0x1u << 1) /**< \brief (FREQM_STATUS) Reference Clock busy */\r
+/* -------- FREQM_VALUE : (FREQM Offset: 0x00C) Value register -------- */\r
+#define FREQM_VALUE_VALUE_Pos 0\r
+#define FREQM_VALUE_VALUE_Msk (0xFFFFFFu << FREQM_VALUE_VALUE_Pos) /**< \brief (FREQM_VALUE) Measured frequency */\r
+#define FREQM_VALUE_VALUE(value) ((FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos)))\r
+/* -------- FREQM_IER : (FREQM Offset: 0x010) Interrupt Enable Register -------- */\r
+#define FREQM_IER_DONE (0x1u << 0) /**< \brief (FREQM_IER) Frequency measurment done */\r
+#define FREQM_IER_RCLKRDY (0x1u << 1) /**< \brief (FREQM_IER) Reference Clock ready */\r
+/* -------- FREQM_IDR : (FREQM Offset: 0x014) Interrupt Diable Register -------- */\r
+#define FREQM_IDR_DONE (0x1u << 0) /**< \brief (FREQM_IDR) Frequency measurment done */\r
+#define FREQM_IDR_RCLKRDY (0x1u << 1) /**< \brief (FREQM_IDR) Reference Clock ready */\r
+/* -------- FREQM_IMR : (FREQM Offset: 0x018) Interrupt Mask Register -------- */\r
+#define FREQM_IMR_DONE (0x1u << 0) /**< \brief (FREQM_IMR) Frequency measurment done */\r
+#define FREQM_IMR_RCLKRDY (0x1u << 1) /**< \brief (FREQM_IMR) Reference Clock ready */\r
+/* -------- FREQM_ISR : (FREQM Offset: 0x01C) Interrupt Status Register -------- */\r
+#define FREQM_ISR_DONE (0x1u << 0) /**< \brief (FREQM_ISR) Frequency measurment done */\r
+#define FREQM_ISR_RCLKRDY (0x1u << 1) /**< \brief (FREQM_ISR) Reference Clock ready */\r
+/* -------- FREQM_ICR : (FREQM Offset: 0x020) Interrupt Clear Register -------- */\r
+#define FREQM_ICR_DONE (0x1u << 0) /**< \brief (FREQM_ICR) Frequency measurment done */\r
+#define FREQM_ICR_RCLKRDY (0x1u << 1) /**< \brief (FREQM_ICR) Reference Clock ready */\r
+/* -------- FREQM_VERSION : (FREQM Offset: 0x3FC) Version Register -------- */\r
+#define FREQM_VERSION_VERSION_Pos 0\r
+#define FREQM_VERSION_VERSION_Msk (0xFFFu << FREQM_VERSION_VERSION_Pos) /**< \brief (FREQM_VERSION) Version number */\r
+#define FREQM_VERSION_VERSION(value) ((FREQM_VERSION_VERSION_Msk & ((value) << FREQM_VERSION_VERSION_Pos)))\r
+#define FREQM_VERSION_VARIANT_Pos 16\r
+#define FREQM_VERSION_VARIANT_Msk (0xFu << FREQM_VERSION_VARIANT_Pos) /**< \brief (FREQM_VERSION) Variant number */\r
+#define FREQM_VERSION_VARIANT(value) ((FREQM_VERSION_VARIANT_Msk & ((value) << FREQM_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR GLOC */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_GLOC Glue Logic Controller */\r
+/*@{*/\r
+\r
+#define REV_GLOC 0x102\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief GlocLut hardware registers */\r
+typedef struct {\r
+ RwReg GLOC_CR; /**< \brief (GlocLut Offset: 0x00) Control Register */\r
+ RwReg GLOC_TRUTH; /**< \brief (GlocLut Offset: 0x04) Truth Register */\r
+} GlocLut;\r
+/** \brief GLOC hardware registers */\r
+#define GLOC_LUTS 2\r
+typedef struct {\r
+ GlocLut GLOC_LUT[GLOC_LUTS]; /**< \brief (GLOC Offset: 0x00) GlocLut groups */\r
+ GlocLut Reserved1[7 - GLOC_LUTS];\r
+ RoReg GLOC_PARAMETER; /**< \brief (GLOC Offset: 0x38) Parameter Register */\r
+ RoReg GLOC_VERSION; /**< \brief (GLOC Offset: 0x3C) Version Register */\r
+} Gloc;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- GLOC_CR : (GLOC Offset: 0x00) Lut Control Register -------- */\r
+#define GLOC_CR_AEN_Pos 0\r
+#define GLOC_CR_AEN_Msk (0xFu << GLOC_CR_AEN_Pos) /**< \brief (GLOC_CR) Input mask */\r
+#define GLOC_CR_AEN(value) ((GLOC_CR_AEN_Msk & ((value) << GLOC_CR_AEN_Pos)))\r
+#define GLOC_CR_FILTEN (0x1u << 31) /**< \brief (GLOC_CR) Filter enable */\r
+/* -------- GLOC_TRUTH : (GLOC Offset: 0x04) Lut Truth Register -------- */\r
+#define GLOC_TRUTH_TRUTH_Pos 0\r
+#define GLOC_TRUTH_TRUTH_Msk (0xFFFFu << GLOC_TRUTH_TRUTH_Pos) /**< \brief (GLOC_TRUTH) Truth */\r
+#define GLOC_TRUTH_TRUTH(value) ((GLOC_TRUTH_TRUTH_Msk & ((value) << GLOC_TRUTH_TRUTH_Pos)))\r
+/* -------- GLOC_PARAMETER : (GLOC Offset: 0x38) Parameter Register -------- */\r
+#define GLOC_PARAMETER_LUTS_Pos 0\r
+#define GLOC_PARAMETER_LUTS_Msk (0xFFu << GLOC_PARAMETER_LUTS_Pos) /**< \brief (GLOC_PARAMETER) LUTs */\r
+#define GLOC_PARAMETER_LUTS(value) ((GLOC_PARAMETER_LUTS_Msk & ((value) << GLOC_PARAMETER_LUTS_Pos)))\r
+/* -------- GLOC_VERSION : (GLOC Offset: 0x3C) Version Register -------- */\r
+#define GLOC_VERSION_VERSION_Pos 0\r
+#define GLOC_VERSION_VERSION_Msk (0xFFFu << GLOC_VERSION_VERSION_Pos) /**< \brief (GLOC_VERSION) Version */\r
+#define GLOC_VERSION_VERSION(value) ((GLOC_VERSION_VERSION_Msk & ((value) << GLOC_VERSION_VERSION_Pos)))\r
+#define GLOC_VERSION_VARIANT_Pos 16\r
+#define GLOC_VERSION_VARIANT_Msk (0xFu << GLOC_VERSION_VARIANT_Pos) /**< \brief (GLOC_VERSION) Variant */\r
+#define GLOC_VERSION_VARIANT(value) ((GLOC_VERSION_VARIANT_Msk & ((value) << GLOC_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR GPIO */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_GPIO General-Purpose Input/Output Controller */\r
+/*@{*/\r
+\r
+#define REV_GPIO 0x215\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief GpioPort hardware registers */\r
+typedef struct {\r
+ RwReg GPIO_GPER; /**< \brief (GpioPort Offset: 0x000) GPIO Enable Register */\r
+ WoReg GPIO_GPERS; /**< \brief (GpioPort Offset: 0x004) GPIO Enable Register - Set */\r
+ WoReg GPIO_GPERC; /**< \brief (GpioPort Offset: 0x008) GPIO Enable Register - Clear */\r
+ WoReg GPIO_GPERT; /**< \brief (GpioPort Offset: 0x00C) GPIO Enable Register - Toggle */\r
+ RwReg GPIO_PMR0; /**< \brief (GpioPort Offset: 0x010) Peripheral Mux Register 0 */\r
+ WoReg GPIO_PMR0S; /**< \brief (GpioPort Offset: 0x014) Peripheral Mux Register 0 - Set */\r
+ WoReg GPIO_PMR0C; /**< \brief (GpioPort Offset: 0x018) Peripheral Mux Register 0 - Clear */\r
+ WoReg GPIO_PMR0T; /**< \brief (GpioPort Offset: 0x01C) Peripheral Mux Register 0 - Toggle */\r
+ RwReg GPIO_PMR1; /**< \brief (GpioPort Offset: 0x020) Peripheral Mux Register 1 */\r
+ WoReg GPIO_PMR1S; /**< \brief (GpioPort Offset: 0x024) Peripheral Mux Register 1 - Set */\r
+ WoReg GPIO_PMR1C; /**< \brief (GpioPort Offset: 0x028) Peripheral Mux Register 1 - Clear */\r
+ WoReg GPIO_PMR1T; /**< \brief (GpioPort Offset: 0x02C) Peripheral Mux Register 1 - Toggle */\r
+ RwReg GPIO_PMR2; /**< \brief (GpioPort Offset: 0x030) Peripheral Mux Register 2 */\r
+ WoReg GPIO_PMR2S; /**< \brief (GpioPort Offset: 0x034) Peripheral Mux Register 2 - Set */\r
+ WoReg GPIO_PMR2C; /**< \brief (GpioPort Offset: 0x038) Peripheral Mux Register 2 - Clear */\r
+ WoReg GPIO_PMR2T; /**< \brief (GpioPort Offset: 0x03C) Peripheral Mux Register 2 - Toggle */\r
+ RwReg GPIO_ODER; /**< \brief (GpioPort Offset: 0x040) Output Driver Enable Register */\r
+ WoReg GPIO_ODERS; /**< \brief (GpioPort Offset: 0x044) Output Driver Enable Register - Set */\r
+ WoReg GPIO_ODERC; /**< \brief (GpioPort Offset: 0x048) Output Driver Enable Register - Clear */\r
+ WoReg GPIO_ODERT; /**< \brief (GpioPort Offset: 0x04C) Output Driver Enable Register - Toggle */\r
+ RwReg GPIO_OVR; /**< \brief (GpioPort Offset: 0x050) Output Value Register */\r
+ WoReg GPIO_OVRS; /**< \brief (GpioPort Offset: 0x054) Output Value Register - Set */\r
+ WoReg GPIO_OVRC; /**< \brief (GpioPort Offset: 0x058) Output Value Register - Clear */\r
+ WoReg GPIO_OVRT; /**< \brief (GpioPort Offset: 0x05C) Output Value Register - Toggle */\r
+ RoReg GPIO_PVR; /**< \brief (GpioPort Offset: 0x060) Pin Value Register */\r
+ RoReg Reserved1[3];\r
+ RwReg GPIO_PUER; /**< \brief (GpioPort Offset: 0x070) Pull-up Enable Register */\r
+ WoReg GPIO_PUERS; /**< \brief (GpioPort Offset: 0x074) Pull-up Enable Register - Set */\r
+ WoReg GPIO_PUERC; /**< \brief (GpioPort Offset: 0x078) Pull-up Enable Register - Clear */\r
+ WoReg GPIO_PUERT; /**< \brief (GpioPort Offset: 0x07C) Pull-up Enable Register - Toggle */\r
+ RwReg GPIO_PDER; /**< \brief (GpioPort Offset: 0x080) Pull-down Enable Register */\r
+ WoReg GPIO_PDERS; /**< \brief (GpioPort Offset: 0x084) Pull-down Enable Register - Set */\r
+ WoReg GPIO_PDERC; /**< \brief (GpioPort Offset: 0x088) Pull-down Enable Register - Clear */\r
+ WoReg GPIO_PDERT; /**< \brief (GpioPort Offset: 0x08C) Pull-down Enable Register - Toggle */\r
+ RwReg GPIO_IER; /**< \brief (GpioPort Offset: 0x090) Interrupt Enable Register */\r
+ WoReg GPIO_IERS; /**< \brief (GpioPort Offset: 0x094) Interrupt Enable Register - Set */\r
+ WoReg GPIO_IERC; /**< \brief (GpioPort Offset: 0x098) Interrupt Enable Register - Clear */\r
+ WoReg GPIO_IERT; /**< \brief (GpioPort Offset: 0x09C) Interrupt Enable Register - Toggle */\r
+ RwReg GPIO_IMR0; /**< \brief (GpioPort Offset: 0x0A0) Interrupt Mode Register 0 */\r
+ WoReg GPIO_IMR0S; /**< \brief (GpioPort Offset: 0x0A4) Interrupt Mode Register 0 - Set */\r
+ WoReg GPIO_IMR0C; /**< \brief (GpioPort Offset: 0x0A8) Interrupt Mode Register 0 - Clear */\r
+ WoReg GPIO_IMR0T; /**< \brief (GpioPort Offset: 0x0AC) Interrupt Mode Register 0 - Toggle */\r
+ RwReg GPIO_IMR1; /**< \brief (GpioPort Offset: 0x0B0) Interrupt Mode Register 1 */\r
+ WoReg GPIO_IMR1S; /**< \brief (GpioPort Offset: 0x0B4) Interrupt Mode Register 1 - Set */\r
+ WoReg GPIO_IMR1C; /**< \brief (GpioPort Offset: 0x0B8) Interrupt Mode Register 1 - Clear */\r
+ WoReg GPIO_IMR1T; /**< \brief (GpioPort Offset: 0x0BC) Interrupt Mode Register 1 - Toggle */\r
+ RwReg GPIO_GFER; /**< \brief (GpioPort Offset: 0x0C0) Glitch Filter Enable Register */\r
+ WoReg GPIO_GFERS; /**< \brief (GpioPort Offset: 0x0C4) Glitch Filter Enable Register - Set */\r
+ WoReg GPIO_GFERC; /**< \brief (GpioPort Offset: 0x0C8) Glitch Filter Enable Register - Clear */\r
+ WoReg GPIO_GFERT; /**< \brief (GpioPort Offset: 0x0CC) Glitch Filter Enable Register - Toggle */\r
+ RoReg GPIO_IFR; /**< \brief (GpioPort Offset: 0x0D0) Interrupt Flag Register */\r
+ RoReg Reserved2[1];\r
+ WoReg GPIO_IFRC; /**< \brief (GpioPort Offset: 0x0D8) Interrupt Flag Register - Clear */\r
+ RoReg Reserved3[1];\r
+ RwReg GPIO_ODMER; /**< \brief (GpioPort Offset: 0x0E0) Open Drain Mode Register */\r
+ WoReg GPIO_ODMERS; /**< \brief (GpioPort Offset: 0x0E4) Open Drain Mode Register - Set */\r
+ WoReg GPIO_ODMERC; /**< \brief (GpioPort Offset: 0x0E8) Open Drain Mode Register - Clear */\r
+ WoReg GPIO_ODMERT; /**< \brief (GpioPort Offset: 0x0EC) Open Drain Mode Register - Toggle */\r
+ RoReg Reserved4[4];\r
+ RwReg GPIO_ODCR0; /**< \brief (GpioPort Offset: 0x100) Output Driving Capability Register 0 */\r
+ RwReg GPIO_ODCR0S; /**< \brief (GpioPort Offset: 0x104) Output Driving Capability Register 0 - Set */\r
+ RwReg GPIO_ODCR0C; /**< \brief (GpioPort Offset: 0x108) Output Driving Capability Register 0 - Clear */\r
+ RwReg GPIO_ODCR0T; /**< \brief (GpioPort Offset: 0x10C) Output Driving Capability Register 0 - Toggle */\r
+ RwReg GPIO_ODCR1; /**< \brief (GpioPort Offset: 0x110) Output Driving Capability Register 1 */\r
+ RwReg GPIO_ODCR1S; /**< \brief (GpioPort Offset: 0x114) Output Driving Capability Register 1 - Set */\r
+ RwReg GPIO_ODCR1C; /**< \brief (GpioPort Offset: 0x118) Output Driving Capability Register 1 - Clear */\r
+ RwReg GPIO_ODCR1T; /**< \brief (GpioPort Offset: 0x11C) Output Driving Capability Register 1 - Toggle */\r
+ RoReg Reserved5[4];\r
+ RwReg GPIO_OSRR0; /**< \brief (GpioPort Offset: 0x130) Output Slew Rate Register 0 */\r
+ RwReg GPIO_OSRR0S; /**< \brief (GpioPort Offset: 0x134) Output Slew Rate Register 0 - Set */\r
+ RwReg GPIO_OSRR0C; /**< \brief (GpioPort Offset: 0x138) Output Slew Rate Register 0 - Clear */\r
+ RwReg GPIO_OSRR0T; /**< \brief (GpioPort Offset: 0x13C) Output Slew Rate Register 0 - Toggle */\r
+ RoReg Reserved6[8];\r
+ RwReg GPIO_STER; /**< \brief (GpioPort Offset: 0x160) Schmitt Trigger Enable Register */\r
+ RwReg GPIO_STERS; /**< \brief (GpioPort Offset: 0x164) Schmitt Trigger Enable Register - Set */\r
+ RwReg GPIO_STERC; /**< \brief (GpioPort Offset: 0x168) Schmitt Trigger Enable Register - Clear */\r
+ RwReg GPIO_STERT; /**< \brief (GpioPort Offset: 0x16C) Schmitt Trigger Enable Register - Toggle */\r
+ RoReg Reserved7[4];\r
+ RwReg GPIO_EVER; /**< \brief (GpioPort Offset: 0x180) Event Enable Register */\r
+ WoReg GPIO_EVERS; /**< \brief (GpioPort Offset: 0x184) Event Enable Register - Set */\r
+ WoReg GPIO_EVERC; /**< \brief (GpioPort Offset: 0x188) Event Enable Register - Clear */\r
+ WoReg GPIO_EVERT; /**< \brief (GpioPort Offset: 0x18C) Event Enable Register - Toggle */\r
+ RoReg Reserved8[4];\r
+ RwReg GPIO_LOCK; /**< \brief (GpioPort Offset: 0x1A0) Lock Register */\r
+ WoReg GPIO_LOCKS; /**< \brief (GpioPort Offset: 0x1A4) Lock Register - Set */\r
+ WoReg GPIO_LOCKC; /**< \brief (GpioPort Offset: 0x1A8) Lock Register - Clear */\r
+ WoReg GPIO_LOCKT; /**< \brief (GpioPort Offset: 0x1AC) Lock Register - Toggle */\r
+ RoReg Reserved9[12];\r
+ WoReg GPIO_UNLOCK; /**< \brief (GpioPort Offset: 0x1E0) Unlock Register */\r
+ RwReg GPIO_ASR; /**< \brief (GpioPort Offset: 0x1E4) Access Status Register */\r
+ RoReg Reserved10[4];\r
+ RoReg GPIO_PARAMETER; /**< \brief (GpioPort Offset: 0x1F8) Parameter Register */\r
+ RoReg GPIO_VERSION; /**< \brief (GpioPort Offset: 0x1FC) Version Register */\r
+} GpioPort;\r
+/** \brief GPIO hardware registers */\r
+#define GPIO_PORT_LENGTH 3\r
+typedef struct {\r
+ GpioPort GPIO_PORT[GPIO_PORT_LENGTH]; /**< \brief (GPIO Offset: 0x000) GpioPort groups */\r
+ GpioPort Reserved1[64 - GPIO_PORT_LENGTH];\r
+} Gpio;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- GPIO_GPER : (GPIO Offset: 0x000) Port GPIO Enable Register -------- */\r
+#define GPIO_GPER_P0 (0x1u << 0) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P1 (0x1u << 1) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P2 (0x1u << 2) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P3 (0x1u << 3) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P4 (0x1u << 4) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P5 (0x1u << 5) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P6 (0x1u << 6) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P7 (0x1u << 7) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P8 (0x1u << 8) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P9 (0x1u << 9) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P10 (0x1u << 10) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P11 (0x1u << 11) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P12 (0x1u << 12) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P13 (0x1u << 13) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P14 (0x1u << 14) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P15 (0x1u << 15) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P16 (0x1u << 16) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P17 (0x1u << 17) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P18 (0x1u << 18) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P19 (0x1u << 19) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P20 (0x1u << 20) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P21 (0x1u << 21) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P22 (0x1u << 22) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P23 (0x1u << 23) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P24 (0x1u << 24) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P25 (0x1u << 25) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P26 (0x1u << 26) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P27 (0x1u << 27) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P28 (0x1u << 28) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P29 (0x1u << 29) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P30 (0x1u << 30) /**< \brief (GPIO_GPER) GPIO Enable */\r
+#define GPIO_GPER_P31 (0x1u << 31) /**< \brief (GPIO_GPER) GPIO Enable */\r
+/* -------- GPIO_GPERS : (GPIO Offset: 0x004) Port GPIO Enable Register - Set -------- */\r
+#define GPIO_GPERS_P0 (0x1u << 0) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P1 (0x1u << 1) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P2 (0x1u << 2) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P3 (0x1u << 3) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P4 (0x1u << 4) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P5 (0x1u << 5) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P6 (0x1u << 6) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P7 (0x1u << 7) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P8 (0x1u << 8) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P9 (0x1u << 9) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P10 (0x1u << 10) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P11 (0x1u << 11) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P12 (0x1u << 12) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P13 (0x1u << 13) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P14 (0x1u << 14) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P15 (0x1u << 15) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P16 (0x1u << 16) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P17 (0x1u << 17) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P18 (0x1u << 18) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P19 (0x1u << 19) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P20 (0x1u << 20) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P21 (0x1u << 21) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P22 (0x1u << 22) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P23 (0x1u << 23) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P24 (0x1u << 24) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P25 (0x1u << 25) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P26 (0x1u << 26) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P27 (0x1u << 27) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P28 (0x1u << 28) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P29 (0x1u << 29) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P30 (0x1u << 30) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+#define GPIO_GPERS_P31 (0x1u << 31) /**< \brief (GPIO_GPERS) GPIO Enable */\r
+/* -------- GPIO_GPERC : (GPIO Offset: 0x008) Port GPIO Enable Register - Clear -------- */\r
+#define GPIO_GPERC_P0 (0x1u << 0) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P1 (0x1u << 1) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P2 (0x1u << 2) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P3 (0x1u << 3) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P4 (0x1u << 4) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P5 (0x1u << 5) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P6 (0x1u << 6) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P7 (0x1u << 7) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P8 (0x1u << 8) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P9 (0x1u << 9) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P10 (0x1u << 10) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P11 (0x1u << 11) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P12 (0x1u << 12) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P13 (0x1u << 13) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P14 (0x1u << 14) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P15 (0x1u << 15) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P16 (0x1u << 16) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P17 (0x1u << 17) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P18 (0x1u << 18) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P19 (0x1u << 19) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P20 (0x1u << 20) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P21 (0x1u << 21) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P22 (0x1u << 22) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P23 (0x1u << 23) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P24 (0x1u << 24) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P25 (0x1u << 25) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P26 (0x1u << 26) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P27 (0x1u << 27) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P28 (0x1u << 28) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P29 (0x1u << 29) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P30 (0x1u << 30) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+#define GPIO_GPERC_P31 (0x1u << 31) /**< \brief (GPIO_GPERC) GPIO Enable */\r
+/* -------- GPIO_GPERT : (GPIO Offset: 0x00C) Port GPIO Enable Register - Toggle -------- */\r
+#define GPIO_GPERT_P0 (0x1u << 0) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P1 (0x1u << 1) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P2 (0x1u << 2) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P3 (0x1u << 3) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P4 (0x1u << 4) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P5 (0x1u << 5) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P6 (0x1u << 6) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P7 (0x1u << 7) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P8 (0x1u << 8) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P9 (0x1u << 9) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P10 (0x1u << 10) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P11 (0x1u << 11) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P12 (0x1u << 12) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P13 (0x1u << 13) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P14 (0x1u << 14) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P15 (0x1u << 15) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P16 (0x1u << 16) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P17 (0x1u << 17) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P18 (0x1u << 18) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P19 (0x1u << 19) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P20 (0x1u << 20) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P21 (0x1u << 21) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P22 (0x1u << 22) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P23 (0x1u << 23) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P24 (0x1u << 24) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P25 (0x1u << 25) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P26 (0x1u << 26) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P27 (0x1u << 27) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P28 (0x1u << 28) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P29 (0x1u << 29) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P30 (0x1u << 30) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+#define GPIO_GPERT_P31 (0x1u << 31) /**< \brief (GPIO_GPERT) GPIO Enable */\r
+/* -------- GPIO_PMR0 : (GPIO Offset: 0x010) Port Peripheral Mux Register 0 -------- */\r
+#define GPIO_PMR0_P0 (0x1u << 0) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P1 (0x1u << 1) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P2 (0x1u << 2) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P3 (0x1u << 3) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P4 (0x1u << 4) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P5 (0x1u << 5) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P6 (0x1u << 6) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P7 (0x1u << 7) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P8 (0x1u << 8) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P9 (0x1u << 9) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P10 (0x1u << 10) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P11 (0x1u << 11) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P12 (0x1u << 12) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P13 (0x1u << 13) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P14 (0x1u << 14) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P15 (0x1u << 15) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P16 (0x1u << 16) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P17 (0x1u << 17) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P18 (0x1u << 18) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P19 (0x1u << 19) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P20 (0x1u << 20) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P21 (0x1u << 21) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P22 (0x1u << 22) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P23 (0x1u << 23) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P24 (0x1u << 24) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P25 (0x1u << 25) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P26 (0x1u << 26) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P27 (0x1u << 27) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P28 (0x1u << 28) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P29 (0x1u << 29) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P30 (0x1u << 30) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0_P31 (0x1u << 31) /**< \brief (GPIO_PMR0) Peripheral Multiplexer Select bit 0 */\r
+/* -------- GPIO_PMR0S : (GPIO Offset: 0x014) Port Peripheral Mux Register 0 - Set -------- */\r
+#define GPIO_PMR0S_P0 (0x1u << 0) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P1 (0x1u << 1) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P2 (0x1u << 2) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P3 (0x1u << 3) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P4 (0x1u << 4) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P5 (0x1u << 5) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P6 (0x1u << 6) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P7 (0x1u << 7) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P8 (0x1u << 8) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P9 (0x1u << 9) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P10 (0x1u << 10) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P11 (0x1u << 11) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P12 (0x1u << 12) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P13 (0x1u << 13) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P14 (0x1u << 14) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P15 (0x1u << 15) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P16 (0x1u << 16) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P17 (0x1u << 17) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P18 (0x1u << 18) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P19 (0x1u << 19) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P20 (0x1u << 20) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P21 (0x1u << 21) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P22 (0x1u << 22) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P23 (0x1u << 23) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P24 (0x1u << 24) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P25 (0x1u << 25) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P26 (0x1u << 26) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P27 (0x1u << 27) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P28 (0x1u << 28) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P29 (0x1u << 29) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P30 (0x1u << 30) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0S_P31 (0x1u << 31) /**< \brief (GPIO_PMR0S) Peripheral Multiplexer Select bit 0 */\r
+/* -------- GPIO_PMR0C : (GPIO Offset: 0x018) Port Peripheral Mux Register 0 - Clear -------- */\r
+#define GPIO_PMR0C_P0 (0x1u << 0) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P1 (0x1u << 1) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P2 (0x1u << 2) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P3 (0x1u << 3) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P4 (0x1u << 4) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P5 (0x1u << 5) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P6 (0x1u << 6) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P7 (0x1u << 7) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P8 (0x1u << 8) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P9 (0x1u << 9) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P10 (0x1u << 10) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P11 (0x1u << 11) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P12 (0x1u << 12) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P13 (0x1u << 13) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P14 (0x1u << 14) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P15 (0x1u << 15) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P16 (0x1u << 16) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P17 (0x1u << 17) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P18 (0x1u << 18) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P19 (0x1u << 19) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P20 (0x1u << 20) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P21 (0x1u << 21) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P22 (0x1u << 22) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P23 (0x1u << 23) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P24 (0x1u << 24) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P25 (0x1u << 25) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P26 (0x1u << 26) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P27 (0x1u << 27) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P28 (0x1u << 28) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P29 (0x1u << 29) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P30 (0x1u << 30) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0C_P31 (0x1u << 31) /**< \brief (GPIO_PMR0C) Peripheral Multiplexer Select bit 0 */\r
+/* -------- GPIO_PMR0T : (GPIO Offset: 0x01C) Port Peripheral Mux Register 0 - Toggle -------- */\r
+#define GPIO_PMR0T_P0 (0x1u << 0) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P1 (0x1u << 1) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P2 (0x1u << 2) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P3 (0x1u << 3) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P4 (0x1u << 4) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P5 (0x1u << 5) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P6 (0x1u << 6) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P7 (0x1u << 7) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P8 (0x1u << 8) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P9 (0x1u << 9) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P10 (0x1u << 10) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P11 (0x1u << 11) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P12 (0x1u << 12) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P13 (0x1u << 13) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P14 (0x1u << 14) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P15 (0x1u << 15) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P16 (0x1u << 16) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P17 (0x1u << 17) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P18 (0x1u << 18) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P19 (0x1u << 19) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P20 (0x1u << 20) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P21 (0x1u << 21) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P22 (0x1u << 22) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P23 (0x1u << 23) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P24 (0x1u << 24) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P25 (0x1u << 25) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P26 (0x1u << 26) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P27 (0x1u << 27) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P28 (0x1u << 28) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P29 (0x1u << 29) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P30 (0x1u << 30) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+#define GPIO_PMR0T_P31 (0x1u << 31) /**< \brief (GPIO_PMR0T) Peripheral Multiplexer Select bit 0 */\r
+/* -------- GPIO_PMR1 : (GPIO Offset: 0x020) Port Peripheral Mux Register 1 -------- */\r
+#define GPIO_PMR1_P0 (0x1u << 0) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P1 (0x1u << 1) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P2 (0x1u << 2) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P3 (0x1u << 3) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P4 (0x1u << 4) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P5 (0x1u << 5) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P6 (0x1u << 6) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P7 (0x1u << 7) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P8 (0x1u << 8) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P9 (0x1u << 9) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P10 (0x1u << 10) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P11 (0x1u << 11) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P12 (0x1u << 12) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P13 (0x1u << 13) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P14 (0x1u << 14) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P15 (0x1u << 15) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P16 (0x1u << 16) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P17 (0x1u << 17) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P18 (0x1u << 18) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P19 (0x1u << 19) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P20 (0x1u << 20) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P21 (0x1u << 21) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P22 (0x1u << 22) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P23 (0x1u << 23) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P24 (0x1u << 24) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P25 (0x1u << 25) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P26 (0x1u << 26) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P27 (0x1u << 27) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P28 (0x1u << 28) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P29 (0x1u << 29) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P30 (0x1u << 30) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1_P31 (0x1u << 31) /**< \brief (GPIO_PMR1) Peripheral Multiplexer Select bit 1 */\r
+/* -------- GPIO_PMR1S : (GPIO Offset: 0x024) Port Peripheral Mux Register 1 - Set -------- */\r
+#define GPIO_PMR1S_P0 (0x1u << 0) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P1 (0x1u << 1) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P2 (0x1u << 2) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P3 (0x1u << 3) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P4 (0x1u << 4) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P5 (0x1u << 5) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P6 (0x1u << 6) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P7 (0x1u << 7) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P8 (0x1u << 8) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P9 (0x1u << 9) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P10 (0x1u << 10) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P11 (0x1u << 11) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P12 (0x1u << 12) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P13 (0x1u << 13) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P14 (0x1u << 14) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P15 (0x1u << 15) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P16 (0x1u << 16) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P17 (0x1u << 17) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P18 (0x1u << 18) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P19 (0x1u << 19) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P20 (0x1u << 20) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P21 (0x1u << 21) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P22 (0x1u << 22) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P23 (0x1u << 23) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P24 (0x1u << 24) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P25 (0x1u << 25) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P26 (0x1u << 26) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P27 (0x1u << 27) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P28 (0x1u << 28) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P29 (0x1u << 29) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P30 (0x1u << 30) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1S_P31 (0x1u << 31) /**< \brief (GPIO_PMR1S) Peripheral Multiplexer Select bit 1 */\r
+/* -------- GPIO_PMR1C : (GPIO Offset: 0x028) Port Peripheral Mux Register 1 - Clear -------- */\r
+#define GPIO_PMR1C_P0 (0x1u << 0) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P1 (0x1u << 1) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P2 (0x1u << 2) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P3 (0x1u << 3) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P4 (0x1u << 4) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P5 (0x1u << 5) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P6 (0x1u << 6) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P7 (0x1u << 7) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P8 (0x1u << 8) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P9 (0x1u << 9) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P10 (0x1u << 10) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P11 (0x1u << 11) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P12 (0x1u << 12) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P13 (0x1u << 13) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P14 (0x1u << 14) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P15 (0x1u << 15) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P16 (0x1u << 16) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P17 (0x1u << 17) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P18 (0x1u << 18) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P19 (0x1u << 19) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P20 (0x1u << 20) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P21 (0x1u << 21) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P22 (0x1u << 22) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P23 (0x1u << 23) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P24 (0x1u << 24) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P25 (0x1u << 25) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P26 (0x1u << 26) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P27 (0x1u << 27) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P28 (0x1u << 28) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P29 (0x1u << 29) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P30 (0x1u << 30) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1C_P31 (0x1u << 31) /**< \brief (GPIO_PMR1C) Peripheral Multiplexer Select bit 1 */\r
+/* -------- GPIO_PMR1T : (GPIO Offset: 0x02C) Port Peripheral Mux Register 1 - Toggle -------- */\r
+#define GPIO_PMR1T_P0 (0x1u << 0) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P1 (0x1u << 1) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P2 (0x1u << 2) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P3 (0x1u << 3) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P4 (0x1u << 4) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P5 (0x1u << 5) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P6 (0x1u << 6) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P7 (0x1u << 7) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P8 (0x1u << 8) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P9 (0x1u << 9) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P10 (0x1u << 10) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P11 (0x1u << 11) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P12 (0x1u << 12) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P13 (0x1u << 13) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P14 (0x1u << 14) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P15 (0x1u << 15) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P16 (0x1u << 16) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P17 (0x1u << 17) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P18 (0x1u << 18) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P19 (0x1u << 19) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P20 (0x1u << 20) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P21 (0x1u << 21) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P22 (0x1u << 22) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P23 (0x1u << 23) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P24 (0x1u << 24) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P25 (0x1u << 25) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P26 (0x1u << 26) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P27 (0x1u << 27) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P28 (0x1u << 28) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P29 (0x1u << 29) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P30 (0x1u << 30) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+#define GPIO_PMR1T_P31 (0x1u << 31) /**< \brief (GPIO_PMR1T) Peripheral Multiplexer Select bit 1 */\r
+/* -------- GPIO_PMR2 : (GPIO Offset: 0x030) Port Peripheral Mux Register 2 -------- */\r
+#define GPIO_PMR2_P0 (0x1u << 0) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P1 (0x1u << 1) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P2 (0x1u << 2) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P3 (0x1u << 3) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P4 (0x1u << 4) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P5 (0x1u << 5) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P6 (0x1u << 6) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P7 (0x1u << 7) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P8 (0x1u << 8) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P9 (0x1u << 9) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P10 (0x1u << 10) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P11 (0x1u << 11) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P12 (0x1u << 12) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P13 (0x1u << 13) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P14 (0x1u << 14) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P15 (0x1u << 15) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P16 (0x1u << 16) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P17 (0x1u << 17) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P18 (0x1u << 18) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P19 (0x1u << 19) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P20 (0x1u << 20) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P21 (0x1u << 21) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P22 (0x1u << 22) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P23 (0x1u << 23) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P24 (0x1u << 24) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P25 (0x1u << 25) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P26 (0x1u << 26) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P27 (0x1u << 27) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P28 (0x1u << 28) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P29 (0x1u << 29) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P30 (0x1u << 30) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2_P31 (0x1u << 31) /**< \brief (GPIO_PMR2) Peripheral Multiplexer Select bit 2 */\r
+/* -------- GPIO_PMR2S : (GPIO Offset: 0x034) Port Peripheral Mux Register 2 - Set -------- */\r
+#define GPIO_PMR2S_P0 (0x1u << 0) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P1 (0x1u << 1) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P2 (0x1u << 2) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P3 (0x1u << 3) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P4 (0x1u << 4) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P5 (0x1u << 5) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P6 (0x1u << 6) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P7 (0x1u << 7) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P8 (0x1u << 8) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P9 (0x1u << 9) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P10 (0x1u << 10) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P11 (0x1u << 11) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P12 (0x1u << 12) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P13 (0x1u << 13) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P14 (0x1u << 14) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P15 (0x1u << 15) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P16 (0x1u << 16) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P17 (0x1u << 17) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P18 (0x1u << 18) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P19 (0x1u << 19) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P20 (0x1u << 20) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P21 (0x1u << 21) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P22 (0x1u << 22) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P23 (0x1u << 23) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P24 (0x1u << 24) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P25 (0x1u << 25) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P26 (0x1u << 26) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P27 (0x1u << 27) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P28 (0x1u << 28) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P29 (0x1u << 29) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P30 (0x1u << 30) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2S_P31 (0x1u << 31) /**< \brief (GPIO_PMR2S) Peripheral Multiplexer Select bit 2 */\r
+/* -------- GPIO_PMR2C : (GPIO Offset: 0x038) Port Peripheral Mux Register 2 - Clear -------- */\r
+#define GPIO_PMR2C_P0 (0x1u << 0) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P1 (0x1u << 1) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P2 (0x1u << 2) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P3 (0x1u << 3) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P4 (0x1u << 4) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P5 (0x1u << 5) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P6 (0x1u << 6) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P7 (0x1u << 7) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P8 (0x1u << 8) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P9 (0x1u << 9) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P10 (0x1u << 10) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P11 (0x1u << 11) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P12 (0x1u << 12) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P13 (0x1u << 13) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P14 (0x1u << 14) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P15 (0x1u << 15) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P16 (0x1u << 16) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P17 (0x1u << 17) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P18 (0x1u << 18) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P19 (0x1u << 19) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P20 (0x1u << 20) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P21 (0x1u << 21) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P22 (0x1u << 22) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P23 (0x1u << 23) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P24 (0x1u << 24) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P25 (0x1u << 25) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P26 (0x1u << 26) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P27 (0x1u << 27) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P28 (0x1u << 28) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P29 (0x1u << 29) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P30 (0x1u << 30) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2C_P31 (0x1u << 31) /**< \brief (GPIO_PMR2C) Peripheral Multiplexer Select bit 2 */\r
+/* -------- GPIO_PMR2T : (GPIO Offset: 0x03C) Port Peripheral Mux Register 2 - Toggle -------- */\r
+#define GPIO_PMR2T_P0 (0x1u << 0) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P1 (0x1u << 1) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P2 (0x1u << 2) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P3 (0x1u << 3) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P4 (0x1u << 4) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P5 (0x1u << 5) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P6 (0x1u << 6) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P7 (0x1u << 7) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P8 (0x1u << 8) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P9 (0x1u << 9) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P10 (0x1u << 10) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P11 (0x1u << 11) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P12 (0x1u << 12) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P13 (0x1u << 13) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P14 (0x1u << 14) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P15 (0x1u << 15) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P16 (0x1u << 16) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P17 (0x1u << 17) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P18 (0x1u << 18) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P19 (0x1u << 19) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P20 (0x1u << 20) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P21 (0x1u << 21) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P22 (0x1u << 22) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P23 (0x1u << 23) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P24 (0x1u << 24) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P25 (0x1u << 25) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P26 (0x1u << 26) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P27 (0x1u << 27) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P28 (0x1u << 28) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P29 (0x1u << 29) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P30 (0x1u << 30) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+#define GPIO_PMR2T_P31 (0x1u << 31) /**< \brief (GPIO_PMR2T) Peripheral Multiplexer Select bit 2 */\r
+/* -------- GPIO_ODER : (GPIO Offset: 0x040) Port Output Driver Enable Register -------- */\r
+#define GPIO_ODER_P0 (0x1u << 0) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P1 (0x1u << 1) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P2 (0x1u << 2) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P3 (0x1u << 3) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P4 (0x1u << 4) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P5 (0x1u << 5) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P6 (0x1u << 6) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P7 (0x1u << 7) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P8 (0x1u << 8) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P9 (0x1u << 9) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P10 (0x1u << 10) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P11 (0x1u << 11) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P12 (0x1u << 12) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P13 (0x1u << 13) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P14 (0x1u << 14) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P15 (0x1u << 15) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P16 (0x1u << 16) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P17 (0x1u << 17) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P18 (0x1u << 18) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P19 (0x1u << 19) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P20 (0x1u << 20) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P21 (0x1u << 21) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P22 (0x1u << 22) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P23 (0x1u << 23) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P24 (0x1u << 24) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P25 (0x1u << 25) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P26 (0x1u << 26) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P27 (0x1u << 27) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P28 (0x1u << 28) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P29 (0x1u << 29) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P30 (0x1u << 30) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+#define GPIO_ODER_P31 (0x1u << 31) /**< \brief (GPIO_ODER) Output Driver Enable */\r
+/* -------- GPIO_ODERS : (GPIO Offset: 0x044) Port Output Driver Enable Register - Set -------- */\r
+#define GPIO_ODERS_P0 (0x1u << 0) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P1 (0x1u << 1) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P2 (0x1u << 2) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P3 (0x1u << 3) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P4 (0x1u << 4) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P5 (0x1u << 5) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P6 (0x1u << 6) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P7 (0x1u << 7) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P8 (0x1u << 8) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P9 (0x1u << 9) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P10 (0x1u << 10) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P11 (0x1u << 11) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P12 (0x1u << 12) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P13 (0x1u << 13) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P14 (0x1u << 14) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P15 (0x1u << 15) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P16 (0x1u << 16) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P17 (0x1u << 17) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P18 (0x1u << 18) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P19 (0x1u << 19) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P20 (0x1u << 20) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P21 (0x1u << 21) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P22 (0x1u << 22) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P23 (0x1u << 23) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P24 (0x1u << 24) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P25 (0x1u << 25) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P26 (0x1u << 26) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P27 (0x1u << 27) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P28 (0x1u << 28) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P29 (0x1u << 29) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P30 (0x1u << 30) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+#define GPIO_ODERS_P31 (0x1u << 31) /**< \brief (GPIO_ODERS) Output Driver Enable */\r
+/* -------- GPIO_ODERC : (GPIO Offset: 0x048) Port Output Driver Enable Register - Clear -------- */\r
+#define GPIO_ODERC_P0 (0x1u << 0) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P1 (0x1u << 1) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P2 (0x1u << 2) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P3 (0x1u << 3) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P4 (0x1u << 4) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P5 (0x1u << 5) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P6 (0x1u << 6) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P7 (0x1u << 7) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P8 (0x1u << 8) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P9 (0x1u << 9) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P10 (0x1u << 10) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P11 (0x1u << 11) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P12 (0x1u << 12) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P13 (0x1u << 13) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P14 (0x1u << 14) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P15 (0x1u << 15) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P16 (0x1u << 16) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P17 (0x1u << 17) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P18 (0x1u << 18) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P19 (0x1u << 19) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P20 (0x1u << 20) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P21 (0x1u << 21) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P22 (0x1u << 22) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P23 (0x1u << 23) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P24 (0x1u << 24) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P25 (0x1u << 25) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P26 (0x1u << 26) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P27 (0x1u << 27) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P28 (0x1u << 28) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P29 (0x1u << 29) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P30 (0x1u << 30) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+#define GPIO_ODERC_P31 (0x1u << 31) /**< \brief (GPIO_ODERC) Output Driver Enable */\r
+/* -------- GPIO_ODERT : (GPIO Offset: 0x04C) Port Output Driver Enable Register - Toggle -------- */\r
+#define GPIO_ODERT_P0 (0x1u << 0) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P1 (0x1u << 1) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P2 (0x1u << 2) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P3 (0x1u << 3) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P4 (0x1u << 4) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P5 (0x1u << 5) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P6 (0x1u << 6) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P7 (0x1u << 7) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P8 (0x1u << 8) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P9 (0x1u << 9) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P10 (0x1u << 10) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P11 (0x1u << 11) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P12 (0x1u << 12) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P13 (0x1u << 13) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P14 (0x1u << 14) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P15 (0x1u << 15) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P16 (0x1u << 16) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P17 (0x1u << 17) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P18 (0x1u << 18) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P19 (0x1u << 19) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P20 (0x1u << 20) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P21 (0x1u << 21) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P22 (0x1u << 22) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P23 (0x1u << 23) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P24 (0x1u << 24) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P25 (0x1u << 25) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P26 (0x1u << 26) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P27 (0x1u << 27) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P28 (0x1u << 28) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P29 (0x1u << 29) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P30 (0x1u << 30) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+#define GPIO_ODERT_P31 (0x1u << 31) /**< \brief (GPIO_ODERT) Output Driver Enable */\r
+/* -------- GPIO_OVR : (GPIO Offset: 0x050) Port Output Value Register -------- */\r
+#define GPIO_OVR_P0 (0x1u << 0) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P1 (0x1u << 1) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P2 (0x1u << 2) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P3 (0x1u << 3) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P4 (0x1u << 4) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P5 (0x1u << 5) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P6 (0x1u << 6) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P7 (0x1u << 7) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P8 (0x1u << 8) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P9 (0x1u << 9) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P10 (0x1u << 10) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P11 (0x1u << 11) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P12 (0x1u << 12) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P13 (0x1u << 13) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P14 (0x1u << 14) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P15 (0x1u << 15) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P16 (0x1u << 16) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P17 (0x1u << 17) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P18 (0x1u << 18) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P19 (0x1u << 19) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P20 (0x1u << 20) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P21 (0x1u << 21) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P22 (0x1u << 22) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P23 (0x1u << 23) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P24 (0x1u << 24) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P25 (0x1u << 25) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P26 (0x1u << 26) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P27 (0x1u << 27) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P28 (0x1u << 28) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P29 (0x1u << 29) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P30 (0x1u << 30) /**< \brief (GPIO_OVR) Output Value */\r
+#define GPIO_OVR_P31 (0x1u << 31) /**< \brief (GPIO_OVR) Output Value */\r
+/* -------- GPIO_OVRS : (GPIO Offset: 0x054) Port Output Value Register - Set -------- */\r
+#define GPIO_OVRS_P0 (0x1u << 0) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P1 (0x1u << 1) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P2 (0x1u << 2) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P3 (0x1u << 3) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P4 (0x1u << 4) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P5 (0x1u << 5) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P6 (0x1u << 6) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P7 (0x1u << 7) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P8 (0x1u << 8) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P9 (0x1u << 9) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P10 (0x1u << 10) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P11 (0x1u << 11) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P12 (0x1u << 12) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P13 (0x1u << 13) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P14 (0x1u << 14) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P15 (0x1u << 15) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P16 (0x1u << 16) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P17 (0x1u << 17) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P18 (0x1u << 18) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P19 (0x1u << 19) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P20 (0x1u << 20) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P21 (0x1u << 21) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P22 (0x1u << 22) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P23 (0x1u << 23) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P24 (0x1u << 24) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P25 (0x1u << 25) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P26 (0x1u << 26) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P27 (0x1u << 27) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P28 (0x1u << 28) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P29 (0x1u << 29) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P30 (0x1u << 30) /**< \brief (GPIO_OVRS) Output Value */\r
+#define GPIO_OVRS_P31 (0x1u << 31) /**< \brief (GPIO_OVRS) Output Value */\r
+/* -------- GPIO_OVRC : (GPIO Offset: 0x058) Port Output Value Register - Clear -------- */\r
+#define GPIO_OVRC_P0 (0x1u << 0) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P1 (0x1u << 1) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P2 (0x1u << 2) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P3 (0x1u << 3) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P4 (0x1u << 4) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P5 (0x1u << 5) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P6 (0x1u << 6) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P7 (0x1u << 7) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P8 (0x1u << 8) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P9 (0x1u << 9) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P10 (0x1u << 10) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P11 (0x1u << 11) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P12 (0x1u << 12) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P13 (0x1u << 13) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P14 (0x1u << 14) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P15 (0x1u << 15) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P16 (0x1u << 16) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P17 (0x1u << 17) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P18 (0x1u << 18) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P19 (0x1u << 19) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P20 (0x1u << 20) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P21 (0x1u << 21) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P22 (0x1u << 22) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P23 (0x1u << 23) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P24 (0x1u << 24) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P25 (0x1u << 25) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P26 (0x1u << 26) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P27 (0x1u << 27) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P28 (0x1u << 28) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P29 (0x1u << 29) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P30 (0x1u << 30) /**< \brief (GPIO_OVRC) Output Value */\r
+#define GPIO_OVRC_P31 (0x1u << 31) /**< \brief (GPIO_OVRC) Output Value */\r
+/* -------- GPIO_OVRT : (GPIO Offset: 0x05C) Port Output Value Register - Toggle -------- */\r
+#define GPIO_OVRT_P0 (0x1u << 0) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P1 (0x1u << 1) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P2 (0x1u << 2) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P3 (0x1u << 3) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P4 (0x1u << 4) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P5 (0x1u << 5) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P6 (0x1u << 6) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P7 (0x1u << 7) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P8 (0x1u << 8) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P9 (0x1u << 9) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P10 (0x1u << 10) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P11 (0x1u << 11) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P12 (0x1u << 12) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P13 (0x1u << 13) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P14 (0x1u << 14) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P15 (0x1u << 15) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P16 (0x1u << 16) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P17 (0x1u << 17) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P18 (0x1u << 18) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P19 (0x1u << 19) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P20 (0x1u << 20) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P21 (0x1u << 21) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P22 (0x1u << 22) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P23 (0x1u << 23) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P24 (0x1u << 24) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P25 (0x1u << 25) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P26 (0x1u << 26) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P27 (0x1u << 27) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P28 (0x1u << 28) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P29 (0x1u << 29) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P30 (0x1u << 30) /**< \brief (GPIO_OVRT) Output Value */\r
+#define GPIO_OVRT_P31 (0x1u << 31) /**< \brief (GPIO_OVRT) Output Value */\r
+/* -------- GPIO_PVR : (GPIO Offset: 0x060) Port Pin Value Register -------- */\r
+#define GPIO_PVR_P0 (0x1u << 0) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P1 (0x1u << 1) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P2 (0x1u << 2) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P3 (0x1u << 3) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P4 (0x1u << 4) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P5 (0x1u << 5) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P6 (0x1u << 6) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P7 (0x1u << 7) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P8 (0x1u << 8) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P9 (0x1u << 9) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P10 (0x1u << 10) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P11 (0x1u << 11) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P12 (0x1u << 12) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P13 (0x1u << 13) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P14 (0x1u << 14) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P15 (0x1u << 15) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P16 (0x1u << 16) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P17 (0x1u << 17) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P18 (0x1u << 18) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P19 (0x1u << 19) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P20 (0x1u << 20) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P21 (0x1u << 21) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P22 (0x1u << 22) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P23 (0x1u << 23) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P24 (0x1u << 24) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P25 (0x1u << 25) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P26 (0x1u << 26) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P27 (0x1u << 27) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P28 (0x1u << 28) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P29 (0x1u << 29) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P30 (0x1u << 30) /**< \brief (GPIO_PVR) Pin Value */\r
+#define GPIO_PVR_P31 (0x1u << 31) /**< \brief (GPIO_PVR) Pin Value */\r
+/* -------- GPIO_PUER : (GPIO Offset: 0x070) Port Pull-up Enable Register -------- */\r
+#define GPIO_PUER_P0 (0x1u << 0) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P1 (0x1u << 1) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P2 (0x1u << 2) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P3 (0x1u << 3) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P4 (0x1u << 4) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P5 (0x1u << 5) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P6 (0x1u << 6) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P7 (0x1u << 7) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P8 (0x1u << 8) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P9 (0x1u << 9) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P10 (0x1u << 10) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P11 (0x1u << 11) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P12 (0x1u << 12) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P13 (0x1u << 13) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P14 (0x1u << 14) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P15 (0x1u << 15) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P16 (0x1u << 16) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P17 (0x1u << 17) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P18 (0x1u << 18) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P19 (0x1u << 19) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P20 (0x1u << 20) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P21 (0x1u << 21) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P22 (0x1u << 22) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P23 (0x1u << 23) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P24 (0x1u << 24) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P25 (0x1u << 25) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P26 (0x1u << 26) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P27 (0x1u << 27) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P28 (0x1u << 28) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P29 (0x1u << 29) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P30 (0x1u << 30) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+#define GPIO_PUER_P31 (0x1u << 31) /**< \brief (GPIO_PUER) Pull-up Enable */\r
+/* -------- GPIO_PUERS : (GPIO Offset: 0x074) Port Pull-up Enable Register - Set -------- */\r
+#define GPIO_PUERS_P0 (0x1u << 0) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P1 (0x1u << 1) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P2 (0x1u << 2) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P3 (0x1u << 3) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P4 (0x1u << 4) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P5 (0x1u << 5) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P6 (0x1u << 6) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P7 (0x1u << 7) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P8 (0x1u << 8) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P9 (0x1u << 9) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P10 (0x1u << 10) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P11 (0x1u << 11) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P12 (0x1u << 12) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P13 (0x1u << 13) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P14 (0x1u << 14) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P15 (0x1u << 15) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P16 (0x1u << 16) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P17 (0x1u << 17) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P18 (0x1u << 18) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P19 (0x1u << 19) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P20 (0x1u << 20) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P21 (0x1u << 21) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P22 (0x1u << 22) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P23 (0x1u << 23) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P24 (0x1u << 24) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P25 (0x1u << 25) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P26 (0x1u << 26) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P27 (0x1u << 27) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P28 (0x1u << 28) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P29 (0x1u << 29) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P30 (0x1u << 30) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+#define GPIO_PUERS_P31 (0x1u << 31) /**< \brief (GPIO_PUERS) Pull-up Enable */\r
+/* -------- GPIO_PUERC : (GPIO Offset: 0x078) Port Pull-up Enable Register - Clear -------- */\r
+#define GPIO_PUERC_P0 (0x1u << 0) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P1 (0x1u << 1) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P2 (0x1u << 2) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P3 (0x1u << 3) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P4 (0x1u << 4) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P5 (0x1u << 5) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P6 (0x1u << 6) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P7 (0x1u << 7) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P8 (0x1u << 8) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P9 (0x1u << 9) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P10 (0x1u << 10) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P11 (0x1u << 11) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P12 (0x1u << 12) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P13 (0x1u << 13) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P14 (0x1u << 14) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P15 (0x1u << 15) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P16 (0x1u << 16) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P17 (0x1u << 17) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P18 (0x1u << 18) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P19 (0x1u << 19) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P20 (0x1u << 20) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P21 (0x1u << 21) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P22 (0x1u << 22) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P23 (0x1u << 23) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P24 (0x1u << 24) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P25 (0x1u << 25) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P26 (0x1u << 26) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P27 (0x1u << 27) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P28 (0x1u << 28) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P29 (0x1u << 29) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P30 (0x1u << 30) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+#define GPIO_PUERC_P31 (0x1u << 31) /**< \brief (GPIO_PUERC) Pull-up Enable */\r
+/* -------- GPIO_PUERT : (GPIO Offset: 0x07C) Port Pull-up Enable Register - Toggle -------- */\r
+#define GPIO_PUERT_P0 (0x1u << 0) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P1 (0x1u << 1) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P2 (0x1u << 2) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P3 (0x1u << 3) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P4 (0x1u << 4) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P5 (0x1u << 5) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P6 (0x1u << 6) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P7 (0x1u << 7) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P8 (0x1u << 8) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P9 (0x1u << 9) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P10 (0x1u << 10) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P11 (0x1u << 11) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P12 (0x1u << 12) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P13 (0x1u << 13) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P14 (0x1u << 14) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P15 (0x1u << 15) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P16 (0x1u << 16) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P17 (0x1u << 17) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P18 (0x1u << 18) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P19 (0x1u << 19) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P20 (0x1u << 20) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P21 (0x1u << 21) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P22 (0x1u << 22) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P23 (0x1u << 23) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P24 (0x1u << 24) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P25 (0x1u << 25) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P26 (0x1u << 26) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P27 (0x1u << 27) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P28 (0x1u << 28) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P29 (0x1u << 29) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P30 (0x1u << 30) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+#define GPIO_PUERT_P31 (0x1u << 31) /**< \brief (GPIO_PUERT) Pull-up Enable */\r
+/* -------- GPIO_PDER : (GPIO Offset: 0x080) Port Pull-down Enable Register -------- */\r
+#define GPIO_PDER_P0 (0x1u << 0) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P1 (0x1u << 1) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P2 (0x1u << 2) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P3 (0x1u << 3) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P4 (0x1u << 4) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P5 (0x1u << 5) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P6 (0x1u << 6) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P7 (0x1u << 7) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P8 (0x1u << 8) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P9 (0x1u << 9) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P10 (0x1u << 10) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P11 (0x1u << 11) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P12 (0x1u << 12) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P13 (0x1u << 13) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P14 (0x1u << 14) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P15 (0x1u << 15) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P16 (0x1u << 16) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P17 (0x1u << 17) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P18 (0x1u << 18) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P19 (0x1u << 19) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P20 (0x1u << 20) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P21 (0x1u << 21) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P22 (0x1u << 22) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P23 (0x1u << 23) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P24 (0x1u << 24) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P25 (0x1u << 25) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P26 (0x1u << 26) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P27 (0x1u << 27) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P28 (0x1u << 28) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P29 (0x1u << 29) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P30 (0x1u << 30) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+#define GPIO_PDER_P31 (0x1u << 31) /**< \brief (GPIO_PDER) Pull-down Enable */\r
+/* -------- GPIO_PDERS : (GPIO Offset: 0x084) Port Pull-down Enable Register - Set -------- */\r
+#define GPIO_PDERS_P0 (0x1u << 0) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P1 (0x1u << 1) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P2 (0x1u << 2) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P3 (0x1u << 3) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P4 (0x1u << 4) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P5 (0x1u << 5) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P6 (0x1u << 6) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P7 (0x1u << 7) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P8 (0x1u << 8) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P9 (0x1u << 9) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P10 (0x1u << 10) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P11 (0x1u << 11) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P12 (0x1u << 12) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P13 (0x1u << 13) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P14 (0x1u << 14) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P15 (0x1u << 15) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P16 (0x1u << 16) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P17 (0x1u << 17) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P18 (0x1u << 18) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P19 (0x1u << 19) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P20 (0x1u << 20) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P21 (0x1u << 21) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P22 (0x1u << 22) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P23 (0x1u << 23) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P24 (0x1u << 24) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P25 (0x1u << 25) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P26 (0x1u << 26) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P27 (0x1u << 27) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P28 (0x1u << 28) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P29 (0x1u << 29) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P30 (0x1u << 30) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+#define GPIO_PDERS_P31 (0x1u << 31) /**< \brief (GPIO_PDERS) Pull-down Enable */\r
+/* -------- GPIO_PDERC : (GPIO Offset: 0x088) Port Pull-down Enable Register - Clear -------- */\r
+#define GPIO_PDERC_P0 (0x1u << 0) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P1 (0x1u << 1) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P2 (0x1u << 2) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P3 (0x1u << 3) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P4 (0x1u << 4) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P5 (0x1u << 5) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P6 (0x1u << 6) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P7 (0x1u << 7) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P8 (0x1u << 8) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P9 (0x1u << 9) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P10 (0x1u << 10) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P11 (0x1u << 11) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P12 (0x1u << 12) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P13 (0x1u << 13) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P14 (0x1u << 14) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P15 (0x1u << 15) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P16 (0x1u << 16) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P17 (0x1u << 17) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P18 (0x1u << 18) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P19 (0x1u << 19) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P20 (0x1u << 20) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P21 (0x1u << 21) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P22 (0x1u << 22) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P23 (0x1u << 23) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P24 (0x1u << 24) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P25 (0x1u << 25) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P26 (0x1u << 26) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P27 (0x1u << 27) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P28 (0x1u << 28) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P29 (0x1u << 29) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P30 (0x1u << 30) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+#define GPIO_PDERC_P31 (0x1u << 31) /**< \brief (GPIO_PDERC) Pull-down Enable */\r
+/* -------- GPIO_PDERT : (GPIO Offset: 0x08C) Port Pull-down Enable Register - Toggle -------- */\r
+#define GPIO_PDERT_P0 (0x1u << 0) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P1 (0x1u << 1) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P2 (0x1u << 2) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P3 (0x1u << 3) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P4 (0x1u << 4) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P5 (0x1u << 5) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P6 (0x1u << 6) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P7 (0x1u << 7) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P8 (0x1u << 8) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P9 (0x1u << 9) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P10 (0x1u << 10) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P11 (0x1u << 11) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P12 (0x1u << 12) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P13 (0x1u << 13) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P14 (0x1u << 14) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P15 (0x1u << 15) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P16 (0x1u << 16) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P17 (0x1u << 17) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P18 (0x1u << 18) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P19 (0x1u << 19) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P20 (0x1u << 20) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P21 (0x1u << 21) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P22 (0x1u << 22) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P23 (0x1u << 23) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P24 (0x1u << 24) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P25 (0x1u << 25) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P26 (0x1u << 26) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P27 (0x1u << 27) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P28 (0x1u << 28) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P29 (0x1u << 29) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P30 (0x1u << 30) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+#define GPIO_PDERT_P31 (0x1u << 31) /**< \brief (GPIO_PDERT) Pull-down Enable */\r
+/* -------- GPIO_IER : (GPIO Offset: 0x090) Port Interrupt Enable Register -------- */\r
+#define GPIO_IER_P0 (0x1u << 0) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P1 (0x1u << 1) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P2 (0x1u << 2) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P3 (0x1u << 3) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P4 (0x1u << 4) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P5 (0x1u << 5) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P6 (0x1u << 6) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P7 (0x1u << 7) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P8 (0x1u << 8) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P9 (0x1u << 9) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P10 (0x1u << 10) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P11 (0x1u << 11) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P12 (0x1u << 12) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P13 (0x1u << 13) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P14 (0x1u << 14) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P15 (0x1u << 15) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P16 (0x1u << 16) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P17 (0x1u << 17) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P18 (0x1u << 18) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P19 (0x1u << 19) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P20 (0x1u << 20) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P21 (0x1u << 21) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P22 (0x1u << 22) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P23 (0x1u << 23) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P24 (0x1u << 24) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P25 (0x1u << 25) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P26 (0x1u << 26) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P27 (0x1u << 27) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P28 (0x1u << 28) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P29 (0x1u << 29) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P30 (0x1u << 30) /**< \brief (GPIO_IER) Interrupt Enable */\r
+#define GPIO_IER_P31 (0x1u << 31) /**< \brief (GPIO_IER) Interrupt Enable */\r
+/* -------- GPIO_IERS : (GPIO Offset: 0x094) Port Interrupt Enable Register - Set -------- */\r
+#define GPIO_IERS_P0 (0x1u << 0) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P1 (0x1u << 1) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P2 (0x1u << 2) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P3 (0x1u << 3) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P4 (0x1u << 4) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P5 (0x1u << 5) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P6 (0x1u << 6) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P7 (0x1u << 7) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P8 (0x1u << 8) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P9 (0x1u << 9) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P10 (0x1u << 10) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P11 (0x1u << 11) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P12 (0x1u << 12) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P13 (0x1u << 13) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P14 (0x1u << 14) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P15 (0x1u << 15) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P16 (0x1u << 16) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P17 (0x1u << 17) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P18 (0x1u << 18) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P19 (0x1u << 19) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P20 (0x1u << 20) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P21 (0x1u << 21) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P22 (0x1u << 22) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P23 (0x1u << 23) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P24 (0x1u << 24) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P25 (0x1u << 25) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P26 (0x1u << 26) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P27 (0x1u << 27) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P28 (0x1u << 28) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P29 (0x1u << 29) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P30 (0x1u << 30) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+#define GPIO_IERS_P31 (0x1u << 31) /**< \brief (GPIO_IERS) Interrupt Enable */\r
+/* -------- GPIO_IERC : (GPIO Offset: 0x098) Port Interrupt Enable Register - Clear -------- */\r
+#define GPIO_IERC_P0 (0x1u << 0) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P1 (0x1u << 1) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P2 (0x1u << 2) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P3 (0x1u << 3) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P4 (0x1u << 4) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P5 (0x1u << 5) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P6 (0x1u << 6) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P7 (0x1u << 7) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P8 (0x1u << 8) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P9 (0x1u << 9) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P10 (0x1u << 10) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P11 (0x1u << 11) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P12 (0x1u << 12) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P13 (0x1u << 13) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P14 (0x1u << 14) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P15 (0x1u << 15) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P16 (0x1u << 16) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P17 (0x1u << 17) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P18 (0x1u << 18) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P19 (0x1u << 19) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P20 (0x1u << 20) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P21 (0x1u << 21) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P22 (0x1u << 22) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P23 (0x1u << 23) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P24 (0x1u << 24) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P25 (0x1u << 25) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P26 (0x1u << 26) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P27 (0x1u << 27) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P28 (0x1u << 28) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P29 (0x1u << 29) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P30 (0x1u << 30) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+#define GPIO_IERC_P31 (0x1u << 31) /**< \brief (GPIO_IERC) Interrupt Enable */\r
+/* -------- GPIO_IERT : (GPIO Offset: 0x09C) Port Interrupt Enable Register - Toggle -------- */\r
+#define GPIO_IERT_P0 (0x1u << 0) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P1 (0x1u << 1) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P2 (0x1u << 2) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P3 (0x1u << 3) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P4 (0x1u << 4) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P5 (0x1u << 5) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P6 (0x1u << 6) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P7 (0x1u << 7) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P8 (0x1u << 8) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P9 (0x1u << 9) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P10 (0x1u << 10) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P11 (0x1u << 11) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P12 (0x1u << 12) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P13 (0x1u << 13) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P14 (0x1u << 14) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P15 (0x1u << 15) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P16 (0x1u << 16) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P17 (0x1u << 17) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P18 (0x1u << 18) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P19 (0x1u << 19) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P20 (0x1u << 20) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P21 (0x1u << 21) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P22 (0x1u << 22) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P23 (0x1u << 23) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P24 (0x1u << 24) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P25 (0x1u << 25) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P26 (0x1u << 26) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P27 (0x1u << 27) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P28 (0x1u << 28) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P29 (0x1u << 29) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P30 (0x1u << 30) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+#define GPIO_IERT_P31 (0x1u << 31) /**< \brief (GPIO_IERT) Interrupt Enable */\r
+/* -------- GPIO_IMR0 : (GPIO Offset: 0x0A0) Port Interrupt Mode Register 0 -------- */\r
+#define GPIO_IMR0_P0 (0x1u << 0) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P1 (0x1u << 1) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P2 (0x1u << 2) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P3 (0x1u << 3) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P4 (0x1u << 4) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P5 (0x1u << 5) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P6 (0x1u << 6) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P7 (0x1u << 7) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P8 (0x1u << 8) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P9 (0x1u << 9) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P10 (0x1u << 10) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P11 (0x1u << 11) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P12 (0x1u << 12) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P13 (0x1u << 13) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P14 (0x1u << 14) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P15 (0x1u << 15) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P16 (0x1u << 16) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P17 (0x1u << 17) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P18 (0x1u << 18) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P19 (0x1u << 19) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P20 (0x1u << 20) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P21 (0x1u << 21) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P22 (0x1u << 22) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P23 (0x1u << 23) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P24 (0x1u << 24) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P25 (0x1u << 25) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P26 (0x1u << 26) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P27 (0x1u << 27) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P28 (0x1u << 28) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P29 (0x1u << 29) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P30 (0x1u << 30) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0_P31 (0x1u << 31) /**< \brief (GPIO_IMR0) Interrupt Mode Bit 0 */\r
+/* -------- GPIO_IMR0S : (GPIO Offset: 0x0A4) Port Interrupt Mode Register 0 - Set -------- */\r
+#define GPIO_IMR0S_P0 (0x1u << 0) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P1 (0x1u << 1) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P2 (0x1u << 2) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P3 (0x1u << 3) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P4 (0x1u << 4) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P5 (0x1u << 5) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P6 (0x1u << 6) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P7 (0x1u << 7) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P8 (0x1u << 8) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P9 (0x1u << 9) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P10 (0x1u << 10) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P11 (0x1u << 11) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P12 (0x1u << 12) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P13 (0x1u << 13) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P14 (0x1u << 14) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P15 (0x1u << 15) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P16 (0x1u << 16) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P17 (0x1u << 17) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P18 (0x1u << 18) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P19 (0x1u << 19) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P20 (0x1u << 20) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P21 (0x1u << 21) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P22 (0x1u << 22) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P23 (0x1u << 23) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P24 (0x1u << 24) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P25 (0x1u << 25) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P26 (0x1u << 26) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P27 (0x1u << 27) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P28 (0x1u << 28) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P29 (0x1u << 29) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P30 (0x1u << 30) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0S_P31 (0x1u << 31) /**< \brief (GPIO_IMR0S) Interrupt Mode Bit 0 */\r
+/* -------- GPIO_IMR0C : (GPIO Offset: 0x0A8) Port Interrupt Mode Register 0 - Clear -------- */\r
+#define GPIO_IMR0C_P0 (0x1u << 0) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P1 (0x1u << 1) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P2 (0x1u << 2) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P3 (0x1u << 3) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P4 (0x1u << 4) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P5 (0x1u << 5) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P6 (0x1u << 6) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P7 (0x1u << 7) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P8 (0x1u << 8) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P9 (0x1u << 9) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P10 (0x1u << 10) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P11 (0x1u << 11) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P12 (0x1u << 12) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P13 (0x1u << 13) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P14 (0x1u << 14) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P15 (0x1u << 15) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P16 (0x1u << 16) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P17 (0x1u << 17) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P18 (0x1u << 18) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P19 (0x1u << 19) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P20 (0x1u << 20) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P21 (0x1u << 21) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P22 (0x1u << 22) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P23 (0x1u << 23) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P24 (0x1u << 24) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P25 (0x1u << 25) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P26 (0x1u << 26) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P27 (0x1u << 27) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P28 (0x1u << 28) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P29 (0x1u << 29) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P30 (0x1u << 30) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0C_P31 (0x1u << 31) /**< \brief (GPIO_IMR0C) Interrupt Mode Bit 0 */\r
+/* -------- GPIO_IMR0T : (GPIO Offset: 0x0AC) Port Interrupt Mode Register 0 - Toggle -------- */\r
+#define GPIO_IMR0T_P0 (0x1u << 0) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P1 (0x1u << 1) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P2 (0x1u << 2) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P3 (0x1u << 3) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P4 (0x1u << 4) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P5 (0x1u << 5) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P6 (0x1u << 6) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P7 (0x1u << 7) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P8 (0x1u << 8) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P9 (0x1u << 9) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P10 (0x1u << 10) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P11 (0x1u << 11) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P12 (0x1u << 12) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P13 (0x1u << 13) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P14 (0x1u << 14) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P15 (0x1u << 15) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P16 (0x1u << 16) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P17 (0x1u << 17) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P18 (0x1u << 18) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P19 (0x1u << 19) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P20 (0x1u << 20) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P21 (0x1u << 21) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P22 (0x1u << 22) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P23 (0x1u << 23) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P24 (0x1u << 24) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P25 (0x1u << 25) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P26 (0x1u << 26) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P27 (0x1u << 27) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P28 (0x1u << 28) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P29 (0x1u << 29) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P30 (0x1u << 30) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+#define GPIO_IMR0T_P31 (0x1u << 31) /**< \brief (GPIO_IMR0T) Interrupt Mode Bit 0 */\r
+/* -------- GPIO_IMR1 : (GPIO Offset: 0x0B0) Port Interrupt Mode Register 1 -------- */\r
+#define GPIO_IMR1_P0 (0x1u << 0) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P1 (0x1u << 1) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P2 (0x1u << 2) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P3 (0x1u << 3) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P4 (0x1u << 4) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P5 (0x1u << 5) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P6 (0x1u << 6) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P7 (0x1u << 7) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P8 (0x1u << 8) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P9 (0x1u << 9) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P10 (0x1u << 10) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P11 (0x1u << 11) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P12 (0x1u << 12) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P13 (0x1u << 13) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P14 (0x1u << 14) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P15 (0x1u << 15) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P16 (0x1u << 16) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P17 (0x1u << 17) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P18 (0x1u << 18) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P19 (0x1u << 19) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P20 (0x1u << 20) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P21 (0x1u << 21) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P22 (0x1u << 22) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P23 (0x1u << 23) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P24 (0x1u << 24) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P25 (0x1u << 25) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P26 (0x1u << 26) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P27 (0x1u << 27) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P28 (0x1u << 28) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P29 (0x1u << 29) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P30 (0x1u << 30) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1_P31 (0x1u << 31) /**< \brief (GPIO_IMR1) Interrupt Mode Bit 1 */\r
+/* -------- GPIO_IMR1S : (GPIO Offset: 0x0B4) Port Interrupt Mode Register 1 - Set -------- */\r
+#define GPIO_IMR1S_P0 (0x1u << 0) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P1 (0x1u << 1) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P2 (0x1u << 2) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P3 (0x1u << 3) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P4 (0x1u << 4) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P5 (0x1u << 5) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P6 (0x1u << 6) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P7 (0x1u << 7) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P8 (0x1u << 8) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P9 (0x1u << 9) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P10 (0x1u << 10) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P11 (0x1u << 11) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P12 (0x1u << 12) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P13 (0x1u << 13) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P14 (0x1u << 14) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P15 (0x1u << 15) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P16 (0x1u << 16) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P17 (0x1u << 17) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P18 (0x1u << 18) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P19 (0x1u << 19) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P20 (0x1u << 20) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P21 (0x1u << 21) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P22 (0x1u << 22) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P23 (0x1u << 23) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P24 (0x1u << 24) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P25 (0x1u << 25) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P26 (0x1u << 26) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P27 (0x1u << 27) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P28 (0x1u << 28) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P29 (0x1u << 29) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P30 (0x1u << 30) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1S_P31 (0x1u << 31) /**< \brief (GPIO_IMR1S) Interrupt Mode Bit 1 */\r
+/* -------- GPIO_IMR1C : (GPIO Offset: 0x0B8) Port Interrupt Mode Register 1 - Clear -------- */\r
+#define GPIO_IMR1C_P0 (0x1u << 0) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P1 (0x1u << 1) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P2 (0x1u << 2) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P3 (0x1u << 3) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P4 (0x1u << 4) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P5 (0x1u << 5) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P6 (0x1u << 6) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P7 (0x1u << 7) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P8 (0x1u << 8) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P9 (0x1u << 9) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P10 (0x1u << 10) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P11 (0x1u << 11) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P12 (0x1u << 12) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P13 (0x1u << 13) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P14 (0x1u << 14) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P15 (0x1u << 15) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P16 (0x1u << 16) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P17 (0x1u << 17) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P18 (0x1u << 18) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P19 (0x1u << 19) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P20 (0x1u << 20) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P21 (0x1u << 21) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P22 (0x1u << 22) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P23 (0x1u << 23) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P24 (0x1u << 24) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P25 (0x1u << 25) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P26 (0x1u << 26) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P27 (0x1u << 27) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P28 (0x1u << 28) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P29 (0x1u << 29) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P30 (0x1u << 30) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1C_P31 (0x1u << 31) /**< \brief (GPIO_IMR1C) Interrupt Mode Bit 1 */\r
+/* -------- GPIO_IMR1T : (GPIO Offset: 0x0BC) Port Interrupt Mode Register 1 - Toggle -------- */\r
+#define GPIO_IMR1T_P0 (0x1u << 0) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P1 (0x1u << 1) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P2 (0x1u << 2) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P3 (0x1u << 3) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P4 (0x1u << 4) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P5 (0x1u << 5) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P6 (0x1u << 6) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P7 (0x1u << 7) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P8 (0x1u << 8) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P9 (0x1u << 9) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P10 (0x1u << 10) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P11 (0x1u << 11) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P12 (0x1u << 12) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P13 (0x1u << 13) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P14 (0x1u << 14) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P15 (0x1u << 15) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P16 (0x1u << 16) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P17 (0x1u << 17) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P18 (0x1u << 18) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P19 (0x1u << 19) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P20 (0x1u << 20) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P21 (0x1u << 21) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P22 (0x1u << 22) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P23 (0x1u << 23) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P24 (0x1u << 24) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P25 (0x1u << 25) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P26 (0x1u << 26) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P27 (0x1u << 27) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P28 (0x1u << 28) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P29 (0x1u << 29) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P30 (0x1u << 30) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+#define GPIO_IMR1T_P31 (0x1u << 31) /**< \brief (GPIO_IMR1T) Interrupt Mode Bit 1 */\r
+/* -------- GPIO_GFER : (GPIO Offset: 0x0C0) Port Glitch Filter Enable Register -------- */\r
+#define GPIO_GFER_P0 (0x1u << 0) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P1 (0x1u << 1) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P2 (0x1u << 2) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P3 (0x1u << 3) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P4 (0x1u << 4) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P5 (0x1u << 5) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P6 (0x1u << 6) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P7 (0x1u << 7) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P8 (0x1u << 8) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P9 (0x1u << 9) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P10 (0x1u << 10) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P11 (0x1u << 11) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P12 (0x1u << 12) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P13 (0x1u << 13) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P14 (0x1u << 14) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P15 (0x1u << 15) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P16 (0x1u << 16) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P17 (0x1u << 17) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P18 (0x1u << 18) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P19 (0x1u << 19) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P20 (0x1u << 20) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P21 (0x1u << 21) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P22 (0x1u << 22) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P23 (0x1u << 23) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P24 (0x1u << 24) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P25 (0x1u << 25) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P26 (0x1u << 26) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P27 (0x1u << 27) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P28 (0x1u << 28) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P29 (0x1u << 29) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P30 (0x1u << 30) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+#define GPIO_GFER_P31 (0x1u << 31) /**< \brief (GPIO_GFER) Glitch Filter Enable */\r
+/* -------- GPIO_GFERS : (GPIO Offset: 0x0C4) Port Glitch Filter Enable Register - Set -------- */\r
+#define GPIO_GFERS_P0 (0x1u << 0) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P1 (0x1u << 1) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P2 (0x1u << 2) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P3 (0x1u << 3) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P4 (0x1u << 4) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P5 (0x1u << 5) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P6 (0x1u << 6) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P7 (0x1u << 7) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P8 (0x1u << 8) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P9 (0x1u << 9) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P10 (0x1u << 10) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P11 (0x1u << 11) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P12 (0x1u << 12) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P13 (0x1u << 13) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P14 (0x1u << 14) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P15 (0x1u << 15) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P16 (0x1u << 16) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P17 (0x1u << 17) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P18 (0x1u << 18) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P19 (0x1u << 19) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P20 (0x1u << 20) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P21 (0x1u << 21) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P22 (0x1u << 22) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P23 (0x1u << 23) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P24 (0x1u << 24) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P25 (0x1u << 25) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P26 (0x1u << 26) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P27 (0x1u << 27) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P28 (0x1u << 28) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P29 (0x1u << 29) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P30 (0x1u << 30) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+#define GPIO_GFERS_P31 (0x1u << 31) /**< \brief (GPIO_GFERS) Glitch Filter Enable */\r
+/* -------- GPIO_GFERC : (GPIO Offset: 0x0C8) Port Glitch Filter Enable Register - Clear -------- */\r
+#define GPIO_GFERC_P0 (0x1u << 0) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P1 (0x1u << 1) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P2 (0x1u << 2) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P3 (0x1u << 3) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P4 (0x1u << 4) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P5 (0x1u << 5) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P6 (0x1u << 6) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P7 (0x1u << 7) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P8 (0x1u << 8) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P9 (0x1u << 9) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P10 (0x1u << 10) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P11 (0x1u << 11) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P12 (0x1u << 12) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P13 (0x1u << 13) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P14 (0x1u << 14) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P15 (0x1u << 15) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P16 (0x1u << 16) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P17 (0x1u << 17) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P18 (0x1u << 18) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P19 (0x1u << 19) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P20 (0x1u << 20) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P21 (0x1u << 21) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P22 (0x1u << 22) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P23 (0x1u << 23) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P24 (0x1u << 24) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P25 (0x1u << 25) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P26 (0x1u << 26) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P27 (0x1u << 27) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P28 (0x1u << 28) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P29 (0x1u << 29) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P30 (0x1u << 30) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+#define GPIO_GFERC_P31 (0x1u << 31) /**< \brief (GPIO_GFERC) Glitch Filter Enable */\r
+/* -------- GPIO_GFERT : (GPIO Offset: 0x0CC) Port Glitch Filter Enable Register - Toggle -------- */\r
+#define GPIO_GFERT_P0 (0x1u << 0) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P1 (0x1u << 1) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P2 (0x1u << 2) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P3 (0x1u << 3) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P4 (0x1u << 4) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P5 (0x1u << 5) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P6 (0x1u << 6) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P7 (0x1u << 7) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P8 (0x1u << 8) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P9 (0x1u << 9) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P10 (0x1u << 10) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P11 (0x1u << 11) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P12 (0x1u << 12) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P13 (0x1u << 13) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P14 (0x1u << 14) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P15 (0x1u << 15) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P16 (0x1u << 16) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P17 (0x1u << 17) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P18 (0x1u << 18) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P19 (0x1u << 19) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P20 (0x1u << 20) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P21 (0x1u << 21) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P22 (0x1u << 22) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P23 (0x1u << 23) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P24 (0x1u << 24) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P25 (0x1u << 25) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P26 (0x1u << 26) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P27 (0x1u << 27) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P28 (0x1u << 28) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P29 (0x1u << 29) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P30 (0x1u << 30) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+#define GPIO_GFERT_P31 (0x1u << 31) /**< \brief (GPIO_GFERT) Glitch Filter Enable */\r
+/* -------- GPIO_IFR : (GPIO Offset: 0x0D0) Port Interrupt Flag Register -------- */\r
+#define GPIO_IFR_P0 (0x1u << 0) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P1 (0x1u << 1) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P2 (0x1u << 2) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P3 (0x1u << 3) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P4 (0x1u << 4) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P5 (0x1u << 5) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P6 (0x1u << 6) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P7 (0x1u << 7) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P8 (0x1u << 8) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P9 (0x1u << 9) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P10 (0x1u << 10) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P11 (0x1u << 11) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P12 (0x1u << 12) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P13 (0x1u << 13) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P14 (0x1u << 14) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P15 (0x1u << 15) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P16 (0x1u << 16) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P17 (0x1u << 17) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P18 (0x1u << 18) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P19 (0x1u << 19) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P20 (0x1u << 20) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P21 (0x1u << 21) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P22 (0x1u << 22) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P23 (0x1u << 23) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P24 (0x1u << 24) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P25 (0x1u << 25) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P26 (0x1u << 26) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P27 (0x1u << 27) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P28 (0x1u << 28) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P29 (0x1u << 29) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P30 (0x1u << 30) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+#define GPIO_IFR_P31 (0x1u << 31) /**< \brief (GPIO_IFR) Interrupt Flag */\r
+/* -------- GPIO_IFRC : (GPIO Offset: 0x0D8) Port Interrupt Flag Register - Clear -------- */\r
+#define GPIO_IFRC_P0 (0x1u << 0) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P1 (0x1u << 1) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P2 (0x1u << 2) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P3 (0x1u << 3) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P4 (0x1u << 4) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P5 (0x1u << 5) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P6 (0x1u << 6) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P7 (0x1u << 7) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P8 (0x1u << 8) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P9 (0x1u << 9) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P10 (0x1u << 10) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P11 (0x1u << 11) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P12 (0x1u << 12) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P13 (0x1u << 13) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P14 (0x1u << 14) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P15 (0x1u << 15) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P16 (0x1u << 16) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P17 (0x1u << 17) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P18 (0x1u << 18) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P19 (0x1u << 19) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P20 (0x1u << 20) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P21 (0x1u << 21) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P22 (0x1u << 22) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P23 (0x1u << 23) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P24 (0x1u << 24) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P25 (0x1u << 25) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P26 (0x1u << 26) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P27 (0x1u << 27) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P28 (0x1u << 28) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P29 (0x1u << 29) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P30 (0x1u << 30) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+#define GPIO_IFRC_P31 (0x1u << 31) /**< \brief (GPIO_IFRC) Interrupt Flag */\r
+/* -------- GPIO_ODMER : (GPIO Offset: 0x0E0) Port Open Drain Mode Register -------- */\r
+#define GPIO_ODMER_P0 (0x1u << 0) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P1 (0x1u << 1) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P2 (0x1u << 2) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P3 (0x1u << 3) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P4 (0x1u << 4) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P5 (0x1u << 5) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P6 (0x1u << 6) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P7 (0x1u << 7) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P8 (0x1u << 8) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P9 (0x1u << 9) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P10 (0x1u << 10) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P11 (0x1u << 11) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P12 (0x1u << 12) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P13 (0x1u << 13) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P14 (0x1u << 14) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P15 (0x1u << 15) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P16 (0x1u << 16) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P17 (0x1u << 17) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P18 (0x1u << 18) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P19 (0x1u << 19) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P20 (0x1u << 20) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P21 (0x1u << 21) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P22 (0x1u << 22) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P23 (0x1u << 23) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P24 (0x1u << 24) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P25 (0x1u << 25) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P26 (0x1u << 26) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P27 (0x1u << 27) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P28 (0x1u << 28) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P29 (0x1u << 29) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P30 (0x1u << 30) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+#define GPIO_ODMER_P31 (0x1u << 31) /**< \brief (GPIO_ODMER) Open Drain Mode Enable */\r
+/* -------- GPIO_ODMERS : (GPIO Offset: 0x0E4) Port Open Drain Mode Register - Set -------- */\r
+#define GPIO_ODMERS_P0 (0x1u << 0) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P1 (0x1u << 1) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P2 (0x1u << 2) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P3 (0x1u << 3) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P4 (0x1u << 4) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P5 (0x1u << 5) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P6 (0x1u << 6) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P7 (0x1u << 7) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P8 (0x1u << 8) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P9 (0x1u << 9) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P10 (0x1u << 10) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P11 (0x1u << 11) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P12 (0x1u << 12) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P13 (0x1u << 13) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P14 (0x1u << 14) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P15 (0x1u << 15) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P16 (0x1u << 16) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P17 (0x1u << 17) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P18 (0x1u << 18) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P19 (0x1u << 19) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P20 (0x1u << 20) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P21 (0x1u << 21) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P22 (0x1u << 22) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P23 (0x1u << 23) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P24 (0x1u << 24) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P25 (0x1u << 25) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P26 (0x1u << 26) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P27 (0x1u << 27) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P28 (0x1u << 28) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P29 (0x1u << 29) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P30 (0x1u << 30) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+#define GPIO_ODMERS_P31 (0x1u << 31) /**< \brief (GPIO_ODMERS) Open Drain Mode Enable */\r
+/* -------- GPIO_ODMERC : (GPIO Offset: 0x0E8) Port Open Drain Mode Register - Clear -------- */\r
+#define GPIO_ODMERC_P0 (0x1u << 0) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P1 (0x1u << 1) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P2 (0x1u << 2) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P3 (0x1u << 3) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P4 (0x1u << 4) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P5 (0x1u << 5) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P6 (0x1u << 6) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P7 (0x1u << 7) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P8 (0x1u << 8) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P9 (0x1u << 9) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P10 (0x1u << 10) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P11 (0x1u << 11) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P12 (0x1u << 12) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P13 (0x1u << 13) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P14 (0x1u << 14) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P15 (0x1u << 15) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P16 (0x1u << 16) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P17 (0x1u << 17) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P18 (0x1u << 18) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P19 (0x1u << 19) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P20 (0x1u << 20) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P21 (0x1u << 21) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P22 (0x1u << 22) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P23 (0x1u << 23) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P24 (0x1u << 24) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P25 (0x1u << 25) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P26 (0x1u << 26) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P27 (0x1u << 27) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P28 (0x1u << 28) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P29 (0x1u << 29) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P30 (0x1u << 30) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+#define GPIO_ODMERC_P31 (0x1u << 31) /**< \brief (GPIO_ODMERC) Open Drain Mode Enable */\r
+/* -------- GPIO_ODMERT : (GPIO Offset: 0x0EC) Port Open Drain Mode Register - Toggle -------- */\r
+#define GPIO_ODMERT_P0 (0x1u << 0) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P1 (0x1u << 1) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P2 (0x1u << 2) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P3 (0x1u << 3) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P4 (0x1u << 4) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P5 (0x1u << 5) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P6 (0x1u << 6) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P7 (0x1u << 7) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P8 (0x1u << 8) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P9 (0x1u << 9) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P10 (0x1u << 10) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P11 (0x1u << 11) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P12 (0x1u << 12) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P13 (0x1u << 13) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P14 (0x1u << 14) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P15 (0x1u << 15) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P16 (0x1u << 16) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P17 (0x1u << 17) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P18 (0x1u << 18) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P19 (0x1u << 19) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P20 (0x1u << 20) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P21 (0x1u << 21) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P22 (0x1u << 22) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P23 (0x1u << 23) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P24 (0x1u << 24) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P25 (0x1u << 25) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P26 (0x1u << 26) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P27 (0x1u << 27) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P28 (0x1u << 28) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P29 (0x1u << 29) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P30 (0x1u << 30) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+#define GPIO_ODMERT_P31 (0x1u << 31) /**< \brief (GPIO_ODMERT) Open Drain Mode Enable */\r
+/* -------- GPIO_ODCR0 : (GPIO Offset: 0x100) Port Output Driving Capability Register 0 -------- */\r
+#define GPIO_ODCR0_P0 (0x1u << 0) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P1 (0x1u << 1) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P2 (0x1u << 2) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P3 (0x1u << 3) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P4 (0x1u << 4) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P5 (0x1u << 5) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P6 (0x1u << 6) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P7 (0x1u << 7) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P8 (0x1u << 8) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P9 (0x1u << 9) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P10 (0x1u << 10) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P11 (0x1u << 11) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P12 (0x1u << 12) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P13 (0x1u << 13) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P14 (0x1u << 14) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P15 (0x1u << 15) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P16 (0x1u << 16) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P17 (0x1u << 17) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P18 (0x1u << 18) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P19 (0x1u << 19) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P20 (0x1u << 20) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P21 (0x1u << 21) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P22 (0x1u << 22) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P23 (0x1u << 23) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P24 (0x1u << 24) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P25 (0x1u << 25) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P26 (0x1u << 26) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P27 (0x1u << 27) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P28 (0x1u << 28) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P29 (0x1u << 29) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P30 (0x1u << 30) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0_P31 (0x1u << 31) /**< \brief (GPIO_ODCR0) Output Driving Capability Register Bit 0 */\r
+/* -------- GPIO_ODCR0S : (GPIO Offset: 0x104) Port Output Driving Capability Register 0 - Set -------- */\r
+#define GPIO_ODCR0S_P0 (0x1u << 0) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P1 (0x1u << 1) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P2 (0x1u << 2) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P3 (0x1u << 3) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P4 (0x1u << 4) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P5 (0x1u << 5) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P6 (0x1u << 6) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P7 (0x1u << 7) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P8 (0x1u << 8) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P9 (0x1u << 9) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P10 (0x1u << 10) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P11 (0x1u << 11) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P12 (0x1u << 12) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P13 (0x1u << 13) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P14 (0x1u << 14) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P15 (0x1u << 15) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P16 (0x1u << 16) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P17 (0x1u << 17) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P18 (0x1u << 18) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P19 (0x1u << 19) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P20 (0x1u << 20) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P21 (0x1u << 21) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P22 (0x1u << 22) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P23 (0x1u << 23) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P24 (0x1u << 24) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P25 (0x1u << 25) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P26 (0x1u << 26) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P27 (0x1u << 27) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P28 (0x1u << 28) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P29 (0x1u << 29) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P30 (0x1u << 30) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0S_P31 (0x1u << 31) /**< \brief (GPIO_ODCR0S) Output Driving Capability Register Bit 0 */\r
+/* -------- GPIO_ODCR0C : (GPIO Offset: 0x108) Port Output Driving Capability Register 0 - Clear -------- */\r
+#define GPIO_ODCR0C_P0 (0x1u << 0) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P1 (0x1u << 1) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P2 (0x1u << 2) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P3 (0x1u << 3) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P4 (0x1u << 4) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P5 (0x1u << 5) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P6 (0x1u << 6) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P7 (0x1u << 7) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P8 (0x1u << 8) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P9 (0x1u << 9) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P10 (0x1u << 10) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P11 (0x1u << 11) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P12 (0x1u << 12) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P13 (0x1u << 13) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P14 (0x1u << 14) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P15 (0x1u << 15) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P16 (0x1u << 16) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P17 (0x1u << 17) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P18 (0x1u << 18) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P19 (0x1u << 19) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P20 (0x1u << 20) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P21 (0x1u << 21) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P22 (0x1u << 22) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P23 (0x1u << 23) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P24 (0x1u << 24) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P25 (0x1u << 25) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P26 (0x1u << 26) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P27 (0x1u << 27) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P28 (0x1u << 28) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P29 (0x1u << 29) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P30 (0x1u << 30) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0C_P31 (0x1u << 31) /**< \brief (GPIO_ODCR0C) Output Driving Capability Register Bit 0 */\r
+/* -------- GPIO_ODCR0T : (GPIO Offset: 0x10C) Port Output Driving Capability Register 0 - Toggle -------- */\r
+#define GPIO_ODCR0T_P0 (0x1u << 0) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P1 (0x1u << 1) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P2 (0x1u << 2) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P3 (0x1u << 3) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P4 (0x1u << 4) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P5 (0x1u << 5) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P6 (0x1u << 6) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P7 (0x1u << 7) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P8 (0x1u << 8) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P9 (0x1u << 9) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P10 (0x1u << 10) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P11 (0x1u << 11) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P12 (0x1u << 12) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P13 (0x1u << 13) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P14 (0x1u << 14) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P15 (0x1u << 15) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P16 (0x1u << 16) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P17 (0x1u << 17) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P18 (0x1u << 18) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P19 (0x1u << 19) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P20 (0x1u << 20) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P21 (0x1u << 21) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P22 (0x1u << 22) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P23 (0x1u << 23) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P24 (0x1u << 24) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P25 (0x1u << 25) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P26 (0x1u << 26) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P27 (0x1u << 27) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P28 (0x1u << 28) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P29 (0x1u << 29) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P30 (0x1u << 30) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+#define GPIO_ODCR0T_P31 (0x1u << 31) /**< \brief (GPIO_ODCR0T) Output Driving Capability Register Bit 0 */\r
+/* -------- GPIO_ODCR1 : (GPIO Offset: 0x110) Port Output Driving Capability Register 1 -------- */\r
+#define GPIO_ODCR1_P0 (0x1u << 0) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P1 (0x1u << 1) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P2 (0x1u << 2) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P3 (0x1u << 3) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P4 (0x1u << 4) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P5 (0x1u << 5) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P6 (0x1u << 6) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P7 (0x1u << 7) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P8 (0x1u << 8) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P9 (0x1u << 9) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P10 (0x1u << 10) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P11 (0x1u << 11) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P12 (0x1u << 12) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P13 (0x1u << 13) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P14 (0x1u << 14) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P15 (0x1u << 15) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P16 (0x1u << 16) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P17 (0x1u << 17) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P18 (0x1u << 18) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P19 (0x1u << 19) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P20 (0x1u << 20) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P21 (0x1u << 21) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P22 (0x1u << 22) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P23 (0x1u << 23) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P24 (0x1u << 24) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P25 (0x1u << 25) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P26 (0x1u << 26) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P27 (0x1u << 27) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P28 (0x1u << 28) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P29 (0x1u << 29) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P30 (0x1u << 30) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1_P31 (0x1u << 31) /**< \brief (GPIO_ODCR1) Output Driving Capability Register Bit 1 */\r
+/* -------- GPIO_ODCR1S : (GPIO Offset: 0x114) Port Output Driving Capability Register 1 - Set -------- */\r
+#define GPIO_ODCR1S_P0 (0x1u << 0) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P1 (0x1u << 1) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P2 (0x1u << 2) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P3 (0x1u << 3) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P4 (0x1u << 4) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P5 (0x1u << 5) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P6 (0x1u << 6) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P7 (0x1u << 7) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P8 (0x1u << 8) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P9 (0x1u << 9) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P10 (0x1u << 10) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P11 (0x1u << 11) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P12 (0x1u << 12) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P13 (0x1u << 13) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P14 (0x1u << 14) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P15 (0x1u << 15) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P16 (0x1u << 16) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P17 (0x1u << 17) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P18 (0x1u << 18) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P19 (0x1u << 19) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P20 (0x1u << 20) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P21 (0x1u << 21) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P22 (0x1u << 22) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P23 (0x1u << 23) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P24 (0x1u << 24) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P25 (0x1u << 25) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P26 (0x1u << 26) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P27 (0x1u << 27) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P28 (0x1u << 28) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P29 (0x1u << 29) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P30 (0x1u << 30) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1S_P31 (0x1u << 31) /**< \brief (GPIO_ODCR1S) Output Driving Capability Register Bit 1 */\r
+/* -------- GPIO_ODCR1C : (GPIO Offset: 0x118) Port Output Driving Capability Register 1 - Clear -------- */\r
+#define GPIO_ODCR1C_P0 (0x1u << 0) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P1 (0x1u << 1) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P2 (0x1u << 2) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P3 (0x1u << 3) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P4 (0x1u << 4) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P5 (0x1u << 5) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P6 (0x1u << 6) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P7 (0x1u << 7) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P8 (0x1u << 8) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P9 (0x1u << 9) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P10 (0x1u << 10) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P11 (0x1u << 11) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P12 (0x1u << 12) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P13 (0x1u << 13) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P14 (0x1u << 14) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P15 (0x1u << 15) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P16 (0x1u << 16) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P17 (0x1u << 17) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P18 (0x1u << 18) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P19 (0x1u << 19) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P20 (0x1u << 20) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P21 (0x1u << 21) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P22 (0x1u << 22) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P23 (0x1u << 23) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P24 (0x1u << 24) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P25 (0x1u << 25) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P26 (0x1u << 26) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P27 (0x1u << 27) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P28 (0x1u << 28) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P29 (0x1u << 29) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P30 (0x1u << 30) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1C_P31 (0x1u << 31) /**< \brief (GPIO_ODCR1C) Output Driving Capability Register Bit 1 */\r
+/* -------- GPIO_ODCR1T : (GPIO Offset: 0x11C) Port Output Driving Capability Register 1 - Toggle -------- */\r
+#define GPIO_ODCR1T_P0 (0x1u << 0) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P1 (0x1u << 1) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P2 (0x1u << 2) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P3 (0x1u << 3) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P4 (0x1u << 4) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P5 (0x1u << 5) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P6 (0x1u << 6) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P7 (0x1u << 7) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P8 (0x1u << 8) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P9 (0x1u << 9) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P10 (0x1u << 10) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P11 (0x1u << 11) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P12 (0x1u << 12) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P13 (0x1u << 13) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P14 (0x1u << 14) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P15 (0x1u << 15) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P16 (0x1u << 16) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P17 (0x1u << 17) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P18 (0x1u << 18) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P19 (0x1u << 19) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P20 (0x1u << 20) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P21 (0x1u << 21) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P22 (0x1u << 22) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P23 (0x1u << 23) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P24 (0x1u << 24) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P25 (0x1u << 25) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P26 (0x1u << 26) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P27 (0x1u << 27) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P28 (0x1u << 28) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P29 (0x1u << 29) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P30 (0x1u << 30) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+#define GPIO_ODCR1T_P31 (0x1u << 31) /**< \brief (GPIO_ODCR1T) Output Driving Capability Register Bit 1 */\r
+/* -------- GPIO_OSRR0 : (GPIO Offset: 0x130) Port Output Slew Rate Register 0 -------- */\r
+#define GPIO_OSRR0_P0 (0x1u << 0) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P1 (0x1u << 1) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P2 (0x1u << 2) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P3 (0x1u << 3) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P4 (0x1u << 4) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P5 (0x1u << 5) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P6 (0x1u << 6) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P7 (0x1u << 7) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P8 (0x1u << 8) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P9 (0x1u << 9) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P10 (0x1u << 10) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P11 (0x1u << 11) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P12 (0x1u << 12) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P13 (0x1u << 13) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P14 (0x1u << 14) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P15 (0x1u << 15) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P16 (0x1u << 16) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P17 (0x1u << 17) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P18 (0x1u << 18) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P19 (0x1u << 19) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P20 (0x1u << 20) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P21 (0x1u << 21) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P22 (0x1u << 22) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P23 (0x1u << 23) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P24 (0x1u << 24) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P25 (0x1u << 25) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P26 (0x1u << 26) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P27 (0x1u << 27) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P28 (0x1u << 28) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P29 (0x1u << 29) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P30 (0x1u << 30) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0_P31 (0x1u << 31) /**< \brief (GPIO_OSRR0) Output Slew Rate Control Enable */\r
+/* -------- GPIO_OSRR0S : (GPIO Offset: 0x134) Port Output Slew Rate Register 0 - Set -------- */\r
+#define GPIO_OSRR0S_P0 (0x1u << 0) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P1 (0x1u << 1) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P2 (0x1u << 2) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P3 (0x1u << 3) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P4 (0x1u << 4) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P5 (0x1u << 5) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P6 (0x1u << 6) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P7 (0x1u << 7) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P8 (0x1u << 8) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P9 (0x1u << 9) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P10 (0x1u << 10) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P11 (0x1u << 11) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P12 (0x1u << 12) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P13 (0x1u << 13) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P14 (0x1u << 14) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P15 (0x1u << 15) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P16 (0x1u << 16) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P17 (0x1u << 17) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P18 (0x1u << 18) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P19 (0x1u << 19) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P20 (0x1u << 20) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P21 (0x1u << 21) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P22 (0x1u << 22) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P23 (0x1u << 23) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P24 (0x1u << 24) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P25 (0x1u << 25) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P26 (0x1u << 26) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P27 (0x1u << 27) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P28 (0x1u << 28) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P29 (0x1u << 29) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P30 (0x1u << 30) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0S_P31 (0x1u << 31) /**< \brief (GPIO_OSRR0S) Output Slew Rate Control Enable */\r
+/* -------- GPIO_OSRR0C : (GPIO Offset: 0x138) Port Output Slew Rate Register 0 - Clear -------- */\r
+#define GPIO_OSRR0C_P0 (0x1u << 0) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P1 (0x1u << 1) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P2 (0x1u << 2) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P3 (0x1u << 3) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P4 (0x1u << 4) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P5 (0x1u << 5) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P6 (0x1u << 6) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P7 (0x1u << 7) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P8 (0x1u << 8) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P9 (0x1u << 9) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P10 (0x1u << 10) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P11 (0x1u << 11) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P12 (0x1u << 12) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P13 (0x1u << 13) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P14 (0x1u << 14) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P15 (0x1u << 15) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P16 (0x1u << 16) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P17 (0x1u << 17) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P18 (0x1u << 18) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P19 (0x1u << 19) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P20 (0x1u << 20) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P21 (0x1u << 21) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P22 (0x1u << 22) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P23 (0x1u << 23) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P24 (0x1u << 24) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P25 (0x1u << 25) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P26 (0x1u << 26) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P27 (0x1u << 27) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P28 (0x1u << 28) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P29 (0x1u << 29) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P30 (0x1u << 30) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0C_P31 (0x1u << 31) /**< \brief (GPIO_OSRR0C) Output Slew Rate Control Enable */\r
+/* -------- GPIO_OSRR0T : (GPIO Offset: 0x13C) Port Output Slew Rate Register 0 - Toggle -------- */\r
+#define GPIO_OSRR0T_P0 (0x1u << 0) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P1 (0x1u << 1) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P2 (0x1u << 2) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P3 (0x1u << 3) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P4 (0x1u << 4) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P5 (0x1u << 5) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P6 (0x1u << 6) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P7 (0x1u << 7) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P8 (0x1u << 8) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P9 (0x1u << 9) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P10 (0x1u << 10) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P11 (0x1u << 11) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P12 (0x1u << 12) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P13 (0x1u << 13) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P14 (0x1u << 14) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P15 (0x1u << 15) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P16 (0x1u << 16) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P17 (0x1u << 17) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P18 (0x1u << 18) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P19 (0x1u << 19) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P20 (0x1u << 20) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P21 (0x1u << 21) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P22 (0x1u << 22) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P23 (0x1u << 23) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P24 (0x1u << 24) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P25 (0x1u << 25) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P26 (0x1u << 26) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P27 (0x1u << 27) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P28 (0x1u << 28) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P29 (0x1u << 29) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P30 (0x1u << 30) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+#define GPIO_OSRR0T_P31 (0x1u << 31) /**< \brief (GPIO_OSRR0T) Output Slew Rate Control Enable */\r
+/* -------- GPIO_STER : (GPIO Offset: 0x160) Port Schmitt Trigger Enable Register -------- */\r
+#define GPIO_STER_P0 (0x1u << 0) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P1 (0x1u << 1) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P2 (0x1u << 2) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P3 (0x1u << 3) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P4 (0x1u << 4) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P5 (0x1u << 5) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P6 (0x1u << 6) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P7 (0x1u << 7) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P8 (0x1u << 8) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P9 (0x1u << 9) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P10 (0x1u << 10) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P11 (0x1u << 11) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P12 (0x1u << 12) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P13 (0x1u << 13) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P14 (0x1u << 14) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P15 (0x1u << 15) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P16 (0x1u << 16) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P17 (0x1u << 17) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P18 (0x1u << 18) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P19 (0x1u << 19) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P20 (0x1u << 20) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P21 (0x1u << 21) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P22 (0x1u << 22) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P23 (0x1u << 23) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P24 (0x1u << 24) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P25 (0x1u << 25) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P26 (0x1u << 26) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P27 (0x1u << 27) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P28 (0x1u << 28) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P29 (0x1u << 29) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P30 (0x1u << 30) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+#define GPIO_STER_P31 (0x1u << 31) /**< \brief (GPIO_STER) Schmitt Trigger Enable */\r
+/* -------- GPIO_STERS : (GPIO Offset: 0x164) Port Schmitt Trigger Enable Register - Set -------- */\r
+#define GPIO_STERS_P0 (0x1u << 0) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P1 (0x1u << 1) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P2 (0x1u << 2) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P3 (0x1u << 3) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P4 (0x1u << 4) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P5 (0x1u << 5) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P6 (0x1u << 6) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P7 (0x1u << 7) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P8 (0x1u << 8) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P9 (0x1u << 9) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P10 (0x1u << 10) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P11 (0x1u << 11) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P12 (0x1u << 12) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P13 (0x1u << 13) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P14 (0x1u << 14) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P15 (0x1u << 15) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P16 (0x1u << 16) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P17 (0x1u << 17) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P18 (0x1u << 18) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P19 (0x1u << 19) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P20 (0x1u << 20) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P21 (0x1u << 21) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P22 (0x1u << 22) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P23 (0x1u << 23) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P24 (0x1u << 24) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P25 (0x1u << 25) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P26 (0x1u << 26) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P27 (0x1u << 27) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P28 (0x1u << 28) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P29 (0x1u << 29) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P30 (0x1u << 30) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+#define GPIO_STERS_P31 (0x1u << 31) /**< \brief (GPIO_STERS) Schmitt Trigger Enable */\r
+/* -------- GPIO_STERC : (GPIO Offset: 0x168) Port Schmitt Trigger Enable Register - Clear -------- */\r
+#define GPIO_STERC_P0 (0x1u << 0) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P1 (0x1u << 1) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P2 (0x1u << 2) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P3 (0x1u << 3) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P4 (0x1u << 4) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P5 (0x1u << 5) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P6 (0x1u << 6) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P7 (0x1u << 7) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P8 (0x1u << 8) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P9 (0x1u << 9) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P10 (0x1u << 10) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P11 (0x1u << 11) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P12 (0x1u << 12) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P13 (0x1u << 13) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P14 (0x1u << 14) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P15 (0x1u << 15) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P16 (0x1u << 16) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P17 (0x1u << 17) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P18 (0x1u << 18) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P19 (0x1u << 19) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P20 (0x1u << 20) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P21 (0x1u << 21) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P22 (0x1u << 22) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P23 (0x1u << 23) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P24 (0x1u << 24) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P25 (0x1u << 25) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P26 (0x1u << 26) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P27 (0x1u << 27) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P28 (0x1u << 28) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P29 (0x1u << 29) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P30 (0x1u << 30) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+#define GPIO_STERC_P31 (0x1u << 31) /**< \brief (GPIO_STERC) Schmitt Trigger Enable */\r
+/* -------- GPIO_STERT : (GPIO Offset: 0x16C) Port Schmitt Trigger Enable Register - Toggle -------- */\r
+#define GPIO_STERT_P0 (0x1u << 0) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P1 (0x1u << 1) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P2 (0x1u << 2) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P3 (0x1u << 3) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P4 (0x1u << 4) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P5 (0x1u << 5) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P6 (0x1u << 6) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P7 (0x1u << 7) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P8 (0x1u << 8) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P9 (0x1u << 9) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P10 (0x1u << 10) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P11 (0x1u << 11) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P12 (0x1u << 12) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P13 (0x1u << 13) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P14 (0x1u << 14) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P15 (0x1u << 15) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P16 (0x1u << 16) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P17 (0x1u << 17) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P18 (0x1u << 18) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P19 (0x1u << 19) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P20 (0x1u << 20) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P21 (0x1u << 21) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P22 (0x1u << 22) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P23 (0x1u << 23) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P24 (0x1u << 24) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P25 (0x1u << 25) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P26 (0x1u << 26) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P27 (0x1u << 27) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P28 (0x1u << 28) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P29 (0x1u << 29) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P30 (0x1u << 30) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+#define GPIO_STERT_P31 (0x1u << 31) /**< \brief (GPIO_STERT) Schmitt Trigger Enable */\r
+/* -------- GPIO_EVER : (GPIO Offset: 0x180) Port Event Enable Register -------- */\r
+#define GPIO_EVER_P0 (0x1u << 0) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P1 (0x1u << 1) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P2 (0x1u << 2) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P3 (0x1u << 3) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P4 (0x1u << 4) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P5 (0x1u << 5) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P6 (0x1u << 6) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P7 (0x1u << 7) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P8 (0x1u << 8) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P9 (0x1u << 9) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P10 (0x1u << 10) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P11 (0x1u << 11) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P12 (0x1u << 12) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P13 (0x1u << 13) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P14 (0x1u << 14) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P15 (0x1u << 15) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P16 (0x1u << 16) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P17 (0x1u << 17) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P18 (0x1u << 18) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P19 (0x1u << 19) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P20 (0x1u << 20) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P21 (0x1u << 21) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P22 (0x1u << 22) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P23 (0x1u << 23) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P24 (0x1u << 24) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P25 (0x1u << 25) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P26 (0x1u << 26) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P27 (0x1u << 27) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P28 (0x1u << 28) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P29 (0x1u << 29) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P30 (0x1u << 30) /**< \brief (GPIO_EVER) Event Enable */\r
+#define GPIO_EVER_P31 (0x1u << 31) /**< \brief (GPIO_EVER) Event Enable */\r
+/* -------- GPIO_EVERS : (GPIO Offset: 0x184) Port Event Enable Register - Set -------- */\r
+#define GPIO_EVERS_P0 (0x1u << 0) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P1 (0x1u << 1) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P2 (0x1u << 2) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P3 (0x1u << 3) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P4 (0x1u << 4) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P5 (0x1u << 5) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P6 (0x1u << 6) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P7 (0x1u << 7) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P8 (0x1u << 8) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P9 (0x1u << 9) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P10 (0x1u << 10) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P11 (0x1u << 11) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P12 (0x1u << 12) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P13 (0x1u << 13) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P14 (0x1u << 14) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P15 (0x1u << 15) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P16 (0x1u << 16) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P17 (0x1u << 17) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P18 (0x1u << 18) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P19 (0x1u << 19) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P20 (0x1u << 20) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P21 (0x1u << 21) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P22 (0x1u << 22) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P23 (0x1u << 23) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P24 (0x1u << 24) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P25 (0x1u << 25) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P26 (0x1u << 26) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P27 (0x1u << 27) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P28 (0x1u << 28) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P29 (0x1u << 29) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P30 (0x1u << 30) /**< \brief (GPIO_EVERS) Event Enable */\r
+#define GPIO_EVERS_P31 (0x1u << 31) /**< \brief (GPIO_EVERS) Event Enable */\r
+/* -------- GPIO_EVERC : (GPIO Offset: 0x188) Port Event Enable Register - Clear -------- */\r
+#define GPIO_EVERC_P0 (0x1u << 0) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P1 (0x1u << 1) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P2 (0x1u << 2) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P3 (0x1u << 3) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P4 (0x1u << 4) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P5 (0x1u << 5) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P6 (0x1u << 6) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P7 (0x1u << 7) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P8 (0x1u << 8) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P9 (0x1u << 9) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P10 (0x1u << 10) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P11 (0x1u << 11) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P12 (0x1u << 12) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P13 (0x1u << 13) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P14 (0x1u << 14) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P15 (0x1u << 15) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P16 (0x1u << 16) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P17 (0x1u << 17) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P18 (0x1u << 18) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P19 (0x1u << 19) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P20 (0x1u << 20) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P21 (0x1u << 21) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P22 (0x1u << 22) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P23 (0x1u << 23) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P24 (0x1u << 24) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P25 (0x1u << 25) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P26 (0x1u << 26) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P27 (0x1u << 27) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P28 (0x1u << 28) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P29 (0x1u << 29) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P30 (0x1u << 30) /**< \brief (GPIO_EVERC) Event Enable */\r
+#define GPIO_EVERC_P31 (0x1u << 31) /**< \brief (GPIO_EVERC) Event Enable */\r
+/* -------- GPIO_EVERT : (GPIO Offset: 0x18C) Port Event Enable Register - Toggle -------- */\r
+#define GPIO_EVERT_P0 (0x1u << 0) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P1 (0x1u << 1) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P2 (0x1u << 2) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P3 (0x1u << 3) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P4 (0x1u << 4) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P5 (0x1u << 5) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P6 (0x1u << 6) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P7 (0x1u << 7) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P8 (0x1u << 8) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P9 (0x1u << 9) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P10 (0x1u << 10) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P11 (0x1u << 11) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P12 (0x1u << 12) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P13 (0x1u << 13) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P14 (0x1u << 14) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P15 (0x1u << 15) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P16 (0x1u << 16) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P17 (0x1u << 17) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P18 (0x1u << 18) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P19 (0x1u << 19) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P20 (0x1u << 20) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P21 (0x1u << 21) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P22 (0x1u << 22) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P23 (0x1u << 23) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P24 (0x1u << 24) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P25 (0x1u << 25) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P26 (0x1u << 26) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P27 (0x1u << 27) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P28 (0x1u << 28) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P29 (0x1u << 29) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P30 (0x1u << 30) /**< \brief (GPIO_EVERT) Event Enable */\r
+#define GPIO_EVERT_P31 (0x1u << 31) /**< \brief (GPIO_EVERT) Event Enable */\r
+/* -------- GPIO_LOCK : (GPIO Offset: 0x1A0) Port Lock Register -------- */\r
+#define GPIO_LOCK_P0 (0x1u << 0) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P1 (0x1u << 1) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P2 (0x1u << 2) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P3 (0x1u << 3) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P4 (0x1u << 4) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P5 (0x1u << 5) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P6 (0x1u << 6) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P7 (0x1u << 7) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P8 (0x1u << 8) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P9 (0x1u << 9) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P10 (0x1u << 10) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P11 (0x1u << 11) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P12 (0x1u << 12) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P13 (0x1u << 13) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P14 (0x1u << 14) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P15 (0x1u << 15) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P16 (0x1u << 16) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P17 (0x1u << 17) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P18 (0x1u << 18) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P19 (0x1u << 19) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P20 (0x1u << 20) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P21 (0x1u << 21) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P22 (0x1u << 22) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P23 (0x1u << 23) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P24 (0x1u << 24) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P25 (0x1u << 25) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P26 (0x1u << 26) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P27 (0x1u << 27) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P28 (0x1u << 28) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P29 (0x1u << 29) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P30 (0x1u << 30) /**< \brief (GPIO_LOCK) Lock State */\r
+#define GPIO_LOCK_P31 (0x1u << 31) /**< \brief (GPIO_LOCK) Lock State */\r
+/* -------- GPIO_LOCKS : (GPIO Offset: 0x1A4) Port Lock Register - Set -------- */\r
+#define GPIO_LOCKS_P0 (0x1u << 0) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P1 (0x1u << 1) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P2 (0x1u << 2) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P3 (0x1u << 3) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P4 (0x1u << 4) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P5 (0x1u << 5) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P6 (0x1u << 6) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P7 (0x1u << 7) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P8 (0x1u << 8) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P9 (0x1u << 9) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P10 (0x1u << 10) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P11 (0x1u << 11) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P12 (0x1u << 12) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P13 (0x1u << 13) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P14 (0x1u << 14) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P15 (0x1u << 15) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P16 (0x1u << 16) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P17 (0x1u << 17) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P18 (0x1u << 18) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P19 (0x1u << 19) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P20 (0x1u << 20) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P21 (0x1u << 21) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P22 (0x1u << 22) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P23 (0x1u << 23) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P24 (0x1u << 24) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P25 (0x1u << 25) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P26 (0x1u << 26) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P27 (0x1u << 27) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P28 (0x1u << 28) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P29 (0x1u << 29) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P30 (0x1u << 30) /**< \brief (GPIO_LOCKS) Lock State */\r
+#define GPIO_LOCKS_P31 (0x1u << 31) /**< \brief (GPIO_LOCKS) Lock State */\r
+/* -------- GPIO_LOCKC : (GPIO Offset: 0x1A8) Port Lock Register - Clear -------- */\r
+#define GPIO_LOCKC_P0 (0x1u << 0) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P1 (0x1u << 1) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P2 (0x1u << 2) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P3 (0x1u << 3) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P4 (0x1u << 4) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P5 (0x1u << 5) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P6 (0x1u << 6) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P7 (0x1u << 7) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P8 (0x1u << 8) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P9 (0x1u << 9) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P10 (0x1u << 10) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P11 (0x1u << 11) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P12 (0x1u << 12) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P13 (0x1u << 13) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P14 (0x1u << 14) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P15 (0x1u << 15) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P16 (0x1u << 16) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P17 (0x1u << 17) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P18 (0x1u << 18) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P19 (0x1u << 19) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P20 (0x1u << 20) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P21 (0x1u << 21) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P22 (0x1u << 22) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P23 (0x1u << 23) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P24 (0x1u << 24) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P25 (0x1u << 25) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P26 (0x1u << 26) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P27 (0x1u << 27) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P28 (0x1u << 28) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P29 (0x1u << 29) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P30 (0x1u << 30) /**< \brief (GPIO_LOCKC) Lock State */\r
+#define GPIO_LOCKC_P31 (0x1u << 31) /**< \brief (GPIO_LOCKC) Lock State */\r
+/* -------- GPIO_LOCKT : (GPIO Offset: 0x1AC) Port Lock Register - Toggle -------- */\r
+#define GPIO_LOCKT_P0 (0x1u << 0) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P1 (0x1u << 1) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P2 (0x1u << 2) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P3 (0x1u << 3) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P4 (0x1u << 4) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P5 (0x1u << 5) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P6 (0x1u << 6) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P7 (0x1u << 7) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P8 (0x1u << 8) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P9 (0x1u << 9) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P10 (0x1u << 10) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P11 (0x1u << 11) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P12 (0x1u << 12) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P13 (0x1u << 13) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P14 (0x1u << 14) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P15 (0x1u << 15) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P16 (0x1u << 16) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P17 (0x1u << 17) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P18 (0x1u << 18) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P19 (0x1u << 19) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P20 (0x1u << 20) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P21 (0x1u << 21) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P22 (0x1u << 22) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P23 (0x1u << 23) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P24 (0x1u << 24) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P25 (0x1u << 25) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P26 (0x1u << 26) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P27 (0x1u << 27) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P28 (0x1u << 28) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P29 (0x1u << 29) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P30 (0x1u << 30) /**< \brief (GPIO_LOCKT) Lock State */\r
+#define GPIO_LOCKT_P31 (0x1u << 31) /**< \brief (GPIO_LOCKT) Lock State */\r
+/* -------- GPIO_UNLOCK : (GPIO Offset: 0x1E0) Port Unlock Register -------- */\r
+#define GPIO_UNLOCK_OFFSET_Pos 0\r
+#define GPIO_UNLOCK_OFFSET_Msk (0x3FFu << GPIO_UNLOCK_OFFSET_Pos) /**< \brief (GPIO_UNLOCK) Offset Register */\r
+#define GPIO_UNLOCK_OFFSET(value) ((GPIO_UNLOCK_OFFSET_Msk & ((value) << GPIO_UNLOCK_OFFSET_Pos)))\r
+#define GPIO_UNLOCK_KEY_Pos 24\r
+#define GPIO_UNLOCK_KEY_Msk (0xFFu << GPIO_UNLOCK_KEY_Pos) /**< \brief (GPIO_UNLOCK) Unlocking Key */\r
+#define GPIO_UNLOCK_KEY(value) ((GPIO_UNLOCK_KEY_Msk & ((value) << GPIO_UNLOCK_KEY_Pos)))\r
+/* -------- GPIO_ASR : (GPIO Offset: 0x1E4) Port Access Status Register -------- */\r
+#define GPIO_ASR_AR (0x1u << 0) /**< \brief (GPIO_ASR) Access Error */\r
+/* -------- GPIO_PARAMETER : (GPIO Offset: 0x1F8) Port Parameter Register -------- */\r
+#define GPIO_PARAMETER_PARAMETER_Pos 0\r
+#define GPIO_PARAMETER_PARAMETER_Msk (0xFFFFFFFFu << GPIO_PARAMETER_PARAMETER_Pos) /**< \brief (GPIO_PARAMETER) Parameter */\r
+#define GPIO_PARAMETER_PARAMETER(value) ((GPIO_PARAMETER_PARAMETER_Msk & ((value) << GPIO_PARAMETER_PARAMETER_Pos)))\r
+/* -------- GPIO_VERSION : (GPIO Offset: 0x1FC) Port Version Register -------- */\r
+#define GPIO_VERSION_VERSION_Pos 0\r
+#define GPIO_VERSION_VERSION_Msk (0xFFFu << GPIO_VERSION_VERSION_Pos) /**< \brief (GPIO_VERSION) Version Number */\r
+#define GPIO_VERSION_VERSION(value) ((GPIO_VERSION_VERSION_Msk & ((value) << GPIO_VERSION_VERSION_Pos)))\r
+#define GPIO_VERSION_VARIANT_Pos 16\r
+#define GPIO_VERSION_VARIANT_Msk (0xFu << GPIO_VERSION_VARIANT_Pos) /**< \brief (GPIO_VERSION) Variant Number */\r
+#define GPIO_VERSION_VARIANT(value) ((GPIO_VERSION_VARIANT_Msk & ((value) << GPIO_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR HCACHE */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_HCACHE Cortex M I&D Cache Controller */\r
+/*@{*/\r
+\r
+#define REV_HCACHE 0x101\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief HCACHE hardware registers */\r
+typedef struct {\r
+ RoReg Reserved1[2];\r
+ WoReg HCACHE_CTRL; /**< \brief (HCACHE Offset: 0x08) Control Register */\r
+ RwReg HCACHE_SR; /**< \brief (HCACHE Offset: 0x0C) Status Register */\r
+ RoReg Reserved2[4];\r
+ WoReg HCACHE_MAINT0; /**< \brief (HCACHE Offset: 0x20) Maintenance Register 0 */\r
+ WoReg HCACHE_MAINT1; /**< \brief (HCACHE Offset: 0x24) Maintenance Register 1 */\r
+ RwReg HCACHE_MCFG; /**< \brief (HCACHE Offset: 0x28) Monitor Configuration Register */\r
+ RwReg HCACHE_MEN; /**< \brief (HCACHE Offset: 0x2C) Monitor Enable Register */\r
+ WoReg HCACHE_MCTRL; /**< \brief (HCACHE Offset: 0x30) Monitor Control Register */\r
+ RoReg HCACHE_MSR; /**< \brief (HCACHE Offset: 0x34) Monitor Status Register */\r
+ RoReg Reserved3[49];\r
+ RoReg HCACHE_VERSION; /**< \brief (HCACHE Offset: 0xFC) Version Register */\r
+} Hcache;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- HCACHE_CTRL : (HCACHE Offset: 0x08) Control Register -------- */\r
+#define HCACHE_CTRL_CEN (0x1u << 0) /**< \brief (HCACHE_CTRL) Cache Enable */\r
+#define HCACHE_CTRL_CEN_NO (0x0u << 0) /**< \brief (HCACHE_CTRL) Disable Cache Controller */\r
+#define HCACHE_CTRL_CEN_YES (0x1u << 0) /**< \brief (HCACHE_CTRL) Enable Cache Controller */\r
+/* -------- HCACHE_SR : (HCACHE Offset: 0x0C) Status Register -------- */\r
+#define HCACHE_SR_CSTS (0x1u << 0) /**< \brief (HCACHE_SR) Cache Controller Status */\r
+#define HCACHE_SR_CSTS_DIS (0x0u << 0) /**< \brief (HCACHE_SR) Cache Controller Disabled */\r
+#define HCACHE_SR_CSTS_EN (0x1u << 0) /**< \brief (HCACHE_SR) Cache Controller Enabled */\r
+/* -------- HCACHE_MAINT0 : (HCACHE Offset: 0x20) Maintenance Register 0 -------- */\r
+#define HCACHE_MAINT0_INVALL (0x1u << 0) /**< \brief (HCACHE_MAINT0) Cache Controller Invalidate All */\r
+#define HCACHE_MAINT0_INVALL_NO (0x0u << 0) /**< \brief (HCACHE_MAINT0) No effect */\r
+#define HCACHE_MAINT0_INVALL_YES (0x1u << 0) /**< \brief (HCACHE_MAINT0) Invalidate all cache entries */\r
+/* -------- HCACHE_MAINT1 : (HCACHE Offset: 0x24) Maintenance Register 1 -------- */\r
+#define HCACHE_MAINT1_INDEX_Pos 4\r
+#define HCACHE_MAINT1_INDEX_Msk (0xFu << HCACHE_MAINT1_INDEX_Pos) /**< \brief (HCACHE_MAINT1) Invalidate Index */\r
+#define HCACHE_MAINT1_INDEX(value) ((HCACHE_MAINT1_INDEX_Msk & ((value) << HCACHE_MAINT1_INDEX_Pos)))\r
+/* -------- HCACHE_MCFG : (HCACHE Offset: 0x28) Monitor Configuration Register -------- */\r
+#define HCACHE_MCFG_MODE_Pos 0\r
+#define HCACHE_MCFG_MODE_Msk (0x3u << HCACHE_MCFG_MODE_Pos) /**< \brief (HCACHE_MCFG) Cache Controller Monitor Counter Mode */\r
+#define HCACHE_MCFG_MODE(value) ((HCACHE_MCFG_MODE_Msk & ((value) << HCACHE_MCFG_MODE_Pos)))\r
+#define HCACHE_MCFG_MODE_CYCLE (0x0u << 0) /**< \brief (HCACHE_MCFG) Cycle Counter */\r
+#define HCACHE_MCFG_MODE_IHIT (0x1u << 0) /**< \brief (HCACHE_MCFG) Instruction Hit Counter */\r
+#define HCACHE_MCFG_MODE_DHIT (0x2u << 0) /**< \brief (HCACHE_MCFG) Data Hit Counter */\r
+/* -------- HCACHE_MEN : (HCACHE Offset: 0x2C) Monitor Enable Register -------- */\r
+#define HCACHE_MEN_MENABLE (0x1u << 0) /**< \brief (HCACHE_MEN) Monitor Enable */\r
+#define HCACHE_MEN_MENABLE_DIS (0x0u << 0) /**< \brief (HCACHE_MEN) Disable Monitor Counter */\r
+#define HCACHE_MEN_MENABLE_EN (0x1u << 0) /**< \brief (HCACHE_MEN) Enable Monitor Counter */\r
+/* -------- HCACHE_MCTRL : (HCACHE Offset: 0x30) Monitor Control Register -------- */\r
+#define HCACHE_MCTRL_SWRST (0x1u << 0) /**< \brief (HCACHE_MCTRL) Monitor Software Reset */\r
+#define HCACHE_MCTRL_SWRST_NO (0x0u << 0) /**< \brief (HCACHE_MCTRL) No effect */\r
+#define HCACHE_MCTRL_SWRST_YES (0x1u << 0) /**< \brief (HCACHE_MCTRL) Reset event counter register */\r
+/* -------- HCACHE_MSR : (HCACHE Offset: 0x34) Monitor Status Register -------- */\r
+#define HCACHE_MSR_EVENTCNT_Pos 0\r
+#define HCACHE_MSR_EVENTCNT_Msk (0xFFFFFFFFu << HCACHE_MSR_EVENTCNT_Pos) /**< \brief (HCACHE_MSR) Monitor Event Counter */\r
+#define HCACHE_MSR_EVENTCNT(value) ((HCACHE_MSR_EVENTCNT_Msk & ((value) << HCACHE_MSR_EVENTCNT_Pos)))\r
+/* -------- HCACHE_VERSION : (HCACHE Offset: 0xFC) Version Register -------- */\r
+#define HCACHE_VERSION_VERSION_Pos 0\r
+#define HCACHE_VERSION_VERSION_Msk (0xFFFu << HCACHE_VERSION_VERSION_Pos) /**< \brief (HCACHE_VERSION) VERSION */\r
+#define HCACHE_VERSION_VERSION(value) ((HCACHE_VERSION_VERSION_Msk & ((value) << HCACHE_VERSION_VERSION_Pos)))\r
+#define HCACHE_VERSION_MFN_Pos 16\r
+#define HCACHE_VERSION_MFN_Msk (0xFu << HCACHE_VERSION_MFN_Pos) /**< \brief (HCACHE_VERSION) MFN */\r
+#define HCACHE_VERSION_MFN(value) ((HCACHE_VERSION_MFN_Msk & ((value) << HCACHE_VERSION_MFN_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR HMATRIXB */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_HMATRIXB HSB Matrix */\r
+/*@{*/\r
+\r
+#define REV_HMATRIXB 0x130\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief HmatrixbMcfg hardware registers */\r
+typedef struct {\r
+ RwReg HMATRIXB_MCFG; /**< \brief (HmatrixbMcfg Offset: 0x000) Master Configuration Register 0 */\r
+} HmatrixbMcfg;\r
+/** \brief HmatrixbPrs hardware registers */\r
+typedef struct {\r
+ RwReg HMATRIXB_PRAS; /**< \brief (HmatrixbPrs Offset: 0x000) Priority Register A for Slave 0 */\r
+ RwReg HMATRIXB_PRBS; /**< \brief (HmatrixbPrs Offset: 0x004) Priority Register B for Slave 0 */\r
+} HmatrixbPrs;\r
+/** \brief HmatrixbScfg hardware registers */\r
+typedef struct {\r
+ RwReg HMATRIXB_SCFG; /**< \brief (HmatrixbScfg Offset: 0x000) Slave Configuration Register 0 */\r
+} HmatrixbScfg;\r
+/** \brief HmatrixbSfr hardware registers */\r
+typedef struct {\r
+ RwReg HMATRIXB_SFR; /**< \brief (HmatrixbSfr Offset: 0x000) Special Function Register 0 */\r
+} HmatrixbSfr;\r
+/** \brief HMATRIXB hardware registers */\r
+typedef struct {\r
+ HmatrixbMcfg HMATRIXB_MCFG[16]; /**< \brief (HMATRIXB Offset: 0x000) HmatrixbMcfg groups */\r
+ HmatrixbScfg HMATRIXB_SCFG[16]; /**< \brief (HMATRIXB Offset: 0x040) HmatrixbScfg groups */\r
+ HmatrixbPrs HMATRIXB_PRS[16]; /**< \brief (HMATRIXB Offset: 0x080) HmatrixbPrs groups */\r
+ RwReg HMATRIXB_MRCR; /**< \brief (HMATRIXB Offset: 0x100) Master Remap Control Register */\r
+ RoReg Reserved1[3];\r
+ HmatrixbSfr HMATRIXB_SFR[16]; /**< \brief (HMATRIXB Offset: 0x110) HmatrixbSfr groups */\r
+} Hmatrixb;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- HMATRIXB_MCFG : (HMATRIXB Offset: 0x000) Mcfg Master Configuration Register 0 -------- */\r
+#define HMATRIXB_MCFG_ULBT_Pos 0\r
+#define HMATRIXB_MCFG_ULBT_Msk (0x7u << HMATRIXB_MCFG_ULBT_Pos) /**< \brief (HMATRIXB_MCFG) Undefined Length Burst Type */\r
+#define HMATRIXB_MCFG_ULBT(value) ((HMATRIXB_MCFG_ULBT_Msk & ((value) << HMATRIXB_MCFG_ULBT_Pos)))\r
+#define HMATRIXB_MCFG_ULBT_INFINITE (0x0u << 0) /**< \brief (HMATRIXB_MCFG) Infinite Length */\r
+#define HMATRIXB_MCFG_ULBT_SINGLE (0x1u << 0) /**< \brief (HMATRIXB_MCFG) Single Access */\r
+#define HMATRIXB_MCFG_ULBT_FOUR_BEAT (0x2u << 0) /**< \brief (HMATRIXB_MCFG) Four Beat Burst */\r
+#define HMATRIXB_MCFG_ULBT_EIGHT_BEAT (0x3u << 0) /**< \brief (HMATRIXB_MCFG) Eight Beat Burst */\r
+#define HMATRIXB_MCFG_ULBT_SIXTEEN_BEAT (0x4u << 0) /**< \brief (HMATRIXB_MCFG) Sixteen Beat Burst */\r
+/* -------- HMATRIXB_SCFG : (HMATRIXB Offset: 0x040) Scfg Slave Configuration Register 0 -------- */\r
+#define HMATRIXB_SCFG_SLOT_CYCLE_Pos 0\r
+#define HMATRIXB_SCFG_SLOT_CYCLE_Msk (0xFFu << HMATRIXB_SCFG_SLOT_CYCLE_Pos) /**< \brief (HMATRIXB_SCFG) Maximum Number of Allowed Cycles for a Burst */\r
+#define HMATRIXB_SCFG_SLOT_CYCLE(value) ((HMATRIXB_SCFG_SLOT_CYCLE_Msk & ((value) << HMATRIXB_SCFG_SLOT_CYCLE_Pos)))\r
+#define HMATRIXB_SCFG_DEFMSTR_TYPE_Pos 16\r
+#define HMATRIXB_SCFG_DEFMSTR_TYPE_Msk (0x3u << HMATRIXB_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (HMATRIXB_SCFG) Default Master Type */\r
+#define HMATRIXB_SCFG_DEFMSTR_TYPE(value) ((HMATRIXB_SCFG_DEFMSTR_TYPE_Msk & ((value) << HMATRIXB_SCFG_DEFMSTR_TYPE_Pos)))\r
+#define HMATRIXB_SCFG_DEFMSTR_TYPE_NO_DEFAULT (0x0u << 16) /**< \brief (HMATRIXB_SCFG) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. */\r
+#define HMATRIXB_SCFG_DEFMSTR_TYPE_LAST_DEFAULT (0x1u << 16) /**< \brief (HMATRIXB_SCFG) Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. */\r
+#define HMATRIXB_SCFG_DEFMSTR_TYPE_FIXED_DEFAULT (0x2u << 16) /**< \brief (HMATRIXB_SCFG) Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. */\r
+#define HMATRIXB_SCFG_FIXED_DEFMSTR_Pos 18\r
+#define HMATRIXB_SCFG_FIXED_DEFMSTR_Msk (0xFu << HMATRIXB_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (HMATRIXB_SCFG) Fixed Index of Default Master */\r
+#define HMATRIXB_SCFG_FIXED_DEFMSTR(value) ((HMATRIXB_SCFG_FIXED_DEFMSTR_Msk & ((value) << HMATRIXB_SCFG_FIXED_DEFMSTR_Pos)))\r
+#define HMATRIXB_SCFG_ARBT (0x1u << 24) /**< \brief (HMATRIXB_SCFG) Arbitration Type */\r
+#define HMATRIXB_SCFG_ARBT_ROUND_ROBIN (0x0u << 24) /**< \brief (HMATRIXB_SCFG) Round-Robin Arbitration */\r
+#define HMATRIXB_SCFG_ARBT_FIXED_PRIORITY (0x1u << 24) /**< \brief (HMATRIXB_SCFG) Fixed Priority Arbitration */\r
+/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) Prs Priority Register A for Slave 0 -------- */\r
+#define HMATRIXB_PRAS_M0PR_Pos 0\r
+#define HMATRIXB_PRAS_M0PR_Msk (0xFu << HMATRIXB_PRAS_M0PR_Pos) /**< \brief (HMATRIXB_PRAS) Master 0 Priority */\r
+#define HMATRIXB_PRAS_M0PR(value) ((HMATRIXB_PRAS_M0PR_Msk & ((value) << HMATRIXB_PRAS_M0PR_Pos)))\r
+#define HMATRIXB_PRAS_M1PR_Pos 4\r
+#define HMATRIXB_PRAS_M1PR_Msk (0xFu << HMATRIXB_PRAS_M1PR_Pos) /**< \brief (HMATRIXB_PRAS) Master 1 Priority */\r
+#define HMATRIXB_PRAS_M1PR(value) ((HMATRIXB_PRAS_M1PR_Msk & ((value) << HMATRIXB_PRAS_M1PR_Pos)))\r
+#define HMATRIXB_PRAS_M2PR_Pos 8\r
+#define HMATRIXB_PRAS_M2PR_Msk (0xFu << HMATRIXB_PRAS_M2PR_Pos) /**< \brief (HMATRIXB_PRAS) Master 2 Priority */\r
+#define HMATRIXB_PRAS_M2PR(value) ((HMATRIXB_PRAS_M2PR_Msk & ((value) << HMATRIXB_PRAS_M2PR_Pos)))\r
+#define HMATRIXB_PRAS_M3PR_Pos 12\r
+#define HMATRIXB_PRAS_M3PR_Msk (0xFu << HMATRIXB_PRAS_M3PR_Pos) /**< \brief (HMATRIXB_PRAS) Master 3 Priority */\r
+#define HMATRIXB_PRAS_M3PR(value) ((HMATRIXB_PRAS_M3PR_Msk & ((value) << HMATRIXB_PRAS_M3PR_Pos)))\r
+#define HMATRIXB_PRAS_M4PR_Pos 16\r
+#define HMATRIXB_PRAS_M4PR_Msk (0xFu << HMATRIXB_PRAS_M4PR_Pos) /**< \brief (HMATRIXB_PRAS) Master 4 Priority */\r
+#define HMATRIXB_PRAS_M4PR(value) ((HMATRIXB_PRAS_M4PR_Msk & ((value) << HMATRIXB_PRAS_M4PR_Pos)))\r
+#define HMATRIXB_PRAS_M5PR_Pos 20\r
+#define HMATRIXB_PRAS_M5PR_Msk (0xFu << HMATRIXB_PRAS_M5PR_Pos) /**< \brief (HMATRIXB_PRAS) Master 5 Priority */\r
+#define HMATRIXB_PRAS_M5PR(value) ((HMATRIXB_PRAS_M5PR_Msk & ((value) << HMATRIXB_PRAS_M5PR_Pos)))\r
+#define HMATRIXB_PRAS_M6PR_Pos 24\r
+#define HMATRIXB_PRAS_M6PR_Msk (0xFu << HMATRIXB_PRAS_M6PR_Pos) /**< \brief (HMATRIXB_PRAS) Master 6 Priority */\r
+#define HMATRIXB_PRAS_M6PR(value) ((HMATRIXB_PRAS_M6PR_Msk & ((value) << HMATRIXB_PRAS_M6PR_Pos)))\r
+#define HMATRIXB_PRAS_M7PR_Pos 28\r
+#define HMATRIXB_PRAS_M7PR_Msk (0xFu << HMATRIXB_PRAS_M7PR_Pos) /**< \brief (HMATRIXB_PRAS) Master 7 Priority */\r
+#define HMATRIXB_PRAS_M7PR(value) ((HMATRIXB_PRAS_M7PR_Msk & ((value) << HMATRIXB_PRAS_M7PR_Pos)))\r
+/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) Prs Priority Register B for Slave 0 -------- */\r
+#define HMATRIXB_PRBS_M8PR_Pos 0\r
+#define HMATRIXB_PRBS_M8PR_Msk (0xFu << HMATRIXB_PRBS_M8PR_Pos) /**< \brief (HMATRIXB_PRBS) Master 8 Priority */\r
+#define HMATRIXB_PRBS_M8PR(value) ((HMATRIXB_PRBS_M8PR_Msk & ((value) << HMATRIXB_PRBS_M8PR_Pos)))\r
+#define HMATRIXB_PRBS_M9PR_Pos 4\r
+#define HMATRIXB_PRBS_M9PR_Msk (0xFu << HMATRIXB_PRBS_M9PR_Pos) /**< \brief (HMATRIXB_PRBS) Master 9 Priority */\r
+#define HMATRIXB_PRBS_M9PR(value) ((HMATRIXB_PRBS_M9PR_Msk & ((value) << HMATRIXB_PRBS_M9PR_Pos)))\r
+#define HMATRIXB_PRBS_M10PR_Pos 8\r
+#define HMATRIXB_PRBS_M10PR_Msk (0xFu << HMATRIXB_PRBS_M10PR_Pos) /**< \brief (HMATRIXB_PRBS) Master 10 Priority */\r
+#define HMATRIXB_PRBS_M10PR(value) ((HMATRIXB_PRBS_M10PR_Msk & ((value) << HMATRIXB_PRBS_M10PR_Pos)))\r
+#define HMATRIXB_PRBS_M11PR_Pos 12\r
+#define HMATRIXB_PRBS_M11PR_Msk (0xFu << HMATRIXB_PRBS_M11PR_Pos) /**< \brief (HMATRIXB_PRBS) Master 11 Priority */\r
+#define HMATRIXB_PRBS_M11PR(value) ((HMATRIXB_PRBS_M11PR_Msk & ((value) << HMATRIXB_PRBS_M11PR_Pos)))\r
+#define HMATRIXB_PRBS_M12PR_Pos 16\r
+#define HMATRIXB_PRBS_M12PR_Msk (0xFu << HMATRIXB_PRBS_M12PR_Pos) /**< \brief (HMATRIXB_PRBS) Master 12 Priority */\r
+#define HMATRIXB_PRBS_M12PR(value) ((HMATRIXB_PRBS_M12PR_Msk & ((value) << HMATRIXB_PRBS_M12PR_Pos)))\r
+#define HMATRIXB_PRBS_M13PR_Pos 20\r
+#define HMATRIXB_PRBS_M13PR_Msk (0xFu << HMATRIXB_PRBS_M13PR_Pos) /**< \brief (HMATRIXB_PRBS) Master 13 Priority */\r
+#define HMATRIXB_PRBS_M13PR(value) ((HMATRIXB_PRBS_M13PR_Msk & ((value) << HMATRIXB_PRBS_M13PR_Pos)))\r
+#define HMATRIXB_PRBS_M14PR_Pos 24\r
+#define HMATRIXB_PRBS_M14PR_Msk (0xFu << HMATRIXB_PRBS_M14PR_Pos) /**< \brief (HMATRIXB_PRBS) Master 14 Priority */\r
+#define HMATRIXB_PRBS_M14PR(value) ((HMATRIXB_PRBS_M14PR_Msk & ((value) << HMATRIXB_PRBS_M14PR_Pos)))\r
+#define HMATRIXB_PRBS_M15PR_Pos 28\r
+#define HMATRIXB_PRBS_M15PR_Msk (0xFu << HMATRIXB_PRBS_M15PR_Pos) /**< \brief (HMATRIXB_PRBS) Master 15 Priority */\r
+#define HMATRIXB_PRBS_M15PR(value) ((HMATRIXB_PRBS_M15PR_Msk & ((value) << HMATRIXB_PRBS_M15PR_Pos)))\r
+/* -------- HMATRIXB_MRCR : (HMATRIXB Offset: 0x100) Master Remap Control Register -------- */\r
+#define HMATRIXB_MRCR_RCB0 (0x1u << 0) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 0 */\r
+#define HMATRIXB_MRCR_RCB0_0 (0x0u << 0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB0_1 (0x1u << 0) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB1 (0x1u << 1) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 1 */\r
+#define HMATRIXB_MRCR_RCB1_0 (0x0u << 1) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB1_1 (0x1u << 1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB2 (0x1u << 2) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 2 */\r
+#define HMATRIXB_MRCR_RCB2_0 (0x0u << 2) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB2_1 (0x1u << 2) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB3 (0x1u << 3) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 3 */\r
+#define HMATRIXB_MRCR_RCB3_0 (0x0u << 3) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB3_1 (0x1u << 3) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB4 (0x1u << 4) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 4 */\r
+#define HMATRIXB_MRCR_RCB4_0 (0x0u << 4) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB4_1 (0x1u << 4) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB5 (0x1u << 5) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 5 */\r
+#define HMATRIXB_MRCR_RCB5_0 (0x0u << 5) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB5_1 (0x1u << 5) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB6 (0x1u << 6) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 6 */\r
+#define HMATRIXB_MRCR_RCB6_0 (0x0u << 6) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB6_1 (0x1u << 6) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB7 (0x1u << 7) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 7 */\r
+#define HMATRIXB_MRCR_RCB7_0 (0x0u << 7) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB7_1 (0x1u << 7) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB8 (0x1u << 8) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 8 */\r
+#define HMATRIXB_MRCR_RCB8_0 (0x0u << 8) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB8_1 (0x1u << 8) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB9 (0x1u << 9) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 9 */\r
+#define HMATRIXB_MRCR_RCB9_0 (0x0u << 9) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB9_1 (0x1u << 9) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB10 (0x1u << 10) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 10 */\r
+#define HMATRIXB_MRCR_RCB10_0 (0x0u << 10) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB10_1 (0x1u << 10) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB11 (0x1u << 11) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 11 */\r
+#define HMATRIXB_MRCR_RCB11_0 (0x0u << 11) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB11_1 (0x1u << 11) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB12 (0x1u << 12) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 12 */\r
+#define HMATRIXB_MRCR_RCB12_0 (0x0u << 12) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB12_1 (0x1u << 12) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB13 (0x1u << 13) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 13 */\r
+#define HMATRIXB_MRCR_RCB13_0 (0x0u << 13) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB13_1 (0x1u << 13) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB14 (0x1u << 14) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 14 */\r
+#define HMATRIXB_MRCR_RCB14_0 (0x0u << 14) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB14_1 (0x1u << 14) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB15 (0x1u << 15) /**< \brief (HMATRIXB_MRCR) Remap Command bit for Master 15 */\r
+#define HMATRIXB_MRCR_RCB15_0 (0x0u << 15) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */\r
+#define HMATRIXB_MRCR_RCB15_1 (0x1u << 15) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */\r
+/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) Sfr Special Function Register 0 -------- */\r
+#define HMATRIXB_SFR_SFR_Pos 0\r
+#define HMATRIXB_SFR_SFR_Msk (0xFFFFFFFFu << HMATRIXB_SFR_SFR_Pos) /**< \brief (HMATRIXB_SFR) Special Function Register */\r
+#define HMATRIXB_SFR_SFR(value) ((HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR IISC */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_IISC Inter-IC Sound (I2S) Controller */\r
+/*@{*/\r
+\r
+#define REV_IISC 0x100\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief IISC hardware registers */\r
+typedef struct {\r
+ WoReg IISC_CR; /**< \brief (IISC Offset: 0x00) Control Register */\r
+ RwReg IISC_MR; /**< \brief (IISC Offset: 0x04) Mode Register */\r
+ RoReg IISC_SR; /**< \brief (IISC Offset: 0x08) Status Register */\r
+ WoReg IISC_SCR; /**< \brief (IISC Offset: 0x0C) Status Clear Register */\r
+ WoReg IISC_SSR; /**< \brief (IISC Offset: 0x10) Status Set Register */\r
+ WoReg IISC_IER; /**< \brief (IISC Offset: 0x14) Interrupt Enable Register */\r
+ WoReg IISC_IDR; /**< \brief (IISC Offset: 0x18) Interrupt Disable Register */\r
+ RoReg IISC_IMR; /**< \brief (IISC Offset: 0x1C) Interrupt Mask Register */\r
+ RoReg IISC_RHR; /**< \brief (IISC Offset: 0x20) Receive Holding Register */\r
+ WoReg IISC_THR; /**< \brief (IISC Offset: 0x24) Transmit Holding Register */\r
+ RoReg IISC_VERSION; /**< \brief (IISC Offset: 0x28) Version Register */\r
+ RoReg IISC_PARAMETER; /**< \brief (IISC Offset: 0x2C) Parameter Register */\r
+} Iisc;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- IISC_CR : (IISC Offset: 0x00) Control Register -------- */\r
+#define IISC_CR_RXEN (0x1u << 0) /**< \brief (IISC_CR) Receive Enable */\r
+#define IISC_CR_RXEN_OFF (0x0u << 0) /**< \brief (IISC_CR) No effect */\r
+#define IISC_CR_RXEN_ON (0x1u << 0) /**< \brief (IISC_CR) Enables Data Receive if RXDIS is not set */\r
+#define IISC_CR_RXDIS (0x1u << 1) /**< \brief (IISC_CR) Receive Disable */\r
+#define IISC_CR_RXDIS_OFF (0x0u << 1) /**< \brief (IISC_CR) No effect */\r
+#define IISC_CR_RXDIS_ON (0x1u << 1) /**< \brief (IISC_CR) Disables Data Receive */\r
+#define IISC_CR_CKEN (0x1u << 2) /**< \brief (IISC_CR) Clocks Enable */\r
+#define IISC_CR_CKEN_OFF (0x0u << 2) /**< \brief (IISC_CR) No effect */\r
+#define IISC_CR_CKEN_ON (0x1u << 2) /**< \brief (IISC_CR) Enables clocks if CKDIS is not set */\r
+#define IISC_CR_CKDIS (0x1u << 3) /**< \brief (IISC_CR) Clocks Disable */\r
+#define IISC_CR_CKDIS_OFF (0x0u << 3) /**< \brief (IISC_CR) No effect */\r
+#define IISC_CR_CKDIS_ON (0x1u << 3) /**< \brief (IISC_CR) Disables clocks */\r
+#define IISC_CR_TXEN (0x1u << 4) /**< \brief (IISC_CR) Transmit Enable */\r
+#define IISC_CR_TXEN_OFF (0x0u << 4) /**< \brief (IISC_CR) No effect */\r
+#define IISC_CR_TXEN_ON (0x1u << 4) /**< \brief (IISC_CR) Enables Data Transmit if TXDIS is not set */\r
+#define IISC_CR_TXDIS (0x1u << 5) /**< \brief (IISC_CR) Transmit Disable */\r
+#define IISC_CR_TXDIS_OFF (0x0u << 5) /**< \brief (IISC_CR) No effect */\r
+#define IISC_CR_TXDIS_ON (0x1u << 5) /**< \brief (IISC_CR) Disables Data Transmit */\r
+#define IISC_CR_SWRST (0x1u << 7) /**< \brief (IISC_CR) Software Reset */\r
+#define IISC_CR_SWRST_OFF (0x0u << 7) /**< \brief (IISC_CR) No effect */\r
+#define IISC_CR_SWRST_ON (0x1u << 7) /**< \brief (IISC_CR) Performs a software reset. Has priority on any other bit in CR */\r
+/* -------- IISC_MR : (IISC Offset: 0x04) Mode Register -------- */\r
+#define IISC_MR_MODE (0x1u << 0) /**< \brief (IISC_MR) Master/Slave/Controller Mode */\r
+#define IISC_MR_MODE_SLAVE (0x0u << 0) /**< \brief (IISC_MR) Slave mode (only serial data handled, clocks received from external master or controller) */\r
+#define IISC_MR_MODE_MASTER (0x1u << 0) /**< \brief (IISC_MR) Master mode (clocks generated and output by IISC, serial data handled if CR.RXEN and/or CR.TXEN written to 1) */\r
+#define IISC_MR_DATALENGTH_Pos 2\r
+#define IISC_MR_DATALENGTH_Msk (0x7u << IISC_MR_DATALENGTH_Pos) /**< \brief (IISC_MR) Data Word Length */\r
+#define IISC_MR_DATALENGTH(value) ((IISC_MR_DATALENGTH_Msk & ((value) << IISC_MR_DATALENGTH_Pos)))\r
+#define IISC_MR_DATALENGTH_32 (0x0u << 2) /**< \brief (IISC_MR) 32 bits */\r
+#define IISC_MR_DATALENGTH_24 (0x1u << 2) /**< \brief (IISC_MR) 24 bits */\r
+#define IISC_MR_DATALENGTH_20 (0x2u << 2) /**< \brief (IISC_MR) 20 bits */\r
+#define IISC_MR_DATALENGTH_18 (0x3u << 2) /**< \brief (IISC_MR) 18 bits */\r
+#define IISC_MR_DATALENGTH_16 (0x4u << 2) /**< \brief (IISC_MR) 16 bits */\r
+#define IISC_MR_DATALENGTH_16C (0x5u << 2) /**< \brief (IISC_MR) 16 bits compact stereo */\r
+#define IISC_MR_DATALENGTH_8 (0x6u << 2) /**< \brief (IISC_MR) 8 bits */\r
+#define IISC_MR_DATALENGTH_8C (0x7u << 2) /**< \brief (IISC_MR) 8 bits compact stereo */\r
+#define IISC_MR_RXMONO (0x1u << 8) /**< \brief (IISC_MR) Receiver Mono */\r
+#define IISC_MR_RXMONO_STEREO (0x0u << 8) /**< \brief (IISC_MR) Normal mode */\r
+#define IISC_MR_RXMONO_MONO (0x1u << 8) /**< \brief (IISC_MR) Left channel data is duplicated to right channel */\r
+#define IISC_MR_RXDMA (0x1u << 9) /**< \brief (IISC_MR) Single or Multiple DMA Channels for Receiver */\r
+#define IISC_MR_RXDMA_SINGLE (0x0u << 9) /**< \brief (IISC_MR) Single DMA channel */\r
+#define IISC_MR_RXDMA_MULTIPLE (0x1u << 9) /**< \brief (IISC_MR) One DMA channel per data channel */\r
+#define IISC_MR_RXLOOP (0x1u << 10) /**< \brief (IISC_MR) Loop-back Test Mode */\r
+#define IISC_MR_RXLOOP_OFF (0x0u << 10) /**< \brief (IISC_MR) Normal mode */\r
+#define IISC_MR_RXLOOP_ON (0x1u << 10) /**< \brief (IISC_MR) ISDO internally connected to ISDI */\r
+#define IISC_MR_TXMONO (0x1u << 12) /**< \brief (IISC_MR) Transmitter Mono */\r
+#define IISC_MR_TXMONO_STEREO (0x0u << 12) /**< \brief (IISC_MR) Normal mode */\r
+#define IISC_MR_TXMONO_MONO (0x1u << 12) /**< \brief (IISC_MR) Left channel data is duplicated to right channel */\r
+#define IISC_MR_TXDMA (0x1u << 13) /**< \brief (IISC_MR) Single or Multiple DMA Channels for Transmitter */\r
+#define IISC_MR_TXDMA_SINGLE (0x0u << 13) /**< \brief (IISC_MR) Single DMA channel */\r
+#define IISC_MR_TXDMA_MULTIPLE (0x1u << 13) /**< \brief (IISC_MR) One DMA channel per data channel */\r
+#define IISC_MR_TXSAME (0x1u << 14) /**< \brief (IISC_MR) Transmit Data when Underrun */\r
+#define IISC_MR_TXSAME_ZERO (0x0u << 14) /**< \brief (IISC_MR) Zero data transmitted in case of underrun */\r
+#define IISC_MR_TXSAME_SAME (0x1u << 14) /**< \brief (IISC_MR) Last data transmitted in case of underrun */\r
+#define IISC_MR_IMCKFS_Pos 24\r
+#define IISC_MR_IMCKFS_Msk (0x3Fu << IISC_MR_IMCKFS_Pos) /**< \brief (IISC_MR) Master Clock to fs Ratio */\r
+#define IISC_MR_IMCKFS(value) ((IISC_MR_IMCKFS_Msk & ((value) << IISC_MR_IMCKFS_Pos)))\r
+#define IISC_MR_IMCKFS_16 (0x0u << 24) /**< \brief (IISC_MR) 16 fs */\r
+#define IISC_MR_IMCKFS_32 (0x1u << 24) /**< \brief (IISC_MR) 32 fs */\r
+#define IISC_MR_IMCKFS_64 (0x3u << 24) /**< \brief (IISC_MR) 64 fs */\r
+#define IISC_MR_IMCKFS_128 (0x7u << 24) /**< \brief (IISC_MR) 128 fs */\r
+#define IISC_MR_IMCKFS_256 (0xFu << 24) /**< \brief (IISC_MR) 256 fs */\r
+#define IISC_MR_IMCKFS_384 (0x17u << 24) /**< \brief (IISC_MR) 384 fs */\r
+#define IISC_MR_IMCKFS_512 (0x1Fu << 24) /**< \brief (IISC_MR) 512 fs */\r
+#define IISC_MR_IMCKFS_768 (0x2Fu << 24) /**< \brief (IISC_MR) 768 fs */\r
+#define IISC_MR_IMCKFS_1024 (0x3Fu << 24) /**< \brief (IISC_MR) 1024 fs */\r
+#define IISC_MR_IMCKMODE (0x1u << 30) /**< \brief (IISC_MR) Master Clock Mode */\r
+#define IISC_MR_IMCKMODE_NO_IMCK (0x0u << 30) /**< \brief (IISC_MR) No IMCK generated */\r
+#define IISC_MR_IMCKMODE_IMCK (0x1u << 30) /**< \brief (IISC_MR) IMCK generated */\r
+#define IISC_MR_IWS24 (0x1u << 31) /**< \brief (IISC_MR) IWS Data Slot Width */\r
+#define IISC_MR_IWS24_32 (0x0u << 31) /**< \brief (IISC_MR) IWS Data Slot is 32-bit wide for DATALENGTH=18/20/24-bit */\r
+#define IISC_MR_IWS24_24 (0x1u << 31) /**< \brief (IISC_MR) IWS Data Slot is 24-bit wide for DATALENGTH=18/20/24-bit */\r
+/* -------- IISC_SR : (IISC Offset: 0x08) Status Register -------- */\r
+#define IISC_SR_RXEN (0x1u << 0) /**< \brief (IISC_SR) Receive Enable */\r
+#define IISC_SR_RXEN_OFF (0x0u << 0) /**< \brief (IISC_SR) Receiver is effectively disabled, following a CR.RXDIS or CR.SWRST request */\r
+#define IISC_SR_RXEN_ON (0x1u << 0) /**< \brief (IISC_SR) Receiver is effectively enabled, following a CR.RXEN request */\r
+#define IISC_SR_RXRDY (0x1u << 1) /**< \brief (IISC_SR) Receive Ready */\r
+#define IISC_SR_RXRDY_EMPTY (0x0u << 1) /**< \brief (IISC_SR) The register RHR is empty and can't be read */\r
+#define IISC_SR_RXRDY_FULL (0x1u << 1) /**< \brief (IISC_SR) The register RHR is full and is ready to be read */\r
+#define IISC_SR_RXOR (0x1u << 2) /**< \brief (IISC_SR) Receive Overrun */\r
+#define IISC_SR_RXOR_NO (0x0u << 2) /**< \brief (IISC_SR) No overrun */\r
+#define IISC_SR_RXOR_YES (0x1u << 2) /**< \brief (IISC_SR) The previous received data has not been read. This data is lost */\r
+#define IISC_SR_TXEN (0x1u << 4) /**< \brief (IISC_SR) Transmit Enable */\r
+#define IISC_SR_TXEN_OFF (0x0u << 4) /**< \brief (IISC_SR) Transmitter is effectively disabled, following a CR.TXDIS or CR.SWRST request */\r
+#define IISC_SR_TXEN_ON (0x1u << 4) /**< \brief (IISC_SR) Transmitter is effectively enabled, following a CR.TXEN request */\r
+#define IISC_SR_TXRDY (0x1u << 5) /**< \brief (IISC_SR) Transmit Ready */\r
+#define IISC_SR_TXRDY_FULL (0x0u << 5) /**< \brief (IISC_SR) The register THR is full and can't be written */\r
+#define IISC_SR_TXRDY_EMPTY (0x1u << 5) /**< \brief (IISC_SR) The register THR is empty and is ready to be written */\r
+#define IISC_SR_TXUR (0x1u << 6) /**< \brief (IISC_SR) Transmit Underrun */\r
+#define IISC_SR_TXUR_NO (0x0u << 6) /**< \brief (IISC_SR) No underrun */\r
+#define IISC_SR_TXUR_YES (0x1u << 6) /**< \brief (IISC_SR) The last bit of the last data written to the register THR has been set. Until the next write to THR, data will be sent according to MR.TXSAME field */\r
+#define IISC_SR_RXORCH_Pos 8\r
+#define IISC_SR_RXORCH_Msk (0x3u << IISC_SR_RXORCH_Pos) /**< \brief (IISC_SR) Receive Overrun Channels */\r
+#define IISC_SR_RXORCH(value) ((IISC_SR_RXORCH_Msk & ((value) << IISC_SR_RXORCH_Pos)))\r
+#define IISC_SR_RXORCH_LEFT (0x0u << 8) /**< \brief (IISC_SR) Overrun first occurred on left channel */\r
+#define IISC_SR_RXORCH_RIGHT (0x1u << 8) /**< \brief (IISC_SR) Overrun first occurred on right channel */\r
+#define IISC_SR_TXURCH_Pos 20\r
+#define IISC_SR_TXURCH_Msk (0x3u << IISC_SR_TXURCH_Pos) /**< \brief (IISC_SR) Transmit Underrun Channels */\r
+#define IISC_SR_TXURCH(value) ((IISC_SR_TXURCH_Msk & ((value) << IISC_SR_TXURCH_Pos)))\r
+#define IISC_SR_TXURCH_LEFT (0x0u << 20) /**< \brief (IISC_SR) Underrun first occurred on left channel */\r
+#define IISC_SR_TXURCH_RIGHT (0x1u << 20) /**< \brief (IISC_SR) Underrun first occurred on right channel */\r
+/* -------- IISC_SCR : (IISC Offset: 0x0C) Status Clear Register -------- */\r
+#define IISC_SCR_RXOR (0x1u << 2) /**< \brief (IISC_SCR) Receive Overrun */\r
+#define IISC_SCR_RXOR_NO (0x0u << 2) /**< \brief (IISC_SCR) No effect */\r
+#define IISC_SCR_RXOR_CLEAR (0x1u << 2) /**< \brief (IISC_SCR) Clears the corresponding SR bit */\r
+#define IISC_SCR_TXUR (0x1u << 6) /**< \brief (IISC_SCR) Transmit Underrun */\r
+#define IISC_SCR_TXUR_NO (0x0u << 6) /**< \brief (IISC_SCR) No effect */\r
+#define IISC_SCR_TXUR_CLEAR (0x1u << 6) /**< \brief (IISC_SCR) Clears the corresponding SR bit */\r
+#define IISC_SCR_RXORCH_Pos 8\r
+#define IISC_SCR_RXORCH_Msk (0x3u << IISC_SCR_RXORCH_Pos) /**< \brief (IISC_SCR) Receive Overrun Channels */\r
+#define IISC_SCR_RXORCH(value) ((IISC_SCR_RXORCH_Msk & ((value) << IISC_SCR_RXORCH_Pos)))\r
+#define IISC_SCR_TXURCH_Pos 20\r
+#define IISC_SCR_TXURCH_Msk (0x3u << IISC_SCR_TXURCH_Pos) /**< \brief (IISC_SCR) Transmit Underrun Channels */\r
+#define IISC_SCR_TXURCH(value) ((IISC_SCR_TXURCH_Msk & ((value) << IISC_SCR_TXURCH_Pos)))\r
+/* -------- IISC_SSR : (IISC Offset: 0x10) Status Set Register -------- */\r
+#define IISC_SSR_RXOR (0x1u << 2) /**< \brief (IISC_SSR) Receive Overrun */\r
+#define IISC_SSR_RXOR_NO (0x0u << 2) /**< \brief (IISC_SSR) No effect */\r
+#define IISC_SSR_RXOR_SET (0x1u << 2) /**< \brief (IISC_SSR) Sets corresponding SR bit */\r
+#define IISC_SSR_TXUR (0x1u << 6) /**< \brief (IISC_SSR) Transmit Underrun */\r
+#define IISC_SSR_TXUR_NO (0x0u << 6) /**< \brief (IISC_SSR) No effect */\r
+#define IISC_SSR_TXUR_SET (0x1u << 6) /**< \brief (IISC_SSR) Sets corresponding SR bit */\r
+#define IISC_SSR_RXORCH_Pos 8\r
+#define IISC_SSR_RXORCH_Msk (0x3u << IISC_SSR_RXORCH_Pos) /**< \brief (IISC_SSR) Receive Overrun Channels */\r
+#define IISC_SSR_RXORCH(value) ((IISC_SSR_RXORCH_Msk & ((value) << IISC_SSR_RXORCH_Pos)))\r
+#define IISC_SSR_TXURCH_Pos 20\r
+#define IISC_SSR_TXURCH_Msk (0x3u << IISC_SSR_TXURCH_Pos) /**< \brief (IISC_SSR) Transmit Underrun Channels */\r
+#define IISC_SSR_TXURCH(value) ((IISC_SSR_TXURCH_Msk & ((value) << IISC_SSR_TXURCH_Pos)))\r
+/* -------- IISC_IER : (IISC Offset: 0x14) Interrupt Enable Register -------- */\r
+#define IISC_IER_RXRDY (0x1u << 1) /**< \brief (IISC_IER) Receiver Ready Interrupt Enable */\r
+#define IISC_IER_RXRDY_OFF (0x0u << 1) /**< \brief (IISC_IER) No effect */\r
+#define IISC_IER_RXRDY_ON (0x1u << 1) /**< \brief (IISC_IER) Enables the corresponding interrupt */\r
+#define IISC_IER_RXOR (0x1u << 2) /**< \brief (IISC_IER) Receive Overrun Interrupt Enable */\r
+#define IISC_IER_RXOR_OFF (0x0u << 2) /**< \brief (IISC_IER) No effect */\r
+#define IISC_IER_RXOR_ON (0x1u << 2) /**< \brief (IISC_IER) Enables the corresponding interrupt */\r
+#define IISC_IER_TXRDY (0x1u << 5) /**< \brief (IISC_IER) Transmit Ready Interrupt Enable */\r
+#define IISC_IER_TXRDY_OFF (0x0u << 5) /**< \brief (IISC_IER) No effect */\r
+#define IISC_IER_TXRDY_ON (0x1u << 5) /**< \brief (IISC_IER) Enables the corresponding interrupt */\r
+#define IISC_IER_TXUR (0x1u << 6) /**< \brief (IISC_IER) Transmit Underrun Interrupt Enable */\r
+#define IISC_IER_TXUR_OFF (0x0u << 6) /**< \brief (IISC_IER) No effect */\r
+#define IISC_IER_TXUR_ON (0x1u << 6) /**< \brief (IISC_IER) Enables the corresponding interrupt */\r
+/* -------- IISC_IDR : (IISC Offset: 0x18) Interrupt Disable Register -------- */\r
+#define IISC_IDR_RXRDY (0x1u << 1) /**< \brief (IISC_IDR) Receive Ready Interrupt Disable */\r
+#define IISC_IDR_RXRDY_OFF (0x0u << 1) /**< \brief (IISC_IDR) No effect */\r
+#define IISC_IDR_RXRDY_ON (0x1u << 1) /**< \brief (IISC_IDR) Disables the corresponding interrupt */\r
+#define IISC_IDR_RXOR (0x1u << 2) /**< \brief (IISC_IDR) Receive Overrun Interrupt Disable */\r
+#define IISC_IDR_RXOR_OFF (0x0u << 2) /**< \brief (IISC_IDR) No effect */\r
+#define IISC_IDR_RXOR_ON (0x1u << 2) /**< \brief (IISC_IDR) Disables the corresponding interrupt */\r
+#define IISC_IDR_TXRDY (0x1u << 5) /**< \brief (IISC_IDR) Transmit Ready Interrupt Disable */\r
+#define IISC_IDR_TXRDY_OFF (0x0u << 5) /**< \brief (IISC_IDR) No effect */\r
+#define IISC_IDR_TXRDY_ON (0x1u << 5) /**< \brief (IISC_IDR) Disables the corresponding interrupt */\r
+#define IISC_IDR_TXUR (0x1u << 6) /**< \brief (IISC_IDR) Transmit Underrun Interrupt Disable */\r
+#define IISC_IDR_TXUR_OFF (0x0u << 6) /**< \brief (IISC_IDR) No effect */\r
+#define IISC_IDR_TXUR_ON (0x1u << 6) /**< \brief (IISC_IDR) Disables the corresponding interrupt */\r
+/* -------- IISC_IMR : (IISC Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define IISC_IMR_RXRDY (0x1u << 1) /**< \brief (IISC_IMR) Receive Ready Interrupt Mask */\r
+#define IISC_IMR_RXRDY_DISABLED (0x0u << 1) /**< \brief (IISC_IMR) The corresponding interrupt is disabled */\r
+#define IISC_IMR_RXRDY_ENABLED (0x1u << 1) /**< \brief (IISC_IMR) The corresponding interrupt is enabled */\r
+#define IISC_IMR_RXOR (0x1u << 2) /**< \brief (IISC_IMR) Receive Overrun Interrupt Mask */\r
+#define IISC_IMR_RXOR_DISABLED (0x0u << 2) /**< \brief (IISC_IMR) The corresponding interrupt is disabled */\r
+#define IISC_IMR_RXOR_ENABLED (0x1u << 2) /**< \brief (IISC_IMR) The corresponding interrupt is enabled */\r
+#define IISC_IMR_TXRDY (0x1u << 5) /**< \brief (IISC_IMR) Transmit Ready Interrupt Mask */\r
+#define IISC_IMR_TXRDY_DISABLED (0x0u << 5) /**< \brief (IISC_IMR) The corresponding interrupt is disabled */\r
+#define IISC_IMR_TXRDY_ENABLED (0x1u << 5) /**< \brief (IISC_IMR) The corresponding interrupt is enabled */\r
+#define IISC_IMR_TXUR (0x1u << 6) /**< \brief (IISC_IMR) Transmit Underrun Interrupt Mask */\r
+#define IISC_IMR_TXUR_DISABLED (0x0u << 6) /**< \brief (IISC_IMR) The corresponding interrupt is disabled */\r
+#define IISC_IMR_TXUR_ENABLED (0x1u << 6) /**< \brief (IISC_IMR) The corresponding interrupt is enabled */\r
+/* -------- IISC_RHR : (IISC Offset: 0x20) Receive Holding Register -------- */\r
+#define IISC_RHR_RDAT_Pos 0\r
+#define IISC_RHR_RDAT_Msk (0xFFFFFFFFu << IISC_RHR_RDAT_Pos) /**< \brief (IISC_RHR) Receive Data */\r
+#define IISC_RHR_RDAT(value) ((IISC_RHR_RDAT_Msk & ((value) << IISC_RHR_RDAT_Pos)))\r
+/* -------- IISC_THR : (IISC Offset: 0x24) Transmit Holding Register -------- */\r
+#define IISC_THR_TDAT_Pos 0\r
+#define IISC_THR_TDAT_Msk (0xFFFFFFFFu << IISC_THR_TDAT_Pos) /**< \brief (IISC_THR) Transmit Data */\r
+#define IISC_THR_TDAT(value) ((IISC_THR_TDAT_Msk & ((value) << IISC_THR_TDAT_Pos)))\r
+/* -------- IISC_VERSION : (IISC Offset: 0x28) Version Register -------- */\r
+#define IISC_VERSION_VERSION_Pos 0\r
+#define IISC_VERSION_VERSION_Msk (0xFFFu << IISC_VERSION_VERSION_Pos) /**< \brief (IISC_VERSION) Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. */\r
+#define IISC_VERSION_VERSION(value) ((IISC_VERSION_VERSION_Msk & ((value) << IISC_VERSION_VERSION_Pos)))\r
+#define IISC_VERSION_VARIANT_Pos 16\r
+#define IISC_VERSION_VARIANT_Msk (0xFu << IISC_VERSION_VARIANT_Pos) /**< \brief (IISC_VERSION) Reserved. Value subject to change. No functionality associated. */\r
+#define IISC_VERSION_VARIANT(value) ((IISC_VERSION_VARIANT_Msk & ((value) << IISC_VERSION_VARIANT_Pos)))\r
+/* -------- IISC_PARAMETER : (IISC Offset: 0x2C) Parameter Register -------- */\r
+#define IISC_PARAMETER_FORMAT (0x1u << 7) /**< \brief (IISC_PARAMETER) Data protocol format */\r
+#define IISC_PARAMETER_FORMAT_I2S (0x0u << 7) /**< \brief (IISC_PARAMETER) I2S format, stereo with IWS low for left channel */\r
+#define IISC_PARAMETER_NBCHAN_Pos 16\r
+#define IISC_PARAMETER_NBCHAN_Msk (0x1Fu << IISC_PARAMETER_NBCHAN_Pos) /**< \brief (IISC_PARAMETER) Maximum number of channels - 1 */\r
+#define IISC_PARAMETER_NBCHAN(value) ((IISC_PARAMETER_NBCHAN_Msk & ((value) << IISC_PARAMETER_NBCHAN_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR LCDCA */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_LCDCA LCD Controller */\r
+/*@{*/\r
+\r
+#define REV_LCDCA 0x100\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief LCDCA hardware registers */\r
+typedef struct {\r
+ WoReg LCDCA_CR; /**< \brief (LCDCA Offset: 0x00) Control Register */\r
+ RwReg LCDCA_CFG; /**< \brief (LCDCA Offset: 0x04) Configuration Register */\r
+ RwReg LCDCA_TIM; /**< \brief (LCDCA Offset: 0x08) Timing Register */\r
+ RoReg LCDCA_SR; /**< \brief (LCDCA Offset: 0x0C) Status Register */\r
+ WoReg LCDCA_SCR; /**< \brief (LCDCA Offset: 0x10) Status Clear Register */\r
+ RwReg LCDCA_DRL0; /**< \brief (LCDCA Offset: 0x14) Data Register Low 0 */\r
+ RwReg LCDCA_DRH0; /**< \brief (LCDCA Offset: 0x18) Data Register High 0 */\r
+ RwReg LCDCA_DRL1; /**< \brief (LCDCA Offset: 0x1C) Data Register Low 1 */\r
+ RwReg LCDCA_DRH1; /**< \brief (LCDCA Offset: 0x20) Data Register High 1 */\r
+ RwReg LCDCA_DRL2; /**< \brief (LCDCA Offset: 0x24) Data Register Low 2 */\r
+ RwReg LCDCA_DRH2; /**< \brief (LCDCA Offset: 0x28) Data Register High 2 */\r
+ RwReg LCDCA_DRL3; /**< \brief (LCDCA Offset: 0x2C) Data Register Low 3 */\r
+ RwReg LCDCA_DRH3; /**< \brief (LCDCA Offset: 0x30) Data Register High 3 */\r
+ WoReg LCDCA_IADR; /**< \brief (LCDCA Offset: 0x34) Indirect Access Data Register */\r
+ RwReg LCDCA_BCFG; /**< \brief (LCDCA Offset: 0x38) Blink Configuration Register */\r
+ RwReg LCDCA_CSRCFG; /**< \brief (LCDCA Offset: 0x3C) Circular Shift Register Configuration */\r
+ RwReg LCDCA_CMCFG; /**< \brief (LCDCA Offset: 0x40) Character Mapping Configuration Register */\r
+ WoReg LCDCA_CMDR; /**< \brief (LCDCA Offset: 0x44) Character Mapping Data Register */\r
+ RwReg LCDCA_ACMCFG; /**< \brief (LCDCA Offset: 0x48) Automated Character Mapping Configuration Register */\r
+ WoReg LCDCA_ACMDR; /**< \brief (LCDCA Offset: 0x4C) Automated Character Mapping Data Register */\r
+ RwReg LCDCA_ABMCFG; /**< \brief (LCDCA Offset: 0x50) Automated Bit Mapping Configuration Register */\r
+ WoReg LCDCA_ABMDR; /**< \brief (LCDCA Offset: 0x54) Automated Bit Mapping Data Register */\r
+ WoReg LCDCA_IER; /**< \brief (LCDCA Offset: 0x58) Interrupt Enable Register */\r
+ WoReg LCDCA_IDR; /**< \brief (LCDCA Offset: 0x5C) Interrupt Disable Register */\r
+ RoReg LCDCA_IMR; /**< \brief (LCDCA Offset: 0x60) Interrupt Mask Register */\r
+ RoReg LCDCA_VERSION; /**< \brief (LCDCA Offset: 0x64) Version Register */\r
+} Lcdca;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- LCDCA_CR : (LCDCA Offset: 0x00) Control Register -------- */\r
+#define LCDCA_CR_DIS (0x1u << 0) /**< \brief (LCDCA_CR) Disable */\r
+#define LCDCA_CR_EN (0x1u << 1) /**< \brief (LCDCA_CR) Enable */\r
+#define LCDCA_CR_FC0DIS (0x1u << 2) /**< \brief (LCDCA_CR) Frame Counter 0 Disable */\r
+#define LCDCA_CR_FC0EN (0x1u << 3) /**< \brief (LCDCA_CR) Frame Counter 0 Enable */\r
+#define LCDCA_CR_FC1DIS (0x1u << 4) /**< \brief (LCDCA_CR) Frame Counter 1 Disable */\r
+#define LCDCA_CR_FC1EN (0x1u << 5) /**< \brief (LCDCA_CR) Frame Counter 1 Enable */\r
+#define LCDCA_CR_FC2DIS (0x1u << 6) /**< \brief (LCDCA_CR) Frame Counter 2 Disable */\r
+#define LCDCA_CR_FC2EN (0x1u << 7) /**< \brief (LCDCA_CR) Frame Counter 2 Enable */\r
+#define LCDCA_CR_CDM (0x1u << 8) /**< \brief (LCDCA_CR) Clear Display Memory */\r
+#define LCDCA_CR_WDIS (0x1u << 9) /**< \brief (LCDCA_CR) Wake up Disable */\r
+#define LCDCA_CR_WEN (0x1u << 10) /**< \brief (LCDCA_CR) Wake up Enable */\r
+#define LCDCA_CR_BSTART (0x1u << 11) /**< \brief (LCDCA_CR) Blinking Start */\r
+#define LCDCA_CR_BSTOP (0x1u << 12) /**< \brief (LCDCA_CR) Blinking Stop */\r
+#define LCDCA_CR_CSTART (0x1u << 13) /**< \brief (LCDCA_CR) Circular Shift Start */\r
+#define LCDCA_CR_CSTOP (0x1u << 14) /**< \brief (LCDCA_CR) Circular Shift Stop */\r
+/* -------- LCDCA_CFG : (LCDCA Offset: 0x04) Configuration Register -------- */\r
+#define LCDCA_CFG_XBIAS (0x1u << 0) /**< \brief (LCDCA_CFG) External Bias Generation */\r
+#define LCDCA_CFG_WMOD (0x1u << 1) /**< \brief (LCDCA_CFG) Waveform Mode */\r
+#define LCDCA_CFG_BLANK (0x1u << 2) /**< \brief (LCDCA_CFG) Blank LCD */\r
+#define LCDCA_CFG_LOCK (0x1u << 3) /**< \brief (LCDCA_CFG) Lock */\r
+#define LCDCA_CFG_DUTY_Pos 8\r
+#define LCDCA_CFG_DUTY_Msk (0x3u << LCDCA_CFG_DUTY_Pos) /**< \brief (LCDCA_CFG) Duty Select */\r
+#define LCDCA_CFG_DUTY(value) ((LCDCA_CFG_DUTY_Msk & ((value) << LCDCA_CFG_DUTY_Pos)))\r
+#define LCDCA_CFG_FCST_Pos 16\r
+#define LCDCA_CFG_FCST_Msk (0x3Fu << LCDCA_CFG_FCST_Pos) /**< \brief (LCDCA_CFG) Fine Contrast */\r
+#define LCDCA_CFG_FCST(value) ((LCDCA_CFG_FCST_Msk & ((value) << LCDCA_CFG_FCST_Pos)))\r
+#define LCDCA_CFG_NSU_Pos 24\r
+#define LCDCA_CFG_NSU_Msk (0x3Fu << LCDCA_CFG_NSU_Pos) /**< \brief (LCDCA_CFG) Number of Segment Terminals in Use */\r
+#define LCDCA_CFG_NSU(value) ((LCDCA_CFG_NSU_Msk & ((value) << LCDCA_CFG_NSU_Pos)))\r
+/* -------- LCDCA_TIM : (LCDCA Offset: 0x08) Timing Register -------- */\r
+#define LCDCA_TIM_PRESC (0x1u << 0) /**< \brief (LCDCA_TIM) LCD Prescaler Select */\r
+#define LCDCA_TIM_CLKDIV_Pos 1\r
+#define LCDCA_TIM_CLKDIV_Msk (0x7u << LCDCA_TIM_CLKDIV_Pos) /**< \brief (LCDCA_TIM) LCD Clock Division */\r
+#define LCDCA_TIM_CLKDIV(value) ((LCDCA_TIM_CLKDIV_Msk & ((value) << LCDCA_TIM_CLKDIV_Pos)))\r
+#define LCDCA_TIM_FC0_Pos 8\r
+#define LCDCA_TIM_FC0_Msk (0x1Fu << LCDCA_TIM_FC0_Pos) /**< \brief (LCDCA_TIM) Frame Counter 0 */\r
+#define LCDCA_TIM_FC0(value) ((LCDCA_TIM_FC0_Msk & ((value) << LCDCA_TIM_FC0_Pos)))\r
+#define LCDCA_TIM_FC0PB (0x1u << 13) /**< \brief (LCDCA_TIM) Frame Counter 0 Prescaler Bypass */\r
+#define LCDCA_TIM_FC1_Pos 16\r
+#define LCDCA_TIM_FC1_Msk (0x1Fu << LCDCA_TIM_FC1_Pos) /**< \brief (LCDCA_TIM) Frame Counter 1 */\r
+#define LCDCA_TIM_FC1(value) ((LCDCA_TIM_FC1_Msk & ((value) << LCDCA_TIM_FC1_Pos)))\r
+#define LCDCA_TIM_FC2_Pos 24\r
+#define LCDCA_TIM_FC2_Msk (0x1Fu << LCDCA_TIM_FC2_Pos) /**< \brief (LCDCA_TIM) Frame Counter 2 */\r
+#define LCDCA_TIM_FC2(value) ((LCDCA_TIM_FC2_Msk & ((value) << LCDCA_TIM_FC2_Pos)))\r
+/* -------- LCDCA_SR : (LCDCA Offset: 0x0C) Status Register -------- */\r
+#define LCDCA_SR_FC0R (0x1u << 0) /**< \brief (LCDCA_SR) Frame Counter 0 Rollover */\r
+#define LCDCA_SR_FC0S (0x1u << 1) /**< \brief (LCDCA_SR) Frame Counter 0 Status */\r
+#define LCDCA_SR_FC1S (0x1u << 2) /**< \brief (LCDCA_SR) Frame Counter 1 Status */\r
+#define LCDCA_SR_FC2S (0x1u << 3) /**< \brief (LCDCA_SR) Frame Counter 2 Status */\r
+#define LCDCA_SR_EN (0x1u << 4) /**< \brief (LCDCA_SR) LCDCA Status */\r
+#define LCDCA_SR_WEN (0x1u << 5) /**< \brief (LCDCA_SR) Wake up Status */\r
+#define LCDCA_SR_BLKS (0x1u << 6) /**< \brief (LCDCA_SR) Blink Status */\r
+#define LCDCA_SR_CSRS (0x1u << 7) /**< \brief (LCDCA_SR) Circular Shift Register Status */\r
+#define LCDCA_SR_CPS (0x1u << 8) /**< \brief (LCDCA_SR) Charge Pump Status */\r
+/* -------- LCDCA_SCR : (LCDCA Offset: 0x10) Status Clear Register -------- */\r
+#define LCDCA_SCR_FC0R (0x1u << 0) /**< \brief (LCDCA_SCR) Frame Counter 0 Rollover */\r
+/* -------- LCDCA_DRL0 : (LCDCA Offset: 0x14) Data Register Low 0 -------- */\r
+#define LCDCA_DRL0_DATA_Pos 0\r
+#define LCDCA_DRL0_DATA_Msk (0xFFFFFFFFu << LCDCA_DRL0_DATA_Pos) /**< \brief (LCDCA_DRL0) Segments Value */\r
+#define LCDCA_DRL0_DATA(value) ((LCDCA_DRL0_DATA_Msk & ((value) << LCDCA_DRL0_DATA_Pos)))\r
+/* -------- LCDCA_DRH0 : (LCDCA Offset: 0x18) Data Register High 0 -------- */\r
+#define LCDCA_DRH0_DATA_Pos 0\r
+#define LCDCA_DRH0_DATA_Msk (0xFFu << LCDCA_DRH0_DATA_Pos) /**< \brief (LCDCA_DRH0) Segments Value */\r
+#define LCDCA_DRH0_DATA(value) ((LCDCA_DRH0_DATA_Msk & ((value) << LCDCA_DRH0_DATA_Pos)))\r
+/* -------- LCDCA_DRL1 : (LCDCA Offset: 0x1C) Data Register Low 1 -------- */\r
+#define LCDCA_DRL1_DATA_Pos 0\r
+#define LCDCA_DRL1_DATA_Msk (0xFFFFFFFFu << LCDCA_DRL1_DATA_Pos) /**< \brief (LCDCA_DRL1) Segments Value */\r
+#define LCDCA_DRL1_DATA(value) ((LCDCA_DRL1_DATA_Msk & ((value) << LCDCA_DRL1_DATA_Pos)))\r
+/* -------- LCDCA_DRH1 : (LCDCA Offset: 0x20) Data Register High 1 -------- */\r
+#define LCDCA_DRH1_DATA_Pos 0\r
+#define LCDCA_DRH1_DATA_Msk (0xFFu << LCDCA_DRH1_DATA_Pos) /**< \brief (LCDCA_DRH1) Segments Value */\r
+#define LCDCA_DRH1_DATA(value) ((LCDCA_DRH1_DATA_Msk & ((value) << LCDCA_DRH1_DATA_Pos)))\r
+/* -------- LCDCA_DRL2 : (LCDCA Offset: 0x24) Data Register Low 2 -------- */\r
+#define LCDCA_DRL2_DATA_Pos 0\r
+#define LCDCA_DRL2_DATA_Msk (0xFFFFFFFFu << LCDCA_DRL2_DATA_Pos) /**< \brief (LCDCA_DRL2) Segments Value */\r
+#define LCDCA_DRL2_DATA(value) ((LCDCA_DRL2_DATA_Msk & ((value) << LCDCA_DRL2_DATA_Pos)))\r
+/* -------- LCDCA_DRH2 : (LCDCA Offset: 0x28) Data Register High 2 -------- */\r
+#define LCDCA_DRH2_DATA_Pos 0\r
+#define LCDCA_DRH2_DATA_Msk (0xFFu << LCDCA_DRH2_DATA_Pos) /**< \brief (LCDCA_DRH2) Segments Value */\r
+#define LCDCA_DRH2_DATA(value) ((LCDCA_DRH2_DATA_Msk & ((value) << LCDCA_DRH2_DATA_Pos)))\r
+/* -------- LCDCA_DRL3 : (LCDCA Offset: 0x2C) Data Register Low 3 -------- */\r
+#define LCDCA_DRL3_DATA_Pos 0\r
+#define LCDCA_DRL3_DATA_Msk (0xFFFFFFFFu << LCDCA_DRL3_DATA_Pos) /**< \brief (LCDCA_DRL3) Segments Value */\r
+#define LCDCA_DRL3_DATA(value) ((LCDCA_DRL3_DATA_Msk & ((value) << LCDCA_DRL3_DATA_Pos)))\r
+/* -------- LCDCA_DRH3 : (LCDCA Offset: 0x30) Data Register High 3 -------- */\r
+#define LCDCA_DRH3_DATA_Pos 0\r
+#define LCDCA_DRH3_DATA_Msk (0xFFu << LCDCA_DRH3_DATA_Pos) /**< \brief (LCDCA_DRH3) Segments Value */\r
+#define LCDCA_DRH3_DATA(value) ((LCDCA_DRH3_DATA_Msk & ((value) << LCDCA_DRH3_DATA_Pos)))\r
+/* -------- LCDCA_IADR : (LCDCA Offset: 0x34) Indirect Access Data Register -------- */\r
+#define LCDCA_IADR_DATA_Pos 0\r
+#define LCDCA_IADR_DATA_Msk (0xFFu << LCDCA_IADR_DATA_Pos) /**< \brief (LCDCA_IADR) Segments Value */\r
+#define LCDCA_IADR_DATA(value) ((LCDCA_IADR_DATA_Msk & ((value) << LCDCA_IADR_DATA_Pos)))\r
+#define LCDCA_IADR_DMASK_Pos 8\r
+#define LCDCA_IADR_DMASK_Msk (0xFFu << LCDCA_IADR_DMASK_Pos) /**< \brief (LCDCA_IADR) Data Mask */\r
+#define LCDCA_IADR_DMASK(value) ((LCDCA_IADR_DMASK_Msk & ((value) << LCDCA_IADR_DMASK_Pos)))\r
+#define LCDCA_IADR_OFF_Pos 16\r
+#define LCDCA_IADR_OFF_Msk (0x1Fu << LCDCA_IADR_OFF_Pos) /**< \brief (LCDCA_IADR) Byte Offset */\r
+#define LCDCA_IADR_OFF(value) ((LCDCA_IADR_OFF_Msk & ((value) << LCDCA_IADR_OFF_Pos)))\r
+/* -------- LCDCA_BCFG : (LCDCA Offset: 0x38) Blink Configuration Register -------- */\r
+#define LCDCA_BCFG_MODE (0x1u << 0) /**< \brief (LCDCA_BCFG) Blinking Mode */\r
+#define LCDCA_BCFG_FCS_Pos 1\r
+#define LCDCA_BCFG_FCS_Msk (0x3u << LCDCA_BCFG_FCS_Pos) /**< \brief (LCDCA_BCFG) Frame Counter Selection */\r
+#define LCDCA_BCFG_FCS(value) ((LCDCA_BCFG_FCS_Msk & ((value) << LCDCA_BCFG_FCS_Pos)))\r
+#define LCDCA_BCFG_BSS0_Pos 8\r
+#define LCDCA_BCFG_BSS0_Msk (0xFu << LCDCA_BCFG_BSS0_Pos) /**< \brief (LCDCA_BCFG) Blink Segment Selection 0 */\r
+#define LCDCA_BCFG_BSS0(value) ((LCDCA_BCFG_BSS0_Msk & ((value) << LCDCA_BCFG_BSS0_Pos)))\r
+#define LCDCA_BCFG_BSS1_Pos 12\r
+#define LCDCA_BCFG_BSS1_Msk (0xFu << LCDCA_BCFG_BSS1_Pos) /**< \brief (LCDCA_BCFG) Blink Segment Selection 1 */\r
+#define LCDCA_BCFG_BSS1(value) ((LCDCA_BCFG_BSS1_Msk & ((value) << LCDCA_BCFG_BSS1_Pos)))\r
+/* -------- LCDCA_CSRCFG : (LCDCA Offset: 0x3C) Circular Shift Register Configuration -------- */\r
+#define LCDCA_CSRCFG_DIR (0x1u << 0) /**< \brief (LCDCA_CSRCFG) Direction */\r
+#define LCDCA_CSRCFG_FCS_Pos 1\r
+#define LCDCA_CSRCFG_FCS_Msk (0x3u << LCDCA_CSRCFG_FCS_Pos) /**< \brief (LCDCA_CSRCFG) Frame Counter Selection */\r
+#define LCDCA_CSRCFG_FCS(value) ((LCDCA_CSRCFG_FCS_Msk & ((value) << LCDCA_CSRCFG_FCS_Pos)))\r
+#define LCDCA_CSRCFG_SIZE_Pos 3\r
+#define LCDCA_CSRCFG_SIZE_Msk (0x7u << LCDCA_CSRCFG_SIZE_Pos) /**< \brief (LCDCA_CSRCFG) Size */\r
+#define LCDCA_CSRCFG_SIZE(value) ((LCDCA_CSRCFG_SIZE_Msk & ((value) << LCDCA_CSRCFG_SIZE_Pos)))\r
+#define LCDCA_CSRCFG_DATA_Pos 8\r
+#define LCDCA_CSRCFG_DATA_Msk (0xFFu << LCDCA_CSRCFG_DATA_Pos) /**< \brief (LCDCA_CSRCFG) Circular Shift Register Value */\r
+#define LCDCA_CSRCFG_DATA(value) ((LCDCA_CSRCFG_DATA_Msk & ((value) << LCDCA_CSRCFG_DATA_Pos)))\r
+/* -------- LCDCA_CMCFG : (LCDCA Offset: 0x40) Character Mapping Configuration Register -------- */\r
+#define LCDCA_CMCFG_DREV (0x1u << 0) /**< \brief (LCDCA_CMCFG) Digit Reverse Mode */\r
+#define LCDCA_CMCFG_TDG_Pos 1\r
+#define LCDCA_CMCFG_TDG_Msk (0x3u << LCDCA_CMCFG_TDG_Pos) /**< \brief (LCDCA_CMCFG) Type of Digit */\r
+#define LCDCA_CMCFG_TDG(value) ((LCDCA_CMCFG_TDG_Msk & ((value) << LCDCA_CMCFG_TDG_Pos)))\r
+#define LCDCA_CMCFG_STSEG_Pos 8\r
+#define LCDCA_CMCFG_STSEG_Msk (0x3Fu << LCDCA_CMCFG_STSEG_Pos) /**< \brief (LCDCA_CMCFG) Start Segment */\r
+#define LCDCA_CMCFG_STSEG(value) ((LCDCA_CMCFG_STSEG_Msk & ((value) << LCDCA_CMCFG_STSEG_Pos)))\r
+/* -------- LCDCA_CMDR : (LCDCA Offset: 0x44) Character Mapping Data Register -------- */\r
+#define LCDCA_CMDR_ASCII_Pos 0\r
+#define LCDCA_CMDR_ASCII_Msk (0x7Fu << LCDCA_CMDR_ASCII_Pos) /**< \brief (LCDCA_CMDR) ASCII Code */\r
+#define LCDCA_CMDR_ASCII(value) ((LCDCA_CMDR_ASCII_Msk & ((value) << LCDCA_CMDR_ASCII_Pos)))\r
+/* -------- LCDCA_ACMCFG : (LCDCA Offset: 0x48) Automated Character Mapping Configuration Register -------- */\r
+#define LCDCA_ACMCFG_EN (0x1u << 0) /**< \brief (LCDCA_ACMCFG) Enable */\r
+#define LCDCA_ACMCFG_FCS_Pos 1\r
+#define LCDCA_ACMCFG_FCS_Msk (0x3u << LCDCA_ACMCFG_FCS_Pos) /**< \brief (LCDCA_ACMCFG) Frame Counter Selection */\r
+#define LCDCA_ACMCFG_FCS(value) ((LCDCA_ACMCFG_FCS_Msk & ((value) << LCDCA_ACMCFG_FCS_Pos)))\r
+#define LCDCA_ACMCFG_MODE (0x1u << 3) /**< \brief (LCDCA_ACMCFG) Mode (sequential or scrolling) */\r
+#define LCDCA_ACMCFG_DREV (0x1u << 4) /**< \brief (LCDCA_ACMCFG) Digit Reverse */\r
+#define LCDCA_ACMCFG_TDG_Pos 5\r
+#define LCDCA_ACMCFG_TDG_Msk (0x3u << LCDCA_ACMCFG_TDG_Pos) /**< \brief (LCDCA_ACMCFG) Type of Digit */\r
+#define LCDCA_ACMCFG_TDG(value) ((LCDCA_ACMCFG_TDG_Msk & ((value) << LCDCA_ACMCFG_TDG_Pos)))\r
+#define LCDCA_ACMCFG_STSEG_Pos 8\r
+#define LCDCA_ACMCFG_STSEG_Msk (0x3Fu << LCDCA_ACMCFG_STSEG_Pos) /**< \brief (LCDCA_ACMCFG) Start Segment */\r
+#define LCDCA_ACMCFG_STSEG(value) ((LCDCA_ACMCFG_STSEG_Msk & ((value) << LCDCA_ACMCFG_STSEG_Pos)))\r
+#define LCDCA_ACMCFG_STEPS_Pos 16\r
+#define LCDCA_ACMCFG_STEPS_Msk (0xFFu << LCDCA_ACMCFG_STEPS_Pos) /**< \brief (LCDCA_ACMCFG) Scrolling Steps */\r
+#define LCDCA_ACMCFG_STEPS(value) ((LCDCA_ACMCFG_STEPS_Msk & ((value) << LCDCA_ACMCFG_STEPS_Pos)))\r
+#define LCDCA_ACMCFG_DIGN_Pos 24\r
+#define LCDCA_ACMCFG_DIGN_Msk (0xFu << LCDCA_ACMCFG_DIGN_Pos) /**< \brief (LCDCA_ACMCFG) Digit Number */\r
+#define LCDCA_ACMCFG_DIGN(value) ((LCDCA_ACMCFG_DIGN_Msk & ((value) << LCDCA_ACMCFG_DIGN_Pos)))\r
+/* -------- LCDCA_ACMDR : (LCDCA Offset: 0x4C) Automated Character Mapping Data Register -------- */\r
+#define LCDCA_ACMDR_ASCII_Pos 0\r
+#define LCDCA_ACMDR_ASCII_Msk (0x7Fu << LCDCA_ACMDR_ASCII_Pos) /**< \brief (LCDCA_ACMDR) ASCII Code */\r
+#define LCDCA_ACMDR_ASCII(value) ((LCDCA_ACMDR_ASCII_Msk & ((value) << LCDCA_ACMDR_ASCII_Pos)))\r
+/* -------- LCDCA_ABMCFG : (LCDCA Offset: 0x50) Automated Bit Mapping Configuration Register -------- */\r
+#define LCDCA_ABMCFG_EN (0x1u << 0) /**< \brief (LCDCA_ABMCFG) Enable */\r
+#define LCDCA_ABMCFG_FCS_Pos 1\r
+#define LCDCA_ABMCFG_FCS_Msk (0x3u << LCDCA_ABMCFG_FCS_Pos) /**< \brief (LCDCA_ABMCFG) Frame Counter Selection */\r
+#define LCDCA_ABMCFG_FCS(value) ((LCDCA_ABMCFG_FCS_Msk & ((value) << LCDCA_ABMCFG_FCS_Pos)))\r
+#define LCDCA_ABMCFG_SIZE_Pos 8\r
+#define LCDCA_ABMCFG_SIZE_Msk (0x1Fu << LCDCA_ABMCFG_SIZE_Pos) /**< \brief (LCDCA_ABMCFG) Size */\r
+#define LCDCA_ABMCFG_SIZE(value) ((LCDCA_ABMCFG_SIZE_Msk & ((value) << LCDCA_ABMCFG_SIZE_Pos)))\r
+/* -------- LCDCA_ABMDR : (LCDCA Offset: 0x54) Automated Bit Mapping Data Register -------- */\r
+#define LCDCA_ABMDR_DATA_Pos 0\r
+#define LCDCA_ABMDR_DATA_Msk (0xFFu << LCDCA_ABMDR_DATA_Pos) /**< \brief (LCDCA_ABMDR) Segments Value */\r
+#define LCDCA_ABMDR_DATA(value) ((LCDCA_ABMDR_DATA_Msk & ((value) << LCDCA_ABMDR_DATA_Pos)))\r
+#define LCDCA_ABMDR_DMASK_Pos 8\r
+#define LCDCA_ABMDR_DMASK_Msk (0xFFu << LCDCA_ABMDR_DMASK_Pos) /**< \brief (LCDCA_ABMDR) Data Mask */\r
+#define LCDCA_ABMDR_DMASK(value) ((LCDCA_ABMDR_DMASK_Msk & ((value) << LCDCA_ABMDR_DMASK_Pos)))\r
+#define LCDCA_ABMDR_OFF_Pos 16\r
+#define LCDCA_ABMDR_OFF_Msk (0x1Fu << LCDCA_ABMDR_OFF_Pos) /**< \brief (LCDCA_ABMDR) Byte Offset */\r
+#define LCDCA_ABMDR_OFF(value) ((LCDCA_ABMDR_OFF_Msk & ((value) << LCDCA_ABMDR_OFF_Pos)))\r
+/* -------- LCDCA_IER : (LCDCA Offset: 0x58) Interrupt Enable Register -------- */\r
+#define LCDCA_IER_FC0R (0x1u << 0) /**< \brief (LCDCA_IER) Frame Counter 0 Rollover */\r
+/* -------- LCDCA_IDR : (LCDCA Offset: 0x5C) Interrupt Disable Register -------- */\r
+#define LCDCA_IDR_FC0R (0x1u << 0) /**< \brief (LCDCA_IDR) Frame Counter 0 Rollover */\r
+/* -------- LCDCA_IMR : (LCDCA Offset: 0x60) Interrupt Mask Register -------- */\r
+#define LCDCA_IMR_FC0R (0x1u << 0) /**< \brief (LCDCA_IMR) Frame Counter 0 Rollover */\r
+/* -------- LCDCA_VERSION : (LCDCA Offset: 0x64) Version Register -------- */\r
+#define LCDCA_VERSION_VERSION_Pos 0\r
+#define LCDCA_VERSION_VERSION_Msk (0xFFFu << LCDCA_VERSION_VERSION_Pos) /**< \brief (LCDCA_VERSION) Version Number */\r
+#define LCDCA_VERSION_VERSION(value) ((LCDCA_VERSION_VERSION_Msk & ((value) << LCDCA_VERSION_VERSION_Pos)))\r
+#define LCDCA_VERSION_VARIANT_Pos 16\r
+#define LCDCA_VERSION_VARIANT_Msk (0xFu << LCDCA_VERSION_VARIANT_Pos) /**< \brief (LCDCA_VERSION) Variant Number */\r
+#define LCDCA_VERSION_VARIANT(value) ((LCDCA_VERSION_VARIANT_Msk & ((value) << LCDCA_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR PARC */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_PARC Parallel Capture */\r
+/*@{*/\r
+\r
+#define REV_PARC 0x100\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief PARC hardware registers */\r
+typedef struct {\r
+ RwReg PARC_CFG; /**< \brief (PARC Offset: 0x00) Configuration Register */\r
+ RwReg PARC_CR; /**< \brief (PARC Offset: 0x04) Control Register */\r
+ WoReg PARC_IER; /**< \brief (PARC Offset: 0x08) Interrupt Enable Register */\r
+ WoReg PARC_IDR; /**< \brief (PARC Offset: 0x0C) Interrupt Disable Register */\r
+ RoReg PARC_IMR; /**< \brief (PARC Offset: 0x10) Interrupt Mask Register */\r
+ RoReg PARC_SR; /**< \brief (PARC Offset: 0x14) Status Register */\r
+ WoReg PARC_ICR; /**< \brief (PARC Offset: 0x18) Interrupt Status Clear Register */\r
+ RoReg PARC_RHR; /**< \brief (PARC Offset: 0x1C) Receive Holding Register */\r
+ RoReg PARC_VERSION; /**< \brief (PARC Offset: 0x20) Version Register */\r
+} Parc;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- PARC_CFG : (PARC Offset: 0x00) Configuration Register -------- */\r
+#define PARC_CFG_DSIZE_Pos 0\r
+#define PARC_CFG_DSIZE_Msk (0x3u << PARC_CFG_DSIZE_Pos) /**< \brief (PARC_CFG) Data Size */\r
+#define PARC_CFG_DSIZE(value) ((PARC_CFG_DSIZE_Msk & ((value) << PARC_CFG_DSIZE_Pos)))\r
+#define PARC_CFG_SMODE_Pos 2\r
+#define PARC_CFG_SMODE_Msk (0x3u << PARC_CFG_SMODE_Pos) /**< \brief (PARC_CFG) Sampling Mode */\r
+#define PARC_CFG_SMODE(value) ((PARC_CFG_SMODE_Msk & ((value) << PARC_CFG_SMODE_Pos)))\r
+#define PARC_CFG_EMODE (0x1u << 4) /**< \brief (PARC_CFG) Events Mode */\r
+#define PARC_CFG_EDGE (0x1u << 5) /**< \brief (PARC_CFG) Sampling Edge Select */\r
+#define PARC_CFG_HALF (0x1u << 6) /**< \brief (PARC_CFG) Half Capture */\r
+#define PARC_CFG_ODD (0x1u << 7) /**< \brief (PARC_CFG) Odd Capture */\r
+/* -------- PARC_CR : (PARC Offset: 0x04) Control Register -------- */\r
+#define PARC_CR_EN (0x1u << 0) /**< \brief (PARC_CR) Enable */\r
+#define PARC_CR_DIS (0x1u << 1) /**< \brief (PARC_CR) Disable */\r
+#define PARC_CR_START (0x1u << 2) /**< \brief (PARC_CR) Start Capture */\r
+#define PARC_CR_STOP (0x1u << 3) /**< \brief (PARC_CR) Stop Capture */\r
+/* -------- PARC_IER : (PARC Offset: 0x08) Interrupt Enable Register -------- */\r
+#define PARC_IER_DRDY (0x1u << 2) /**< \brief (PARC_IER) Data Ready Interrupt Enable */\r
+#define PARC_IER_OVR (0x1u << 3) /**< \brief (PARC_IER) Overrun Interrupt Enable */\r
+/* -------- PARC_IDR : (PARC Offset: 0x0C) Interrupt Disable Register -------- */\r
+#define PARC_IDR_DRDY (0x1u << 2) /**< \brief (PARC_IDR) Data Ready Interrupt Disable */\r
+#define PARC_IDR_OVR (0x1u << 3) /**< \brief (PARC_IDR) Overrun Interrupt Disable */\r
+/* -------- PARC_IMR : (PARC Offset: 0x10) Interrupt Mask Register -------- */\r
+#define PARC_IMR_DRDY (0x1u << 2) /**< \brief (PARC_IMR) Data Ready Interrupt Mask */\r
+#define PARC_IMR_OVR (0x1u << 3) /**< \brief (PARC_IMR) Overrun Interrupt Mask */\r
+/* -------- PARC_SR : (PARC Offset: 0x14) Status Register -------- */\r
+#define PARC_SR_EN (0x1u << 0) /**< \brief (PARC_SR) Enable Status */\r
+#define PARC_SR_CS (0x1u << 1) /**< \brief (PARC_SR) Capture Status */\r
+#define PARC_SR_DRDY (0x1u << 2) /**< \brief (PARC_SR) Data Ready Interrupt Status */\r
+#define PARC_SR_OVR (0x1u << 3) /**< \brief (PARC_SR) Overrun Interrupt Status */\r
+/* -------- PARC_ICR : (PARC Offset: 0x18) Interrupt Status Clear Register -------- */\r
+#define PARC_ICR_DRDY (0x1u << 2) /**< \brief (PARC_ICR) Data Ready Interrupt Status Clear */\r
+#define PARC_ICR_OVR (0x1u << 3) /**< \brief (PARC_ICR) Overrun Interrupt Status Clear */\r
+/* -------- PARC_RHR : (PARC Offset: 0x1C) Receive Holding Register -------- */\r
+#define PARC_RHR_CDATA_Pos 0\r
+#define PARC_RHR_CDATA_Msk (0xFFFFFFFFu << PARC_RHR_CDATA_Pos) /**< \brief (PARC_RHR) Captured Data */\r
+#define PARC_RHR_CDATA(value) ((PARC_RHR_CDATA_Msk & ((value) << PARC_RHR_CDATA_Pos)))\r
+/* -------- PARC_VERSION : (PARC Offset: 0x20) Version Register -------- */\r
+#define PARC_VERSION_VERSION_Pos 0\r
+#define PARC_VERSION_VERSION_Msk (0xFFFu << PARC_VERSION_VERSION_Pos) /**< \brief (PARC_VERSION) Version Number */\r
+#define PARC_VERSION_VERSION(value) ((PARC_VERSION_VERSION_Msk & ((value) << PARC_VERSION_VERSION_Pos)))\r
+#define PARC_VERSION_VARIANT_Pos 16\r
+#define PARC_VERSION_VARIANT_Msk (0xFu << PARC_VERSION_VARIANT_Pos) /**< \brief (PARC_VERSION) Variant Number */\r
+#define PARC_VERSION_VARIANT(value) ((PARC_VERSION_VARIANT_Msk & ((value) << PARC_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR PDCA */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_PDCA Peripheral DMA Controller */\r
+/*@{*/\r
+\r
+#define REV_PDCA 0x124\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief PdcaChannel hardware registers */\r
+typedef struct {\r
+ RwReg PDCA_MAR; /**< \brief (PdcaChannel Offset: 0x000) Memory Address Register */\r
+ RwReg PDCA_PSR; /**< \brief (PdcaChannel Offset: 0x004) Peripheral Select Register */\r
+ RwReg PDCA_TCR; /**< \brief (PdcaChannel Offset: 0x008) Transfer Counter Register */\r
+ RwReg PDCA_MARR; /**< \brief (PdcaChannel Offset: 0x00C) Memory Address Reload Register */\r
+ RwReg PDCA_TCRR; /**< \brief (PdcaChannel Offset: 0x010) Transfer Counter Reload Register */\r
+ WoReg PDCA_CR; /**< \brief (PdcaChannel Offset: 0x014) Control Register */\r
+ RwReg PDCA_MR; /**< \brief (PdcaChannel Offset: 0x018) Mode Register */\r
+ RoReg PDCA_SR; /**< \brief (PdcaChannel Offset: 0x01C) Status Register */\r
+ WoReg PDCA_IER; /**< \brief (PdcaChannel Offset: 0x020) Interrupt Enable Register */\r
+ WoReg PDCA_IDR; /**< \brief (PdcaChannel Offset: 0x024) Interrupt Disable Register */\r
+ RoReg PDCA_IMR; /**< \brief (PdcaChannel Offset: 0x028) Interrupt Mask Register */\r
+ RoReg PDCA_ISR; /**< \brief (PdcaChannel Offset: 0x02C) Interrupt Status Register */\r
+ RoReg Reserved1[4];\r
+} PdcaChannel;\r
+/** \brief PDCA hardware registers */\r
+#define PDCA_CHANNEL_LENGTH 16\r
+typedef struct {\r
+ PdcaChannel PDCA_CHANNEL[PDCA_CHANNEL_LENGTH]; /**< \brief (PDCA Offset: 0x000) PdcaChannel groups */\r
+ PdcaChannel Reserved1[32 - PDCA_CHANNEL_LENGTH];\r
+ RwReg PDCA_PCONTROL; /**< \brief (PDCA Offset: 0x800) Performance Control Register */\r
+ RoReg PDCA_PRDATA0; /**< \brief (PDCA Offset: 0x804) Channel 0 Read Data Cycles */\r
+ RoReg PDCA_PRSTALL0; /**< \brief (PDCA Offset: 0x808) Channel 0 Read Stall Cycles */\r
+ RoReg PDCA_PRLAT0; /**< \brief (PDCA Offset: 0x80C) Channel 0 Read Max Latency */\r
+ RoReg PDCA_PWDATA0; /**< \brief (PDCA Offset: 0x810) Channel 0 Write Data Cycles */\r
+ RoReg PDCA_PWSTALL0; /**< \brief (PDCA Offset: 0x814) Channel 0 Write Stall Cycles */\r
+ RoReg PDCA_PWLAT0; /**< \brief (PDCA Offset: 0x818) Channel0 Write Max Latency */\r
+ RoReg PDCA_PRDATA1; /**< \brief (PDCA Offset: 0x81C) Channel 1 Read Data Cycles */\r
+ RoReg PDCA_PRSTALL1; /**< \brief (PDCA Offset: 0x820) Channel Read Stall Cycles */\r
+ RoReg PDCA_PRLAT1; /**< \brief (PDCA Offset: 0x824) Channel 1 Read Max Latency */\r
+ RoReg PDCA_PWDATA1; /**< \brief (PDCA Offset: 0x828) Channel 1 Write Data Cycles */\r
+ RoReg PDCA_PWSTALL1; /**< \brief (PDCA Offset: 0x82C) Channel 1 Write stall Cycles */\r
+ RoReg PDCA_PWLAT1; /**< \brief (PDCA Offset: 0x830) Channel 1 Read Max Latency */\r
+ RoReg PDCA_VERSION; /**< \brief (PDCA Offset: 0x834) Version Register */\r
+} Pdca;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- PDCA_MAR : (PDCA Offset: 0x000) Channel Memory Address Register -------- */\r
+#define PDCA_MAR_MADDR_Pos 0\r
+#define PDCA_MAR_MADDR_Msk (0xFFFFFFFFu << PDCA_MAR_MADDR_Pos) /**< \brief (PDCA_MAR) Memory Address */\r
+#define PDCA_MAR_MADDR(value) ((PDCA_MAR_MADDR_Msk & ((value) << PDCA_MAR_MADDR_Pos)))\r
+/* -------- PDCA_PSR : (PDCA Offset: 0x004) Channel Peripheral Select Register -------- */\r
+#define PDCA_PSR_PID_Pos 0\r
+#define PDCA_PSR_PID_Msk (0xFFu << PDCA_PSR_PID_Pos) /**< \brief (PDCA_PSR) Peripheral Identifier */\r
+#define PDCA_PSR_PID(value) ((PDCA_PSR_PID_Msk & ((value) << PDCA_PSR_PID_Pos)))\r
+/* -------- PDCA_TCR : (PDCA Offset: 0x008) Channel Transfer Counter Register -------- */\r
+#define PDCA_TCR_TCV_Pos 0\r
+#define PDCA_TCR_TCV_Msk (0xFFFFu << PDCA_TCR_TCV_Pos) /**< \brief (PDCA_TCR) Transfer Counter Value */\r
+#define PDCA_TCR_TCV(value) ((PDCA_TCR_TCV_Msk & ((value) << PDCA_TCR_TCV_Pos)))\r
+/* -------- PDCA_MARR : (PDCA Offset: 0x00C) Channel Memory Address Reload Register -------- */\r
+#define PDCA_MARR_MARV_Pos 0\r
+#define PDCA_MARR_MARV_Msk (0xFFFFFFFFu << PDCA_MARR_MARV_Pos) /**< \brief (PDCA_MARR) Memory Address Reload Value */\r
+#define PDCA_MARR_MARV(value) ((PDCA_MARR_MARV_Msk & ((value) << PDCA_MARR_MARV_Pos)))\r
+/* -------- PDCA_TCRR : (PDCA Offset: 0x010) Channel Transfer Counter Reload Register -------- */\r
+#define PDCA_TCRR_TCRV_Pos 0\r
+#define PDCA_TCRR_TCRV_Msk (0xFFFFu << PDCA_TCRR_TCRV_Pos) /**< \brief (PDCA_TCRR) Transfer Counter Reload Value */\r
+#define PDCA_TCRR_TCRV(value) ((PDCA_TCRR_TCRV_Msk & ((value) << PDCA_TCRR_TCRV_Pos)))\r
+/* -------- PDCA_CR : (PDCA Offset: 0x014) Channel Control Register -------- */\r
+#define PDCA_CR_TEN (0x1u << 0) /**< \brief (PDCA_CR) Transfer Enable */\r
+#define PDCA_CR_TDIS (0x1u << 1) /**< \brief (PDCA_CR) Transfer Disable */\r
+#define PDCA_CR_ECLR (0x1u << 8) /**< \brief (PDCA_CR) Error Clear */\r
+/* -------- PDCA_MR : (PDCA Offset: 0x018) Channel Mode Register -------- */\r
+#define PDCA_MR_SIZE_Pos 0\r
+#define PDCA_MR_SIZE_Msk (0x3u << PDCA_MR_SIZE_Pos) /**< \brief (PDCA_MR) Transfer size */\r
+#define PDCA_MR_SIZE(value) ((PDCA_MR_SIZE_Msk & ((value) << PDCA_MR_SIZE_Pos)))\r
+#define PDCA_MR_SIZE_BYTE (0x0u << 0) /**< \brief (PDCA_MR) */\r
+#define PDCA_MR_SIZE_HALF_WORD (0x1u << 0) /**< \brief (PDCA_MR) */\r
+#define PDCA_MR_SIZE_WORD (0x2u << 0) /**< \brief (PDCA_MR) */\r
+#define PDCA_MR_ETRIG (0x1u << 2) /**< \brief (PDCA_MR) Event trigger */\r
+#define PDCA_MR_RING (0x1u << 3) /**< \brief (PDCA_MR) Ring Buffer */\r
+/* -------- PDCA_SR : (PDCA Offset: 0x01C) Channel Status Register -------- */\r
+#define PDCA_SR_TEN (0x1u << 0) /**< \brief (PDCA_SR) Transfer Enabled */\r
+/* -------- PDCA_IER : (PDCA Offset: 0x020) Channel Interrupt Enable Register -------- */\r
+#define PDCA_IER_RCZ (0x1u << 0) /**< \brief (PDCA_IER) Reload Counter Zero */\r
+#define PDCA_IER_TRC (0x1u << 1) /**< \brief (PDCA_IER) Transfer Complete */\r
+#define PDCA_IER_TERR (0x1u << 2) /**< \brief (PDCA_IER) Transfer Error */\r
+/* -------- PDCA_IDR : (PDCA Offset: 0x024) Channel Interrupt Disable Register -------- */\r
+#define PDCA_IDR_RCZ (0x1u << 0) /**< \brief (PDCA_IDR) Reload Counter Zero */\r
+#define PDCA_IDR_TRC (0x1u << 1) /**< \brief (PDCA_IDR) Transfer Complete */\r
+#define PDCA_IDR_TERR (0x1u << 2) /**< \brief (PDCA_IDR) Transfer Error */\r
+/* -------- PDCA_IMR : (PDCA Offset: 0x028) Channel Interrupt Mask Register -------- */\r
+#define PDCA_IMR_RCZ (0x1u << 0) /**< \brief (PDCA_IMR) Reload Counter Zero */\r
+#define PDCA_IMR_TRC (0x1u << 1) /**< \brief (PDCA_IMR) Transfer Complete */\r
+#define PDCA_IMR_TERR (0x1u << 2) /**< \brief (PDCA_IMR) Transfer Error */\r
+/* -------- PDCA_ISR : (PDCA Offset: 0x02C) Channel Interrupt Status Register -------- */\r
+#define PDCA_ISR_RCZ (0x1u << 0) /**< \brief (PDCA_ISR) Reload Counter Zero */\r
+#define PDCA_ISR_TRC (0x1u << 1) /**< \brief (PDCA_ISR) Transfer Complete */\r
+#define PDCA_ISR_TERR (0x1u << 2) /**< \brief (PDCA_ISR) Transfer Error */\r
+/* -------- PDCA_PCONTROL : (PDCA Offset: 0x800) Performance Control Register -------- */\r
+#define PDCA_PCONTROL_CH0EN (0x1u << 0) /**< \brief (PDCA_PCONTROL) Channel 0 Enabled */\r
+#define PDCA_PCONTROL_CH1EN (0x1u << 1) /**< \brief (PDCA_PCONTROL) Channel 1 Enabled. */\r
+#define PDCA_PCONTROL_CH0OF (0x1u << 4) /**< \brief (PDCA_PCONTROL) Channel 0 Overflow Freeze */\r
+#define PDCA_PCONTROL_CH1OF (0x1u << 5) /**< \brief (PDCA_PCONTROL) Channel 1 overflow freeze */\r
+#define PDCA_PCONTROL_CH0RES (0x1u << 8) /**< \brief (PDCA_PCONTROL) Channel 0 counter reset */\r
+#define PDCA_PCONTROL_CH1RES (0x1u << 9) /**< \brief (PDCA_PCONTROL) Channel 1 counter reset */\r
+#define PDCA_PCONTROL_MON0CH_Pos 16\r
+#define PDCA_PCONTROL_MON0CH_Msk (0x3Fu << PDCA_PCONTROL_MON0CH_Pos) /**< \brief (PDCA_PCONTROL) PDCA Channel to monitor with counter 0 */\r
+#define PDCA_PCONTROL_MON0CH(value) ((PDCA_PCONTROL_MON0CH_Msk & ((value) << PDCA_PCONTROL_MON0CH_Pos)))\r
+#define PDCA_PCONTROL_MON1CH_Pos 24\r
+#define PDCA_PCONTROL_MON1CH_Msk (0x3Fu << PDCA_PCONTROL_MON1CH_Pos) /**< \brief (PDCA_PCONTROL) PDCA Channel to monitor with counter 1 */\r
+#define PDCA_PCONTROL_MON1CH(value) ((PDCA_PCONTROL_MON1CH_Msk & ((value) << PDCA_PCONTROL_MON1CH_Pos)))\r
+/* -------- PDCA_PRDATA0 : (PDCA Offset: 0x804) Channel 0 Read Data Cycles -------- */\r
+#define PDCA_PRDATA0_DATA_Pos 0\r
+#define PDCA_PRDATA0_DATA_Msk (0xFFFFFFFFu << PDCA_PRDATA0_DATA_Pos) /**< \brief (PDCA_PRDATA0) Data Cycles Counted Since Last reset */\r
+#define PDCA_PRDATA0_DATA(value) ((PDCA_PRDATA0_DATA_Msk & ((value) << PDCA_PRDATA0_DATA_Pos)))\r
+/* -------- PDCA_PRSTALL0 : (PDCA Offset: 0x808) Channel 0 Read Stall Cycles -------- */\r
+#define PDCA_PRSTALL0_STALL_Pos 0\r
+#define PDCA_PRSTALL0_STALL_Msk (0xFFFFFFFFu << PDCA_PRSTALL0_STALL_Pos) /**< \brief (PDCA_PRSTALL0) Stall Cycles counted since last reset */\r
+#define PDCA_PRSTALL0_STALL(value) ((PDCA_PRSTALL0_STALL_Msk & ((value) << PDCA_PRSTALL0_STALL_Pos)))\r
+/* -------- PDCA_PRLAT0 : (PDCA Offset: 0x80C) Channel 0 Read Max Latency -------- */\r
+#define PDCA_PRLAT0_LAT_Pos 0\r
+#define PDCA_PRLAT0_LAT_Msk (0xFFFFu << PDCA_PRLAT0_LAT_Pos) /**< \brief (PDCA_PRLAT0) Maximum Transfer Initiation cycles counted since last reset */\r
+#define PDCA_PRLAT0_LAT(value) ((PDCA_PRLAT0_LAT_Msk & ((value) << PDCA_PRLAT0_LAT_Pos)))\r
+/* -------- PDCA_PWDATA0 : (PDCA Offset: 0x810) Channel 0 Write Data Cycles -------- */\r
+#define PDCA_PWDATA0_DATA_Pos 0\r
+#define PDCA_PWDATA0_DATA_Msk (0xFFFFFFFFu << PDCA_PWDATA0_DATA_Pos) /**< \brief (PDCA_PWDATA0) Data Cycles Counted since last Reset */\r
+#define PDCA_PWDATA0_DATA(value) ((PDCA_PWDATA0_DATA_Msk & ((value) << PDCA_PWDATA0_DATA_Pos)))\r
+/* -------- PDCA_PWSTALL0 : (PDCA Offset: 0x814) Channel 0 Write Stall Cycles -------- */\r
+#define PDCA_PWSTALL0_STALL_Pos 0\r
+#define PDCA_PWSTALL0_STALL_Msk (0xFFFFFFFFu << PDCA_PWSTALL0_STALL_Pos) /**< \brief (PDCA_PWSTALL0) Stall cycles counted since last reset */\r
+#define PDCA_PWSTALL0_STALL(value) ((PDCA_PWSTALL0_STALL_Msk & ((value) << PDCA_PWSTALL0_STALL_Pos)))\r
+/* -------- PDCA_PWLAT0 : (PDCA Offset: 0x818) Channel0 Write Max Latency -------- */\r
+#define PDCA_PWLAT0_LAT_Pos 0\r
+#define PDCA_PWLAT0_LAT_Msk (0xFFFFu << PDCA_PWLAT0_LAT_Pos) /**< \brief (PDCA_PWLAT0) Maximum transfer initiation cycles counted since last reset */\r
+#define PDCA_PWLAT0_LAT(value) ((PDCA_PWLAT0_LAT_Msk & ((value) << PDCA_PWLAT0_LAT_Pos)))\r
+/* -------- PDCA_PRDATA1 : (PDCA Offset: 0x81C) Channel 1 Read Data Cycles -------- */\r
+#define PDCA_PRDATA1_DATA_Pos 0\r
+#define PDCA_PRDATA1_DATA_Msk (0xFFFFFFFFu << PDCA_PRDATA1_DATA_Pos) /**< \brief (PDCA_PRDATA1) Data Cycles Counted Since Last reset */\r
+#define PDCA_PRDATA1_DATA(value) ((PDCA_PRDATA1_DATA_Msk & ((value) << PDCA_PRDATA1_DATA_Pos)))\r
+/* -------- PDCA_PRSTALL1 : (PDCA Offset: 0x820) Channel Read Stall Cycles -------- */\r
+#define PDCA_PRSTALL1_STALL_Pos 0\r
+#define PDCA_PRSTALL1_STALL_Msk (0xFFFFFFFFu << PDCA_PRSTALL1_STALL_Pos) /**< \brief (PDCA_PRSTALL1) Stall Cycles Counted since last reset */\r
+#define PDCA_PRSTALL1_STALL(value) ((PDCA_PRSTALL1_STALL_Msk & ((value) << PDCA_PRSTALL1_STALL_Pos)))\r
+/* -------- PDCA_PRLAT1 : (PDCA Offset: 0x824) Channel 1 Read Max Latency -------- */\r
+#define PDCA_PRLAT1_LAT_Pos 0\r
+#define PDCA_PRLAT1_LAT_Msk (0xFFFFu << PDCA_PRLAT1_LAT_Pos) /**< \brief (PDCA_PRLAT1) Maximum Transfer initiation cycles counted since last reset */\r
+#define PDCA_PRLAT1_LAT(value) ((PDCA_PRLAT1_LAT_Msk & ((value) << PDCA_PRLAT1_LAT_Pos)))\r
+/* -------- PDCA_PWDATA1 : (PDCA Offset: 0x828) Channel 1 Write Data Cycles -------- */\r
+#define PDCA_PWDATA1_DATA_Pos 0\r
+#define PDCA_PWDATA1_DATA_Msk (0xFFFFFFFFu << PDCA_PWDATA1_DATA_Pos) /**< \brief (PDCA_PWDATA1) Data cycles Counted Since last reset */\r
+#define PDCA_PWDATA1_DATA(value) ((PDCA_PWDATA1_DATA_Msk & ((value) << PDCA_PWDATA1_DATA_Pos)))\r
+/* -------- PDCA_PWSTALL1 : (PDCA Offset: 0x82C) Channel 1 Write stall Cycles -------- */\r
+#define PDCA_PWSTALL1_STALL_Pos 0\r
+#define PDCA_PWSTALL1_STALL_Msk (0xFFFFFFFFu << PDCA_PWSTALL1_STALL_Pos) /**< \brief (PDCA_PWSTALL1) Stall cycles counted since last reset */\r
+#define PDCA_PWSTALL1_STALL(value) ((PDCA_PWSTALL1_STALL_Msk & ((value) << PDCA_PWSTALL1_STALL_Pos)))\r
+/* -------- PDCA_PWLAT1 : (PDCA Offset: 0x830) Channel 1 Read Max Latency -------- */\r
+#define PDCA_PWLAT1_LAT_Pos 0\r
+#define PDCA_PWLAT1_LAT_Msk (0xFFFFu << PDCA_PWLAT1_LAT_Pos) /**< \brief (PDCA_PWLAT1) Maximum transfer initiation cycles counted since last reset */\r
+#define PDCA_PWLAT1_LAT(value) ((PDCA_PWLAT1_LAT_Msk & ((value) << PDCA_PWLAT1_LAT_Pos)))\r
+/* -------- PDCA_VERSION : (PDCA Offset: 0x834) Version Register -------- */\r
+#define PDCA_VERSION_VERSION_Pos 0\r
+#define PDCA_VERSION_VERSION_Msk (0xFFFu << PDCA_VERSION_VERSION_Pos) /**< \brief (PDCA_VERSION) Version Number */\r
+#define PDCA_VERSION_VERSION(value) ((PDCA_VERSION_VERSION_Msk & ((value) << PDCA_VERSION_VERSION_Pos)))\r
+#define PDCA_VERSION_VARIANT_Pos 16\r
+#define PDCA_VERSION_VARIANT_Msk (0xFu << PDCA_VERSION_VARIANT_Pos) /**< \brief (PDCA_VERSION) Variant Number */\r
+#define PDCA_VERSION_VARIANT(value) ((PDCA_VERSION_VARIANT_Msk & ((value) << PDCA_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR PEVC */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_PEVC Peripheral Event Controller */\r
+/*@{*/\r
+\r
+#define REV_PEVC 0x200\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief PevcChmx hardware registers */\r
+typedef struct {\r
+ RwReg PEVC_CHMX; /**< \brief (PevcChmx Offset: 0x000) Channel Multiplexer 0 */\r
+} PevcChmx;\r
+/** \brief PevcEvs hardware registers */\r
+typedef struct {\r
+ RwReg PEVC_EVS; /**< \brief (PevcEvs Offset: 0x000) Event Shaper 0 */\r
+} PevcEvs;\r
+/** \brief PEVC hardware registers */\r
+#define PEVC_TRIGOUT_BITS 19\r
+#define PEVC_EVIN_BITS 31\r
+typedef struct {\r
+ RoReg PEVC_CHSR; /**< \brief (PEVC Offset: 0x000) Channel Status Register */\r
+ WoReg PEVC_CHER; /**< \brief (PEVC Offset: 0x004) Channel Enable Register */\r
+ WoReg PEVC_CHDR; /**< \brief (PEVC Offset: 0x008) Channel Disable Register */\r
+ RoReg Reserved1[1];\r
+ WoReg PEVC_SEV; /**< \brief (PEVC Offset: 0x010) Software Event */\r
+ RoReg PEVC_BUSY; /**< \brief (PEVC Offset: 0x014) Channel / User Busy */\r
+ RoReg Reserved2[2];\r
+ WoReg PEVC_TRIER; /**< \brief (PEVC Offset: 0x020) Trigger Interrupt Mask Enable Register */\r
+ WoReg PEVC_TRIDR; /**< \brief (PEVC Offset: 0x024) Trigger Interrupt Mask Disable Register */\r
+ RoReg PEVC_TRIMR; /**< \brief (PEVC Offset: 0x028) Trigger Interrupt Mask Register */\r
+ RoReg Reserved3[1];\r
+ RoReg PEVC_TRSR; /**< \brief (PEVC Offset: 0x030) Trigger Status Register */\r
+ WoReg PEVC_TRSCR; /**< \brief (PEVC Offset: 0x034) Trigger Status Clear Register */\r
+ RoReg Reserved4[2];\r
+ WoReg PEVC_OVIER; /**< \brief (PEVC Offset: 0x040) Overrun Interrupt Mask Enable Register */\r
+ WoReg PEVC_OVIDR; /**< \brief (PEVC Offset: 0x044) Overrun Interrupt Mask Disable Register */\r
+ RoReg PEVC_OVIMR; /**< \brief (PEVC Offset: 0x048) Overrun Interrupt Mask Register */\r
+ RoReg Reserved5[1];\r
+ RoReg PEVC_OVSR; /**< \brief (PEVC Offset: 0x050) Overrun Status Register */\r
+ WoReg PEVC_OVSCR; /**< \brief (PEVC Offset: 0x054) Overrun Status Clear Register */\r
+ RoReg Reserved6[42];\r
+ PevcChmx PEVC_CHMX[PEVC_TRIGOUT_BITS]; /**< \brief (PEVC Offset: 0x100) PevcChmx groups */\r
+ PevcChmx Reserved7[32 - PEVC_TRIGOUT_BITS];\r
+ RoReg Reserved8[32];\r
+ PevcEvs PEVC_EVS[PEVC_EVIN_BITS]; /**< \brief (PEVC Offset: 0x200) PevcEvs groups */\r
+ PevcEvs Reserved9[64 - PEVC_EVIN_BITS];\r
+ RwReg PEVC_IGFDR; /**< \brief (PEVC Offset: 0x300) Input Glitch Filter Divider Register */\r
+ RoReg Reserved10[61];\r
+ RoReg PEVC_PARAMETER; /**< \brief (PEVC Offset: 0x3F8) Parameter */\r
+ RoReg PEVC_VERSION; /**< \brief (PEVC Offset: 0x3FC) Version */\r
+} Pevc;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- PEVC_CHSR : (PEVC Offset: 0x000) Channel Status Register -------- */\r
+#define PEVC_CHSR_CHS_Pos 0\r
+#define PEVC_CHSR_CHS_Msk (0xFFFFFFFFu << PEVC_CHSR_CHS_Pos) /**< \brief (PEVC_CHSR) Channel Status */\r
+#define PEVC_CHSR_CHS(value) ((PEVC_CHSR_CHS_Msk & ((value) << PEVC_CHSR_CHS_Pos)))\r
+#define PEVC_CHSR_CHS_0 (0x0u << 0) /**< \brief (PEVC_CHSR) Channel j Disabled */\r
+#define PEVC_CHSR_CHS_1 (0x1u << 0) /**< \brief (PEVC_CHSR) Channel j Enabled */\r
+/* -------- PEVC_CHER : (PEVC Offset: 0x004) Channel Enable Register -------- */\r
+#define PEVC_CHER_CHE_Pos 0\r
+#define PEVC_CHER_CHE_Msk (0xFFFFFFFFu << PEVC_CHER_CHE_Pos) /**< \brief (PEVC_CHER) Channel Enable */\r
+#define PEVC_CHER_CHE(value) ((PEVC_CHER_CHE_Msk & ((value) << PEVC_CHER_CHE_Pos)))\r
+#define PEVC_CHER_CHE_0 (0x0u << 0) /**< \brief (PEVC_CHER) No Action */\r
+#define PEVC_CHER_CHE_1 (0x1u << 0) /**< \brief (PEVC_CHER) Enable Channel j */\r
+/* -------- PEVC_CHDR : (PEVC Offset: 0x008) Channel Disable Register -------- */\r
+#define PEVC_CHDR_CHD_Pos 0\r
+#define PEVC_CHDR_CHD_Msk (0xFFFFFFFFu << PEVC_CHDR_CHD_Pos) /**< \brief (PEVC_CHDR) Channel Disable */\r
+#define PEVC_CHDR_CHD(value) ((PEVC_CHDR_CHD_Msk & ((value) << PEVC_CHDR_CHD_Pos)))\r
+#define PEVC_CHDR_CHD_0 (0x0u << 0) /**< \brief (PEVC_CHDR) No Action */\r
+#define PEVC_CHDR_CHD_1 (0x1u << 0) /**< \brief (PEVC_CHDR) Disable Channel j */\r
+/* -------- PEVC_SEV : (PEVC Offset: 0x010) Software Event -------- */\r
+#define PEVC_SEV_SEV_Pos 0\r
+#define PEVC_SEV_SEV_Msk (0xFFFFFFFFu << PEVC_SEV_SEV_Pos) /**< \brief (PEVC_SEV) Software Event */\r
+#define PEVC_SEV_SEV(value) ((PEVC_SEV_SEV_Msk & ((value) << PEVC_SEV_SEV_Pos)))\r
+#define PEVC_SEV_SEV_0 (0x0u << 0) /**< \brief (PEVC_SEV) No Action */\r
+#define PEVC_SEV_SEV_1 (0x1u << 0) /**< \brief (PEVC_SEV) CPU forces software event to channel j */\r
+/* -------- PEVC_BUSY : (PEVC Offset: 0x014) Channel / User Busy -------- */\r
+#define PEVC_BUSY_BUSY_Pos 0\r
+#define PEVC_BUSY_BUSY_Msk (0xFFFFFFFFu << PEVC_BUSY_BUSY_Pos) /**< \brief (PEVC_BUSY) Channel Status */\r
+#define PEVC_BUSY_BUSY(value) ((PEVC_BUSY_BUSY_Msk & ((value) << PEVC_BUSY_BUSY_Pos)))\r
+#define PEVC_BUSY_BUSY_0 (0x0u << 0) /**< \brief (PEVC_BUSY) No Action */\r
+#define PEVC_BUSY_BUSY_1 (0x1u << 0) /**< \brief (PEVC_BUSY) Channel j or User j is Busy */\r
+/* -------- PEVC_TRIER : (PEVC Offset: 0x020) Trigger Interrupt Mask Enable Register -------- */\r
+#define PEVC_TRIER_TRIE_Pos 0\r
+#define PEVC_TRIER_TRIE_Msk (0xFFFFFFFFu << PEVC_TRIER_TRIE_Pos) /**< \brief (PEVC_TRIER) Trigger Interrupt Enable */\r
+#define PEVC_TRIER_TRIE(value) ((PEVC_TRIER_TRIE_Msk & ((value) << PEVC_TRIER_TRIE_Pos)))\r
+#define PEVC_TRIER_TRIE_0 (0x0u << 0) /**< \brief (PEVC_TRIER) No Action */\r
+#define PEVC_TRIER_TRIE_1 (0x1u << 0) /**< \brief (PEVC_TRIER) Enable Trigger j Interrupt */\r
+/* -------- PEVC_TRIDR : (PEVC Offset: 0x024) Trigger Interrupt Mask Disable Register -------- */\r
+#define PEVC_TRIDR_TRID_Pos 0\r
+#define PEVC_TRIDR_TRID_Msk (0xFFFFFFFFu << PEVC_TRIDR_TRID_Pos) /**< \brief (PEVC_TRIDR) Trigger Interrupt Disable */\r
+#define PEVC_TRIDR_TRID(value) ((PEVC_TRIDR_TRID_Msk & ((value) << PEVC_TRIDR_TRID_Pos)))\r
+#define PEVC_TRIDR_TRID_0 (0x0u << 0) /**< \brief (PEVC_TRIDR) No Action */\r
+#define PEVC_TRIDR_TRID_1 (0x1u << 0) /**< \brief (PEVC_TRIDR) Disable Trigger j Interrupt */\r
+/* -------- PEVC_TRIMR : (PEVC Offset: 0x028) Trigger Interrupt Mask Register -------- */\r
+#define PEVC_TRIMR_TRIM_Pos 0\r
+#define PEVC_TRIMR_TRIM_Msk (0xFFFFFFFFu << PEVC_TRIMR_TRIM_Pos) /**< \brief (PEVC_TRIMR) Trigger Interrupt Mask */\r
+#define PEVC_TRIMR_TRIM(value) ((PEVC_TRIMR_TRIM_Msk & ((value) << PEVC_TRIMR_TRIM_Pos)))\r
+#define PEVC_TRIMR_TRIM_0 (0x0u << 0) /**< \brief (PEVC_TRIMR) Trigger j Interrupt Disabled */\r
+#define PEVC_TRIMR_TRIM_1 (0x1u << 0) /**< \brief (PEVC_TRIMR) Trigger j Interrupt Enabled */\r
+/* -------- PEVC_TRSR : (PEVC Offset: 0x030) Trigger Status Register -------- */\r
+#define PEVC_TRSR_TRS_Pos 0\r
+#define PEVC_TRSR_TRS_Msk (0xFFFFFFFFu << PEVC_TRSR_TRS_Pos) /**< \brief (PEVC_TRSR) Trigger Interrupt Status */\r
+#define PEVC_TRSR_TRS(value) ((PEVC_TRSR_TRS_Msk & ((value) << PEVC_TRSR_TRS_Pos)))\r
+#define PEVC_TRSR_TRS_0 (0x0u << 0) /**< \brief (PEVC_TRSR) Channel j did not send out an Event in the past */\r
+#define PEVC_TRSR_TRS_1 (0x1u << 0) /**< \brief (PEVC_TRSR) Channel j did send out an Event in the past */\r
+/* -------- PEVC_TRSCR : (PEVC Offset: 0x034) Trigger Status Clear Register -------- */\r
+#define PEVC_TRSCR_TRSC_Pos 0\r
+#define PEVC_TRSCR_TRSC_Msk (0xFFFFFFFFu << PEVC_TRSCR_TRSC_Pos) /**< \brief (PEVC_TRSCR) Trigger Interrupt Status Clear */\r
+#define PEVC_TRSCR_TRSC(value) ((PEVC_TRSCR_TRSC_Msk & ((value) << PEVC_TRSCR_TRSC_Pos)))\r
+#define PEVC_TRSCR_TRSC_0 (0x0u << 0) /**< \brief (PEVC_TRSCR) No Action */\r
+#define PEVC_TRSCR_TRSC_1 (0x1u << 0) /**< \brief (PEVC_TRSCR) Clear TRSR[j] */\r
+/* -------- PEVC_OVIER : (PEVC Offset: 0x040) Overrun Interrupt Mask Enable Register -------- */\r
+#define PEVC_OVIER_OVIE_Pos 0\r
+#define PEVC_OVIER_OVIE_Msk (0xFFFFFFFFu << PEVC_OVIER_OVIE_Pos) /**< \brief (PEVC_OVIER) Overrun Interrupt Enable */\r
+#define PEVC_OVIER_OVIE(value) ((PEVC_OVIER_OVIE_Msk & ((value) << PEVC_OVIER_OVIE_Pos)))\r
+#define PEVC_OVIER_OVIE_0 (0x0u << 0) /**< \brief (PEVC_OVIER) No Action */\r
+#define PEVC_OVIER_OVIE_1 (0x1u << 0) /**< \brief (PEVC_OVIER) Enable Overrun Interrupt for Channel j */\r
+/* -------- PEVC_OVIDR : (PEVC Offset: 0x044) Overrun Interrupt Mask Disable Register -------- */\r
+#define PEVC_OVIDR_OVID_Pos 0\r
+#define PEVC_OVIDR_OVID_Msk (0xFFFFFFFFu << PEVC_OVIDR_OVID_Pos) /**< \brief (PEVC_OVIDR) Overrun Interrupt Disable */\r
+#define PEVC_OVIDR_OVID(value) ((PEVC_OVIDR_OVID_Msk & ((value) << PEVC_OVIDR_OVID_Pos)))\r
+#define PEVC_OVIDR_OVID_0 (0x0u << 0) /**< \brief (PEVC_OVIDR) No Action */\r
+#define PEVC_OVIDR_OVID_1 (0x1u << 0) /**< \brief (PEVC_OVIDR) Enable Overrun Interrupt for Channel j */\r
+/* -------- PEVC_OVIMR : (PEVC Offset: 0x048) Overrun Interrupt Mask Register -------- */\r
+#define PEVC_OVIMR_OVIM_Pos 0\r
+#define PEVC_OVIMR_OVIM_Msk (0xFFFFFFFFu << PEVC_OVIMR_OVIM_Pos) /**< \brief (PEVC_OVIMR) Overrun Interrupt Mask */\r
+#define PEVC_OVIMR_OVIM(value) ((PEVC_OVIMR_OVIM_Msk & ((value) << PEVC_OVIMR_OVIM_Pos)))\r
+#define PEVC_OVIMR_OVIM_0 (0x0u << 0) /**< \brief (PEVC_OVIMR) Overrun Interrupt for Channel j Disabled */\r
+#define PEVC_OVIMR_OVIM_1 (0x1u << 0) /**< \brief (PEVC_OVIMR) Overrun Interrupt for Channel j Enabled */\r
+/* -------- PEVC_OVSR : (PEVC Offset: 0x050) Overrun Status Register -------- */\r
+#define PEVC_OVSR_OVS_Pos 0\r
+#define PEVC_OVSR_OVS_Msk (0xFFFFFFFFu << PEVC_OVSR_OVS_Pos) /**< \brief (PEVC_OVSR) Overrun Interrupt Status */\r
+#define PEVC_OVSR_OVS(value) ((PEVC_OVSR_OVS_Msk & ((value) << PEVC_OVSR_OVS_Pos)))\r
+#define PEVC_OVSR_OVS_0 (0x0u << 0) /**< \brief (PEVC_OVSR) No Overrun occured on Channel j */\r
+#define PEVC_OVSR_OVS_1 (0x1u << 0) /**< \brief (PEVC_OVSR) Overrun occured on Channel j */\r
+/* -------- PEVC_OVSCR : (PEVC Offset: 0x054) Overrun Status Clear Register -------- */\r
+#define PEVC_OVSCR_OVSC_Pos 0\r
+#define PEVC_OVSCR_OVSC_Msk (0xFFFFFFFFu << PEVC_OVSCR_OVSC_Pos) /**< \brief (PEVC_OVSCR) Overrun Interrupt Status Clear */\r
+#define PEVC_OVSCR_OVSC(value) ((PEVC_OVSCR_OVSC_Msk & ((value) << PEVC_OVSCR_OVSC_Pos)))\r
+#define PEVC_OVSCR_OVSC_0 (0x0u << 0) /**< \brief (PEVC_OVSCR) No Action */\r
+#define PEVC_OVSCR_OVSC_1 (0x1u << 0) /**< \brief (PEVC_OVSCR) Clear Overrun Status Bit j */\r
+/* -------- PEVC_CHMX : (PEVC Offset: 0x100) Chmx Channel Multiplexer 0 -------- */\r
+#define PEVC_CHMX_EVMX_Pos 0\r
+#define PEVC_CHMX_EVMX_Msk (0x3Fu << PEVC_CHMX_EVMX_Pos) /**< \brief (PEVC_CHMX) Event Multiplexer */\r
+#define PEVC_CHMX_EVMX(value) ((PEVC_CHMX_EVMX_Msk & ((value) << PEVC_CHMX_EVMX_Pos)))\r
+#define PEVC_CHMX_EVMX_0 (0x0u << 0) /**< \brief (PEVC_CHMX) Event 0 */\r
+#define PEVC_CHMX_EVMX_1 (0x1u << 0) /**< \brief (PEVC_CHMX) Event 1 */\r
+#define PEVC_CHMX_SMX (0x1u << 8) /**< \brief (PEVC_CHMX) Software Event Multiplexer */\r
+#define PEVC_CHMX_SMX_0 (0x0u << 8) /**< \brief (PEVC_CHMX) Hardware events */\r
+#define PEVC_CHMX_SMX_1 (0x1u << 8) /**< \brief (PEVC_CHMX) Software event */\r
+/* -------- PEVC_EVS : (PEVC Offset: 0x200) Evs Event Shaper 0 -------- */\r
+#define PEVC_EVS_EN (0x1u << 0) /**< \brief (PEVC_EVS) Event Shaper Enable */\r
+#define PEVC_EVS_EN_0 (0x0u << 0) /**< \brief (PEVC_EVS) No Action */\r
+#define PEVC_EVS_EN_1 (0x1u << 0) /**< \brief (PEVC_EVS) Event Shaper enable */\r
+#define PEVC_EVS_IGFR (0x1u << 16) /**< \brief (PEVC_EVS) Input Glitch Filter Rise */\r
+#define PEVC_EVS_IGFR_0 (0x0u << 16) /**< \brief (PEVC_EVS) No Action */\r
+#define PEVC_EVS_IGFR_1 (0x1u << 16) /**< \brief (PEVC_EVS) Input Glitch Filter : a rising edge on event input will raise trigger output */\r
+#define PEVC_EVS_IGFF (0x1u << 17) /**< \brief (PEVC_EVS) Input Glitch Filter Fall */\r
+#define PEVC_EVS_IGFF_0 (0x0u << 17) /**< \brief (PEVC_EVS) No Action */\r
+#define PEVC_EVS_IGFF_1 (0x1u << 17) /**< \brief (PEVC_EVS) Input Glitch Filter : a falling edge on event input will raise trigger output */\r
+#define PEVC_EVS_IGFON (0x1u << 18) /**< \brief (PEVC_EVS) Input Glitch Filter Status */\r
+/* -------- PEVC_IGFDR : (PEVC Offset: 0x300) Input Glitch Filter Divider Register -------- */\r
+#define PEVC_IGFDR_IGFDR_Pos 0\r
+#define PEVC_IGFDR_IGFDR_Msk (0xFu << PEVC_IGFDR_IGFDR_Pos) /**< \brief (PEVC_IGFDR) Input Glitch Filter Divider Register */\r
+#define PEVC_IGFDR_IGFDR(value) ((PEVC_IGFDR_IGFDR_Msk & ((value) << PEVC_IGFDR_IGFDR_Pos)))\r
+/* -------- PEVC_PARAMETER : (PEVC Offset: 0x3F8) Parameter -------- */\r
+#define PEVC_PARAMETER_IGF_COUNT_Pos 0\r
+#define PEVC_PARAMETER_IGF_COUNT_Msk (0xFFu << PEVC_PARAMETER_IGF_COUNT_Pos) /**< \brief (PEVC_PARAMETER) Number of Input Glitch Filters */\r
+#define PEVC_PARAMETER_IGF_COUNT(value) ((PEVC_PARAMETER_IGF_COUNT_Msk & ((value) << PEVC_PARAMETER_IGF_COUNT_Pos)))\r
+#define PEVC_PARAMETER_EVS_COUNT_Pos 8\r
+#define PEVC_PARAMETER_EVS_COUNT_Msk (0xFFu << PEVC_PARAMETER_EVS_COUNT_Pos) /**< \brief (PEVC_PARAMETER) Number of Event Shapers */\r
+#define PEVC_PARAMETER_EVS_COUNT(value) ((PEVC_PARAMETER_EVS_COUNT_Msk & ((value) << PEVC_PARAMETER_EVS_COUNT_Pos)))\r
+#define PEVC_PARAMETER_EVIN_Pos 16\r
+#define PEVC_PARAMETER_EVIN_Msk (0xFFu << PEVC_PARAMETER_EVIN_Pos) /**< \brief (PEVC_PARAMETER) Number of Event Inputs / Generators */\r
+#define PEVC_PARAMETER_EVIN(value) ((PEVC_PARAMETER_EVIN_Msk & ((value) << PEVC_PARAMETER_EVIN_Pos)))\r
+#define PEVC_PARAMETER_TRIGOUT_Pos 24\r
+#define PEVC_PARAMETER_TRIGOUT_Msk (0xFFu << PEVC_PARAMETER_TRIGOUT_Pos) /**< \brief (PEVC_PARAMETER) Number of Trigger Outputs / Channels / Users */\r
+#define PEVC_PARAMETER_TRIGOUT(value) ((PEVC_PARAMETER_TRIGOUT_Msk & ((value) << PEVC_PARAMETER_TRIGOUT_Pos)))\r
+/* -------- PEVC_VERSION : (PEVC Offset: 0x3FC) Version -------- */\r
+#define PEVC_VERSION_VERSION_Pos 0\r
+#define PEVC_VERSION_VERSION_Msk (0xFFFu << PEVC_VERSION_VERSION_Pos) /**< \brief (PEVC_VERSION) Version Number */\r
+#define PEVC_VERSION_VERSION(value) ((PEVC_VERSION_VERSION_Msk & ((value) << PEVC_VERSION_VERSION_Pos)))\r
+#define PEVC_VERSION_VARIANT_Pos 16\r
+#define PEVC_VERSION_VARIANT_Msk (0xFu << PEVC_VERSION_VARIANT_Pos) /**< \brief (PEVC_VERSION) Variant Number */\r
+#define PEVC_VERSION_VARIANT(value) ((PEVC_VERSION_VARIANT_Msk & ((value) << PEVC_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR PICOUART */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_PICOUART Pico UART */\r
+/*@{*/\r
+\r
+#define REV_PICOUART 0x101\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief PICOUART hardware registers */\r
+typedef struct {\r
+ WoReg PICOUART_CR; /**< \brief (PICOUART Offset: 0x00) Control Register */\r
+ RwReg PICOUART_CFG; /**< \brief (PICOUART Offset: 0x04) Configuration Register */\r
+ RoReg PICOUART_SR; /**< \brief (PICOUART Offset: 0x08) Status Register */\r
+ RoReg PICOUART_RHR; /**< \brief (PICOUART Offset: 0x0C) Receive Holding Register */\r
+ RoReg Reserved1[4];\r
+ RoReg PICOUART_VERSION; /**< \brief (PICOUART Offset: 0x20) Version Register */\r
+} Picouart;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- PICOUART_CR : (PICOUART Offset: 0x00) Control Register -------- */\r
+#define PICOUART_CR_EN (0x1u << 0) /**< \brief (PICOUART_CR) Enable */\r
+#define PICOUART_CR_DIS (0x1u << 1) /**< \brief (PICOUART_CR) Disable */\r
+/* -------- PICOUART_CFG : (PICOUART Offset: 0x04) Configuration Register -------- */\r
+#define PICOUART_CFG_SOURCE_Pos 0\r
+#define PICOUART_CFG_SOURCE_Msk (0x3u << PICOUART_CFG_SOURCE_Pos) /**< \brief (PICOUART_CFG) Source Enable Mode */\r
+#define PICOUART_CFG_SOURCE(value) ((PICOUART_CFG_SOURCE_Msk & ((value) << PICOUART_CFG_SOURCE_Pos)))\r
+#define PICOUART_CFG_ACTION (0x1u << 2) /**< \brief (PICOUART_CFG) Action to perform */\r
+#define PICOUART_CFG_MATCH_Pos 8\r
+#define PICOUART_CFG_MATCH_Msk (0xFFu << PICOUART_CFG_MATCH_Pos) /**< \brief (PICOUART_CFG) Data Match */\r
+#define PICOUART_CFG_MATCH(value) ((PICOUART_CFG_MATCH_Msk & ((value) << PICOUART_CFG_MATCH_Pos)))\r
+/* -------- PICOUART_SR : (PICOUART Offset: 0x08) Status Register -------- */\r
+#define PICOUART_SR_EN (0x1u << 0) /**< \brief (PICOUART_SR) Enable Interrupt Status */\r
+#define PICOUART_SR_DRDY (0x1u << 1) /**< \brief (PICOUART_SR) Data Ready Interrupt Status */\r
+/* -------- PICOUART_RHR : (PICOUART Offset: 0x0C) Receive Holding Register -------- */\r
+#define PICOUART_RHR_CDATA_Pos 0\r
+#define PICOUART_RHR_CDATA_Msk (0xFFFFFFFFu << PICOUART_RHR_CDATA_Pos) /**< \brief (PICOUART_RHR) Received Data */\r
+#define PICOUART_RHR_CDATA(value) ((PICOUART_RHR_CDATA_Msk & ((value) << PICOUART_RHR_CDATA_Pos)))\r
+/* -------- PICOUART_VERSION : (PICOUART Offset: 0x20) Version Register -------- */\r
+#define PICOUART_VERSION_VERSION_Pos 0\r
+#define PICOUART_VERSION_VERSION_Msk (0xFFFu << PICOUART_VERSION_VERSION_Pos) /**< \brief (PICOUART_VERSION) Version Number */\r
+#define PICOUART_VERSION_VERSION(value) ((PICOUART_VERSION_VERSION_Msk & ((value) << PICOUART_VERSION_VERSION_Pos)))\r
+#define PICOUART_VERSION_VARIANT_Pos 16\r
+#define PICOUART_VERSION_VARIANT_Msk (0xFu << PICOUART_VERSION_VARIANT_Pos) /**< \brief (PICOUART_VERSION) Variant Number */\r
+#define PICOUART_VERSION_VARIANT(value) ((PICOUART_VERSION_VARIANT_Msk & ((value) << PICOUART_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR PM */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_PM Power Manager */\r
+/*@{*/\r
+\r
+#define REV_PM 0x441\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief PM hardware registers */\r
+typedef struct {\r
+ RwReg PM_MCCTRL; /**< \brief (PM Offset: 0x000) Main Clock Control */\r
+ RwReg PM_CPUSEL; /**< \brief (PM Offset: 0x004) CPU Clock Select */\r
+ RoReg Reserved1[1];\r
+ RwReg PM_PBASEL; /**< \brief (PM Offset: 0x00C) PBA Clock Select */\r
+ RwReg PM_PBBSEL; /**< \brief (PM Offset: 0x010) PBB Clock Select */\r
+ RwReg PM_PBCSEL; /**< \brief (PM Offset: 0x014) PBC Clock Select */\r
+ RwReg PM_PBDSEL; /**< \brief (PM Offset: 0x018) PBD Clock Select */\r
+ RoReg Reserved2[1];\r
+ RwReg PM_CPUMASK; /**< \brief (PM Offset: 0x020) CPU Mask */\r
+ RwReg PM_HSBMASK; /**< \brief (PM Offset: 0x024) HSB Mask */\r
+ RwReg PM_PBAMASK; /**< \brief (PM Offset: 0x028) PBA Mask */\r
+ RwReg PM_PBBMASK; /**< \brief (PM Offset: 0x02C) PBB Mask */\r
+ RwReg PM_PBCMASK; /**< \brief (PM Offset: 0x030) PBC Mask */\r
+ RwReg PM_PBDMASK; /**< \brief (PM Offset: 0x034) PBD Mask */\r
+ RoReg Reserved3[2];\r
+ RwReg PM_PBADIVMASK; /**< \brief (PM Offset: 0x040) PBA Divided Clock Mask */\r
+ RoReg Reserved4[4];\r
+ RwReg PM_CFDCTRL; /**< \brief (PM Offset: 0x054) Clock Failure Detector Control */\r
+ WoReg PM_UNLOCK; /**< \brief (PM Offset: 0x058) Unlock Register */\r
+ RoReg Reserved5[25];\r
+ WoReg PM_IER; /**< \brief (PM Offset: 0x0C0) Interrupt Enable Register */\r
+ WoReg PM_IDR; /**< \brief (PM Offset: 0x0C4) Interrupt Disable Register */\r
+ RoReg PM_IMR; /**< \brief (PM Offset: 0x0C8) Interrupt Mask Register */\r
+ RoReg PM_ISR; /**< \brief (PM Offset: 0x0CC) Interrupt Status Register */\r
+ WoReg PM_ICR; /**< \brief (PM Offset: 0x0D0) Interrupt Clear Register */\r
+ RoReg PM_SR; /**< \brief (PM Offset: 0x0D4) Status Register */\r
+ RoReg Reserved6[34];\r
+ RwReg PM_PPCR; /**< \brief (PM Offset: 0x160) Peripheral Power Control Register */\r
+ RoReg Reserved7[7];\r
+ RoReg PM_RCAUSE; /**< \brief (PM Offset: 0x180) Reset Cause Register */\r
+ RoReg PM_WCAUSE; /**< \brief (PM Offset: 0x184) Wake Cause Register */\r
+ RwReg PM_AWEN; /**< \brief (PM Offset: 0x188) Asynchronous Wake Enable */\r
+ RoReg Reserved8[1];\r
+ RwReg PM_OBS; /**< \brief (PM Offset: 0x190) Obsvervability */\r
+ RwReg PM_FASTSLEEP; /**< \brief (PM Offset: 0x194) Fast Sleep Register */\r
+ RoReg Reserved9[152];\r
+ RoReg PM_CONFIG; /**< \brief (PM Offset: 0x3F8) Configuration Register */\r
+ RoReg PM_VERSION; /**< \brief (PM Offset: 0x3FC) Version Register */\r
+} Pm;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- PM_MCCTRL : (PM Offset: 0x000) Main Clock Control -------- */\r
+#define PM_MCCTRL_MCSEL_Pos 0\r
+#define PM_MCCTRL_MCSEL_Msk (0x7u << PM_MCCTRL_MCSEL_Pos) /**< \brief (PM_MCCTRL) Main Clock Select */\r
+#define PM_MCCTRL_MCSEL(value) ((PM_MCCTRL_MCSEL_Msk & ((value) << PM_MCCTRL_MCSEL_Pos)))\r
+/* -------- PM_CPUSEL : (PM Offset: 0x004) CPU Clock Select -------- */\r
+#define PM_CPUSEL_CPUSEL_Pos 0\r
+#define PM_CPUSEL_CPUSEL_Msk (0x7u << PM_CPUSEL_CPUSEL_Pos) /**< \brief (PM_CPUSEL) CPU Clock Select */\r
+#define PM_CPUSEL_CPUSEL(value) ((PM_CPUSEL_CPUSEL_Msk & ((value) << PM_CPUSEL_CPUSEL_Pos)))\r
+#define PM_CPUSEL_CPUSEL_0 (0x0u << 0) /**< \brief (PM_CPUSEL) fCPU:fmain. CPUDIV: */\r
+#define PM_CPUSEL_CPUSEL_1 (0x1u << 0) /**< \brief (PM_CPUSEL) fCPU:fmain / 2^(CPUSEL+1) */\r
+#define PM_CPUSEL_CPUDIV (0x1u << 7) /**< \brief (PM_CPUSEL) CPU Division */\r
+/* -------- PM_PBASEL : (PM Offset: 0x00C) PBA Clock Select -------- */\r
+#define PM_PBASEL_PBSEL_Pos 0\r
+#define PM_PBASEL_PBSEL_Msk (0x7u << PM_PBASEL_PBSEL_Pos) /**< \brief (PM_PBASEL) PBA Clock Select */\r
+#define PM_PBASEL_PBSEL(value) ((PM_PBASEL_PBSEL_Msk & ((value) << PM_PBASEL_PBSEL_Pos)))\r
+#define PM_PBASEL_PBDIV (0x1u << 7) /**< \brief (PM_PBASEL) PBA Division Select */\r
+/* -------- PM_PBBSEL : (PM Offset: 0x010) PBB Clock Select -------- */\r
+#define PM_PBBSEL_PBSEL_Pos 0\r
+#define PM_PBBSEL_PBSEL_Msk (0x7u << PM_PBBSEL_PBSEL_Pos) /**< \brief (PM_PBBSEL) PBB Clock Select */\r
+#define PM_PBBSEL_PBSEL(value) ((PM_PBBSEL_PBSEL_Msk & ((value) << PM_PBBSEL_PBSEL_Pos)))\r
+#define PM_PBBSEL_PBDIV (0x1u << 7) /**< \brief (PM_PBBSEL) PBB Division Select */\r
+/* -------- PM_PBCSEL : (PM Offset: 0x014) PBC Clock Select -------- */\r
+#define PM_PBCSEL_PBSEL_Pos 0\r
+#define PM_PBCSEL_PBSEL_Msk (0x7u << PM_PBCSEL_PBSEL_Pos) /**< \brief (PM_PBCSEL) PBC Clock Select */\r
+#define PM_PBCSEL_PBSEL(value) ((PM_PBCSEL_PBSEL_Msk & ((value) << PM_PBCSEL_PBSEL_Pos)))\r
+#define PM_PBCSEL_PBDIV (0x1u << 7) /**< \brief (PM_PBCSEL) PBC Division Select */\r
+/* -------- PM_PBDSEL : (PM Offset: 0x018) PBD Clock Select -------- */\r
+#define PM_PBDSEL_PBSEL_Pos 0\r
+#define PM_PBDSEL_PBSEL_Msk (0x7u << PM_PBDSEL_PBSEL_Pos) /**< \brief (PM_PBDSEL) PBD Clock Select */\r
+#define PM_PBDSEL_PBSEL(value) ((PM_PBDSEL_PBSEL_Msk & ((value) << PM_PBDSEL_PBSEL_Pos)))\r
+#define PM_PBDSEL_PBDIV (0x1u << 7) /**< \brief (PM_PBDSEL) PBD Division Select */\r
+/* -------- PM_CPUMASK : (PM Offset: 0x020) CPU Mask -------- */\r
+#define PM_CPUMASK_OCD (0x1u << 0) /**< \brief (PM_CPUMASK) OCD CPU Clock Mask */\r
+/* -------- PM_HSBMASK : (PM Offset: 0x024) HSB Mask -------- */\r
+#define PM_HSBMASK_PDCA (0x1u << 0) /**< \brief (PM_HSBMASK) PDCA HSB Clock Mask */\r
+#define PM_HSBMASK_HFLASHC (0x1u << 1) /**< \brief (PM_HSBMASK) HFLASHC HSB Clock Mask */\r
+#define PM_HSBMASK_HRAMC1 (0x1u << 2) /**< \brief (PM_HSBMASK) HRAMC1 HSB Clock Mask */\r
+#define PM_HSBMASK_USBC (0x1u << 3) /**< \brief (PM_HSBMASK) USBC HSB Clock Mask */\r
+#define PM_HSBMASK_CRCCU (0x1u << 4) /**< \brief (PM_HSBMASK) CRCCU HSB Clock Mask */\r
+#define PM_HSBMASK_HTOP0 (0x1u << 5) /**< \brief (PM_HSBMASK) HTOP0 HSB Clock Mask */\r
+#define PM_HSBMASK_HTOP1 (0x1u << 6) /**< \brief (PM_HSBMASK) HTOP1 HSB Clock Mask */\r
+#define PM_HSBMASK_HTOP2 (0x1u << 7) /**< \brief (PM_HSBMASK) HTOP2 HSB Clock Mask */\r
+#define PM_HSBMASK_HTOP3 (0x1u << 8) /**< \brief (PM_HSBMASK) HTOP3 HSB Clock Mask */\r
+#define PM_HSBMASK_AESA (0x1u << 9) /**< \brief (PM_HSBMASK) AESA HSB Clock Mask */\r
+/* -------- PM_PBAMASK : (PM Offset: 0x028) PBA Mask -------- */\r
+#define PM_PBAMASK_IISC (0x1u << 0) /**< \brief (PM_PBAMASK) IISC PB Clock Mask */\r
+#define PM_PBAMASK_SPI (0x1u << 1) /**< \brief (PM_PBAMASK) SPI PB Clock Mask */\r
+#define PM_PBAMASK_TC0 (0x1u << 2) /**< \brief (PM_PBAMASK) TC0 PB Clock Mask */\r
+#define PM_PBAMASK_TC1 (0x1u << 3) /**< \brief (PM_PBAMASK) TC1 PB Clock Mask */\r
+#define PM_PBAMASK_TWIM0 (0x1u << 4) /**< \brief (PM_PBAMASK) TWIM0 PB Clock Mask */\r
+#define PM_PBAMASK_TWIS0 (0x1u << 5) /**< \brief (PM_PBAMASK) TWIS0 PB Clock Mask */\r
+#define PM_PBAMASK_TWIM1 (0x1u << 6) /**< \brief (PM_PBAMASK) TWIM1 PB Clock Mask */\r
+#define PM_PBAMASK_TWIS1 (0x1u << 7) /**< \brief (PM_PBAMASK) TWIS1 PB Clock Mask */\r
+#define PM_PBAMASK_USART0 (0x1u << 8) /**< \brief (PM_PBAMASK) USART0 PB Clock Mask */\r
+#define PM_PBAMASK_USART1 (0x1u << 9) /**< \brief (PM_PBAMASK) USART1 PB Clock Mask */\r
+#define PM_PBAMASK_USART2 (0x1u << 10) /**< \brief (PM_PBAMASK) USART2 PB Clock Mask */\r
+#define PM_PBAMASK_USART3 (0x1u << 11) /**< \brief (PM_PBAMASK) USART3 PB Clock Mask */\r
+#define PM_PBAMASK_ADCIFE (0x1u << 12) /**< \brief (PM_PBAMASK) ADCIFE PB Clock Mask */\r
+#define PM_PBAMASK_DACC (0x1u << 13) /**< \brief (PM_PBAMASK) DACC PB Clock Mask */\r
+#define PM_PBAMASK_ACIFC (0x1u << 14) /**< \brief (PM_PBAMASK) ACIFC PB Clock Mask */\r
+#define PM_PBAMASK_GLOC (0x1u << 15) /**< \brief (PM_PBAMASK) GLOC PB Clock Mask */\r
+#define PM_PBAMASK_ABDACB (0x1u << 16) /**< \brief (PM_PBAMASK) ABDACB PB Clock Mask */\r
+#define PM_PBAMASK_TRNG (0x1u << 17) /**< \brief (PM_PBAMASK) TRNG PB Clock Mask */\r
+#define PM_PBAMASK_PARC (0x1u << 18) /**< \brief (PM_PBAMASK) PARC PB Clock Mask */\r
+#define PM_PBAMASK_CATB (0x1u << 19) /**< \brief (PM_PBAMASK) CATB PB Clock Mask */\r
+#define PM_PBAMASK_TWIM2 (0x1u << 21) /**< \brief (PM_PBAMASK) TWIM2 PB Clock Mask */\r
+#define PM_PBAMASK_TWIM3 (0x1u << 22) /**< \brief (PM_PBAMASK) TWIM3 PB Clock Mask */\r
+#define PM_PBAMASK_LCDCA (0x1u << 23) /**< \brief (PM_PBAMASK) LCDCA PB Clock Mask */\r
+/* -------- PM_PBBMASK : (PM Offset: 0x02C) PBB Mask -------- */\r
+#define PM_PBBMASK_HFLASHC (0x1u << 0) /**< \brief (PM_PBBMASK) HFLASHC PB Clock Mask */\r
+#define PM_PBBMASK_HCACHE (0x1u << 1) /**< \brief (PM_PBBMASK) HCACHE PB Clock Mask */\r
+#define PM_PBBMASK_HMATRIX (0x1u << 2) /**< \brief (PM_PBBMASK) HMATRIX PB Clock Mask */\r
+#define PM_PBBMASK_PDCA (0x1u << 3) /**< \brief (PM_PBBMASK) PDCA PB Clock Mask */\r
+#define PM_PBBMASK_CRCCU (0x1u << 4) /**< \brief (PM_PBBMASK) CRCCU PB Clock Mask */\r
+#define PM_PBBMASK_USBC (0x1u << 5) /**< \brief (PM_PBBMASK) USBC PB Clock Mask */\r
+#define PM_PBBMASK_PEVC (0x1u << 6) /**< \brief (PM_PBBMASK) PEVC PB Clock Mask */\r
+/* -------- PM_PBCMASK : (PM Offset: 0x030) PBC Mask -------- */\r
+#define PM_PBCMASK_PM (0x1u << 0) /**< \brief (PM_PBCMASK) PM PB Clock Mask */\r
+#define PM_PBCMASK_CHIPID (0x1u << 1) /**< \brief (PM_PBCMASK) CHIPID PB Clock Mask */\r
+#define PM_PBCMASK_SCIF (0x1u << 2) /**< \brief (PM_PBCMASK) SCIF PB Clock Mask */\r
+#define PM_PBCMASK_FREQM (0x1u << 3) /**< \brief (PM_PBCMASK) FREQM PB Clock Mask */\r
+#define PM_PBCMASK_GPIO (0x1u << 4) /**< \brief (PM_PBCMASK) GPIO PB Clock Mask */\r
+/* -------- PM_PBDMASK : (PM Offset: 0x034) PBD Mask -------- */\r
+#define PM_PBDMASK_BPM (0x1u << 0) /**< \brief (PM_PBDMASK) BPM PB Clock Mask */\r
+#define PM_PBDMASK_BSCIF (0x1u << 1) /**< \brief (PM_PBDMASK) BSCIF PB Clock Mask */\r
+#define PM_PBDMASK_AST (0x1u << 2) /**< \brief (PM_PBDMASK) AST PB Clock Mask */\r
+#define PM_PBDMASK_WDT (0x1u << 3) /**< \brief (PM_PBDMASK) WDT PB Clock Mask */\r
+#define PM_PBDMASK_EIC (0x1u << 4) /**< \brief (PM_PBDMASK) EIC PB Clock Mask */\r
+#define PM_PBDMASK_PICOUART (0x1u << 5) /**< \brief (PM_PBDMASK) PICOUART PB Clock Mask */\r
+/* -------- PM_CFDCTRL : (PM Offset: 0x054) Clock Failure Detector Control -------- */\r
+#define PM_CFDCTRL_CFDEN (0x1u << 0) /**< \brief (PM_CFDCTRL) Clock Failure Detection Enable */\r
+#define PM_CFDCTRL_SFV (0x1u << 31) /**< \brief (PM_CFDCTRL) Store Final Value */\r
+/* -------- PM_UNLOCK : (PM Offset: 0x058) Unlock Register -------- */\r
+#define PM_UNLOCK_ADDR_Pos 0\r
+#define PM_UNLOCK_ADDR_Msk (0x3FFu << PM_UNLOCK_ADDR_Pos) /**< \brief (PM_UNLOCK) Unlock Address */\r
+#define PM_UNLOCK_ADDR(value) ((PM_UNLOCK_ADDR_Msk & ((value) << PM_UNLOCK_ADDR_Pos)))\r
+#define PM_UNLOCK_KEY_Pos 24\r
+#define PM_UNLOCK_KEY_Msk (0xFFu << PM_UNLOCK_KEY_Pos) /**< \brief (PM_UNLOCK) Unlock Key */\r
+#define PM_UNLOCK_KEY(value) ((PM_UNLOCK_KEY_Msk & ((value) << PM_UNLOCK_KEY_Pos)))\r
+/* -------- PM_IER : (PM Offset: 0x0C0) Interrupt Enable Register -------- */\r
+#define PM_IER_CFD (0x1u << 0) /**< \brief (PM_IER) Clock Failure Detected Interrupt Enable */\r
+#define PM_IER_CKRDY (0x1u << 5) /**< \brief (PM_IER) Clock Ready Interrupt Enable */\r
+#define PM_IER_WAKE (0x1u << 8) /**< \brief (PM_IER) Wake up Interrupt Enable */\r
+#define PM_IER_WAKE_0 (0x0u << 8) /**< \brief (PM_IER) No effect */\r
+#define PM_IER_WAKE_1 (0x1u << 8) /**< \brief (PM_IER) Disable Interrupt. */\r
+#define PM_IER_AE (0x1u << 31) /**< \brief (PM_IER) Access Error Interrupt Enable */\r
+/* -------- PM_IDR : (PM Offset: 0x0C4) Interrupt Disable Register -------- */\r
+#define PM_IDR_CFD (0x1u << 0) /**< \brief (PM_IDR) Clock Failure Detected Interrupt Disable */\r
+#define PM_IDR_CKRDY (0x1u << 5) /**< \brief (PM_IDR) Clock Ready Interrupt Disable */\r
+#define PM_IDR_WAKE (0x1u << 8) /**< \brief (PM_IDR) Wake up Interrupt Disable */\r
+#define PM_IDR_WAKE_0 (0x0u << 8) /**< \brief (PM_IDR) No effect */\r
+#define PM_IDR_WAKE_1 (0x1u << 8) /**< \brief (PM_IDR) Disable Interrupt. */\r
+#define PM_IDR_AE (0x1u << 31) /**< \brief (PM_IDR) Access Error Interrupt Disable */\r
+/* -------- PM_IMR : (PM Offset: 0x0C8) Interrupt Mask Register -------- */\r
+#define PM_IMR_CFD (0x1u << 0) /**< \brief (PM_IMR) Clock Failure Detected Interrupt Mask */\r
+#define PM_IMR_CKRDY (0x1u << 5) /**< \brief (PM_IMR) Clock Ready Interrupt Mask */\r
+#define PM_IMR_WAKE (0x1u << 8) /**< \brief (PM_IMR) Wake up Interrupt Mask */\r
+#define PM_IMR_WAKE_0 (0x0u << 8) /**< \brief (PM_IMR) No effect */\r
+#define PM_IMR_WAKE_1 (0x1u << 8) /**< \brief (PM_IMR) Disable Interrupt. */\r
+#define PM_IMR_AE (0x1u << 31) /**< \brief (PM_IMR) Access Error Interrupt Mask */\r
+/* -------- PM_ISR : (PM Offset: 0x0CC) Interrupt Status Register -------- */\r
+#define PM_ISR_CFD (0x1u << 0) /**< \brief (PM_ISR) Clock Failure Detected Interrupt Status */\r
+#define PM_ISR_CKRDY (0x1u << 5) /**< \brief (PM_ISR) Clock Ready Interrupt Status */\r
+#define PM_ISR_WAKE (0x1u << 8) /**< \brief (PM_ISR) Wake up Interrupt Status */\r
+#define PM_ISR_WAKE_0 (0x0u << 8) /**< \brief (PM_ISR) No effect */\r
+#define PM_ISR_WAKE_1 (0x1u << 8) /**< \brief (PM_ISR) Disable Interrupt. */\r
+#define PM_ISR_AE (0x1u << 31) /**< \brief (PM_ISR) Access Error Interrupt Status */\r
+/* -------- PM_ICR : (PM Offset: 0x0D0) Interrupt Clear Register -------- */\r
+#define PM_ICR_CFD (0x1u << 0) /**< \brief (PM_ICR) Clock Failure Detected Interrupt Status Clear */\r
+#define PM_ICR_CKRDY (0x1u << 5) /**< \brief (PM_ICR) Clock Ready Interrupt Status Clear */\r
+#define PM_ICR_WAKE (0x1u << 8) /**< \brief (PM_ICR) Wake up Interrupt Status Clear */\r
+#define PM_ICR_AE (0x1u << 31) /**< \brief (PM_ICR) Access Error Interrupt Status Clear */\r
+/* -------- PM_SR : (PM Offset: 0x0D4) Status Register -------- */\r
+#define PM_SR_CFD (0x1u << 0) /**< \brief (PM_SR) Clock Failure Detected */\r
+#define PM_SR_OCP (0x1u << 1) /**< \brief (PM_SR) Over Clock Detected */\r
+#define PM_SR_CKRDY (0x1u << 5) /**< \brief (PM_SR) Clock Ready */\r
+#define PM_SR_WAKE (0x1u << 8) /**< \brief (PM_SR) Wake up */\r
+#define PM_SR_WAKE_0 (0x0u << 8) /**< \brief (PM_SR) No effect */\r
+#define PM_SR_WAKE_1 (0x1u << 8) /**< \brief (PM_SR) Disable Interrupt. */\r
+#define PM_SR_PERRDY (0x1u << 28) /**< \brief (PM_SR) Peripheral Ready */\r
+#define PM_SR_AE (0x1u << 31) /**< \brief (PM_SR) Access Error */\r
+/* -------- PM_PPCR : (PM Offset: 0x160) Peripheral Power Control Register -------- */\r
+#define PM_PPCR_RSTPUN (0x1u << 0) /**< \brief (PM_PPCR) Reset Pullup */\r
+#define PM_PPCR_CATBRCMASK (0x1u << 1) /**< \brief (PM_PPCR) CAT Request Clock Mask */\r
+#define PM_PPCR_ACIFCRCMASK (0x1u << 2) /**< \brief (PM_PPCR) ACIFC Request Clock Mask */\r
+#define PM_PPCR_ASTRCMASK (0x1u << 3) /**< \brief (PM_PPCR) AST Request Clock Mask */\r
+#define PM_PPCR_TWIS0RCMASK (0x1u << 4) /**< \brief (PM_PPCR) TWIS0 Request Clock Mask */\r
+#define PM_PPCR_TWIS1RCMASK (0x1u << 5) /**< \brief (PM_PPCR) TWIS1 Request Clock Mask */\r
+#define PM_PPCR_PEVCRCMASK (0x1u << 6) /**< \brief (PM_PPCR) PEVC Request Clock Mask */\r
+#define PM_PPCR_ADCIFERCMASK (0x1u << 7) /**< \brief (PM_PPCR) ADCIFE Request Clock Mask */\r
+#define PM_PPCR_VREGRCMASK (0x1u << 8) /**< \brief (PM_PPCR) VREG Request Clock Mask */\r
+#define PM_PPCR_FWBGREF (0x1u << 9) /**< \brief (PM_PPCR) Flash Wait BGREF */\r
+#define PM_PPCR_FWBOD18 (0x1u << 10) /**< \brief (PM_PPCR) Flash Wait BOD18 */\r
+/* -------- PM_RCAUSE : (PM Offset: 0x180) Reset Cause Register -------- */\r
+#define PM_RCAUSE_POR (0x1u << 0) /**< \brief (PM_RCAUSE) Power-on Reset */\r
+#define PM_RCAUSE_BOD (0x1u << 1) /**< \brief (PM_RCAUSE) Brown-out Reset */\r
+#define PM_RCAUSE_EXT (0x1u << 2) /**< \brief (PM_RCAUSE) External Reset Pin */\r
+#define PM_RCAUSE_WDT (0x1u << 3) /**< \brief (PM_RCAUSE) Watchdog Reset */\r
+#define PM_RCAUSE_OCDRST (0x1u << 8) /**< \brief (PM_RCAUSE) OCD Reset */\r
+#define PM_RCAUSE_POR33 (0x1u << 10) /**< \brief (PM_RCAUSE) Power-on Reset */\r
+#define PM_RCAUSE_BOD33 (0x1u << 13) /**< \brief (PM_RCAUSE) Brown-out 3.3V Reset */\r
+/* -------- PM_WCAUSE : (PM Offset: 0x184) Wake Cause Register -------- */\r
+#define PM_WCAUSE_TWI_SLAVE_0 (0x1u << 0) /**< \brief (PM_WCAUSE) Two-wire Slave Interface 0 */\r
+#define PM_WCAUSE_TWI_SLAVE_1 (0x1u << 1) /**< \brief (PM_WCAUSE) Two-wire Slave Interface 1 */\r
+#define PM_WCAUSE_USBC (0x1u << 2) /**< \brief (PM_WCAUSE) USB Device and Embedded Host Interface */\r
+#define PM_WCAUSE_PSOK (0x1u << 3) /**< \brief (PM_WCAUSE) Power Scaling OK */\r
+#define PM_WCAUSE_BOD18_IRQ (0x1u << 4) /**< \brief (PM_WCAUSE) BOD18 Interrupt */\r
+#define PM_WCAUSE_BOD33_IRQ (0x1u << 5) /**< \brief (PM_WCAUSE) BOD33 Interrupt */\r
+#define PM_WCAUSE_PICOUART (0x1u << 6) /**< \brief (PM_WCAUSE) Picopower UART */\r
+#define PM_WCAUSE_LCDCA (0x1u << 7) /**< \brief (PM_WCAUSE) LCD Controller */\r
+#define PM_WCAUSE_EIC (0x1u << 16) /**< \brief (PM_WCAUSE) External Interrupt Controller */\r
+#define PM_WCAUSE_AST (0x1u << 17) /**< \brief (PM_WCAUSE) Asynchronous Timer */\r
+/* -------- PM_AWEN : (PM Offset: 0x188) Asynchronous Wake Enable -------- */\r
+#define PM_AWEN_AWEN_Pos 0\r
+#define PM_AWEN_AWEN_Msk (0xFFFFFFFFu << PM_AWEN_AWEN_Pos) /**< \brief (PM_AWEN) Asynchronous Wake Up */\r
+#define PM_AWEN_AWEN(value) ((PM_AWEN_AWEN_Msk & ((value) << PM_AWEN_AWEN_Pos)))\r
+/* -------- PM_OBS : (PM Offset: 0x190) Obsvervability -------- */\r
+/* -------- PM_FASTSLEEP : (PM Offset: 0x194) Fast Sleep Register -------- */\r
+#define PM_FASTSLEEP_OSC (0x1u << 0) /**< \brief (PM_FASTSLEEP) Oscillator */\r
+#define PM_FASTSLEEP_PLL (0x1u << 8) /**< \brief (PM_FASTSLEEP) PLL */\r
+#define PM_FASTSLEEP_FASTRCOSC_Pos 16\r
+#define PM_FASTSLEEP_FASTRCOSC_Msk (0x1Fu << PM_FASTSLEEP_FASTRCOSC_Pos) /**< \brief (PM_FASTSLEEP) RC80 or FLO */\r
+#define PM_FASTSLEEP_FASTRCOSC(value) ((PM_FASTSLEEP_FASTRCOSC_Msk & ((value) << PM_FASTSLEEP_FASTRCOSC_Pos)))\r
+#define PM_FASTSLEEP_DFLL (0x1u << 24) /**< \brief (PM_FASTSLEEP) DFLL */\r
+/* -------- PM_CONFIG : (PM Offset: 0x3F8) Configuration Register -------- */\r
+#define PM_CONFIG_PBA (0x1u << 0) /**< \brief (PM_CONFIG) APBA Implemented */\r
+#define PM_CONFIG_PBB (0x1u << 1) /**< \brief (PM_CONFIG) APBB Implemented */\r
+#define PM_CONFIG_PBC (0x1u << 2) /**< \brief (PM_CONFIG) APBC Implemented */\r
+#define PM_CONFIG_PBD (0x1u << 3) /**< \brief (PM_CONFIG) APBD Implemented */\r
+#define PM_CONFIG_HSBPEVC (0x1u << 7) /**< \brief (PM_CONFIG) HSB PEVC Clock Implemented */\r
+/* -------- PM_VERSION : (PM Offset: 0x3FC) Version Register -------- */\r
+#define PM_VERSION_VERSION_Pos 0\r
+#define PM_VERSION_VERSION_Msk (0xFFFu << PM_VERSION_VERSION_Pos) /**< \brief (PM_VERSION) Version number */\r
+#define PM_VERSION_VERSION(value) ((PM_VERSION_VERSION_Msk & ((value) << PM_VERSION_VERSION_Pos)))\r
+#define PM_VERSION_VARIANT_Pos 16\r
+#define PM_VERSION_VARIANT_Msk (0xFu << PM_VERSION_VARIANT_Pos) /**< \brief (PM_VERSION) Variant number */\r
+#define PM_VERSION_VARIANT(value) ((PM_VERSION_VARIANT_Msk & ((value) << PM_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR SCIF */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_SCIF System Control Interface */\r
+/*@{*/\r
+\r
+#define REV_SCIF 0x130\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief ScifGcctrl hardware registers */\r
+typedef struct {\r
+ RwReg SCIF_GCCTRL; /**< \brief (ScifGcctrl Offset: 0x000) Generic Clock Control */\r
+} ScifGcctrl;\r
+/** \brief ScifPll hardware registers */\r
+typedef struct {\r
+ RwReg SCIF_PLL; /**< \brief (ScifPll Offset: 0x000) PLL0 Control Register */\r
+} ScifPll;\r
+/** \brief SCIF hardware registers */\r
+typedef struct {\r
+ WoReg SCIF_IER; /**< \brief (SCIF Offset: 0x000) Interrupt Enable Register */\r
+ WoReg SCIF_IDR; /**< \brief (SCIF Offset: 0x004) Interrupt Disable Register */\r
+ RoReg SCIF_IMR; /**< \brief (SCIF Offset: 0x008) Interrupt Mask Register */\r
+ RoReg SCIF_ISR; /**< \brief (SCIF Offset: 0x00C) Interrupt Status Register */\r
+ WoReg SCIF_ICR; /**< \brief (SCIF Offset: 0x010) Interrupt Clear Register */\r
+ RoReg SCIF_PCLKSR; /**< \brief (SCIF Offset: 0x014) Power and Clocks Status Register */\r
+ WoReg SCIF_UNLOCK; /**< \brief (SCIF Offset: 0x018) Unlock Register */\r
+ RwReg SCIF_CSCR; /**< \brief (SCIF Offset: 0x01C) Chip Specific Configuration Register */\r
+ RwReg SCIF_OSCCTRL0; /**< \brief (SCIF Offset: 0x020) Oscillator Control Register */\r
+ ScifPll SCIF_PLL[1]; /**< \brief (SCIF Offset: 0x024) ScifPll groups */\r
+ RwReg SCIF_DFLL0CONF; /**< \brief (SCIF Offset: 0x028) DFLL0 Config Register */\r
+ RwReg SCIF_DFLL0VAL; /**< \brief (SCIF Offset: 0x02C) DFLL Value Register */\r
+ RwReg SCIF_DFLL0MUL; /**< \brief (SCIF Offset: 0x030) DFLL0 Multiplier Register */\r
+ RwReg SCIF_DFLL0STEP; /**< \brief (SCIF Offset: 0x034) DFLL0 Step Register */\r
+ RwReg SCIF_DFLL0SSG; /**< \brief (SCIF Offset: 0x038) DFLL0 Spread Spectrum Generator Control Register */\r
+ RoReg SCIF_DFLL0RATIO; /**< \brief (SCIF Offset: 0x03C) DFLL0 Ratio Registe */\r
+ WoReg SCIF_DFLL0SYNC; /**< \brief (SCIF Offset: 0x040) DFLL0 Synchronization Register */\r
+ RwReg SCIF_RCCR; /**< \brief (SCIF Offset: 0x044) System RC Oscillator Calibration Register */\r
+ RwReg SCIF_RCFASTCFG; /**< \brief (SCIF Offset: 0x048) 4/8/12 MHz RC Oscillator Configuration\r
+Register */\r
+ RwReg SCIF_RCFASTSR; /**< \brief (SCIF Offset: 0x04C) 4/8/12 MHz RC Oscillator Status Register */\r
+ RwReg SCIF_RC80MCR; /**< \brief (SCIF Offset: 0x050) 80 MHz RC Oscillator Register */\r
+ RoReg Reserved1[4];\r
+ RwReg SCIF_HRPCR; /**< \brief (SCIF Offset: 0x064) High Resolution Prescaler Control Register */\r
+ RwReg SCIF_FPCR; /**< \brief (SCIF Offset: 0x068) Fractional Prescaler Control Register */\r
+ RwReg SCIF_FPMUL; /**< \brief (SCIF Offset: 0x06C) Fractional Prescaler Multiplier Register */\r
+ RwReg SCIF_FPDIV; /**< \brief (SCIF Offset: 0x070) Fractional Prescaler DIVIDER Register */\r
+ ScifGcctrl SCIF_GCCTRL[12]; /**< \brief (SCIF Offset: 0x074) ScifGcctrl groups */\r
+ RoReg Reserved2[205];\r
+ RoReg SCIF_RCFASTVERSION; /**< \brief (SCIF Offset: 0x3D8) 4/8/12 MHz RC Oscillator Version Register */\r
+ RoReg SCIF_GCLKPRESCVERSION; /**< \brief (SCIF Offset: 0x3DC) Generic Clock Prescaler Version Register */\r
+ RoReg SCIF_PLLIFAVERSION; /**< \brief (SCIF Offset: 0x3E0) PLL Version Register */\r
+ RoReg SCIF_OSCIFAVERSION; /**< \brief (SCIF Offset: 0x3E4) Oscillator 0 Version Register */\r
+ RoReg SCIF_DFLLIFBVERSION; /**< \brief (SCIF Offset: 0x3E8) DFLL Version Register */\r
+ RoReg SCIF_RCOSCIFAVERSION; /**< \brief (SCIF Offset: 0x3EC) System RC Oscillator Version Register */\r
+ RoReg SCIF_FLOVERSION; /**< \brief (SCIF Offset: 0x3F0) Frequency Locked Oscillator Version Register */\r
+ RoReg SCIF_RC80MVERSION; /**< \brief (SCIF Offset: 0x3F4) 80MHz RC Oscillator Version Register */\r
+ RoReg SCIF_GCLKIFVERSION; /**< \brief (SCIF Offset: 0x3F8) Generic Clock Version Register */\r
+ RoReg SCIF_VERSION; /**< \brief (SCIF Offset: 0x3FC) SCIF Version Register */\r
+} Scif;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- SCIF_IER : (SCIF Offset: 0x000) Interrupt Enable Register -------- */\r
+#define SCIF_IER_OSC0RDY (0x1u << 0) /**< \brief (SCIF_IER) */\r
+#define SCIF_IER_DFLL0LOCKC (0x1u << 1) /**< \brief (SCIF_IER) */\r
+#define SCIF_IER_DFLL0LOCKF (0x1u << 2) /**< \brief (SCIF_IER) */\r
+#define SCIF_IER_DFLL0RDY (0x1u << 3) /**< \brief (SCIF_IER) */\r
+#define SCIF_IER_DFLL0RCS (0x1u << 4) /**< \brief (SCIF_IER) */\r
+#define SCIF_IER_DFLL0OOB (0x1u << 5) /**< \brief (SCIF_IER) */\r
+#define SCIF_IER_PLL0LOCK (0x1u << 6) /**< \brief (SCIF_IER) */\r
+#define SCIF_IER_PLL0LOCKLOST (0x1u << 7) /**< \brief (SCIF_IER) */\r
+#define SCIF_IER_RCFASTLOCK (0x1u << 13) /**< \brief (SCIF_IER) */\r
+#define SCIF_IER_RCFASTLOCKLOST (0x1u << 14) /**< \brief (SCIF_IER) */\r
+#define SCIF_IER_AE (0x1u << 31) /**< \brief (SCIF_IER) */\r
+/* -------- SCIF_IDR : (SCIF Offset: 0x004) Interrupt Disable Register -------- */\r
+#define SCIF_IDR_OSC0RDY (0x1u << 0) /**< \brief (SCIF_IDR) */\r
+#define SCIF_IDR_DFLL0LOCKC (0x1u << 1) /**< \brief (SCIF_IDR) */\r
+#define SCIF_IDR_DFLL0LOCKF (0x1u << 2) /**< \brief (SCIF_IDR) */\r
+#define SCIF_IDR_DFLL0RDY (0x1u << 3) /**< \brief (SCIF_IDR) */\r
+#define SCIF_IDR_DFLL0RCS (0x1u << 4) /**< \brief (SCIF_IDR) */\r
+#define SCIF_IDR_DFLL0OOB (0x1u << 5) /**< \brief (SCIF_IDR) */\r
+#define SCIF_IDR_PLL0LOCK (0x1u << 6) /**< \brief (SCIF_IDR) */\r
+#define SCIF_IDR_PLL0LOCKLOST (0x1u << 7) /**< \brief (SCIF_IDR) */\r
+#define SCIF_IDR_RCFASTLOCK (0x1u << 13) /**< \brief (SCIF_IDR) */\r
+#define SCIF_IDR_RCFASTLOCKLOST (0x1u << 14) /**< \brief (SCIF_IDR) */\r
+#define SCIF_IDR_AE (0x1u << 31) /**< \brief (SCIF_IDR) */\r
+/* -------- SCIF_IMR : (SCIF Offset: 0x008) Interrupt Mask Register -------- */\r
+#define SCIF_IMR_OSC0RDY (0x1u << 0) /**< \brief (SCIF_IMR) */\r
+#define SCIF_IMR_DFLL0LOCKC (0x1u << 1) /**< \brief (SCIF_IMR) */\r
+#define SCIF_IMR_DFLL0LOCKF (0x1u << 2) /**< \brief (SCIF_IMR) */\r
+#define SCIF_IMR_DFLL0RDY (0x1u << 3) /**< \brief (SCIF_IMR) */\r
+#define SCIF_IMR_DFLL0RCS (0x1u << 4) /**< \brief (SCIF_IMR) */\r
+#define SCIF_IMR_DFLL0OOB (0x1u << 5) /**< \brief (SCIF_IMR) */\r
+#define SCIF_IMR_PLL0LOCK (0x1u << 6) /**< \brief (SCIF_IMR) */\r
+#define SCIF_IMR_PLL0LOCKLOST (0x1u << 7) /**< \brief (SCIF_IMR) */\r
+#define SCIF_IMR_RCFASTLOCK (0x1u << 13) /**< \brief (SCIF_IMR) */\r
+#define SCIF_IMR_RCFASTLOCKLOST (0x1u << 14) /**< \brief (SCIF_IMR) */\r
+#define SCIF_IMR_AE (0x1u << 31) /**< \brief (SCIF_IMR) */\r
+/* -------- SCIF_ISR : (SCIF Offset: 0x00C) Interrupt Status Register -------- */\r
+#define SCIF_ISR_OSC0RDY (0x1u << 0) /**< \brief (SCIF_ISR) */\r
+#define SCIF_ISR_DFLL0LOCKC (0x1u << 1) /**< \brief (SCIF_ISR) */\r
+#define SCIF_ISR_DFLL0LOCKF (0x1u << 2) /**< \brief (SCIF_ISR) */\r
+#define SCIF_ISR_DFLL0RDY (0x1u << 3) /**< \brief (SCIF_ISR) */\r
+#define SCIF_ISR_DFLL0RCS (0x1u << 4) /**< \brief (SCIF_ISR) */\r
+#define SCIF_ISR_DFLL0OOB (0x1u << 5) /**< \brief (SCIF_ISR) */\r
+#define SCIF_ISR_PLL0LOCK (0x1u << 6) /**< \brief (SCIF_ISR) */\r
+#define SCIF_ISR_PLL0LOCKLOST (0x1u << 7) /**< \brief (SCIF_ISR) */\r
+#define SCIF_ISR_RCFASTLOCK (0x1u << 13) /**< \brief (SCIF_ISR) */\r
+#define SCIF_ISR_RCFASTLOCKLOST (0x1u << 14) /**< \brief (SCIF_ISR) */\r
+#define SCIF_ISR_AE (0x1u << 31) /**< \brief (SCIF_ISR) */\r
+/* -------- SCIF_ICR : (SCIF Offset: 0x010) Interrupt Clear Register -------- */\r
+#define SCIF_ICR_OSC0RDY (0x1u << 0) /**< \brief (SCIF_ICR) */\r
+#define SCIF_ICR_DFLL0LOCKC (0x1u << 1) /**< \brief (SCIF_ICR) */\r
+#define SCIF_ICR_DFLL0LOCKF (0x1u << 2) /**< \brief (SCIF_ICR) */\r
+#define SCIF_ICR_DFLL0RDY (0x1u << 3) /**< \brief (SCIF_ICR) */\r
+#define SCIF_ICR_DFLL0RCS (0x1u << 4) /**< \brief (SCIF_ICR) */\r
+#define SCIF_ICR_DFLL0OOB (0x1u << 5) /**< \brief (SCIF_ICR) */\r
+#define SCIF_ICR_PLL0LOCK (0x1u << 6) /**< \brief (SCIF_ICR) */\r
+#define SCIF_ICR_PLL0LOCKLOST (0x1u << 7) /**< \brief (SCIF_ICR) */\r
+#define SCIF_ICR_RCFASTLOCK (0x1u << 13) /**< \brief (SCIF_ICR) */\r
+#define SCIF_ICR_RCFASTLOCKLOST (0x1u << 14) /**< \brief (SCIF_ICR) */\r
+#define SCIF_ICR_AE (0x1u << 31) /**< \brief (SCIF_ICR) */\r
+/* -------- SCIF_PCLKSR : (SCIF Offset: 0x014) Power and Clocks Status Register -------- */\r
+#define SCIF_PCLKSR_OSC0RDY (0x1u << 0) /**< \brief (SCIF_PCLKSR) OSC0 Ready */\r
+#define SCIF_PCLKSR_DFLL0LOCKC (0x1u << 1) /**< \brief (SCIF_PCLKSR) DFLL0 Locked on Coarse Value */\r
+#define SCIF_PCLKSR_DFLL0LOCKF (0x1u << 2) /**< \brief (SCIF_PCLKSR) DFLL0 Locked on Fine Value */\r
+#define SCIF_PCLKSR_DFLL0RDY (0x1u << 3) /**< \brief (SCIF_PCLKSR) DFLL0 Synchronization Ready */\r
+#define SCIF_PCLKSR_DFLL0RCS (0x1u << 4) /**< \brief (SCIF_PCLKSR) DFLL0 Reference Clock Stopped */\r
+#define SCIF_PCLKSR_DFLL0OOB (0x1u << 5) /**< \brief (SCIF_PCLKSR) DFLL0 Track Out Of Bounds */\r
+#define SCIF_PCLKSR_PLL0LOCK (0x1u << 6) /**< \brief (SCIF_PCLKSR) PLL0 Locked on Accurate value */\r
+#define SCIF_PCLKSR_PLL0LOCKLOST (0x1u << 7) /**< \brief (SCIF_PCLKSR) PLL0 lock lost value */\r
+#define SCIF_PCLKSR_RCFASTLOCK (0x1u << 13) /**< \brief (SCIF_PCLKSR) RCFAST Locked on Accurate value */\r
+#define SCIF_PCLKSR_RCFASTLOCKLOST (0x1u << 14) /**< \brief (SCIF_PCLKSR) RCFAST lock lost value */\r
+/* -------- SCIF_UNLOCK : (SCIF Offset: 0x018) Unlock Register -------- */\r
+#define SCIF_UNLOCK_ADDR_Pos 0\r
+#define SCIF_UNLOCK_ADDR_Msk (0x3FFu << SCIF_UNLOCK_ADDR_Pos) /**< \brief (SCIF_UNLOCK) Unlock Address */\r
+#define SCIF_UNLOCK_ADDR(value) ((SCIF_UNLOCK_ADDR_Msk & ((value) << SCIF_UNLOCK_ADDR_Pos)))\r
+#define SCIF_UNLOCK_KEY_Pos 24\r
+#define SCIF_UNLOCK_KEY_Msk (0xFFu << SCIF_UNLOCK_KEY_Pos) /**< \brief (SCIF_UNLOCK) Unlock Key */\r
+#define SCIF_UNLOCK_KEY(value) ((SCIF_UNLOCK_KEY_Msk & ((value) << SCIF_UNLOCK_KEY_Pos)))\r
+/* -------- SCIF_OSCCTRL0 : (SCIF Offset: 0x020) Oscillator Control Register -------- */\r
+#define SCIF_OSCCTRL0_MODE (0x1u << 0) /**< \brief (SCIF_OSCCTRL0) Oscillator Mode */\r
+#define SCIF_OSCCTRL0_GAIN_Pos 1\r
+#define SCIF_OSCCTRL0_GAIN_Msk (0x3u << SCIF_OSCCTRL0_GAIN_Pos) /**< \brief (SCIF_OSCCTRL0) Gain */\r
+#define SCIF_OSCCTRL0_GAIN(value) ((SCIF_OSCCTRL0_GAIN_Msk & ((value) << SCIF_OSCCTRL0_GAIN_Pos)))\r
+#define SCIF_OSCCTRL0_AGC (0x1u << 3) /**< \brief (SCIF_OSCCTRL0) Automatic Gain Control */\r
+#define SCIF_OSCCTRL0_STARTUP_Pos 8\r
+#define SCIF_OSCCTRL0_STARTUP_Msk (0xFu << SCIF_OSCCTRL0_STARTUP_Pos) /**< \brief (SCIF_OSCCTRL0) Oscillator Start-up Time */\r
+#define SCIF_OSCCTRL0_STARTUP(value) ((SCIF_OSCCTRL0_STARTUP_Msk & ((value) << SCIF_OSCCTRL0_STARTUP_Pos)))\r
+#define SCIF_OSCCTRL0_OSCEN (0x1u << 16) /**< \brief (SCIF_OSCCTRL0) Oscillator Enable */\r
+/* -------- SCIF_PLL : (SCIF Offset: 0x024) Pll PLL0 Control Register -------- */\r
+#define SCIF_PLL_PLLEN (0x1u << 0) /**< \brief (SCIF_PLL) PLL Enable */\r
+#define SCIF_PLL_PLLOSC_Pos 1\r
+#define SCIF_PLL_PLLOSC_Msk (0x3u << SCIF_PLL_PLLOSC_Pos) /**< \brief (SCIF_PLL) PLL Oscillator Select */\r
+#define SCIF_PLL_PLLOSC(value) ((SCIF_PLL_PLLOSC_Msk & ((value) << SCIF_PLL_PLLOSC_Pos)))\r
+#define SCIF_PLL_PLLOPT_Pos 3\r
+#define SCIF_PLL_PLLOPT_Msk (0x7u << SCIF_PLL_PLLOPT_Pos) /**< \brief (SCIF_PLL) PLL Option */\r
+#define SCIF_PLL_PLLOPT(value) ((SCIF_PLL_PLLOPT_Msk & ((value) << SCIF_PLL_PLLOPT_Pos)))\r
+#define SCIF_PLL_PLLDIV_Pos 8\r
+#define SCIF_PLL_PLLDIV_Msk (0xFu << SCIF_PLL_PLLDIV_Pos) /**< \brief (SCIF_PLL) PLL Division Factor */\r
+#define SCIF_PLL_PLLDIV(value) ((SCIF_PLL_PLLDIV_Msk & ((value) << SCIF_PLL_PLLDIV_Pos)))\r
+#define SCIF_PLL_PLLMUL_Pos 16\r
+#define SCIF_PLL_PLLMUL_Msk (0xFu << SCIF_PLL_PLLMUL_Pos) /**< \brief (SCIF_PLL) PLL Multiply Factor */\r
+#define SCIF_PLL_PLLMUL(value) ((SCIF_PLL_PLLMUL_Msk & ((value) << SCIF_PLL_PLLMUL_Pos)))\r
+#define SCIF_PLL_PLLCOUNT_Pos 24\r
+#define SCIF_PLL_PLLCOUNT_Msk (0x3Fu << SCIF_PLL_PLLCOUNT_Pos) /**< \brief (SCIF_PLL) PLL Count */\r
+#define SCIF_PLL_PLLCOUNT(value) ((SCIF_PLL_PLLCOUNT_Msk & ((value) << SCIF_PLL_PLLCOUNT_Pos)))\r
+/* -------- SCIF_DFLL0CONF : (SCIF Offset: 0x028) DFLL0 Config Register -------- */\r
+#define SCIF_DFLL0CONF_EN (0x1u << 0) /**< \brief (SCIF_DFLL0CONF) Enable */\r
+#define SCIF_DFLL0CONF_MODE (0x1u << 1) /**< \brief (SCIF_DFLL0CONF) Mode Selection */\r
+#define SCIF_DFLL0CONF_STABLE (0x1u << 2) /**< \brief (SCIF_DFLL0CONF) Stable DFLL Frequency */\r
+#define SCIF_DFLL0CONF_LLAW (0x1u << 3) /**< \brief (SCIF_DFLL0CONF) Lose Lock After Wake */\r
+#define SCIF_DFLL0CONF_CCDIS (0x1u << 5) /**< \brief (SCIF_DFLL0CONF) Chill Cycle Disable */\r
+#define SCIF_DFLL0CONF_QLDIS (0x1u << 6) /**< \brief (SCIF_DFLL0CONF) Quick Lock Disable */\r
+#define SCIF_DFLL0CONF_RANGE_Pos 16\r
+#define SCIF_DFLL0CONF_RANGE_Msk (0x3u << SCIF_DFLL0CONF_RANGE_Pos) /**< \brief (SCIF_DFLL0CONF) Range Value */\r
+#define SCIF_DFLL0CONF_RANGE(value) ((SCIF_DFLL0CONF_RANGE_Msk & ((value) << SCIF_DFLL0CONF_RANGE_Pos)))\r
+#define SCIF_DFLL0CONF_FCD (0x1u << 23) /**< \brief (SCIF_DFLL0CONF) Fuse Calibration Done */\r
+#define SCIF_DFLL0CONF_CALIB_Pos 24\r
+#define SCIF_DFLL0CONF_CALIB_Msk (0xFu << SCIF_DFLL0CONF_CALIB_Pos) /**< \brief (SCIF_DFLL0CONF) Calibration Value */\r
+#define SCIF_DFLL0CONF_CALIB(value) ((SCIF_DFLL0CONF_CALIB_Msk & ((value) << SCIF_DFLL0CONF_CALIB_Pos)))\r
+/* -------- SCIF_DFLL0VAL : (SCIF Offset: 0x02C) DFLL Value Register -------- */\r
+#define SCIF_DFLL0VAL_FINE_Pos 0\r
+#define SCIF_DFLL0VAL_FINE_Msk (0xFFu << SCIF_DFLL0VAL_FINE_Pos) /**< \brief (SCIF_DFLL0VAL) Fine Value */\r
+#define SCIF_DFLL0VAL_FINE(value) ((SCIF_DFLL0VAL_FINE_Msk & ((value) << SCIF_DFLL0VAL_FINE_Pos)))\r
+#define SCIF_DFLL0VAL_COARSE_Pos 16\r
+#define SCIF_DFLL0VAL_COARSE_Msk (0x1Fu << SCIF_DFLL0VAL_COARSE_Pos) /**< \brief (SCIF_DFLL0VAL) Coarse Value */\r
+#define SCIF_DFLL0VAL_COARSE(value) ((SCIF_DFLL0VAL_COARSE_Msk & ((value) << SCIF_DFLL0VAL_COARSE_Pos)))\r
+/* -------- SCIF_DFLL0MUL : (SCIF Offset: 0x030) DFLL0 Multiplier Register -------- */\r
+#define SCIF_DFLL0MUL_MUL_Pos 0\r
+#define SCIF_DFLL0MUL_MUL_Msk (0xFFFFu << SCIF_DFLL0MUL_MUL_Pos) /**< \brief (SCIF_DFLL0MUL) DFLL Multiply Factor */\r
+#define SCIF_DFLL0MUL_MUL(value) ((SCIF_DFLL0MUL_MUL_Msk & ((value) << SCIF_DFLL0MUL_MUL_Pos)))\r
+/* -------- SCIF_DFLL0STEP : (SCIF Offset: 0x034) DFLL0 Step Register -------- */\r
+#define SCIF_DFLL0STEP_FSTEP_Pos 0\r
+#define SCIF_DFLL0STEP_FSTEP_Msk (0xFFu << SCIF_DFLL0STEP_FSTEP_Pos) /**< \brief (SCIF_DFLL0STEP) Fine Maximum Step */\r
+#define SCIF_DFLL0STEP_FSTEP(value) ((SCIF_DFLL0STEP_FSTEP_Msk & ((value) << SCIF_DFLL0STEP_FSTEP_Pos)))\r
+#define SCIF_DFLL0STEP_CSTEP_Pos 16\r
+#define SCIF_DFLL0STEP_CSTEP_Msk (0x1Fu << SCIF_DFLL0STEP_CSTEP_Pos) /**< \brief (SCIF_DFLL0STEP) Coarse Maximum Step */\r
+#define SCIF_DFLL0STEP_CSTEP(value) ((SCIF_DFLL0STEP_CSTEP_Msk & ((value) << SCIF_DFLL0STEP_CSTEP_Pos)))\r
+/* -------- SCIF_DFLL0SSG : (SCIF Offset: 0x038) DFLL0 Spread Spectrum Generator Control Register -------- */\r
+#define SCIF_DFLL0SSG_EN (0x1u << 0) /**< \brief (SCIF_DFLL0SSG) Enable */\r
+#define SCIF_DFLL0SSG_PRBS (0x1u << 1) /**< \brief (SCIF_DFLL0SSG) Pseudo Random Bit Sequence */\r
+#define SCIF_DFLL0SSG_AMPLITUDE_Pos 8\r
+#define SCIF_DFLL0SSG_AMPLITUDE_Msk (0x1Fu << SCIF_DFLL0SSG_AMPLITUDE_Pos) /**< \brief (SCIF_DFLL0SSG) SSG Amplitude */\r
+#define SCIF_DFLL0SSG_AMPLITUDE(value) ((SCIF_DFLL0SSG_AMPLITUDE_Msk & ((value) << SCIF_DFLL0SSG_AMPLITUDE_Pos)))\r
+#define SCIF_DFLL0SSG_STEPSIZE_Pos 16\r
+#define SCIF_DFLL0SSG_STEPSIZE_Msk (0x1Fu << SCIF_DFLL0SSG_STEPSIZE_Pos) /**< \brief (SCIF_DFLL0SSG) SSG Step Size */\r
+#define SCIF_DFLL0SSG_STEPSIZE(value) ((SCIF_DFLL0SSG_STEPSIZE_Msk & ((value) << SCIF_DFLL0SSG_STEPSIZE_Pos)))\r
+/* -------- SCIF_DFLL0RATIO : (SCIF Offset: 0x03C) DFLL0 Ratio Registe -------- */\r
+#define SCIF_DFLL0RATIO_RATIODIFF_Pos 0\r
+#define SCIF_DFLL0RATIO_RATIODIFF_Msk (0xFFFFu << SCIF_DFLL0RATIO_RATIODIFF_Pos) /**< \brief (SCIF_DFLL0RATIO) Multiplication Ratio Difference */\r
+#define SCIF_DFLL0RATIO_RATIODIFF(value) ((SCIF_DFLL0RATIO_RATIODIFF_Msk & ((value) << SCIF_DFLL0RATIO_RATIODIFF_Pos)))\r
+/* -------- SCIF_DFLL0SYNC : (SCIF Offset: 0x040) DFLL0 Synchronization Register -------- */\r
+#define SCIF_DFLL0SYNC_SYNC (0x1u << 0) /**< \brief (SCIF_DFLL0SYNC) Synchronization */\r
+/* -------- SCIF_RCCR : (SCIF Offset: 0x044) System RC Oscillator Calibration Register -------- */\r
+#define SCIF_RCCR_CALIB_Pos 0\r
+#define SCIF_RCCR_CALIB_Msk (0x3FFu << SCIF_RCCR_CALIB_Pos) /**< \brief (SCIF_RCCR) Calibration Value */\r
+#define SCIF_RCCR_CALIB(value) ((SCIF_RCCR_CALIB_Msk & ((value) << SCIF_RCCR_CALIB_Pos)))\r
+#define SCIF_RCCR_FCD (0x1u << 16) /**< \brief (SCIF_RCCR) Flash Calibration Done */\r
+/* -------- SCIF_RCFASTCFG : (SCIF Offset: 0x048) 4/8/12 MHz RC Oscillator Configuration\r
+Register -------- */\r
+#define SCIF_RCFASTCFG_EN (0x1u << 0) /**< \brief (SCIF_RCFASTCFG) Oscillator Enable */\r
+#define SCIF_RCFASTCFG_TUNEEN (0x1u << 1) /**< \brief (SCIF_RCFASTCFG) Tuner Enable */\r
+#define SCIF_RCFASTCFG_JITMODE (0x1u << 2) /**< \brief (SCIF_RCFASTCFG) Jitter Mode */\r
+#define SCIF_RCFASTCFG_NBPERIODS_Pos 4\r
+#define SCIF_RCFASTCFG_NBPERIODS_Msk (0x7u << SCIF_RCFASTCFG_NBPERIODS_Pos) /**< \brief (SCIF_RCFASTCFG) Number of 32kHz Periods */\r
+#define SCIF_RCFASTCFG_NBPERIODS(value) ((SCIF_RCFASTCFG_NBPERIODS_Msk & ((value) << SCIF_RCFASTCFG_NBPERIODS_Pos)))\r
+#define SCIF_RCFASTCFG_FCD (0x1u << 7) /**< \brief (SCIF_RCFASTCFG) RCFAST Fuse Calibration Done */\r
+#define SCIF_RCFASTCFG_FRANGE_Pos 8\r
+#define SCIF_RCFASTCFG_FRANGE_Msk (0x3u << SCIF_RCFASTCFG_FRANGE_Pos) /**< \brief (SCIF_RCFASTCFG) Frequency Range */\r
+#define SCIF_RCFASTCFG_FRANGE(value) ((SCIF_RCFASTCFG_FRANGE_Msk & ((value) << SCIF_RCFASTCFG_FRANGE_Pos)))\r
+#define SCIF_RCFASTCFG_LOCKMARGIN_Pos 12\r
+#define SCIF_RCFASTCFG_LOCKMARGIN_Msk (0xFu << SCIF_RCFASTCFG_LOCKMARGIN_Pos) /**< \brief (SCIF_RCFASTCFG) Accepted Count Error for Lock */\r
+#define SCIF_RCFASTCFG_LOCKMARGIN(value) ((SCIF_RCFASTCFG_LOCKMARGIN_Msk & ((value) << SCIF_RCFASTCFG_LOCKMARGIN_Pos)))\r
+#define SCIF_RCFASTCFG_CALIB_Pos 16\r
+#define SCIF_RCFASTCFG_CALIB_Msk (0x7Fu << SCIF_RCFASTCFG_CALIB_Pos) /**< \brief (SCIF_RCFASTCFG) Oscillator Calibration Value */\r
+#define SCIF_RCFASTCFG_CALIB(value) ((SCIF_RCFASTCFG_CALIB_Msk & ((value) << SCIF_RCFASTCFG_CALIB_Pos)))\r
+/* -------- SCIF_RCFASTSR : (SCIF Offset: 0x04C) 4/8/12 MHz RC Oscillator Status Register -------- */\r
+#define SCIF_RCFASTSR_CURTRIM_Pos 0\r
+#define SCIF_RCFASTSR_CURTRIM_Msk (0x7Fu << SCIF_RCFASTSR_CURTRIM_Pos) /**< \brief (SCIF_RCFASTSR) Current Trim Value */\r
+#define SCIF_RCFASTSR_CURTRIM(value) ((SCIF_RCFASTSR_CURTRIM_Msk & ((value) << SCIF_RCFASTSR_CURTRIM_Pos)))\r
+#define SCIF_RCFASTSR_CNTERR_Pos 16\r
+#define SCIF_RCFASTSR_CNTERR_Msk (0x1Fu << SCIF_RCFASTSR_CNTERR_Pos) /**< \brief (SCIF_RCFASTSR) Current Count Error */\r
+#define SCIF_RCFASTSR_CNTERR(value) ((SCIF_RCFASTSR_CNTERR_Msk & ((value) << SCIF_RCFASTSR_CNTERR_Pos)))\r
+#define SCIF_RCFASTSR_SIGN (0x1u << 21) /**< \brief (SCIF_RCFASTSR) Sign of Current Count Error */\r
+#define SCIF_RCFASTSR_LOCK (0x1u << 24) /**< \brief (SCIF_RCFASTSR) Lock */\r
+#define SCIF_RCFASTSR_LOCKLOST (0x1u << 25) /**< \brief (SCIF_RCFASTSR) Lock Lost */\r
+#define SCIF_RCFASTSR_UPDATED (0x1u << 31) /**< \brief (SCIF_RCFASTSR) Current Trim Value Updated */\r
+/* -------- SCIF_RC80MCR : (SCIF Offset: 0x050) 80 MHz RC Oscillator Register -------- */\r
+#define SCIF_RC80MCR_EN (0x1u << 0) /**< \brief (SCIF_RC80MCR) Enable */\r
+#define SCIF_RC80MCR_FCD (0x1u << 7) /**< \brief (SCIF_RC80MCR) Flash Calibration Done */\r
+#define SCIF_RC80MCR_CALIB_Pos 16\r
+#define SCIF_RC80MCR_CALIB_Msk (0x3u << SCIF_RC80MCR_CALIB_Pos) /**< \brief (SCIF_RC80MCR) Calibration Value */\r
+#define SCIF_RC80MCR_CALIB(value) ((SCIF_RC80MCR_CALIB_Msk & ((value) << SCIF_RC80MCR_CALIB_Pos)))\r
+/* -------- SCIF_HRPCR : (SCIF Offset: 0x064) High Resolution Prescaler Control Register -------- */\r
+#define SCIF_HRPCR_HRPEN (0x1u << 0) /**< \brief (SCIF_HRPCR) High Resolution Prescaler Enable */\r
+#define SCIF_HRPCR_CKSEL_Pos 1\r
+#define SCIF_HRPCR_CKSEL_Msk (0x7u << SCIF_HRPCR_CKSEL_Pos) /**< \brief (SCIF_HRPCR) Clock Input Selection */\r
+#define SCIF_HRPCR_CKSEL(value) ((SCIF_HRPCR_CKSEL_Msk & ((value) << SCIF_HRPCR_CKSEL_Pos)))\r
+#define SCIF_HRPCR_HRCOUNT_Pos 8\r
+#define SCIF_HRPCR_HRCOUNT_Msk (0xFFFFFFu << SCIF_HRPCR_HRCOUNT_Pos) /**< \brief (SCIF_HRPCR) High Resolution Counter */\r
+#define SCIF_HRPCR_HRCOUNT(value) ((SCIF_HRPCR_HRCOUNT_Msk & ((value) << SCIF_HRPCR_HRCOUNT_Pos)))\r
+/* -------- SCIF_FPCR : (SCIF Offset: 0x068) Fractional Prescaler Control Register -------- */\r
+#define SCIF_FPCR_FPEN (0x1u << 0) /**< \brief (SCIF_FPCR) High Resolution Prescaler Enable */\r
+#define SCIF_FPCR_CKSEL_Pos 1\r
+#define SCIF_FPCR_CKSEL_Msk (0x7u << SCIF_FPCR_CKSEL_Pos) /**< \brief (SCIF_FPCR) Clock Input Selection */\r
+#define SCIF_FPCR_CKSEL(value) ((SCIF_FPCR_CKSEL_Msk & ((value) << SCIF_FPCR_CKSEL_Pos)))\r
+/* -------- SCIF_FPMUL : (SCIF Offset: 0x06C) Fractional Prescaler Multiplier Register -------- */\r
+#define SCIF_FPMUL_FPMUL_Pos 0\r
+#define SCIF_FPMUL_FPMUL_Msk (0xFFFFu << SCIF_FPMUL_FPMUL_Pos) /**< \brief (SCIF_FPMUL) Fractional Prescaler Multiplication Factor */\r
+#define SCIF_FPMUL_FPMUL(value) ((SCIF_FPMUL_FPMUL_Msk & ((value) << SCIF_FPMUL_FPMUL_Pos)))\r
+/* -------- SCIF_FPDIV : (SCIF Offset: 0x070) Fractional Prescaler DIVIDER Register -------- */\r
+#define SCIF_FPDIV_FPDIV_Pos 0\r
+#define SCIF_FPDIV_FPDIV_Msk (0xFFFFu << SCIF_FPDIV_FPDIV_Pos) /**< \brief (SCIF_FPDIV) Fractional Prescaler Division Factor */\r
+#define SCIF_FPDIV_FPDIV(value) ((SCIF_FPDIV_FPDIV_Msk & ((value) << SCIF_FPDIV_FPDIV_Pos)))\r
+/* -------- SCIF_GCCTRL : (SCIF Offset: 0x074) Gcctrl Generic Clock Control -------- */\r
+#define SCIF_GCCTRL_CEN (0x1u << 0) /**< \brief (SCIF_GCCTRL) Clock Enable */\r
+#define SCIF_GCCTRL_DIVEN (0x1u << 1) /**< \brief (SCIF_GCCTRL) Divide Enable */\r
+#define SCIF_GCCTRL_OSCSEL_Pos 8\r
+#define SCIF_GCCTRL_OSCSEL_Msk (0x1Fu << SCIF_GCCTRL_OSCSEL_Pos) /**< \brief (SCIF_GCCTRL) Clock Select */\r
+#define SCIF_GCCTRL_OSCSEL(value) ((SCIF_GCCTRL_OSCSEL_Msk & ((value) << SCIF_GCCTRL_OSCSEL_Pos)))\r
+#define SCIF_GCCTRL_DIV_Pos 16\r
+#define SCIF_GCCTRL_DIV_Msk (0xFFFFu << SCIF_GCCTRL_DIV_Pos) /**< \brief (SCIF_GCCTRL) Division Factor */\r
+#define SCIF_GCCTRL_DIV(value) ((SCIF_GCCTRL_DIV_Msk & ((value) << SCIF_GCCTRL_DIV_Pos)))\r
+/* -------- SCIF_RCFASTVERSION : (SCIF Offset: 0x3D8) 4/8/12 MHz RC Oscillator Version Register -------- */\r
+#define SCIF_RCFASTVERSION_VERSION_Pos 0\r
+#define SCIF_RCFASTVERSION_VERSION_Msk (0xFFFu << SCIF_RCFASTVERSION_VERSION_Pos) /**< \brief (SCIF_RCFASTVERSION) Version number */\r
+#define SCIF_RCFASTVERSION_VERSION(value) ((SCIF_RCFASTVERSION_VERSION_Msk & ((value) << SCIF_RCFASTVERSION_VERSION_Pos)))\r
+#define SCIF_RCFASTVERSION_VARIANT_Pos 16\r
+#define SCIF_RCFASTVERSION_VARIANT_Msk (0xFu << SCIF_RCFASTVERSION_VARIANT_Pos) /**< \brief (SCIF_RCFASTVERSION) Variant number */\r
+#define SCIF_RCFASTVERSION_VARIANT(value) ((SCIF_RCFASTVERSION_VARIANT_Msk & ((value) << SCIF_RCFASTVERSION_VARIANT_Pos)))\r
+/* -------- SCIF_GCLKPRESCVERSION : (SCIF Offset: 0x3DC) Generic Clock Prescaler Version Register -------- */\r
+#define SCIF_GCLKPRESCVERSION_VERSION_Pos 0\r
+#define SCIF_GCLKPRESCVERSION_VERSION_Msk (0xFFFu << SCIF_GCLKPRESCVERSION_VERSION_Pos) /**< \brief (SCIF_GCLKPRESCVERSION) Version number */\r
+#define SCIF_GCLKPRESCVERSION_VERSION(value) ((SCIF_GCLKPRESCVERSION_VERSION_Msk & ((value) << SCIF_GCLKPRESCVERSION_VERSION_Pos)))\r
+#define SCIF_GCLKPRESCVERSION_VARIANT_Pos 16\r
+#define SCIF_GCLKPRESCVERSION_VARIANT_Msk (0xFu << SCIF_GCLKPRESCVERSION_VARIANT_Pos) /**< \brief (SCIF_GCLKPRESCVERSION) Variant number */\r
+#define SCIF_GCLKPRESCVERSION_VARIANT(value) ((SCIF_GCLKPRESCVERSION_VARIANT_Msk & ((value) << SCIF_GCLKPRESCVERSION_VARIANT_Pos)))\r
+/* -------- SCIF_PLLIFAVERSION : (SCIF Offset: 0x3E0) PLL Version Register -------- */\r
+#define SCIF_PLLIFAVERSION_VERSION_Pos 0\r
+#define SCIF_PLLIFAVERSION_VERSION_Msk (0xFFFu << SCIF_PLLIFAVERSION_VERSION_Pos) /**< \brief (SCIF_PLLIFAVERSION) Version number */\r
+#define SCIF_PLLIFAVERSION_VERSION(value) ((SCIF_PLLIFAVERSION_VERSION_Msk & ((value) << SCIF_PLLIFAVERSION_VERSION_Pos)))\r
+#define SCIF_PLLIFAVERSION_VARIANT_Pos 16\r
+#define SCIF_PLLIFAVERSION_VARIANT_Msk (0xFu << SCIF_PLLIFAVERSION_VARIANT_Pos) /**< \brief (SCIF_PLLIFAVERSION) Variant nubmer */\r
+#define SCIF_PLLIFAVERSION_VARIANT(value) ((SCIF_PLLIFAVERSION_VARIANT_Msk & ((value) << SCIF_PLLIFAVERSION_VARIANT_Pos)))\r
+/* -------- SCIF_OSCIFAVERSION : (SCIF Offset: 0x3E4) Oscillator 0 Version Register -------- */\r
+#define SCIF_OSCIFAVERSION_VERSION_Pos 0\r
+#define SCIF_OSCIFAVERSION_VERSION_Msk (0xFFFu << SCIF_OSCIFAVERSION_VERSION_Pos) /**< \brief (SCIF_OSCIFAVERSION) Version number */\r
+#define SCIF_OSCIFAVERSION_VERSION(value) ((SCIF_OSCIFAVERSION_VERSION_Msk & ((value) << SCIF_OSCIFAVERSION_VERSION_Pos)))\r
+#define SCIF_OSCIFAVERSION_VARIANT_Pos 16\r
+#define SCIF_OSCIFAVERSION_VARIANT_Msk (0xFu << SCIF_OSCIFAVERSION_VARIANT_Pos) /**< \brief (SCIF_OSCIFAVERSION) Variant nubmer */\r
+#define SCIF_OSCIFAVERSION_VARIANT(value) ((SCIF_OSCIFAVERSION_VARIANT_Msk & ((value) << SCIF_OSCIFAVERSION_VARIANT_Pos)))\r
+/* -------- SCIF_DFLLIFBVERSION : (SCIF Offset: 0x3E8) DFLL Version Register -------- */\r
+#define SCIF_DFLLIFBVERSION_VERSION_Pos 0\r
+#define SCIF_DFLLIFBVERSION_VERSION_Msk (0xFFFu << SCIF_DFLLIFBVERSION_VERSION_Pos) /**< \brief (SCIF_DFLLIFBVERSION) Version number */\r
+#define SCIF_DFLLIFBVERSION_VERSION(value) ((SCIF_DFLLIFBVERSION_VERSION_Msk & ((value) << SCIF_DFLLIFBVERSION_VERSION_Pos)))\r
+#define SCIF_DFLLIFBVERSION_VARIANT_Pos 16\r
+#define SCIF_DFLLIFBVERSION_VARIANT_Msk (0xFu << SCIF_DFLLIFBVERSION_VARIANT_Pos) /**< \brief (SCIF_DFLLIFBVERSION) Variant number */\r
+#define SCIF_DFLLIFBVERSION_VARIANT(value) ((SCIF_DFLLIFBVERSION_VARIANT_Msk & ((value) << SCIF_DFLLIFBVERSION_VARIANT_Pos)))\r
+/* -------- SCIF_RCOSCIFAVERSION : (SCIF Offset: 0x3EC) System RC Oscillator Version Register -------- */\r
+#define SCIF_RCOSCIFAVERSION_VERSION_Pos 0\r
+#define SCIF_RCOSCIFAVERSION_VERSION_Msk (0xFFFu << SCIF_RCOSCIFAVERSION_VERSION_Pos) /**< \brief (SCIF_RCOSCIFAVERSION) Version number */\r
+#define SCIF_RCOSCIFAVERSION_VERSION(value) ((SCIF_RCOSCIFAVERSION_VERSION_Msk & ((value) << SCIF_RCOSCIFAVERSION_VERSION_Pos)))\r
+#define SCIF_RCOSCIFAVERSION_VARIANT_Pos 16\r
+#define SCIF_RCOSCIFAVERSION_VARIANT_Msk (0xFu << SCIF_RCOSCIFAVERSION_VARIANT_Pos) /**< \brief (SCIF_RCOSCIFAVERSION) Variant number */\r
+#define SCIF_RCOSCIFAVERSION_VARIANT(value) ((SCIF_RCOSCIFAVERSION_VARIANT_Msk & ((value) << SCIF_RCOSCIFAVERSION_VARIANT_Pos)))\r
+/* -------- SCIF_FLOVERSION : (SCIF Offset: 0x3F0) Frequency Locked Oscillator Version Register -------- */\r
+#define SCIF_FLOVERSION_VERSION_Pos 0\r
+#define SCIF_FLOVERSION_VERSION_Msk (0xFFFu << SCIF_FLOVERSION_VERSION_Pos) /**< \brief (SCIF_FLOVERSION) Version number */\r
+#define SCIF_FLOVERSION_VERSION(value) ((SCIF_FLOVERSION_VERSION_Msk & ((value) << SCIF_FLOVERSION_VERSION_Pos)))\r
+#define SCIF_FLOVERSION_VARIANT_Pos 16\r
+#define SCIF_FLOVERSION_VARIANT_Msk (0xFu << SCIF_FLOVERSION_VARIANT_Pos) /**< \brief (SCIF_FLOVERSION) Variant number */\r
+#define SCIF_FLOVERSION_VARIANT(value) ((SCIF_FLOVERSION_VARIANT_Msk & ((value) << SCIF_FLOVERSION_VARIANT_Pos)))\r
+/* -------- SCIF_RC80MVERSION : (SCIF Offset: 0x3F4) 80MHz RC Oscillator Version Register -------- */\r
+#define SCIF_RC80MVERSION_VERSION_Pos 0\r
+#define SCIF_RC80MVERSION_VERSION_Msk (0xFFFu << SCIF_RC80MVERSION_VERSION_Pos) /**< \brief (SCIF_RC80MVERSION) Version number */\r
+#define SCIF_RC80MVERSION_VERSION(value) ((SCIF_RC80MVERSION_VERSION_Msk & ((value) << SCIF_RC80MVERSION_VERSION_Pos)))\r
+#define SCIF_RC80MVERSION_VARIANT_Pos 16\r
+#define SCIF_RC80MVERSION_VARIANT_Msk (0xFu << SCIF_RC80MVERSION_VARIANT_Pos) /**< \brief (SCIF_RC80MVERSION) Variant number */\r
+#define SCIF_RC80MVERSION_VARIANT(value) ((SCIF_RC80MVERSION_VARIANT_Msk & ((value) << SCIF_RC80MVERSION_VARIANT_Pos)))\r
+/* -------- SCIF_GCLKIFVERSION : (SCIF Offset: 0x3F8) Generic Clock Version Register -------- */\r
+#define SCIF_GCLKIFVERSION_VERSION_Pos 0\r
+#define SCIF_GCLKIFVERSION_VERSION_Msk (0xFFFu << SCIF_GCLKIFVERSION_VERSION_Pos) /**< \brief (SCIF_GCLKIFVERSION) Version number */\r
+#define SCIF_GCLKIFVERSION_VERSION(value) ((SCIF_GCLKIFVERSION_VERSION_Msk & ((value) << SCIF_GCLKIFVERSION_VERSION_Pos)))\r
+#define SCIF_GCLKIFVERSION_VARIANT_Pos 16\r
+#define SCIF_GCLKIFVERSION_VARIANT_Msk (0xFu << SCIF_GCLKIFVERSION_VARIANT_Pos) /**< \brief (SCIF_GCLKIFVERSION) Variant number */\r
+#define SCIF_GCLKIFVERSION_VARIANT(value) ((SCIF_GCLKIFVERSION_VARIANT_Msk & ((value) << SCIF_GCLKIFVERSION_VARIANT_Pos)))\r
+/* -------- SCIF_VERSION : (SCIF Offset: 0x3FC) SCIF Version Register -------- */\r
+#define SCIF_VERSION_VERSION_Pos 0\r
+#define SCIF_VERSION_VERSION_Msk (0xFFFu << SCIF_VERSION_VERSION_Pos) /**< \brief (SCIF_VERSION) Version number */\r
+#define SCIF_VERSION_VERSION(value) ((SCIF_VERSION_VERSION_Msk & ((value) << SCIF_VERSION_VERSION_Pos)))\r
+#define SCIF_VERSION_VARIANT_Pos 16\r
+#define SCIF_VERSION_VARIANT_Msk (0xFu << SCIF_VERSION_VARIANT_Pos) /**< \brief (SCIF_VERSION) Variant number */\r
+#define SCIF_VERSION_VARIANT(value) ((SCIF_VERSION_VARIANT_Msk & ((value) << SCIF_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR SMAP */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_SMAP System Manager Access Port */\r
+/*@{*/\r
+\r
+#define REV_SMAP 0x100\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief SMAP hardware registers */\r
+typedef struct {\r
+ WoReg SMAP_CR; /**< \brief (SMAP Offset: 0x00) Control Register */\r
+ RoReg SMAP_SR; /**< \brief (SMAP Offset: 0x04) Status Register */\r
+ WoReg SMAP_SCR; /**< \brief (SMAP Offset: 0x08) Status Clear Register */\r
+ RwReg SMAP_ADDR; /**< \brief (SMAP Offset: 0x0C) Address Register */\r
+ RwReg SMAP_LENGTH; /**< \brief (SMAP Offset: 0x10) Length Register */\r
+ RwReg SMAP_DATA; /**< \brief (SMAP Offset: 0x14) Data Register */\r
+ RoReg Reserved1[4];\r
+ RoReg SMAP_VERSION; /**< \brief (SMAP Offset: 0x28) VERSION register */\r
+ RoReg Reserved2[49];\r
+ RoReg SMAP_CIDR; /**< \brief (SMAP Offset: 0xF0) Chip ID Register */\r
+ RoReg SMAP_EXID; /**< \brief (SMAP Offset: 0xF4) Chip ID Extension Register */\r
+ RoReg Reserved3[1];\r
+ RoReg SMAP_IDR; /**< \brief (SMAP Offset: 0xFC) AP Identification register */\r
+} Smap;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- SMAP_CR : (SMAP Offset: 0x00) Control Register -------- */\r
+#define SMAP_CR_EN (0x1u << 0) /**< \brief (SMAP_CR) Enable */\r
+#define SMAP_CR_DIS (0x1u << 1) /**< \brief (SMAP_CR) Disable */\r
+#define SMAP_CR_CRC (0x1u << 2) /**< \brief (SMAP_CR) User Page Read */\r
+#define SMAP_CR_FSPR (0x1u << 3) /**< \brief (SMAP_CR) Flash Supplementary Page Read */\r
+#define SMAP_CR_CE (0x1u << 4) /**< \brief (SMAP_CR) Chip Erase */\r
+/* -------- SMAP_SR : (SMAP Offset: 0x04) Status Register -------- */\r
+#define SMAP_SR_DONE (0x1u << 0) /**< \brief (SMAP_SR) Operation done */\r
+#define SMAP_SR_HCR (0x1u << 1) /**< \brief (SMAP_SR) Hold Core reset */\r
+#define SMAP_SR_BERR (0x1u << 2) /**< \brief (SMAP_SR) Bus error */\r
+#define SMAP_SR_FAIL (0x1u << 3) /**< \brief (SMAP_SR) Failure */\r
+#define SMAP_SR_LCK (0x1u << 4) /**< \brief (SMAP_SR) Lock */\r
+#define SMAP_SR_EN (0x1u << 8) /**< \brief (SMAP_SR) Enabled */\r
+#define SMAP_SR_PROT (0x1u << 9) /**< \brief (SMAP_SR) Protected */\r
+#define SMAP_SR_DBGP (0x1u << 10) /**< \brief (SMAP_SR) Debugger Present */\r
+#define SMAP_SR_STATE_Pos 24\r
+#define SMAP_SR_STATE_Msk (0x7u << SMAP_SR_STATE_Pos) /**< \brief (SMAP_SR) State */\r
+#define SMAP_SR_STATE(value) ((SMAP_SR_STATE_Msk & ((value) << SMAP_SR_STATE_Pos)))\r
+/* -------- SMAP_SCR : (SMAP Offset: 0x08) Status Clear Register -------- */\r
+#define SMAP_SCR_DONE (0x1u << 0) /**< \brief (SMAP_SCR) Done */\r
+#define SMAP_SCR_HCR (0x1u << 1) /**< \brief (SMAP_SCR) Hold Core Register */\r
+#define SMAP_SCR_BERR (0x1u << 2) /**< \brief (SMAP_SCR) Bus error */\r
+#define SMAP_SCR_FAIL (0x1u << 3) /**< \brief (SMAP_SCR) Failure */\r
+#define SMAP_SCR_LCK (0x1u << 4) /**< \brief (SMAP_SCR) Lock error */\r
+/* -------- SMAP_ADDR : (SMAP Offset: 0x0C) Address Register -------- */\r
+#define SMAP_ADDR_ADDR_Pos 2\r
+#define SMAP_ADDR_ADDR_Msk (0x3FFFFFFFu << SMAP_ADDR_ADDR_Pos) /**< \brief (SMAP_ADDR) Address Value */\r
+#define SMAP_ADDR_ADDR(value) ((SMAP_ADDR_ADDR_Msk & ((value) << SMAP_ADDR_ADDR_Pos)))\r
+/* -------- SMAP_LENGTH : (SMAP Offset: 0x10) Length Register -------- */\r
+#define SMAP_LENGTH_LENGTH_Pos 2\r
+#define SMAP_LENGTH_LENGTH_Msk (0x3FFFFFFFu << SMAP_LENGTH_LENGTH_Pos) /**< \brief (SMAP_LENGTH) Length Register */\r
+#define SMAP_LENGTH_LENGTH(value) ((SMAP_LENGTH_LENGTH_Msk & ((value) << SMAP_LENGTH_LENGTH_Pos)))\r
+/* -------- SMAP_DATA : (SMAP Offset: 0x14) Data Register -------- */\r
+#define SMAP_DATA_DATA_Pos 0\r
+#define SMAP_DATA_DATA_Msk (0xFFFFFFFFu << SMAP_DATA_DATA_Pos) /**< \brief (SMAP_DATA) Generic data register */\r
+#define SMAP_DATA_DATA(value) ((SMAP_DATA_DATA_Msk & ((value) << SMAP_DATA_DATA_Pos)))\r
+/* -------- SMAP_VERSION : (SMAP Offset: 0x28) VERSION register -------- */\r
+#define SMAP_VERSION_VERSION_Pos 0\r
+#define SMAP_VERSION_VERSION_Msk (0xFFFu << SMAP_VERSION_VERSION_Pos) /**< \brief (SMAP_VERSION) Version number */\r
+#define SMAP_VERSION_VERSION(value) ((SMAP_VERSION_VERSION_Msk & ((value) << SMAP_VERSION_VERSION_Pos)))\r
+#define SMAP_VERSION_VARIANT_Pos 16\r
+#define SMAP_VERSION_VARIANT_Msk (0xFu << SMAP_VERSION_VARIANT_Pos) /**< \brief (SMAP_VERSION) Variant number */\r
+#define SMAP_VERSION_VARIANT(value) ((SMAP_VERSION_VARIANT_Msk & ((value) << SMAP_VERSION_VARIANT_Pos)))\r
+/* -------- SMAP_CIDR : (SMAP Offset: 0xF0) Chip ID Register -------- */\r
+#define SMAP_CIDR_VERSION_Pos 0\r
+#define SMAP_CIDR_VERSION_Msk (0x1Fu << SMAP_CIDR_VERSION_Pos) /**< \brief (SMAP_CIDR) Version of the Device */\r
+#define SMAP_CIDR_VERSION(value) ((SMAP_CIDR_VERSION_Msk & ((value) << SMAP_CIDR_VERSION_Pos)))\r
+#define SMAP_CIDR_EPROC_Pos 5\r
+#define SMAP_CIDR_EPROC_Msk (0x7u << SMAP_CIDR_EPROC_Pos) /**< \brief (SMAP_CIDR) Embedded Processor */\r
+#define SMAP_CIDR_EPROC(value) ((SMAP_CIDR_EPROC_Msk & ((value) << SMAP_CIDR_EPROC_Pos)))\r
+#define SMAP_CIDR_NVPSIZ_Pos 8\r
+#define SMAP_CIDR_NVPSIZ_Msk (0xFu << SMAP_CIDR_NVPSIZ_Pos) /**< \brief (SMAP_CIDR) Nonvolatile Program Memory Size */\r
+#define SMAP_CIDR_NVPSIZ(value) ((SMAP_CIDR_NVPSIZ_Msk & ((value) << SMAP_CIDR_NVPSIZ_Pos)))\r
+#define SMAP_CIDR_NVPSIZ2_Pos 12\r
+#define SMAP_CIDR_NVPSIZ2_Msk (0xFu << SMAP_CIDR_NVPSIZ2_Pos) /**< \brief (SMAP_CIDR) Second Nonvolatile Program Memory Size */\r
+#define SMAP_CIDR_NVPSIZ2(value) ((SMAP_CIDR_NVPSIZ2_Msk & ((value) << SMAP_CIDR_NVPSIZ2_Pos)))\r
+#define SMAP_CIDR_SRAMSIZ_Pos 16\r
+#define SMAP_CIDR_SRAMSIZ_Msk (0x1Fu << SMAP_CIDR_SRAMSIZ_Pos) /**< \brief (SMAP_CIDR) Internal SRAM Size */\r
+#define SMAP_CIDR_SRAMSIZ(value) ((SMAP_CIDR_SRAMSIZ_Msk & ((value) << SMAP_CIDR_SRAMSIZ_Pos)))\r
+#define SMAP_CIDR_ARCH_Pos 21\r
+#define SMAP_CIDR_ARCH_Msk (0x7Fu << SMAP_CIDR_ARCH_Pos) /**< \brief (SMAP_CIDR) Architecture Identifier */\r
+#define SMAP_CIDR_ARCH(value) ((SMAP_CIDR_ARCH_Msk & ((value) << SMAP_CIDR_ARCH_Pos)))\r
+#define SMAP_CIDR_NVPTYP_Pos 28\r
+#define SMAP_CIDR_NVPTYP_Msk (0x7u << SMAP_CIDR_NVPTYP_Pos) /**< \brief (SMAP_CIDR) Nonvolatile Program Memory Type */\r
+#define SMAP_CIDR_NVPTYP(value) ((SMAP_CIDR_NVPTYP_Msk & ((value) << SMAP_CIDR_NVPTYP_Pos)))\r
+#define SMAP_CIDR_EXT (0x1u << 31) /**< \brief (SMAP_CIDR) Extension Flag */\r
+/* -------- SMAP_EXID : (SMAP Offset: 0xF4) Chip ID Extension Register -------- */\r
+#define SMAP_EXID_EXID_Pos 0\r
+#define SMAP_EXID_EXID_Msk (0xFFFFFFFFu << SMAP_EXID_EXID_Pos) /**< \brief (SMAP_EXID) Chip ID Extension */\r
+#define SMAP_EXID_EXID(value) ((SMAP_EXID_EXID_Msk & ((value) << SMAP_EXID_EXID_Pos)))\r
+/* -------- SMAP_IDR : (SMAP Offset: 0xFC) AP Identification register -------- */\r
+#define SMAP_IDR_APIDV_Pos 0\r
+#define SMAP_IDR_APIDV_Msk (0xFu << SMAP_IDR_APIDV_Pos) /**< \brief (SMAP_IDR) AP Identification Variant */\r
+#define SMAP_IDR_APIDV(value) ((SMAP_IDR_APIDV_Msk & ((value) << SMAP_IDR_APIDV_Pos)))\r
+#define SMAP_IDR_APID_Pos 4\r
+#define SMAP_IDR_APID_Msk (0xFu << SMAP_IDR_APID_Pos) /**< \brief (SMAP_IDR) AP Identification */\r
+#define SMAP_IDR_APID(value) ((SMAP_IDR_APID_Msk & ((value) << SMAP_IDR_APID_Pos)))\r
+#define SMAP_IDR_CLSS (0x1u << 16) /**< \brief (SMAP_IDR) Class */\r
+#define SMAP_IDR_IC_Pos 17\r
+#define SMAP_IDR_IC_Msk (0x7Fu << SMAP_IDR_IC_Pos) /**< \brief (SMAP_IDR) JEP-106 Identity Code */\r
+#define SMAP_IDR_IC(value) ((SMAP_IDR_IC_Msk & ((value) << SMAP_IDR_IC_Pos)))\r
+#define SMAP_IDR_CC_Pos 24\r
+#define SMAP_IDR_CC_Msk (0xFu << SMAP_IDR_CC_Pos) /**< \brief (SMAP_IDR) JEP-106 Continuation Code */\r
+#define SMAP_IDR_CC(value) ((SMAP_IDR_CC_Msk & ((value) << SMAP_IDR_CC_Pos)))\r
+#define SMAP_IDR_REVISION_Pos 28\r
+#define SMAP_IDR_REVISION_Msk (0xFu << SMAP_IDR_REVISION_Pos) /**< \brief (SMAP_IDR) Revision */\r
+#define SMAP_IDR_REVISION(value) ((SMAP_IDR_REVISION_Msk & ((value) << SMAP_IDR_REVISION_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR SPI */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_SPI Serial Peripheral Interface */\r
+/*@{*/\r
+\r
+#define REV_SPI 0x211\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief SPI hardware registers */\r
+typedef struct {\r
+ WoReg SPI_CR; /**< \brief (SPI Offset: 0x00) Control Register */\r
+ RwReg SPI_MR; /**< \brief (SPI Offset: 0x04) Mode Register */\r
+ RoReg SPI_RDR; /**< \brief (SPI Offset: 0x08) Receive Data Register */\r
+ WoReg SPI_TDR; /**< \brief (SPI Offset: 0x0C) Transmit Data Register */\r
+ RoReg SPI_SR; /**< \brief (SPI Offset: 0x10) Status Register */\r
+ WoReg SPI_IER; /**< \brief (SPI Offset: 0x14) Interrupt Enable Register */\r
+ WoReg SPI_IDR; /**< \brief (SPI Offset: 0x18) Interrupt Disable Register */\r
+ RoReg SPI_IMR; /**< \brief (SPI Offset: 0x1C) Interrupt Mask Register */\r
+ RoReg Reserved1[4];\r
+ RwReg SPI_CSR[4]; /**< \brief (SPI Offset: 0x30) Chip Select Registers */\r
+ RoReg Reserved2[41];\r
+ RwReg SPI_WPCR; /**< \brief (SPI Offset: 0xE4) Write Protection control Register */\r
+ RoReg SPI_WPSR; /**< \brief (SPI Offset: 0xE8) Write Protection status Register */\r
+ RoReg Reserved3[3];\r
+ RoReg SPI_FEATURES; /**< \brief (SPI Offset: 0xF8) Features Register */\r
+ RoReg SPI_VERSION; /**< \brief (SPI Offset: 0xFC) Version Register */\r
+} Spi;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */\r
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */\r
+#define SPI_CR_SPIEN_0 (0x0u << 0) /**< \brief (SPI_CR) No effect. */\r
+#define SPI_CR_SPIEN_1 (0x1u << 0) /**< \brief (SPI_CR) Enables the SPI to transfer and receive data. */\r
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */\r
+#define SPI_CR_SPIDIS_0 (0x0u << 1) /**< \brief (SPI_CR) No effect. */\r
+#define SPI_CR_SPIDIS_1 (0x1u << 1) /**< \brief (SPI_CR) Disables the SPI.All pins are set in input mode and no data is received or transmitted.If a transfer is in progress, the transfer is finished before the SPI is disabled.If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. */\r
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */\r
+#define SPI_CR_SWRST_0 (0x0u << 7) /**< \brief (SPI_CR) No effect. */\r
+#define SPI_CR_SWRST_1 (0x1u << 7) /**< \brief (SPI_CR) Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. */\r
+#define SPI_CR_FLUSHFIFO (0x1u << 8) /**< \brief (SPI_CR) Flush FIFO command */\r
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */\r
+#define SPI_CR_LASTXFER_0 (0x0u << 24) /**< \brief (SPI_CR) No effect. */\r
+#define SPI_CR_LASTXFER_1 (0x1u << 24) /**< \brief (SPI_CR) The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, thisallows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TDtransfer has completed. */\r
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */\r
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */\r
+#define SPI_MR_MSTR_0 (0x0u << 0) /**< \brief (SPI_MR) SPI is in Slave mode. */\r
+#define SPI_MR_MSTR_1 (0x1u << 0) /**< \brief (SPI_MR) SPI is in Master mode. */\r
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */\r
+#define SPI_MR_PS_0 (0x0u << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */\r
+#define SPI_MR_PS_1 (0x1u << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */\r
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */\r
+#define SPI_MR_PCSDEC_0 (0x0u << 2) /**< \brief (SPI_MR) The chip selects are directly connected to a peripheral device. */\r
+#define SPI_MR_PCSDEC_1 (0x1u << 2) /**< \brief (SPI_MR) The four chip select lines are connected to a 4- to 16-bit decoder.When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bitdecoder. The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:CSR0 defines peripheral chip select signals 0 to 3.CSR1 defines peripheral chip select signals 4 to 7.CSR2 defines peripheral chip select signals 8 to 11.CSR3 defines peripheral chip select signals 12 to 15. */\r
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */\r
+#define SPI_MR_MODFDIS_0 (0x0u << 4) /**< \brief (SPI_MR) Mode fault detection is enabled. */\r
+#define SPI_MR_MODFDIS_1 (0x1u << 4) /**< \brief (SPI_MR) Mode fault detection is disabled. */\r
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) wait data read before transfer */\r
+#define SPI_MR_RXFIFOEN (0x1u << 6) /**< \brief (SPI_MR) FIFO in Reception Enable */\r
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */\r
+#define SPI_MR_LLB_0 (0x0u << 7) /**< \brief (SPI_MR) Local loopback path disabled. */\r
+#define SPI_MR_LLB_1 (0x1u << 7) /**< \brief (SPI_MR) Local loopback path enabled.LLB controls the local loopback on the data serializer for testing in Master Mode only. */\r
+#define SPI_MR_PCS_Pos 16\r
+#define SPI_MR_PCS_Msk (0xFu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */\r
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))\r
+#define SPI_MR_DLYBCS_Pos 24\r
+#define SPI_MR_DLYBCS_Msk (0xFFu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */\r
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))\r
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */\r
+#define SPI_RDR_RD_Pos 0\r
+#define SPI_RDR_RD_Msk (0xFFFFu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_RD(value) ((SPI_RDR_RD_Msk & ((value) << SPI_RDR_RD_Pos)))\r
+#define SPI_RDR_PCS_Pos 16\r
+#define SPI_RDR_PCS_Msk (0xFu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */\r
+#define SPI_RDR_PCS(value) ((SPI_RDR_PCS_Msk & ((value) << SPI_RDR_PCS_Pos)))\r
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */\r
+#define SPI_TDR_TD_Pos 0\r
+#define SPI_TDR_TD_Msk (0xFFFFu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */\r
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))\r
+#define SPI_TDR_PCS_Pos 16\r
+#define SPI_TDR_PCS_Msk (0xFu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */\r
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))\r
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */\r
+#define SPI_TDR_LASTXFER_0 (0x0u << 24) /**< \brief (SPI_TDR) No effect. */\r
+#define SPI_TDR_LASTXFER_1 (0x1u << 24) /**< \brief (SPI_TDR) The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, thisallows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TDtransfer has completed. */\r
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */\r
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */\r
+#define SPI_SR_RDRF_0 (0x0u << 0) /**< \brief (SPI_SR) No data has been received since the last read of RDR */\r
+#define SPI_SR_RDRF_1 (0x1u << 0) /**< \brief (SPI_SR) Data has been received and the received data has been transferred from the serializer to RDR since the last readof RDR. */\r
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */\r
+#define SPI_SR_TDRE_0 (0x0u << 1) /**< \brief (SPI_SR) Data has been written to TDR and not yet transferred to the serializer. */\r
+#define SPI_SR_TDRE_1 (0x1u << 1) /**< \brief (SPI_SR) The last data written in the Transmit Data Register has been transferred to the serializer.TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. */\r
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */\r
+#define SPI_SR_MODF_0 (0x0u << 2) /**< \brief (SPI_SR) No Mode Fault has been detected since the last read of SR. */\r
+#define SPI_SR_MODF_1 (0x1u << 2) /**< \brief (SPI_SR) A Mode Fault occurred since the last read of the SR. */\r
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */\r
+#define SPI_SR_OVRES_0 (0x0u << 3) /**< \brief (SPI_SR) No overrun has been detected since the last read of SR. */\r
+#define SPI_SR_OVRES_1 (0x1u << 3) /**< \brief (SPI_SR) An overrun has occurred since the last read of SR. */\r
+#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */\r
+#define SPI_SR_ENDRX_0 (0x0u << 4) /**< \brief (SPI_SR) The Receive Counter Register has not reached 0 since the last write in RCR or RNCR. */\r
+#define SPI_SR_ENDRX_1 (0x1u << 4) /**< \brief (SPI_SR) The Receive Counter Register has reached 0 since the last write in RCR or RNCR. */\r
+#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */\r
+#define SPI_SR_ENDTX_0 (0x0u << 5) /**< \brief (SPI_SR) The Transmit Counter Register has not reached 0 since the last write in TCR or TNCR. */\r
+#define SPI_SR_ENDTX_1 (0x1u << 5) /**< \brief (SPI_SR) The Transmit Counter Register has reached 0 since the last write in TCR or TNCR. */\r
+#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */\r
+#define SPI_SR_RXBUFF_0 (0x0u << 6) /**< \brief (SPI_SR) RCR or RNCR has a value other than 0. */\r
+#define SPI_SR_RXBUFF_1 (0x1u << 6) /**< \brief (SPI_SR) Both RCR and RNCR has a value of 0. */\r
+#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */\r
+#define SPI_SR_TXBUFE_0 (0x0u << 7) /**< \brief (SPI_SR) TCR or TNCR has a value other than 0. */\r
+#define SPI_SR_TXBUFE_1 (0x1u << 7) /**< \brief (SPI_SR) Both TCR and TNCR has a value of 0. */\r
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */\r
+#define SPI_SR_NSSR_0 (0x0u << 8) /**< \brief (SPI_SR) No rising edge detected on NSS pin since last read. */\r
+#define SPI_SR_NSSR_1 (0x1u << 8) /**< \brief (SPI_SR) A rising edge occurred on NSS pin since last read. */\r
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */\r
+#define SPI_SR_TXEMPTY_0 (0x0u << 9) /**< \brief (SPI_SR) As soon as data is written in TDR. */\r
+#define SPI_SR_TXEMPTY_1 (0x1u << 9) /**< \brief (SPI_SR) TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion ofsuch delay. */\r
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */\r
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */\r
+#define SPI_SR_SPIENS_0 (0x0u << 16) /**< \brief (SPI_SR) SPI is disabled. */\r
+#define SPI_SR_SPIENS_1 (0x1u << 16) /**< \brief (SPI_SR) SPI is enabled. */\r
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */\r
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */\r
+#define SPI_IER_RDRF_0 (0x0u << 0) /**< \brief (SPI_IER) No effect. */\r
+#define SPI_IER_RDRF_1 (0x1u << 0) /**< \brief (SPI_IER) Enables the corresponding interrupt. */\r
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) Transmit Data Register Empty Interrupt Enable */\r
+#define SPI_IER_TDRE_0 (0x0u << 1) /**< \brief (SPI_IER) No effect. */\r
+#define SPI_IER_TDRE_1 (0x1u << 1) /**< \brief (SPI_IER) Enables the corresponding interrupt. */\r
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */\r
+#define SPI_IER_MODF_0 (0x0u << 2) /**< \brief (SPI_IER) No effect. */\r
+#define SPI_IER_MODF_1 (0x1u << 2) /**< \brief (SPI_IER) Enables the corresponding interrupt. */\r
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */\r
+#define SPI_IER_OVRES_0 (0x0u << 3) /**< \brief (SPI_IER) No effect. */\r
+#define SPI_IER_OVRES_1 (0x1u << 3) /**< \brief (SPI_IER) Enables the corresponding interrupt. */\r
+#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */\r
+#define SPI_IER_ENDRX_0 (0x0u << 4) /**< \brief (SPI_IER) No effect. */\r
+#define SPI_IER_ENDRX_1 (0x1u << 4) /**< \brief (SPI_IER) Enables the corresponding interrupt. */\r
+#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */\r
+#define SPI_IER_ENDTX_0 (0x0u << 5) /**< \brief (SPI_IER) No effect. */\r
+#define SPI_IER_ENDTX_1 (0x1u << 5) /**< \brief (SPI_IER) Enables the corresponding interrupt. */\r
+#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */\r
+#define SPI_IER_RXBUFF_0 (0x0u << 6) /**< \brief (SPI_IER) No effect. */\r
+#define SPI_IER_RXBUFF_1 (0x1u << 6) /**< \brief (SPI_IER) Enables the corresponding interrupt. */\r
+#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */\r
+#define SPI_IER_TXBUFE_0 (0x0u << 7) /**< \brief (SPI_IER) No effect. */\r
+#define SPI_IER_TXBUFE_1 (0x1u << 7) /**< \brief (SPI_IER) Enables the corresponding interrupt. */\r
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */\r
+#define SPI_IER_NSSR_0 (0x0u << 8) /**< \brief (SPI_IER) No effect. */\r
+#define SPI_IER_NSSR_1 (0x1u << 8) /**< \brief (SPI_IER) Enables the corresponding interrupt. */\r
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */\r
+#define SPI_IER_TXEMPTY_0 (0x0u << 9) /**< \brief (SPI_IER) No effect. */\r
+#define SPI_IER_TXEMPTY_1 (0x1u << 9) /**< \brief (SPI_IER) Enables the corresponding interrupt. */\r
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */\r
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */\r
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */\r
+#define SPI_IDR_RDRF_0 (0x0u << 0) /**< \brief (SPI_IDR) No effect. */\r
+#define SPI_IDR_RDRF_1 (0x1u << 0) /**< \brief (SPI_IDR) Disables the corresponding interrupt. */\r
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) Transmit Data Register Empty Interrupt Disable */\r
+#define SPI_IDR_TDRE_0 (0x0u << 1) /**< \brief (SPI_IDR) No effect. */\r
+#define SPI_IDR_TDRE_1 (0x1u << 1) /**< \brief (SPI_IDR) Disables the corresponding interrupt. */\r
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */\r
+#define SPI_IDR_MODF_0 (0x0u << 2) /**< \brief (SPI_IDR) No effect. */\r
+#define SPI_IDR_MODF_1 (0x1u << 2) /**< \brief (SPI_IDR) Disables the corresponding interrupt. */\r
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */\r
+#define SPI_IDR_OVRES_0 (0x0u << 3) /**< \brief (SPI_IDR) No effect. */\r
+#define SPI_IDR_OVRES_1 (0x1u << 3) /**< \brief (SPI_IDR) Disables the corresponding interrupt. */\r
+#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */\r
+#define SPI_IDR_ENDRX_0 (0x0u << 4) /**< \brief (SPI_IDR) No effect. */\r
+#define SPI_IDR_ENDRX_1 (0x1u << 4) /**< \brief (SPI_IDR) Disables the corresponding interrupt. */\r
+#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define SPI_IDR_ENDTX_0 (0x0u << 5) /**< \brief (SPI_IDR) No effect. */\r
+#define SPI_IDR_ENDTX_1 (0x1u << 5) /**< \brief (SPI_IDR) Disables the corresponding interrupt. */\r
+#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */\r
+#define SPI_IDR_RXBUFF_0 (0x0u << 6) /**< \brief (SPI_IDR) No effect. */\r
+#define SPI_IDR_RXBUFF_1 (0x1u << 6) /**< \brief (SPI_IDR) Disables the corresponding interrupt. */\r
+#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */\r
+#define SPI_IDR_TXBUFE_0 (0x0u << 7) /**< \brief (SPI_IDR) No effect. */\r
+#define SPI_IDR_TXBUFE_1 (0x1u << 7) /**< \brief (SPI_IDR) Disables the corresponding interrupt. */\r
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */\r
+#define SPI_IDR_NSSR_0 (0x0u << 8) /**< \brief (SPI_IDR) No effect. */\r
+#define SPI_IDR_NSSR_1 (0x1u << 8) /**< \brief (SPI_IDR) Disables the corresponding interrupt. */\r
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */\r
+#define SPI_IDR_TXEMPTY_0 (0x0u << 9) /**< \brief (SPI_IDR) No effect. */\r
+#define SPI_IDR_TXEMPTY_1 (0x1u << 9) /**< \brief (SPI_IDR) Disables the corresponding interrupt. */\r
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */\r
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */\r
+#define SPI_IMR_RDRF_0 (0x0u << 0) /**< \brief (SPI_IMR) The corresponding interrupt is not enabled. */\r
+#define SPI_IMR_RDRF_1 (0x1u << 0) /**< \brief (SPI_IMR) The corresponding interrupt is enabled. */\r
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) Transmit Data Register Empty Interrupt Mask */\r
+#define SPI_IMR_TDRE_0 (0x0u << 1) /**< \brief (SPI_IMR) The corresponding interrupt is not enabled. */\r
+#define SPI_IMR_TDRE_1 (0x1u << 1) /**< \brief (SPI_IMR) The corresponding interrupt is enabled. */\r
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */\r
+#define SPI_IMR_MODF_0 (0x0u << 2) /**< \brief (SPI_IMR) The corresponding interrupt is not enabled. */\r
+#define SPI_IMR_MODF_1 (0x1u << 2) /**< \brief (SPI_IMR) The corresponding interrupt is enabled. */\r
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */\r
+#define SPI_IMR_OVRES_0 (0x0u << 3) /**< \brief (SPI_IMR) The corresponding interrupt is not enabled. */\r
+#define SPI_IMR_OVRES_1 (0x1u << 3) /**< \brief (SPI_IMR) The corresponding interrupt is enabled. */\r
+#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */\r
+#define SPI_IMR_ENDRX_0 (0x0u << 4) /**< \brief (SPI_IMR) The corresponding interrupt is not enabled. */\r
+#define SPI_IMR_ENDRX_1 (0x1u << 4) /**< \brief (SPI_IMR) The corresponding interrupt is enabled. */\r
+#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define SPI_IMR_ENDTX_0 (0x0u << 5) /**< \brief (SPI_IMR) The corresponding interrupt is not enabled. */\r
+#define SPI_IMR_ENDTX_1 (0x1u << 5) /**< \brief (SPI_IMR) The corresponding interrupt is enabled. */\r
+#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */\r
+#define SPI_IMR_RXBUFF_0 (0x0u << 6) /**< \brief (SPI_IMR) The corresponding interrupt is not enabled. */\r
+#define SPI_IMR_RXBUFF_1 (0x1u << 6) /**< \brief (SPI_IMR) The corresponding interrupt is enabled. */\r
+#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */\r
+#define SPI_IMR_TXBUFE_0 (0x0u << 7) /**< \brief (SPI_IMR) The corresponding interrupt is not enabled. */\r
+#define SPI_IMR_TXBUFE_1 (0x1u << 7) /**< \brief (SPI_IMR) The corresponding interrupt is enabled. */\r
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */\r
+#define SPI_IMR_NSSR_0 (0x0u << 8) /**< \brief (SPI_IMR) The corresponding interrupt is not enabled. */\r
+#define SPI_IMR_NSSR_1 (0x1u << 8) /**< \brief (SPI_IMR) The corresponding interrupt is enabled. */\r
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */\r
+#define SPI_IMR_TXEMPTY_0 (0x0u << 9) /**< \brief (SPI_IMR) The corresponding interrupt is not enabled. */\r
+#define SPI_IMR_TXEMPTY_1 (0x1u << 9) /**< \brief (SPI_IMR) The corresponding interrupt is enabled. */\r
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */\r
+/* -------- SPI_CSR0 : (SPI Offset: 0x30) Chip Select Register 0 -------- */\r
+#define SPI_CSR0_CPOL (0x1u << 0) /**< \brief (SPI_CSR0) Clock Polarity */\r
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (Unified SPI_CSR) Clock Polarity */\r
+#define SPI_CSR0_CPOL_0 (0x0u << 0) /**< \brief (SPI_CSR0) The inactive state value of SPCK is logic level zero. */\r
+#define SPI_CSR_CPOL_0 (0x0u << 0) /**< \brief (Unified SPI_CSR) The inactive state value of SPCK is logic level zero. */\r
+#define SPI_CSR0_CPOL_1 (0x1u << 0) /**< \brief (SPI_CSR0) The inactive state value of SPCK is logic level one.CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce therequired clock/data relationship between master and slave devices. */\r
+#define SPI_CSR_CPOL_1 (0x1u << 0) /**< \brief (Unified SPI_CSR) The inactive state value of SPCK is logic level one.CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce therequired clock/data relationship between master and slave devices. */\r
+#define SPI_CSR0_NCPHA (0x1u << 1) /**< \brief (SPI_CSR0) Clock Phase */\r
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (Unified SPI_CSR) Clock Phase */\r
+#define SPI_CSR0_NCPHA_0 (0x0u << 1) /**< \brief (SPI_CSR0) Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. */\r
+#define SPI_CSR_NCPHA_0 (0x0u << 1) /**< \brief (Unified SPI_CSR) Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. */\r
+#define SPI_CSR0_NCPHA_1 (0x1u << 1) /**< \brief (SPI_CSR0) Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA isused with CPOL to produce the required clock/data relationship between master and slave devices. */\r
+#define SPI_CSR_NCPHA_1 (0x1u << 1) /**< \brief (Unified SPI_CSR) Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA isused with CPOL to produce the required clock/data relationship between master and slave devices. */\r
+#define SPI_CSR0_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR0) Chip Select Not Active After Transfer */\r
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (Unified SPI_CSR) Chip Select Not Active After Transfer */\r
+#define SPI_CSR0_CSAAT (0x1u << 3) /**< \brief (SPI_CSR0) Chip Select Active After Transfer */\r
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (Unified SPI_CSR) Chip Select Active After Transfer */\r
+#define SPI_CSR0_CSAAT_0 (0x0u << 3) /**< \brief (SPI_CSR0) The Peripheral Chip Select Line rises as soon as the last transfer is achieved. */\r
+#define SPI_CSR_CSAAT_0 (0x0u << 3) /**< \brief (Unified SPI_CSR) The Peripheral Chip Select Line rises as soon as the last transfer is achieved. */\r
+#define SPI_CSR0_CSAAT_1 (0x1u << 3) /**< \brief (SPI_CSR0) The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer isrequested on a different chip select. */\r
+#define SPI_CSR_CSAAT_1 (0x1u << 3) /**< \brief (Unified SPI_CSR) The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer isrequested on a different chip select. */\r
+#define SPI_CSR0_BITS_Pos 4\r
+#define SPI_CSR0_BITS_Msk (0xFu << SPI_CSR0_BITS_Pos) /**< \brief (SPI_CSR0) Bits Per Transfer */\r
+#define SPI_CSR0_BITS(value) ((SPI_CSR0_BITS_Msk & ((value) << SPI_CSR0_BITS_Pos)))\r
+#define SPI_CSR_BITS_Pos 4\r
+#define SPI_CSR_BITS_Msk (0xFu << SPI_CSR0_BITS_Pos) /**< \brief (SPI_CSR0) Bits Per Transfer */\r
+#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)))\r
+#define SPI_CSR0_BITS_8_BPT (0x0u << 4) /**< \brief (SPI_CSR0) 8 bits per transfer */\r
+#define SPI_CSR_BITS_8_BPT (0x0u << 4) /**< \brief (Unified SPI_CSR) 8 bits per transfer */\r
+#define SPI_CSR0_BITS_9_BPT (0x1u << 4) /**< \brief (SPI_CSR0) 9 bits per transfer */\r
+#define SPI_CSR_BITS_9_BPT (0x1u << 4) /**< \brief (Unified SPI_CSR) 9 bits per transfer */\r
+#define SPI_CSR0_BITS_10_BPT (0x2u << 4) /**< \brief (SPI_CSR0) 10 bits per transfer */\r
+#define SPI_CSR_BITS_10_BPT (0x2u << 4) /**< \brief (Unified SPI_CSR) 10 bits per transfer */\r
+#define SPI_CSR0_BITS_11_BPT (0x3u << 4) /**< \brief (SPI_CSR0) 11 bits per transfer */\r
+#define SPI_CSR_BITS_11_BPT (0x3u << 4) /**< \brief (Unified SPI_CSR) 11 bits per transfer */\r
+#define SPI_CSR0_BITS_12_BPT (0x4u << 4) /**< \brief (SPI_CSR0) 12 bits per transfer */\r
+#define SPI_CSR_BITS_12_BPT (0x4u << 4) /**< \brief (Unified SPI_CSR) 12 bits per transfer */\r
+#define SPI_CSR0_BITS_13_BPT (0x5u << 4) /**< \brief (SPI_CSR0) 13 bits per transfer */\r
+#define SPI_CSR_BITS_13_BPT (0x5u << 4) /**< \brief (Unified SPI_CSR) 13 bits per transfer */\r
+#define SPI_CSR0_BITS_14_BPT (0x6u << 4) /**< \brief (SPI_CSR0) 14 bits per transfer */\r
+#define SPI_CSR_BITS_14_BPT (0x6u << 4) /**< \brief (Unified SPI_CSR) 14 bits per transfer */\r
+#define SPI_CSR0_BITS_15_BPT (0x7u << 4) /**< \brief (SPI_CSR0) 15 bits per transfer */\r
+#define SPI_CSR_BITS_15_BPT (0x7u << 4) /**< \brief (Unified SPI_CSR) 15 bits per transfer */\r
+#define SPI_CSR0_BITS_16_BPT (0x8u << 4) /**< \brief (SPI_CSR0) 16 bits per transfer */\r
+#define SPI_CSR_BITS_16_BPT (0x8u << 4) /**< \brief (Unified SPI_CSR) 16 bits per transfer */\r
+#define SPI_CSR0_SCBR_Pos 8\r
+#define SPI_CSR0_SCBR_Msk (0xFFu << SPI_CSR0_SCBR_Pos) /**< \brief (SPI_CSR0) Serial Clock Baud Rate */\r
+#define SPI_CSR0_SCBR(value) ((SPI_CSR0_SCBR_Msk & ((value) << SPI_CSR0_SCBR_Pos)))\r
+#define SPI_CSR_SCBR_Pos 8\r
+#define SPI_CSR_SCBR_Msk (0xFFu << SPI_CSR0_SCBR_Pos) /**< \brief (SPI_CSR0) Serial Clock Baud Rate */\r
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))\r
+#define SPI_CSR0_DLYBS_Pos 16\r
+#define SPI_CSR0_DLYBS_Msk (0xFFu << SPI_CSR0_DLYBS_Pos) /**< \brief (SPI_CSR0) Delay Before SPCK */\r
+#define SPI_CSR0_DLYBS(value) ((SPI_CSR0_DLYBS_Msk & ((value) << SPI_CSR0_DLYBS_Pos)))\r
+#define SPI_CSR_DLYBS_Pos 16\r
+#define SPI_CSR_DLYBS_Msk (0xFFu << SPI_CSR0_DLYBS_Pos) /**< \brief (SPI_CSR0) Delay Before SPCK */\r
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))\r
+#define SPI_CSR0_DLYBCT_Pos 24\r
+#define SPI_CSR0_DLYBCT_Msk (0xFFu << SPI_CSR0_DLYBCT_Pos) /**< \brief (SPI_CSR0) Delay Between Consecutive Transfers */\r
+#define SPI_CSR0_DLYBCT(value) ((SPI_CSR0_DLYBCT_Msk & ((value) << SPI_CSR0_DLYBCT_Pos)))\r
+#define SPI_CSR_DLYBCT_Pos 24\r
+#define SPI_CSR_DLYBCT_Msk (0xFFu << SPI_CSR0_DLYBCT_Pos) /**< \brief (SPI_CSR0) Delay Between Consecutive Transfers */\r
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))\r
+/* -------- SPI_CSR1 : (SPI Offset: 0x34) Chip Select Register 1 -------- */\r
+#define SPI_CSR1_CPOL (0x1u << 0) /**< \brief (SPI_CSR1) Clock Polarity */\r
+#define SPI_CSR1_CPOL_0 (0x0u << 0) /**< \brief (SPI_CSR1) The inactive state value of SPCK is logic level zero. */\r
+#define SPI_CSR1_CPOL_1 (0x1u << 0) /**< \brief (SPI_CSR1) The inactive state value of SPCK is logic level one.CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce therequired clock/data relationship between master and slave devices. */\r
+#define SPI_CSR1_NCPHA (0x1u << 1) /**< \brief (SPI_CSR1) Clock Phase */\r
+#define SPI_CSR1_NCPHA_0 (0x0u << 1) /**< \brief (SPI_CSR1) Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. */\r
+#define SPI_CSR1_NCPHA_1 (0x1u << 1) /**< \brief (SPI_CSR1) Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA isused with CPOL to produce the required clock/data relationship between master and slave devices. */\r
+#define SPI_CSR1_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR1) Chip Select Not Active After Transfer */\r
+#define SPI_CSR1_CSAAT (0x1u << 3) /**< \brief (SPI_CSR1) Chip Select Active After Transfer */\r
+#define SPI_CSR1_CSAAT_0 (0x0u << 3) /**< \brief (SPI_CSR1) The Peripheral Chip Select Line rises as soon as the last transfer is achieved. */\r
+#define SPI_CSR1_CSAAT_1 (0x1u << 3) /**< \brief (SPI_CSR1) The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer isrequested on a different chip select. */\r
+#define SPI_CSR1_BITS_Pos 4\r
+#define SPI_CSR1_BITS_Msk (0xFu << SPI_CSR1_BITS_Pos) /**< \brief (SPI_CSR1) Bits Per Transfer */\r
+#define SPI_CSR1_BITS(value) ((SPI_CSR1_BITS_Msk & ((value) << SPI_CSR1_BITS_Pos)))\r
+#define SPI_CSR1_BITS_8_BPT (0x0u << 4) /**< \brief (SPI_CSR1) 8 bits per transfer */\r
+#define SPI_CSR1_BITS_9_BPT (0x1u << 4) /**< \brief (SPI_CSR1) 9 bits per transfer */\r
+#define SPI_CSR1_BITS_10_BPT (0x2u << 4) /**< \brief (SPI_CSR1) 10 bits per transfer */\r
+#define SPI_CSR1_BITS_11_BPT (0x3u << 4) /**< \brief (SPI_CSR1) 11 bits per transfer */\r
+#define SPI_CSR1_BITS_12_BPT (0x4u << 4) /**< \brief (SPI_CSR1) 12 bits per transfer */\r
+#define SPI_CSR1_BITS_13_BPT (0x5u << 4) /**< \brief (SPI_CSR1) 13 bits per transfer */\r
+#define SPI_CSR1_BITS_14_BPT (0x6u << 4) /**< \brief (SPI_CSR1) 14 bits per transfer */\r
+#define SPI_CSR1_BITS_15_BPT (0x7u << 4) /**< \brief (SPI_CSR1) 15 bits per transfer */\r
+#define SPI_CSR1_BITS_16_BPT (0x8u << 4) /**< \brief (SPI_CSR1) 16 bits per transfer */\r
+#define SPI_CSR1_SCBR_Pos 8\r
+#define SPI_CSR1_SCBR_Msk (0xFFu << SPI_CSR1_SCBR_Pos) /**< \brief (SPI_CSR1) Serial Clock Baud Rate */\r
+#define SPI_CSR1_SCBR(value) ((SPI_CSR1_SCBR_Msk & ((value) << SPI_CSR1_SCBR_Pos)))\r
+#define SPI_CSR1_DLYBS_Pos 16\r
+#define SPI_CSR1_DLYBS_Msk (0xFFu << SPI_CSR1_DLYBS_Pos) /**< \brief (SPI_CSR1) Delay Before SPCK */\r
+#define SPI_CSR1_DLYBS(value) ((SPI_CSR1_DLYBS_Msk & ((value) << SPI_CSR1_DLYBS_Pos)))\r
+#define SPI_CSR1_DLYBCT_Pos 24\r
+#define SPI_CSR1_DLYBCT_Msk (0xFFu << SPI_CSR1_DLYBCT_Pos) /**< \brief (SPI_CSR1) Delay Between Consecutive Transfers */\r
+#define SPI_CSR1_DLYBCT(value) ((SPI_CSR1_DLYBCT_Msk & ((value) << SPI_CSR1_DLYBCT_Pos)))\r
+/* -------- SPI_CSR2 : (SPI Offset: 0x38) Chip Select Register 2 -------- */\r
+#define SPI_CSR2_CPOL (0x1u << 0) /**< \brief (SPI_CSR2) Clock Polarity */\r
+#define SPI_CSR2_CPOL_0 (0x0u << 0) /**< \brief (SPI_CSR2) The inactive state value of SPCK is logic level zero. */\r
+#define SPI_CSR2_CPOL_1 (0x1u << 0) /**< \brief (SPI_CSR2) The inactive state value of SPCK is logic level one.CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce therequired clock/data relationship between master and slave devices. */\r
+#define SPI_CSR2_NCPHA (0x1u << 1) /**< \brief (SPI_CSR2) Clock Phase */\r
+#define SPI_CSR2_NCPHA_0 (0x0u << 1) /**< \brief (SPI_CSR2) Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. */\r
+#define SPI_CSR2_NCPHA_1 (0x1u << 1) /**< \brief (SPI_CSR2) Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA isused with CPOL to produce the required clock/data relationship between master and slave devices. */\r
+#define SPI_CSR2_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR2) Chip Select Not Active After Transfer */\r
+#define SPI_CSR2_CSAAT (0x1u << 3) /**< \brief (SPI_CSR2) Chip Select Active After Transfer */\r
+#define SPI_CSR2_CSAAT_0 (0x0u << 3) /**< \brief (SPI_CSR2) The Peripheral Chip Select Line rises as soon as the last transfer is achieved. */\r
+#define SPI_CSR2_CSAAT_1 (0x1u << 3) /**< \brief (SPI_CSR2) The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer isrequested on a different chip select. */\r
+#define SPI_CSR2_BITS_Pos 4\r
+#define SPI_CSR2_BITS_Msk (0xFu << SPI_CSR2_BITS_Pos) /**< \brief (SPI_CSR2) Bits Per Transfer */\r
+#define SPI_CSR2_BITS(value) ((SPI_CSR2_BITS_Msk & ((value) << SPI_CSR2_BITS_Pos)))\r
+#define SPI_CSR2_BITS_8_BPT (0x0u << 4) /**< \brief (SPI_CSR2) 8 bits per transfer */\r
+#define SPI_CSR2_BITS_9_BPT (0x1u << 4) /**< \brief (SPI_CSR2) 9 bits per transfer */\r
+#define SPI_CSR2_BITS_10_BPT (0x2u << 4) /**< \brief (SPI_CSR2) 10 bits per transfer */\r
+#define SPI_CSR2_BITS_11_BPT (0x3u << 4) /**< \brief (SPI_CSR2) 11 bits per transfer */\r
+#define SPI_CSR2_BITS_12_BPT (0x4u << 4) /**< \brief (SPI_CSR2) 12 bits per transfer */\r
+#define SPI_CSR2_BITS_13_BPT (0x5u << 4) /**< \brief (SPI_CSR2) 13 bits per transfer */\r
+#define SPI_CSR2_BITS_14_BPT (0x6u << 4) /**< \brief (SPI_CSR2) 14 bits per transfer */\r
+#define SPI_CSR2_BITS_15_BPT (0x7u << 4) /**< \brief (SPI_CSR2) 15 bits per transfer */\r
+#define SPI_CSR2_BITS_16_BPT (0x8u << 4) /**< \brief (SPI_CSR2) 16 bits per transfer */\r
+#define SPI_CSR2_SCBR_Pos 8\r
+#define SPI_CSR2_SCBR_Msk (0xFFu << SPI_CSR2_SCBR_Pos) /**< \brief (SPI_CSR2) Serial Clock Baud Rate */\r
+#define SPI_CSR2_SCBR(value) ((SPI_CSR2_SCBR_Msk & ((value) << SPI_CSR2_SCBR_Pos)))\r
+#define SPI_CSR2_DLYBS_Pos 16\r
+#define SPI_CSR2_DLYBS_Msk (0xFFu << SPI_CSR2_DLYBS_Pos) /**< \brief (SPI_CSR2) Delay Before SPCK */\r
+#define SPI_CSR2_DLYBS(value) ((SPI_CSR2_DLYBS_Msk & ((value) << SPI_CSR2_DLYBS_Pos)))\r
+#define SPI_CSR2_DLYBCT_Pos 24\r
+#define SPI_CSR2_DLYBCT_Msk (0xFFu << SPI_CSR2_DLYBCT_Pos) /**< \brief (SPI_CSR2) Delay Between Consecutive Transfers */\r
+#define SPI_CSR2_DLYBCT(value) ((SPI_CSR2_DLYBCT_Msk & ((value) << SPI_CSR2_DLYBCT_Pos)))\r
+/* -------- SPI_CSR3 : (SPI Offset: 0x3C) Chip Select Register 3 -------- */\r
+#define SPI_CSR3_CPOL (0x1u << 0) /**< \brief (SPI_CSR3) Clock Polarity */\r
+#define SPI_CSR3_CPOL_0 (0x0u << 0) /**< \brief (SPI_CSR3) The inactive state value of SPCK is logic level zero. */\r
+#define SPI_CSR3_CPOL_1 (0x1u << 0) /**< \brief (SPI_CSR3) The inactive state value of SPCK is logic level one.CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce therequired clock/data relationship between master and slave devices. */\r
+#define SPI_CSR3_NCPHA (0x1u << 1) /**< \brief (SPI_CSR3) Clock Phase */\r
+#define SPI_CSR3_NCPHA_0 (0x0u << 1) /**< \brief (SPI_CSR3) Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. */\r
+#define SPI_CSR3_NCPHA_1 (0x1u << 1) /**< \brief (SPI_CSR3) Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA isused with CPOL to produce the required clock/data relationship between master and slave devices. */\r
+#define SPI_CSR3_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR3) Chip Select Not Active After Transfer */\r
+#define SPI_CSR3_CSAAT (0x1u << 3) /**< \brief (SPI_CSR3) Chip Select Active After Transfer */\r
+#define SPI_CSR3_CSAAT_0 (0x0u << 3) /**< \brief (SPI_CSR3) The Peripheral Chip Select Line rises as soon as the last transfer is achieved. */\r
+#define SPI_CSR3_CSAAT_1 (0x1u << 3) /**< \brief (SPI_CSR3) The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer isrequested on a different chip select. */\r
+#define SPI_CSR3_BITS_Pos 4\r
+#define SPI_CSR3_BITS_Msk (0xFu << SPI_CSR3_BITS_Pos) /**< \brief (SPI_CSR3) Bits Per Transfer */\r
+#define SPI_CSR3_BITS(value) ((SPI_CSR3_BITS_Msk & ((value) << SPI_CSR3_BITS_Pos)))\r
+#define SPI_CSR3_BITS_8_BPT (0x0u << 4) /**< \brief (SPI_CSR3) 8 bits per transfer */\r
+#define SPI_CSR3_BITS_9_BPT (0x1u << 4) /**< \brief (SPI_CSR3) 9 bits per transfer */\r
+#define SPI_CSR3_BITS_10_BPT (0x2u << 4) /**< \brief (SPI_CSR3) 10 bits per transfer */\r
+#define SPI_CSR3_BITS_11_BPT (0x3u << 4) /**< \brief (SPI_CSR3) 11 bits per transfer */\r
+#define SPI_CSR3_BITS_12_BPT (0x4u << 4) /**< \brief (SPI_CSR3) 12 bits per transfer */\r
+#define SPI_CSR3_BITS_13_BPT (0x5u << 4) /**< \brief (SPI_CSR3) 13 bits per transfer */\r
+#define SPI_CSR3_BITS_14_BPT (0x6u << 4) /**< \brief (SPI_CSR3) 14 bits per transfer */\r
+#define SPI_CSR3_BITS_15_BPT (0x7u << 4) /**< \brief (SPI_CSR3) 15 bits per transfer */\r
+#define SPI_CSR3_BITS_16_BPT (0x8u << 4) /**< \brief (SPI_CSR3) 16 bits per transfer */\r
+#define SPI_CSR3_SCBR_Pos 8\r
+#define SPI_CSR3_SCBR_Msk (0xFFu << SPI_CSR3_SCBR_Pos) /**< \brief (SPI_CSR3) Serial Clock Baud Rate */\r
+#define SPI_CSR3_SCBR(value) ((SPI_CSR3_SCBR_Msk & ((value) << SPI_CSR3_SCBR_Pos)))\r
+#define SPI_CSR3_DLYBS_Pos 16\r
+#define SPI_CSR3_DLYBS_Msk (0xFFu << SPI_CSR3_DLYBS_Pos) /**< \brief (SPI_CSR3) Delay Before SPCK */\r
+#define SPI_CSR3_DLYBS(value) ((SPI_CSR3_DLYBS_Msk & ((value) << SPI_CSR3_DLYBS_Pos)))\r
+#define SPI_CSR3_DLYBCT_Pos 24\r
+#define SPI_CSR3_DLYBCT_Msk (0xFFu << SPI_CSR3_DLYBCT_Pos) /**< \brief (SPI_CSR3) Delay Between Consecutive Transfers */\r
+#define SPI_CSR3_DLYBCT(value) ((SPI_CSR3_DLYBCT_Msk & ((value) << SPI_CSR3_DLYBCT_Pos)))\r
+/* -------- SPI_WPCR : (SPI Offset: 0xE4) Write Protection control Register -------- */\r
+#define SPI_WPCR_SPIWPEN (0x1u << 0) /**< \brief (SPI_WPCR) SPI write Protection Enable */\r
+#define SPI_WPCR_SPIWPKEY_Pos 8\r
+#define SPI_WPCR_SPIWPKEY_Msk (0xFFFFFFu << SPI_WPCR_SPIWPKEY_Pos) /**< \brief (SPI_WPCR) SPI write Protection Key Password */\r
+#define SPI_WPCR_SPIWPKEY(value) ((SPI_WPCR_SPIWPKEY_Msk & ((value) << SPI_WPCR_SPIWPKEY_Pos)))\r
+#define SPI_WPCR_SPIWPKEY_VALUE (0x535049u << 8) /**< \brief (SPI_WPCR) SPI Write Protection Key Password */\r
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection status Register -------- */\r
+#define SPI_WPSR_SPIWPVS_Pos 0\r
+#define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /**< \brief (SPI_WPSR) SPI write protection Violation Status */\r
+#define SPI_WPSR_SPIWPVS(value) ((SPI_WPSR_SPIWPVS_Msk & ((value) << SPI_WPSR_SPIWPVS_Pos)))\r
+#define SPI_WPSR_SPIWPVS_WRITE_WITH_WP (0x1u << 0) /**< \brief (SPI_WPSR) The Write Protection has blocked a Write access to a protected register (since the last read). */\r
+#define SPI_WPSR_SPIWPVS_SWRST_WITH_WP (0x2u << 0) /**< \brief (SPI_WPSR) Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on MR, IER, IDR or CSRx). */\r
+#define SPI_WPSR_SPIWPVS_UNEXPECTED_WRITE (0x4u << 0) /**< \brief (SPI_WPSR) Write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select “i” was active) since the last read. */\r
+#define SPI_WPSR_SPIWPVSRC_Pos 8\r
+#define SPI_WPSR_SPIWPVSRC_Msk (0xFFu << SPI_WPSR_SPIWPVSRC_Pos) /**< \brief (SPI_WPSR) SPI write Protection Violation source */\r
+#define SPI_WPSR_SPIWPVSRC(value) ((SPI_WPSR_SPIWPVSRC_Msk & ((value) << SPI_WPSR_SPIWPVSRC_Pos)))\r
+/* -------- SPI_FEATURES : (SPI Offset: 0xF8) Features Register -------- */\r
+#define SPI_FEATURES_NCS_Pos 0\r
+#define SPI_FEATURES_NCS_Msk (0xFu << SPI_FEATURES_NCS_Pos) /**< \brief (SPI_FEATURES) Number of Chip Selects */\r
+#define SPI_FEATURES_NCS(value) ((SPI_FEATURES_NCS_Msk & ((value) << SPI_FEATURES_NCS_Pos)))\r
+#define SPI_FEATURES_PCONF (0x1u << 4) /**< \brief (SPI_FEATURES) Polarity is Configurable */\r
+#define SPI_FEATURES_PPNCONF (0x1u << 5) /**< \brief (SPI_FEATURES) Polarity is Positive if Polarity is not Configurable */\r
+#define SPI_FEATURES_PHCONF (0x1u << 6) /**< \brief (SPI_FEATURES) Phase is Configurable */\r
+#define SPI_FEATURES_PHZNCONF (0x1u << 7) /**< \brief (SPI_FEATURES) Phase is Zero if Phase is not Configurable */\r
+#define SPI_FEATURES_LENCONF (0x1u << 8) /**< \brief (SPI_FEATURES) Character Length is Configurable */\r
+#define SPI_FEATURES_LENNCONF_Pos 9\r
+#define SPI_FEATURES_LENNCONF_Msk (0x7Fu << SPI_FEATURES_LENNCONF_Pos) /**< \brief (SPI_FEATURES) Character Length if not Configurable */\r
+#define SPI_FEATURES_LENNCONF(value) ((SPI_FEATURES_LENNCONF_Msk & ((value) << SPI_FEATURES_LENNCONF_Pos)))\r
+#define SPI_FEATURES_EXTDEC (0x1u << 16) /**< \brief (SPI_FEATURES) External Decoder is True */\r
+#define SPI_FEATURES_CSNAATIMPL (0x1u << 17) /**< \brief (SPI_FEATURES) CSNAAT Features are Implemented */\r
+#define SPI_FEATURES_BRPBHSB (0x1u << 18) /**< \brief (SPI_FEATURES) Bridge Type is PB to HSB */\r
+#define SPI_FEATURES_FIFORIMPL (0x1u << 19) /**< \brief (SPI_FEATURES) FIFO in Reception is Implemented */\r
+#define SPI_FEATURES_SWPIMPL (0x1u << 20) /**< \brief (SPI_FEATURES) Spurious Write Protection is Implemented */\r
+/* -------- SPI_VERSION : (SPI Offset: 0xFC) Version Register -------- */\r
+#define SPI_VERSION_VERSION_Pos 0\r
+#define SPI_VERSION_VERSION_Msk (0xFFFu << SPI_VERSION_VERSION_Pos) /**< \brief (SPI_VERSION) Version */\r
+#define SPI_VERSION_VERSION(value) ((SPI_VERSION_VERSION_Msk & ((value) << SPI_VERSION_VERSION_Pos)))\r
+#define SPI_VERSION_MFN_Pos 16\r
+#define SPI_VERSION_MFN_Msk (0x7u << SPI_VERSION_MFN_Pos) /**< \brief (SPI_VERSION) mfn */\r
+#define SPI_VERSION_MFN(value) ((SPI_VERSION_MFN_Msk & ((value) << SPI_VERSION_MFN_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR TC */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_TC Timer/Counter */\r
+/*@{*/\r
+\r
+#define REV_TC 0x402\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief TcChannel hardware registers */\r
+typedef struct {\r
+ WoReg TC_CCR; /**< \brief (TcChannel Offset: 0x00) Channel Control Register Channel 0 */\r
+ RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x04) Channel Mode Register Channel 0 */\r
+ RwReg TC_SMC; /**< \brief (TcChannel Offset: 0x08) Stepper Motor Mode Register */\r
+ RoReg Reserved1[1];\r
+ RoReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value Channel 0 */\r
+ RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A Channel 0 */\r
+ RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B Channel 0 */\r
+ RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C Channel 0 */\r
+ RoReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register Channel 0 */\r
+ WoReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register Channel 0 */\r
+ WoReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register Channel 0 */\r
+ RoReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register Channel 0 */\r
+ RoReg Reserved2[4];\r
+} TcChannel;\r
+/** \brief TC hardware registers */\r
+typedef struct {\r
+ TcChannel TC_CHANNEL[3]; /**< \brief (TC Offset: 0x00) TcChannel groups */\r
+ WoReg TC_BCR; /**< \brief (TC Offset: 0xC0) TC Block Control Register */\r
+ RwReg TC_BMR; /**< \brief (TC Offset: 0xC4) TC Block Mode Register */\r
+ RoReg Reserved1[7];\r
+ RwReg TC_WPMR; /**< \brief (TC Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg Reserved2[4];\r
+ RoReg TC_FEATURES; /**< \brief (TC Offset: 0xF8) Features Register */\r
+ RoReg TC_VERSION; /**< \brief (TC Offset: 0xFC) Version Register */\r
+} Tc;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- TC_CCR : (TC Offset: 0x00) Channel Channel Control Register Channel 0 -------- */\r
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */\r
+#define TC_CCR_CLKEN_0 (0x0u << 0) /**< \brief (TC_CCR) No effect. */\r
+#define TC_CCR_CLKEN_1 (0x1u << 0) /**< \brief (TC_CCR) Enables the clock if CLKDIS is not 1. */\r
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */\r
+#define TC_CCR_CLKDIS_0 (0x0u << 1) /**< \brief (TC_CCR) No effect. */\r
+#define TC_CCR_CLKDIS_1 (0x1u << 1) /**< \brief (TC_CCR) Disables the clock. */\r
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */\r
+#define TC_CCR_SWTRG_0 (0x0u << 2) /**< \brief (TC_CCR) No effect. */\r
+#define TC_CCR_SWTRG_1 (0x1u << 2) /**< \brief (TC_CCR) A software trigger is performed:the counter is reset and clock is started. */\r
+/* -------- TC_CAPTURE_CMR : (TC Offset: 0x04) Channel Channel Mode Register Channel 0 -------- */\r
+#define TC_CAPTURE_CMR_TCCLKS_Pos 0\r
+#define TC_CAPTURE_CMR_TCCLKS_Msk (0x7u << TC_CAPTURE_CMR_TCCLKS_Pos) /**< \brief (TC_CAPTURE_CMR) Clock Selection */\r
+#define TC_CAPTURE_CMR_TCCLKS(value) ((TC_CAPTURE_CMR_TCCLKS_Msk & ((value) << TC_CAPTURE_CMR_TCCLKS_Pos)))\r
+#define TC_CAPTURE_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CAPTURE_CMR) TIMER_CLOCK1 */\r
+#define TC_CAPTURE_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CAPTURE_CMR) TIMER_CLOCK2 */\r
+#define TC_CAPTURE_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CAPTURE_CMR) TIMER_CLOCK3 */\r
+#define TC_CAPTURE_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CAPTURE_CMR) TIMER_CLOCK4 */\r
+#define TC_CAPTURE_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CAPTURE_CMR) TIMER_CLOCK5 */\r
+#define TC_CAPTURE_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CAPTURE_CMR) XC0 */\r
+#define TC_CAPTURE_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CAPTURE_CMR) XC1 */\r
+#define TC_CAPTURE_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CAPTURE_CMR) XC2 */\r
+#define TC_CAPTURE_CMR_CLKI (0x1u << 3) /**< \brief (TC_CAPTURE_CMR) Clock Invert */\r
+#define TC_CAPTURE_CMR_CLKI_0 (0x0u << 3) /**< \brief (TC_CAPTURE_CMR) Counter is incremented on rising edge of the clock. */\r
+#define TC_CAPTURE_CMR_CLKI_1 (0x1u << 3) /**< \brief (TC_CAPTURE_CMR) Counter is incremented on falling edge of the clock. */\r
+#define TC_CAPTURE_CMR_BURST_Pos 4\r
+#define TC_CAPTURE_CMR_BURST_Msk (0x3u << TC_CAPTURE_CMR_BURST_Pos) /**< \brief (TC_CAPTURE_CMR) Burst Signal Selection */\r
+#define TC_CAPTURE_CMR_BURST(value) ((TC_CAPTURE_CMR_BURST_Msk & ((value) << TC_CAPTURE_CMR_BURST_Pos)))\r
+#define TC_CAPTURE_CMR_BURST_NOT_GATED (0x0u << 4) /**< \brief (TC_CAPTURE_CMR) The clock is not gated by an external signal. */\r
+#define TC_CAPTURE_CMR_BURST_CLK_AND_XC0 (0x1u << 4) /**< \brief (TC_CAPTURE_CMR) XC0 is ANDed with the selected clock. */\r
+#define TC_CAPTURE_CMR_BURST_CLK_AND_XC1 (0x2u << 4) /**< \brief (TC_CAPTURE_CMR) XC1 is ANDed with the selected clock. */\r
+#define TC_CAPTURE_CMR_BURST_CLK_AND_XC2 (0x3u << 4) /**< \brief (TC_CAPTURE_CMR) XC2 is ANDed with the selected clock. */\r
+#define TC_CAPTURE_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CAPTURE_CMR) Counter Clock Stopped with RB Loading */\r
+#define TC_CAPTURE_CMR_LDBSTOP_0 (0x0u << 6) /**< \brief (TC_CAPTURE_CMR) Counter clock is not stopped when RB loading occurs. */\r
+#define TC_CAPTURE_CMR_LDBSTOP_1 (0x1u << 6) /**< \brief (TC_CAPTURE_CMR) Counter clock is stopped when RB loading occurs. */\r
+#define TC_CAPTURE_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CAPTURE_CMR) Counter Clock Disable with RB Loading */\r
+#define TC_CAPTURE_CMR_LDBDIS_0 (0x0u << 7) /**< \brief (TC_CAPTURE_CMR) Counter clock is not disabled when RB loading occurs. */\r
+#define TC_CAPTURE_CMR_LDBDIS_1 (0x1u << 7) /**< \brief (TC_CAPTURE_CMR) Counter clock is disabled when RB loading occurs. */\r
+#define TC_CAPTURE_CMR_ETRGEDG_Pos 8\r
+#define TC_CAPTURE_CMR_ETRGEDG_Msk (0x3u << TC_CAPTURE_CMR_ETRGEDG_Pos) /**< \brief (TC_CAPTURE_CMR) External Trigger Edge Selection */\r
+#define TC_CAPTURE_CMR_ETRGEDG(value) ((TC_CAPTURE_CMR_ETRGEDG_Msk & ((value) << TC_CAPTURE_CMR_ETRGEDG_Pos)))\r
+#define TC_CAPTURE_CMR_ETRGEDG_NO_EDGE (0x0u << 8) /**< \brief (TC_CAPTURE_CMR) none */\r
+#define TC_CAPTURE_CMR_ETRGEDG_POS_EDGE (0x1u << 8) /**< \brief (TC_CAPTURE_CMR) rising edge */\r
+#define TC_CAPTURE_CMR_ETRGEDG_NEG_EDGE (0x2u << 8) /**< \brief (TC_CAPTURE_CMR) falling edge */\r
+#define TC_CAPTURE_CMR_ETRGEDG_BOTH_EDGES (0x3u << 8) /**< \brief (TC_CAPTURE_CMR) each edge */\r
+#define TC_CAPTURE_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CAPTURE_CMR) TIOA or TIOB External Trigger Selection */\r
+#define TC_CAPTURE_CMR_ABETRG_0 (0x0u << 10) /**< \brief (TC_CAPTURE_CMR) TIOB is used as an external trigger. */\r
+#define TC_CAPTURE_CMR_ABETRG_1 (0x1u << 10) /**< \brief (TC_CAPTURE_CMR) TIOA is used as an external trigger. */\r
+#define TC_CAPTURE_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CAPTURE_CMR) RC Compare Trigger Enable */\r
+#define TC_CAPTURE_CMR_CPCTRG_0 (0x0u << 14) /**< \brief (TC_CAPTURE_CMR) RC Compare has no effect on the counter and its clock. */\r
+#define TC_CAPTURE_CMR_CPCTRG_1 (0x1u << 14) /**< \brief (TC_CAPTURE_CMR) RC Compare resets the counter and starts the counter clock. */\r
+#define TC_CAPTURE_CMR_WAVE (0x1u << 15) /**< \brief (TC_CAPTURE_CMR) Wave */\r
+#define TC_CAPTURE_CMR_WAVE_0 (0x0u << 15) /**< \brief (TC_CAPTURE_CMR) Capture Mode is enabled. */\r
+#define TC_CAPTURE_CMR_WAVE_1 (0x1u << 15) /**< \brief (TC_CAPTURE_CMR) Capture Mode is disabled (Waveform Mode is enabled). */\r
+#define TC_CAPTURE_CMR_LDRA_Pos 16\r
+#define TC_CAPTURE_CMR_LDRA_Msk (0x3u << TC_CAPTURE_CMR_LDRA_Pos) /**< \brief (TC_CAPTURE_CMR) RA Loading Selection */\r
+#define TC_CAPTURE_CMR_LDRA(value) ((TC_CAPTURE_CMR_LDRA_Msk & ((value) << TC_CAPTURE_CMR_LDRA_Pos)))\r
+#define TC_CAPTURE_CMR_LDRA_NO_EDGE (0x0u << 16) /**< \brief (TC_CAPTURE_CMR) none */\r
+#define TC_CAPTURE_CMR_LDRA_POS_EDGE_TIOA (0x1u << 16) /**< \brief (TC_CAPTURE_CMR) rising edge of TIOA */\r
+#define TC_CAPTURE_CMR_LDRA_NEG_EDGE_TIOA (0x2u << 16) /**< \brief (TC_CAPTURE_CMR) falling edge of TIOA */\r
+#define TC_CAPTURE_CMR_LDRA_BIOTH_EDGES_TIOA (0x3u << 16) /**< \brief (TC_CAPTURE_CMR) each edge of TIOA */\r
+#define TC_CAPTURE_CMR_LDRB_Pos 18\r
+#define TC_CAPTURE_CMR_LDRB_Msk (0x3u << TC_CAPTURE_CMR_LDRB_Pos) /**< \brief (TC_CAPTURE_CMR) RB Loading Selection */\r
+#define TC_CAPTURE_CMR_LDRB(value) ((TC_CAPTURE_CMR_LDRB_Msk & ((value) << TC_CAPTURE_CMR_LDRB_Pos)))\r
+#define TC_CAPTURE_CMR_LDRB_NO_EDGE (0x0u << 18) /**< \brief (TC_CAPTURE_CMR) none */\r
+#define TC_CAPTURE_CMR_LDRB_POS_EDGE_TIOA (0x1u << 18) /**< \brief (TC_CAPTURE_CMR) rising edge of TIOA */\r
+#define TC_CAPTURE_CMR_LDRB_NEG_EDGE_TIOA (0x2u << 18) /**< \brief (TC_CAPTURE_CMR) falling edge of TIOA */\r
+#define TC_CAPTURE_CMR_LDRB_BIOTH_EDGES_TIOA (0x3u << 18) /**< \brief (TC_CAPTURE_CMR) each edge of TIOA */\r
+/* -------- TC_WAVEFORM_CMR : (TC Offset: 0x04) Channel Channel Mode Register Channel 0 -------- */\r
+#define TC_WAVEFORM_CMR_TCCLKS_Pos 0\r
+#define TC_WAVEFORM_CMR_TCCLKS_Msk (0x7u << TC_WAVEFORM_CMR_TCCLKS_Pos) /**< \brief (TC_WAVEFORM_CMR) Clock Selection */\r
+#define TC_WAVEFORM_CMR_TCCLKS(value) ((TC_WAVEFORM_CMR_TCCLKS_Msk & ((value) << TC_WAVEFORM_CMR_TCCLKS_Pos)))\r
+#define TC_WAVEFORM_CMR_TCCLKS_TIMER_DIV1_CLOCK (0x0u << 0) /**< \brief (TC_WAVEFORM_CMR) TIMER_DIV1_CLOCK */\r
+#define TC_WAVEFORM_CMR_TCCLKS_TIMER_DIV2_CLOCK (0x1u << 0) /**< \brief (TC_WAVEFORM_CMR) TIMER_DIV2_CLOCK */\r
+#define TC_WAVEFORM_CMR_TCCLKS_TIMER_DIV3_CLOCK (0x2u << 0) /**< \brief (TC_WAVEFORM_CMR) TIMER_DIV3_CLOCK */\r
+#define TC_WAVEFORM_CMR_TCCLKS_TIMER_DIV4_CLOCK (0x3u << 0) /**< \brief (TC_WAVEFORM_CMR) TIMER_DIV4_CLOCK */\r
+#define TC_WAVEFORM_CMR_TCCLKS_TIMER_DIV5_CLOCK (0x4u << 0) /**< \brief (TC_WAVEFORM_CMR) TIMER_DIV5_CLOCK */\r
+#define TC_WAVEFORM_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_WAVEFORM_CMR) XC0 */\r
+#define TC_WAVEFORM_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_WAVEFORM_CMR) XC1 */\r
+#define TC_WAVEFORM_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_WAVEFORM_CMR) XC2 */\r
+#define TC_WAVEFORM_CMR_CLKI (0x1u << 3) /**< \brief (TC_WAVEFORM_CMR) Clock Invert */\r
+#define TC_WAVEFORM_CMR_CLKI_0 (0x0u << 3) /**< \brief (TC_WAVEFORM_CMR) Counter is incremented on rising edge of the clock. */\r
+#define TC_WAVEFORM_CMR_CLKI_1 (0x1u << 3) /**< \brief (TC_WAVEFORM_CMR) Counter is incremented on falling edge of the clock. */\r
+#define TC_WAVEFORM_CMR_BURST_Pos 4\r
+#define TC_WAVEFORM_CMR_BURST_Msk (0x3u << TC_WAVEFORM_CMR_BURST_Pos) /**< \brief (TC_WAVEFORM_CMR) Burst Signal Selection */\r
+#define TC_WAVEFORM_CMR_BURST(value) ((TC_WAVEFORM_CMR_BURST_Msk & ((value) << TC_WAVEFORM_CMR_BURST_Pos)))\r
+#define TC_WAVEFORM_CMR_BURST_NOT_GATED (0x0u << 4) /**< \brief (TC_WAVEFORM_CMR) The clock is not gated by an external signal. */\r
+#define TC_WAVEFORM_CMR_BURST_CLK_AND_XC0 (0x1u << 4) /**< \brief (TC_WAVEFORM_CMR) XC0 is ANDed with the selected clock. */\r
+#define TC_WAVEFORM_CMR_BURST_CLK_AND_XC1 (0x2u << 4) /**< \brief (TC_WAVEFORM_CMR) XC1 is ANDed with the selected clock. */\r
+#define TC_WAVEFORM_CMR_BURST_CLK_AND_XC2 (0x3u << 4) /**< \brief (TC_WAVEFORM_CMR) XC2 is ANDed with the selected clock. */\r
+#define TC_WAVEFORM_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_WAVEFORM_CMR) Counter Clock Stopped with RC Compare */\r
+#define TC_WAVEFORM_CMR_CPCSTOP_0 (0x0u << 6) /**< \brief (TC_WAVEFORM_CMR) Counter clock is not stopped when counter reaches RC. */\r
+#define TC_WAVEFORM_CMR_CPCSTOP_1 (0x1u << 6) /**< \brief (TC_WAVEFORM_CMR) Counter clock is stopped when counter reaches RC. */\r
+#define TC_WAVEFORM_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_WAVEFORM_CMR) Counter Clock Disable with RC Compare */\r
+#define TC_WAVEFORM_CMR_CPCDIS_0 (0x0u << 7) /**< \brief (TC_WAVEFORM_CMR) Counter clock is not disabled when counter reaches RC. */\r
+#define TC_WAVEFORM_CMR_CPCDIS_1 (0x1u << 7) /**< \brief (TC_WAVEFORM_CMR) Counter clock is disabled when counter reaches RC. */\r
+#define TC_WAVEFORM_CMR_EEVTEDG_Pos 8\r
+#define TC_WAVEFORM_CMR_EEVTEDG_Msk (0x3u << TC_WAVEFORM_CMR_EEVTEDG_Pos) /**< \brief (TC_WAVEFORM_CMR) External Event Edge Selection */\r
+#define TC_WAVEFORM_CMR_EEVTEDG(value) ((TC_WAVEFORM_CMR_EEVTEDG_Msk & ((value) << TC_WAVEFORM_CMR_EEVTEDG_Pos)))\r
+#define TC_WAVEFORM_CMR_EEVTEDG_NO_EDGE (0x0u << 8) /**< \brief (TC_WAVEFORM_CMR) none */\r
+#define TC_WAVEFORM_CMR_EEVTEDG_POS_EDGE (0x1u << 8) /**< \brief (TC_WAVEFORM_CMR) rising edge */\r
+#define TC_WAVEFORM_CMR_EEVTEDG_NEG_EDGE (0x2u << 8) /**< \brief (TC_WAVEFORM_CMR) falling edge */\r
+#define TC_WAVEFORM_CMR_EEVTEDG_BOTH_EDGES (0x3u << 8) /**< \brief (TC_WAVEFORM_CMR) each edge */\r
+#define TC_WAVEFORM_CMR_EEVT_Pos 10\r
+#define TC_WAVEFORM_CMR_EEVT_Msk (0x3u << TC_WAVEFORM_CMR_EEVT_Pos) /**< \brief (TC_WAVEFORM_CMR) External Event Selection */\r
+#define TC_WAVEFORM_CMR_EEVT(value) ((TC_WAVEFORM_CMR_EEVT_Msk & ((value) << TC_WAVEFORM_CMR_EEVT_Pos)))\r
+#define TC_WAVEFORM_CMR_EEVT_TIOB_INPUT (0x0u << 10) /**< \brief (TC_WAVEFORM_CMR) TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. */\r
+#define TC_WAVEFORM_CMR_EEVT_XC0_OUTPUT (0x1u << 10) /**< \brief (TC_WAVEFORM_CMR) XC0 output */\r
+#define TC_WAVEFORM_CMR_EEVT_XC1_OUTPUT (0x2u << 10) /**< \brief (TC_WAVEFORM_CMR) XC1 output */\r
+#define TC_WAVEFORM_CMR_EEVT_XC2_OUTPUT (0x3u << 10) /**< \brief (TC_WAVEFORM_CMR) XC2 output */\r
+#define TC_WAVEFORM_CMR_ENETRG (0x1u << 12) /**< \brief (TC_WAVEFORM_CMR) External Event Trigger Enable */\r
+#define TC_WAVEFORM_CMR_ENETRG_0 (0x0u << 12) /**< \brief (TC_WAVEFORM_CMR) The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. */\r
+#define TC_WAVEFORM_CMR_ENETRG_1 (0x1u << 12) /**< \brief (TC_WAVEFORM_CMR) The external event resets the counter and starts the counter clock. */\r
+#define TC_WAVEFORM_CMR_WAVSEL_Pos 13\r
+#define TC_WAVEFORM_CMR_WAVSEL_Msk (0x3u << TC_WAVEFORM_CMR_WAVSEL_Pos) /**< \brief (TC_WAVEFORM_CMR) Waveform Selection */\r
+#define TC_WAVEFORM_CMR_WAVSEL(value) ((TC_WAVEFORM_CMR_WAVSEL_Msk & ((value) << TC_WAVEFORM_CMR_WAVSEL_Pos)))\r
+#define TC_WAVEFORM_CMR_WAVSEL_UP_NO_AUTO (0x0u << 13) /**< \brief (TC_WAVEFORM_CMR) UP mode without automatic trigger on RC Compare */\r
+#define TC_WAVEFORM_CMR_WAVSEL_UPDOWN_NO_AUTO (0x1u << 13) /**< \brief (TC_WAVEFORM_CMR) UPDOWN mode without automatic trigger on RC Compare */\r
+#define TC_WAVEFORM_CMR_WAVSEL_UP_AUTO (0x2u << 13) /**< \brief (TC_WAVEFORM_CMR) UP mode with automatic trigger on RC Compare */\r
+#define TC_WAVEFORM_CMR_WAVSEL_UPDOWN_AUTO (0x3u << 13) /**< \brief (TC_WAVEFORM_CMR) UPDOWN mode with automatic trigger on RC Compare */\r
+#define TC_WAVEFORM_CMR_WAVE (0x1u << 15) /**< \brief (TC_WAVEFORM_CMR) WAVE */\r
+#define TC_WAVEFORM_CMR_WAVE_0 (0x0u << 15) /**< \brief (TC_WAVEFORM_CMR) Waveform Mode is disabled (Capture Mode is enabled). */\r
+#define TC_WAVEFORM_CMR_WAVE_1 (0x1u << 15) /**< \brief (TC_WAVEFORM_CMR) Waveform Mode is enabled. */\r
+#define TC_WAVEFORM_CMR_ACPA_Pos 16\r
+#define TC_WAVEFORM_CMR_ACPA_Msk (0x3u << TC_WAVEFORM_CMR_ACPA_Pos) /**< \brief (TC_WAVEFORM_CMR) RA Compare Effect on TIOA */\r
+#define TC_WAVEFORM_CMR_ACPA(value) ((TC_WAVEFORM_CMR_ACPA_Msk & ((value) << TC_WAVEFORM_CMR_ACPA_Pos)))\r
+#define TC_WAVEFORM_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_WAVEFORM_CMR) none */\r
+#define TC_WAVEFORM_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_WAVEFORM_CMR) set */\r
+#define TC_WAVEFORM_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_WAVEFORM_CMR) clear */\r
+#define TC_WAVEFORM_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_WAVEFORM_CMR) toggle */\r
+#define TC_WAVEFORM_CMR_ACPC_Pos 18\r
+#define TC_WAVEFORM_CMR_ACPC_Msk (0x3u << TC_WAVEFORM_CMR_ACPC_Pos) /**< \brief (TC_WAVEFORM_CMR) RC Compare Effect on TIOA */\r
+#define TC_WAVEFORM_CMR_ACPC(value) ((TC_WAVEFORM_CMR_ACPC_Msk & ((value) << TC_WAVEFORM_CMR_ACPC_Pos)))\r
+#define TC_WAVEFORM_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_WAVEFORM_CMR) none */\r
+#define TC_WAVEFORM_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_WAVEFORM_CMR) set */\r
+#define TC_WAVEFORM_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_WAVEFORM_CMR) clear */\r
+#define TC_WAVEFORM_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_WAVEFORM_CMR) toggle */\r
+#define TC_WAVEFORM_CMR_AEEVT_Pos 20\r
+#define TC_WAVEFORM_CMR_AEEVT_Msk (0x3u << TC_WAVEFORM_CMR_AEEVT_Pos) /**< \brief (TC_WAVEFORM_CMR) External Event Effect on TIOA */\r
+#define TC_WAVEFORM_CMR_AEEVT(value) ((TC_WAVEFORM_CMR_AEEVT_Msk & ((value) << TC_WAVEFORM_CMR_AEEVT_Pos)))\r
+#define TC_WAVEFORM_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_WAVEFORM_CMR) none */\r
+#define TC_WAVEFORM_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_WAVEFORM_CMR) set */\r
+#define TC_WAVEFORM_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_WAVEFORM_CMR) clear */\r
+#define TC_WAVEFORM_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_WAVEFORM_CMR) toggle */\r
+#define TC_WAVEFORM_CMR_ASWTRG_Pos 22\r
+#define TC_WAVEFORM_CMR_ASWTRG_Msk (0x3u << TC_WAVEFORM_CMR_ASWTRG_Pos) /**< \brief (TC_WAVEFORM_CMR) Software Trigger Effect on TIOA */\r
+#define TC_WAVEFORM_CMR_ASWTRG(value) ((TC_WAVEFORM_CMR_ASWTRG_Msk & ((value) << TC_WAVEFORM_CMR_ASWTRG_Pos)))\r
+#define TC_WAVEFORM_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_WAVEFORM_CMR) none */\r
+#define TC_WAVEFORM_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_WAVEFORM_CMR) set */\r
+#define TC_WAVEFORM_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_WAVEFORM_CMR) clear */\r
+#define TC_WAVEFORM_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_WAVEFORM_CMR) toggle */\r
+#define TC_WAVEFORM_CMR_BCPB_Pos 24\r
+#define TC_WAVEFORM_CMR_BCPB_Msk (0x3u << TC_WAVEFORM_CMR_BCPB_Pos) /**< \brief (TC_WAVEFORM_CMR) RB Compare Effect on TIOB */\r
+#define TC_WAVEFORM_CMR_BCPB(value) ((TC_WAVEFORM_CMR_BCPB_Msk & ((value) << TC_WAVEFORM_CMR_BCPB_Pos)))\r
+#define TC_WAVEFORM_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_WAVEFORM_CMR) none */\r
+#define TC_WAVEFORM_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_WAVEFORM_CMR) set */\r
+#define TC_WAVEFORM_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_WAVEFORM_CMR) clear */\r
+#define TC_WAVEFORM_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_WAVEFORM_CMR) toggle */\r
+#define TC_WAVEFORM_CMR_BCPC_Pos 26\r
+#define TC_WAVEFORM_CMR_BCPC_Msk (0x3u << TC_WAVEFORM_CMR_BCPC_Pos) /**< \brief (TC_WAVEFORM_CMR) RC Compare Effect on TIOB */\r
+#define TC_WAVEFORM_CMR_BCPC(value) ((TC_WAVEFORM_CMR_BCPC_Msk & ((value) << TC_WAVEFORM_CMR_BCPC_Pos)))\r
+#define TC_WAVEFORM_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_WAVEFORM_CMR) none */\r
+#define TC_WAVEFORM_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_WAVEFORM_CMR) set */\r
+#define TC_WAVEFORM_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_WAVEFORM_CMR) clear */\r
+#define TC_WAVEFORM_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_WAVEFORM_CMR) toggle */\r
+#define TC_WAVEFORM_CMR_BEEVT_Pos 28\r
+#define TC_WAVEFORM_CMR_BEEVT_Msk (0x3u << TC_WAVEFORM_CMR_BEEVT_Pos) /**< \brief (TC_WAVEFORM_CMR) External Event Effect on TIOB */\r
+#define TC_WAVEFORM_CMR_BEEVT(value) ((TC_WAVEFORM_CMR_BEEVT_Msk & ((value) << TC_WAVEFORM_CMR_BEEVT_Pos)))\r
+#define TC_WAVEFORM_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_WAVEFORM_CMR) none */\r
+#define TC_WAVEFORM_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_WAVEFORM_CMR) set */\r
+#define TC_WAVEFORM_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_WAVEFORM_CMR) clear */\r
+#define TC_WAVEFORM_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_WAVEFORM_CMR) toggle */\r
+#define TC_WAVEFORM_CMR_BSWTRG_Pos 30\r
+#define TC_WAVEFORM_CMR_BSWTRG_Msk (0x3u << TC_WAVEFORM_CMR_BSWTRG_Pos) /**< \brief (TC_WAVEFORM_CMR) Software Trigger Effect on TIOB */\r
+#define TC_WAVEFORM_CMR_BSWTRG(value) ((TC_WAVEFORM_CMR_BSWTRG_Msk & ((value) << TC_WAVEFORM_CMR_BSWTRG_Pos)))\r
+#define TC_WAVEFORM_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_WAVEFORM_CMR) none */\r
+#define TC_WAVEFORM_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_WAVEFORM_CMR) set */\r
+#define TC_WAVEFORM_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_WAVEFORM_CMR) clear */\r
+#define TC_WAVEFORM_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_WAVEFORM_CMR) toggle */\r
+/* -------- TC_CMR : (TC Offset: 0x04) Channel Channel Mode Register Channel 0 -------- */\r
+#define TC_CMR_TCCLKS_Pos 0\r
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */\r
+#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)))\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) TIMER_CLOCK1 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) TIMER_CLOCK2 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) TIMER_CLOCK3 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) TIMER_CLOCK4 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) TIMER_CLOCK5 */\r
+#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) XC0 */\r
+#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) XC1 */\r
+#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) XC2 */\r
+#define TC_CMR_TCCLKS_TIMER_DIV1_CLOCK (0x0u << 0) /**< \brief (TC_CMR) TIMER_DIV1_CLOCK */\r
+#define TC_CMR_TCCLKS_TIMER_DIV2_CLOCK (0x1u << 0) /**< \brief (TC_CMR) TIMER_DIV2_CLOCK */\r
+#define TC_CMR_TCCLKS_TIMER_DIV3_CLOCK (0x2u << 0) /**< \brief (TC_CMR) TIMER_DIV3_CLOCK */\r
+#define TC_CMR_TCCLKS_TIMER_DIV4_CLOCK (0x3u << 0) /**< \brief (TC_CMR) TIMER_DIV4_CLOCK */\r
+#define TC_CMR_TCCLKS_TIMER_DIV5_CLOCK (0x4u << 0) /**< \brief (TC_CMR) TIMER_DIV5_CLOCK */\r
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */\r
+#define TC_CMR_BURST_Pos 4\r
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */\r
+#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)))\r
+#define TC_CMR_BURST_NOT_GATED (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_BURST_CLK_AND_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_CLK_AND_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_CLK_AND_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */\r
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */\r
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */\r
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */\r
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */\r
+#define TC_CMR_ETRGEDG_Pos 8\r
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */\r
+#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)))\r
+#define TC_CMR_ETRGEDG_NO_EDGE (0x0u << 8) /**< \brief (TC_CMR) none */\r
+#define TC_CMR_ETRGEDG_POS_EDGE (0x1u << 8) /**< \brief (TC_CMR) rising edge */\r
+#define TC_CMR_ETRGEDG_NEG_EDGE (0x2u << 8) /**< \brief (TC_CMR) falling edge */\r
+#define TC_CMR_ETRGEDG_BOTH_EDGES (0x3u << 8) /**< \brief (TC_CMR) each edge */\r
+#define TC_CMR_EEVTEDG_Pos 8\r
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */\r
+#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos)))\r
+#define TC_CMR_EEVTEDG_NO_EDGE (0x0u << 8) /**< \brief (TC_CMR) none */\r
+#define TC_CMR_EEVTEDG_POS_EDGE (0x1u << 8) /**< \brief (TC_CMR) rising edge */\r
+#define TC_CMR_EEVTEDG_NEG_EDGE (0x2u << 8) /**< \brief (TC_CMR) falling edge */\r
+#define TC_CMR_EEVTEDG_BOTH_EDGES (0x3u << 8) /**< \brief (TC_CMR) each edge */\r
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */\r
+#define TC_CMR_EEVT_TIOB_INPUT (0x0u << 10) /**< \brief (TC_CMR) TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. */\r
+#define TC_CMR_EEVT_XC0_OUTPUT (0x1u << 10) /**< \brief (TC_CMR) XC0 output */\r
+#define TC_CMR_EEVT_XC1_OUTPUT (0x2u << 10) /**< \brief (TC_CMR) XC1 output */\r
+#define TC_CMR_EEVT_XC2_OUTPUT (0x3u << 10) /**< \brief (TC_CMR) XC2 output */\r
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */\r
+#define TC_CMR_WAVSEL_Pos 13\r
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */\r
+#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos)))\r
+#define TC_CMR_WAVSEL_UP_NO_AUTO (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN_NO_AUTO (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UP_AUTO (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN_AUTO (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */\r
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */\r
+#define TC_CMR_ACPA_Pos 16\r
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */\r
+#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos)))\r
+#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) none */\r
+#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) set */\r
+#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) clear */\r
+#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) toggle */\r
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Wave */\r
+#define TC_CMR_LDRA_Pos 16\r
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Selection */\r
+#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)))\r
+#define TC_CMR_LDRA_NO_EDGE (0x0u << 16) /**< \brief (TC_CMR) none */\r
+#define TC_CMR_LDRA_POS_EDGE_TIOA (0x1u << 16) /**< \brief (TC_CMR) rising edge of TIOA */\r
+#define TC_CMR_LDRA_NEG_EDGE_TIOA (0x2u << 16) /**< \brief (TC_CMR) falling edge of TIOA */\r
+#define TC_CMR_LDRA_BIOTH_EDGES_TIOA (0x3u << 16) /**< \brief (TC_CMR) each edge of TIOA */\r
+#define TC_CMR_ACPC_Pos 18\r
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */\r
+#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos)))\r
+#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) none */\r
+#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) set */\r
+#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) clear */\r
+#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) toggle */\r
+#define TC_CMR_LDRB_Pos 18\r
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Selection */\r
+#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)))\r
+#define TC_CMR_LDRB_NO_EDGE (0x0u << 18) /**< \brief (TC_CMR) none */\r
+#define TC_CMR_LDRB_POS_EDGE_TIOA (0x1u << 18) /**< \brief (TC_CMR) rising edge of TIOA */\r
+#define TC_CMR_LDRB_NEG_EDGE_TIOA (0x2u << 18) /**< \brief (TC_CMR) falling edge of TIOA */\r
+#define TC_CMR_LDRB_BIOTH_EDGES_TIOA (0x3u << 18) /**< \brief (TC_CMR) each edge of TIOA */\r
+#define TC_CMR_AEEVT_Pos 20\r
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */\r
+#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos)))\r
+#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) none */\r
+#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) set */\r
+#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) clear */\r
+#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) toggle */\r
+#define TC_CMR_ASWTRG_Pos 22\r
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */\r
+#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos)))\r
+#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) none */\r
+#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) set */\r
+#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) clear */\r
+#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) toggle */\r
+#define TC_CMR_BCPB_Pos 24\r
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */\r
+#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos)))\r
+#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) none */\r
+#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) set */\r
+#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) clear */\r
+#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) toggle */\r
+#define TC_CMR_BCPC_Pos 26\r
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */\r
+#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos)))\r
+#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) none */\r
+#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) set */\r
+#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) clear */\r
+#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) toggle */\r
+#define TC_CMR_BEEVT_Pos 28\r
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */\r
+#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos)))\r
+#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) none */\r
+#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) set */\r
+#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) clear */\r
+#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) toggle */\r
+#define TC_CMR_BSWTRG_Pos 30\r
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */\r
+#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos)))\r
+#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) none */\r
+#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) set */\r
+#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) clear */\r
+#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) toggle */\r
+\r
+/* -------- TC_SMC : (TC Offset: 0x08) Channel Stepper Motor Mode Register -------- */\r
+#define TC_SMC_GCEN (0x1u << 0) /**< \brief (TC_SMC) Gray Count Enable */\r
+#define TC_SMC_DOWN (0x1u << 1) /**< \brief (TC_SMC) Down Count */\r
+/* -------- TC_CV : (TC Offset: 0x10) Channel Counter Value Channel 0 -------- */\r
+#define TC_CV_CV_Pos 0\r
+#define TC_CV_CV_Msk (0xFFFFu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */\r
+#define TC_CV_CV(value) ((TC_CV_CV_Msk & ((value) << TC_CV_CV_Pos)))\r
+/* -------- TC_RA : (TC Offset: 0x14) Channel Register A Channel 0 -------- */\r
+#define TC_RA_RA_Pos 0\r
+#define TC_RA_RA_Msk (0xFFFFu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */\r
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))\r
+/* -------- TC_RB : (TC Offset: 0x18) Channel Register B Channel 0 -------- */\r
+#define TC_RB_RB_Pos 0\r
+#define TC_RB_RB_Msk (0xFFFFu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */\r
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))\r
+/* -------- TC_RC : (TC Offset: 0x1C) Channel Register C Channel 0 -------- */\r
+#define TC_RC_RC_Pos 0\r
+#define TC_RC_RC_Msk (0xFFFFu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */\r
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))\r
+/* -------- TC_SR : (TC Offset: 0x20) Channel Status Register Channel 0 -------- */\r
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */\r
+#define TC_SR_COVFS_0 (0x0u << 0) /**< \brief (TC_SR) No counter overflow has occurred since the last read of the Status Register. */\r
+#define TC_SR_COVFS_1 (0x1u << 0) /**< \brief (TC_SR) A counter overflow has occurred since the last read of the Status Register. */\r
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */\r
+#define TC_SR_LOVRS_0 (0x0u << 1) /**< \brief (TC_SR) Load overrun has not occurred since the last read of the Status Register or WAVE:1. */\r
+#define TC_SR_LOVRS_1 (0x1u << 1) /**< \brief (TC_SR) RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. */\r
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */\r
+#define TC_SR_CPAS_0 (0x0u << 2) /**< \brief (TC_SR) RA Compare has not occurred since the last read of the Status Register or WAVE:0. */\r
+#define TC_SR_CPAS_1 (0x1u << 2) /**< \brief (TC_SR) RA Compare has occurred since the last read of the Status Register, if WAVE:1. */\r
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */\r
+#define TC_SR_CPBS_0 (0x0u << 3) /**< \brief (TC_SR) RB Compare has not occurred since the last read of the Status Register or WAVE:0. */\r
+#define TC_SR_CPBS_1 (0x1u << 3) /**< \brief (TC_SR) RB Compare has occurred since the last read of the Status Register, if WAVE:1. */\r
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */\r
+#define TC_SR_CPCS_0 (0x0u << 4) /**< \brief (TC_SR) RC Compare has not occurred since the last read of the Status Register. */\r
+#define TC_SR_CPCS_1 (0x1u << 4) /**< \brief (TC_SR) RC Compare has occurred since the last read of the Status Register. */\r
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */\r
+#define TC_SR_LDRAS_0 (0x0u << 5) /**< \brief (TC_SR) RA Load has not occurred since the last read of the Status Register or WAVE:1. */\r
+#define TC_SR_LDRAS_1 (0x1u << 5) /**< \brief (TC_SR) RA Load has occurred since the last read of the Status Register, if WAVE:0. */\r
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */\r
+#define TC_SR_LDRBS_0 (0x0u << 6) /**< \brief (TC_SR) RB Load has not occurred since the last read of the Status Register or WAVE:1. */\r
+#define TC_SR_LDRBS_1 (0x1u << 6) /**< \brief (TC_SR) RB Load has occurred since the last read of the Status Register, if WAVE:0. */\r
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */\r
+#define TC_SR_ETRGS_0 (0x0u << 7) /**< \brief (TC_SR) External trigger has not occurred since the last read of the Status Register. */\r
+#define TC_SR_ETRGS_1 (0x1u << 7) /**< \brief (TC_SR) External trigger has occurred since the last read of the Status Register. */\r
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */\r
+#define TC_SR_CLKSTA_0 (0x0u << 16) /**< \brief (TC_SR) Clock is disabled. */\r
+#define TC_SR_CLKSTA_1 (0x1u << 16) /**< \brief (TC_SR) Clock is enabled. */\r
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */\r
+#define TC_SR_MTIOA_0 (0x0u << 17) /**< \brief (TC_SR) TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. */\r
+#define TC_SR_MTIOA_1 (0x1u << 17) /**< \brief (TC_SR) TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. */\r
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */\r
+#define TC_SR_MTIOB_0 (0x0u << 18) /**< \brief (TC_SR) TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. */\r
+#define TC_SR_MTIOB_1 (0x1u << 18) /**< \brief (TC_SR) TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. */\r
+/* -------- TC_IER : (TC Offset: 0x24) Channel Interrupt Enable Register Channel 0 -------- */\r
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */\r
+#define TC_IER_COVFS_0 (0x0u << 0) /**< \brief (TC_IER) No effect. */\r
+#define TC_IER_COVFS_1 (0x1u << 0) /**< \brief (TC_IER) Enables the Counter Overflow Interrupt. */\r
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */\r
+#define TC_IER_LOVRS_0 (0x0u << 1) /**< \brief (TC_IER) No effect. */\r
+#define TC_IER_LOVRS_1 (0x1u << 1) /**< \brief (TC_IER) Enables the Load Overrun Interrupt. */\r
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */\r
+#define TC_IER_CPAS_0 (0x0u << 2) /**< \brief (TC_IER) No effect. */\r
+#define TC_IER_CPAS_1 (0x1u << 2) /**< \brief (TC_IER) Enables the RA Compare Interrupt. */\r
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */\r
+#define TC_IER_CPBS_0 (0x0u << 3) /**< \brief (TC_IER) No effect. */\r
+#define TC_IER_CPBS_1 (0x1u << 3) /**< \brief (TC_IER) Enables the RB Compare Interrupt. */\r
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */\r
+#define TC_IER_CPCS_0 (0x0u << 4) /**< \brief (TC_IER) No effect. */\r
+#define TC_IER_CPCS_1 (0x1u << 4) /**< \brief (TC_IER) Enables the RC Compare Interrupt. */\r
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */\r
+#define TC_IER_LDRAS_0 (0x0u << 5) /**< \brief (TC_IER) No effect. */\r
+#define TC_IER_LDRAS_1 (0x1u << 5) /**< \brief (TC_IER) Enables the RA Load Interrupt. */\r
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */\r
+#define TC_IER_LDRBS_0 (0x0u << 6) /**< \brief (TC_IER) No effect. */\r
+#define TC_IER_LDRBS_1 (0x1u << 6) /**< \brief (TC_IER) Enables the RB Load Interrupt. */\r
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */\r
+#define TC_IER_ETRGS_0 (0x0u << 7) /**< \brief (TC_IER) No effect. */\r
+#define TC_IER_ETRGS_1 (0x1u << 7) /**< \brief (TC_IER) Enables the External Trigger Interrupt. */\r
+/* -------- TC_IDR : (TC Offset: 0x28) Channel Interrupt Disable Register Channel 0 -------- */\r
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */\r
+#define TC_IDR_COVFS_0 (0x0u << 0) /**< \brief (TC_IDR) No effect. */\r
+#define TC_IDR_COVFS_1 (0x1u << 0) /**< \brief (TC_IDR) Disables the Counter Overflow Interrupt. */\r
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */\r
+#define TC_IDR_LOVRS_0 (0x0u << 1) /**< \brief (TC_IDR) No effect. */\r
+#define TC_IDR_LOVRS_1 (0x1u << 1) /**< \brief (TC_IDR) Disables the Load Overrun Interrupt (if WAVE:0). */\r
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */\r
+#define TC_IDR_CPAS_0 (0x0u << 2) /**< \brief (TC_IDR) No effect. */\r
+#define TC_IDR_CPAS_1 (0x1u << 2) /**< \brief (TC_IDR) Disables the RA Compare Interrupt (if WAVE:1). */\r
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */\r
+#define TC_IDR_CPBS_0 (0x0u << 3) /**< \brief (TC_IDR) No effect. */\r
+#define TC_IDR_CPBS_1 (0x1u << 3) /**< \brief (TC_IDR) Disables the RB Compare Interrupt (if WAVE:1). */\r
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */\r
+#define TC_IDR_CPCS_0 (0x0u << 4) /**< \brief (TC_IDR) No effect. */\r
+#define TC_IDR_CPCS_1 (0x1u << 4) /**< \brief (TC_IDR) Disables the RC Compare Interrupt. */\r
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */\r
+#define TC_IDR_LDRAS_0 (0x0u << 5) /**< \brief (TC_IDR) No effect. */\r
+#define TC_IDR_LDRAS_1 (0x1u << 5) /**< \brief (TC_IDR) Disables the RA Load Interrupt (if WAVE:0). */\r
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */\r
+#define TC_IDR_LDRBS_0 (0x0u << 6) /**< \brief (TC_IDR) No effect. */\r
+#define TC_IDR_LDRBS_1 (0x1u << 6) /**< \brief (TC_IDR) Disables the RB Load Interrupt (if WAVE:0). */\r
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */\r
+#define TC_IDR_ETRGS_0 (0x0u << 7) /**< \brief (TC_IDR) No effect. */\r
+#define TC_IDR_ETRGS_1 (0x1u << 7) /**< \brief (TC_IDR) Disables the External Trigger Interrupt. */\r
+/* -------- TC_IMR : (TC Offset: 0x2C) Channel Interrupt Mask Register Channel 0 -------- */\r
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */\r
+#define TC_IMR_COVFS_0 (0x0u << 0) /**< \brief (TC_IMR) The Counter Overflow Interrupt is disabled. */\r
+#define TC_IMR_COVFS_1 (0x1u << 0) /**< \brief (TC_IMR) The Counter Overflow Interrupt is enabled. */\r
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */\r
+#define TC_IMR_LOVRS_0 (0x0u << 1) /**< \brief (TC_IMR) The Load Overrun Interrupt is disabled. */\r
+#define TC_IMR_LOVRS_1 (0x1u << 1) /**< \brief (TC_IMR) The Load Overrun Interrupt is enabled. */\r
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */\r
+#define TC_IMR_CPAS_0 (0x0u << 2) /**< \brief (TC_IMR) The RA Compare Interrupt is disabled. */\r
+#define TC_IMR_CPAS_1 (0x1u << 2) /**< \brief (TC_IMR) The RA Compare Interrupt is enabled. */\r
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */\r
+#define TC_IMR_CPBS_0 (0x0u << 3) /**< \brief (TC_IMR) The RB Compare Interrupt is disabled. */\r
+#define TC_IMR_CPBS_1 (0x1u << 3) /**< \brief (TC_IMR) The RB Compare Interrupt is enabled. */\r
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */\r
+#define TC_IMR_CPCS_0 (0x0u << 4) /**< \brief (TC_IMR) The RC Compare Interrupt is disabled. */\r
+#define TC_IMR_CPCS_1 (0x1u << 4) /**< \brief (TC_IMR) The RC Compare Interrupt is enabled. */\r
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */\r
+#define TC_IMR_LDRAS_0 (0x0u << 5) /**< \brief (TC_IMR) The Load RA Interrupt is disabled. */\r
+#define TC_IMR_LDRAS_1 (0x1u << 5) /**< \brief (TC_IMR) The Load RA Interrupt is enabled. */\r
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */\r
+#define TC_IMR_LDRBS_0 (0x0u << 6) /**< \brief (TC_IMR) The Load RB Interrupt is disabled. */\r
+#define TC_IMR_LDRBS_1 (0x1u << 6) /**< \brief (TC_IMR) The Load RB Interrupt is enabled. */\r
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */\r
+#define TC_IMR_ETRGS_0 (0x0u << 7) /**< \brief (TC_IMR) The External Trigger Interrupt is disabled. */\r
+#define TC_IMR_ETRGS_1 (0x1u << 7) /**< \brief (TC_IMR) The External Trigger Interrupt is enabled. */\r
+/* -------- TC_BCR : (TC Offset: 0xC0) TC Block Control Register -------- */\r
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */\r
+#define TC_BCR_SYNC_0 (0x0u << 0) /**< \brief (TC_BCR) No effect. */\r
+#define TC_BCR_SYNC_1 (0x1u << 0) /**< \brief (TC_BCR) Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. */\r
+/* -------- TC_BMR : (TC Offset: 0xC4) TC Block Mode Register -------- */\r
+#define TC_BMR_TC0XC0S_Pos 0\r
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */\r
+#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)))\r
+#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Select TCLK0 as clock signal 0. */\r
+#define TC_BMR_TC0XC0S_NO_CLK (0x1u << 0) /**< \brief (TC_BMR) Select no clock as clock signal 0. */\r
+#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Select TIOA1 as clock signal 0. */\r
+#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Select TIOA2 as clock signal 0. */\r
+#define TC_BMR_TC1XC1S_Pos 2\r
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */\r
+#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)))\r
+#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Select TCLK1 as clock signal 1. */\r
+#define TC_BMR_TC1XC1S_NO_CLK (0x1u << 2) /**< \brief (TC_BMR) Select no clock as clock signal 1. */\r
+#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Select TIOA0 as clock signal 1. */\r
+#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Select TIOA2 as clock signal 1. */\r
+#define TC_BMR_TC2XC2S_Pos 4\r
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */\r
+#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)))\r
+#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Select TCLK2 as clock signal 2. */\r
+#define TC_BMR_TC2XC2S_NO_CLK (0x1u << 4) /**< \brief (TC_BMR) Select no clock as clock signal 2. */\r
+#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Select TIOA0 as clock signal 2. */\r
+#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Select TIOA1 as clock signal 2. */\r
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */\r
+#define TC_WPMR_WPKEY_Pos 8\r
+#define TC_WPMR_WPKEY_Msk (0xFFFFFFu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect Key */\r
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))\r
+/* -------- TC_FEATURES : (TC Offset: 0xF8) Features Register -------- */\r
+#define TC_FEATURES_CTRSIZE_Pos 0\r
+#define TC_FEATURES_CTRSIZE_Msk (0xFFu << TC_FEATURES_CTRSIZE_Pos) /**< \brief (TC_FEATURES) Counter Size */\r
+#define TC_FEATURES_CTRSIZE(value) ((TC_FEATURES_CTRSIZE_Msk & ((value) << TC_FEATURES_CTRSIZE_Pos)))\r
+#define TC_FEATURES_UPDNIMPL (0x1u << 8) /**< \brief (TC_FEATURES) Up Down is Implemented */\r
+#define TC_FEATURES_BRPBHSB (0x1u << 9) /**< \brief (TC_FEATURES) Bridge Type is PB to HSB */\r
+/* -------- TC_VERSION : (TC Offset: 0xFC) Version Register -------- */\r
+#define TC_VERSION_VERSION_Pos 0\r
+#define TC_VERSION_VERSION_Msk (0xFFFu << TC_VERSION_VERSION_Pos) /**< \brief (TC_VERSION) Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. */\r
+#define TC_VERSION_VERSION(value) ((TC_VERSION_VERSION_Msk & ((value) << TC_VERSION_VERSION_Pos)))\r
+#define TC_VERSION_VARIANT_Pos 16\r
+#define TC_VERSION_VARIANT_Msk (0xFu << TC_VERSION_VARIANT_Pos) /**< \brief (TC_VERSION) Reserved. Value subject to change. No functionality associated. */\r
+#define TC_VERSION_VARIANT(value) ((TC_VERSION_VARIANT_Msk & ((value) << TC_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR TRNG */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_TRNG True Random Number Generator */\r
+/*@{*/\r
+\r
+#define REV_TRNG 0x103\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief TRNG hardware registers */\r
+typedef struct {\r
+ WoReg TRNG_CR; /**< \brief (TRNG Offset: 0x00) Control Register */\r
+ RoReg Reserved1[3];\r
+ WoReg TRNG_IER; /**< \brief (TRNG Offset: 0x10) Interrupt Enable Register */\r
+ WoReg TRNG_IDR; /**< \brief (TRNG Offset: 0x14) Interrupt Disable Register */\r
+ RoReg TRNG_IMR; /**< \brief (TRNG Offset: 0x18) Interrupt Mask Register */\r
+ RoReg TRNG_ISR; /**< \brief (TRNG Offset: 0x1C) Interrupt Status Register */\r
+ RoReg Reserved2[12];\r
+ RoReg TRNG_ODATA; /**< \brief (TRNG Offset: 0x50) Output Data Register */\r
+ RoReg Reserved3[42];\r
+ RoReg TRNG_VERSION; /**< \brief (TRNG Offset: 0xFC) Version Register */\r
+} Trng;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */\r
+#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */\r
+#define TRNG_CR_KEY_Pos 8\r
+#define TRNG_CR_KEY_Msk (0xFFFFFFu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */\r
+#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)))\r
+/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */\r
+#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */\r
+/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */\r
+#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */\r
+/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */\r
+#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */\r
+/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */\r
+#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready Interrupt Status */\r
+/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */\r
+#define TRNG_ODATA_ODATA (0x1u << 0) /**< \brief (TRNG_ODATA) Output Data */\r
+/* -------- TRNG_VERSION : (TRNG Offset: 0xFC) Version Register -------- */\r
+#define TRNG_VERSION_VERSION_Pos 0\r
+#define TRNG_VERSION_VERSION_Msk (0xFFFu << TRNG_VERSION_VERSION_Pos) /**< \brief (TRNG_VERSION) Version Number */\r
+#define TRNG_VERSION_VERSION(value) ((TRNG_VERSION_VERSION_Msk & ((value) << TRNG_VERSION_VERSION_Pos)))\r
+#define TRNG_VERSION_VARIANT_Pos 16\r
+#define TRNG_VERSION_VARIANT_Msk (0x7u << TRNG_VERSION_VARIANT_Pos) /**< \brief (TRNG_VERSION) Variant Number */\r
+#define TRNG_VERSION_VARIANT(value) ((TRNG_VERSION_VARIANT_Msk & ((value) << TRNG_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR TWIM */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_TWIM Two-wire Master Interface */\r
+/*@{*/\r
+\r
+#define REV_TWIM 0x120\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief TWIM hardware registers */\r
+typedef struct {\r
+ WoReg TWIM_CR; /**< \brief (TWIM Offset: 0x00) Control Register */\r
+ RwReg TWIM_CWGR; /**< \brief (TWIM Offset: 0x04) Clock Waveform Generator Register */\r
+ RwReg TWIM_SMBTR; /**< \brief (TWIM Offset: 0x08) SMBus Timing Register */\r
+ RwReg TWIM_CMDR; /**< \brief (TWIM Offset: 0x0C) Command Register */\r
+ RwReg TWIM_NCMDR; /**< \brief (TWIM Offset: 0x10) Next Command Register */\r
+ RoReg TWIM_RHR; /**< \brief (TWIM Offset: 0x14) Receive Holding Register */\r
+ WoReg TWIM_THR; /**< \brief (TWIM Offset: 0x18) Transmit Holding Register */\r
+ RoReg TWIM_SR; /**< \brief (TWIM Offset: 0x1C) Status Register */\r
+ WoReg TWIM_IER; /**< \brief (TWIM Offset: 0x20) Interrupt Enable Register */\r
+ WoReg TWIM_IDR; /**< \brief (TWIM Offset: 0x24) Interrupt Disable Register */\r
+ RoReg TWIM_IMR; /**< \brief (TWIM Offset: 0x28) Interrupt Mask Register */\r
+ WoReg TWIM_SCR; /**< \brief (TWIM Offset: 0x2C) Status Clear Register */\r
+ RoReg TWIM_PR; /**< \brief (TWIM Offset: 0x30) Parameter Register */\r
+ RoReg TWIM_VR; /**< \brief (TWIM Offset: 0x34) Version Register */\r
+ RwReg TWIM_HSCWGR; /**< \brief (TWIM Offset: 0x38) HS-mode Clock Waveform Generator */\r
+ RwReg TWIM_SRR; /**< \brief (TWIM Offset: 0x3C) Slew Rate Register */\r
+ RwReg TWIM_HSSRR; /**< \brief (TWIM Offset: 0x40) HS-mode Slew Rate Register */\r
+} Twim;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- TWIM_CR : (TWIM Offset: 0x00) Control Register -------- */\r
+#define TWIM_CR_MEN (0x1u << 0) /**< \brief (TWIM_CR) Master Enable */\r
+#define TWIM_CR_MDIS (0x1u << 1) /**< \brief (TWIM_CR) Master Disable */\r
+#define TWIM_CR_SMEN (0x1u << 4) /**< \brief (TWIM_CR) SMBus Enable */\r
+#define TWIM_CR_SMDIS (0x1u << 5) /**< \brief (TWIM_CR) SMBus Disable */\r
+#define TWIM_CR_SWRST (0x1u << 7) /**< \brief (TWIM_CR) Software Reset */\r
+#define TWIM_CR_STOP (0x1u << 8) /**< \brief (TWIM_CR) Stop the current transfer */\r
+/* -------- TWIM_CWGR : (TWIM Offset: 0x04) Clock Waveform Generator Register -------- */\r
+#define TWIM_CWGR_LOW_Pos 0\r
+#define TWIM_CWGR_LOW_Msk (0xFFu << TWIM_CWGR_LOW_Pos) /**< \brief (TWIM_CWGR) Clock Low Cycles */\r
+#define TWIM_CWGR_LOW(value) ((TWIM_CWGR_LOW_Msk & ((value) << TWIM_CWGR_LOW_Pos)))\r
+#define TWIM_CWGR_HIGH_Pos 8\r
+#define TWIM_CWGR_HIGH_Msk (0xFFu << TWIM_CWGR_HIGH_Pos) /**< \brief (TWIM_CWGR) Clock High Cycles */\r
+#define TWIM_CWGR_HIGH(value) ((TWIM_CWGR_HIGH_Msk & ((value) << TWIM_CWGR_HIGH_Pos)))\r
+#define TWIM_CWGR_STASTO_Pos 16\r
+#define TWIM_CWGR_STASTO_Msk (0xFFu << TWIM_CWGR_STASTO_Pos) /**< \brief (TWIM_CWGR) START and STOP Cycles */\r
+#define TWIM_CWGR_STASTO(value) ((TWIM_CWGR_STASTO_Msk & ((value) << TWIM_CWGR_STASTO_Pos)))\r
+#define TWIM_CWGR_DATA_Pos 24\r
+#define TWIM_CWGR_DATA_Msk (0xFu << TWIM_CWGR_DATA_Pos) /**< \brief (TWIM_CWGR) Data Setup and Hold Cycles */\r
+#define TWIM_CWGR_DATA(value) ((TWIM_CWGR_DATA_Msk & ((value) << TWIM_CWGR_DATA_Pos)))\r
+#define TWIM_CWGR_EXP_Pos 28\r
+#define TWIM_CWGR_EXP_Msk (0x7u << TWIM_CWGR_EXP_Pos) /**< \brief (TWIM_CWGR) Clock Prescaler */\r
+#define TWIM_CWGR_EXP(value) ((TWIM_CWGR_EXP_Msk & ((value) << TWIM_CWGR_EXP_Pos)))\r
+/* -------- TWIM_SMBTR : (TWIM Offset: 0x08) SMBus Timing Register -------- */\r
+#define TWIM_SMBTR_TLOWS_Pos 0\r
+#define TWIM_SMBTR_TLOWS_Msk (0xFFu << TWIM_SMBTR_TLOWS_Pos) /**< \brief (TWIM_SMBTR) Slave Clock stretch maximum cycles */\r
+#define TWIM_SMBTR_TLOWS(value) ((TWIM_SMBTR_TLOWS_Msk & ((value) << TWIM_SMBTR_TLOWS_Pos)))\r
+#define TWIM_SMBTR_TLOWM_Pos 8\r
+#define TWIM_SMBTR_TLOWM_Msk (0xFFu << TWIM_SMBTR_TLOWM_Pos) /**< \brief (TWIM_SMBTR) Master Clock stretch maximum cycles */\r
+#define TWIM_SMBTR_TLOWM(value) ((TWIM_SMBTR_TLOWM_Msk & ((value) << TWIM_SMBTR_TLOWM_Pos)))\r
+#define TWIM_SMBTR_THMAX_Pos 16\r
+#define TWIM_SMBTR_THMAX_Msk (0xFFu << TWIM_SMBTR_THMAX_Pos) /**< \brief (TWIM_SMBTR) Clock High maximum cycles */\r
+#define TWIM_SMBTR_THMAX(value) ((TWIM_SMBTR_THMAX_Msk & ((value) << TWIM_SMBTR_THMAX_Pos)))\r
+#define TWIM_SMBTR_EXP_Pos 28\r
+#define TWIM_SMBTR_EXP_Msk (0xFu << TWIM_SMBTR_EXP_Pos) /**< \brief (TWIM_SMBTR) SMBus Timeout Clock prescaler */\r
+#define TWIM_SMBTR_EXP(value) ((TWIM_SMBTR_EXP_Msk & ((value) << TWIM_SMBTR_EXP_Pos)))\r
+/* -------- TWIM_CMDR : (TWIM Offset: 0x0C) Command Register -------- */\r
+#define TWIM_CMDR_READ (0x1u << 0) /**< \brief (TWIM_CMDR) Transfer Direction */\r
+#define TWIM_CMDR_SADR_Pos 1\r
+#define TWIM_CMDR_SADR_Msk (0x3FFu << TWIM_CMDR_SADR_Pos) /**< \brief (TWIM_CMDR) Slave Address */\r
+#define TWIM_CMDR_SADR(value) ((TWIM_CMDR_SADR_Msk & ((value) << TWIM_CMDR_SADR_Pos)))\r
+#define TWIM_CMDR_TENBIT (0x1u << 11) /**< \brief (TWIM_CMDR) Ten Bit Addressing Mode */\r
+#define TWIM_CMDR_REPSAME (0x1u << 12) /**< \brief (TWIM_CMDR) Transfer is to same address as previous address */\r
+#define TWIM_CMDR_START (0x1u << 13) /**< \brief (TWIM_CMDR) Send START condition */\r
+#define TWIM_CMDR_STOP (0x1u << 14) /**< \brief (TWIM_CMDR) Send STOP condition */\r
+#define TWIM_CMDR_VALID (0x1u << 15) /**< \brief (TWIM_CMDR) CMDR Valid */\r
+#define TWIM_CMDR_NBYTES_Pos 16\r
+#define TWIM_CMDR_NBYTES_Msk (0xFFu << TWIM_CMDR_NBYTES_Pos) /**< \brief (TWIM_CMDR) Number of data bytes in transfer */\r
+#define TWIM_CMDR_NBYTES(value) ((TWIM_CMDR_NBYTES_Msk & ((value) << TWIM_CMDR_NBYTES_Pos)))\r
+#define TWIM_CMDR_PECEN (0x1u << 24) /**< \brief (TWIM_CMDR) Packet Error Checking Enable */\r
+#define TWIM_CMDR_ACKLAST (0x1u << 25) /**< \brief (TWIM_CMDR) ACK Last Master RX Byte */\r
+#define TWIM_CMDR_HS (0x1u << 26) /**< \brief (TWIM_CMDR) HS-mode */\r
+#define TWIM_CMDR_HSMCODE_Pos 28\r
+#define TWIM_CMDR_HSMCODE_Msk (0x7u << TWIM_CMDR_HSMCODE_Pos) /**< \brief (TWIM_CMDR) HS-mode Master Code */\r
+#define TWIM_CMDR_HSMCODE(value) ((TWIM_CMDR_HSMCODE_Msk & ((value) << TWIM_CMDR_HSMCODE_Pos)))\r
+/* -------- TWIM_NCMDR : (TWIM Offset: 0x10) Next Command Register -------- */\r
+#define TWIM_NCMDR_READ (0x1u << 0) /**< \brief (TWIM_NCMDR) Transfer Direction */\r
+#define TWIM_NCMDR_SADR_Pos 1\r
+#define TWIM_NCMDR_SADR_Msk (0x3FFu << TWIM_NCMDR_SADR_Pos) /**< \brief (TWIM_NCMDR) Slave Address */\r
+#define TWIM_NCMDR_SADR(value) ((TWIM_NCMDR_SADR_Msk & ((value) << TWIM_NCMDR_SADR_Pos)))\r
+#define TWIM_NCMDR_TENBIT (0x1u << 11) /**< \brief (TWIM_NCMDR) Ten Bit Addressing Mode */\r
+#define TWIM_NCMDR_REPSAME (0x1u << 12) /**< \brief (TWIM_NCMDR) Transfer is to same address as previous address */\r
+#define TWIM_NCMDR_START (0x1u << 13) /**< \brief (TWIM_NCMDR) Send START condition */\r
+#define TWIM_NCMDR_STOP (0x1u << 14) /**< \brief (TWIM_NCMDR) Send STOP condition */\r
+#define TWIM_NCMDR_VALID (0x1u << 15) /**< \brief (TWIM_NCMDR) CMDR Valid */\r
+#define TWIM_NCMDR_NBYTES_Pos 16\r
+#define TWIM_NCMDR_NBYTES_Msk (0xFFu << TWIM_NCMDR_NBYTES_Pos) /**< \brief (TWIM_NCMDR) Number of data bytes in transfer */\r
+#define TWIM_NCMDR_NBYTES(value) ((TWIM_NCMDR_NBYTES_Msk & ((value) << TWIM_NCMDR_NBYTES_Pos)))\r
+#define TWIM_NCMDR_PECEN (0x1u << 24) /**< \brief (TWIM_NCMDR) Packet Error Checking Enable */\r
+#define TWIM_NCMDR_ACKLAST (0x1u << 25) /**< \brief (TWIM_NCMDR) ACK Last Master RX Byte */\r
+#define TWIM_NCMDR_HS (0x1u << 26) /**< \brief (TWIM_NCMDR) HS-mode */\r
+#define TWIM_NCMDR_HSMCODE_Pos 28\r
+#define TWIM_NCMDR_HSMCODE_Msk (0x7u << TWIM_NCMDR_HSMCODE_Pos) /**< \brief (TWIM_NCMDR) HS-mode Master Code */\r
+#define TWIM_NCMDR_HSMCODE(value) ((TWIM_NCMDR_HSMCODE_Msk & ((value) << TWIM_NCMDR_HSMCODE_Pos)))\r
+/* -------- TWIM_RHR : (TWIM Offset: 0x14) Receive Holding Register -------- */\r
+#define TWIM_RHR_RXDATA_Pos 0\r
+#define TWIM_RHR_RXDATA_Msk (0xFFu << TWIM_RHR_RXDATA_Pos) /**< \brief (TWIM_RHR) Received Data */\r
+#define TWIM_RHR_RXDATA(value) ((TWIM_RHR_RXDATA_Msk & ((value) << TWIM_RHR_RXDATA_Pos)))\r
+/* -------- TWIM_THR : (TWIM Offset: 0x18) Transmit Holding Register -------- */\r
+#define TWIM_THR_TXDATA_Pos 0\r
+#define TWIM_THR_TXDATA_Msk (0xFFu << TWIM_THR_TXDATA_Pos) /**< \brief (TWIM_THR) Data to Transmit */\r
+#define TWIM_THR_TXDATA(value) ((TWIM_THR_TXDATA_Msk & ((value) << TWIM_THR_TXDATA_Pos)))\r
+/* -------- TWIM_SR : (TWIM Offset: 0x1C) Status Register -------- */\r
+#define TWIM_SR_RXRDY (0x1u << 0) /**< \brief (TWIM_SR) RHR Data Ready */\r
+#define TWIM_SR_TXRDY (0x1u << 1) /**< \brief (TWIM_SR) THR Data Ready */\r
+#define TWIM_SR_CRDY (0x1u << 2) /**< \brief (TWIM_SR) Ready for More Commands */\r
+#define TWIM_SR_CCOMP (0x1u << 3) /**< \brief (TWIM_SR) Command Complete */\r
+#define TWIM_SR_IDLE (0x1u << 4) /**< \brief (TWIM_SR) Master Interface is Idle */\r
+#define TWIM_SR_BUSFREE (0x1u << 5) /**< \brief (TWIM_SR) Two-wire Bus is Free */\r
+#define TWIM_SR_ANAK (0x1u << 8) /**< \brief (TWIM_SR) NAK in Address Phase Received */\r
+#define TWIM_SR_DNAK (0x1u << 9) /**< \brief (TWIM_SR) NAK in Data Phase Received */\r
+#define TWIM_SR_ARBLST (0x1u << 10) /**< \brief (TWIM_SR) Arbitration Lost */\r
+#define TWIM_SR_SMBALERT (0x1u << 11) /**< \brief (TWIM_SR) SMBus Alert */\r
+#define TWIM_SR_TOUT (0x1u << 12) /**< \brief (TWIM_SR) Timeout */\r
+#define TWIM_SR_PECERR (0x1u << 13) /**< \brief (TWIM_SR) PEC Error */\r
+#define TWIM_SR_STOP (0x1u << 14) /**< \brief (TWIM_SR) Stop Request Accepted */\r
+#define TWIM_SR_MENB (0x1u << 16) /**< \brief (TWIM_SR) Master Interface Enable */\r
+#define TWIM_SR_HSMCACK (0x1u << 17) /**< \brief (TWIM_SR) ACK in HS-mode Master Code Phase Received */\r
+/* -------- TWIM_IER : (TWIM Offset: 0x20) Interrupt Enable Register -------- */\r
+#define TWIM_IER_RXRDY (0x1u << 0) /**< \brief (TWIM_IER) RHR Data Ready */\r
+#define TWIM_IER_TXRDY (0x1u << 1) /**< \brief (TWIM_IER) THR Data Ready */\r
+#define TWIM_IER_CRDY (0x1u << 2) /**< \brief (TWIM_IER) Ready for More Commands */\r
+#define TWIM_IER_CCOMP (0x1u << 3) /**< \brief (TWIM_IER) Command Complete */\r
+#define TWIM_IER_IDLE (0x1u << 4) /**< \brief (TWIM_IER) Master Interface is Idle */\r
+#define TWIM_IER_BUSFREE (0x1u << 5) /**< \brief (TWIM_IER) Two-wire Bus is Free */\r
+#define TWIM_IER_ANAK (0x1u << 8) /**< \brief (TWIM_IER) NAK in Address Phase Received */\r
+#define TWIM_IER_DNAK (0x1u << 9) /**< \brief (TWIM_IER) NAK in Data Phase Received */\r
+#define TWIM_IER_ARBLST (0x1u << 10) /**< \brief (TWIM_IER) Arbitration Lost */\r
+#define TWIM_IER_SMBALERT (0x1u << 11) /**< \brief (TWIM_IER) SMBus Alert */\r
+#define TWIM_IER_TOUT (0x1u << 12) /**< \brief (TWIM_IER) Timeout */\r
+#define TWIM_IER_PECERR (0x1u << 13) /**< \brief (TWIM_IER) PEC Error */\r
+#define TWIM_IER_STOP (0x1u << 14) /**< \brief (TWIM_IER) Stop Request Accepted */\r
+#define TWIM_IER_HSMCACK (0x1u << 17) /**< \brief (TWIM_IER) ACK in HS-mode Master Code Phase Received */\r
+/* -------- TWIM_IDR : (TWIM Offset: 0x24) Interrupt Disable Register -------- */\r
+#define TWIM_IDR_RXRDY (0x1u << 0) /**< \brief (TWIM_IDR) RHR Data Ready */\r
+#define TWIM_IDR_TXRDY (0x1u << 1) /**< \brief (TWIM_IDR) THR Data Ready */\r
+#define TWIM_IDR_CRDY (0x1u << 2) /**< \brief (TWIM_IDR) Ready for More Commands */\r
+#define TWIM_IDR_CCOMP (0x1u << 3) /**< \brief (TWIM_IDR) Command Complete */\r
+#define TWIM_IDR_IDLE (0x1u << 4) /**< \brief (TWIM_IDR) Master Interface is Idle */\r
+#define TWIM_IDR_BUSFREE (0x1u << 5) /**< \brief (TWIM_IDR) Two-wire Bus is Free */\r
+#define TWIM_IDR_ANAK (0x1u << 8) /**< \brief (TWIM_IDR) NAK in Address Phase Received */\r
+#define TWIM_IDR_DNAK (0x1u << 9) /**< \brief (TWIM_IDR) NAK in Data Phase Received */\r
+#define TWIM_IDR_ARBLST (0x1u << 10) /**< \brief (TWIM_IDR) Arbitration Lost */\r
+#define TWIM_IDR_SMBALERT (0x1u << 11) /**< \brief (TWIM_IDR) SMBus Alert */\r
+#define TWIM_IDR_TOUT (0x1u << 12) /**< \brief (TWIM_IDR) Timeout */\r
+#define TWIM_IDR_PECERR (0x1u << 13) /**< \brief (TWIM_IDR) PEC Error */\r
+#define TWIM_IDR_STOP (0x1u << 14) /**< \brief (TWIM_IDR) Stop Request Accepted */\r
+#define TWIM_IDR_HSMCACK (0x1u << 17) /**< \brief (TWIM_IDR) ACK in HS-mode Master Code Phase Received */\r
+/* -------- TWIM_IMR : (TWIM Offset: 0x28) Interrupt Mask Register -------- */\r
+#define TWIM_IMR_RXRDY (0x1u << 0) /**< \brief (TWIM_IMR) RHR Data Ready */\r
+#define TWIM_IMR_TXRDY (0x1u << 1) /**< \brief (TWIM_IMR) THR Data Ready */\r
+#define TWIM_IMR_CRDY (0x1u << 2) /**< \brief (TWIM_IMR) Ready for More Commands */\r
+#define TWIM_IMR_CCOMP (0x1u << 3) /**< \brief (TWIM_IMR) Command Complete */\r
+#define TWIM_IMR_IDLE (0x1u << 4) /**< \brief (TWIM_IMR) Master Interface is Idle */\r
+#define TWIM_IMR_BUSFREE (0x1u << 5) /**< \brief (TWIM_IMR) Two-wire Bus is Free */\r
+#define TWIM_IMR_ANAK (0x1u << 8) /**< \brief (TWIM_IMR) NAK in Address Phase Received */\r
+#define TWIM_IMR_DNAK (0x1u << 9) /**< \brief (TWIM_IMR) NAK in Data Phase Received */\r
+#define TWIM_IMR_ARBLST (0x1u << 10) /**< \brief (TWIM_IMR) Arbitration Lost */\r
+#define TWIM_IMR_SMBALERT (0x1u << 11) /**< \brief (TWIM_IMR) SMBus Alert */\r
+#define TWIM_IMR_TOUT (0x1u << 12) /**< \brief (TWIM_IMR) Timeout */\r
+#define TWIM_IMR_PECERR (0x1u << 13) /**< \brief (TWIM_IMR) PEC Error */\r
+#define TWIM_IMR_STOP (0x1u << 14) /**< \brief (TWIM_IMR) Stop Request Accepted */\r
+#define TWIM_IMR_HSMCACK (0x1u << 17) /**< \brief (TWIM_IMR) ACK in HS-mode Master Code Phase Received */\r
+/* -------- TWIM_SCR : (TWIM Offset: 0x2C) Status Clear Register -------- */\r
+#define TWIM_SCR_CCOMP (0x1u << 3) /**< \brief (TWIM_SCR) Command Complete */\r
+#define TWIM_SCR_ANAK (0x1u << 8) /**< \brief (TWIM_SCR) NAK in Address Phase Received */\r
+#define TWIM_SCR_DNAK (0x1u << 9) /**< \brief (TWIM_SCR) NAK in Data Phase Received */\r
+#define TWIM_SCR_ARBLST (0x1u << 10) /**< \brief (TWIM_SCR) Arbitration Lost */\r
+#define TWIM_SCR_SMBALERT (0x1u << 11) /**< \brief (TWIM_SCR) SMBus Alert */\r
+#define TWIM_SCR_TOUT (0x1u << 12) /**< \brief (TWIM_SCR) Timeout */\r
+#define TWIM_SCR_PECERR (0x1u << 13) /**< \brief (TWIM_SCR) PEC Error */\r
+#define TWIM_SCR_STOP (0x1u << 14) /**< \brief (TWIM_SCR) Stop Request Accepted */\r
+#define TWIM_SCR_HSMCACK (0x1u << 17) /**< \brief (TWIM_SCR) ACK in HS-mode Master Code Phase Received */\r
+/* -------- TWIM_PR : (TWIM Offset: 0x30) Parameter Register -------- */\r
+#define TWIM_PR_HS (0x1u << 0) /**< \brief (TWIM_PR) HS-mode */\r
+/* -------- TWIM_VR : (TWIM Offset: 0x34) Version Register -------- */\r
+#define TWIM_VR_VERSION_Pos 0\r
+#define TWIM_VR_VERSION_Msk (0xFFFu << TWIM_VR_VERSION_Pos) /**< \brief (TWIM_VR) Version number */\r
+#define TWIM_VR_VERSION(value) ((TWIM_VR_VERSION_Msk & ((value) << TWIM_VR_VERSION_Pos)))\r
+#define TWIM_VR_VARIANT_Pos 16\r
+#define TWIM_VR_VARIANT_Msk (0xFu << TWIM_VR_VARIANT_Pos) /**< \brief (TWIM_VR) Variant number */\r
+#define TWIM_VR_VARIANT(value) ((TWIM_VR_VARIANT_Msk & ((value) << TWIM_VR_VARIANT_Pos)))\r
+/* -------- TWIM_HSCWGR : (TWIM Offset: 0x38) HS-mode Clock Waveform Generator -------- */\r
+#define TWIM_HSCWGR_LOW_Pos 0\r
+#define TWIM_HSCWGR_LOW_Msk (0xFFu << TWIM_HSCWGR_LOW_Pos) /**< \brief (TWIM_HSCWGR) Clock Low Cycles */\r
+#define TWIM_HSCWGR_LOW(value) ((TWIM_HSCWGR_LOW_Msk & ((value) << TWIM_HSCWGR_LOW_Pos)))\r
+#define TWIM_HSCWGR_HIGH_Pos 8\r
+#define TWIM_HSCWGR_HIGH_Msk (0xFFu << TWIM_HSCWGR_HIGH_Pos) /**< \brief (TWIM_HSCWGR) Clock High Cycles */\r
+#define TWIM_HSCWGR_HIGH(value) ((TWIM_HSCWGR_HIGH_Msk & ((value) << TWIM_HSCWGR_HIGH_Pos)))\r
+#define TWIM_HSCWGR_STASTO_Pos 16\r
+#define TWIM_HSCWGR_STASTO_Msk (0xFFu << TWIM_HSCWGR_STASTO_Pos) /**< \brief (TWIM_HSCWGR) START and STOP Cycles */\r
+#define TWIM_HSCWGR_STASTO(value) ((TWIM_HSCWGR_STASTO_Msk & ((value) << TWIM_HSCWGR_STASTO_Pos)))\r
+#define TWIM_HSCWGR_DATA_Pos 24\r
+#define TWIM_HSCWGR_DATA_Msk (0xFu << TWIM_HSCWGR_DATA_Pos) /**< \brief (TWIM_HSCWGR) Data Setup and Hold Cycles */\r
+#define TWIM_HSCWGR_DATA(value) ((TWIM_HSCWGR_DATA_Msk & ((value) << TWIM_HSCWGR_DATA_Pos)))\r
+#define TWIM_HSCWGR_EXP_Pos 28\r
+#define TWIM_HSCWGR_EXP_Msk (0x7u << TWIM_HSCWGR_EXP_Pos) /**< \brief (TWIM_HSCWGR) Clock Prescaler */\r
+#define TWIM_HSCWGR_EXP(value) ((TWIM_HSCWGR_EXP_Msk & ((value) << TWIM_HSCWGR_EXP_Pos)))\r
+/* -------- TWIM_SRR : (TWIM Offset: 0x3C) Slew Rate Register -------- */\r
+#define TWIM_SRR_DADRIVEL_Pos 0\r
+#define TWIM_SRR_DADRIVEL_Msk (0x7u << TWIM_SRR_DADRIVEL_Pos) /**< \brief (TWIM_SRR) Data Drive Strength LOW */\r
+#define TWIM_SRR_DADRIVEL(value) ((TWIM_SRR_DADRIVEL_Msk & ((value) << TWIM_SRR_DADRIVEL_Pos)))\r
+#define TWIM_SRR_DASLEW_Pos 8\r
+#define TWIM_SRR_DASLEW_Msk (0x3u << TWIM_SRR_DASLEW_Pos) /**< \brief (TWIM_SRR) Data Slew Limit */\r
+#define TWIM_SRR_DASLEW(value) ((TWIM_SRR_DASLEW_Msk & ((value) << TWIM_SRR_DASLEW_Pos)))\r
+#define TWIM_SRR_CLDRIVEL_Pos 16\r
+#define TWIM_SRR_CLDRIVEL_Msk (0x7u << TWIM_SRR_CLDRIVEL_Pos) /**< \brief (TWIM_SRR) Clock Drive Strength LOW */\r
+#define TWIM_SRR_CLDRIVEL(value) ((TWIM_SRR_CLDRIVEL_Msk & ((value) << TWIM_SRR_CLDRIVEL_Pos)))\r
+#define TWIM_SRR_CLSLEW_Pos 24\r
+#define TWIM_SRR_CLSLEW_Msk (0x3u << TWIM_SRR_CLSLEW_Pos) /**< \brief (TWIM_SRR) Clock Slew Limit */\r
+#define TWIM_SRR_CLSLEW(value) ((TWIM_SRR_CLSLEW_Msk & ((value) << TWIM_SRR_CLSLEW_Pos)))\r
+#define TWIM_SRR_FILTER_Pos 28\r
+#define TWIM_SRR_FILTER_Msk (0x3u << TWIM_SRR_FILTER_Pos) /**< \brief (TWIM_SRR) Input Spike Filter Control */\r
+#define TWIM_SRR_FILTER(value) ((TWIM_SRR_FILTER_Msk & ((value) << TWIM_SRR_FILTER_Pos)))\r
+/* -------- TWIM_HSSRR : (TWIM Offset: 0x40) HS-mode Slew Rate Register -------- */\r
+#define TWIM_HSSRR_DADRIVEL_Pos 0\r
+#define TWIM_HSSRR_DADRIVEL_Msk (0x7u << TWIM_HSSRR_DADRIVEL_Pos) /**< \brief (TWIM_HSSRR) Data Drive Strength LOW */\r
+#define TWIM_HSSRR_DADRIVEL(value) ((TWIM_HSSRR_DADRIVEL_Msk & ((value) << TWIM_HSSRR_DADRIVEL_Pos)))\r
+#define TWIM_HSSRR_DASLEW_Pos 8\r
+#define TWIM_HSSRR_DASLEW_Msk (0x3u << TWIM_HSSRR_DASLEW_Pos) /**< \brief (TWIM_HSSRR) Data Slew Limit */\r
+#define TWIM_HSSRR_DASLEW(value) ((TWIM_HSSRR_DASLEW_Msk & ((value) << TWIM_HSSRR_DASLEW_Pos)))\r
+#define TWIM_HSSRR_CLDRIVEL_Pos 16\r
+#define TWIM_HSSRR_CLDRIVEL_Msk (0x7u << TWIM_HSSRR_CLDRIVEL_Pos) /**< \brief (TWIM_HSSRR) Clock Drive Strength LOW */\r
+#define TWIM_HSSRR_CLDRIVEL(value) ((TWIM_HSSRR_CLDRIVEL_Msk & ((value) << TWIM_HSSRR_CLDRIVEL_Pos)))\r
+#define TWIM_HSSRR_CLDRIVEH_Pos 20\r
+#define TWIM_HSSRR_CLDRIVEH_Msk (0x3u << TWIM_HSSRR_CLDRIVEH_Pos) /**< \brief (TWIM_HSSRR) Clock Drive Strength HIGH */\r
+#define TWIM_HSSRR_CLDRIVEH(value) ((TWIM_HSSRR_CLDRIVEH_Msk & ((value) << TWIM_HSSRR_CLDRIVEH_Pos)))\r
+#define TWIM_HSSRR_CLSLEW_Pos 24\r
+#define TWIM_HSSRR_CLSLEW_Msk (0x3u << TWIM_HSSRR_CLSLEW_Pos) /**< \brief (TWIM_HSSRR) Clock Slew Limit */\r
+#define TWIM_HSSRR_CLSLEW(value) ((TWIM_HSSRR_CLSLEW_Msk & ((value) << TWIM_HSSRR_CLSLEW_Pos)))\r
+#define TWIM_HSSRR_FILTER_Pos 28\r
+#define TWIM_HSSRR_FILTER_Msk (0x3u << TWIM_HSSRR_FILTER_Pos) /**< \brief (TWIM_HSSRR) Input Spike Filter Control */\r
+#define TWIM_HSSRR_FILTER(value) ((TWIM_HSSRR_FILTER_Msk & ((value) << TWIM_HSSRR_FILTER_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR TWIS */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_TWIS Two-wire Slave Interface */\r
+/*@{*/\r
+\r
+#define REV_TWIS 0x140\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief TWIS hardware registers */\r
+typedef struct {\r
+ RwReg TWIS_CR; /**< \brief (TWIS Offset: 0x00) Control Register */\r
+ RwReg TWIS_NBYTES; /**< \brief (TWIS Offset: 0x04) NBYTES Register */\r
+ RwReg TWIS_TR; /**< \brief (TWIS Offset: 0x08) Timing Register */\r
+ RoReg TWIS_RHR; /**< \brief (TWIS Offset: 0x0C) Receive Holding Register */\r
+ WoReg TWIS_THR; /**< \brief (TWIS Offset: 0x10) Transmit Holding Register */\r
+ RoReg TWIS_PECR; /**< \brief (TWIS Offset: 0x14) Packet Error Check Register */\r
+ RoReg TWIS_SR; /**< \brief (TWIS Offset: 0x18) Status Register */\r
+ WoReg TWIS_IER; /**< \brief (TWIS Offset: 0x1C) Interrupt Enable Register */\r
+ WoReg TWIS_IDR; /**< \brief (TWIS Offset: 0x20) Interrupt Disable Register */\r
+ RoReg TWIS_IMR; /**< \brief (TWIS Offset: 0x24) Interrupt Mask Register */\r
+ WoReg TWIS_SCR; /**< \brief (TWIS Offset: 0x28) Status Clear Register */\r
+ RoReg TWIS_PR; /**< \brief (TWIS Offset: 0x2C) Parameter Register */\r
+ RoReg TWIS_VR; /**< \brief (TWIS Offset: 0x30) Version Register */\r
+ RwReg TWIS_HSTR; /**< \brief (TWIS Offset: 0x34) HS-mode Timing Register */\r
+ RwReg TWIS_SRR; /**< \brief (TWIS Offset: 0x38) Slew Rate Register */\r
+ RwReg TWIS_HSSRR; /**< \brief (TWIS Offset: 0x3C) HS-mode Slew Rate Register */\r
+} Twis;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- TWIS_CR : (TWIS Offset: 0x00) Control Register -------- */\r
+#define TWIS_CR_SEN (0x1u << 0) /**< \brief (TWIS_CR) Slave Enable */\r
+#define TWIS_CR_SMEN (0x1u << 1) /**< \brief (TWIS_CR) SMBus Mode Enable */\r
+#define TWIS_CR_SMATCH (0x1u << 2) /**< \brief (TWIS_CR) Slave Address Match */\r
+#define TWIS_CR_GCMATCH (0x1u << 3) /**< \brief (TWIS_CR) General Call Address Match */\r
+#define TWIS_CR_STREN (0x1u << 4) /**< \brief (TWIS_CR) Clock Stretch Enable */\r
+#define TWIS_CR_SWRST (0x1u << 7) /**< \brief (TWIS_CR) Software Reset */\r
+#define TWIS_CR_SMBALERT (0x1u << 8) /**< \brief (TWIS_CR) SMBus Alert */\r
+#define TWIS_CR_SMDA (0x1u << 9) /**< \brief (TWIS_CR) SMBus Default Address */\r
+#define TWIS_CR_SMHH (0x1u << 10) /**< \brief (TWIS_CR) SMBus Host Header */\r
+#define TWIS_CR_PECEN (0x1u << 11) /**< \brief (TWIS_CR) Packet Error Checking Enable */\r
+#define TWIS_CR_ACK (0x1u << 12) /**< \brief (TWIS_CR) Slave Receiver Data Phase ACK Value */\r
+#define TWIS_CR_CUP (0x1u << 13) /**< \brief (TWIS_CR) NBYTES Count Up */\r
+#define TWIS_CR_SOAM (0x1u << 14) /**< \brief (TWIS_CR) Stretch Clock on Address Match */\r
+#define TWIS_CR_SODR (0x1u << 15) /**< \brief (TWIS_CR) Stretch Clock on Data Byte Reception */\r
+#define TWIS_CR_ADR_Pos 16\r
+#define TWIS_CR_ADR_Msk (0x3FFu << TWIS_CR_ADR_Pos) /**< \brief (TWIS_CR) Slave Address */\r
+#define TWIS_CR_ADR(value) ((TWIS_CR_ADR_Msk & ((value) << TWIS_CR_ADR_Pos)))\r
+#define TWIS_CR_TENBIT (0x1u << 26) /**< \brief (TWIS_CR) Ten Bit Address Match */\r
+#define TWIS_CR_BRIDGE (0x1u << 27) /**< \brief (TWIS_CR) Bridge Control Enable */\r
+/* -------- TWIS_NBYTES : (TWIS Offset: 0x04) NBYTES Register -------- */\r
+#define TWIS_NBYTES_NBYTES_Pos 0\r
+#define TWIS_NBYTES_NBYTES_Msk (0xFFu << TWIS_NBYTES_NBYTES_Pos) /**< \brief (TWIS_NBYTES) Number of Bytes to Transfer */\r
+#define TWIS_NBYTES_NBYTES(value) ((TWIS_NBYTES_NBYTES_Msk & ((value) << TWIS_NBYTES_NBYTES_Pos)))\r
+/* -------- TWIS_TR : (TWIS Offset: 0x08) Timing Register -------- */\r
+#define TWIS_TR_TLOWS_Pos 0\r
+#define TWIS_TR_TLOWS_Msk (0xFFu << TWIS_TR_TLOWS_Pos) /**< \brief (TWIS_TR) SMBus Tlow:sext Cycles */\r
+#define TWIS_TR_TLOWS(value) ((TWIS_TR_TLOWS_Msk & ((value) << TWIS_TR_TLOWS_Pos)))\r
+#define TWIS_TR_TTOUT_Pos 8\r
+#define TWIS_TR_TTOUT_Msk (0xFFu << TWIS_TR_TTOUT_Pos) /**< \brief (TWIS_TR) SMBus Ttimeout Cycles */\r
+#define TWIS_TR_TTOUT(value) ((TWIS_TR_TTOUT_Msk & ((value) << TWIS_TR_TTOUT_Pos)))\r
+#define TWIS_TR_SUDAT_Pos 16\r
+#define TWIS_TR_SUDAT_Msk (0xFFu << TWIS_TR_SUDAT_Pos) /**< \brief (TWIS_TR) Data Setup Cycles */\r
+#define TWIS_TR_SUDAT(value) ((TWIS_TR_SUDAT_Msk & ((value) << TWIS_TR_SUDAT_Pos)))\r
+#define TWIS_TR_EXP_Pos 28\r
+#define TWIS_TR_EXP_Msk (0xFu << TWIS_TR_EXP_Pos) /**< \brief (TWIS_TR) Clock Prescaler */\r
+#define TWIS_TR_EXP(value) ((TWIS_TR_EXP_Msk & ((value) << TWIS_TR_EXP_Pos)))\r
+/* -------- TWIS_RHR : (TWIS Offset: 0x0C) Receive Holding Register -------- */\r
+#define TWIS_RHR_RXDATA_Pos 0\r
+#define TWIS_RHR_RXDATA_Msk (0xFFu << TWIS_RHR_RXDATA_Pos) /**< \brief (TWIS_RHR) Received Data Byte */\r
+#define TWIS_RHR_RXDATA(value) ((TWIS_RHR_RXDATA_Msk & ((value) << TWIS_RHR_RXDATA_Pos)))\r
+/* -------- TWIS_THR : (TWIS Offset: 0x10) Transmit Holding Register -------- */\r
+#define TWIS_THR_TXDATA_Pos 0\r
+#define TWIS_THR_TXDATA_Msk (0xFFu << TWIS_THR_TXDATA_Pos) /**< \brief (TWIS_THR) Data Byte to Transmit */\r
+#define TWIS_THR_TXDATA(value) ((TWIS_THR_TXDATA_Msk & ((value) << TWIS_THR_TXDATA_Pos)))\r
+/* -------- TWIS_PECR : (TWIS Offset: 0x14) Packet Error Check Register -------- */\r
+#define TWIS_PECR_PEC_Pos 0\r
+#define TWIS_PECR_PEC_Msk (0xFFu << TWIS_PECR_PEC_Pos) /**< \brief (TWIS_PECR) Calculated PEC Value */\r
+#define TWIS_PECR_PEC(value) ((TWIS_PECR_PEC_Msk & ((value) << TWIS_PECR_PEC_Pos)))\r
+/* -------- TWIS_SR : (TWIS Offset: 0x18) Status Register -------- */\r
+#define TWIS_SR_RXRDY (0x1u << 0) /**< \brief (TWIS_SR) RX Buffer Ready */\r
+#define TWIS_SR_TXRDY (0x1u << 1) /**< \brief (TWIS_SR) TX Buffer Ready */\r
+#define TWIS_SR_SEN (0x1u << 2) /**< \brief (TWIS_SR) Slave Enabled */\r
+#define TWIS_SR_TCOMP (0x1u << 3) /**< \brief (TWIS_SR) Transmission Complete */\r
+#define TWIS_SR_TRA (0x1u << 5) /**< \brief (TWIS_SR) Transmitter Mode */\r
+#define TWIS_SR_URUN (0x1u << 6) /**< \brief (TWIS_SR) Underrun */\r
+#define TWIS_SR_ORUN (0x1u << 7) /**< \brief (TWIS_SR) Overrun */\r
+#define TWIS_SR_NAK (0x1u << 8) /**< \brief (TWIS_SR) NAK Received */\r
+#define TWIS_SR_SMBTOUT (0x1u << 12) /**< \brief (TWIS_SR) SMBus Timeout */\r
+#define TWIS_SR_SMBPECERR (0x1u << 13) /**< \brief (TWIS_SR) SMBus PEC Error */\r
+#define TWIS_SR_BUSERR (0x1u << 14) /**< \brief (TWIS_SR) Bus Error */\r
+#define TWIS_SR_SAM (0x1u << 16) /**< \brief (TWIS_SR) Slave Address Match */\r
+#define TWIS_SR_GCM (0x1u << 17) /**< \brief (TWIS_SR) General Call Match */\r
+#define TWIS_SR_SMBALERTM (0x1u << 18) /**< \brief (TWIS_SR) SMBus Alert Response Address Match */\r
+#define TWIS_SR_SMBHHM (0x1u << 19) /**< \brief (TWIS_SR) SMBus Host Header Address Match */\r
+#define TWIS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIS_SR) SMBus Default Address Match */\r
+#define TWIS_SR_STO (0x1u << 21) /**< \brief (TWIS_SR) Stop Received */\r
+#define TWIS_SR_REP (0x1u << 22) /**< \brief (TWIS_SR) Repeated Start Received */\r
+#define TWIS_SR_BTF (0x1u << 23) /**< \brief (TWIS_SR) Byte Transfer Finished */\r
+/* -------- TWIS_IER : (TWIS Offset: 0x1C) Interrupt Enable Register -------- */\r
+#define TWIS_IER_RXRDY (0x1u << 0) /**< \brief (TWIS_IER) RX Buffer Ready */\r
+#define TWIS_IER_TXRDY (0x1u << 1) /**< \brief (TWIS_IER) TX Buffer Ready */\r
+#define TWIS_IER_TCOMP (0x1u << 3) /**< \brief (TWIS_IER) Transmission Complete */\r
+#define TWIS_IER_URUN (0x1u << 6) /**< \brief (TWIS_IER) Underrun */\r
+#define TWIS_IER_ORUN (0x1u << 7) /**< \brief (TWIS_IER) Overrun */\r
+#define TWIS_IER_NAK (0x1u << 8) /**< \brief (TWIS_IER) NAK Received */\r
+#define TWIS_IER_SMBTOUT (0x1u << 12) /**< \brief (TWIS_IER) SMBus Timeout */\r
+#define TWIS_IER_SMBPECERR (0x1u << 13) /**< \brief (TWIS_IER) SMBus PEC Error */\r
+#define TWIS_IER_BUSERR (0x1u << 14) /**< \brief (TWIS_IER) Bus Error */\r
+#define TWIS_IER_SAM (0x1u << 16) /**< \brief (TWIS_IER) Slave Address Match */\r
+#define TWIS_IER_GCM (0x1u << 17) /**< \brief (TWIS_IER) General Call Match */\r
+#define TWIS_IER_SMBALERTM (0x1u << 18) /**< \brief (TWIS_IER) SMBus Alert Response Address Match */\r
+#define TWIS_IER_SMBHHM (0x1u << 19) /**< \brief (TWIS_IER) SMBus Host Header Address Match */\r
+#define TWIS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIS_IER) SMBus Default Address Match */\r
+#define TWIS_IER_STO (0x1u << 21) /**< \brief (TWIS_IER) Stop Received */\r
+#define TWIS_IER_REP (0x1u << 22) /**< \brief (TWIS_IER) Repeated Start Received */\r
+#define TWIS_IER_BTF (0x1u << 23) /**< \brief (TWIS_IER) Byte Transfer Finished */\r
+/* -------- TWIS_IDR : (TWIS Offset: 0x20) Interrupt Disable Register -------- */\r
+#define TWIS_IDR_RXRDY (0x1u << 0) /**< \brief (TWIS_IDR) RX Buffer Ready */\r
+#define TWIS_IDR_TXRDY (0x1u << 1) /**< \brief (TWIS_IDR) TX Buffer Ready */\r
+#define TWIS_IDR_TCOMP (0x1u << 3) /**< \brief (TWIS_IDR) Transmission Complete */\r
+#define TWIS_IDR_URUN (0x1u << 6) /**< \brief (TWIS_IDR) Underrun */\r
+#define TWIS_IDR_ORUN (0x1u << 7) /**< \brief (TWIS_IDR) Overrun */\r
+#define TWIS_IDR_NAK (0x1u << 8) /**< \brief (TWIS_IDR) NAK Received */\r
+#define TWIS_IDR_SMBTOUT (0x1u << 12) /**< \brief (TWIS_IDR) SMBus Timeout */\r
+#define TWIS_IDR_SMBPECERR (0x1u << 13) /**< \brief (TWIS_IDR) SMBus PEC Error */\r
+#define TWIS_IDR_BUSERR (0x1u << 14) /**< \brief (TWIS_IDR) Bus Error */\r
+#define TWIS_IDR_SAM (0x1u << 16) /**< \brief (TWIS_IDR) Slave Address Match */\r
+#define TWIS_IDR_GCM (0x1u << 17) /**< \brief (TWIS_IDR) General Call Match */\r
+#define TWIS_IDR_SMBALERTM (0x1u << 18) /**< \brief (TWIS_IDR) SMBus Alert Response Address Match */\r
+#define TWIS_IDR_SMBHHM (0x1u << 19) /**< \brief (TWIS_IDR) SMBus Host Header Address Match */\r
+#define TWIS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIS_IDR) SMBus Default Address Match */\r
+#define TWIS_IDR_STO (0x1u << 21) /**< \brief (TWIS_IDR) Stop Received */\r
+#define TWIS_IDR_REP (0x1u << 22) /**< \brief (TWIS_IDR) Repeated Start Received */\r
+#define TWIS_IDR_BTF (0x1u << 23) /**< \brief (TWIS_IDR) Byte Transfer Finished */\r
+/* -------- TWIS_IMR : (TWIS Offset: 0x24) Interrupt Mask Register -------- */\r
+#define TWIS_IMR_RXRDY (0x1u << 0) /**< \brief (TWIS_IMR) RX Buffer Ready */\r
+#define TWIS_IMR_TXRDY (0x1u << 1) /**< \brief (TWIS_IMR) TX Buffer Ready */\r
+#define TWIS_IMR_TCOMP (0x1u << 3) /**< \brief (TWIS_IMR) Transmission Complete */\r
+#define TWIS_IMR_URUN (0x1u << 6) /**< \brief (TWIS_IMR) Underrun */\r
+#define TWIS_IMR_ORUN (0x1u << 7) /**< \brief (TWIS_IMR) Overrun */\r
+#define TWIS_IMR_NAK (0x1u << 8) /**< \brief (TWIS_IMR) NAK Received */\r
+#define TWIS_IMR_SMBTOUT (0x1u << 12) /**< \brief (TWIS_IMR) SMBus Timeout */\r
+#define TWIS_IMR_SMBPECERR (0x1u << 13) /**< \brief (TWIS_IMR) SMBus PEC Error */\r
+#define TWIS_IMR_BUSERR (0x1u << 14) /**< \brief (TWIS_IMR) Bus Error */\r
+#define TWIS_IMR_SAM (0x1u << 16) /**< \brief (TWIS_IMR) Slave Address Match */\r
+#define TWIS_IMR_GCM (0x1u << 17) /**< \brief (TWIS_IMR) General Call Match */\r
+#define TWIS_IMR_SMBALERTM (0x1u << 18) /**< \brief (TWIS_IMR) SMBus Alert Response Address Match */\r
+#define TWIS_IMR_SMBHHM (0x1u << 19) /**< \brief (TWIS_IMR) SMBus Host Header Address Match */\r
+#define TWIS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIS_IMR) SMBus Default Address Match */\r
+#define TWIS_IMR_STO (0x1u << 21) /**< \brief (TWIS_IMR) Stop Received */\r
+#define TWIS_IMR_REP (0x1u << 22) /**< \brief (TWIS_IMR) Repeated Start Received */\r
+#define TWIS_IMR_BTF (0x1u << 23) /**< \brief (TWIS_IMR) Byte Transfer Finished */\r
+/* -------- TWIS_SCR : (TWIS Offset: 0x28) Status Clear Register -------- */\r
+#define TWIS_SCR_TCOMP (0x1u << 3) /**< \brief (TWIS_SCR) Transmission Complete */\r
+#define TWIS_SCR_URUN (0x1u << 6) /**< \brief (TWIS_SCR) Underrun */\r
+#define TWIS_SCR_ORUN (0x1u << 7) /**< \brief (TWIS_SCR) Overrun */\r
+#define TWIS_SCR_NAK (0x1u << 8) /**< \brief (TWIS_SCR) NAK Received */\r
+#define TWIS_SCR_SMBTOUT (0x1u << 12) /**< \brief (TWIS_SCR) SMBus Timeout */\r
+#define TWIS_SCR_SMBPECERR (0x1u << 13) /**< \brief (TWIS_SCR) SMBus PEC Error */\r
+#define TWIS_SCR_BUSERR (0x1u << 14) /**< \brief (TWIS_SCR) Bus Error */\r
+#define TWIS_SCR_SAM (0x1u << 16) /**< \brief (TWIS_SCR) Slave Address Match */\r
+#define TWIS_SCR_GCM (0x1u << 17) /**< \brief (TWIS_SCR) General Call Match */\r
+#define TWIS_SCR_SMBALERTM (0x1u << 18) /**< \brief (TWIS_SCR) SMBus Alert Response Address Match */\r
+#define TWIS_SCR_SMBHHM (0x1u << 19) /**< \brief (TWIS_SCR) SMBus Host Header Address Match */\r
+#define TWIS_SCR_SMBDAM (0x1u << 20) /**< \brief (TWIS_SCR) SMBus Default Address Match */\r
+#define TWIS_SCR_STO (0x1u << 21) /**< \brief (TWIS_SCR) Stop Received */\r
+#define TWIS_SCR_REP (0x1u << 22) /**< \brief (TWIS_SCR) Repeated Start Received */\r
+#define TWIS_SCR_BTF (0x1u << 23) /**< \brief (TWIS_SCR) Byte Transfer Finished */\r
+/* -------- TWIS_PR : (TWIS Offset: 0x2C) Parameter Register -------- */\r
+#define TWIS_PR_HS (0x1u << 0) /**< \brief (TWIS_PR) HS-mode */\r
+/* -------- TWIS_VR : (TWIS Offset: 0x30) Version Register -------- */\r
+#define TWIS_VR_VERSION_Pos 0\r
+#define TWIS_VR_VERSION_Msk (0xFFFu << TWIS_VR_VERSION_Pos) /**< \brief (TWIS_VR) Version Number */\r
+#define TWIS_VR_VERSION(value) ((TWIS_VR_VERSION_Msk & ((value) << TWIS_VR_VERSION_Pos)))\r
+#define TWIS_VR_VARIANT_Pos 16\r
+#define TWIS_VR_VARIANT_Msk (0xFu << TWIS_VR_VARIANT_Pos) /**< \brief (TWIS_VR) Variant Number */\r
+#define TWIS_VR_VARIANT(value) ((TWIS_VR_VARIANT_Msk & ((value) << TWIS_VR_VARIANT_Pos)))\r
+/* -------- TWIS_HSTR : (TWIS Offset: 0x34) HS-mode Timing Register -------- */\r
+#define TWIS_HSTR_HDDAT_Pos 16\r
+#define TWIS_HSTR_HDDAT_Msk (0xFFu << TWIS_HSTR_HDDAT_Pos) /**< \brief (TWIS_HSTR) Data Hold Cycles */\r
+#define TWIS_HSTR_HDDAT(value) ((TWIS_HSTR_HDDAT_Msk & ((value) << TWIS_HSTR_HDDAT_Pos)))\r
+/* -------- TWIS_SRR : (TWIS Offset: 0x38) Slew Rate Register -------- */\r
+#define TWIS_SRR_DADRIVEL_Pos 0\r
+#define TWIS_SRR_DADRIVEL_Msk (0x7u << TWIS_SRR_DADRIVEL_Pos) /**< \brief (TWIS_SRR) Data Drive Strength LOW */\r
+#define TWIS_SRR_DADRIVEL(value) ((TWIS_SRR_DADRIVEL_Msk & ((value) << TWIS_SRR_DADRIVEL_Pos)))\r
+#define TWIS_SRR_DASLEW_Pos 8\r
+#define TWIS_SRR_DASLEW_Msk (0x3u << TWIS_SRR_DASLEW_Pos) /**< \brief (TWIS_SRR) Data Slew Limit */\r
+#define TWIS_SRR_DASLEW(value) ((TWIS_SRR_DASLEW_Msk & ((value) << TWIS_SRR_DASLEW_Pos)))\r
+#define TWIS_SRR_FILTER_Pos 28\r
+#define TWIS_SRR_FILTER_Msk (0x3u << TWIS_SRR_FILTER_Pos) /**< \brief (TWIS_SRR) Input Spike Filter Control */\r
+#define TWIS_SRR_FILTER(value) ((TWIS_SRR_FILTER_Msk & ((value) << TWIS_SRR_FILTER_Pos)))\r
+/* -------- TWIS_HSSRR : (TWIS Offset: 0x3C) HS-mode Slew Rate Register -------- */\r
+#define TWIS_HSSRR_DADRIVEL_Pos 0\r
+#define TWIS_HSSRR_DADRIVEL_Msk (0x7u << TWIS_HSSRR_DADRIVEL_Pos) /**< \brief (TWIS_HSSRR) Data Drive Strength LOW */\r
+#define TWIS_HSSRR_DADRIVEL(value) ((TWIS_HSSRR_DADRIVEL_Msk & ((value) << TWIS_HSSRR_DADRIVEL_Pos)))\r
+#define TWIS_HSSRR_DASLEW_Pos 8\r
+#define TWIS_HSSRR_DASLEW_Msk (0x3u << TWIS_HSSRR_DASLEW_Pos) /**< \brief (TWIS_HSSRR) Data Slew Limit */\r
+#define TWIS_HSSRR_DASLEW(value) ((TWIS_HSSRR_DASLEW_Msk & ((value) << TWIS_HSSRR_DASLEW_Pos)))\r
+#define TWIS_HSSRR_FILTER_Pos 28\r
+#define TWIS_HSSRR_FILTER_Msk (0x3u << TWIS_HSSRR_FILTER_Pos) /**< \brief (TWIS_HSSRR) Input Spike Filter Control */\r
+#define TWIS_HSSRR_FILTER(value) ((TWIS_HSSRR_FILTER_Msk & ((value) << TWIS_HSSRR_FILTER_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR USART */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_USART Universal Synchronous Asynchronous Receiver Transmitter */\r
+/*@{*/\r
+\r
+#define REV_USART 0x6021\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief USART hardware registers */\r
+typedef struct {\r
+ WoReg US_CR; /**< \brief (USART Offset: 0x00) Control Register */\r
+ RwReg US_MR; /**< \brief (USART Offset: 0x04) Mode Register */\r
+ WoReg US_IER; /**< \brief (USART Offset: 0x08) Interrupt Enable Register */\r
+ WoReg US_IDR; /**< \brief (USART Offset: 0x0C) Interrupt Disable Register */\r
+ RoReg US_IMR; /**< \brief (USART Offset: 0x10) Interrupt Mask Register */\r
+ RoReg US_CSR; /**< \brief (USART Offset: 0x14) Channel Status Register */\r
+ RoReg US_RHR; /**< \brief (USART Offset: 0x18) Receiver Holding Register */\r
+ WoReg US_THR; /**< \brief (USART Offset: 0x1C) Transmitter Holding Register */\r
+ RwReg US_BRGR; /**< \brief (USART Offset: 0x20) Baud Rate Generator Register */\r
+ RwReg US_RTOR; /**< \brief (USART Offset: 0x24) Receiver Time-out Register */\r
+ RwReg US_TTGR; /**< \brief (USART Offset: 0x28) Transmitter Timeguard Register */\r
+ RoReg Reserved1[5];\r
+ RwReg US_FIDI; /**< \brief (USART Offset: 0x40) FI DI Ratio Register */\r
+ RoReg US_NER; /**< \brief (USART Offset: 0x44) Number of Errors Register */\r
+ RoReg Reserved2[1];\r
+ RwReg US_IFR; /**< \brief (USART Offset: 0x4C) IrDA Filter Register */\r
+ RwReg US_MAN; /**< \brief (USART Offset: 0x50) Manchester Configuration Register */\r
+ RwReg US_LINMR; /**< \brief (USART Offset: 0x54) LIN Mode Register */\r
+ RwReg US_LINIR; /**< \brief (USART Offset: 0x58) LIN Identifier Register */\r
+ RoReg US_LINBRR; /**< \brief (USART Offset: 0x5C) LIN Baud Rate Register */\r
+ RoReg Reserved3[33];\r
+ RwReg US_WPMR; /**< \brief (USART Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg US_WPSR; /**< \brief (USART Offset: 0xE8) Write Protect Status Register */\r
+ RoReg Reserved4[4];\r
+ RoReg US_VERSION; /**< \brief (USART Offset: 0xFC) Version Register */\r
+} Usart;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- US_LIN_CR : (USART Offset: 0x00) Control Register -------- */\r
+#define US_LIN_CR_RSTRX (0x1u << 2) /**< \brief (US_LIN_CR) Reset Receiver */\r
+#define US_LIN_CR_RSTRX_0 (0x0u << 2) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_RSTRX_1 (0x1u << 2) /**< \brief (US_LIN_CR) Resets the receiver */\r
+#define US_LIN_CR_RSTTX (0x1u << 3) /**< \brief (US_LIN_CR) Reset Transmitter */\r
+#define US_LIN_CR_RSTTX_0 (0x0u << 3) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_RSTTX_1 (0x1u << 3) /**< \brief (US_LIN_CR) Resets the transmitter */\r
+#define US_LIN_CR_RXEN (0x1u << 4) /**< \brief (US_LIN_CR) Receiver Enable */\r
+#define US_LIN_CR_RXEN_0 (0x0u << 4) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_RXEN_1 (0x1u << 4) /**< \brief (US_LIN_CR) Enables the receiver, if RXDIS is 0 */\r
+#define US_LIN_CR_RXDIS (0x1u << 5) /**< \brief (US_LIN_CR) Receiver Disable */\r
+#define US_LIN_CR_RXDIS_0 (0x0u << 5) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_RXDIS_1 (0x1u << 5) /**< \brief (US_LIN_CR) Disables the receiver */\r
+#define US_LIN_CR_TXEN (0x1u << 6) /**< \brief (US_LIN_CR) Transmitter Enable */\r
+#define US_LIN_CR_TXEN_0 (0x0u << 6) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_TXEN_1 (0x1u << 6) /**< \brief (US_LIN_CR) Enables the transmitter if TXDIS is 0 */\r
+#define US_LIN_CR_TXDIS (0x1u << 7) /**< \brief (US_LIN_CR) Transmitter Disable */\r
+#define US_LIN_CR_TXDIS_0 (0x0u << 7) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_TXDIS_1 (0x1u << 7) /**< \brief (US_LIN_CR) Disables the transmitter */\r
+#define US_LIN_CR_RSTSTA (0x1u << 8) /**< \brief (US_LIN_CR) Reset Status Bits */\r
+#define US_LIN_CR_RSTSTA_0 (0x0u << 8) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_RSTSTA_1 (0x1u << 8) /**< \brief (US_LIN_CR) Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR */\r
+#define US_LIN_CR_STTBRK (0x1u << 9) /**< \brief (US_LIN_CR) Start Break */\r
+#define US_LIN_CR_STTBRK_0 (0x0u << 9) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_STTBRK_1 (0x1u << 9) /**< \brief (US_LIN_CR) Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted */\r
+#define US_LIN_CR_STPBRK (0x1u << 10) /**< \brief (US_LIN_CR) Stop Break */\r
+#define US_LIN_CR_STPBRK_0 (0x0u << 10) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_STPBRK_1 (0x1u << 10) /**< \brief (US_LIN_CR) Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted */\r
+#define US_LIN_CR_STTTO (0x1u << 11) /**< \brief (US_LIN_CR) Start Time-out */\r
+#define US_LIN_CR_STTTO_0 (0x0u << 11) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_STTTO_1 (0x1u << 11) /**< \brief (US_LIN_CR) Starts waiting for a character before clocking the time-out counter */\r
+#define US_LIN_CR_SENDA (0x1u << 12) /**< \brief (US_LIN_CR) Send Address */\r
+#define US_LIN_CR_SENDA_0 (0x0u << 12) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_SENDA_1 (0x1u << 12) /**< \brief (US_LIN_CR) In Multi-drop Mode only, the next character written to the THR is sent with the address bit set */\r
+#define US_LIN_CR_RSTIT (0x1u << 13) /**< \brief (US_LIN_CR) Reset Iterations */\r
+#define US_LIN_CR_RSTIT_0 (0x0u << 13) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_RSTIT_1 (0x1u << 13) /**< \brief (US_LIN_CR) Resets ITERATION in CSR. No effect if the ISO7816 is not enabled */\r
+#define US_LIN_CR_RSTNACK (0x1u << 14) /**< \brief (US_LIN_CR) Reset Non Acknowledge */\r
+#define US_LIN_CR_RSTNACK_0 (0x0u << 14) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_RSTNACK_1 (0x1u << 14) /**< \brief (US_LIN_CR) Resets NACK in CSR */\r
+#define US_LIN_CR_RETTO (0x1u << 15) /**< \brief (US_LIN_CR) Rearm Time-out */\r
+#define US_LIN_CR_RETTO_0 (0x0u << 15) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_RETTO_1 (0x1u << 15) /**< \brief (US_LIN_CR) Restart Time-out */\r
+#define US_LIN_CR_DTREN (0x1u << 16) /**< \brief (US_LIN_CR) Data Terminal Ready Enable */\r
+#define US_LIN_CR_DTREN_0 (0x0u << 16) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_DTREN_1 (0x1u << 16) /**< \brief (US_LIN_CR) Drives the pin DTR at 0 */\r
+#define US_LIN_CR_DTRDIS (0x1u << 17) /**< \brief (US_LIN_CR) Data Terminal Ready Disable */\r
+#define US_LIN_CR_DTRDIS_0 (0x0u << 17) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_DTRDIS_1 (0x1u << 17) /**< \brief (US_LIN_CR) Drives the pin DTR to 1 */\r
+#define US_LIN_CR_RTSEN (0x1u << 18) /**< \brief (US_LIN_CR) Request to Send Enable */\r
+#define US_LIN_CR_RTSEN_0 (0x0u << 18) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_RTSEN_1 (0x1u << 18) /**< \brief (US_LIN_CR) Drives the pin RTS to 0 */\r
+#define US_LIN_CR_RTSDIS (0x1u << 19) /**< \brief (US_LIN_CR) Request to Send Disable */\r
+#define US_LIN_CR_RTSDIS_0 (0x0u << 19) /**< \brief (US_LIN_CR) No effect */\r
+#define US_LIN_CR_RTSDIS_1 (0x1u << 19) /**< \brief (US_LIN_CR) Drives the pin RTS to 1 */\r
+#define US_LIN_CR_LINABT (0x1u << 20) /**< \brief (US_LIN_CR) Abort the current LIN transmission */\r
+#define US_LIN_CR_LINWKUP (0x1u << 21) /**< \brief (US_LIN_CR) Sends a wakeup signal on the LIN bus */\r
+/* -------- US_SPI_MASTER_CR : (USART Offset: 0x00) Control Register -------- */\r
+#define US_SPI_MASTER_CR_RSTRX (0x1u << 2) /**< \brief (US_SPI_MASTER_CR) Reset Receiver */\r
+#define US_SPI_MASTER_CR_RSTRX_0 (0x0u << 2) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_RSTRX_1 (0x1u << 2) /**< \brief (US_SPI_MASTER_CR) Resets the receiver */\r
+#define US_SPI_MASTER_CR_RSTTX (0x1u << 3) /**< \brief (US_SPI_MASTER_CR) Reset Transmitter */\r
+#define US_SPI_MASTER_CR_RSTTX_0 (0x0u << 3) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_RSTTX_1 (0x1u << 3) /**< \brief (US_SPI_MASTER_CR) Resets the transmitter */\r
+#define US_SPI_MASTER_CR_RXEN (0x1u << 4) /**< \brief (US_SPI_MASTER_CR) Receiver Enable */\r
+#define US_SPI_MASTER_CR_RXEN_0 (0x0u << 4) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_RXEN_1 (0x1u << 4) /**< \brief (US_SPI_MASTER_CR) Enables the receiver, if RXDIS is 0 */\r
+#define US_SPI_MASTER_CR_RXDIS (0x1u << 5) /**< \brief (US_SPI_MASTER_CR) Receiver Disable */\r
+#define US_SPI_MASTER_CR_RXDIS_0 (0x0u << 5) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_RXDIS_1 (0x1u << 5) /**< \brief (US_SPI_MASTER_CR) Disables the receiver */\r
+#define US_SPI_MASTER_CR_TXEN (0x1u << 6) /**< \brief (US_SPI_MASTER_CR) Transmitter Enable */\r
+#define US_SPI_MASTER_CR_TXEN_0 (0x0u << 6) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_TXEN_1 (0x1u << 6) /**< \brief (US_SPI_MASTER_CR) Enables the transmitter if TXDIS is 0 */\r
+#define US_SPI_MASTER_CR_TXDIS (0x1u << 7) /**< \brief (US_SPI_MASTER_CR) Transmitter Disable */\r
+#define US_SPI_MASTER_CR_TXDIS_0 (0x0u << 7) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_TXDIS_1 (0x1u << 7) /**< \brief (US_SPI_MASTER_CR) Disables the transmitter */\r
+#define US_SPI_MASTER_CR_RSTSTA (0x1u << 8) /**< \brief (US_SPI_MASTER_CR) Reset Status Bits */\r
+#define US_SPI_MASTER_CR_RSTSTA_0 (0x0u << 8) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_RSTSTA_1 (0x1u << 8) /**< \brief (US_SPI_MASTER_CR) Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR */\r
+#define US_SPI_MASTER_CR_STTBRK (0x1u << 9) /**< \brief (US_SPI_MASTER_CR) Start Break */\r
+#define US_SPI_MASTER_CR_STTBRK_0 (0x0u << 9) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_STTBRK_1 (0x1u << 9) /**< \brief (US_SPI_MASTER_CR) Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted */\r
+#define US_SPI_MASTER_CR_STPBRK (0x1u << 10) /**< \brief (US_SPI_MASTER_CR) Stop Break */\r
+#define US_SPI_MASTER_CR_STPBRK_0 (0x0u << 10) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_STPBRK_1 (0x1u << 10) /**< \brief (US_SPI_MASTER_CR) Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted */\r
+#define US_SPI_MASTER_CR_STTTO (0x1u << 11) /**< \brief (US_SPI_MASTER_CR) Start Time-out */\r
+#define US_SPI_MASTER_CR_STTTO_0 (0x0u << 11) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_STTTO_1 (0x1u << 11) /**< \brief (US_SPI_MASTER_CR) Starts waiting for a character before clocking the time-out counter */\r
+#define US_SPI_MASTER_CR_SENDA (0x1u << 12) /**< \brief (US_SPI_MASTER_CR) Send Address */\r
+#define US_SPI_MASTER_CR_SENDA_0 (0x0u << 12) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_SENDA_1 (0x1u << 12) /**< \brief (US_SPI_MASTER_CR) In Multi-drop Mode only, the next character written to the THR is sent with the address bit set */\r
+#define US_SPI_MASTER_CR_RSTIT (0x1u << 13) /**< \brief (US_SPI_MASTER_CR) Reset Iterations */\r
+#define US_SPI_MASTER_CR_RSTIT_0 (0x0u << 13) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_RSTIT_1 (0x1u << 13) /**< \brief (US_SPI_MASTER_CR) Resets ITERATION in CSR. No effect if the ISO7816 is not enabled */\r
+#define US_SPI_MASTER_CR_RSTNACK (0x1u << 14) /**< \brief (US_SPI_MASTER_CR) Reset Non Acknowledge */\r
+#define US_SPI_MASTER_CR_RSTNACK_0 (0x0u << 14) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_RSTNACK_1 (0x1u << 14) /**< \brief (US_SPI_MASTER_CR) Resets NACK in CSR */\r
+#define US_SPI_MASTER_CR_RETTO (0x1u << 15) /**< \brief (US_SPI_MASTER_CR) Rearm Time-out */\r
+#define US_SPI_MASTER_CR_RETTO_0 (0x0u << 15) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_RETTO_1 (0x1u << 15) /**< \brief (US_SPI_MASTER_CR) Restart Time-out */\r
+#define US_SPI_MASTER_CR_DTREN (0x1u << 16) /**< \brief (US_SPI_MASTER_CR) Data Terminal Ready Enable */\r
+#define US_SPI_MASTER_CR_DTREN_0 (0x0u << 16) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_DTREN_1 (0x1u << 16) /**< \brief (US_SPI_MASTER_CR) Drives the pin DTR at 0 */\r
+#define US_SPI_MASTER_CR_DTRDIS (0x1u << 17) /**< \brief (US_SPI_MASTER_CR) Data Terminal Ready Disable */\r
+#define US_SPI_MASTER_CR_DTRDIS_0 (0x0u << 17) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_DTRDIS_1 (0x1u << 17) /**< \brief (US_SPI_MASTER_CR) Drives the pin DTR to 1 */\r
+#define US_SPI_MASTER_CR_FCS (0x1u << 18) /**< \brief (US_SPI_MASTER_CR) Force SPI Chip Select */\r
+#define US_SPI_MASTER_CR_FCS_0 (0x0u << 18) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_FCS_1 (0x1u << 18) /**< \brief (US_SPI_MASTER_CR) Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer) */\r
+#define US_SPI_MASTER_CR_RCS (0x1u << 19) /**< \brief (US_SPI_MASTER_CR) Release SPI Chip Select */\r
+#define US_SPI_MASTER_CR_RCS_0 (0x0u << 19) /**< \brief (US_SPI_MASTER_CR) No effect */\r
+#define US_SPI_MASTER_CR_RCS_1 (0x1u << 19) /**< \brief (US_SPI_MASTER_CR) Releases the Slave Select Line NSS (RTS pin) */\r
+/* -------- US_USART_CR : (USART Offset: 0x00) Control Register -------- */\r
+#define US_USART_CR_RSTRX (0x1u << 2) /**< \brief (US_USART_CR) Reset Receiver */\r
+#define US_USART_CR_RSTRX_0 (0x0u << 2) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_RSTRX_1 (0x1u << 2) /**< \brief (US_USART_CR) Resets the receiver */\r
+#define US_USART_CR_RSTTX (0x1u << 3) /**< \brief (US_USART_CR) Reset Transmitter */\r
+#define US_USART_CR_RSTTX_0 (0x0u << 3) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_RSTTX_1 (0x1u << 3) /**< \brief (US_USART_CR) Resets the transmitter */\r
+#define US_USART_CR_RXEN (0x1u << 4) /**< \brief (US_USART_CR) Receiver Enable */\r
+#define US_USART_CR_RXEN_0 (0x0u << 4) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_RXEN_1 (0x1u << 4) /**< \brief (US_USART_CR) Enables the receiver, if RXDIS is 0 */\r
+#define US_USART_CR_RXDIS (0x1u << 5) /**< \brief (US_USART_CR) Receiver Disable */\r
+#define US_USART_CR_RXDIS_0 (0x0u << 5) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_RXDIS_1 (0x1u << 5) /**< \brief (US_USART_CR) Disables the receiver */\r
+#define US_USART_CR_TXEN (0x1u << 6) /**< \brief (US_USART_CR) Transmitter Enable */\r
+#define US_USART_CR_TXEN_0 (0x0u << 6) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_TXEN_1 (0x1u << 6) /**< \brief (US_USART_CR) Enables the transmitter if TXDIS is 0 */\r
+#define US_USART_CR_TXDIS (0x1u << 7) /**< \brief (US_USART_CR) Transmitter Disable */\r
+#define US_USART_CR_TXDIS_0 (0x0u << 7) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_TXDIS_1 (0x1u << 7) /**< \brief (US_USART_CR) Disables the transmitter */\r
+#define US_USART_CR_RSTSTA (0x1u << 8) /**< \brief (US_USART_CR) Reset Status Bits */\r
+#define US_USART_CR_RSTSTA_0 (0x0u << 8) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_RSTSTA_1 (0x1u << 8) /**< \brief (US_USART_CR) Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR */\r
+#define US_USART_CR_STTBRK (0x1u << 9) /**< \brief (US_USART_CR) Start Break */\r
+#define US_USART_CR_STTBRK_0 (0x0u << 9) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_STTBRK_1 (0x1u << 9) /**< \brief (US_USART_CR) Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted */\r
+#define US_USART_CR_STPBRK (0x1u << 10) /**< \brief (US_USART_CR) Stop Break */\r
+#define US_USART_CR_STPBRK_0 (0x0u << 10) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_STPBRK_1 (0x1u << 10) /**< \brief (US_USART_CR) Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted */\r
+#define US_USART_CR_STTTO (0x1u << 11) /**< \brief (US_USART_CR) Start Time-out */\r
+#define US_USART_CR_STTTO_0 (0x0u << 11) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_STTTO_1 (0x1u << 11) /**< \brief (US_USART_CR) Starts waiting for a character before clocking the time-out counter */\r
+#define US_USART_CR_SENDA (0x1u << 12) /**< \brief (US_USART_CR) Send Address */\r
+#define US_USART_CR_SENDA_0 (0x0u << 12) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_SENDA_1 (0x1u << 12) /**< \brief (US_USART_CR) In Multi-drop Mode only, the next character written to the THR is sent with the address bit set */\r
+#define US_USART_CR_RSTIT (0x1u << 13) /**< \brief (US_USART_CR) Reset Iterations */\r
+#define US_USART_CR_RSTIT_0 (0x0u << 13) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_RSTIT_1 (0x1u << 13) /**< \brief (US_USART_CR) Resets ITERATION in CSR. No effect if the ISO7816 is not enabled */\r
+#define US_USART_CR_RSTNACK (0x1u << 14) /**< \brief (US_USART_CR) Reset Non Acknowledge */\r
+#define US_USART_CR_RSTNACK_0 (0x0u << 14) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_RSTNACK_1 (0x1u << 14) /**< \brief (US_USART_CR) Resets NACK in CSR */\r
+#define US_USART_CR_RETTO (0x1u << 15) /**< \brief (US_USART_CR) Rearm Time-out */\r
+#define US_USART_CR_RETTO_0 (0x0u << 15) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_RETTO_1 (0x1u << 15) /**< \brief (US_USART_CR) Restart Time-out */\r
+#define US_USART_CR_DTREN (0x1u << 16) /**< \brief (US_USART_CR) Data Terminal Ready Enable */\r
+#define US_USART_CR_DTREN_0 (0x0u << 16) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_DTREN_1 (0x1u << 16) /**< \brief (US_USART_CR) Drives the pin DTR at 0 */\r
+#define US_USART_CR_DTRDIS (0x1u << 17) /**< \brief (US_USART_CR) Data Terminal Ready Disable */\r
+#define US_USART_CR_DTRDIS_0 (0x0u << 17) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_DTRDIS_1 (0x1u << 17) /**< \brief (US_USART_CR) Drives the pin DTR to 1 */\r
+#define US_USART_CR_RTSEN (0x1u << 18) /**< \brief (US_USART_CR) Request to Send Enable */\r
+#define US_USART_CR_RTSEN_0 (0x0u << 18) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_RTSEN_1 (0x1u << 18) /**< \brief (US_USART_CR) Drives the pin RTS to 0 */\r
+#define US_USART_CR_RTSDIS (0x1u << 19) /**< \brief (US_USART_CR) Request to Send Disable */\r
+#define US_USART_CR_RTSDIS_0 (0x0u << 19) /**< \brief (US_USART_CR) No effect */\r
+#define US_USART_CR_RTSDIS_1 (0x1u << 19) /**< \brief (US_USART_CR) Drives the pin RTS to 1 */\r
+/* -------- US_CR : (USART Offset: 0x00) Control Register -------- */\r
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */\r
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */\r
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */\r
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */\r
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */\r
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */\r
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */\r
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */\r
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */\r
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */\r
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */\r
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */\r
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */\r
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */\r
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */\r
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */\r
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */\r
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */\r
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */\r
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */\r
+#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort the current LIN transmission */\r
+#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Sends a wakeup signal on the LIN bus */\r
+\r
+/* -------- US_SPI_MR : (USART Offset: 0x04) Mode Register -------- */\r
+#define US_SPI_MR_MODE_Pos 0\r
+#define US_SPI_MR_MODE_Msk (0xFu << US_SPI_MR_MODE_Pos) /**< \brief (US_SPI_MR) Usart Mode */\r
+#define US_SPI_MR_MODE(value) ((US_SPI_MR_MODE_Msk & ((value) << US_SPI_MR_MODE_Pos)))\r
+#define US_SPI_MR_MODE_NORMAL (0x0u << 0) /**< \brief (US_SPI_MR) Normal */\r
+#define US_SPI_MR_MODE_RS485 (0x1u << 0) /**< \brief (US_SPI_MR) RS485 */\r
+#define US_SPI_MR_MODE_HARDWARE (0x2u << 0) /**< \brief (US_SPI_MR) Hardware Handshaking */\r
+#define US_SPI_MR_MODE_MODEM (0x3u << 0) /**< \brief (US_SPI_MR) Modem */\r
+#define US_SPI_MR_MODE_ISO7816_T0 (0x4u << 0) /**< \brief (US_SPI_MR) IS07816 Protocol: T = 0 */\r
+#define US_SPI_MR_MODE_ISO7816_T1 (0x6u << 0) /**< \brief (US_SPI_MR) IS07816 Protocol: T = 1 */\r
+#define US_SPI_MR_MODE_IRDA (0x8u << 0) /**< \brief (US_SPI_MR) IrDA */\r
+#define US_SPI_MR_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_SPI_MR) LIN Master */\r
+#define US_SPI_MR_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_SPI_MR) LIN Slave */\r
+#define US_SPI_MR_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_SPI_MR) SPI Master */\r
+#define US_SPI_MR_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_SPI_MR) SPI Slave */\r
+#define US_SPI_MR_USCLKS_Pos 4\r
+#define US_SPI_MR_USCLKS_Msk (0x3u << US_SPI_MR_USCLKS_Pos) /**< \brief (US_SPI_MR) Clock Selection */\r
+#define US_SPI_MR_USCLKS(value) ((US_SPI_MR_USCLKS_Msk & ((value) << US_SPI_MR_USCLKS_Pos)))\r
+#define US_SPI_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_SPI_MR) MCK */\r
+#define US_SPI_MR_USCLKS_MCK_DIV (0x1u << 4) /**< \brief (US_SPI_MR) MCK / DIV */\r
+#define US_SPI_MR_USCLKS_2 (0x2u << 4) /**< \brief (US_SPI_MR) Reserved */\r
+#define US_SPI_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_SPI_MR) SCK */\r
+#define US_SPI_MR_CHRL_Pos 6\r
+#define US_SPI_MR_CHRL_Msk (0x3u << US_SPI_MR_CHRL_Pos) /**< \brief (US_SPI_MR) Character Length. */\r
+#define US_SPI_MR_CHRL(value) ((US_SPI_MR_CHRL_Msk & ((value) << US_SPI_MR_CHRL_Pos)))\r
+#define US_SPI_MR_CHRL_5 (0x0u << 6) /**< \brief (US_SPI_MR) 5 bits */\r
+#define US_SPI_MR_CHRL_6 (0x1u << 6) /**< \brief (US_SPI_MR) 6 bits */\r
+#define US_SPI_MR_CHRL_7 (0x2u << 6) /**< \brief (US_SPI_MR) 7 bits */\r
+#define US_SPI_MR_CHRL_8 (0x3u << 6) /**< \brief (US_SPI_MR) 8 bits */\r
+#define US_SPI_MR_CPHA (0x1u << 8) /**< \brief (US_SPI_MR) SPI CLock Phase */\r
+#define US_SPI_MR_CPHA_0 (0x0u << 8) /**< \brief (US_SPI_MR) Data is changed on the leading edge of SPCK and captured on the following edge of SPCK */\r
+#define US_SPI_MR_CPHA_1 (0x1u << 8) /**< \brief (US_SPI_MR) Data is captured on the leading edge of SPCK and changed on the following edge of SPCK */\r
+#define US_SPI_MR_PAR_Pos 9\r
+#define US_SPI_MR_PAR_Msk (0x7u << US_SPI_MR_PAR_Pos) /**< \brief (US_SPI_MR) Parity Type */\r
+#define US_SPI_MR_PAR(value) ((US_SPI_MR_PAR_Msk & ((value) << US_SPI_MR_PAR_Pos)))\r
+#define US_SPI_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_SPI_MR) Even parity */\r
+#define US_SPI_MR_PAR_ODD (0x1u << 9) /**< \brief (US_SPI_MR) Odd parity */\r
+#define US_SPI_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_SPI_MR) Parity forced to 0 (Space) */\r
+#define US_SPI_MR_PAR_MARK (0x3u << 9) /**< \brief (US_SPI_MR) Parity forced to 1 (Mark) */\r
+#define US_SPI_MR_PAR_NONE (0x4u << 9) /**< \brief (US_SPI_MR) No Parity */\r
+#define US_SPI_MR_PAR_5 (0x5u << 9) /**< \brief (US_SPI_MR) No Parity */\r
+#define US_SPI_MR_PAR_MULTI (0x6u << 9) /**< \brief (US_SPI_MR) Multi-drop mode */\r
+#define US_SPI_MR_PAR_7 (0x7u << 9) /**< \brief (US_SPI_MR) Multi-drop mode */\r
+#define US_SPI_MR_NBSTOP_Pos 12\r
+#define US_SPI_MR_NBSTOP_Msk (0x3u << US_SPI_MR_NBSTOP_Pos) /**< \brief (US_SPI_MR) Number of Stop Bits */\r
+#define US_SPI_MR_NBSTOP(value) ((US_SPI_MR_NBSTOP_Msk & ((value) << US_SPI_MR_NBSTOP_Pos)))\r
+#define US_SPI_MR_NBSTOP_1 (0x0u << 12) /**< \brief (US_SPI_MR) 1 stop bit */\r
+#define US_SPI_MR_NBSTOP_1_5 (0x1u << 12) /**< \brief (US_SPI_MR) 1.5 stop bits (Only valid if SYNC=0) */\r
+#define US_SPI_MR_NBSTOP_2 (0x2u << 12) /**< \brief (US_SPI_MR) 2 stop bits */\r
+#define US_SPI_MR_NBSTOP_3 (0x3u << 12) /**< \brief (US_SPI_MR) Reserved */\r
+#define US_SPI_MR_CHMODE_Pos 14\r
+#define US_SPI_MR_CHMODE_Msk (0x3u << US_SPI_MR_CHMODE_Pos) /**< \brief (US_SPI_MR) Channel Mode */\r
+#define US_SPI_MR_CHMODE(value) ((US_SPI_MR_CHMODE_Msk & ((value) << US_SPI_MR_CHMODE_Pos)))\r
+#define US_SPI_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_SPI_MR) Normal Mode */\r
+#define US_SPI_MR_CHMODE_ECHO (0x1u << 14) /**< \brief (US_SPI_MR) Automatic Echo. Receiver input is connected to the TXD pin */\r
+#define US_SPI_MR_CHMODE_LOCAL_LOOP (0x2u << 14) /**< \brief (US_SPI_MR) Local Loopback. Transmitter output is connected to the Receiver Input */\r
+#define US_SPI_MR_CHMODE_REMOTE_LOOP (0x3u << 14) /**< \brief (US_SPI_MR) Remote Loopback. RXD pin is internally connected to the TXD pin */\r
+#define US_SPI_MR_CPOL (0x1u << 16) /**< \brief (US_SPI_MR) SPI Clock Polarity */\r
+#define US_SPI_MR_CPOL_ZERO (0x0u << 16) /**< \brief (US_SPI_MR) The inactive state value of SPCK is logic level zero */\r
+#define US_SPI_MR_CPOL_ONE (0x1u << 16) /**< \brief (US_SPI_MR) The inactive state value of SPCK is logic level one */\r
+#define US_SPI_MR_MODE9 (0x1u << 17) /**< \brief (US_SPI_MR) 9-bit Character Length */\r
+#define US_SPI_MR_MODE9_0 (0x0u << 17) /**< \brief (US_SPI_MR) CHRL defines character length */\r
+#define US_SPI_MR_MODE9_1 (0x1u << 17) /**< \brief (US_SPI_MR) 9-bit character length */\r
+#define US_SPI_MR_CLKO (0x1u << 18) /**< \brief (US_SPI_MR) Clock Output Select */\r
+#define US_SPI_MR_CLKO_0 (0x0u << 18) /**< \brief (US_SPI_MR) The USART does not drive the SCK pin */\r
+#define US_SPI_MR_CLKO_1 (0x1u << 18) /**< \brief (US_SPI_MR) The USART drives the SCK pin if USCLKS does not select the external clock SCK */\r
+#define US_SPI_MR_OVER (0x1u << 19) /**< \brief (US_SPI_MR) Oversampling Mode */\r
+#define US_SPI_MR_OVER_X16 (0x0u << 19) /**< \brief (US_SPI_MR) 16x Oversampling */\r
+#define US_SPI_MR_OVER_X8 (0x1u << 19) /**< \brief (US_SPI_MR) 8x Oversampling */\r
+#define US_SPI_MR_INACK (0x1u << 20) /**< \brief (US_SPI_MR) Inhibit Non Acknowledge */\r
+#define US_SPI_MR_INACK_0 (0x0u << 20) /**< \brief (US_SPI_MR) The NACK is generated */\r
+#define US_SPI_MR_INACK_1 (0x1u << 20) /**< \brief (US_SPI_MR) The NACK is not generated */\r
+#define US_SPI_MR_DSNACK (0x1u << 21) /**< \brief (US_SPI_MR) Disable Successive NACK */\r
+#define US_SPI_MR_DSNACK_0 (0x0u << 21) /**< \brief (US_SPI_MR) NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) */\r
+#define US_SPI_MR_DSNACK_1 (0x1u << 21) /**< \brief (US_SPI_MR) Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted */\r
+#define US_SPI_MR_INVDATA (0x1u << 23) /**< \brief (US_SPI_MR) Inverted data */\r
+#define US_SPI_MR_MAX_ITERATION_Pos 24\r
+#define US_SPI_MR_MAX_ITERATION_Msk (0x7u << US_SPI_MR_MAX_ITERATION_Pos) /**< \brief (US_SPI_MR) Max interation */\r
+#define US_SPI_MR_MAX_ITERATION(value) ((US_SPI_MR_MAX_ITERATION_Msk & ((value) << US_SPI_MR_MAX_ITERATION_Pos)))\r
+#define US_SPI_MR_FILTER (0x1u << 28) /**< \brief (US_SPI_MR) Infrared Receive Line Filter */\r
+#define US_SPI_MR_FILTER_0 (0x0u << 28) /**< \brief (US_SPI_MR) The USART does not filter the receive line */\r
+#define US_SPI_MR_FILTER_1 (0x1u << 28) /**< \brief (US_SPI_MR) The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) */\r
+/* -------- US_USART_MR : (USART Offset: 0x04) Mode Register -------- */\r
+#define US_USART_MR_MODE_Pos 0\r
+#define US_USART_MR_MODE_Msk (0xFu << US_USART_MR_MODE_Pos) /**< \brief (US_USART_MR) Usart Mode */\r
+#define US_USART_MR_MODE(value) ((US_USART_MR_MODE_Msk & ((value) << US_USART_MR_MODE_Pos)))\r
+#define US_USART_MR_MODE_NORMAL (0x0u << 0) /**< \brief (US_USART_MR) Normal */\r
+#define US_USART_MR_MODE_RS485 (0x1u << 0) /**< \brief (US_USART_MR) RS485 */\r
+#define US_USART_MR_MODE_HARDWARE (0x2u << 0) /**< \brief (US_USART_MR) Hardware Handshaking */\r
+#define US_USART_MR_MODE_MODEM (0x3u << 0) /**< \brief (US_USART_MR) Modem */\r
+#define US_USART_MR_MODE_ISO7816_T0 (0x4u << 0) /**< \brief (US_USART_MR) IS07816 Protocol: T = 0 */\r
+#define US_USART_MR_MODE_ISO7816_T1 (0x6u << 0) /**< \brief (US_USART_MR) IS07816 Protocol: T = 1 */\r
+#define US_USART_MR_MODE_IRDA (0x8u << 0) /**< \brief (US_USART_MR) IrDA */\r
+#define US_USART_MR_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_USART_MR) LIN Master */\r
+#define US_USART_MR_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_USART_MR) LIN Slave */\r
+#define US_USART_MR_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_USART_MR) SPI Master */\r
+#define US_USART_MR_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_USART_MR) SPI Slave */\r
+#define US_USART_MR_USCLKS_Pos 4\r
+#define US_USART_MR_USCLKS_Msk (0x3u << US_USART_MR_USCLKS_Pos) /**< \brief (US_USART_MR) Clock Selection */\r
+#define US_USART_MR_USCLKS(value) ((US_USART_MR_USCLKS_Msk & ((value) << US_USART_MR_USCLKS_Pos)))\r
+#define US_USART_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_USART_MR) MCK */\r
+#define US_USART_MR_USCLKS_MCK_DIV (0x1u << 4) /**< \brief (US_USART_MR) MCK / DIV */\r
+#define US_USART_MR_USCLKS_2 (0x2u << 4) /**< \brief (US_USART_MR) Reserved */\r
+#define US_USART_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_USART_MR) SCK */\r
+#define US_USART_MR_CHRL_Pos 6\r
+#define US_USART_MR_CHRL_Msk (0x3u << US_USART_MR_CHRL_Pos) /**< \brief (US_USART_MR) Character Length. */\r
+#define US_USART_MR_CHRL(value) ((US_USART_MR_CHRL_Msk & ((value) << US_USART_MR_CHRL_Pos)))\r
+#define US_USART_MR_CHRL_5 (0x0u << 6) /**< \brief (US_USART_MR) 5 bits */\r
+#define US_USART_MR_CHRL_6 (0x1u << 6) /**< \brief (US_USART_MR) 6 bits */\r
+#define US_USART_MR_CHRL_7 (0x2u << 6) /**< \brief (US_USART_MR) 7 bits */\r
+#define US_USART_MR_CHRL_8 (0x3u << 6) /**< \brief (US_USART_MR) 8 bits */\r
+#define US_USART_MR_SYNC (0x1u << 8) /**< \brief (US_USART_MR) Synchronous Mode Select */\r
+#define US_USART_MR_SYNC_0 (0x0u << 8) /**< \brief (US_USART_MR) USART operates in Synchronous Mode */\r
+#define US_USART_MR_SYNC_1 (0x1u << 8) /**< \brief (US_USART_MR) USART operates in Asynchronous Mode */\r
+#define US_USART_MR_PAR_Pos 9\r
+#define US_USART_MR_PAR_Msk (0x7u << US_USART_MR_PAR_Pos) /**< \brief (US_USART_MR) Parity Type */\r
+#define US_USART_MR_PAR(value) ((US_USART_MR_PAR_Msk & ((value) << US_USART_MR_PAR_Pos)))\r
+#define US_USART_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_USART_MR) Even parity */\r
+#define US_USART_MR_PAR_ODD (0x1u << 9) /**< \brief (US_USART_MR) Odd parity */\r
+#define US_USART_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_USART_MR) Parity forced to 0 (Space) */\r
+#define US_USART_MR_PAR_MARK (0x3u << 9) /**< \brief (US_USART_MR) Parity forced to 1 (Mark) */\r
+#define US_USART_MR_PAR_NONE (0x4u << 9) /**< \brief (US_USART_MR) No Parity */\r
+#define US_USART_MR_PAR_5 (0x5u << 9) /**< \brief (US_USART_MR) No Parity */\r
+#define US_USART_MR_PAR_MULTI (0x6u << 9) /**< \brief (US_USART_MR) Multi-drop mode */\r
+#define US_USART_MR_PAR_7 (0x7u << 9) /**< \brief (US_USART_MR) Multi-drop mode */\r
+#define US_USART_MR_NBSTOP_Pos 12\r
+#define US_USART_MR_NBSTOP_Msk (0x3u << US_USART_MR_NBSTOP_Pos) /**< \brief (US_USART_MR) Number of Stop Bits */\r
+#define US_USART_MR_NBSTOP(value) ((US_USART_MR_NBSTOP_Msk & ((value) << US_USART_MR_NBSTOP_Pos)))\r
+#define US_USART_MR_NBSTOP_1 (0x0u << 12) /**< \brief (US_USART_MR) 1 stop bit */\r
+#define US_USART_MR_NBSTOP_1_5 (0x1u << 12) /**< \brief (US_USART_MR) 1.5 stop bits (Only valid if SYNC=0) */\r
+#define US_USART_MR_NBSTOP_2 (0x2u << 12) /**< \brief (US_USART_MR) 2 stop bits */\r
+#define US_USART_MR_NBSTOP_3 (0x3u << 12) /**< \brief (US_USART_MR) Reserved */\r
+#define US_USART_MR_CHMODE_Pos 14\r
+#define US_USART_MR_CHMODE_Msk (0x3u << US_USART_MR_CHMODE_Pos) /**< \brief (US_USART_MR) Channel Mode */\r
+#define US_USART_MR_CHMODE(value) ((US_USART_MR_CHMODE_Msk & ((value) << US_USART_MR_CHMODE_Pos)))\r
+#define US_USART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_USART_MR) Normal Mode */\r
+#define US_USART_MR_CHMODE_ECHO (0x1u << 14) /**< \brief (US_USART_MR) Automatic Echo. Receiver input is connected to the TXD pin */\r
+#define US_USART_MR_CHMODE_LOCAL_LOOP (0x2u << 14) /**< \brief (US_USART_MR) Local Loopback. Transmitter output is connected to the Receiver Input */\r
+#define US_USART_MR_CHMODE_REMOTE_LOOP (0x3u << 14) /**< \brief (US_USART_MR) Remote Loopback. RXD pin is internally connected to the TXD pin */\r
+#define US_USART_MR_MSBF (0x1u << 16) /**< \brief (US_USART_MR) Bit Order */\r
+#define US_USART_MR_MSBF_LSBF (0x0u << 16) /**< \brief (US_USART_MR) Least Significant Bit first */\r
+#define US_USART_MR_MSBF_MSBF (0x1u << 16) /**< \brief (US_USART_MR) Most Significant Bit first */\r
+#define US_USART_MR_MODE9 (0x1u << 17) /**< \brief (US_USART_MR) 9-bit Character Length */\r
+#define US_USART_MR_MODE9_0 (0x0u << 17) /**< \brief (US_USART_MR) CHRL defines character length */\r
+#define US_USART_MR_MODE9_1 (0x1u << 17) /**< \brief (US_USART_MR) 9-bit character length */\r
+#define US_USART_MR_CLKO (0x1u << 18) /**< \brief (US_USART_MR) Clock Output Select */\r
+#define US_USART_MR_CLKO_0 (0x0u << 18) /**< \brief (US_USART_MR) The USART does not drive the SCK pin */\r
+#define US_USART_MR_CLKO_1 (0x1u << 18) /**< \brief (US_USART_MR) The USART drives the SCK pin if USCLKS does not select the external clock SCK */\r
+#define US_USART_MR_OVER (0x1u << 19) /**< \brief (US_USART_MR) Oversampling Mode */\r
+#define US_USART_MR_OVER_X16 (0x0u << 19) /**< \brief (US_USART_MR) 16x Oversampling */\r
+#define US_USART_MR_OVER_X8 (0x1u << 19) /**< \brief (US_USART_MR) 8x Oversampling */\r
+#define US_USART_MR_INACK (0x1u << 20) /**< \brief (US_USART_MR) Inhibit Non Acknowledge */\r
+#define US_USART_MR_INACK_0 (0x0u << 20) /**< \brief (US_USART_MR) The NACK is generated */\r
+#define US_USART_MR_INACK_1 (0x1u << 20) /**< \brief (US_USART_MR) The NACK is not generated */\r
+#define US_USART_MR_DSNACK (0x1u << 21) /**< \brief (US_USART_MR) Disable Successive NACK */\r
+#define US_USART_MR_DSNACK_0 (0x0u << 21) /**< \brief (US_USART_MR) NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) */\r
+#define US_USART_MR_DSNACK_1 (0x1u << 21) /**< \brief (US_USART_MR) Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted */\r
+#define US_USART_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_USART_MR) Variable synchronization of command/data sync Start Frame Delimiter */\r
+#define US_USART_MR_VAR_SYNC_0 (0x0u << 22) /**< \brief (US_USART_MR) User defined configuration of command or data sync field depending on SYNC value */\r
+#define US_USART_MR_VAR_SYNC_1 (0x1u << 22) /**< \brief (US_USART_MR) The sync field is updated when a character is written into THR register */\r
+#define US_USART_MR_INVDATA (0x1u << 23) /**< \brief (US_USART_MR) Inverted data */\r
+#define US_USART_MR_MAX_ITERATION_Pos 24\r
+#define US_USART_MR_MAX_ITERATION_Msk (0x7u << US_USART_MR_MAX_ITERATION_Pos) /**< \brief (US_USART_MR) Max interation */\r
+#define US_USART_MR_MAX_ITERATION(value) ((US_USART_MR_MAX_ITERATION_Msk & ((value) << US_USART_MR_MAX_ITERATION_Pos)))\r
+#define US_USART_MR_FILTER (0x1u << 28) /**< \brief (US_USART_MR) Infrared Receive Line Filter */\r
+#define US_USART_MR_FILTER_0 (0x0u << 28) /**< \brief (US_USART_MR) The USART does not filter the receive line */\r
+#define US_USART_MR_FILTER_1 (0x1u << 28) /**< \brief (US_USART_MR) The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) */\r
+#define US_USART_MR_MAN (0x1u << 29) /**< \brief (US_USART_MR) Manchester Encoder/Decoder Enable */\r
+#define US_USART_MR_MAN_0 (0x0u << 29) /**< \brief (US_USART_MR) Manchester Encoder/Decoder is disabled */\r
+#define US_USART_MR_MAN_1 (0x1u << 29) /**< \brief (US_USART_MR) Manchester Encoder/Decoder is enabled */\r
+#define US_USART_MR_MODSYNC (0x1u << 30) /**< \brief (US_USART_MR) Manchester Synchronization Mode */\r
+#define US_USART_MR_MODSYNC_0 (0x0u << 30) /**< \brief (US_USART_MR) The Manchester Start bit is a 0 to 1 transition */\r
+#define US_USART_MR_MODSYNC_1 (0x1u << 30) /**< \brief (US_USART_MR) The Manchester Start bit is a 1 to 0 transition */\r
+#define US_USART_MR_ONEBIT (0x1u << 31) /**< \brief (US_USART_MR) Start Frame Delimiter selector */\r
+#define US_USART_MR_ONEBIT_0 (0x0u << 31) /**< \brief (US_USART_MR) Start Frame delimiter is COMMAND or DATA SYNC */\r
+#define US_USART_MR_ONEBIT_1 (0x1u << 31) /**< \brief (US_USART_MR) Start Frame delimiter is One Bit */\r
+/* -------- US_MR : (USART Offset: 0x04) Mode Register -------- */\r
+#define US_MR_USART_MODE_Pos 0\r
+#define US_MR_USART_MODE_Msk (0xFu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) Usart Mode */\r
+#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)))\r
+#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal */\r
+#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */\r
+#define US_MR_USART_MODE_HARDWARE (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */\r
+#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */\r
+#define US_MR_USART_MODE_ISO7816_T0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */\r
+#define US_MR_USART_MODE_ISO7816_T1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */\r
+#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */\r
+#define US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN Master */\r
+#define US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave */\r
+#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */\r
+#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */\r
+#define US_MR_USCLKS_Pos 4\r
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */\r
+#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos)))\r
+#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) MCK */\r
+#define US_MR_USCLKS_MCK_DIV (0x1u << 4) /**< \brief (US_MR) MCK / DIV */\r
+#define US_MR_USCLKS_2 (0x2u << 4) /**< \brief (US_MR) Reserved */\r
+#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) SCK */\r
+#define US_MR_CHRL_Pos 6\r
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */\r
+#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos)))\r
+#define US_MR_CHRL_5 (0x0u << 6) /**< \brief (US_MR) 5 bits */\r
+#define US_MR_CHRL_6 (0x1u << 6) /**< \brief (US_MR) 6 bits */\r
+#define US_MR_CHRL_7 (0x2u << 6) /**< \brief (US_MR) 7 bits */\r
+#define US_MR_CHRL_8 (0x3u << 6) /**< \brief (US_MR) 8 bits */\r
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI CLock Phase */\r
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */\r
+#define US_MR_PAR_Pos 9\r
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */\r
+#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos)))\r
+#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */\r
+#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */\r
+#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */\r
+#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */\r
+#define US_MR_PAR_NONE (0x4u << 9) /**< \brief (US_MR) No Parity */\r
+#define US_MR_PAR_5 (0x5u << 9) /**< \brief (US_MR) No Parity */\r
+#define US_MR_PAR_MULTI (0x6u << 9) /**< \brief (US_MR) Multi-drop mode */\r
+#define US_MR_PAR_7 (0x7u << 9) /**< \brief (US_MR) Multi-drop mode */\r
+#define US_MR_NBSTOP_Pos 12\r
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */\r
+#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos)))\r
+#define US_MR_NBSTOP_1 (0x0u << 12) /**< \brief (US_MR) 1 stop bit */\r
+#define US_MR_NBSTOP_1_5 (0x1u << 12) /**< \brief (US_MR) 1.5 stop bits (Only valid if SYNC=0) */\r
+#define US_MR_NBSTOP_2 (0x2u << 12) /**< \brief (US_MR) 2 stop bits */\r
+#define US_MR_NBSTOP_3 (0x3u << 12) /**< \brief (US_MR) Reserved */\r
+#define US_MR_CHMODE_Pos 14\r
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */\r
+#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos)))\r
+#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */\r
+#define US_MR_CHMODE_ECHO (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin */\r
+#define US_MR_CHMODE_LOCAL_LOOP (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input */\r
+#define US_MR_CHMODE_REMOTE_LOOP (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin */\r
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */\r
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */\r
+#define US_MR_USART_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */\r
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */\r
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */\r
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */\r
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */\r
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable synchronization of command/data sync Start Frame Delimiter */\r
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted data */\r
+#define US_MR_MAX_ITERATION_Pos 24\r
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Max interation */\r
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))\r
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */\r
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */\r
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */\r
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter selector */\r
+\r
+/* -------- US_LIN_IER : (USART Offset: 0x08) Interrupt Enable Register -------- */\r
+#define US_LIN_IER_RXRDY (0x1u << 0) /**< \brief (US_LIN_IER) Receiver Ready Interrupt Enable */\r
+#define US_LIN_IER_RXRDY_0 (0x0u << 0) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_RXRDY_1 (0x1u << 0) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_TXRDY (0x1u << 1) /**< \brief (US_LIN_IER) Transmitter Ready Interrupt Enable */\r
+#define US_LIN_IER_TXRDY_0 (0x0u << 1) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_TXRDY_1 (0x1u << 1) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_RXBRK (0x1u << 2) /**< \brief (US_LIN_IER) Receiver Break Interrupt Enable */\r
+#define US_LIN_IER_RXBRK_0 (0x0u << 2) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_RXBRK_1 (0x1u << 2) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_ENDRX (0x1u << 3) /**< \brief (US_LIN_IER) End of Receive Transfer Interrupt Enable */\r
+#define US_LIN_IER_ENDRX_0 (0x0u << 3) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_ENDRX_1 (0x1u << 3) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_ENDTX (0x1u << 4) /**< \brief (US_LIN_IER) End of Transmit Interrupt Enable */\r
+#define US_LIN_IER_ENDTX_0 (0x0u << 4) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_ENDTX_1 (0x1u << 4) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_OVRE (0x1u << 5) /**< \brief (US_LIN_IER) Overrun Error Interrupt Enable */\r
+#define US_LIN_IER_OVRE_0 (0x0u << 5) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_OVRE_1 (0x1u << 5) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_FRAME (0x1u << 6) /**< \brief (US_LIN_IER) Framing Error Interrupt Enable */\r
+#define US_LIN_IER_FRAME_0 (0x0u << 6) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_FRAME_1 (0x1u << 6) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_PARE (0x1u << 7) /**< \brief (US_LIN_IER) Parity Error Interrupt Enable */\r
+#define US_LIN_IER_PARE_0 (0x0u << 7) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_PARE_1 (0x1u << 7) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_TIMEOUT (0x1u << 8) /**< \brief (US_LIN_IER) Time-out Interrupt Enable */\r
+#define US_LIN_IER_TIMEOUT_0 (0x0u << 8) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_TIMEOUT_1 (0x1u << 8) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_TXEMPTY (0x1u << 9) /**< \brief (US_LIN_IER) Transmitter Empty Interrupt Enable */\r
+#define US_LIN_IER_TXEMPTY_0 (0x0u << 9) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_TXEMPTY_1 (0x1u << 9) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_ITER (0x1u << 10) /**< \brief (US_LIN_IER) Iteration Interrupt Enable */\r
+#define US_LIN_IER_ITER_0 (0x0u << 10) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_ITER_1 (0x1u << 10) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_TXBUFE (0x1u << 11) /**< \brief (US_LIN_IER) Buffer Empty Interrupt Enable */\r
+#define US_LIN_IER_TXBUFE_0 (0x0u << 11) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_TXBUFE_1 (0x1u << 11) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_RXBUFF (0x1u << 12) /**< \brief (US_LIN_IER) Buffer Full Interrupt Enable */\r
+#define US_LIN_IER_RXBUFF_0 (0x0u << 12) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_RXBUFF_1 (0x1u << 12) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_NACK (0x1u << 13) /**< \brief (US_LIN_IER) Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Enable */\r
+#define US_LIN_IER_NACK_0 (0x0u << 13) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_NACK_1 (0x1u << 13) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_LINID (0x1u << 14) /**< \brief (US_LIN_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */\r
+#define US_LIN_IER_LINTC (0x1u << 15) /**< \brief (US_LIN_IER) LIN Transfer Conpleted Interrupt Enable */\r
+#define US_LIN_IER_RIIC (0x1u << 16) /**< \brief (US_LIN_IER) Ring Indicator Input Change Enable */\r
+#define US_LIN_IER_RIIC_0 (0x0u << 16) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_RIIC_1 (0x1u << 16) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_DSRIC (0x1u << 17) /**< \brief (US_LIN_IER) Data Set Ready Input Change Enable */\r
+#define US_LIN_IER_DSRIC_0 (0x0u << 17) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_DSRIC_1 (0x1u << 17) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_DCDIC (0x1u << 18) /**< \brief (US_LIN_IER) Data Carrier Detect Input Change Interrupt Enable */\r
+#define US_LIN_IER_DCDIC_0 (0x0u << 18) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_DCDIC_1 (0x1u << 18) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_CTSIC (0x1u << 19) /**< \brief (US_LIN_IER) Clear to Send Input Change Interrupt Enable */\r
+#define US_LIN_IER_CTSIC_0 (0x0u << 19) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_CTSIC_1 (0x1u << 19) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_LINBE (0x1u << 25) /**< \brief (US_LIN_IER) LIN Bus Error Interrupt Enable */\r
+#define US_LIN_IER_LINISFE (0x1u << 26) /**< \brief (US_LIN_IER) LIN Inconsistent Synch Field Error Interrupt Enable */\r
+#define US_LIN_IER_LINIPE (0x1u << 27) /**< \brief (US_LIN_IER) LIN Identifier Parity Interrupt Enable */\r
+#define US_LIN_IER_LINCE (0x1u << 28) /**< \brief (US_LIN_IER) LIN Checksum Error Interrupt Enable */\r
+#define US_LIN_IER_LINSNRE (0x1u << 29) /**< \brief (US_LIN_IER) LIN Slave Not Responding Error Interrupt Enable */\r
+#define US_LIN_IER_LINSTE (0x1u << 30) /**< \brief (US_LIN_IER) LIN Synch Tolerance Error Interrupt Enable */\r
+#define US_LIN_IER_LINSTE_0 (0x0u << 30) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_LINSTE_1 (0x1u << 30) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+#define US_LIN_IER_LINHTE (0x1u << 31) /**< \brief (US_LIN_IER) LIN Header Timeout Error Interrupt Enable */\r
+#define US_LIN_IER_LINHTE_0 (0x0u << 31) /**< \brief (US_LIN_IER) No Effect */\r
+#define US_LIN_IER_LINHTE_1 (0x1u << 31) /**< \brief (US_LIN_IER) Enables the interrupt */\r
+/* -------- US_SPI_SLAVE_IER : (USART Offset: 0x08) Interrupt Enable Register -------- */\r
+#define US_SPI_SLAVE_IER_RXRDY (0x1u << 0) /**< \brief (US_SPI_SLAVE_IER) Receiver Ready Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_RXRDY_0 (0x0u << 0) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_RXRDY_1 (0x1u << 0) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_TXRDY (0x1u << 1) /**< \brief (US_SPI_SLAVE_IER) Transmitter Ready Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_TXRDY_0 (0x0u << 1) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_TXRDY_1 (0x1u << 1) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_RXBRK (0x1u << 2) /**< \brief (US_SPI_SLAVE_IER) Receiver Break Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_RXBRK_0 (0x0u << 2) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_RXBRK_1 (0x1u << 2) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_ENDRX (0x1u << 3) /**< \brief (US_SPI_SLAVE_IER) End of Receive Transfer Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_ENDRX_0 (0x0u << 3) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_ENDRX_1 (0x1u << 3) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_ENDTX (0x1u << 4) /**< \brief (US_SPI_SLAVE_IER) End of Transmit Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_ENDTX_0 (0x0u << 4) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_ENDTX_1 (0x1u << 4) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_OVRE (0x1u << 5) /**< \brief (US_SPI_SLAVE_IER) Overrun Error Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_OVRE_0 (0x0u << 5) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_OVRE_1 (0x1u << 5) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_FRAME (0x1u << 6) /**< \brief (US_SPI_SLAVE_IER) Framing Error Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_FRAME_0 (0x0u << 6) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_FRAME_1 (0x1u << 6) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_PARE (0x1u << 7) /**< \brief (US_SPI_SLAVE_IER) Parity Error Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_PARE_0 (0x0u << 7) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_PARE_1 (0x1u << 7) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_TIMEOUT (0x1u << 8) /**< \brief (US_SPI_SLAVE_IER) Time-out Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_TIMEOUT_0 (0x0u << 8) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_TIMEOUT_1 (0x1u << 8) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_TXEMPTY (0x1u << 9) /**< \brief (US_SPI_SLAVE_IER) Transmitter Empty Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_TXEMPTY_0 (0x0u << 9) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_TXEMPTY_1 (0x1u << 9) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_UNRE (0x1u << 10) /**< \brief (US_SPI_SLAVE_IER) SPI Underrun Error Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_UNRE_0 (0x0u << 10) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_UNRE_1 (0x1u << 10) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_TXBUFE (0x1u << 11) /**< \brief (US_SPI_SLAVE_IER) Buffer Empty Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_TXBUFE_0 (0x0u << 11) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_TXBUFE_1 (0x1u << 11) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_RXBUFF (0x1u << 12) /**< \brief (US_SPI_SLAVE_IER) Buffer Full Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_RXBUFF_0 (0x0u << 12) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_RXBUFF_1 (0x1u << 12) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_NACK (0x1u << 13) /**< \brief (US_SPI_SLAVE_IER) Non Acknowledge Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_NACK_0 (0x0u << 13) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_NACK_1 (0x1u << 13) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_RIIC (0x1u << 16) /**< \brief (US_SPI_SLAVE_IER) Ring Indicator Input Change Enable */\r
+#define US_SPI_SLAVE_IER_RIIC_0 (0x0u << 16) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_RIIC_1 (0x1u << 16) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_DSRIC (0x1u << 17) /**< \brief (US_SPI_SLAVE_IER) Data Set Ready Input Change Enable */\r
+#define US_SPI_SLAVE_IER_DSRIC_0 (0x0u << 17) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_DSRIC_1 (0x1u << 17) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_DCDIC (0x1u << 18) /**< \brief (US_SPI_SLAVE_IER) Data Carrier Detect Input Change Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_DCDIC_0 (0x0u << 18) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_DCDIC_1 (0x1u << 18) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+#define US_SPI_SLAVE_IER_CTSIC (0x1u << 19) /**< \brief (US_SPI_SLAVE_IER) Clear to Send Input Change Interrupt Enable */\r
+#define US_SPI_SLAVE_IER_CTSIC_0 (0x0u << 19) /**< \brief (US_SPI_SLAVE_IER) No Effect */\r
+#define US_SPI_SLAVE_IER_CTSIC_1 (0x1u << 19) /**< \brief (US_SPI_SLAVE_IER) Enables the interrupt */\r
+/* -------- US_USART_IER : (USART Offset: 0x08) Interrupt Enable Register -------- */\r
+#define US_USART_IER_RXRDY (0x1u << 0) /**< \brief (US_USART_IER) Receiver Ready Interrupt Enable */\r
+#define US_USART_IER_RXRDY_0 (0x0u << 0) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_RXRDY_1 (0x1u << 0) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_TXRDY (0x1u << 1) /**< \brief (US_USART_IER) Transmitter Ready Interrupt Enable */\r
+#define US_USART_IER_TXRDY_0 (0x0u << 1) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_TXRDY_1 (0x1u << 1) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_RXBRK (0x1u << 2) /**< \brief (US_USART_IER) Receiver Break Interrupt Enable */\r
+#define US_USART_IER_RXBRK_0 (0x0u << 2) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_RXBRK_1 (0x1u << 2) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_ENDRX (0x1u << 3) /**< \brief (US_USART_IER) End of Receive Transfer Interrupt Enable */\r
+#define US_USART_IER_ENDRX_0 (0x0u << 3) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_ENDRX_1 (0x1u << 3) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_ENDTX (0x1u << 4) /**< \brief (US_USART_IER) End of Transmit Interrupt Enable */\r
+#define US_USART_IER_ENDTX_0 (0x0u << 4) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_ENDTX_1 (0x1u << 4) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_OVRE (0x1u << 5) /**< \brief (US_USART_IER) Overrun Error Interrupt Enable */\r
+#define US_USART_IER_OVRE_0 (0x0u << 5) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_OVRE_1 (0x1u << 5) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_FRAME (0x1u << 6) /**< \brief (US_USART_IER) Framing Error Interrupt Enable */\r
+#define US_USART_IER_FRAME_0 (0x0u << 6) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_FRAME_1 (0x1u << 6) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_PARE (0x1u << 7) /**< \brief (US_USART_IER) Parity Error Interrupt Enable */\r
+#define US_USART_IER_PARE_0 (0x0u << 7) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_PARE_1 (0x1u << 7) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_TIMEOUT (0x1u << 8) /**< \brief (US_USART_IER) Time-out Interrupt Enable */\r
+#define US_USART_IER_TIMEOUT_0 (0x0u << 8) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_TIMEOUT_1 (0x1u << 8) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_TXEMPTY (0x1u << 9) /**< \brief (US_USART_IER) Transmitter Empty Interrupt Enable */\r
+#define US_USART_IER_TXEMPTY_0 (0x0u << 9) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_TXEMPTY_1 (0x1u << 9) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_ITER (0x1u << 10) /**< \brief (US_USART_IER) Iteration Interrupt Enable */\r
+#define US_USART_IER_ITER_0 (0x0u << 10) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_ITER_1 (0x1u << 10) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_TXBUFE (0x1u << 11) /**< \brief (US_USART_IER) Buffer Empty Interrupt Enable */\r
+#define US_USART_IER_TXBUFE_0 (0x0u << 11) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_TXBUFE_1 (0x1u << 11) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_RXBUFF (0x1u << 12) /**< \brief (US_USART_IER) Buffer Full Interrupt Enable */\r
+#define US_USART_IER_RXBUFF_0 (0x0u << 12) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_RXBUFF_1 (0x1u << 12) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_NACK (0x1u << 13) /**< \brief (US_USART_IER) Non Acknowledge Interrupt Enable */\r
+#define US_USART_IER_NACK_0 (0x0u << 13) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_NACK_1 (0x1u << 13) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_RIIC (0x1u << 16) /**< \brief (US_USART_IER) Ring Indicator Input Change Enable */\r
+#define US_USART_IER_RIIC_0 (0x0u << 16) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_RIIC_1 (0x1u << 16) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_DSRIC (0x1u << 17) /**< \brief (US_USART_IER) Data Set Ready Input Change Enable */\r
+#define US_USART_IER_DSRIC_0 (0x0u << 17) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_DSRIC_1 (0x1u << 17) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_DCDIC (0x1u << 18) /**< \brief (US_USART_IER) Data Carrier Detect Input Change Interrupt Enable */\r
+#define US_USART_IER_DCDIC_0 (0x0u << 18) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_DCDIC_1 (0x1u << 18) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_CTSIC (0x1u << 19) /**< \brief (US_USART_IER) Clear to Send Input Change Interrupt Enable */\r
+#define US_USART_IER_CTSIC_0 (0x0u << 19) /**< \brief (US_USART_IER) No Effect */\r
+#define US_USART_IER_CTSIC_1 (0x1u << 19) /**< \brief (US_USART_IER) Enables the interrupt */\r
+#define US_USART_IER_MANE (0x1u << 20) /**< \brief (US_USART_IER) Manchester Error Interrupt Enable */\r
+#define US_USART_IER_MANEA (0x1u << 24) /**< \brief (US_USART_IER) Manchester Error Interrupt Enable */\r
+#define US_USART_IER_MANEA_0 (0x0u << 24) /**< \brief (US_USART_IER) No effect */\r
+#define US_USART_IER_MANEA_1 (0x1u << 24) /**< \brief (US_USART_IER) Enables the interrupt */\r
+/* -------- US_IER : (USART Offset: 0x08) Interrupt Enable Register -------- */\r
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) Receiver Ready Interrupt Enable */\r
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) Transmitter Ready Interrupt Enable */\r
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */\r
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */\r
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */\r
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */\r
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */\r
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */\r
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */\r
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) Transmitter Empty Interrupt Enable */\r
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Iteration Interrupt Enable */\r
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */\r
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */\r
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */\r
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Enable */\r
+#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */\r
+#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Conpleted Interrupt Enable */\r
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */\r
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */\r
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */\r
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */\r
+#define US_IER_MANE (0x1u << 20) /**< \brief (US_IER) Manchester Error Interrupt Enable */\r
+#define US_IER_MANEA (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */\r
+#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */\r
+#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */\r
+#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */\r
+#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */\r
+#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */\r
+#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */\r
+#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */\r
+\r
+/* -------- US_LIN_IDR : (USART Offset: 0x0C) Interrupt Disable Register -------- */\r
+#define US_LIN_IDR_RXRDY (0x1u << 0) /**< \brief (US_LIN_IDR) Receiver Ready Interrupt Disable */\r
+#define US_LIN_IDR_RXRDY_0 (0x0u << 0) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_RXRDY_1 (0x1u << 0) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_TXRDY (0x1u << 1) /**< \brief (US_LIN_IDR) Transmitter Ready Interrupt Disable */\r
+#define US_LIN_IDR_TXRDY_0 (0x0u << 1) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_TXRDY_1 (0x1u << 1) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_RXBRK (0x1u << 2) /**< \brief (US_LIN_IDR) Receiver Break Interrupt Disable */\r
+#define US_LIN_IDR_RXBRK_0 (0x0u << 2) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_RXBRK_1 (0x1u << 2) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_ENDRX (0x1u << 3) /**< \brief (US_LIN_IDR) End of Receive Transfer Interrupt Disable */\r
+#define US_LIN_IDR_ENDRX_0 (0x0u << 3) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_ENDRX_1 (0x1u << 3) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_ENDTX (0x1u << 4) /**< \brief (US_LIN_IDR) End of Transmit Interrupt Disable */\r
+#define US_LIN_IDR_ENDTX_0 (0x0u << 4) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_ENDTX_1 (0x1u << 4) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_OVRE (0x1u << 5) /**< \brief (US_LIN_IDR) Overrun Error Interrupt Disable */\r
+#define US_LIN_IDR_OVRE_0 (0x0u << 5) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_OVRE_1 (0x1u << 5) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_FRAME (0x1u << 6) /**< \brief (US_LIN_IDR) Framing Error Interrupt Disable */\r
+#define US_LIN_IDR_FRAME_0 (0x0u << 6) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_FRAME_1 (0x1u << 6) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_PARE (0x1u << 7) /**< \brief (US_LIN_IDR) Parity Error Interrupt Disable */\r
+#define US_LIN_IDR_PARE_0 (0x0u << 7) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_PARE_1 (0x1u << 7) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_LIN_IDR) Time-out Interrupt Disable */\r
+#define US_LIN_IDR_TIMEOUT_0 (0x0u << 8) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_TIMEOUT_1 (0x1u << 8) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_LIN_IDR) Transmitter Empty Interrupt Disable */\r
+#define US_LIN_IDR_TXEMPTY_0 (0x0u << 9) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_TXEMPTY_1 (0x1u << 9) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_ITER (0x1u << 10) /**< \brief (US_LIN_IDR) Iteration Interrupt Disable */\r
+#define US_LIN_IDR_ITER_0 (0x0u << 10) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_ITER_1 (0x1u << 10) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_TXBUFE (0x1u << 11) /**< \brief (US_LIN_IDR) Buffer Empty Interrupt Disable */\r
+#define US_LIN_IDR_TXBUFE_0 (0x0u << 11) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_TXBUFE_1 (0x1u << 11) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_RXBUFF (0x1u << 12) /**< \brief (US_LIN_IDR) Buffer Full Interrupt Disable */\r
+#define US_LIN_IDR_RXBUFF_0 (0x0u << 12) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_RXBUFF_1 (0x1u << 12) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_NACK (0x1u << 13) /**< \brief (US_LIN_IDR) Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Disable */\r
+#define US_LIN_IDR_NACK_0 (0x0u << 13) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_NACK_1 (0x1u << 13) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_LINID (0x1u << 14) /**< \brief (US_LIN_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */\r
+#define US_LIN_IDR_LINTC (0x1u << 15) /**< \brief (US_LIN_IDR) LIN Transfer Conpleted Interrupt Disable */\r
+#define US_LIN_IDR_RIIC (0x1u << 16) /**< \brief (US_LIN_IDR) Ring Indicator Input Change Disable */\r
+#define US_LIN_IDR_RIIC_0 (0x0u << 16) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_RIIC_1 (0x1u << 16) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_DSRIC (0x1u << 17) /**< \brief (US_LIN_IDR) Data Set Ready Input Change Disable */\r
+#define US_LIN_IDR_DSRIC_0 (0x0u << 17) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_DSRIC_1 (0x1u << 17) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_DCDIC (0x1u << 18) /**< \brief (US_LIN_IDR) Data Carrier Detect Input Change Interrupt Disable */\r
+#define US_LIN_IDR_DCDIC_0 (0x0u << 18) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_DCDIC_1 (0x1u << 18) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_CTSIC (0x1u << 19) /**< \brief (US_LIN_IDR) Clear to Send Input Change Interrupt Disable */\r
+#define US_LIN_IDR_CTSIC_0 (0x0u << 19) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_CTSIC_1 (0x1u << 19) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_LINBE (0x1u << 25) /**< \brief (US_LIN_IDR) LIN Bus Error Interrupt Disable */\r
+#define US_LIN_IDR_LINISFE (0x1u << 26) /**< \brief (US_LIN_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */\r
+#define US_LIN_IDR_LINIPE (0x1u << 27) /**< \brief (US_LIN_IDR) LIN Identifier Parity Interrupt Disable */\r
+#define US_LIN_IDR_LINCE (0x1u << 28) /**< \brief (US_LIN_IDR) LIN Checksum Error Interrupt Disable */\r
+#define US_LIN_IDR_LINSNRE (0x1u << 29) /**< \brief (US_LIN_IDR) LIN Slave Not Responding Error Interrupt Disable */\r
+#define US_LIN_IDR_LINSTE (0x1u << 30) /**< \brief (US_LIN_IDR) LIN Synch Tolerance Error Interrupt Disable */\r
+#define US_LIN_IDR_LINSTE_0 (0x0u << 30) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_LINSTE_1 (0x1u << 30) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+#define US_LIN_IDR_LINHTE (0x1u << 31) /**< \brief (US_LIN_IDR) LIN Header Timeout Error Interrupt Disable */\r
+#define US_LIN_IDR_LINHTE_0 (0x0u << 31) /**< \brief (US_LIN_IDR) No Effect */\r
+#define US_LIN_IDR_LINHTE_1 (0x1u << 31) /**< \brief (US_LIN_IDR) Disables the interrupt */\r
+/* -------- US_SPI_SLAVE_IDR : (USART Offset: 0x0C) Interrupt Disable Register -------- */\r
+#define US_SPI_SLAVE_IDR_RXRDY (0x1u << 0) /**< \brief (US_SPI_SLAVE_IDR) Receiver Ready Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_RXRDY_0 (0x0u << 0) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_RXRDY_1 (0x1u << 0) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_TXRDY (0x1u << 1) /**< \brief (US_SPI_SLAVE_IDR) Transmitter Ready Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_TXRDY_0 (0x0u << 1) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_TXRDY_1 (0x1u << 1) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_RXBRK (0x1u << 2) /**< \brief (US_SPI_SLAVE_IDR) Receiver Break Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_RXBRK_0 (0x0u << 2) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_RXBRK_1 (0x1u << 2) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_ENDRX (0x1u << 3) /**< \brief (US_SPI_SLAVE_IDR) End of Receive Transfer Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_ENDRX_0 (0x0u << 3) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_ENDRX_1 (0x1u << 3) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_ENDTX (0x1u << 4) /**< \brief (US_SPI_SLAVE_IDR) End of Transmit Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_ENDTX_0 (0x0u << 4) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_ENDTX_1 (0x1u << 4) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_OVRE (0x1u << 5) /**< \brief (US_SPI_SLAVE_IDR) Overrun Error Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_OVRE_0 (0x0u << 5) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_OVRE_1 (0x1u << 5) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_FRAME (0x1u << 6) /**< \brief (US_SPI_SLAVE_IDR) Framing Error Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_FRAME_0 (0x0u << 6) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_FRAME_1 (0x1u << 6) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_PARE (0x1u << 7) /**< \brief (US_SPI_SLAVE_IDR) Parity Error Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_PARE_0 (0x0u << 7) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_PARE_1 (0x1u << 7) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_SPI_SLAVE_IDR) Time-out Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_TIMEOUT_0 (0x0u << 8) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_TIMEOUT_1 (0x1u << 8) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_SPI_SLAVE_IDR) Transmitter Empty Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_TXEMPTY_0 (0x0u << 9) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_TXEMPTY_1 (0x1u << 9) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_UNRE (0x1u << 10) /**< \brief (US_SPI_SLAVE_IDR) SPI Underrun Error Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_UNRE_0 (0x0u << 10) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_UNRE_1 (0x1u << 10) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_TXBUFE (0x1u << 11) /**< \brief (US_SPI_SLAVE_IDR) Buffer Empty Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_TXBUFE_0 (0x0u << 11) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_TXBUFE_1 (0x1u << 11) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_RXBUFF (0x1u << 12) /**< \brief (US_SPI_SLAVE_IDR) Buffer Full Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_RXBUFF_0 (0x0u << 12) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_RXBUFF_1 (0x1u << 12) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_NACK (0x1u << 13) /**< \brief (US_SPI_SLAVE_IDR) Non Acknowledge Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_NACK_0 (0x0u << 13) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_NACK_1 (0x1u << 13) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_RIIC (0x1u << 16) /**< \brief (US_SPI_SLAVE_IDR) Ring Indicator Input Change Disable */\r
+#define US_SPI_SLAVE_IDR_RIIC_0 (0x0u << 16) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_RIIC_1 (0x1u << 16) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_DSRIC (0x1u << 17) /**< \brief (US_SPI_SLAVE_IDR) Data Set Ready Input Change Disable */\r
+#define US_SPI_SLAVE_IDR_DSRIC_0 (0x0u << 17) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_DSRIC_1 (0x1u << 17) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_DCDIC (0x1u << 18) /**< \brief (US_SPI_SLAVE_IDR) Data Carrier Detect Input Change Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_DCDIC_0 (0x0u << 18) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_DCDIC_1 (0x1u << 18) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+#define US_SPI_SLAVE_IDR_CTSIC (0x1u << 19) /**< \brief (US_SPI_SLAVE_IDR) Clear to Send Input Change Interrupt Disable */\r
+#define US_SPI_SLAVE_IDR_CTSIC_0 (0x0u << 19) /**< \brief (US_SPI_SLAVE_IDR) No Effect */\r
+#define US_SPI_SLAVE_IDR_CTSIC_1 (0x1u << 19) /**< \brief (US_SPI_SLAVE_IDR) Disables the interrupt */\r
+/* -------- US_USART_IDR : (USART Offset: 0x0C) Interrupt Disable Register -------- */\r
+#define US_USART_IDR_RXRDY (0x1u << 0) /**< \brief (US_USART_IDR) Receiver Ready Interrupt Disable */\r
+#define US_USART_IDR_RXRDY_0 (0x0u << 0) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_RXRDY_1 (0x1u << 0) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_TXRDY (0x1u << 1) /**< \brief (US_USART_IDR) Transmitter Ready Interrupt Disable */\r
+#define US_USART_IDR_TXRDY_0 (0x0u << 1) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_TXRDY_1 (0x1u << 1) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_RXBRK (0x1u << 2) /**< \brief (US_USART_IDR) Receiver Break Interrupt Disable */\r
+#define US_USART_IDR_RXBRK_0 (0x0u << 2) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_RXBRK_1 (0x1u << 2) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_ENDRX (0x1u << 3) /**< \brief (US_USART_IDR) End of Receive Transfer Interrupt Disable */\r
+#define US_USART_IDR_ENDRX_0 (0x0u << 3) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_ENDRX_1 (0x1u << 3) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_ENDTX (0x1u << 4) /**< \brief (US_USART_IDR) End of Transmit Interrupt Disable */\r
+#define US_USART_IDR_ENDTX_0 (0x0u << 4) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_ENDTX_1 (0x1u << 4) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_OVRE (0x1u << 5) /**< \brief (US_USART_IDR) Overrun Error Interrupt Disable */\r
+#define US_USART_IDR_OVRE_0 (0x0u << 5) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_OVRE_1 (0x1u << 5) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_FRAME (0x1u << 6) /**< \brief (US_USART_IDR) Framing Error Interrupt Disable */\r
+#define US_USART_IDR_FRAME_0 (0x0u << 6) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_FRAME_1 (0x1u << 6) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_PARE (0x1u << 7) /**< \brief (US_USART_IDR) Parity Error Interrupt Disable */\r
+#define US_USART_IDR_PARE_0 (0x0u << 7) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_PARE_1 (0x1u << 7) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_USART_IDR) Time-out Interrupt Disable */\r
+#define US_USART_IDR_TIMEOUT_0 (0x0u << 8) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_TIMEOUT_1 (0x1u << 8) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_USART_IDR) Transmitter Empty Interrupt Disable */\r
+#define US_USART_IDR_TXEMPTY_0 (0x0u << 9) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_TXEMPTY_1 (0x1u << 9) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_ITER (0x1u << 10) /**< \brief (US_USART_IDR) Iteration Interrupt Disable */\r
+#define US_USART_IDR_ITER_0 (0x0u << 10) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_ITER_1 (0x1u << 10) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_TXBUFE (0x1u << 11) /**< \brief (US_USART_IDR) Buffer Empty Interrupt Disable */\r
+#define US_USART_IDR_TXBUFE_0 (0x0u << 11) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_TXBUFE_1 (0x1u << 11) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_RXBUFF (0x1u << 12) /**< \brief (US_USART_IDR) Buffer Full Interrupt Disable */\r
+#define US_USART_IDR_RXBUFF_0 (0x0u << 12) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_RXBUFF_1 (0x1u << 12) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_NACK (0x1u << 13) /**< \brief (US_USART_IDR) Non Acknowledge Interrupt Disable */\r
+#define US_USART_IDR_NACK_0 (0x0u << 13) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_NACK_1 (0x1u << 13) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_RIIC (0x1u << 16) /**< \brief (US_USART_IDR) Ring Indicator Input Change Disable */\r
+#define US_USART_IDR_RIIC_0 (0x0u << 16) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_RIIC_1 (0x1u << 16) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_DSRIC (0x1u << 17) /**< \brief (US_USART_IDR) Data Set Ready Input Change Disable */\r
+#define US_USART_IDR_DSRIC_0 (0x0u << 17) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_DSRIC_1 (0x1u << 17) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_DCDIC (0x1u << 18) /**< \brief (US_USART_IDR) Data Carrier Detect Input Change Interrupt Disable */\r
+#define US_USART_IDR_DCDIC_0 (0x0u << 18) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_DCDIC_1 (0x1u << 18) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_CTSIC (0x1u << 19) /**< \brief (US_USART_IDR) Clear to Send Input Change Interrupt Disable */\r
+#define US_USART_IDR_CTSIC_0 (0x0u << 19) /**< \brief (US_USART_IDR) No Effect */\r
+#define US_USART_IDR_CTSIC_1 (0x1u << 19) /**< \brief (US_USART_IDR) Disables the interrupt */\r
+#define US_USART_IDR_MANE (0x1u << 20) /**< \brief (US_USART_IDR) Manchester Error Interrupt Disable */\r
+#define US_USART_IDR_MANEA (0x1u << 24) /**< \brief (US_USART_IDR) Manchester Error Interrupt Disable */\r
+#define US_USART_IDR_MANEA_0 (0x0u << 24) /**< \brief (US_USART_IDR) No effect */\r
+#define US_USART_IDR_MANEA_1 (0x1u << 24) /**< \brief (US_USART_IDR) Disables the corresponding interrupt */\r
+/* -------- US_IDR : (USART Offset: 0x0C) Interrupt Disable Register -------- */\r
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) Receiver Ready Interrupt Disable */\r
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) Transmitter Ready Interrupt Disable */\r
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */\r
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */\r
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */\r
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */\r
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */\r
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */\r
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */\r
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) Transmitter Empty Interrupt Disable */\r
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Iteration Interrupt Disable */\r
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */\r
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */\r
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */\r
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Disable */\r
+#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */\r
+#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Conpleted Interrupt Disable */\r
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */\r
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */\r
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */\r
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */\r
+#define US_IDR_MANE (0x1u << 20) /**< \brief (US_IDR) Manchester Error Interrupt Disable */\r
+#define US_IDR_MANEA (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */\r
+#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */\r
+#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */\r
+#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */\r
+#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */\r
+#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */\r
+#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */\r
+#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */\r
+\r
+/* -------- US_LIN_IMR : (USART Offset: 0x10) Interrupt Mask Register -------- */\r
+#define US_LIN_IMR_RXRDY (0x1u << 0) /**< \brief (US_LIN_IMR) RXRDY Interrupt Mask */\r
+#define US_LIN_IMR_RXRDY_0 (0x0u << 0) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_RXRDY_1 (0x1u << 0) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_TXRDY (0x1u << 1) /**< \brief (US_LIN_IMR) TXRDY Interrupt Mask */\r
+#define US_LIN_IMR_TXRDY_0 (0x0u << 1) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_TXRDY_1 (0x1u << 1) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_RXBRK (0x1u << 2) /**< \brief (US_LIN_IMR) Receiver Break Interrupt Mask */\r
+#define US_LIN_IMR_RXBRK_0 (0x0u << 2) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_RXBRK_1 (0x1u << 2) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_ENDRX (0x1u << 3) /**< \brief (US_LIN_IMR) End of Receive Transfer Interrupt Mask */\r
+#define US_LIN_IMR_ENDRX_0 (0x0u << 3) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_ENDRX_1 (0x1u << 3) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_ENDTX (0x1u << 4) /**< \brief (US_LIN_IMR) End of Transmit Interrupt Mask */\r
+#define US_LIN_IMR_ENDTX_0 (0x0u << 4) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_ENDTX_1 (0x1u << 4) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_OVRE (0x1u << 5) /**< \brief (US_LIN_IMR) Overrun Error Interrupt Mask */\r
+#define US_LIN_IMR_OVRE_0 (0x0u << 5) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_OVRE_1 (0x1u << 5) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_FRAME (0x1u << 6) /**< \brief (US_LIN_IMR) Framing Error Interrupt Mask */\r
+#define US_LIN_IMR_FRAME_0 (0x0u << 6) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_FRAME_1 (0x1u << 6) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_PARE (0x1u << 7) /**< \brief (US_LIN_IMR) Parity Error Interrupt Mask */\r
+#define US_LIN_IMR_PARE_0 (0x0u << 7) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_PARE_1 (0x1u << 7) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_LIN_IMR) Time-out Interrupt Mask */\r
+#define US_LIN_IMR_TIMEOUT_0 (0x0u << 8) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_TIMEOUT_1 (0x1u << 8) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_LIN_IMR) TXEMPTY Interrupt Mask */\r
+#define US_LIN_IMR_TXEMPTY_0 (0x0u << 9) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_TXEMPTY_1 (0x1u << 9) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_ITER (0x1u << 10) /**< \brief (US_LIN_IMR) Iteration Interrupt Mask */\r
+#define US_LIN_IMR_ITER_0 (0x0u << 10) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_ITER_1 (0x1u << 10) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_TXBUFE (0x1u << 11) /**< \brief (US_LIN_IMR) Buffer Empty Interrupt Mask */\r
+#define US_LIN_IMR_TXBUFE_0 (0x0u << 11) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_TXBUFE_1 (0x1u << 11) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_RXBUFF (0x1u << 12) /**< \brief (US_LIN_IMR) Buffer Full Interrupt Mask */\r
+#define US_LIN_IMR_RXBUFF_0 (0x0u << 12) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_RXBUFF_1 (0x1u << 12) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_NACK (0x1u << 13) /**< \brief (US_LIN_IMR) Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask */\r
+#define US_LIN_IMR_NACK_0 (0x0u << 13) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_NACK_1 (0x1u << 13) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_LINID (0x1u << 14) /**< \brief (US_LIN_IMR) LIN Identifier Sent or LIN Received Interrupt Mask */\r
+#define US_LIN_IMR_LINTC (0x1u << 15) /**< \brief (US_LIN_IMR) LIN Transfer Conpleted Interrupt Mask */\r
+#define US_LIN_IMR_RIIC (0x1u << 16) /**< \brief (US_LIN_IMR) Ring Indicator Input Change Mask */\r
+#define US_LIN_IMR_RIIC_0 (0x0u << 16) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_RIIC_1 (0x1u << 16) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_DSRIC (0x1u << 17) /**< \brief (US_LIN_IMR) Data Set Ready Input Change Mask */\r
+#define US_LIN_IMR_DSRIC_0 (0x0u << 17) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_DSRIC_1 (0x1u << 17) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_DCDIC (0x1u << 18) /**< \brief (US_LIN_IMR) Data Carrier Detect Input Change Interrupt Mask */\r
+#define US_LIN_IMR_DCDIC_0 (0x0u << 18) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_DCDIC_1 (0x1u << 18) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_CTSIC (0x1u << 19) /**< \brief (US_LIN_IMR) Clear to Send Input Change Interrupt Mask */\r
+#define US_LIN_IMR_CTSIC_0 (0x0u << 19) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_CTSIC_1 (0x1u << 19) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_LINBE (0x1u << 25) /**< \brief (US_LIN_IMR) LIN Bus Error Interrupt Mask */\r
+#define US_LIN_IMR_LINISFE (0x1u << 26) /**< \brief (US_LIN_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */\r
+#define US_LIN_IMR_LINIPE (0x1u << 27) /**< \brief (US_LIN_IMR) LIN Identifier Parity Interrupt Mask */\r
+#define US_LIN_IMR_LINCE (0x1u << 28) /**< \brief (US_LIN_IMR) LIN Checksum Error Interrupt Mask */\r
+#define US_LIN_IMR_LINSNRE (0x1u << 29) /**< \brief (US_LIN_IMR) LIN Slave Not Responding Error Interrupt Mask */\r
+#define US_LIN_IMR_LINSTE (0x1u << 30) /**< \brief (US_LIN_IMR) LIN Synch Tolerance Error Interrupt Mask */\r
+#define US_LIN_IMR_LINSTE_0 (0x0u << 30) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_LINSTE_1 (0x1u << 30) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+#define US_LIN_IMR_LINHTE (0x1u << 31) /**< \brief (US_LIN_IMR) LIN Header Timeout Error Interrupt Mask */\r
+#define US_LIN_IMR_LINHTE_0 (0x0u << 31) /**< \brief (US_LIN_IMR) The interrupt is disabled */\r
+#define US_LIN_IMR_LINHTE_1 (0x1u << 31) /**< \brief (US_LIN_IMR) The interrupt is enabled */\r
+/* -------- US_SPI_SLAVE_IMR : (USART Offset: 0x10) Interrupt Mask Register -------- */\r
+#define US_SPI_SLAVE_IMR_RXRDY (0x1u << 0) /**< \brief (US_SPI_SLAVE_IMR) RXRDY Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_RXRDY_0 (0x0u << 0) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_RXRDY_1 (0x1u << 0) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_TXRDY (0x1u << 1) /**< \brief (US_SPI_SLAVE_IMR) TXRDY Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_TXRDY_0 (0x0u << 1) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_TXRDY_1 (0x1u << 1) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_RXBRK (0x1u << 2) /**< \brief (US_SPI_SLAVE_IMR) Receiver Break Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_RXBRK_0 (0x0u << 2) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_RXBRK_1 (0x1u << 2) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_ENDRX (0x1u << 3) /**< \brief (US_SPI_SLAVE_IMR) End of Receive Transfer Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_ENDRX_0 (0x0u << 3) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_ENDRX_1 (0x1u << 3) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_ENDTX (0x1u << 4) /**< \brief (US_SPI_SLAVE_IMR) End of Transmit Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_ENDTX_0 (0x0u << 4) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_ENDTX_1 (0x1u << 4) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_OVRE (0x1u << 5) /**< \brief (US_SPI_SLAVE_IMR) Overrun Error Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_OVRE_0 (0x0u << 5) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_OVRE_1 (0x1u << 5) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_FRAME (0x1u << 6) /**< \brief (US_SPI_SLAVE_IMR) Framing Error Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_FRAME_0 (0x0u << 6) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_FRAME_1 (0x1u << 6) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_PARE (0x1u << 7) /**< \brief (US_SPI_SLAVE_IMR) Parity Error Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_PARE_0 (0x0u << 7) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_PARE_1 (0x1u << 7) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_SPI_SLAVE_IMR) Time-out Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_TIMEOUT_0 (0x0u << 8) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_TIMEOUT_1 (0x1u << 8) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_SPI_SLAVE_IMR) TXEMPTY Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_TXEMPTY_0 (0x0u << 9) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_TXEMPTY_1 (0x1u << 9) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_UNRE (0x1u << 10) /**< \brief (US_SPI_SLAVE_IMR) SPI Underrun Error Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_UNRE_0 (0x0u << 10) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_UNRE_1 (0x1u << 10) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_TXBUFE (0x1u << 11) /**< \brief (US_SPI_SLAVE_IMR) Buffer Empty Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_TXBUFE_0 (0x0u << 11) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_TXBUFE_1 (0x1u << 11) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_RXBUFF (0x1u << 12) /**< \brief (US_SPI_SLAVE_IMR) Buffer Full Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_RXBUFF_0 (0x0u << 12) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_RXBUFF_1 (0x1u << 12) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_NACK (0x1u << 13) /**< \brief (US_SPI_SLAVE_IMR) Non Acknowledge Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_NACK_0 (0x0u << 13) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_NACK_1 (0x1u << 13) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_RIIC (0x1u << 16) /**< \brief (US_SPI_SLAVE_IMR) Ring Indicator Input Change Mask */\r
+#define US_SPI_SLAVE_IMR_RIIC_0 (0x0u << 16) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_RIIC_1 (0x1u << 16) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_DSRIC (0x1u << 17) /**< \brief (US_SPI_SLAVE_IMR) Data Set Ready Input Change Mask */\r
+#define US_SPI_SLAVE_IMR_DSRIC_0 (0x0u << 17) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_DSRIC_1 (0x1u << 17) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_DCDIC (0x1u << 18) /**< \brief (US_SPI_SLAVE_IMR) Data Carrier Detect Input Change Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_DCDIC_0 (0x0u << 18) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_DCDIC_1 (0x1u << 18) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+#define US_SPI_SLAVE_IMR_CTSIC (0x1u << 19) /**< \brief (US_SPI_SLAVE_IMR) Clear to Send Input Change Interrupt Mask */\r
+#define US_SPI_SLAVE_IMR_CTSIC_0 (0x0u << 19) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is disabled */\r
+#define US_SPI_SLAVE_IMR_CTSIC_1 (0x1u << 19) /**< \brief (US_SPI_SLAVE_IMR) The interrupt is enabled */\r
+/* -------- US_USART_IMR : (USART Offset: 0x10) Interrupt Mask Register -------- */\r
+#define US_USART_IMR_RXRDY (0x1u << 0) /**< \brief (US_USART_IMR) RXRDY Interrupt Mask */\r
+#define US_USART_IMR_RXRDY_0 (0x0u << 0) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_RXRDY_1 (0x1u << 0) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_TXRDY (0x1u << 1) /**< \brief (US_USART_IMR) TXRDY Interrupt Mask */\r
+#define US_USART_IMR_TXRDY_0 (0x0u << 1) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_TXRDY_1 (0x1u << 1) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_RXBRK (0x1u << 2) /**< \brief (US_USART_IMR) Receiver Break Interrupt Mask */\r
+#define US_USART_IMR_RXBRK_0 (0x0u << 2) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_RXBRK_1 (0x1u << 2) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_ENDRX (0x1u << 3) /**< \brief (US_USART_IMR) End of Receive Transfer Interrupt Mask */\r
+#define US_USART_IMR_ENDRX_0 (0x0u << 3) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_ENDRX_1 (0x1u << 3) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_ENDTX (0x1u << 4) /**< \brief (US_USART_IMR) End of Transmit Interrupt Mask */\r
+#define US_USART_IMR_ENDTX_0 (0x0u << 4) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_ENDTX_1 (0x1u << 4) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_OVRE (0x1u << 5) /**< \brief (US_USART_IMR) Overrun Error Interrupt Mask */\r
+#define US_USART_IMR_OVRE_0 (0x0u << 5) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_OVRE_1 (0x1u << 5) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_FRAME (0x1u << 6) /**< \brief (US_USART_IMR) Framing Error Interrupt Mask */\r
+#define US_USART_IMR_FRAME_0 (0x0u << 6) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_FRAME_1 (0x1u << 6) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_PARE (0x1u << 7) /**< \brief (US_USART_IMR) Parity Error Interrupt Mask */\r
+#define US_USART_IMR_PARE_0 (0x0u << 7) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_PARE_1 (0x1u << 7) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_USART_IMR) Time-out Interrupt Mask */\r
+#define US_USART_IMR_TIMEOUT_0 (0x0u << 8) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_TIMEOUT_1 (0x1u << 8) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_USART_IMR) TXEMPTY Interrupt Mask */\r
+#define US_USART_IMR_TXEMPTY_0 (0x0u << 9) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_TXEMPTY_1 (0x1u << 9) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_ITER (0x1u << 10) /**< \brief (US_USART_IMR) Iteration Interrupt Mask */\r
+#define US_USART_IMR_ITER_0 (0x0u << 10) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_ITER_1 (0x1u << 10) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_TXBUFE (0x1u << 11) /**< \brief (US_USART_IMR) Buffer Empty Interrupt Mask */\r
+#define US_USART_IMR_TXBUFE_0 (0x0u << 11) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_TXBUFE_1 (0x1u << 11) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_RXBUFF (0x1u << 12) /**< \brief (US_USART_IMR) Buffer Full Interrupt Mask */\r
+#define US_USART_IMR_RXBUFF_0 (0x0u << 12) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_RXBUFF_1 (0x1u << 12) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_NACK (0x1u << 13) /**< \brief (US_USART_IMR) Non Acknowledge Interrupt Mask */\r
+#define US_USART_IMR_NACK_0 (0x0u << 13) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_NACK_1 (0x1u << 13) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_RIIC (0x1u << 16) /**< \brief (US_USART_IMR) Ring Indicator Input Change Mask */\r
+#define US_USART_IMR_RIIC_0 (0x0u << 16) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_RIIC_1 (0x1u << 16) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_DSRIC (0x1u << 17) /**< \brief (US_USART_IMR) Data Set Ready Input Change Mask */\r
+#define US_USART_IMR_DSRIC_0 (0x0u << 17) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_DSRIC_1 (0x1u << 17) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_DCDIC (0x1u << 18) /**< \brief (US_USART_IMR) Data Carrier Detect Input Change Interrupt Mask */\r
+#define US_USART_IMR_DCDIC_0 (0x0u << 18) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_DCDIC_1 (0x1u << 18) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_CTSIC (0x1u << 19) /**< \brief (US_USART_IMR) Clear to Send Input Change Interrupt Mask */\r
+#define US_USART_IMR_CTSIC_0 (0x0u << 19) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_CTSIC_1 (0x1u << 19) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+#define US_USART_IMR_MANE (0x1u << 20) /**< \brief (US_USART_IMR) */\r
+#define US_USART_IMR_MANEA (0x1u << 24) /**< \brief (US_USART_IMR) Manchester Error Interrupt Mask */\r
+#define US_USART_IMR_MANEA_0 (0x0u << 24) /**< \brief (US_USART_IMR) The interrupt is disabled */\r
+#define US_USART_IMR_MANEA_1 (0x1u << 24) /**< \brief (US_USART_IMR) The interrupt is enabled */\r
+/* -------- US_IMR : (USART Offset: 0x10) Interrupt Mask Register -------- */\r
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */\r
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */\r
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */\r
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */\r
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */\r
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */\r
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */\r
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */\r
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */\r
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */\r
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Iteration Interrupt Mask */\r
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */\r
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */\r
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */\r
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask */\r
+#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Received Interrupt Mask */\r
+#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Conpleted Interrupt Mask */\r
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */\r
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */\r
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */\r
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */\r
+#define US_IMR_MANE (0x1u << 20) /**< \brief (US_IMR) */\r
+#define US_IMR_MANEA (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */\r
+#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */\r
+#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */\r
+#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */\r
+#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */\r
+#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */\r
+#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */\r
+#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */\r
+\r
+/* -------- US_LIN_CSR : (USART Offset: 0x14) Channel Status Register -------- */\r
+#define US_LIN_CSR_RXRDY (0x1u << 0) /**< \brief (US_LIN_CSR) Receiver Ready */\r
+#define US_LIN_CSR_RXRDY_0 (0x0u << 0) /**< \brief (US_LIN_CSR) No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled */\r
+#define US_LIN_CSR_RXRDY_1 (0x1u << 0) /**< \brief (US_LIN_CSR) At least one complete character has been received and RHR has not yet been read */\r
+#define US_LIN_CSR_TXRDY (0x1u << 1) /**< \brief (US_LIN_CSR) Transmitter Ready */\r
+#define US_LIN_CSR_TXRDY_0 (0x0u << 1) /**< \brief (US_LIN_CSR) A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 */\r
+#define US_LIN_CSR_TXRDY_1 (0x1u << 1) /**< \brief (US_LIN_CSR) There is no character in the THR */\r
+#define US_LIN_CSR_RXBRK (0x1u << 2) /**< \brief (US_LIN_CSR) Break Received/End of Break */\r
+#define US_LIN_CSR_RXBRK_0 (0x0u << 2) /**< \brief (US_LIN_CSR) No Break received or End of Break detected since the last RSTSTA */\r
+#define US_LIN_CSR_RXBRK_1 (0x1u << 2) /**< \brief (US_LIN_CSR) Break Received or End of Break detected since the last RSTSTA */\r
+#define US_LIN_CSR_ENDRX (0x1u << 3) /**< \brief (US_LIN_CSR) End of Receiver Transfer */\r
+#define US_LIN_CSR_ENDRX_0 (0x0u << 3) /**< \brief (US_LIN_CSR) The End of Transfer signal from the Receive PDC channel is inactive */\r
+#define US_LIN_CSR_ENDRX_1 (0x1u << 3) /**< \brief (US_LIN_CSR) The End of Transfer signal from the Receive PDC channel is active */\r
+#define US_LIN_CSR_ENDTX (0x1u << 4) /**< \brief (US_LIN_CSR) End of Transmitter Transfer */\r
+#define US_LIN_CSR_ENDTX_0 (0x0u << 4) /**< \brief (US_LIN_CSR) The End of Transfer signal from the Transmit PDC channel is inactive */\r
+#define US_LIN_CSR_ENDTX_1 (0x1u << 4) /**< \brief (US_LIN_CSR) The End of Transfer signal from the Transmit PDC channel is active */\r
+#define US_LIN_CSR_OVRE (0x1u << 5) /**< \brief (US_LIN_CSR) Overrun Error */\r
+#define US_LIN_CSR_OVRE_0 (0x0u << 5) /**< \brief (US_LIN_CSR) No overrun error has occurred since since the last RSTSTA */\r
+#define US_LIN_CSR_OVRE_1 (0x1u << 5) /**< \brief (US_LIN_CSR) At least one overrun error has occurred since the last RSTSTA */\r
+#define US_LIN_CSR_FRAME (0x1u << 6) /**< \brief (US_LIN_CSR) Framing Error */\r
+#define US_LIN_CSR_FRAME_0 (0x0u << 6) /**< \brief (US_LIN_CSR) No stop bit has been detected low since the last RSTSTA */\r
+#define US_LIN_CSR_FRAME_1 (0x1u << 6) /**< \brief (US_LIN_CSR) At least one stop bit has been detected low since the last RSTSTA */\r
+#define US_LIN_CSR_PARE (0x1u << 7) /**< \brief (US_LIN_CSR) Parity Error */\r
+#define US_LIN_CSR_PARE_0 (0x0u << 7) /**< \brief (US_LIN_CSR) No parity error has been detected since the last RSTSTA */\r
+#define US_LIN_CSR_PARE_1 (0x1u << 7) /**< \brief (US_LIN_CSR) At least one parity error has been detected since the last RSTSTA */\r
+#define US_LIN_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_LIN_CSR) Receiver Time-out */\r
+#define US_LIN_CSR_TIMEOUT_0 (0x0u << 8) /**< \brief (US_LIN_CSR) There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 */\r
+#define US_LIN_CSR_TIMEOUT_1 (0x1u << 8) /**< \brief (US_LIN_CSR) There has been a time-out since the last Start Time-out command */\r
+#define US_LIN_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_LIN_CSR) Transmitter Empty */\r
+#define US_LIN_CSR_TXEMPTY_0 (0x0u << 9) /**< \brief (US_LIN_CSR) There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled */\r
+#define US_LIN_CSR_TXEMPTY_1 (0x1u << 9) /**< \brief (US_LIN_CSR) There is at least one character in either THR or the Transmit Shift Register */\r
+#define US_LIN_CSR_ITER (0x1u << 10) /**< \brief (US_LIN_CSR) Max number of Repetitions Reached */\r
+#define US_LIN_CSR_ITER_0 (0x0u << 10) /**< \brief (US_LIN_CSR) Maximum number of repetitions has not been reached since the last RSIT */\r
+#define US_LIN_CSR_ITER_1 (0x1u << 10) /**< \brief (US_LIN_CSR) Maximum number of repetitions has been reached since the last RSIT */\r
+#define US_LIN_CSR_TXBUFE (0x1u << 11) /**< \brief (US_LIN_CSR) Transmission Buffer Empty */\r
+#define US_LIN_CSR_TXBUFE_0 (0x0u << 11) /**< \brief (US_LIN_CSR) The signal Buffer Empty from the Transmit PDC channel is inactive */\r
+#define US_LIN_CSR_TXBUFE_1 (0x1u << 11) /**< \brief (US_LIN_CSR) The signal Buffer Empty from the Transmit PDC channel is active */\r
+#define US_LIN_CSR_RXBUFF (0x1u << 12) /**< \brief (US_LIN_CSR) Reception Buffer Full */\r
+#define US_LIN_CSR_RXBUFF_0 (0x0u << 12) /**< \brief (US_LIN_CSR) The signal Buffer Full from the Receive PDC channel is inactive */\r
+#define US_LIN_CSR_RXBUFF_1 (0x1u << 12) /**< \brief (US_LIN_CSR) The signal Buffer Full from the Receive PDC channel is active */\r
+#define US_LIN_CSR_NACK (0x1u << 13) /**< \brief (US_LIN_CSR) Non Acknowledge or LIN Break Sent or LIN Break Received */\r
+#define US_LIN_CSR_NACK_0 (0x0u << 13) /**< \brief (US_LIN_CSR) No Non Acknowledge has not been detected since the last RSTNACK */\r
+#define US_LIN_CSR_NACK_1 (0x1u << 13) /**< \brief (US_LIN_CSR) At least one Non Acknowledge has been detected since the last RSTNACK */\r
+#define US_LIN_CSR_LINID (0x1u << 14) /**< \brief (US_LIN_CSR) LIN Identifier Sent or LIN Identifier Received */\r
+#define US_LIN_CSR_LINTC (0x1u << 15) /**< \brief (US_LIN_CSR) LIN Transfer Conpleted */\r
+#define US_LIN_CSR_RIIC (0x1u << 16) /**< \brief (US_LIN_CSR) Ring Indicator Input Change Flag */\r
+#define US_LIN_CSR_RIIC_0 (0x0u << 16) /**< \brief (US_LIN_CSR) No input change has been detected on the RI pin since the last read of CSR */\r
+#define US_LIN_CSR_RIIC_1 (0x1u << 16) /**< \brief (US_LIN_CSR) At least one input change has been detected on the RI pin since the last read of CSR */\r
+#define US_LIN_CSR_DSRIC (0x1u << 17) /**< \brief (US_LIN_CSR) Data Set Ready Input Change Flag */\r
+#define US_LIN_CSR_DSRIC_0 (0x0u << 17) /**< \brief (US_LIN_CSR) No input change has been detected on the DSR pin since the last read of CSR */\r
+#define US_LIN_CSR_DSRIC_1 (0x1u << 17) /**< \brief (US_LIN_CSR) At least one input change has been detected on the DSR pin since the last read of CSR */\r
+#define US_LIN_CSR_DCDIC (0x1u << 18) /**< \brief (US_LIN_CSR) Data Carrier Detect Input Change Flag */\r
+#define US_LIN_CSR_DCDIC_0 (0x0u << 18) /**< \brief (US_LIN_CSR) No input change has been detected on the DCD pin since the last read of CSR */\r
+#define US_LIN_CSR_DCDIC_1 (0x1u << 18) /**< \brief (US_LIN_CSR) At least one input change has been detected on the DCD pin since the last read of CSR */\r
+#define US_LIN_CSR_CTSIC (0x1u << 19) /**< \brief (US_LIN_CSR) Clear to Send Input Change Flag */\r
+#define US_LIN_CSR_CTSIC_0 (0x0u << 19) /**< \brief (US_LIN_CSR) No input change has been detected on the CTS pin since the last read of CSR */\r
+#define US_LIN_CSR_CTSIC_1 (0x1u << 19) /**< \brief (US_LIN_CSR) At least one input change has been detected on the CTS pin since the last read of CSR */\r
+#define US_LIN_CSR_RI (0x1u << 20) /**< \brief (US_LIN_CSR) Image of RI Input */\r
+#define US_LIN_CSR_RI_0 (0x0u << 20) /**< \brief (US_LIN_CSR) RI is at 0 */\r
+#define US_LIN_CSR_RI_1 (0x1u << 20) /**< \brief (US_LIN_CSR) RI is at 1 */\r
+#define US_LIN_CSR_DSR (0x1u << 21) /**< \brief (US_LIN_CSR) Image of DSR Input */\r
+#define US_LIN_CSR_DSR_0 (0x0u << 21) /**< \brief (US_LIN_CSR) DSR is at 0 */\r
+#define US_LIN_CSR_DSR_1 (0x1u << 21) /**< \brief (US_LIN_CSR) DSR is at 1 */\r
+#define US_LIN_CSR_DCD (0x1u << 22) /**< \brief (US_LIN_CSR) Image of DCD Input */\r
+#define US_LIN_CSR_DCD_0 (0x0u << 22) /**< \brief (US_LIN_CSR) DCD is at 0 */\r
+#define US_LIN_CSR_DCD_1 (0x1u << 22) /**< \brief (US_LIN_CSR) DCD is at 1 */\r
+#define US_LIN_CSR_LINBLS (0x1u << 23) /**< \brief (US_LIN_CSR) LIN Bus Line Status */\r
+#define US_LIN_CSR_LINBLS_0 (0x0u << 23) /**< \brief (US_LIN_CSR) CTS is at 0 */\r
+#define US_LIN_CSR_LINBLS_1 (0x1u << 23) /**< \brief (US_LIN_CSR) CTS is at 1 */\r
+#define US_LIN_CSR_LINBE (0x1u << 25) /**< \brief (US_LIN_CSR) LIN Bit Error */\r
+#define US_LIN_CSR_LINISFE (0x1u << 26) /**< \brief (US_LIN_CSR) LIN Inconsistent Synch Field Error */\r
+#define US_LIN_CSR_LINIPE (0x1u << 27) /**< \brief (US_LIN_CSR) LIN Identifier Parity Error */\r
+#define US_LIN_CSR_LINCE (0x1u << 28) /**< \brief (US_LIN_CSR) LIN Checksum Error */\r
+#define US_LIN_CSR_LINSNRE (0x1u << 29) /**< \brief (US_LIN_CSR) LIN Slave Not Responding Error */\r
+#define US_LIN_CSR_LINSTE (0x1u << 30) /**< \brief (US_LIN_CSR) LIN Synch Tolerance Error */\r
+#define US_LIN_CSR_LINSTE_0 (0x0u << 30) /**< \brief (US_LIN_CSR) COMM_TX is at 0 */\r
+#define US_LIN_CSR_LINSTE_1 (0x1u << 30) /**< \brief (US_LIN_CSR) COMM_TX is at 1 */\r
+#define US_LIN_CSR_LINHTE (0x1u << 31) /**< \brief (US_LIN_CSR) LIN Header Timeout Error */\r
+#define US_LIN_CSR_LINHTE_0 (0x0u << 31) /**< \brief (US_LIN_CSR) COMM_RX is at 0 */\r
+#define US_LIN_CSR_LINHTE_1 (0x1u << 31) /**< \brief (US_LIN_CSR) COMM_RX is at 1 */\r
+/* -------- US_SPI_SLAVE_CSR : (USART Offset: 0x14) Channel Status Register -------- */\r
+#define US_SPI_SLAVE_CSR_RXRDY (0x1u << 0) /**< \brief (US_SPI_SLAVE_CSR) Receiver Ready */\r
+#define US_SPI_SLAVE_CSR_RXRDY_0 (0x0u << 0) /**< \brief (US_SPI_SLAVE_CSR) No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled */\r
+#define US_SPI_SLAVE_CSR_RXRDY_1 (0x1u << 0) /**< \brief (US_SPI_SLAVE_CSR) At least one complete character has been received and RHR has not yet been read */\r
+#define US_SPI_SLAVE_CSR_TXRDY (0x1u << 1) /**< \brief (US_SPI_SLAVE_CSR) Transmitter Ready */\r
+#define US_SPI_SLAVE_CSR_TXRDY_0 (0x0u << 1) /**< \brief (US_SPI_SLAVE_CSR) A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 */\r
+#define US_SPI_SLAVE_CSR_TXRDY_1 (0x1u << 1) /**< \brief (US_SPI_SLAVE_CSR) There is no character in the THR */\r
+#define US_SPI_SLAVE_CSR_RXBRK (0x1u << 2) /**< \brief (US_SPI_SLAVE_CSR) Break Received/End of Break */\r
+#define US_SPI_SLAVE_CSR_RXBRK_0 (0x0u << 2) /**< \brief (US_SPI_SLAVE_CSR) No Break received or End of Break detected since the last RSTSTA */\r
+#define US_SPI_SLAVE_CSR_RXBRK_1 (0x1u << 2) /**< \brief (US_SPI_SLAVE_CSR) Break Received or End of Break detected since the last RSTSTA */\r
+#define US_SPI_SLAVE_CSR_ENDRX (0x1u << 3) /**< \brief (US_SPI_SLAVE_CSR) End of Receiver Transfer */\r
+#define US_SPI_SLAVE_CSR_ENDRX_0 (0x0u << 3) /**< \brief (US_SPI_SLAVE_CSR) The End of Transfer signal from the Receive PDC channel is inactive */\r
+#define US_SPI_SLAVE_CSR_ENDRX_1 (0x1u << 3) /**< \brief (US_SPI_SLAVE_CSR) The End of Transfer signal from the Receive PDC channel is active */\r
+#define US_SPI_SLAVE_CSR_ENDTX (0x1u << 4) /**< \brief (US_SPI_SLAVE_CSR) End of Transmitter Transfer */\r
+#define US_SPI_SLAVE_CSR_ENDTX_0 (0x0u << 4) /**< \brief (US_SPI_SLAVE_CSR) The End of Transfer signal from the Transmit PDC channel is inactive */\r
+#define US_SPI_SLAVE_CSR_ENDTX_1 (0x1u << 4) /**< \brief (US_SPI_SLAVE_CSR) The End of Transfer signal from the Transmit PDC channel is active */\r
+#define US_SPI_SLAVE_CSR_OVRE (0x1u << 5) /**< \brief (US_SPI_SLAVE_CSR) Overrun Error */\r
+#define US_SPI_SLAVE_CSR_OVRE_0 (0x0u << 5) /**< \brief (US_SPI_SLAVE_CSR) No overrun error has occurred since since the last RSTSTA */\r
+#define US_SPI_SLAVE_CSR_OVRE_1 (0x1u << 5) /**< \brief (US_SPI_SLAVE_CSR) At least one overrun error has occurred since the last RSTSTA */\r
+#define US_SPI_SLAVE_CSR_FRAME (0x1u << 6) /**< \brief (US_SPI_SLAVE_CSR) Framing Error */\r
+#define US_SPI_SLAVE_CSR_FRAME_0 (0x0u << 6) /**< \brief (US_SPI_SLAVE_CSR) No stop bit has been detected low since the last RSTSTA */\r
+#define US_SPI_SLAVE_CSR_FRAME_1 (0x1u << 6) /**< \brief (US_SPI_SLAVE_CSR) At least one stop bit has been detected low since the last RSTSTA */\r
+#define US_SPI_SLAVE_CSR_PARE (0x1u << 7) /**< \brief (US_SPI_SLAVE_CSR) Parity Error */\r
+#define US_SPI_SLAVE_CSR_PARE_0 (0x0u << 7) /**< \brief (US_SPI_SLAVE_CSR) No parity error has been detected since the last RSTSTA */\r
+#define US_SPI_SLAVE_CSR_PARE_1 (0x1u << 7) /**< \brief (US_SPI_SLAVE_CSR) At least one parity error has been detected since the last RSTSTA */\r
+#define US_SPI_SLAVE_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_SPI_SLAVE_CSR) Receiver Time-out */\r
+#define US_SPI_SLAVE_CSR_TIMEOUT_0 (0x0u << 8) /**< \brief (US_SPI_SLAVE_CSR) There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 */\r
+#define US_SPI_SLAVE_CSR_TIMEOUT_1 (0x1u << 8) /**< \brief (US_SPI_SLAVE_CSR) There has been a time-out since the last Start Time-out command */\r
+#define US_SPI_SLAVE_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_SPI_SLAVE_CSR) Transmitter Empty */\r
+#define US_SPI_SLAVE_CSR_TXEMPTY_0 (0x0u << 9) /**< \brief (US_SPI_SLAVE_CSR) There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled */\r
+#define US_SPI_SLAVE_CSR_TXEMPTY_1 (0x1u << 9) /**< \brief (US_SPI_SLAVE_CSR) There is at least one character in either THR or the Transmit Shift Register */\r
+#define US_SPI_SLAVE_CSR_UNRE (0x1u << 10) /**< \brief (US_SPI_SLAVE_CSR) SPI Underrun Error */\r
+#define US_SPI_SLAVE_CSR_UNRE_0 (0x0u << 10) /**< \brief (US_SPI_SLAVE_CSR) No SPI underrun error has occurred since the last RSTSTA */\r
+#define US_SPI_SLAVE_CSR_UNRE_1 (0x1u << 10) /**< \brief (US_SPI_SLAVE_CSR) At least one SPI underrun error has occurred since the last RSTSTA */\r
+#define US_SPI_SLAVE_CSR_TXBUFE (0x1u << 11) /**< \brief (US_SPI_SLAVE_CSR) Transmission Buffer Empty */\r
+#define US_SPI_SLAVE_CSR_TXBUFE_0 (0x0u << 11) /**< \brief (US_SPI_SLAVE_CSR) The signal Buffer Empty from the Transmit PDC channel is inactive */\r
+#define US_SPI_SLAVE_CSR_TXBUFE_1 (0x1u << 11) /**< \brief (US_SPI_SLAVE_CSR) The signal Buffer Empty from the Transmit PDC channel is active */\r
+#define US_SPI_SLAVE_CSR_RXBUFF (0x1u << 12) /**< \brief (US_SPI_SLAVE_CSR) Reception Buffer Full */\r
+#define US_SPI_SLAVE_CSR_RXBUFF_0 (0x0u << 12) /**< \brief (US_SPI_SLAVE_CSR) The signal Buffer Full from the Receive PDC channel is inactive */\r
+#define US_SPI_SLAVE_CSR_RXBUFF_1 (0x1u << 12) /**< \brief (US_SPI_SLAVE_CSR) The signal Buffer Full from the Receive PDC channel is active */\r
+#define US_SPI_SLAVE_CSR_NACK (0x1u << 13) /**< \brief (US_SPI_SLAVE_CSR) Non Acknowledge */\r
+#define US_SPI_SLAVE_CSR_NACK_0 (0x0u << 13) /**< \brief (US_SPI_SLAVE_CSR) No Non Acknowledge has not been detected since the last RSTNACK */\r
+#define US_SPI_SLAVE_CSR_NACK_1 (0x1u << 13) /**< \brief (US_SPI_SLAVE_CSR) At least one Non Acknowledge has been detected since the last RSTNACK */\r
+#define US_SPI_SLAVE_CSR_RIIC (0x1u << 16) /**< \brief (US_SPI_SLAVE_CSR) Ring Indicator Input Change Flag */\r
+#define US_SPI_SLAVE_CSR_RIIC_0 (0x0u << 16) /**< \brief (US_SPI_SLAVE_CSR) No input change has been detected on the RI pin since the last read of CSR */\r
+#define US_SPI_SLAVE_CSR_RIIC_1 (0x1u << 16) /**< \brief (US_SPI_SLAVE_CSR) At least one input change has been detected on the RI pin since the last read of CSR */\r
+#define US_SPI_SLAVE_CSR_DSRIC (0x1u << 17) /**< \brief (US_SPI_SLAVE_CSR) Data Set Ready Input Change Flag */\r
+#define US_SPI_SLAVE_CSR_DSRIC_0 (0x0u << 17) /**< \brief (US_SPI_SLAVE_CSR) No input change has been detected on the DSR pin since the last read of CSR */\r
+#define US_SPI_SLAVE_CSR_DSRIC_1 (0x1u << 17) /**< \brief (US_SPI_SLAVE_CSR) At least one input change has been detected on the DSR pin since the last read of CSR */\r
+#define US_SPI_SLAVE_CSR_DCDIC (0x1u << 18) /**< \brief (US_SPI_SLAVE_CSR) Data Carrier Detect Input Change Flag */\r
+#define US_SPI_SLAVE_CSR_DCDIC_0 (0x0u << 18) /**< \brief (US_SPI_SLAVE_CSR) No input change has been detected on the DCD pin since the last read of CSR */\r
+#define US_SPI_SLAVE_CSR_DCDIC_1 (0x1u << 18) /**< \brief (US_SPI_SLAVE_CSR) At least one input change has been detected on the DCD pin since the last read of CSR */\r
+#define US_SPI_SLAVE_CSR_CTSIC (0x1u << 19) /**< \brief (US_SPI_SLAVE_CSR) Clear to Send Input Change Flag */\r
+#define US_SPI_SLAVE_CSR_CTSIC_0 (0x0u << 19) /**< \brief (US_SPI_SLAVE_CSR) No input change has been detected on the CTS pin since the last read of CSR */\r
+#define US_SPI_SLAVE_CSR_CTSIC_1 (0x1u << 19) /**< \brief (US_SPI_SLAVE_CSR) At least one input change has been detected on the CTS pin since the last read of CSR */\r
+#define US_SPI_SLAVE_CSR_RI (0x1u << 20) /**< \brief (US_SPI_SLAVE_CSR) Image of RI Input */\r
+#define US_SPI_SLAVE_CSR_RI_0 (0x0u << 20) /**< \brief (US_SPI_SLAVE_CSR) RI is at 0 */\r
+#define US_SPI_SLAVE_CSR_RI_1 (0x1u << 20) /**< \brief (US_SPI_SLAVE_CSR) RI is at 1 */\r
+#define US_SPI_SLAVE_CSR_DSR (0x1u << 21) /**< \brief (US_SPI_SLAVE_CSR) Image of DSR Input */\r
+#define US_SPI_SLAVE_CSR_DSR_0 (0x0u << 21) /**< \brief (US_SPI_SLAVE_CSR) DSR is at 0 */\r
+#define US_SPI_SLAVE_CSR_DSR_1 (0x1u << 21) /**< \brief (US_SPI_SLAVE_CSR) DSR is at 1 */\r
+#define US_SPI_SLAVE_CSR_DCD (0x1u << 22) /**< \brief (US_SPI_SLAVE_CSR) Image of DCD Input */\r
+#define US_SPI_SLAVE_CSR_DCD_0 (0x0u << 22) /**< \brief (US_SPI_SLAVE_CSR) DCD is at 0 */\r
+#define US_SPI_SLAVE_CSR_DCD_1 (0x1u << 22) /**< \brief (US_SPI_SLAVE_CSR) DCD is at 1 */\r
+#define US_SPI_SLAVE_CSR_CTS (0x1u << 23) /**< \brief (US_SPI_SLAVE_CSR) Image of CTS Input */\r
+#define US_SPI_SLAVE_CSR_CTS_0 (0x0u << 23) /**< \brief (US_SPI_SLAVE_CSR) CTS is at 0 */\r
+#define US_SPI_SLAVE_CSR_CTS_1 (0x1u << 23) /**< \brief (US_SPI_SLAVE_CSR) CTS is at 1 */\r
+/* -------- US_USART_CSR : (USART Offset: 0x14) Channel Status Register -------- */\r
+#define US_USART_CSR_RXRDY (0x1u << 0) /**< \brief (US_USART_CSR) Receiver Ready */\r
+#define US_USART_CSR_RXRDY_0 (0x0u << 0) /**< \brief (US_USART_CSR) No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled */\r
+#define US_USART_CSR_RXRDY_1 (0x1u << 0) /**< \brief (US_USART_CSR) At least one complete character has been received and RHR has not yet been read */\r
+#define US_USART_CSR_TXRDY (0x1u << 1) /**< \brief (US_USART_CSR) Transmitter Ready */\r
+#define US_USART_CSR_TXRDY_0 (0x0u << 1) /**< \brief (US_USART_CSR) A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 */\r
+#define US_USART_CSR_TXRDY_1 (0x1u << 1) /**< \brief (US_USART_CSR) There is no character in the THR */\r
+#define US_USART_CSR_RXBRK (0x1u << 2) /**< \brief (US_USART_CSR) Break Received/End of Break */\r
+#define US_USART_CSR_RXBRK_0 (0x0u << 2) /**< \brief (US_USART_CSR) No Break received or End of Break detected since the last RSTSTA */\r
+#define US_USART_CSR_RXBRK_1 (0x1u << 2) /**< \brief (US_USART_CSR) Break Received or End of Break detected since the last RSTSTA */\r
+#define US_USART_CSR_ENDRX (0x1u << 3) /**< \brief (US_USART_CSR) End of Receiver Transfer */\r
+#define US_USART_CSR_ENDRX_0 (0x0u << 3) /**< \brief (US_USART_CSR) The End of Transfer signal from the Receive PDC channel is inactive */\r
+#define US_USART_CSR_ENDRX_1 (0x1u << 3) /**< \brief (US_USART_CSR) The End of Transfer signal from the Receive PDC channel is active */\r
+#define US_USART_CSR_ENDTX (0x1u << 4) /**< \brief (US_USART_CSR) End of Transmitter Transfer */\r
+#define US_USART_CSR_ENDTX_0 (0x0u << 4) /**< \brief (US_USART_CSR) The End of Transfer signal from the Transmit PDC channel is inactive */\r
+#define US_USART_CSR_ENDTX_1 (0x1u << 4) /**< \brief (US_USART_CSR) The End of Transfer signal from the Transmit PDC channel is active */\r
+#define US_USART_CSR_OVRE (0x1u << 5) /**< \brief (US_USART_CSR) Overrun Error */\r
+#define US_USART_CSR_OVRE_0 (0x0u << 5) /**< \brief (US_USART_CSR) No overrun error has occurred since since the last RSTSTA */\r
+#define US_USART_CSR_OVRE_1 (0x1u << 5) /**< \brief (US_USART_CSR) At least one overrun error has occurred since the last RSTSTA */\r
+#define US_USART_CSR_FRAME (0x1u << 6) /**< \brief (US_USART_CSR) Framing Error */\r
+#define US_USART_CSR_FRAME_0 (0x0u << 6) /**< \brief (US_USART_CSR) No stop bit has been detected low since the last RSTSTA */\r
+#define US_USART_CSR_FRAME_1 (0x1u << 6) /**< \brief (US_USART_CSR) At least one stop bit has been detected low since the last RSTSTA */\r
+#define US_USART_CSR_PARE (0x1u << 7) /**< \brief (US_USART_CSR) Parity Error */\r
+#define US_USART_CSR_PARE_0 (0x0u << 7) /**< \brief (US_USART_CSR) No parity error has been detected since the last RSTSTA */\r
+#define US_USART_CSR_PARE_1 (0x1u << 7) /**< \brief (US_USART_CSR) At least one parity error has been detected since the last RSTSTA */\r
+#define US_USART_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_USART_CSR) Receiver Time-out */\r
+#define US_USART_CSR_TIMEOUT_0 (0x0u << 8) /**< \brief (US_USART_CSR) There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 */\r
+#define US_USART_CSR_TIMEOUT_1 (0x1u << 8) /**< \brief (US_USART_CSR) There has been a time-out since the last Start Time-out command */\r
+#define US_USART_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_USART_CSR) Transmitter Empty */\r
+#define US_USART_CSR_TXEMPTY_0 (0x0u << 9) /**< \brief (US_USART_CSR) There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled */\r
+#define US_USART_CSR_TXEMPTY_1 (0x1u << 9) /**< \brief (US_USART_CSR) There is at least one character in either THR or the Transmit Shift Register */\r
+#define US_USART_CSR_ITER (0x1u << 10) /**< \brief (US_USART_CSR) Max number of Repetitions Reached */\r
+#define US_USART_CSR_ITER_0 (0x0u << 10) /**< \brief (US_USART_CSR) Maximum number of repetitions has not been reached since the last RSIT */\r
+#define US_USART_CSR_ITER_1 (0x1u << 10) /**< \brief (US_USART_CSR) Maximum number of repetitions has been reached since the last RSIT */\r
+#define US_USART_CSR_TXBUFE (0x1u << 11) /**< \brief (US_USART_CSR) Transmission Buffer Empty */\r
+#define US_USART_CSR_TXBUFE_0 (0x0u << 11) /**< \brief (US_USART_CSR) The signal Buffer Empty from the Transmit PDC channel is inactive */\r
+#define US_USART_CSR_TXBUFE_1 (0x1u << 11) /**< \brief (US_USART_CSR) The signal Buffer Empty from the Transmit PDC channel is active */\r
+#define US_USART_CSR_RXBUFF (0x1u << 12) /**< \brief (US_USART_CSR) Reception Buffer Full */\r
+#define US_USART_CSR_RXBUFF_0 (0x0u << 12) /**< \brief (US_USART_CSR) The signal Buffer Full from the Receive PDC channel is inactive */\r
+#define US_USART_CSR_RXBUFF_1 (0x1u << 12) /**< \brief (US_USART_CSR) The signal Buffer Full from the Receive PDC channel is active */\r
+#define US_USART_CSR_NACK (0x1u << 13) /**< \brief (US_USART_CSR) Non Acknowledge */\r
+#define US_USART_CSR_NACK_0 (0x0u << 13) /**< \brief (US_USART_CSR) No Non Acknowledge has not been detected since the last RSTNACK */\r
+#define US_USART_CSR_NACK_1 (0x1u << 13) /**< \brief (US_USART_CSR) At least one Non Acknowledge has been detected since the last RSTNACK */\r
+#define US_USART_CSR_RIIC (0x1u << 16) /**< \brief (US_USART_CSR) Ring Indicator Input Change Flag */\r
+#define US_USART_CSR_RIIC_0 (0x0u << 16) /**< \brief (US_USART_CSR) No input change has been detected on the RI pin since the last read of CSR */\r
+#define US_USART_CSR_RIIC_1 (0x1u << 16) /**< \brief (US_USART_CSR) At least one input change has been detected on the RI pin since the last read of CSR */\r
+#define US_USART_CSR_DSRIC (0x1u << 17) /**< \brief (US_USART_CSR) Data Set Ready Input Change Flag */\r
+#define US_USART_CSR_DSRIC_0 (0x0u << 17) /**< \brief (US_USART_CSR) No input change has been detected on the DSR pin since the last read of CSR */\r
+#define US_USART_CSR_DSRIC_1 (0x1u << 17) /**< \brief (US_USART_CSR) At least one input change has been detected on the DSR pin since the last read of CSR */\r
+#define US_USART_CSR_DCDIC (0x1u << 18) /**< \brief (US_USART_CSR) Data Carrier Detect Input Change Flag */\r
+#define US_USART_CSR_DCDIC_0 (0x0u << 18) /**< \brief (US_USART_CSR) No input change has been detected on the DCD pin since the last read of CSR */\r
+#define US_USART_CSR_DCDIC_1 (0x1u << 18) /**< \brief (US_USART_CSR) At least one input change has been detected on the DCD pin since the last read of CSR */\r
+#define US_USART_CSR_CTSIC (0x1u << 19) /**< \brief (US_USART_CSR) Clear to Send Input Change Flag */\r
+#define US_USART_CSR_CTSIC_0 (0x0u << 19) /**< \brief (US_USART_CSR) No input change has been detected on the CTS pin since the last read of CSR */\r
+#define US_USART_CSR_CTSIC_1 (0x1u << 19) /**< \brief (US_USART_CSR) At least one input change has been detected on the CTS pin since the last read of CSR */\r
+#define US_USART_CSR_RI (0x1u << 20) /**< \brief (US_USART_CSR) Image of RI Input */\r
+#define US_USART_CSR_RI_0 (0x0u << 20) /**< \brief (US_USART_CSR) RI is at 0 */\r
+#define US_USART_CSR_RI_1 (0x1u << 20) /**< \brief (US_USART_CSR) RI is at 1 */\r
+#define US_USART_CSR_DSR (0x1u << 21) /**< \brief (US_USART_CSR) Image of DSR Input */\r
+#define US_USART_CSR_DSR_0 (0x0u << 21) /**< \brief (US_USART_CSR) DSR is at 0 */\r
+#define US_USART_CSR_DSR_1 (0x1u << 21) /**< \brief (US_USART_CSR) DSR is at 1 */\r
+#define US_USART_CSR_DCD (0x1u << 22) /**< \brief (US_USART_CSR) Image of DCD Input */\r
+#define US_USART_CSR_DCD_0 (0x0u << 22) /**< \brief (US_USART_CSR) DCD is at 0 */\r
+#define US_USART_CSR_DCD_1 (0x1u << 22) /**< \brief (US_USART_CSR) DCD is at 1 */\r
+#define US_USART_CSR_CTS (0x1u << 23) /**< \brief (US_USART_CSR) Image of CTS Input */\r
+#define US_USART_CSR_CTS_0 (0x0u << 23) /**< \brief (US_USART_CSR) CTS is at 0 */\r
+#define US_USART_CSR_CTS_1 (0x1u << 23) /**< \brief (US_USART_CSR) CTS is at 1 */\r
+#define US_USART_CSR_MANERR (0x1u << 24) /**< \brief (US_USART_CSR) Manchester Error */\r
+#define US_USART_CSR_MANERR_0 (0x0u << 24) /**< \brief (US_USART_CSR) No Manchester error has been detected since the last RSTSTA */\r
+#define US_USART_CSR_MANERR_1 (0x1u << 24) /**< \brief (US_USART_CSR) At least one Manchester error has been detected since the last RSTSTA */\r
+/* -------- US_CSR : (USART Offset: 0x14) Channel Status Register -------- */\r
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */\r
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */\r
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */\r
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */\r
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */\r
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */\r
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */\r
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */\r
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */\r
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */\r
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */\r
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */\r
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */\r
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */\r
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge or LIN Break Sent or LIN Break Received */\r
+#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */\r
+#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Conpleted */\r
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */\r
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */\r
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */\r
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */\r
+#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */\r
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */\r
+#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error */\r
+#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */\r
+#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error */\r
+#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error */\r
+#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error */\r
+#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error */\r
+#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error */\r
+\r
+/* -------- US_RHR : (USART Offset: 0x18) Receiver Holding Register -------- */\r
+#define US_RHR_RXCHR_Pos 0\r
+#define US_RHR_RXCHR_Msk (0x1FFu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */\r
+#define US_RHR_RXCHR(value) ((US_RHR_RXCHR_Msk & ((value) << US_RHR_RXCHR_Pos)))\r
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */\r
+#define US_RHR_RXSYNH_0 (0x0u << 15) /**< \brief (US_RHR) Last character received is a Data */\r
+#define US_RHR_RXSYNH_1 (0x1u << 15) /**< \brief (US_RHR) Last character received is a Command */\r
+/* -------- US_THR : (USART Offset: 0x1C) Transmitter Holding Register -------- */\r
+#define US_THR_TXCHR_Pos 0\r
+#define US_THR_TXCHR_Msk (0x1FFu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */\r
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))\r
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */\r
+#define US_THR_TXSYNH_0 (0x0u << 15) /**< \brief (US_THR) The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC */\r
+#define US_THR_TXSYNH_1 (0x1u << 15) /**< \brief (US_THR) The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC */\r
+/* -------- US_BRGR : (USART Offset: 0x20) Baud Rate Generator Register -------- */\r
+#define US_BRGR_CD_Pos 0\r
+#define US_BRGR_CD_Msk (0xFFFFu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divisor */\r
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))\r
+#define US_BRGR_CD_DISABLE (0x0u << 0) /**< \brief (US_BRGR) Disables the clock */\r
+#define US_BRGR_CD_BYPASS (0x1u << 0) /**< \brief (US_BRGR) Clock Divisor Bypass */\r
+#define US_BRGR_CD_2 (0x2u << 0) /**< \brief (US_BRGR) Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD); Baud Rate (Synchronous Mode) = Selected Clock/CD; */\r
+#define US_BRGR_FP_Pos 16\r
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */\r
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))\r
+#define US_BRGR_FP_0 (0x0u << 16) /**< \brief (US_BRGR) Fractional divider is disabled */\r
+/* -------- US_RTOR : (USART Offset: 0x24) Receiver Time-out Register -------- */\r
+#define US_RTOR_TO_Pos 0\r
+#define US_RTOR_TO_Msk (0x1FFFFu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */\r
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))\r
+#define US_RTOR_TO_DISABLE (0x0u << 0) /**< \brief (US_RTOR) Disables the RX Time-out function */\r
+/* -------- US_TTGR : (USART Offset: 0x28) Transmitter Timeguard Register -------- */\r
+#define US_TTGR_TG_Pos 0\r
+#define US_TTGR_TG_Msk (0xFFu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */\r
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))\r
+#define US_TTGR_TG_DISABLE (0x0u << 0) /**< \brief (US_TTGR) Disables the TX Timeguard function. */\r
+/* -------- US_FIDI : (USART Offset: 0x40) FI DI Ratio Register -------- */\r
+#define US_FIDI_FI_DI_RATIO_Pos 0\r
+#define US_FIDI_FI_DI_RATIO_Msk (0x7FFu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */\r
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))\r
+#define US_FIDI_FI_DI_RATIO_DISABLE (0x0u << 0) /**< \brief (US_FIDI) Baud Rate = 0 */\r
+/* -------- US_NER : (USART Offset: 0x44) Number of Errors Register -------- */\r
+#define US_NER_NB_ERRORS_Pos 0\r
+#define US_NER_NB_ERRORS_Msk (0xFFu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Error number during ISO7816 transfers */\r
+#define US_NER_NB_ERRORS(value) ((US_NER_NB_ERRORS_Msk & ((value) << US_NER_NB_ERRORS_Pos)))\r
+/* -------- US_IFR : (USART Offset: 0x4C) IrDA Filter Register -------- */\r
+#define US_IFR_IRDA_FILTER_Pos 0\r
+#define US_IFR_IRDA_FILTER_Msk (0xFFu << US_IFR_IRDA_FILTER_Pos) /**< \brief (US_IFR) Irda filter */\r
+#define US_IFR_IRDA_FILTER(value) ((US_IFR_IRDA_FILTER_Msk & ((value) << US_IFR_IRDA_FILTER_Pos)))\r
+/* -------- US_MAN : (USART Offset: 0x50) Manchester Configuration Register -------- */\r
+#define US_MAN_TX_PL_Pos 0\r
+#define US_MAN_TX_PL_Msk (0xFu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */\r
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))\r
+#define US_MAN_TX_PL_0 (0x0u << 0) /**< \brief (US_MAN) The Transmitter Preamble pattern generation is disabled */\r
+#define US_MAN_TX_PP_Pos 8\r
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */\r
+#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)))\r
+#define US_MAN_TX_PP_0 (0x0u << 8) /**< \brief (US_MAN) ALL_ONE */\r
+#define US_MAN_TX_PP_1 (0x1u << 8) /**< \brief (US_MAN) ALL_ZERO */\r
+#define US_MAN_TX_PP_2 (0x2u << 8) /**< \brief (US_MAN) ZERO_ONE */\r
+#define US_MAN_TX_PP_3 (0x3u << 8) /**< \brief (US_MAN) ONE_ZERO */\r
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */\r
+#define US_MAN_TX_MPOL_0 (0x0u << 12) /**< \brief (US_MAN) Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition */\r
+#define US_MAN_TX_MPOL_1 (0x1u << 12) /**< \brief (US_MAN) Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition */\r
+#define US_MAN_RX_PL_Pos 16\r
+#define US_MAN_RX_PL_Msk (0xFu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */\r
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))\r
+#define US_MAN_RX_PL_0 (0x0u << 16) /**< \brief (US_MAN) The receiver preamble pattern detection is disabled */\r
+#define US_MAN_RX_PP_Pos 24\r
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */\r
+#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)))\r
+#define US_MAN_RX_PP_0 (0x0u << 24) /**< \brief (US_MAN) ALL_ONE */\r
+#define US_MAN_RX_PP_1 (0x1u << 24) /**< \brief (US_MAN) ALL_ZERO */\r
+#define US_MAN_RX_PP_2 (0x2u << 24) /**< \brief (US_MAN) ZERO_ONE */\r
+#define US_MAN_RX_PP_3 (0x3u << 24) /**< \brief (US_MAN) ONE_ZERO */\r
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */\r
+#define US_MAN_RX_MPOL_0 (0x0u << 28) /**< \brief (US_MAN) Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition */\r
+#define US_MAN_RX_MPOL_1 (0x1u << 28) /**< \brief (US_MAN) Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition */\r
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */\r
+#define US_MAN_DRIFT_0 (0x0u << 30) /**< \brief (US_MAN) The USART can not recover from an important clock drift */\r
+#define US_MAN_DRIFT_1 (0x1u << 30) /**< \brief (US_MAN) The USART can recover from clock drift. The 16X clock mode must be enabled */\r
+/* -------- US_LINMR : (USART Offset: 0x54) LIN Mode Register -------- */\r
+#define US_LINMR_NACT_Pos 0\r
+#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */\r
+#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)))\r
+#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The LIN Controller transmits the response */\r
+#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The LIN Controller receives the response */\r
+#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The LIN Controller doesn't transmit and doesn't receive the response */\r
+#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */\r
+#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */\r
+#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */\r
+#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */\r
+#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */\r
+#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */\r
+#define US_LINMR_DLC_Pos 8\r
+#define US_LINMR_DLC_Msk (0xFFu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */\r
+#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))\r
+#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) PDC Mode */\r
+#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */\r
+/* -------- US_LINIR : (USART Offset: 0x58) LIN Identifier Register -------- */\r
+#define US_LINIR_IDCHR_Pos 0\r
+#define US_LINIR_IDCHR_Msk (0xFFu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */\r
+#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))\r
+/* -------- US_LINBRR : (USART Offset: 0x5C) LIN Baud Rate Register -------- */\r
+#define US_LINBRR_LINCD_Pos 0\r
+#define US_LINBRR_LINCD_Msk (0xFFFFu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */\r
+#define US_LINBRR_LINCD(value) ((US_LINBRR_LINCD_Msk & ((value) << US_LINBRR_LINCD_Pos)))\r
+#define US_LINBRR_LINFP_Pos 16\r
+#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */\r
+#define US_LINBRR_LINFP(value) ((US_LINBRR_LINFP_Msk & ((value) << US_LINBRR_LINFP_Pos)))\r
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */\r
+#define US_WPMR_WPEN_0 (0x0u << 0) /**< \brief (US_WPMR) Disables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) */\r
+#define US_WPMR_WPEN_1 (0x1u << 0) /**< \brief (US_WPMR) Enables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) */\r
+#define US_WPMR_WPKEY_Pos 8\r
+#define US_WPMR_WPKEY_Msk (0xFFFFFFu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect Key */\r
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))\r
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */\r
+#define US_WPSR_WPV (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */\r
+#define US_WPSR_WPV_0 (0x0u << 0) /**< \brief (US_WPSR) No Write Protect Violation has occurred since the last read of the WPSR register */\r
+#define US_WPSR_WPV_1 (0x1u << 0) /**< \brief (US_WPSR) A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC */\r
+#define US_WPSR_WPVSRC_Pos 8\r
+#define US_WPSR_WPVSRC_Msk (0xFFFFu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */\r
+#define US_WPSR_WPVSRC(value) ((US_WPSR_WPVSRC_Msk & ((value) << US_WPSR_WPVSRC_Pos)))\r
+/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */\r
+#define US_VERSION_VERSION_Pos 0\r
+#define US_VERSION_VERSION_Msk (0xFFFu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION) */\r
+#define US_VERSION_VERSION(value) ((US_VERSION_VERSION_Msk & ((value) << US_VERSION_VERSION_Pos)))\r
+#define US_VERSION_MFN_Pos 16\r
+#define US_VERSION_MFN_Msk (0xFu << US_VERSION_MFN_Pos) /**< \brief (US_VERSION) */\r
+#define US_VERSION_MFN(value) ((US_VERSION_MFN_Msk & ((value) << US_VERSION_MFN_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR USBC */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_USBC USB 2.0 Interface */\r
+/*@{*/\r
+\r
+#define REV_USBC 0x310\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief USBC hardware registers */\r
+typedef struct {\r
+ RwReg USBC_UDCON; /**< \brief (USBC Offset: 0x000) Device General Control Register */\r
+ RoReg USBC_UDINT; /**< \brief (USBC Offset: 0x004) Device Global Interupt Register */\r
+ WoReg USBC_UDINTCLR; /**< \brief (USBC Offset: 0x008) Device Global Interrupt Clear Register */\r
+ WoReg USBC_UDINTSET; /**< \brief (USBC Offset: 0x00C) Device Global Interrupt Set Regsiter */\r
+ RoReg USBC_UDINTE; /**< \brief (USBC Offset: 0x010) Device Global Interrupt Enable Register */\r
+ WoReg USBC_UDINTECLR; /**< \brief (USBC Offset: 0x014) Device Global Interrupt Enable Clear Register */\r
+ WoReg USBC_UDINTESET; /**< \brief (USBC Offset: 0x018) Device Global Interrupt Enable Set Register */\r
+ RwReg USBC_UERST; /**< \brief (USBC Offset: 0x01C) Endpoint Enable/Reset Register */\r
+ RoReg USBC_UDFNUM; /**< \brief (USBC Offset: 0x020) Device Frame Number Register */\r
+ RoReg Reserved1[55];\r
+ RwReg USBC_UECFG0; /**< \brief (USBC Offset: 0x100) Endpoint Configuration Register */\r
+ RwReg USBC_UECFG1; /**< \brief (USBC Offset: 0x104) Endpoint Configuration Register */\r
+ RwReg USBC_UECFG2; /**< \brief (USBC Offset: 0x108) Endpoint Configuration Register */\r
+ RwReg USBC_UECFG3; /**< \brief (USBC Offset: 0x10C) Endpoint Configuration Register */\r
+ RwReg USBC_UECFG4; /**< \brief (USBC Offset: 0x110) Endpoint Configuration Register */\r
+ RwReg USBC_UECFG5; /**< \brief (USBC Offset: 0x114) Endpoint Configuration Register */\r
+ RwReg USBC_UECFG6; /**< \brief (USBC Offset: 0x118) Endpoint Configuration Register */\r
+ RwReg USBC_UECFG7; /**< \brief (USBC Offset: 0x11C) Endpoint Configuration Register */\r
+ RoReg Reserved2[4];\r
+ RoReg USBC_UESTA0; /**< \brief (USBC Offset: 0x130) Endpoint Status Register */\r
+ RoReg USBC_UESTA1; /**< \brief (USBC Offset: 0x134) Endpoint Status Register */\r
+ RoReg USBC_UESTA2; /**< \brief (USBC Offset: 0x138) Endpoint Status Register */\r
+ RoReg USBC_UESTA3; /**< \brief (USBC Offset: 0x13C) Endpoint Status Register */\r
+ RoReg USBC_UESTA4; /**< \brief (USBC Offset: 0x140) Endpoint Status Register */\r
+ RoReg USBC_UESTA5; /**< \brief (USBC Offset: 0x144) Endpoint Status Register */\r
+ RoReg USBC_UESTA6; /**< \brief (USBC Offset: 0x148) Endpoint Status Register */\r
+ RoReg USBC_UESTA7; /**< \brief (USBC Offset: 0x14C) Endpoint Status Register */\r
+ RoReg Reserved3[4];\r
+ WoReg USBC_UESTA0CLR; /**< \brief (USBC Offset: 0x160) Endpoint Status Clear Register */\r
+ WoReg USBC_UESTA1CLR; /**< \brief (USBC Offset: 0x164) Endpoint Status Clear Register */\r
+ WoReg USBC_UESTA2CLR; /**< \brief (USBC Offset: 0x168) Endpoint Status Clear Register */\r
+ WoReg USBC_UESTA3CLR; /**< \brief (USBC Offset: 0x16C) Endpoint Status Clear Register */\r
+ WoReg USBC_UESTA4CLR; /**< \brief (USBC Offset: 0x170) Endpoint Status Clear Register */\r
+ WoReg USBC_UESTA5CLR; /**< \brief (USBC Offset: 0x174) Endpoint Status Clear Register */\r
+ WoReg USBC_UESTA6CLR; /**< \brief (USBC Offset: 0x178) Endpoint Status Clear Register */\r
+ WoReg USBC_UESTA7CLR; /**< \brief (USBC Offset: 0x17C) Endpoint Status Clear Register */\r
+ RoReg Reserved4[4];\r
+ WoReg USBC_UESTA0SET; /**< \brief (USBC Offset: 0x190) Endpoint Status Set Register */\r
+ WoReg USBC_UESTA1SET; /**< \brief (USBC Offset: 0x194) Endpoint Status Set Register */\r
+ WoReg USBC_UESTA2SET; /**< \brief (USBC Offset: 0x198) Endpoint Status Set Register */\r
+ WoReg USBC_UESTA3SET; /**< \brief (USBC Offset: 0x19C) Endpoint Status Set Register */\r
+ WoReg USBC_UESTA4SET; /**< \brief (USBC Offset: 0x1A0) Endpoint Status Set Register */\r
+ WoReg USBC_UESTA5SET; /**< \brief (USBC Offset: 0x1A4) Endpoint Status Set Register */\r
+ WoReg USBC_UESTA6SET; /**< \brief (USBC Offset: 0x1A8) Endpoint Status Set Register */\r
+ WoReg USBC_UESTA7SET; /**< \brief (USBC Offset: 0x1AC) Endpoint Status Set Register */\r
+ RoReg Reserved5[4];\r
+ RoReg USBC_UECON0; /**< \brief (USBC Offset: 0x1C0) Endpoint Control Register */\r
+ RoReg USBC_UECON1; /**< \brief (USBC Offset: 0x1C4) Endpoint Control Register */\r
+ RoReg USBC_UECON2; /**< \brief (USBC Offset: 0x1C8) Endpoint Control Register */\r
+ RoReg USBC_UECON3; /**< \brief (USBC Offset: 0x1CC) Endpoint Control Register */\r
+ RoReg USBC_UECON4; /**< \brief (USBC Offset: 0x1D0) Endpoint Control Register */\r
+ RoReg USBC_UECON5; /**< \brief (USBC Offset: 0x1D4) Endpoint Control Register */\r
+ RoReg USBC_UECON6; /**< \brief (USBC Offset: 0x1D8) Endpoint Control Register */\r
+ RoReg USBC_UECON7; /**< \brief (USBC Offset: 0x1DC) Endpoint Control Register */\r
+ RoReg Reserved6[4];\r
+ WoReg USBC_UECON0SET; /**< \brief (USBC Offset: 0x1F0) Endpoint Control Set Register */\r
+ WoReg USBC_UECON1SET; /**< \brief (USBC Offset: 0x1F4) Endpoint Control Set Register */\r
+ WoReg USBC_UECON2SET; /**< \brief (USBC Offset: 0x1F8) Endpoint Control Set Register */\r
+ WoReg USBC_UECON3SET; /**< \brief (USBC Offset: 0x1FC) Endpoint Control Set Register */\r
+ WoReg USBC_UECON4SET; /**< \brief (USBC Offset: 0x200) Endpoint Control Set Register */\r
+ WoReg USBC_UECON5SET; /**< \brief (USBC Offset: 0x204) Endpoint Control Set Register */\r
+ WoReg USBC_UECON6SET; /**< \brief (USBC Offset: 0x208) Endpoint Control Set Register */\r
+ WoReg USBC_UECON7SET; /**< \brief (USBC Offset: 0x20C) Endpoint Control Set Register */\r
+ RoReg Reserved7[4];\r
+ WoReg USBC_UECON0CLR; /**< \brief (USBC Offset: 0x220) Endpoint Control Clear Register */\r
+ WoReg USBC_UECON1CLR; /**< \brief (USBC Offset: 0x224) TXINE Clear */\r
+ WoReg USBC_UECON2CLR; /**< \brief (USBC Offset: 0x228) TXINE Clear */\r
+ WoReg USBC_UECON3CLR; /**< \brief (USBC Offset: 0x22C) TXINE Clear */\r
+ WoReg USBC_UECON4CLR; /**< \brief (USBC Offset: 0x230) TXINE Clear */\r
+ WoReg USBC_UECON5CLR; /**< \brief (USBC Offset: 0x234) TXINE Clear */\r
+ WoReg USBC_UECON6CLR; /**< \brief (USBC Offset: 0x238) TXINE Clear */\r
+ WoReg USBC_UECON7CLR; /**< \brief (USBC Offset: 0x23C) TXINE Clear */\r
+ RoReg Reserved8[112];\r
+ RwReg USBC_UHCON; /**< \brief (USBC Offset: 0x400) Host General Control Register */\r
+ RoReg USBC_UHINT; /**< \brief (USBC Offset: 0x404) Host Global Interrupt Register */\r
+ WoReg USBC_UHINTCLR; /**< \brief (USBC Offset: 0x408) Host Global Interrrupt Clear Register */\r
+ WoReg USBC_UHINTSET; /**< \brief (USBC Offset: 0x40C) Host Global Interrupt Set Register */\r
+ RoReg USBC_UHINTE; /**< \brief (USBC Offset: 0x410) Host Global Interrupt Enable Register */\r
+ WoReg USBC_UHINTECLR; /**< \brief (USBC Offset: 0x414) Host Global Interrupt Enable Clear Register */\r
+ WoReg USBC_UHINTESET; /**< \brief (USBC Offset: 0x418) Host Global Interrupt Enable Set Register */\r
+ RwReg USBC_UPRST; /**< \brief (USBC Offset: 0x41C) Pipe Reset Register */\r
+ RwReg USBC_UHFNUM; /**< \brief (USBC Offset: 0x420) Host Frame Number Register */\r
+ RwReg USBC_UHSOFC; /**< \brief (USBC Offset: 0x424) Host Start of Frame Control Register */\r
+ RoReg Reserved9[54];\r
+ RwReg USBC_UPCFG0; /**< \brief (USBC Offset: 0x500) Pipe Configuration Register */\r
+ RwReg USBC_UPCFG1; /**< \brief (USBC Offset: 0x504) Pipe Configuration Register */\r
+ RwReg USBC_UPCFG2; /**< \brief (USBC Offset: 0x508) Pipe Configuration Register */\r
+ RwReg USBC_UPCFG3; /**< \brief (USBC Offset: 0x50C) Pipe Configuration Register */\r
+ RwReg USBC_UPCFG4; /**< \brief (USBC Offset: 0x510) Pipe Configuration Register */\r
+ RwReg USBC_UPCFG5; /**< \brief (USBC Offset: 0x514) Pipe Configuration Register */\r
+ RwReg USBC_UPCFG6; /**< \brief (USBC Offset: 0x518) Pipe Configuration Register */\r
+ RwReg USBC_UPCFG7; /**< \brief (USBC Offset: 0x51C) Pipe Configuration Register */\r
+ RoReg Reserved10[4];\r
+ RoReg USBC_UPSTA0; /**< \brief (USBC Offset: 0x530) Pipe Status Register */\r
+ RoReg USBC_UPSTA1; /**< \brief (USBC Offset: 0x534) Pipe Status Register */\r
+ RoReg USBC_UPSTA2; /**< \brief (USBC Offset: 0x538) Pipe Status Register */\r
+ RoReg USBC_UPSTA3; /**< \brief (USBC Offset: 0x53C) Pipe Status Register */\r
+ RoReg USBC_UPSTA4; /**< \brief (USBC Offset: 0x540) Pipe Status Register */\r
+ RoReg USBC_UPSTA5; /**< \brief (USBC Offset: 0x544) Pipe Status Register */\r
+ RoReg USBC_UPSTA6; /**< \brief (USBC Offset: 0x548) Pipe Status Register */\r
+ RoReg USBC_UPSTA7; /**< \brief (USBC Offset: 0x54C) Pipe Status Register */\r
+ RoReg Reserved11[4];\r
+ WoReg USBC_UPSTA0CLR; /**< \brief (USBC Offset: 0x560) Pipe Status Clear Register */\r
+ WoReg USBC_UPSTA1CLR; /**< \brief (USBC Offset: 0x564) Pipe Status Clear Register */\r
+ WoReg USBC_UPSTA2CLR; /**< \brief (USBC Offset: 0x568) Pipe Status Clear Register */\r
+ WoReg USBC_UPSTA3CLR; /**< \brief (USBC Offset: 0x56C) Pipe Status Clear Register */\r
+ WoReg USBC_UPSTA4CLR; /**< \brief (USBC Offset: 0x570) Pipe Status Clear Register */\r
+ WoReg USBC_UPSTA5CLR; /**< \brief (USBC Offset: 0x574) Pipe Status Clear Register */\r
+ WoReg USBC_UPSTA6CLR; /**< \brief (USBC Offset: 0x578) Pipe Status Clear Register */\r
+ WoReg USBC_UPSTA7CLR; /**< \brief (USBC Offset: 0x57C) Pipe Status Clear Register */\r
+ RoReg Reserved12[4];\r
+ WoReg USBC_UPSTA0SET; /**< \brief (USBC Offset: 0x590) Pipe Status Set Register */\r
+ WoReg USBC_UPSTA1SET; /**< \brief (USBC Offset: 0x594) Pipe Status Set Register */\r
+ WoReg USBC_UPSTA2SET; /**< \brief (USBC Offset: 0x598) Pipe Status Set Register */\r
+ WoReg USBC_UPSTA3SET; /**< \brief (USBC Offset: 0x59C) Pipe Status Set Register */\r
+ WoReg USBC_UPSTA4SET; /**< \brief (USBC Offset: 0x5A0) Pipe Status Set Register */\r
+ WoReg USBC_UPSTA5SET; /**< \brief (USBC Offset: 0x5A4) Pipe Status Set Register */\r
+ WoReg USBC_UPSTA6SET; /**< \brief (USBC Offset: 0x5A8) Pipe Status Set Register */\r
+ WoReg USBC_UPSTA7SET; /**< \brief (USBC Offset: 0x5AC) Pipe Status Set Register */\r
+ RoReg Reserved13[4];\r
+ RoReg USBC_UPCON0; /**< \brief (USBC Offset: 0x5C0) Pipe Control Register */\r
+ RoReg USBC_UPCON1; /**< \brief (USBC Offset: 0x5C4) Pipe Control Register */\r
+ RoReg USBC_UPCON2; /**< \brief (USBC Offset: 0x5C8) Pipe Control Register */\r
+ RoReg USBC_UPCON3; /**< \brief (USBC Offset: 0x5CC) Pipe Control Register */\r
+ RoReg USBC_UPCON4; /**< \brief (USBC Offset: 0x5D0) Pipe Control Register */\r
+ RoReg USBC_UPCON5; /**< \brief (USBC Offset: 0x5D4) Pipe Control Register */\r
+ RoReg USBC_UPCON6; /**< \brief (USBC Offset: 0x5D8) Pipe Control Register */\r
+ RoReg USBC_UPCON7; /**< \brief (USBC Offset: 0x5DC) Pipe Control Register */\r
+ RoReg Reserved14[4];\r
+ WoReg USBC_UPCON0SET; /**< \brief (USBC Offset: 0x5F0) Pipe Control Set Register */\r
+ WoReg USBC_UPCON1SET; /**< \brief (USBC Offset: 0x5F4) Pipe Control Set Register */\r
+ WoReg USBC_UPCON2SET; /**< \brief (USBC Offset: 0x5F8) Pipe Control Set Register */\r
+ WoReg USBC_UPCON3SET; /**< \brief (USBC Offset: 0x5FC) Pipe Control Set Register */\r
+ WoReg USBC_UPCON4SET; /**< \brief (USBC Offset: 0x600) Pipe Control Set Register */\r
+ WoReg USBC_UPCON5SET; /**< \brief (USBC Offset: 0x604) Pipe Control Set Register */\r
+ WoReg USBC_UPCON6SET; /**< \brief (USBC Offset: 0x608) Pipe Control Set Register */\r
+ WoReg USBC_UPCON7SET; /**< \brief (USBC Offset: 0x60C) Pipe Control Set Register */\r
+ RoReg Reserved15[4];\r
+ WoReg USBC_UPCON0CLR; /**< \brief (USBC Offset: 0x620) Pipe Control Clear Register */\r
+ WoReg USBC_UPCON1CLR; /**< \brief (USBC Offset: 0x624) Pipe Control Clear Register */\r
+ WoReg USBC_UPCON2CLR; /**< \brief (USBC Offset: 0x628) Pipe Control Clear Register */\r
+ WoReg USBC_UPCON3CLR; /**< \brief (USBC Offset: 0x62C) Pipe Control Clear Register */\r
+ WoReg USBC_UPCON4CLR; /**< \brief (USBC Offset: 0x630) Pipe Control Clear Register */\r
+ WoReg USBC_UPCON5CLR; /**< \brief (USBC Offset: 0x634) Pipe Control Clear Register */\r
+ WoReg USBC_UPCON6CLR; /**< \brief (USBC Offset: 0x638) Pipe Control Clear Register */\r
+ WoReg USBC_UPCON7CLR; /**< \brief (USBC Offset: 0x63C) Pipe Control Clear Register */\r
+ RoReg Reserved16[4];\r
+ RwReg USBC_UPINRQ0; /**< \brief (USBC Offset: 0x650) Pipe In Request */\r
+ RwReg USBC_UPINRQ1; /**< \brief (USBC Offset: 0x654) Pipe In Request */\r
+ RwReg USBC_UPINRQ2; /**< \brief (USBC Offset: 0x658) Pipe In Request */\r
+ RwReg USBC_UPINRQ3; /**< \brief (USBC Offset: 0x65C) Pipe In Request */\r
+ RwReg USBC_UPINRQ4; /**< \brief (USBC Offset: 0x660) Pipe In Request */\r
+ RwReg USBC_UPINRQ5; /**< \brief (USBC Offset: 0x664) Pipe In Request */\r
+ RwReg USBC_UPINRQ6; /**< \brief (USBC Offset: 0x668) Pipe In Request */\r
+ RwReg USBC_UPINRQ7; /**< \brief (USBC Offset: 0x66C) Pipe In Request */\r
+ RoReg Reserved17[100];\r
+ RwReg USBC_USBCON; /**< \brief (USBC Offset: 0x800) General Control Register */\r
+ RoReg USBC_USBSTA; /**< \brief (USBC Offset: 0x804) General Status Register */\r
+ WoReg USBC_USBSTACLR; /**< \brief (USBC Offset: 0x808) General Status Clear Register */\r
+ WoReg USBC_USBSTASET; /**< \brief (USBC Offset: 0x80C) General Status Set Register */\r
+ RoReg Reserved18[2];\r
+ RoReg USBC_UVERS; /**< \brief (USBC Offset: 0x818) IP Version Register */\r
+ RoReg USBC_UFEATURES; /**< \brief (USBC Offset: 0x81C) IP Features Register */\r
+ RoReg USBC_UADDRSIZE; /**< \brief (USBC Offset: 0x820) IP PB address size Register */\r
+ RoReg USBC_UNAME1; /**< \brief (USBC Offset: 0x824) IP Name Part One: HUSB */\r
+ RoReg USBC_UNAME2; /**< \brief (USBC Offset: 0x828) IP Name Part Two: HOST */\r
+ RoReg USBC_USBFSM; /**< \brief (USBC Offset: 0x82C) USB internal finite state machine */\r
+ RwReg USBC_UDESC; /**< \brief (USBC Offset: 0x830) Endpoint descriptor table */\r
+} Usbc;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- USBC_UDCON : (USBC Offset: 0x000) Device General Control Register -------- */\r
+#define USBC_UDCON_UADD_Pos 0\r
+#define USBC_UDCON_UADD_Msk (0x7Fu << USBC_UDCON_UADD_Pos) /**< \brief (USBC_UDCON) USB Address */\r
+#define USBC_UDCON_UADD(value) ((USBC_UDCON_UADD_Msk & ((value) << USBC_UDCON_UADD_Pos)))\r
+#define USBC_UDCON_ADDEN (0x1u << 7) /**< \brief (USBC_UDCON) Address Enable */\r
+#define USBC_UDCON_DETACH (0x1u << 8) /**< \brief (USBC_UDCON) Detach */\r
+#define USBC_UDCON_RMWKUP (0x1u << 9) /**< \brief (USBC_UDCON) Remote Wake-Up */\r
+#define USBC_UDCON_SPDCONF_Pos 10\r
+#define USBC_UDCON_SPDCONF_Msk (0x3u << USBC_UDCON_SPDCONF_Pos) /**< \brief (USBC_UDCON) Speed configuration */\r
+#define USBC_UDCON_SPDCONF(value) ((USBC_UDCON_SPDCONF_Msk & ((value) << USBC_UDCON_SPDCONF_Pos)))\r
+#define USBC_UDCON_LS (0x1u << 12) /**< \brief (USBC_UDCON) Low Speed Mode Force */\r
+#define USBC_UDCON_TSTJ (0x1u << 13) /**< \brief (USBC_UDCON) Test mode J */\r
+#define USBC_UDCON_TSTK (0x1u << 14) /**< \brief (USBC_UDCON) Test mode K */\r
+#define USBC_UDCON_TSTPCKT (0x1u << 15) /**< \brief (USBC_UDCON) Test Packet mode */\r
+#define USBC_UDCON_OPMODE2 (0x1u << 16) /**< \brief (USBC_UDCON) Specific Operational mode */\r
+#define USBC_UDCON_GNAK (0x1u << 17) /**< \brief (USBC_UDCON) Global NAK */\r
+/* -------- USBC_UDINT : (USBC Offset: 0x004) Device Global Interupt Register -------- */\r
+#define USBC_UDINT_SUSP (0x1u << 0) /**< \brief (USBC_UDINT) Suspend Interrupt */\r
+#define USBC_UDINT_MSOF (0x1u << 1) /**< \brief (USBC_UDINT) Micro Start of Frame Interrupt */\r
+#define USBC_UDINT_SOF (0x1u << 2) /**< \brief (USBC_UDINT) Start of Frame Interrupt */\r
+#define USBC_UDINT_EORST (0x1u << 3) /**< \brief (USBC_UDINT) End of Reset Interrupt */\r
+#define USBC_UDINT_WAKEUP (0x1u << 4) /**< \brief (USBC_UDINT) Wake-Up Interrupt */\r
+#define USBC_UDINT_EORSM (0x1u << 5) /**< \brief (USBC_UDINT) End Of Resume Interrupt */\r
+#define USBC_UDINT_UPRSM (0x1u << 6) /**< \brief (USBC_UDINT) Upstream Resume Interrupt */\r
+#define USBC_UDINT_EP0INT (0x1u << 12) /**< \brief (USBC_UDINT) Endpoint 0 Interrupt */\r
+#define USBC_UDINT_EP1INT (0x1u << 13) /**< \brief (USBC_UDINT) Endpoint 1 Interrupt */\r
+#define USBC_UDINT_EP2INT (0x1u << 14) /**< \brief (USBC_UDINT) Endpoint 2 Interrupt */\r
+#define USBC_UDINT_EP3INT (0x1u << 15) /**< \brief (USBC_UDINT) Endpoint 3 Interrupt */\r
+#define USBC_UDINT_EP4INT (0x1u << 16) /**< \brief (USBC_UDINT) Endpoint 4 Interrupt */\r
+#define USBC_UDINT_EP5INT (0x1u << 17) /**< \brief (USBC_UDINT) Endpoint 5 Interrupt */\r
+#define USBC_UDINT_EP6INT (0x1u << 18) /**< \brief (USBC_UDINT) Endpoint 6 Interrupt */\r
+#define USBC_UDINT_EP7INT (0x1u << 19) /**< \brief (USBC_UDINT) Endpoint 7 Interrupt */\r
+/* -------- USBC_UDINTCLR : (USBC Offset: 0x008) Device Global Interrupt Clear Register -------- */\r
+#define USBC_UDINTCLR_SUSPC (0x1u << 0) /**< \brief (USBC_UDINTCLR) SUSP Interrupt Clear */\r
+#define USBC_UDINTCLR_MSOFC (0x1u << 1) /**< \brief (USBC_UDINTCLR) MSOF Interrupt Clear */\r
+#define USBC_UDINTCLR_SOFC (0x1u << 2) /**< \brief (USBC_UDINTCLR) SOF Interrupt Clear */\r
+#define USBC_UDINTCLR_EORSTC (0x1u << 3) /**< \brief (USBC_UDINTCLR) EORST Interrupt Clear */\r
+#define USBC_UDINTCLR_WAKEUPC (0x1u << 4) /**< \brief (USBC_UDINTCLR) WAKEUP Interrupt Clear */\r
+#define USBC_UDINTCLR_EORSMC (0x1u << 5) /**< \brief (USBC_UDINTCLR) EORSM Interrupt Clear */\r
+#define USBC_UDINTCLR_UPRSMC (0x1u << 6) /**< \brief (USBC_UDINTCLR) UPRSM Interrupt Clear */\r
+/* -------- USBC_UDINTSET : (USBC Offset: 0x00C) Device Global Interrupt Set Regsiter -------- */\r
+#define USBC_UDINTSET_SUSPS (0x1u << 0) /**< \brief (USBC_UDINTSET) SUSP Interrupt Set */\r
+#define USBC_UDINTSET_MSOFS (0x1u << 1) /**< \brief (USBC_UDINTSET) MSOF Interrupt Set */\r
+#define USBC_UDINTSET_SOFS (0x1u << 2) /**< \brief (USBC_UDINTSET) SOF Interrupt Set */\r
+#define USBC_UDINTSET_EORSTS (0x1u << 3) /**< \brief (USBC_UDINTSET) EORST Interrupt Set */\r
+#define USBC_UDINTSET_WAKEUPS (0x1u << 4) /**< \brief (USBC_UDINTSET) WAKEUP Interrupt Set */\r
+#define USBC_UDINTSET_EORSMS (0x1u << 5) /**< \brief (USBC_UDINTSET) EORSM Interrupt Set */\r
+#define USBC_UDINTSET_UPRSMS (0x1u << 6) /**< \brief (USBC_UDINTSET) UPRSM Interrupt Set */\r
+/* -------- USBC_UDINTE : (USBC Offset: 0x010) Device Global Interrupt Enable Register -------- */\r
+#define USBC_UDINTE_SUSPE (0x1u << 0) /**< \brief (USBC_UDINTE) SUSP Interrupt Enable */\r
+#define USBC_UDINTE_MSOFE (0x1u << 1) /**< \brief (USBC_UDINTE) MSOF Interrupt Enable */\r
+#define USBC_UDINTE_SOFE (0x1u << 2) /**< \brief (USBC_UDINTE) SOF Interrupt Enable */\r
+#define USBC_UDINTE_EORSTE (0x1u << 3) /**< \brief (USBC_UDINTE) EORST Interrupt Enable */\r
+#define USBC_UDINTE_WAKEUPE (0x1u << 4) /**< \brief (USBC_UDINTE) WAKEUP Interrupt Enable */\r
+#define USBC_UDINTE_EORSME (0x1u << 5) /**< \brief (USBC_UDINTE) EORSM Interrupt Enable */\r
+#define USBC_UDINTE_UPRSME (0x1u << 6) /**< \brief (USBC_UDINTE) UPRSM Interrupt Enable */\r
+#define USBC_UDINTE_EP0INTE (0x1u << 12) /**< \brief (USBC_UDINTE) EP0INT Interrupt Enable */\r
+#define USBC_UDINTE_EP1INTE (0x1u << 13) /**< \brief (USBC_UDINTE) EP1INT Interrupt Enable */\r
+#define USBC_UDINTE_EP2INTE (0x1u << 14) /**< \brief (USBC_UDINTE) EP2INT Interrupt Enable */\r
+#define USBC_UDINTE_EP3INTE (0x1u << 15) /**< \brief (USBC_UDINTE) EP3INT Interrupt Enable */\r
+#define USBC_UDINTE_EP4INTE (0x1u << 16) /**< \brief (USBC_UDINTE) EP4INT Interrupt Enable */\r
+#define USBC_UDINTE_EP5INTE (0x1u << 17) /**< \brief (USBC_UDINTE) EP5INT Interrupt Enable */\r
+#define USBC_UDINTE_EP6INTE (0x1u << 18) /**< \brief (USBC_UDINTE) EP6INT Interrupt Enable */\r
+#define USBC_UDINTE_EP7INTE (0x1u << 19) /**< \brief (USBC_UDINTE) EP7INT Interrupt Enable */\r
+/* -------- USBC_UDINTECLR : (USBC Offset: 0x014) Device Global Interrupt Enable Clear Register -------- */\r
+#define USBC_UDINTECLR_SUSPEC (0x1u << 0) /**< \brief (USBC_UDINTECLR) SUSP Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_MSOFEC (0x1u << 1) /**< \brief (USBC_UDINTECLR) MSOF Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_SOFEC (0x1u << 2) /**< \brief (USBC_UDINTECLR) SOF Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_EORSTEC (0x1u << 3) /**< \brief (USBC_UDINTECLR) EORST Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_WAKEUPEC (0x1u << 4) /**< \brief (USBC_UDINTECLR) WAKEUP Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_EORSMEC (0x1u << 5) /**< \brief (USBC_UDINTECLR) EORSM Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_UPRSMEC (0x1u << 6) /**< \brief (USBC_UDINTECLR) UPRSM Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_EP0INTEC (0x1u << 12) /**< \brief (USBC_UDINTECLR) EP0INT Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_EP1INTEC (0x1u << 13) /**< \brief (USBC_UDINTECLR) EP1INT Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_EP2INTEC (0x1u << 14) /**< \brief (USBC_UDINTECLR) EP2INT Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_EP3INTEC (0x1u << 15) /**< \brief (USBC_UDINTECLR) EP3INT Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_EP4INTEC (0x1u << 16) /**< \brief (USBC_UDINTECLR) EP4INT Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_EP5INTEC (0x1u << 17) /**< \brief (USBC_UDINTECLR) EP5INT Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_EP6INTEC (0x1u << 18) /**< \brief (USBC_UDINTECLR) EP6INT Interrupt Enable Clear */\r
+#define USBC_UDINTECLR_EP7INTEC (0x1u << 19) /**< \brief (USBC_UDINTECLR) EP7INT Interrupt Enable Clear */\r
+/* -------- USBC_UDINTESET : (USBC Offset: 0x018) Device Global Interrupt Enable Set Register -------- */\r
+#define USBC_UDINTESET_SUSPES (0x1u << 0) /**< \brief (USBC_UDINTESET) SUSP Interrupt Enable Set */\r
+#define USBC_UDINTESET_MSOFES (0x1u << 1) /**< \brief (USBC_UDINTESET) MSOF Interrupt Enable Set */\r
+#define USBC_UDINTESET_SOFES (0x1u << 2) /**< \brief (USBC_UDINTESET) SOF Interrupt Enable Set */\r
+#define USBC_UDINTESET_EORSTES (0x1u << 3) /**< \brief (USBC_UDINTESET) EORST Interrupt Enable Set */\r
+#define USBC_UDINTESET_WAKEUPES (0x1u << 4) /**< \brief (USBC_UDINTESET) WAKEUP Interrupt Enable Set */\r
+#define USBC_UDINTESET_EORSMES (0x1u << 5) /**< \brief (USBC_UDINTESET) EORSM Interrupt Enable Set */\r
+#define USBC_UDINTESET_UPRSMES (0x1u << 6) /**< \brief (USBC_UDINTESET) UPRSM Interrupt Enable Set */\r
+#define USBC_UDINTESET_EP0INTES (0x1u << 12) /**< \brief (USBC_UDINTESET) EP0INT Interrupt Enable Set */\r
+#define USBC_UDINTESET_EP1INTES (0x1u << 13) /**< \brief (USBC_UDINTESET) EP1INT Interrupt Enable Set */\r
+#define USBC_UDINTESET_EP2INTES (0x1u << 14) /**< \brief (USBC_UDINTESET) EP2INT Interrupt Enable Set */\r
+#define USBC_UDINTESET_EP3INTES (0x1u << 15) /**< \brief (USBC_UDINTESET) EP3INT Interrupt Enable Set */\r
+#define USBC_UDINTESET_EP4INTES (0x1u << 16) /**< \brief (USBC_UDINTESET) EP4INT Interrupt Enable Set */\r
+#define USBC_UDINTESET_EP5INTES (0x1u << 17) /**< \brief (USBC_UDINTESET) EP5INT Interrupt Enable Set */\r
+#define USBC_UDINTESET_EP6INTES (0x1u << 18) /**< \brief (USBC_UDINTESET) EP6INT Interrupt Enable Set */\r
+#define USBC_UDINTESET_EP7INTES (0x1u << 19) /**< \brief (USBC_UDINTESET) EP7INT Interrupt Enable Set */\r
+/* -------- USBC_UERST : (USBC Offset: 0x01C) Endpoint Enable/Reset Register -------- */\r
+#define USBC_UERST_EPEN0 (0x1u << 0) /**< \brief (USBC_UERST) Endpoint0 Enable */\r
+#define USBC_UERST_EPEN1 (0x1u << 1) /**< \brief (USBC_UERST) Endpoint1 Enable */\r
+#define USBC_UERST_EPEN2 (0x1u << 2) /**< \brief (USBC_UERST) Endpoint2 Enable */\r
+#define USBC_UERST_EPEN3 (0x1u << 3) /**< \brief (USBC_UERST) Endpoint3 Enable */\r
+#define USBC_UERST_EPEN4 (0x1u << 4) /**< \brief (USBC_UERST) Endpoint4 Enable */\r
+#define USBC_UERST_EPEN5 (0x1u << 5) /**< \brief (USBC_UERST) Endpoint5 Enable */\r
+#define USBC_UERST_EPEN6 (0x1u << 6) /**< \brief (USBC_UERST) Endpoint6 Enable */\r
+#define USBC_UERST_EPEN7 (0x1u << 7) /**< \brief (USBC_UERST) Endpoint7 Enable */\r
+/* -------- USBC_UDFNUM : (USBC Offset: 0x020) Device Frame Number Register -------- */\r
+#define USBC_UDFNUM_MFNUM_Pos 0\r
+#define USBC_UDFNUM_MFNUM_Msk (0x7u << USBC_UDFNUM_MFNUM_Pos) /**< \brief (USBC_UDFNUM) Micro Frame Number */\r
+#define USBC_UDFNUM_MFNUM(value) ((USBC_UDFNUM_MFNUM_Msk & ((value) << USBC_UDFNUM_MFNUM_Pos)))\r
+#define USBC_UDFNUM_FNUM_Pos 3\r
+#define USBC_UDFNUM_FNUM_Msk (0x7FFu << USBC_UDFNUM_FNUM_Pos) /**< \brief (USBC_UDFNUM) Frame Number */\r
+#define USBC_UDFNUM_FNUM(value) ((USBC_UDFNUM_FNUM_Msk & ((value) << USBC_UDFNUM_FNUM_Pos)))\r
+#define USBC_UDFNUM_FNCERR (0x1u << 15) /**< \brief (USBC_UDFNUM) Frame Number CRC Error */\r
+/* -------- USBC_UECFG0 : (USBC Offset: 0x100) Endpoint Configuration Register -------- */\r
+#define USBC_UECFG0_EPBK (0x1u << 2) /**< \brief (USBC_UECFG0) Endpoint Bank */\r
+#define USBC_UECFG0_EPBK_SINGLE (0x0u << 2) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPSIZE_Pos 4\r
+#define USBC_UECFG0_EPSIZE_Msk (0x7u << USBC_UECFG0_EPSIZE_Pos) /**< \brief (USBC_UECFG0) Endpoint Size */\r
+#define USBC_UECFG0_EPSIZE(value) ((USBC_UECFG0_EPSIZE_Msk & ((value) << USBC_UECFG0_EPSIZE_Pos)))\r
+#define USBC_UECFG0_EPSIZE_8 (0x0u << 4) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPSIZE_16 (0x1u << 4) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPSIZE_32 (0x2u << 4) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPSIZE_64 (0x3u << 4) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPSIZE_128 (0x4u << 4) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPSIZE_256 (0x5u << 4) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPSIZE_512 (0x6u << 4) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPSIZE_1024 (0x7u << 4) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPDIR (0x1u << 8) /**< \brief (USBC_UECFG0) Endpoint Direction */\r
+#define USBC_UECFG0_EPDIR_OUT (0x0u << 8) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPDIR_IN (0x1u << 8) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPTYPE_Pos 11\r
+#define USBC_UECFG0_EPTYPE_Msk (0x3u << USBC_UECFG0_EPTYPE_Pos) /**< \brief (USBC_UECFG0) Endpoint Type */\r
+#define USBC_UECFG0_EPTYPE(value) ((USBC_UECFG0_EPTYPE_Msk & ((value) << USBC_UECFG0_EPTYPE_Pos)))\r
+#define USBC_UECFG0_EPTYPE_CONTROL (0x0u << 11) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPTYPE_ISOCHRONOUS (0x1u << 11) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPTYPE_BULK (0x2u << 11) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_EPTYPE_INTERRUPT (0x3u << 11) /**< \brief (USBC_UECFG0) */\r
+#define USBC_UECFG0_REPNB_Pos 16\r
+#define USBC_UECFG0_REPNB_Msk (0xFu << USBC_UECFG0_REPNB_Pos) /**< \brief (USBC_UECFG0) Redirected Endpoint Number */\r
+#define USBC_UECFG0_REPNB(value) ((USBC_UECFG0_REPNB_Msk & ((value) << USBC_UECFG0_REPNB_Pos)))\r
+/* -------- USBC_UECFG1 : (USBC Offset: 0x104) Endpoint Configuration Register -------- */\r
+#define USBC_UECFG1_EPBK (0x1u << 2) /**< \brief (USBC_UECFG1) Endpoint Bank */\r
+#define USBC_UECFG1_EPBK_SINGLE (0x0u << 2) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPSIZE_Pos 4\r
+#define USBC_UECFG1_EPSIZE_Msk (0x7u << USBC_UECFG1_EPSIZE_Pos) /**< \brief (USBC_UECFG1) Endpoint Size */\r
+#define USBC_UECFG1_EPSIZE(value) ((USBC_UECFG1_EPSIZE_Msk & ((value) << USBC_UECFG1_EPSIZE_Pos)))\r
+#define USBC_UECFG1_EPSIZE_8 (0x0u << 4) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPSIZE_16 (0x1u << 4) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPSIZE_32 (0x2u << 4) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPSIZE_64 (0x3u << 4) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPSIZE_128 (0x4u << 4) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPSIZE_256 (0x5u << 4) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPSIZE_512 (0x6u << 4) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPSIZE_1024 (0x7u << 4) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPDIR (0x1u << 8) /**< \brief (USBC_UECFG1) Endpoint Direction */\r
+#define USBC_UECFG1_EPDIR_OUT (0x0u << 8) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPDIR_IN (0x1u << 8) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPTYPE_Pos 11\r
+#define USBC_UECFG1_EPTYPE_Msk (0x3u << USBC_UECFG1_EPTYPE_Pos) /**< \brief (USBC_UECFG1) Endpoint Type */\r
+#define USBC_UECFG1_EPTYPE(value) ((USBC_UECFG1_EPTYPE_Msk & ((value) << USBC_UECFG1_EPTYPE_Pos)))\r
+#define USBC_UECFG1_EPTYPE_CONTROL (0x0u << 11) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPTYPE_ISOCHRONOUS (0x1u << 11) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPTYPE_BULK (0x2u << 11) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_EPTYPE_INTERRUPT (0x3u << 11) /**< \brief (USBC_UECFG1) */\r
+#define USBC_UECFG1_REPNB_Pos 16\r
+#define USBC_UECFG1_REPNB_Msk (0xFu << USBC_UECFG1_REPNB_Pos) /**< \brief (USBC_UECFG1) Redirected Endpoint Number */\r
+#define USBC_UECFG1_REPNB(value) ((USBC_UECFG1_REPNB_Msk & ((value) << USBC_UECFG1_REPNB_Pos)))\r
+/* -------- USBC_UECFG2 : (USBC Offset: 0x108) Endpoint Configuration Register -------- */\r
+#define USBC_UECFG2_EPBK (0x1u << 2) /**< \brief (USBC_UECFG2) Endpoint Bank */\r
+#define USBC_UECFG2_EPBK_SINGLE (0x0u << 2) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPSIZE_Pos 4\r
+#define USBC_UECFG2_EPSIZE_Msk (0x7u << USBC_UECFG2_EPSIZE_Pos) /**< \brief (USBC_UECFG2) Endpoint Size */\r
+#define USBC_UECFG2_EPSIZE(value) ((USBC_UECFG2_EPSIZE_Msk & ((value) << USBC_UECFG2_EPSIZE_Pos)))\r
+#define USBC_UECFG2_EPSIZE_8 (0x0u << 4) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPSIZE_16 (0x1u << 4) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPSIZE_32 (0x2u << 4) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPSIZE_64 (0x3u << 4) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPSIZE_128 (0x4u << 4) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPSIZE_256 (0x5u << 4) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPSIZE_512 (0x6u << 4) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPSIZE_1024 (0x7u << 4) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPDIR (0x1u << 8) /**< \brief (USBC_UECFG2) Endpoint Direction */\r
+#define USBC_UECFG2_EPDIR_OUT (0x0u << 8) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPDIR_IN (0x1u << 8) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPTYPE_Pos 11\r
+#define USBC_UECFG2_EPTYPE_Msk (0x3u << USBC_UECFG2_EPTYPE_Pos) /**< \brief (USBC_UECFG2) Endpoint Type */\r
+#define USBC_UECFG2_EPTYPE(value) ((USBC_UECFG2_EPTYPE_Msk & ((value) << USBC_UECFG2_EPTYPE_Pos)))\r
+#define USBC_UECFG2_EPTYPE_CONTROL (0x0u << 11) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPTYPE_ISOCHRONOUS (0x1u << 11) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPTYPE_BULK (0x2u << 11) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_EPTYPE_INTERRUPT (0x3u << 11) /**< \brief (USBC_UECFG2) */\r
+#define USBC_UECFG2_REPNB_Pos 16\r
+#define USBC_UECFG2_REPNB_Msk (0xFu << USBC_UECFG2_REPNB_Pos) /**< \brief (USBC_UECFG2) Redirected Endpoint Number */\r
+#define USBC_UECFG2_REPNB(value) ((USBC_UECFG2_REPNB_Msk & ((value) << USBC_UECFG2_REPNB_Pos)))\r
+/* -------- USBC_UECFG3 : (USBC Offset: 0x10C) Endpoint Configuration Register -------- */\r
+#define USBC_UECFG3_EPBK (0x1u << 2) /**< \brief (USBC_UECFG3) Endpoint Bank */\r
+#define USBC_UECFG3_EPBK_SINGLE (0x0u << 2) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPSIZE_Pos 4\r
+#define USBC_UECFG3_EPSIZE_Msk (0x7u << USBC_UECFG3_EPSIZE_Pos) /**< \brief (USBC_UECFG3) Endpoint Size */\r
+#define USBC_UECFG3_EPSIZE(value) ((USBC_UECFG3_EPSIZE_Msk & ((value) << USBC_UECFG3_EPSIZE_Pos)))\r
+#define USBC_UECFG3_EPSIZE_8 (0x0u << 4) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPSIZE_16 (0x1u << 4) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPSIZE_32 (0x2u << 4) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPSIZE_64 (0x3u << 4) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPSIZE_128 (0x4u << 4) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPSIZE_256 (0x5u << 4) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPSIZE_512 (0x6u << 4) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPSIZE_1024 (0x7u << 4) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPDIR (0x1u << 8) /**< \brief (USBC_UECFG3) Endpoint Direction */\r
+#define USBC_UECFG3_EPDIR_OUT (0x0u << 8) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPDIR_IN (0x1u << 8) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPTYPE_Pos 11\r
+#define USBC_UECFG3_EPTYPE_Msk (0x3u << USBC_UECFG3_EPTYPE_Pos) /**< \brief (USBC_UECFG3) Endpoint Type */\r
+#define USBC_UECFG3_EPTYPE(value) ((USBC_UECFG3_EPTYPE_Msk & ((value) << USBC_UECFG3_EPTYPE_Pos)))\r
+#define USBC_UECFG3_EPTYPE_CONTROL (0x0u << 11) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPTYPE_ISOCHRONOUS (0x1u << 11) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPTYPE_BULK (0x2u << 11) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_EPTYPE_INTERRUPT (0x3u << 11) /**< \brief (USBC_UECFG3) */\r
+#define USBC_UECFG3_REPNB_Pos 16\r
+#define USBC_UECFG3_REPNB_Msk (0xFu << USBC_UECFG3_REPNB_Pos) /**< \brief (USBC_UECFG3) Redirected Endpoint Number */\r
+#define USBC_UECFG3_REPNB(value) ((USBC_UECFG3_REPNB_Msk & ((value) << USBC_UECFG3_REPNB_Pos)))\r
+/* -------- USBC_UECFG4 : (USBC Offset: 0x110) Endpoint Configuration Register -------- */\r
+#define USBC_UECFG4_EPBK (0x1u << 2) /**< \brief (USBC_UECFG4) Endpoint Bank */\r
+#define USBC_UECFG4_EPBK_SINGLE (0x0u << 2) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPSIZE_Pos 4\r
+#define USBC_UECFG4_EPSIZE_Msk (0x7u << USBC_UECFG4_EPSIZE_Pos) /**< \brief (USBC_UECFG4) Endpoint Size */\r
+#define USBC_UECFG4_EPSIZE(value) ((USBC_UECFG4_EPSIZE_Msk & ((value) << USBC_UECFG4_EPSIZE_Pos)))\r
+#define USBC_UECFG4_EPSIZE_8 (0x0u << 4) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPSIZE_16 (0x1u << 4) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPSIZE_32 (0x2u << 4) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPSIZE_64 (0x3u << 4) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPSIZE_128 (0x4u << 4) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPSIZE_256 (0x5u << 4) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPSIZE_512 (0x6u << 4) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPSIZE_1024 (0x7u << 4) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPDIR (0x1u << 8) /**< \brief (USBC_UECFG4) Endpoint Direction */\r
+#define USBC_UECFG4_EPDIR_OUT (0x0u << 8) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPDIR_IN (0x1u << 8) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPTYPE_Pos 11\r
+#define USBC_UECFG4_EPTYPE_Msk (0x3u << USBC_UECFG4_EPTYPE_Pos) /**< \brief (USBC_UECFG4) Endpoint Type */\r
+#define USBC_UECFG4_EPTYPE(value) ((USBC_UECFG4_EPTYPE_Msk & ((value) << USBC_UECFG4_EPTYPE_Pos)))\r
+#define USBC_UECFG4_EPTYPE_CONTROL (0x0u << 11) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPTYPE_ISOCHRONOUS (0x1u << 11) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPTYPE_BULK (0x2u << 11) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_EPTYPE_INTERRUPT (0x3u << 11) /**< \brief (USBC_UECFG4) */\r
+#define USBC_UECFG4_REPNB_Pos 16\r
+#define USBC_UECFG4_REPNB_Msk (0xFu << USBC_UECFG4_REPNB_Pos) /**< \brief (USBC_UECFG4) Redirected Endpoint Number */\r
+#define USBC_UECFG4_REPNB(value) ((USBC_UECFG4_REPNB_Msk & ((value) << USBC_UECFG4_REPNB_Pos)))\r
+/* -------- USBC_UECFG5 : (USBC Offset: 0x114) Endpoint Configuration Register -------- */\r
+#define USBC_UECFG5_EPBK (0x1u << 2) /**< \brief (USBC_UECFG5) Endpoint Bank */\r
+#define USBC_UECFG5_EPBK_SINGLE (0x0u << 2) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPSIZE_Pos 4\r
+#define USBC_UECFG5_EPSIZE_Msk (0x7u << USBC_UECFG5_EPSIZE_Pos) /**< \brief (USBC_UECFG5) Endpoint Size */\r
+#define USBC_UECFG5_EPSIZE(value) ((USBC_UECFG5_EPSIZE_Msk & ((value) << USBC_UECFG5_EPSIZE_Pos)))\r
+#define USBC_UECFG5_EPSIZE_8 (0x0u << 4) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPSIZE_16 (0x1u << 4) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPSIZE_32 (0x2u << 4) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPSIZE_64 (0x3u << 4) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPSIZE_128 (0x4u << 4) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPSIZE_256 (0x5u << 4) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPSIZE_512 (0x6u << 4) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPSIZE_1024 (0x7u << 4) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPDIR (0x1u << 8) /**< \brief (USBC_UECFG5) Endpoint Direction */\r
+#define USBC_UECFG5_EPDIR_OUT (0x0u << 8) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPDIR_IN (0x1u << 8) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPTYPE_Pos 11\r
+#define USBC_UECFG5_EPTYPE_Msk (0x3u << USBC_UECFG5_EPTYPE_Pos) /**< \brief (USBC_UECFG5) Endpoint Type */\r
+#define USBC_UECFG5_EPTYPE(value) ((USBC_UECFG5_EPTYPE_Msk & ((value) << USBC_UECFG5_EPTYPE_Pos)))\r
+#define USBC_UECFG5_EPTYPE_CONTROL (0x0u << 11) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPTYPE_ISOCHRONOUS (0x1u << 11) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPTYPE_BULK (0x2u << 11) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_EPTYPE_INTERRUPT (0x3u << 11) /**< \brief (USBC_UECFG5) */\r
+#define USBC_UECFG5_REPNB_Pos 16\r
+#define USBC_UECFG5_REPNB_Msk (0xFu << USBC_UECFG5_REPNB_Pos) /**< \brief (USBC_UECFG5) Redirected Endpoint Number */\r
+#define USBC_UECFG5_REPNB(value) ((USBC_UECFG5_REPNB_Msk & ((value) << USBC_UECFG5_REPNB_Pos)))\r
+/* -------- USBC_UECFG6 : (USBC Offset: 0x118) Endpoint Configuration Register -------- */\r
+#define USBC_UECFG6_EPBK (0x1u << 2) /**< \brief (USBC_UECFG6) Endpoint Bank */\r
+#define USBC_UECFG6_EPBK_SINGLE (0x0u << 2) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPSIZE_Pos 4\r
+#define USBC_UECFG6_EPSIZE_Msk (0x7u << USBC_UECFG6_EPSIZE_Pos) /**< \brief (USBC_UECFG6) Endpoint Size */\r
+#define USBC_UECFG6_EPSIZE(value) ((USBC_UECFG6_EPSIZE_Msk & ((value) << USBC_UECFG6_EPSIZE_Pos)))\r
+#define USBC_UECFG6_EPSIZE_8 (0x0u << 4) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPSIZE_16 (0x1u << 4) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPSIZE_32 (0x2u << 4) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPSIZE_64 (0x3u << 4) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPSIZE_128 (0x4u << 4) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPSIZE_256 (0x5u << 4) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPSIZE_512 (0x6u << 4) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPSIZE_1024 (0x7u << 4) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPDIR (0x1u << 8) /**< \brief (USBC_UECFG6) Endpoint Direction */\r
+#define USBC_UECFG6_EPDIR_OUT (0x0u << 8) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPDIR_IN (0x1u << 8) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPTYPE_Pos 11\r
+#define USBC_UECFG6_EPTYPE_Msk (0x3u << USBC_UECFG6_EPTYPE_Pos) /**< \brief (USBC_UECFG6) Endpoint Type */\r
+#define USBC_UECFG6_EPTYPE(value) ((USBC_UECFG6_EPTYPE_Msk & ((value) << USBC_UECFG6_EPTYPE_Pos)))\r
+#define USBC_UECFG6_EPTYPE_CONTROL (0x0u << 11) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPTYPE_ISOCHRONOUS (0x1u << 11) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPTYPE_BULK (0x2u << 11) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_EPTYPE_INTERRUPT (0x3u << 11) /**< \brief (USBC_UECFG6) */\r
+#define USBC_UECFG6_REPNB_Pos 16\r
+#define USBC_UECFG6_REPNB_Msk (0xFu << USBC_UECFG6_REPNB_Pos) /**< \brief (USBC_UECFG6) Redirected Endpoint Number */\r
+#define USBC_UECFG6_REPNB(value) ((USBC_UECFG6_REPNB_Msk & ((value) << USBC_UECFG6_REPNB_Pos)))\r
+/* -------- USBC_UECFG7 : (USBC Offset: 0x11C) Endpoint Configuration Register -------- */\r
+#define USBC_UECFG7_EPBK (0x1u << 2) /**< \brief (USBC_UECFG7) Endpoint Bank */\r
+#define USBC_UECFG7_EPBK_SINGLE (0x0u << 2) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPSIZE_Pos 4\r
+#define USBC_UECFG7_EPSIZE_Msk (0x7u << USBC_UECFG7_EPSIZE_Pos) /**< \brief (USBC_UECFG7) Endpoint Size */\r
+#define USBC_UECFG7_EPSIZE(value) ((USBC_UECFG7_EPSIZE_Msk & ((value) << USBC_UECFG7_EPSIZE_Pos)))\r
+#define USBC_UECFG7_EPSIZE_8 (0x0u << 4) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPSIZE_16 (0x1u << 4) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPSIZE_32 (0x2u << 4) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPSIZE_64 (0x3u << 4) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPSIZE_128 (0x4u << 4) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPSIZE_256 (0x5u << 4) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPSIZE_512 (0x6u << 4) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPSIZE_1024 (0x7u << 4) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPDIR (0x1u << 8) /**< \brief (USBC_UECFG7) Endpoint Direction */\r
+#define USBC_UECFG7_EPDIR_OUT (0x0u << 8) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPDIR_IN (0x1u << 8) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPTYPE_Pos 11\r
+#define USBC_UECFG7_EPTYPE_Msk (0x3u << USBC_UECFG7_EPTYPE_Pos) /**< \brief (USBC_UECFG7) Endpoint Type */\r
+#define USBC_UECFG7_EPTYPE(value) ((USBC_UECFG7_EPTYPE_Msk & ((value) << USBC_UECFG7_EPTYPE_Pos)))\r
+#define USBC_UECFG7_EPTYPE_CONTROL (0x0u << 11) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPTYPE_ISOCHRONOUS (0x1u << 11) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPTYPE_BULK (0x2u << 11) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_EPTYPE_INTERRUPT (0x3u << 11) /**< \brief (USBC_UECFG7) */\r
+#define USBC_UECFG7_REPNB_Pos 16\r
+#define USBC_UECFG7_REPNB_Msk (0xFu << USBC_UECFG7_REPNB_Pos) /**< \brief (USBC_UECFG7) Redirected Endpoint Number */\r
+#define USBC_UECFG7_REPNB(value) ((USBC_UECFG7_REPNB_Msk & ((value) << USBC_UECFG7_REPNB_Pos)))\r
+/* -------- USBC_UESTA0 : (USBC Offset: 0x130) Endpoint Status Register -------- */\r
+#define USBC_UESTA0_TXINI (0x1u << 0) /**< \brief (USBC_UESTA0) Transmitted IN Data Interrupt */\r
+#define USBC_UESTA0_RXOUTI (0x1u << 1) /**< \brief (USBC_UESTA0) Received OUT Data Interrupt */\r
+#define USBC_UESTA0_RXSTPI (0x1u << 2) /**< \brief (USBC_UESTA0) Received SETUP Interrupt */\r
+#define USBC_UESTA0_NAKOUTI (0x1u << 3) /**< \brief (USBC_UESTA0) NAKed OUT Interrupt */\r
+#define USBC_UESTA0_NAKINI (0x1u << 4) /**< \brief (USBC_UESTA0) NAKed IN Interrupt */\r
+#define USBC_UESTA0_STALLEDI (0x1u << 6) /**< \brief (USBC_UESTA0) STALLed Interrupt */\r
+#define USBC_UESTA0_DTSEQ_Pos 8\r
+#define USBC_UESTA0_DTSEQ_Msk (0x3u << USBC_UESTA0_DTSEQ_Pos) /**< \brief (USBC_UESTA0) Data Toggle Sequence */\r
+#define USBC_UESTA0_DTSEQ(value) ((USBC_UESTA0_DTSEQ_Msk & ((value) << USBC_UESTA0_DTSEQ_Pos)))\r
+#define USBC_UESTA0_RAMACERI (0x1u << 11) /**< \brief (USBC_UESTA0) Ram Access Error Interrupt */\r
+#define USBC_UESTA0_NBUSYBK_Pos 12\r
+#define USBC_UESTA0_NBUSYBK_Msk (0x3u << USBC_UESTA0_NBUSYBK_Pos) /**< \brief (USBC_UESTA0) Number Of Busy Banks */\r
+#define USBC_UESTA0_NBUSYBK(value) ((USBC_UESTA0_NBUSYBK_Msk & ((value) << USBC_UESTA0_NBUSYBK_Pos)))\r
+#define USBC_UESTA0_CURRBK_Pos 14\r
+#define USBC_UESTA0_CURRBK_Msk (0x3u << USBC_UESTA0_CURRBK_Pos) /**< \brief (USBC_UESTA0) Current Bank */\r
+#define USBC_UESTA0_CURRBK(value) ((USBC_UESTA0_CURRBK_Msk & ((value) << USBC_UESTA0_CURRBK_Pos)))\r
+#define USBC_UESTA0_CTRLDIR (0x1u << 17) /**< \brief (USBC_UESTA0) Control Direction */\r
+#define USBC_UESTA0_CTRLDIR_OUT (0x0u << 17) /**< \brief (USBC_UESTA0) */\r
+#define USBC_UESTA0_CTRLDIR_IN (0x1u << 17) /**< \brief (USBC_UESTA0) */\r
+/* -------- USBC_UESTA1 : (USBC Offset: 0x134) Endpoint Status Register -------- */\r
+#define USBC_UESTA1_TXINI (0x1u << 0) /**< \brief (USBC_UESTA1) Transmitted IN Data Interrupt */\r
+#define USBC_UESTA1_RXOUTI (0x1u << 1) /**< \brief (USBC_UESTA1) Received OUT Data Interrupt */\r
+#define USBC_UESTA1_RXSTPI (0x1u << 2) /**< \brief (USBC_UESTA1) Received SETUP Interrupt */\r
+#define USBC_UESTA1_NAKOUTI (0x1u << 3) /**< \brief (USBC_UESTA1) NAKed OUT Interrupt */\r
+#define USBC_UESTA1_NAKINI (0x1u << 4) /**< \brief (USBC_UESTA1) NAKed IN Interrupt */\r
+#define USBC_UESTA1_STALLEDI (0x1u << 6) /**< \brief (USBC_UESTA1) STALLed Interrupt */\r
+#define USBC_UESTA1_DTSEQ_Pos 8\r
+#define USBC_UESTA1_DTSEQ_Msk (0x3u << USBC_UESTA1_DTSEQ_Pos) /**< \brief (USBC_UESTA1) Data Toggle Sequence */\r
+#define USBC_UESTA1_DTSEQ(value) ((USBC_UESTA1_DTSEQ_Msk & ((value) << USBC_UESTA1_DTSEQ_Pos)))\r
+#define USBC_UESTA1_RAMACERI (0x1u << 11) /**< \brief (USBC_UESTA1) Ram Access Error Interrupt */\r
+#define USBC_UESTA1_NBUSYBK_Pos 12\r
+#define USBC_UESTA1_NBUSYBK_Msk (0x3u << USBC_UESTA1_NBUSYBK_Pos) /**< \brief (USBC_UESTA1) Number Of Busy Banks */\r
+#define USBC_UESTA1_NBUSYBK(value) ((USBC_UESTA1_NBUSYBK_Msk & ((value) << USBC_UESTA1_NBUSYBK_Pos)))\r
+#define USBC_UESTA1_CURRBK_Pos 14\r
+#define USBC_UESTA1_CURRBK_Msk (0x3u << USBC_UESTA1_CURRBK_Pos) /**< \brief (USBC_UESTA1) Current Bank */\r
+#define USBC_UESTA1_CURRBK(value) ((USBC_UESTA1_CURRBK_Msk & ((value) << USBC_UESTA1_CURRBK_Pos)))\r
+#define USBC_UESTA1_CTRLDIR (0x1u << 17) /**< \brief (USBC_UESTA1) Control Direction */\r
+#define USBC_UESTA1_CTRLDIR_OUT (0x0u << 17) /**< \brief (USBC_UESTA1) */\r
+#define USBC_UESTA1_CTRLDIR_IN (0x1u << 17) /**< \brief (USBC_UESTA1) */\r
+/* -------- USBC_UESTA2 : (USBC Offset: 0x138) Endpoint Status Register -------- */\r
+#define USBC_UESTA2_TXINI (0x1u << 0) /**< \brief (USBC_UESTA2) Transmitted IN Data Interrupt */\r
+#define USBC_UESTA2_RXOUTI (0x1u << 1) /**< \brief (USBC_UESTA2) Received OUT Data Interrupt */\r
+#define USBC_UESTA2_RXSTPI (0x1u << 2) /**< \brief (USBC_UESTA2) Received SETUP Interrupt */\r
+#define USBC_UESTA2_NAKOUTI (0x1u << 3) /**< \brief (USBC_UESTA2) NAKed OUT Interrupt */\r
+#define USBC_UESTA2_NAKINI (0x1u << 4) /**< \brief (USBC_UESTA2) NAKed IN Interrupt */\r
+#define USBC_UESTA2_STALLEDI (0x1u << 6) /**< \brief (USBC_UESTA2) STALLed Interrupt */\r
+#define USBC_UESTA2_DTSEQ_Pos 8\r
+#define USBC_UESTA2_DTSEQ_Msk (0x3u << USBC_UESTA2_DTSEQ_Pos) /**< \brief (USBC_UESTA2) Data Toggle Sequence */\r
+#define USBC_UESTA2_DTSEQ(value) ((USBC_UESTA2_DTSEQ_Msk & ((value) << USBC_UESTA2_DTSEQ_Pos)))\r
+#define USBC_UESTA2_RAMACERI (0x1u << 11) /**< \brief (USBC_UESTA2) Ram Access Error Interrupt */\r
+#define USBC_UESTA2_NBUSYBK_Pos 12\r
+#define USBC_UESTA2_NBUSYBK_Msk (0x3u << USBC_UESTA2_NBUSYBK_Pos) /**< \brief (USBC_UESTA2) Number Of Busy Banks */\r
+#define USBC_UESTA2_NBUSYBK(value) ((USBC_UESTA2_NBUSYBK_Msk & ((value) << USBC_UESTA2_NBUSYBK_Pos)))\r
+#define USBC_UESTA2_CURRBK_Pos 14\r
+#define USBC_UESTA2_CURRBK_Msk (0x3u << USBC_UESTA2_CURRBK_Pos) /**< \brief (USBC_UESTA2) Current Bank */\r
+#define USBC_UESTA2_CURRBK(value) ((USBC_UESTA2_CURRBK_Msk & ((value) << USBC_UESTA2_CURRBK_Pos)))\r
+#define USBC_UESTA2_CTRLDIR (0x1u << 17) /**< \brief (USBC_UESTA2) Control Direction */\r
+#define USBC_UESTA2_CTRLDIR_OUT (0x0u << 17) /**< \brief (USBC_UESTA2) */\r
+#define USBC_UESTA2_CTRLDIR_IN (0x1u << 17) /**< \brief (USBC_UESTA2) */\r
+/* -------- USBC_UESTA3 : (USBC Offset: 0x13C) Endpoint Status Register -------- */\r
+#define USBC_UESTA3_TXINI (0x1u << 0) /**< \brief (USBC_UESTA3) Transmitted IN Data Interrupt */\r
+#define USBC_UESTA3_RXOUTI (0x1u << 1) /**< \brief (USBC_UESTA3) Received OUT Data Interrupt */\r
+#define USBC_UESTA3_RXSTPI (0x1u << 2) /**< \brief (USBC_UESTA3) Received SETUP Interrupt */\r
+#define USBC_UESTA3_NAKOUTI (0x1u << 3) /**< \brief (USBC_UESTA3) NAKed OUT Interrupt */\r
+#define USBC_UESTA3_NAKINI (0x1u << 4) /**< \brief (USBC_UESTA3) NAKed IN Interrupt */\r
+#define USBC_UESTA3_STALLEDI (0x1u << 6) /**< \brief (USBC_UESTA3) STALLed Interrupt */\r
+#define USBC_UESTA3_DTSEQ_Pos 8\r
+#define USBC_UESTA3_DTSEQ_Msk (0x3u << USBC_UESTA3_DTSEQ_Pos) /**< \brief (USBC_UESTA3) Data Toggle Sequence */\r
+#define USBC_UESTA3_DTSEQ(value) ((USBC_UESTA3_DTSEQ_Msk & ((value) << USBC_UESTA3_DTSEQ_Pos)))\r
+#define USBC_UESTA3_RAMACERI (0x1u << 11) /**< \brief (USBC_UESTA3) Ram Access Error Interrupt */\r
+#define USBC_UESTA3_NBUSYBK_Pos 12\r
+#define USBC_UESTA3_NBUSYBK_Msk (0x3u << USBC_UESTA3_NBUSYBK_Pos) /**< \brief (USBC_UESTA3) Number Of Busy Banks */\r
+#define USBC_UESTA3_NBUSYBK(value) ((USBC_UESTA3_NBUSYBK_Msk & ((value) << USBC_UESTA3_NBUSYBK_Pos)))\r
+#define USBC_UESTA3_CURRBK_Pos 14\r
+#define USBC_UESTA3_CURRBK_Msk (0x3u << USBC_UESTA3_CURRBK_Pos) /**< \brief (USBC_UESTA3) Current Bank */\r
+#define USBC_UESTA3_CURRBK(value) ((USBC_UESTA3_CURRBK_Msk & ((value) << USBC_UESTA3_CURRBK_Pos)))\r
+#define USBC_UESTA3_CTRLDIR (0x1u << 17) /**< \brief (USBC_UESTA3) Control Direction */\r
+#define USBC_UESTA3_CTRLDIR_OUT (0x0u << 17) /**< \brief (USBC_UESTA3) */\r
+#define USBC_UESTA3_CTRLDIR_IN (0x1u << 17) /**< \brief (USBC_UESTA3) */\r
+/* -------- USBC_UESTA4 : (USBC Offset: 0x140) Endpoint Status Register -------- */\r
+#define USBC_UESTA4_TXINI (0x1u << 0) /**< \brief (USBC_UESTA4) Transmitted IN Data Interrupt */\r
+#define USBC_UESTA4_RXOUTI (0x1u << 1) /**< \brief (USBC_UESTA4) Received OUT Data Interrupt */\r
+#define USBC_UESTA4_RXSTPI (0x1u << 2) /**< \brief (USBC_UESTA4) Received SETUP Interrupt */\r
+#define USBC_UESTA4_NAKOUTI (0x1u << 3) /**< \brief (USBC_UESTA4) NAKed OUT Interrupt */\r
+#define USBC_UESTA4_NAKINI (0x1u << 4) /**< \brief (USBC_UESTA4) NAKed IN Interrupt */\r
+#define USBC_UESTA4_STALLEDI (0x1u << 6) /**< \brief (USBC_UESTA4) STALLed Interrupt */\r
+#define USBC_UESTA4_DTSEQ_Pos 8\r
+#define USBC_UESTA4_DTSEQ_Msk (0x3u << USBC_UESTA4_DTSEQ_Pos) /**< \brief (USBC_UESTA4) Data Toggle Sequence */\r
+#define USBC_UESTA4_DTSEQ(value) ((USBC_UESTA4_DTSEQ_Msk & ((value) << USBC_UESTA4_DTSEQ_Pos)))\r
+#define USBC_UESTA4_RAMACERI (0x1u << 11) /**< \brief (USBC_UESTA4) Ram Access Error Interrupt */\r
+#define USBC_UESTA4_NBUSYBK_Pos 12\r
+#define USBC_UESTA4_NBUSYBK_Msk (0x3u << USBC_UESTA4_NBUSYBK_Pos) /**< \brief (USBC_UESTA4) Number Of Busy Banks */\r
+#define USBC_UESTA4_NBUSYBK(value) ((USBC_UESTA4_NBUSYBK_Msk & ((value) << USBC_UESTA4_NBUSYBK_Pos)))\r
+#define USBC_UESTA4_CURRBK_Pos 14\r
+#define USBC_UESTA4_CURRBK_Msk (0x3u << USBC_UESTA4_CURRBK_Pos) /**< \brief (USBC_UESTA4) Current Bank */\r
+#define USBC_UESTA4_CURRBK(value) ((USBC_UESTA4_CURRBK_Msk & ((value) << USBC_UESTA4_CURRBK_Pos)))\r
+#define USBC_UESTA4_CTRLDIR (0x1u << 17) /**< \brief (USBC_UESTA4) Control Direction */\r
+#define USBC_UESTA4_CTRLDIR_OUT (0x0u << 17) /**< \brief (USBC_UESTA4) */\r
+#define USBC_UESTA4_CTRLDIR_IN (0x1u << 17) /**< \brief (USBC_UESTA4) */\r
+/* -------- USBC_UESTA5 : (USBC Offset: 0x144) Endpoint Status Register -------- */\r
+#define USBC_UESTA5_TXINI (0x1u << 0) /**< \brief (USBC_UESTA5) Transmitted IN Data Interrupt */\r
+#define USBC_UESTA5_RXOUTI (0x1u << 1) /**< \brief (USBC_UESTA5) Received OUT Data Interrupt */\r
+#define USBC_UESTA5_RXSTPI (0x1u << 2) /**< \brief (USBC_UESTA5) Received SETUP Interrupt */\r
+#define USBC_UESTA5_NAKOUTI (0x1u << 3) /**< \brief (USBC_UESTA5) NAKed OUT Interrupt */\r
+#define USBC_UESTA5_NAKINI (0x1u << 4) /**< \brief (USBC_UESTA5) NAKed IN Interrupt */\r
+#define USBC_UESTA5_STALLEDI (0x1u << 6) /**< \brief (USBC_UESTA5) STALLed Interrupt */\r
+#define USBC_UESTA5_DTSEQ_Pos 8\r
+#define USBC_UESTA5_DTSEQ_Msk (0x3u << USBC_UESTA5_DTSEQ_Pos) /**< \brief (USBC_UESTA5) Data Toggle Sequence */\r
+#define USBC_UESTA5_DTSEQ(value) ((USBC_UESTA5_DTSEQ_Msk & ((value) << USBC_UESTA5_DTSEQ_Pos)))\r
+#define USBC_UESTA5_RAMACERI (0x1u << 11) /**< \brief (USBC_UESTA5) Ram Access Error Interrupt */\r
+#define USBC_UESTA5_NBUSYBK_Pos 12\r
+#define USBC_UESTA5_NBUSYBK_Msk (0x3u << USBC_UESTA5_NBUSYBK_Pos) /**< \brief (USBC_UESTA5) Number Of Busy Banks */\r
+#define USBC_UESTA5_NBUSYBK(value) ((USBC_UESTA5_NBUSYBK_Msk & ((value) << USBC_UESTA5_NBUSYBK_Pos)))\r
+#define USBC_UESTA5_CURRBK_Pos 14\r
+#define USBC_UESTA5_CURRBK_Msk (0x3u << USBC_UESTA5_CURRBK_Pos) /**< \brief (USBC_UESTA5) Current Bank */\r
+#define USBC_UESTA5_CURRBK(value) ((USBC_UESTA5_CURRBK_Msk & ((value) << USBC_UESTA5_CURRBK_Pos)))\r
+#define USBC_UESTA5_CTRLDIR (0x1u << 17) /**< \brief (USBC_UESTA5) Control Direction */\r
+#define USBC_UESTA5_CTRLDIR_OUT (0x0u << 17) /**< \brief (USBC_UESTA5) */\r
+#define USBC_UESTA5_CTRLDIR_IN (0x1u << 17) /**< \brief (USBC_UESTA5) */\r
+/* -------- USBC_UESTA6 : (USBC Offset: 0x148) Endpoint Status Register -------- */\r
+#define USBC_UESTA6_TXINI (0x1u << 0) /**< \brief (USBC_UESTA6) Transmitted IN Data Interrupt */\r
+#define USBC_UESTA6_RXOUTI (0x1u << 1) /**< \brief (USBC_UESTA6) Received OUT Data Interrupt */\r
+#define USBC_UESTA6_RXSTPI (0x1u << 2) /**< \brief (USBC_UESTA6) Received SETUP Interrupt */\r
+#define USBC_UESTA6_NAKOUTI (0x1u << 3) /**< \brief (USBC_UESTA6) NAKed OUT Interrupt */\r
+#define USBC_UESTA6_NAKINI (0x1u << 4) /**< \brief (USBC_UESTA6) NAKed IN Interrupt */\r
+#define USBC_UESTA6_STALLEDI (0x1u << 6) /**< \brief (USBC_UESTA6) STALLed Interrupt */\r
+#define USBC_UESTA6_DTSEQ_Pos 8\r
+#define USBC_UESTA6_DTSEQ_Msk (0x3u << USBC_UESTA6_DTSEQ_Pos) /**< \brief (USBC_UESTA6) Data Toggle Sequence */\r
+#define USBC_UESTA6_DTSEQ(value) ((USBC_UESTA6_DTSEQ_Msk & ((value) << USBC_UESTA6_DTSEQ_Pos)))\r
+#define USBC_UESTA6_RAMACERI (0x1u << 11) /**< \brief (USBC_UESTA6) Ram Access Error Interrupt */\r
+#define USBC_UESTA6_NBUSYBK_Pos 12\r
+#define USBC_UESTA6_NBUSYBK_Msk (0x3u << USBC_UESTA6_NBUSYBK_Pos) /**< \brief (USBC_UESTA6) Number Of Busy Banks */\r
+#define USBC_UESTA6_NBUSYBK(value) ((USBC_UESTA6_NBUSYBK_Msk & ((value) << USBC_UESTA6_NBUSYBK_Pos)))\r
+#define USBC_UESTA6_CURRBK_Pos 14\r
+#define USBC_UESTA6_CURRBK_Msk (0x3u << USBC_UESTA6_CURRBK_Pos) /**< \brief (USBC_UESTA6) Current Bank */\r
+#define USBC_UESTA6_CURRBK(value) ((USBC_UESTA6_CURRBK_Msk & ((value) << USBC_UESTA6_CURRBK_Pos)))\r
+#define USBC_UESTA6_CTRLDIR (0x1u << 17) /**< \brief (USBC_UESTA6) Control Direction */\r
+#define USBC_UESTA6_CTRLDIR_OUT (0x0u << 17) /**< \brief (USBC_UESTA6) */\r
+#define USBC_UESTA6_CTRLDIR_IN (0x1u << 17) /**< \brief (USBC_UESTA6) */\r
+/* -------- USBC_UESTA7 : (USBC Offset: 0x14C) Endpoint Status Register -------- */\r
+#define USBC_UESTA7_TXINI (0x1u << 0) /**< \brief (USBC_UESTA7) Transmitted IN Data Interrupt */\r
+#define USBC_UESTA7_RXOUTI (0x1u << 1) /**< \brief (USBC_UESTA7) Received OUT Data Interrupt */\r
+#define USBC_UESTA7_RXSTPI (0x1u << 2) /**< \brief (USBC_UESTA7) Received SETUP Interrupt */\r
+#define USBC_UESTA7_NAKOUTI (0x1u << 3) /**< \brief (USBC_UESTA7) NAKed OUT Interrupt */\r
+#define USBC_UESTA7_NAKINI (0x1u << 4) /**< \brief (USBC_UESTA7) NAKed IN Interrupt */\r
+#define USBC_UESTA7_STALLEDI (0x1u << 6) /**< \brief (USBC_UESTA7) STALLed Interrupt */\r
+#define USBC_UESTA7_DTSEQ_Pos 8\r
+#define USBC_UESTA7_DTSEQ_Msk (0x3u << USBC_UESTA7_DTSEQ_Pos) /**< \brief (USBC_UESTA7) Data Toggle Sequence */\r
+#define USBC_UESTA7_DTSEQ(value) ((USBC_UESTA7_DTSEQ_Msk & ((value) << USBC_UESTA7_DTSEQ_Pos)))\r
+#define USBC_UESTA7_RAMACERI (0x1u << 11) /**< \brief (USBC_UESTA7) Ram Access Error Interrupt */\r
+#define USBC_UESTA7_NBUSYBK_Pos 12\r
+#define USBC_UESTA7_NBUSYBK_Msk (0x3u << USBC_UESTA7_NBUSYBK_Pos) /**< \brief (USBC_UESTA7) Number Of Busy Banks */\r
+#define USBC_UESTA7_NBUSYBK(value) ((USBC_UESTA7_NBUSYBK_Msk & ((value) << USBC_UESTA7_NBUSYBK_Pos)))\r
+#define USBC_UESTA7_CURRBK_Pos 14\r
+#define USBC_UESTA7_CURRBK_Msk (0x3u << USBC_UESTA7_CURRBK_Pos) /**< \brief (USBC_UESTA7) Current Bank */\r
+#define USBC_UESTA7_CURRBK(value) ((USBC_UESTA7_CURRBK_Msk & ((value) << USBC_UESTA7_CURRBK_Pos)))\r
+#define USBC_UESTA7_CTRLDIR (0x1u << 17) /**< \brief (USBC_UESTA7) Control Direction */\r
+#define USBC_UESTA7_CTRLDIR_OUT (0x0u << 17) /**< \brief (USBC_UESTA7) */\r
+#define USBC_UESTA7_CTRLDIR_IN (0x1u << 17) /**< \brief (USBC_UESTA7) */\r
+/* -------- USBC_UESTA0CLR : (USBC Offset: 0x160) Endpoint Status Clear Register -------- */\r
+#define USBC_UESTA0CLR_TXINIC (0x1u << 0) /**< \brief (USBC_UESTA0CLR) TXINI Clear */\r
+#define USBC_UESTA0CLR_RXOUTIC (0x1u << 1) /**< \brief (USBC_UESTA0CLR) RXOUTI Clear */\r
+#define USBC_UESTA0CLR_RXSTPIC (0x1u << 2) /**< \brief (USBC_UESTA0CLR) RXSTPI Clear */\r
+#define USBC_UESTA0CLR_NAKOUTIC (0x1u << 3) /**< \brief (USBC_UESTA0CLR) NAKOUTI Clear */\r
+#define USBC_UESTA0CLR_NAKINIC (0x1u << 4) /**< \brief (USBC_UESTA0CLR) NAKINI Clear */\r
+#define USBC_UESTA0CLR_STALLEDIC (0x1u << 6) /**< \brief (USBC_UESTA0CLR) STALLEDI Clear */\r
+#define USBC_UESTA0CLR_RAMACERIC (0x1u << 11) /**< \brief (USBC_UESTA0CLR) RAMACERI Clear */\r
+/* -------- USBC_UESTA1CLR : (USBC Offset: 0x164) Endpoint Status Clear Register -------- */\r
+#define USBC_UESTA1CLR_TXINIC (0x1u << 0) /**< \brief (USBC_UESTA1CLR) TXINI Clear */\r
+#define USBC_UESTA1CLR_RXOUTIC (0x1u << 1) /**< \brief (USBC_UESTA1CLR) RXOUTI Clear */\r
+#define USBC_UESTA1CLR_RXSTPIC (0x1u << 2) /**< \brief (USBC_UESTA1CLR) RXSTPI Clear */\r
+#define USBC_UESTA1CLR_NAKOUTIC (0x1u << 3) /**< \brief (USBC_UESTA1CLR) NAKOUTI Clear */\r
+#define USBC_UESTA1CLR_NAKINIC (0x1u << 4) /**< \brief (USBC_UESTA1CLR) NAKINI Clear */\r
+#define USBC_UESTA1CLR_STALLEDIC (0x1u << 6) /**< \brief (USBC_UESTA1CLR) STALLEDI Clear */\r
+#define USBC_UESTA1CLR_RAMACERIC (0x1u << 11) /**< \brief (USBC_UESTA1CLR) RAMACERI Clear */\r
+/* -------- USBC_UESTA2CLR : (USBC Offset: 0x168) Endpoint Status Clear Register -------- */\r
+#define USBC_UESTA2CLR_TXINIC (0x1u << 0) /**< \brief (USBC_UESTA2CLR) TXINI Clear */\r
+#define USBC_UESTA2CLR_RXOUTIC (0x1u << 1) /**< \brief (USBC_UESTA2CLR) RXOUTI Clear */\r
+#define USBC_UESTA2CLR_RXSTPIC (0x1u << 2) /**< \brief (USBC_UESTA2CLR) RXSTPI Clear */\r
+#define USBC_UESTA2CLR_NAKOUTIC (0x1u << 3) /**< \brief (USBC_UESTA2CLR) NAKOUTI Clear */\r
+#define USBC_UESTA2CLR_NAKINIC (0x1u << 4) /**< \brief (USBC_UESTA2CLR) NAKINI Clear */\r
+#define USBC_UESTA2CLR_STALLEDIC (0x1u << 6) /**< \brief (USBC_UESTA2CLR) STALLEDI Clear */\r
+#define USBC_UESTA2CLR_RAMACERIC (0x1u << 11) /**< \brief (USBC_UESTA2CLR) RAMACERI Clear */\r
+/* -------- USBC_UESTA3CLR : (USBC Offset: 0x16C) Endpoint Status Clear Register -------- */\r
+#define USBC_UESTA3CLR_TXINIC (0x1u << 0) /**< \brief (USBC_UESTA3CLR) TXINI Clear */\r
+#define USBC_UESTA3CLR_RXOUTIC (0x1u << 1) /**< \brief (USBC_UESTA3CLR) RXOUTI Clear */\r
+#define USBC_UESTA3CLR_RXSTPIC (0x1u << 2) /**< \brief (USBC_UESTA3CLR) RXSTPI Clear */\r
+#define USBC_UESTA3CLR_NAKOUTIC (0x1u << 3) /**< \brief (USBC_UESTA3CLR) NAKOUTI Clear */\r
+#define USBC_UESTA3CLR_NAKINIC (0x1u << 4) /**< \brief (USBC_UESTA3CLR) NAKINI Clear */\r
+#define USBC_UESTA3CLR_STALLEDIC (0x1u << 6) /**< \brief (USBC_UESTA3CLR) STALLEDI Clear */\r
+#define USBC_UESTA3CLR_RAMACERIC (0x1u << 11) /**< \brief (USBC_UESTA3CLR) RAMACERI Clear */\r
+/* -------- USBC_UESTA4CLR : (USBC Offset: 0x170) Endpoint Status Clear Register -------- */\r
+#define USBC_UESTA4CLR_TXINIC (0x1u << 0) /**< \brief (USBC_UESTA4CLR) TXINI Clear */\r
+#define USBC_UESTA4CLR_RXOUTIC (0x1u << 1) /**< \brief (USBC_UESTA4CLR) RXOUTI Clear */\r
+#define USBC_UESTA4CLR_RXSTPIC (0x1u << 2) /**< \brief (USBC_UESTA4CLR) RXSTPI Clear */\r
+#define USBC_UESTA4CLR_NAKOUTIC (0x1u << 3) /**< \brief (USBC_UESTA4CLR) NAKOUTI Clear */\r
+#define USBC_UESTA4CLR_NAKINIC (0x1u << 4) /**< \brief (USBC_UESTA4CLR) NAKINI Clear */\r
+#define USBC_UESTA4CLR_STALLEDIC (0x1u << 6) /**< \brief (USBC_UESTA4CLR) STALLEDI Clear */\r
+#define USBC_UESTA4CLR_RAMACERIC (0x1u << 11) /**< \brief (USBC_UESTA4CLR) RAMACERI Clear */\r
+/* -------- USBC_UESTA5CLR : (USBC Offset: 0x174) Endpoint Status Clear Register -------- */\r
+#define USBC_UESTA5CLR_TXINIC (0x1u << 0) /**< \brief (USBC_UESTA5CLR) TXINI Clear */\r
+#define USBC_UESTA5CLR_RXOUTIC (0x1u << 1) /**< \brief (USBC_UESTA5CLR) RXOUTI Clear */\r
+#define USBC_UESTA5CLR_RXSTPIC (0x1u << 2) /**< \brief (USBC_UESTA5CLR) RXSTPI Clear */\r
+#define USBC_UESTA5CLR_NAKOUTIC (0x1u << 3) /**< \brief (USBC_UESTA5CLR) NAKOUTI Clear */\r
+#define USBC_UESTA5CLR_NAKINIC (0x1u << 4) /**< \brief (USBC_UESTA5CLR) NAKINI Clear */\r
+#define USBC_UESTA5CLR_STALLEDIC (0x1u << 6) /**< \brief (USBC_UESTA5CLR) STALLEDI Clear */\r
+#define USBC_UESTA5CLR_RAMACERIC (0x1u << 11) /**< \brief (USBC_UESTA5CLR) RAMACERI Clear */\r
+/* -------- USBC_UESTA6CLR : (USBC Offset: 0x178) Endpoint Status Clear Register -------- */\r
+#define USBC_UESTA6CLR_TXINIC (0x1u << 0) /**< \brief (USBC_UESTA6CLR) TXINI Clear */\r
+#define USBC_UESTA6CLR_RXOUTIC (0x1u << 1) /**< \brief (USBC_UESTA6CLR) RXOUTI Clear */\r
+#define USBC_UESTA6CLR_RXSTPIC (0x1u << 2) /**< \brief (USBC_UESTA6CLR) RXSTPI Clear */\r
+#define USBC_UESTA6CLR_NAKOUTIC (0x1u << 3) /**< \brief (USBC_UESTA6CLR) NAKOUTI Clear */\r
+#define USBC_UESTA6CLR_NAKINIC (0x1u << 4) /**< \brief (USBC_UESTA6CLR) NAKINI Clear */\r
+#define USBC_UESTA6CLR_STALLEDIC (0x1u << 6) /**< \brief (USBC_UESTA6CLR) STALLEDI Clear */\r
+#define USBC_UESTA6CLR_RAMACERIC (0x1u << 11) /**< \brief (USBC_UESTA6CLR) RAMACERI Clear */\r
+/* -------- USBC_UESTA7CLR : (USBC Offset: 0x17C) Endpoint Status Clear Register -------- */\r
+#define USBC_UESTA7CLR_TXINIC (0x1u << 0) /**< \brief (USBC_UESTA7CLR) TXINI Clear */\r
+#define USBC_UESTA7CLR_RXOUTIC (0x1u << 1) /**< \brief (USBC_UESTA7CLR) RXOUTI Clear */\r
+#define USBC_UESTA7CLR_RXSTPIC (0x1u << 2) /**< \brief (USBC_UESTA7CLR) RXSTPI Clear */\r
+#define USBC_UESTA7CLR_NAKOUTIC (0x1u << 3) /**< \brief (USBC_UESTA7CLR) NAKOUTI Clear */\r
+#define USBC_UESTA7CLR_NAKINIC (0x1u << 4) /**< \brief (USBC_UESTA7CLR) NAKINI Clear */\r
+#define USBC_UESTA7CLR_STALLEDIC (0x1u << 6) /**< \brief (USBC_UESTA7CLR) STALLEDI Clear */\r
+#define USBC_UESTA7CLR_RAMACERIC (0x1u << 11) /**< \brief (USBC_UESTA7CLR) RAMACERI Clear */\r
+/* -------- USBC_UESTA0SET : (USBC Offset: 0x190) Endpoint Status Set Register -------- */\r
+#define USBC_UESTA0SET_TXINIS (0x1u << 0) /**< \brief (USBC_UESTA0SET) TXINI Set */\r
+#define USBC_UESTA0SET_RXOUTIS (0x1u << 1) /**< \brief (USBC_UESTA0SET) RXOUTI Set */\r
+#define USBC_UESTA0SET_RXSTPIS (0x1u << 2) /**< \brief (USBC_UESTA0SET) RXSTPI Set */\r
+#define USBC_UESTA0SET_NAKOUTIS (0x1u << 3) /**< \brief (USBC_UESTA0SET) NAKOUTI Set */\r
+#define USBC_UESTA0SET_NAKINIS (0x1u << 4) /**< \brief (USBC_UESTA0SET) NAKINI Set */\r
+#define USBC_UESTA0SET_STALLEDIS (0x1u << 6) /**< \brief (USBC_UESTA0SET) STALLEDI Set */\r
+#define USBC_UESTA0SET_RAMACERIS (0x1u << 11) /**< \brief (USBC_UESTA0SET) RAMACERI Set */\r
+#define USBC_UESTA0SET_NBUSYBKS (0x1u << 12) /**< \brief (USBC_UESTA0SET) NBUSYBK Set */\r
+/* -------- USBC_UESTA1SET : (USBC Offset: 0x194) Endpoint Status Set Register -------- */\r
+#define USBC_UESTA1SET_TXINIS (0x1u << 0) /**< \brief (USBC_UESTA1SET) TXINI Set */\r
+#define USBC_UESTA1SET_RXOUTIS (0x1u << 1) /**< \brief (USBC_UESTA1SET) RXOUTI Set */\r
+#define USBC_UESTA1SET_RXSTPIS (0x1u << 2) /**< \brief (USBC_UESTA1SET) RXSTPI Set */\r
+#define USBC_UESTA1SET_NAKOUTIS (0x1u << 3) /**< \brief (USBC_UESTA1SET) NAKOUTI Set */\r
+#define USBC_UESTA1SET_NAKINIS (0x1u << 4) /**< \brief (USBC_UESTA1SET) NAKINI Set */\r
+#define USBC_UESTA1SET_STALLEDIS (0x1u << 6) /**< \brief (USBC_UESTA1SET) STALLEDI Set */\r
+#define USBC_UESTA1SET_RAMACERIS (0x1u << 11) /**< \brief (USBC_UESTA1SET) RAMACERI Set */\r
+#define USBC_UESTA1SET_NBUSYBKS (0x1u << 12) /**< \brief (USBC_UESTA1SET) NBUSYBK Set */\r
+/* -------- USBC_UESTA2SET : (USBC Offset: 0x198) Endpoint Status Set Register -------- */\r
+#define USBC_UESTA2SET_TXINIS (0x1u << 0) /**< \brief (USBC_UESTA2SET) TXINI Set */\r
+#define USBC_UESTA2SET_RXOUTIS (0x1u << 1) /**< \brief (USBC_UESTA2SET) RXOUTI Set */\r
+#define USBC_UESTA2SET_RXSTPIS (0x1u << 2) /**< \brief (USBC_UESTA2SET) RXSTPI Set */\r
+#define USBC_UESTA2SET_NAKOUTIS (0x1u << 3) /**< \brief (USBC_UESTA2SET) NAKOUTI Set */\r
+#define USBC_UESTA2SET_NAKINIS (0x1u << 4) /**< \brief (USBC_UESTA2SET) NAKINI Set */\r
+#define USBC_UESTA2SET_STALLEDIS (0x1u << 6) /**< \brief (USBC_UESTA2SET) STALLEDI Set */\r
+#define USBC_UESTA2SET_RAMACERIS (0x1u << 11) /**< \brief (USBC_UESTA2SET) RAMACERI Set */\r
+#define USBC_UESTA2SET_NBUSYBKS (0x1u << 12) /**< \brief (USBC_UESTA2SET) NBUSYBK Set */\r
+/* -------- USBC_UESTA3SET : (USBC Offset: 0x19C) Endpoint Status Set Register -------- */\r
+#define USBC_UESTA3SET_TXINIS (0x1u << 0) /**< \brief (USBC_UESTA3SET) TXINI Set */\r
+#define USBC_UESTA3SET_RXOUTIS (0x1u << 1) /**< \brief (USBC_UESTA3SET) RXOUTI Set */\r
+#define USBC_UESTA3SET_RXSTPIS (0x1u << 2) /**< \brief (USBC_UESTA3SET) RXSTPI Set */\r
+#define USBC_UESTA3SET_NAKOUTIS (0x1u << 3) /**< \brief (USBC_UESTA3SET) NAKOUTI Set */\r
+#define USBC_UESTA3SET_NAKINIS (0x1u << 4) /**< \brief (USBC_UESTA3SET) NAKINI Set */\r
+#define USBC_UESTA3SET_STALLEDIS (0x1u << 6) /**< \brief (USBC_UESTA3SET) STALLEDI Set */\r
+#define USBC_UESTA3SET_RAMACERIS (0x1u << 11) /**< \brief (USBC_UESTA3SET) RAMACERI Set */\r
+#define USBC_UESTA3SET_NBUSYBKS (0x1u << 12) /**< \brief (USBC_UESTA3SET) NBUSYBK Set */\r
+/* -------- USBC_UESTA4SET : (USBC Offset: 0x1A0) Endpoint Status Set Register -------- */\r
+#define USBC_UESTA4SET_TXINIS (0x1u << 0) /**< \brief (USBC_UESTA4SET) TXINI Set */\r
+#define USBC_UESTA4SET_RXOUTIS (0x1u << 1) /**< \brief (USBC_UESTA4SET) RXOUTI Set */\r
+#define USBC_UESTA4SET_RXSTPIS (0x1u << 2) /**< \brief (USBC_UESTA4SET) RXSTPI Set */\r
+#define USBC_UESTA4SET_NAKOUTIS (0x1u << 3) /**< \brief (USBC_UESTA4SET) NAKOUTI Set */\r
+#define USBC_UESTA4SET_NAKINIS (0x1u << 4) /**< \brief (USBC_UESTA4SET) NAKINI Set */\r
+#define USBC_UESTA4SET_STALLEDIS (0x1u << 6) /**< \brief (USBC_UESTA4SET) STALLEDI Set */\r
+#define USBC_UESTA4SET_RAMACERIS (0x1u << 11) /**< \brief (USBC_UESTA4SET) RAMACERI Set */\r
+#define USBC_UESTA4SET_NBUSYBKS (0x1u << 12) /**< \brief (USBC_UESTA4SET) NBUSYBK Set */\r
+/* -------- USBC_UESTA5SET : (USBC Offset: 0x1A4) Endpoint Status Set Register -------- */\r
+#define USBC_UESTA5SET_TXINIS (0x1u << 0) /**< \brief (USBC_UESTA5SET) TXINI Set */\r
+#define USBC_UESTA5SET_RXOUTIS (0x1u << 1) /**< \brief (USBC_UESTA5SET) RXOUTI Set */\r
+#define USBC_UESTA5SET_RXSTPIS (0x1u << 2) /**< \brief (USBC_UESTA5SET) RXSTPI Set */\r
+#define USBC_UESTA5SET_NAKOUTIS (0x1u << 3) /**< \brief (USBC_UESTA5SET) NAKOUTI Set */\r
+#define USBC_UESTA5SET_NAKINIS (0x1u << 4) /**< \brief (USBC_UESTA5SET) NAKINI Set */\r
+#define USBC_UESTA5SET_STALLEDIS (0x1u << 6) /**< \brief (USBC_UESTA5SET) STALLEDI Set */\r
+#define USBC_UESTA5SET_RAMACERIS (0x1u << 11) /**< \brief (USBC_UESTA5SET) RAMACERI Set */\r
+#define USBC_UESTA5SET_NBUSYBKS (0x1u << 12) /**< \brief (USBC_UESTA5SET) NBUSYBK Set */\r
+/* -------- USBC_UESTA6SET : (USBC Offset: 0x1A8) Endpoint Status Set Register -------- */\r
+#define USBC_UESTA6SET_TXINIS (0x1u << 0) /**< \brief (USBC_UESTA6SET) TXINI Set */\r
+#define USBC_UESTA6SET_RXOUTIS (0x1u << 1) /**< \brief (USBC_UESTA6SET) RXOUTI Set */\r
+#define USBC_UESTA6SET_RXSTPIS (0x1u << 2) /**< \brief (USBC_UESTA6SET) RXSTPI Set */\r
+#define USBC_UESTA6SET_NAKOUTIS (0x1u << 3) /**< \brief (USBC_UESTA6SET) NAKOUTI Set */\r
+#define USBC_UESTA6SET_NAKINIS (0x1u << 4) /**< \brief (USBC_UESTA6SET) NAKINI Set */\r
+#define USBC_UESTA6SET_STALLEDIS (0x1u << 6) /**< \brief (USBC_UESTA6SET) STALLEDI Set */\r
+#define USBC_UESTA6SET_RAMACERIS (0x1u << 11) /**< \brief (USBC_UESTA6SET) RAMACERI Set */\r
+#define USBC_UESTA6SET_NBUSYBKS (0x1u << 12) /**< \brief (USBC_UESTA6SET) NBUSYBK Set */\r
+/* -------- USBC_UESTA7SET : (USBC Offset: 0x1AC) Endpoint Status Set Register -------- */\r
+#define USBC_UESTA7SET_TXINIS (0x1u << 0) /**< \brief (USBC_UESTA7SET) TXINI Set */\r
+#define USBC_UESTA7SET_RXOUTIS (0x1u << 1) /**< \brief (USBC_UESTA7SET) RXOUTI Set */\r
+#define USBC_UESTA7SET_RXSTPIS (0x1u << 2) /**< \brief (USBC_UESTA7SET) RXSTPI Set */\r
+#define USBC_UESTA7SET_NAKOUTIS (0x1u << 3) /**< \brief (USBC_UESTA7SET) NAKOUTI Set */\r
+#define USBC_UESTA7SET_NAKINIS (0x1u << 4) /**< \brief (USBC_UESTA7SET) NAKINI Set */\r
+#define USBC_UESTA7SET_STALLEDIS (0x1u << 6) /**< \brief (USBC_UESTA7SET) STALLEDI Set */\r
+#define USBC_UESTA7SET_RAMACERIS (0x1u << 11) /**< \brief (USBC_UESTA7SET) RAMACERI Set */\r
+#define USBC_UESTA7SET_NBUSYBKS (0x1u << 12) /**< \brief (USBC_UESTA7SET) NBUSYBK Set */\r
+/* -------- USBC_UECON0 : (USBC Offset: 0x1C0) Endpoint Control Register -------- */\r
+#define USBC_UECON0_TXINE (0x1u << 0) /**< \brief (USBC_UECON0) TXIN Interrupt Enable */\r
+#define USBC_UECON0_RXOUTE (0x1u << 1) /**< \brief (USBC_UECON0) RXOUT Interrupt Enable */\r
+#define USBC_UECON0_RXSTPE (0x1u << 2) /**< \brief (USBC_UECON0) RXSTP Interrupt Enable */\r
+#define USBC_UECON0_NAKOUTE (0x1u << 3) /**< \brief (USBC_UECON0) NAKOUT Interrupt Enable */\r
+#define USBC_UECON0_NAKINE (0x1u << 4) /**< \brief (USBC_UECON0) NAKIN Interrupt Enable */\r
+#define USBC_UECON0_STALLEDE (0x1u << 6) /**< \brief (USBC_UECON0) STALLED Interrupt Enable */\r
+#define USBC_UECON0_NREPLY (0x1u << 8) /**< \brief (USBC_UECON0) No Reply */\r
+#define USBC_UECON0_RAMACERE (0x1u << 11) /**< \brief (USBC_UECON0) RAMACER Interrupt Enable */\r
+#define USBC_UECON0_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UECON0) Number of Busy Banks Interrupt Enable */\r
+#define USBC_UECON0_KILLBK (0x1u << 13) /**< \brief (USBC_UECON0) Kill IN Bank */\r
+#define USBC_UECON0_FIFOCON (0x1u << 14) /**< \brief (USBC_UECON0) FIFO Control */\r
+#define USBC_UECON0_NYETDIS (0x1u << 17) /**< \brief (USBC_UECON0) NYET token disable */\r
+#define USBC_UECON0_RSTDT (0x1u << 18) /**< \brief (USBC_UECON0) Reset Data Toggle */\r
+#define USBC_UECON0_STALLRQ (0x1u << 19) /**< \brief (USBC_UECON0) STALL Request */\r
+#define USBC_UECON0_BUSY0 (0x1u << 24) /**< \brief (USBC_UECON0) Busy Bank1 Enable */\r
+#define USBC_UECON0_BUSY1 (0x1u << 25) /**< \brief (USBC_UECON0) Busy Bank0 Enable */\r
+/* -------- USBC_UECON1 : (USBC Offset: 0x1C4) Endpoint Control Register -------- */\r
+#define USBC_UECON1_TXINE (0x1u << 0) /**< \brief (USBC_UECON1) TXIN Interrupt Enable */\r
+#define USBC_UECON1_RXOUTE (0x1u << 1) /**< \brief (USBC_UECON1) RXOUT Interrupt Enable */\r
+#define USBC_UECON1_RXSTPE (0x1u << 2) /**< \brief (USBC_UECON1) RXSTP Interrupt Enable */\r
+#define USBC_UECON1_NAKOUTE (0x1u << 3) /**< \brief (USBC_UECON1) NAKOUT Interrupt Enable */\r
+#define USBC_UECON1_NAKINE (0x1u << 4) /**< \brief (USBC_UECON1) NAKIN Interrupt Enable */\r
+#define USBC_UECON1_STALLEDE (0x1u << 6) /**< \brief (USBC_UECON1) STALLED Interrupt Enable */\r
+#define USBC_UECON1_NREPLY (0x1u << 8) /**< \brief (USBC_UECON1) No Reply */\r
+#define USBC_UECON1_RAMACERE (0x1u << 11) /**< \brief (USBC_UECON1) RAMACER Interrupt Enable */\r
+#define USBC_UECON1_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UECON1) Number of Busy Banks Interrupt Enable */\r
+#define USBC_UECON1_KILLBK (0x1u << 13) /**< \brief (USBC_UECON1) Kill IN Bank */\r
+#define USBC_UECON1_FIFOCON (0x1u << 14) /**< \brief (USBC_UECON1) FIFO Control */\r
+#define USBC_UECON1_NYETDIS (0x1u << 17) /**< \brief (USBC_UECON1) NYET Token Enable */\r
+#define USBC_UECON1_RSTDT (0x1u << 18) /**< \brief (USBC_UECON1) Reset Data Toggle */\r
+#define USBC_UECON1_STALLRQ (0x1u << 19) /**< \brief (USBC_UECON1) STALL Request */\r
+#define USBC_UECON1_BUSY0 (0x1u << 24) /**< \brief (USBC_UECON1) Busy Bank1 Enable */\r
+#define USBC_UECON1_BUSY1 (0x1u << 25) /**< \brief (USBC_UECON1) Busy Bank0 Enable */\r
+/* -------- USBC_UECON2 : (USBC Offset: 0x1C8) Endpoint Control Register -------- */\r
+#define USBC_UECON2_TXINE (0x1u << 0) /**< \brief (USBC_UECON2) TXIN Interrupt Enable */\r
+#define USBC_UECON2_RXOUTE (0x1u << 1) /**< \brief (USBC_UECON2) RXOUT Interrupt Enable */\r
+#define USBC_UECON2_RXSTPE (0x1u << 2) /**< \brief (USBC_UECON2) RXSTP Interrupt Enable */\r
+#define USBC_UECON2_NAKOUTE (0x1u << 3) /**< \brief (USBC_UECON2) NAKOUT Interrupt Enable */\r
+#define USBC_UECON2_NAKINE (0x1u << 4) /**< \brief (USBC_UECON2) NAKIN Interrupt Enable */\r
+#define USBC_UECON2_STALLEDE (0x1u << 6) /**< \brief (USBC_UECON2) STALLED Interrupt Enable */\r
+#define USBC_UECON2_NREPLY (0x1u << 8) /**< \brief (USBC_UECON2) No Reply */\r
+#define USBC_UECON2_RAMACERE (0x1u << 11) /**< \brief (USBC_UECON2) RAMACER Interrupt Enable */\r
+#define USBC_UECON2_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UECON2) Number of Busy Banks Interrupt Enable */\r
+#define USBC_UECON2_KILLBK (0x1u << 13) /**< \brief (USBC_UECON2) Kill IN Bank */\r
+#define USBC_UECON2_FIFOCON (0x1u << 14) /**< \brief (USBC_UECON2) FIFO Control */\r
+#define USBC_UECON2_NYETDIS (0x1u << 17) /**< \brief (USBC_UECON2) NYET Token Enable */\r
+#define USBC_UECON2_RSTDT (0x1u << 18) /**< \brief (USBC_UECON2) Reset Data Toggle */\r
+#define USBC_UECON2_STALLRQ (0x1u << 19) /**< \brief (USBC_UECON2) STALL Request */\r
+#define USBC_UECON2_BUSY0 (0x1u << 24) /**< \brief (USBC_UECON2) Busy Bank1 Enable */\r
+#define USBC_UECON2_BUSY1 (0x1u << 25) /**< \brief (USBC_UECON2) Busy Bank0 Enable */\r
+/* -------- USBC_UECON3 : (USBC Offset: 0x1CC) Endpoint Control Register -------- */\r
+#define USBC_UECON3_TXINE (0x1u << 0) /**< \brief (USBC_UECON3) TXIN Interrupt Enable */\r
+#define USBC_UECON3_RXOUTE (0x1u << 1) /**< \brief (USBC_UECON3) RXOUT Interrupt Enable */\r
+#define USBC_UECON3_RXSTPE (0x1u << 2) /**< \brief (USBC_UECON3) RXSTP Interrupt Enable */\r
+#define USBC_UECON3_NAKOUTE (0x1u << 3) /**< \brief (USBC_UECON3) NAKOUT Interrupt Enable */\r
+#define USBC_UECON3_NAKINE (0x1u << 4) /**< \brief (USBC_UECON3) NAKIN Interrupt Enable */\r
+#define USBC_UECON3_STALLEDE (0x1u << 6) /**< \brief (USBC_UECON3) STALLED Interrupt Enable */\r
+#define USBC_UECON3_NREPLY (0x1u << 8) /**< \brief (USBC_UECON3) No Reply */\r
+#define USBC_UECON3_RAMACERE (0x1u << 11) /**< \brief (USBC_UECON3) RAMACER Interrupt Enable */\r
+#define USBC_UECON3_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UECON3) Number of Busy Banks Interrupt Enable */\r
+#define USBC_UECON3_KILLBK (0x1u << 13) /**< \brief (USBC_UECON3) Kill IN Bank */\r
+#define USBC_UECON3_FIFOCON (0x1u << 14) /**< \brief (USBC_UECON3) FIFO Control */\r
+#define USBC_UECON3_NYETDIS (0x1u << 17) /**< \brief (USBC_UECON3) NYET Token Enable */\r
+#define USBC_UECON3_RSTDT (0x1u << 18) /**< \brief (USBC_UECON3) Reset Data Toggle */\r
+#define USBC_UECON3_STALLRQ (0x1u << 19) /**< \brief (USBC_UECON3) STALL Request */\r
+#define USBC_UECON3_BUSY0 (0x1u << 24) /**< \brief (USBC_UECON3) Busy Bank1 Enable */\r
+#define USBC_UECON3_BUSY1 (0x1u << 25) /**< \brief (USBC_UECON3) Busy Bank0 Enable */\r
+/* -------- USBC_UECON4 : (USBC Offset: 0x1D0) Endpoint Control Register -------- */\r
+#define USBC_UECON4_TXINE (0x1u << 0) /**< \brief (USBC_UECON4) TXIN Interrupt Enable */\r
+#define USBC_UECON4_RXOUTE (0x1u << 1) /**< \brief (USBC_UECON4) RXOUT Interrupt Enable */\r
+#define USBC_UECON4_RXSTPE (0x1u << 2) /**< \brief (USBC_UECON4) RXSTP Interrupt Enable */\r
+#define USBC_UECON4_NAKOUTE (0x1u << 3) /**< \brief (USBC_UECON4) NAKOUT Interrupt Enable */\r
+#define USBC_UECON4_NAKINE (0x1u << 4) /**< \brief (USBC_UECON4) NAKIN Interrupt Enable */\r
+#define USBC_UECON4_STALLEDE (0x1u << 6) /**< \brief (USBC_UECON4) STALLED Interrupt Enable */\r
+#define USBC_UECON4_NREPLY (0x1u << 8) /**< \brief (USBC_UECON4) No Reply */\r
+#define USBC_UECON4_RAMACERE (0x1u << 11) /**< \brief (USBC_UECON4) RAMACER Interrupt Enable */\r
+#define USBC_UECON4_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UECON4) Number of Busy Banks Interrupt Enable */\r
+#define USBC_UECON4_KILLBK (0x1u << 13) /**< \brief (USBC_UECON4) Kill IN Bank */\r
+#define USBC_UECON4_FIFOCON (0x1u << 14) /**< \brief (USBC_UECON4) FIFO Control */\r
+#define USBC_UECON4_NYETDIS (0x1u << 17) /**< \brief (USBC_UECON4) NYET Token Enable */\r
+#define USBC_UECON4_RSTDT (0x1u << 18) /**< \brief (USBC_UECON4) Reset Data Toggle */\r
+#define USBC_UECON4_STALLRQ (0x1u << 19) /**< \brief (USBC_UECON4) STALL Request */\r
+#define USBC_UECON4_BUSY0 (0x1u << 24) /**< \brief (USBC_UECON4) Busy Bank1 Enable */\r
+#define USBC_UECON4_BUSY1 (0x1u << 25) /**< \brief (USBC_UECON4) Busy Bank0 Enable */\r
+/* -------- USBC_UECON5 : (USBC Offset: 0x1D4) Endpoint Control Register -------- */\r
+#define USBC_UECON5_TXINE (0x1u << 0) /**< \brief (USBC_UECON5) TXIN Interrupt Enable */\r
+#define USBC_UECON5_RXOUTE (0x1u << 1) /**< \brief (USBC_UECON5) RXOUT Interrupt Enable */\r
+#define USBC_UECON5_RXSTPE (0x1u << 2) /**< \brief (USBC_UECON5) RXSTP Interrupt Enable */\r
+#define USBC_UECON5_NAKOUTE (0x1u << 3) /**< \brief (USBC_UECON5) NAKOUT Interrupt Enable */\r
+#define USBC_UECON5_NAKINE (0x1u << 4) /**< \brief (USBC_UECON5) NAKIN Interrupt Enable */\r
+#define USBC_UECON5_STALLEDE (0x1u << 6) /**< \brief (USBC_UECON5) STALLED Interrupt Enable */\r
+#define USBC_UECON5_NREPLY (0x1u << 8) /**< \brief (USBC_UECON5) No Reply */\r
+#define USBC_UECON5_RAMACERE (0x1u << 11) /**< \brief (USBC_UECON5) RAMACER Interrupt Enable */\r
+#define USBC_UECON5_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UECON5) Number of Busy Banks Interrupt Enable */\r
+#define USBC_UECON5_KILLBK (0x1u << 13) /**< \brief (USBC_UECON5) Kill IN Bank */\r
+#define USBC_UECON5_FIFOCON (0x1u << 14) /**< \brief (USBC_UECON5) FIFO Control */\r
+#define USBC_UECON5_NYETDIS (0x1u << 17) /**< \brief (USBC_UECON5) NYET Token Enable */\r
+#define USBC_UECON5_RSTDT (0x1u << 18) /**< \brief (USBC_UECON5) Reset Data Toggle */\r
+#define USBC_UECON5_STALLRQ (0x1u << 19) /**< \brief (USBC_UECON5) STALL Request */\r
+#define USBC_UECON5_BUSY0 (0x1u << 24) /**< \brief (USBC_UECON5) Busy Bank1 Enable */\r
+#define USBC_UECON5_BUSY1 (0x1u << 25) /**< \brief (USBC_UECON5) Busy Bank0 Enable */\r
+/* -------- USBC_UECON6 : (USBC Offset: 0x1D8) Endpoint Control Register -------- */\r
+#define USBC_UECON6_TXINE (0x1u << 0) /**< \brief (USBC_UECON6) TXIN Interrupt Enable */\r
+#define USBC_UECON6_RXOUTE (0x1u << 1) /**< \brief (USBC_UECON6) RXOUT Interrupt Enable */\r
+#define USBC_UECON6_RXSTPE (0x1u << 2) /**< \brief (USBC_UECON6) RXSTP Interrupt Enable */\r
+#define USBC_UECON6_NAKOUTE (0x1u << 3) /**< \brief (USBC_UECON6) NAKOUT Interrupt Enable */\r
+#define USBC_UECON6_NAKINE (0x1u << 4) /**< \brief (USBC_UECON6) NAKIN Interrupt Enable */\r
+#define USBC_UECON6_STALLEDE (0x1u << 6) /**< \brief (USBC_UECON6) STALLED Interrupt Enable */\r
+#define USBC_UECON6_NREPLY (0x1u << 8) /**< \brief (USBC_UECON6) No Reply */\r
+#define USBC_UECON6_RAMACERE (0x1u << 11) /**< \brief (USBC_UECON6) RAMACER Interrupt Enable */\r
+#define USBC_UECON6_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UECON6) Number of Busy Banks Interrupt Enable */\r
+#define USBC_UECON6_KILLBK (0x1u << 13) /**< \brief (USBC_UECON6) Kill IN Bank */\r
+#define USBC_UECON6_FIFOCON (0x1u << 14) /**< \brief (USBC_UECON6) FIFO Control */\r
+#define USBC_UECON6_NYETDIS (0x1u << 17) /**< \brief (USBC_UECON6) NYET Token Enable */\r
+#define USBC_UECON6_RSTDT (0x1u << 18) /**< \brief (USBC_UECON6) Reset Data Toggle */\r
+#define USBC_UECON6_STALLRQ (0x1u << 19) /**< \brief (USBC_UECON6) STALL Request */\r
+#define USBC_UECON6_BUSY0 (0x1u << 24) /**< \brief (USBC_UECON6) Busy Bank1 Enable */\r
+#define USBC_UECON6_BUSY1 (0x1u << 25) /**< \brief (USBC_UECON6) Busy Bank0 Enable */\r
+/* -------- USBC_UECON7 : (USBC Offset: 0x1DC) Endpoint Control Register -------- */\r
+#define USBC_UECON7_TXINE (0x1u << 0) /**< \brief (USBC_UECON7) TXIN Interrupt Enable */\r
+#define USBC_UECON7_RXOUTE (0x1u << 1) /**< \brief (USBC_UECON7) RXOUT Interrupt Enable */\r
+#define USBC_UECON7_RXSTPE (0x1u << 2) /**< \brief (USBC_UECON7) RXSTP Interrupt Enable */\r
+#define USBC_UECON7_NAKOUTE (0x1u << 3) /**< \brief (USBC_UECON7) NAKOUT Interrupt Enable */\r
+#define USBC_UECON7_NAKINE (0x1u << 4) /**< \brief (USBC_UECON7) NAKIN Interrupt Enable */\r
+#define USBC_UECON7_STALLEDE (0x1u << 6) /**< \brief (USBC_UECON7) STALLED Interrupt Enable */\r
+#define USBC_UECON7_NREPLY (0x1u << 8) /**< \brief (USBC_UECON7) No Reply */\r
+#define USBC_UECON7_RAMACERE (0x1u << 11) /**< \brief (USBC_UECON7) RAMACER Interrupt Enable */\r
+#define USBC_UECON7_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UECON7) Number of Busy Banks Interrupt Enable */\r
+#define USBC_UECON7_KILLBK (0x1u << 13) /**< \brief (USBC_UECON7) Kill IN Bank */\r
+#define USBC_UECON7_FIFOCON (0x1u << 14) /**< \brief (USBC_UECON7) FIFO Control */\r
+#define USBC_UECON7_NYETDIS (0x1u << 17) /**< \brief (USBC_UECON7) NYET Token Enable */\r
+#define USBC_UECON7_RSTDT (0x1u << 18) /**< \brief (USBC_UECON7) Reset Data Toggle */\r
+#define USBC_UECON7_STALLRQ (0x1u << 19) /**< \brief (USBC_UECON7) STALL Request */\r
+#define USBC_UECON7_BUSY0 (0x1u << 24) /**< \brief (USBC_UECON7) Busy Bank1 Enable */\r
+#define USBC_UECON7_BUSY1 (0x1u << 25) /**< \brief (USBC_UECON7) Busy Bank0 Enable */\r
+/* -------- USBC_UECON0SET : (USBC Offset: 0x1F0) Endpoint Control Set Register -------- */\r
+#define USBC_UECON0SET_TXINES (0x1u << 0) /**< \brief (USBC_UECON0SET) TXINE Set */\r
+#define USBC_UECON0SET_RXOUTES (0x1u << 1) /**< \brief (USBC_UECON0SET) RXOUTE Set */\r
+#define USBC_UECON0SET_RXSTPES (0x1u << 2) /**< \brief (USBC_UECON0SET) RXSTPE Set */\r
+#define USBC_UECON0SET_NAKOUTES (0x1u << 3) /**< \brief (USBC_UECON0SET) NAKOUTE Set */\r
+#define USBC_UECON0SET_NAKINES (0x1u << 4) /**< \brief (USBC_UECON0SET) NAKINE Set */\r
+#define USBC_UECON0SET_STALLEDES (0x1u << 6) /**< \brief (USBC_UECON0SET) STALLEDE Set */\r
+#define USBC_UECON0SET_NREPLYS (0x1u << 8) /**< \brief (USBC_UECON0SET) NREPLY Set */\r
+#define USBC_UECON0SET_RAMACERES (0x1u << 11) /**< \brief (USBC_UECON0SET) RAMACERE Set */\r
+#define USBC_UECON0SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UECON0SET) NBUSYBKE Set */\r
+#define USBC_UECON0SET_KILLBKS (0x1u << 13) /**< \brief (USBC_UECON0SET) KILLBK Set */\r
+#define USBC_UECON0SET_NYETDISS (0x1u << 17) /**< \brief (USBC_UECON0SET) NYETDIS Set */\r
+#define USBC_UECON0SET_RSTDTS (0x1u << 18) /**< \brief (USBC_UECON0SET) RSTDT Set */\r
+#define USBC_UECON0SET_STALLRQS (0x1u << 19) /**< \brief (USBC_UECON0SET) STALLRQ Set */\r
+#define USBC_UECON0SET_BUSY0S (0x1u << 24) /**< \brief (USBC_UECON0SET) BUSY0 Set */\r
+#define USBC_UECON0SET_BUSY1S (0x1u << 25) /**< \brief (USBC_UECON0SET) BUSY1 Set */\r
+/* -------- USBC_UECON1SET : (USBC Offset: 0x1F4) Endpoint Control Set Register -------- */\r
+#define USBC_UECON1SET_TXINES (0x1u << 0) /**< \brief (USBC_UECON1SET) TXINE Set */\r
+#define USBC_UECON1SET_RXOUTES (0x1u << 1) /**< \brief (USBC_UECON1SET) RXOUTE Set */\r
+#define USBC_UECON1SET_RXSTPES (0x1u << 2) /**< \brief (USBC_UECON1SET) RXSTPE Set */\r
+#define USBC_UECON1SET_NAKOUTES (0x1u << 3) /**< \brief (USBC_UECON1SET) NAKOUTE Set */\r
+#define USBC_UECON1SET_NAKINES (0x1u << 4) /**< \brief (USBC_UECON1SET) NAKINE Set */\r
+#define USBC_UECON1SET_STALLEDES (0x1u << 6) /**< \brief (USBC_UECON1SET) STALLEDE Set */\r
+#define USBC_UECON1SET_NREPLYS (0x1u << 8) /**< \brief (USBC_UECON1SET) NREPLY Set */\r
+#define USBC_UECON1SET_RAMACERES (0x1u << 11) /**< \brief (USBC_UECON1SET) RAMACERE Set */\r
+#define USBC_UECON1SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UECON1SET) NBUSYBKE Set */\r
+#define USBC_UECON1SET_KILLBKS (0x1u << 13) /**< \brief (USBC_UECON1SET) KILLBK Set */\r
+#define USBC_UECON1SET_NYETDISS (0x1u << 17) /**< \brief (USBC_UECON1SET) NYETDIS Set */\r
+#define USBC_UECON1SET_RSTDTS (0x1u << 18) /**< \brief (USBC_UECON1SET) RSTDT Set */\r
+#define USBC_UECON1SET_STALLRQS (0x1u << 19) /**< \brief (USBC_UECON1SET) STALLRQ Set */\r
+#define USBC_UECON1SET_BUSY0S (0x1u << 24) /**< \brief (USBC_UECON1SET) BUSY0 Set */\r
+#define USBC_UECON1SET_BUSY1S (0x1u << 25) /**< \brief (USBC_UECON1SET) BUSY1 Set */\r
+/* -------- USBC_UECON2SET : (USBC Offset: 0x1F8) Endpoint Control Set Register -------- */\r
+#define USBC_UECON2SET_TXINES (0x1u << 0) /**< \brief (USBC_UECON2SET) TXINE Set */\r
+#define USBC_UECON2SET_RXOUTES (0x1u << 1) /**< \brief (USBC_UECON2SET) RXOUTE Set */\r
+#define USBC_UECON2SET_RXSTPES (0x1u << 2) /**< \brief (USBC_UECON2SET) RXSTPE Set */\r
+#define USBC_UECON2SET_NAKOUTES (0x1u << 3) /**< \brief (USBC_UECON2SET) NAKOUTE Set */\r
+#define USBC_UECON2SET_NAKINES (0x1u << 4) /**< \brief (USBC_UECON2SET) NAKINE Set */\r
+#define USBC_UECON2SET_STALLEDES (0x1u << 6) /**< \brief (USBC_UECON2SET) STALLEDE Set */\r
+#define USBC_UECON2SET_NREPLYS (0x1u << 8) /**< \brief (USBC_UECON2SET) NREPLY Set */\r
+#define USBC_UECON2SET_RAMACERES (0x1u << 11) /**< \brief (USBC_UECON2SET) RAMACERE Set */\r
+#define USBC_UECON2SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UECON2SET) NBUSYBKE Set */\r
+#define USBC_UECON2SET_KILLBKS (0x1u << 13) /**< \brief (USBC_UECON2SET) KILLBK Set */\r
+#define USBC_UECON2SET_NYETDISS (0x1u << 17) /**< \brief (USBC_UECON2SET) NYETDIS Set */\r
+#define USBC_UECON2SET_RSTDTS (0x1u << 18) /**< \brief (USBC_UECON2SET) RSTDT Set */\r
+#define USBC_UECON2SET_STALLRQS (0x1u << 19) /**< \brief (USBC_UECON2SET) STALLRQ Set */\r
+#define USBC_UECON2SET_BUSY0S (0x1u << 24) /**< \brief (USBC_UECON2SET) BUSY0 Set */\r
+#define USBC_UECON2SET_BUSY1S (0x1u << 25) /**< \brief (USBC_UECON2SET) BUSY1 Set */\r
+/* -------- USBC_UECON3SET : (USBC Offset: 0x1FC) Endpoint Control Set Register -------- */\r
+#define USBC_UECON3SET_TXINES (0x1u << 0) /**< \brief (USBC_UECON3SET) TXINE Set */\r
+#define USBC_UECON3SET_RXOUTES (0x1u << 1) /**< \brief (USBC_UECON3SET) RXOUTE Set */\r
+#define USBC_UECON3SET_RXSTPES (0x1u << 2) /**< \brief (USBC_UECON3SET) RXSTPE Set */\r
+#define USBC_UECON3SET_NAKOUTES (0x1u << 3) /**< \brief (USBC_UECON3SET) NAKOUTE Set */\r
+#define USBC_UECON3SET_NAKINES (0x1u << 4) /**< \brief (USBC_UECON3SET) NAKINE Set */\r
+#define USBC_UECON3SET_STALLEDES (0x1u << 6) /**< \brief (USBC_UECON3SET) STALLEDE Set */\r
+#define USBC_UECON3SET_NREPLYS (0x1u << 8) /**< \brief (USBC_UECON3SET) NREPLY Set */\r
+#define USBC_UECON3SET_RAMACERES (0x1u << 11) /**< \brief (USBC_UECON3SET) RAMACERE Set */\r
+#define USBC_UECON3SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UECON3SET) NBUSYBKE Set */\r
+#define USBC_UECON3SET_KILLBKS (0x1u << 13) /**< \brief (USBC_UECON3SET) KILLBK Set */\r
+#define USBC_UECON3SET_NYETDISS (0x1u << 17) /**< \brief (USBC_UECON3SET) NYETDIS Set */\r
+#define USBC_UECON3SET_RSTDTS (0x1u << 18) /**< \brief (USBC_UECON3SET) RSTDT Set */\r
+#define USBC_UECON3SET_STALLRQS (0x1u << 19) /**< \brief (USBC_UECON3SET) STALLRQ Set */\r
+#define USBC_UECON3SET_BUSY0S (0x1u << 24) /**< \brief (USBC_UECON3SET) BUSY0 Set */\r
+#define USBC_UECON3SET_BUSY1S (0x1u << 25) /**< \brief (USBC_UECON3SET) BUSY1 Set */\r
+/* -------- USBC_UECON4SET : (USBC Offset: 0x200) Endpoint Control Set Register -------- */\r
+#define USBC_UECON4SET_TXINES (0x1u << 0) /**< \brief (USBC_UECON4SET) TXINE Set */\r
+#define USBC_UECON4SET_RXOUTES (0x1u << 1) /**< \brief (USBC_UECON4SET) RXOUTE Set */\r
+#define USBC_UECON4SET_RXSTPES (0x1u << 2) /**< \brief (USBC_UECON4SET) RXSTPE Set */\r
+#define USBC_UECON4SET_NAKOUTES (0x1u << 3) /**< \brief (USBC_UECON4SET) NAKOUTE Set */\r
+#define USBC_UECON4SET_NAKINES (0x1u << 4) /**< \brief (USBC_UECON4SET) NAKINE Set */\r
+#define USBC_UECON4SET_STALLEDES (0x1u << 6) /**< \brief (USBC_UECON4SET) STALLEDE Set */\r
+#define USBC_UECON4SET_NREPLYS (0x1u << 8) /**< \brief (USBC_UECON4SET) NREPLY Set */\r
+#define USBC_UECON4SET_RAMACERES (0x1u << 11) /**< \brief (USBC_UECON4SET) RAMACERE Set */\r
+#define USBC_UECON4SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UECON4SET) NBUSYBKE Set */\r
+#define USBC_UECON4SET_KILLBKS (0x1u << 13) /**< \brief (USBC_UECON4SET) KILLBK Set */\r
+#define USBC_UECON4SET_NYETDISS (0x1u << 17) /**< \brief (USBC_UECON4SET) NYETDIS Set */\r
+#define USBC_UECON4SET_RSTDTS (0x1u << 18) /**< \brief (USBC_UECON4SET) RSTDT Set */\r
+#define USBC_UECON4SET_STALLRQS (0x1u << 19) /**< \brief (USBC_UECON4SET) STALLRQ Set */\r
+#define USBC_UECON4SET_BUSY0S (0x1u << 24) /**< \brief (USBC_UECON4SET) BUSY0 Set */\r
+#define USBC_UECON4SET_BUSY1S (0x1u << 25) /**< \brief (USBC_UECON4SET) BUSY1 Set */\r
+/* -------- USBC_UECON5SET : (USBC Offset: 0x204) Endpoint Control Set Register -------- */\r
+#define USBC_UECON5SET_TXINES (0x1u << 0) /**< \brief (USBC_UECON5SET) TXINE Set */\r
+#define USBC_UECON5SET_RXOUTES (0x1u << 1) /**< \brief (USBC_UECON5SET) RXOUTE Set */\r
+#define USBC_UECON5SET_RXSTPES (0x1u << 2) /**< \brief (USBC_UECON5SET) RXSTPE Set */\r
+#define USBC_UECON5SET_NAKOUTES (0x1u << 3) /**< \brief (USBC_UECON5SET) NAKOUTE Set */\r
+#define USBC_UECON5SET_NAKINES (0x1u << 4) /**< \brief (USBC_UECON5SET) NAKINE Set */\r
+#define USBC_UECON5SET_STALLEDES (0x1u << 6) /**< \brief (USBC_UECON5SET) STALLEDE Set */\r
+#define USBC_UECON5SET_NREPLYS (0x1u << 8) /**< \brief (USBC_UECON5SET) NREPLY Set */\r
+#define USBC_UECON5SET_RAMACERES (0x1u << 11) /**< \brief (USBC_UECON5SET) RAMACERE Set */\r
+#define USBC_UECON5SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UECON5SET) NBUSYBKE Set */\r
+#define USBC_UECON5SET_KILLBKS (0x1u << 13) /**< \brief (USBC_UECON5SET) KILLBK Set */\r
+#define USBC_UECON5SET_NYETDISS (0x1u << 17) /**< \brief (USBC_UECON5SET) NYETDIS Set */\r
+#define USBC_UECON5SET_RSTDTS (0x1u << 18) /**< \brief (USBC_UECON5SET) RSTDT Set */\r
+#define USBC_UECON5SET_STALLRQS (0x1u << 19) /**< \brief (USBC_UECON5SET) STALLRQ Set */\r
+#define USBC_UECON5SET_BUSY0S (0x1u << 24) /**< \brief (USBC_UECON5SET) BUSY0 Set */\r
+#define USBC_UECON5SET_BUSY1S (0x1u << 25) /**< \brief (USBC_UECON5SET) BUSY1 Set */\r
+/* -------- USBC_UECON6SET : (USBC Offset: 0x208) Endpoint Control Set Register -------- */\r
+#define USBC_UECON6SET_TXINES (0x1u << 0) /**< \brief (USBC_UECON6SET) TXINE Set */\r
+#define USBC_UECON6SET_RXOUTES (0x1u << 1) /**< \brief (USBC_UECON6SET) RXOUTE Set */\r
+#define USBC_UECON6SET_RXSTPES (0x1u << 2) /**< \brief (USBC_UECON6SET) RXSTPE Set */\r
+#define USBC_UECON6SET_NAKOUTES (0x1u << 3) /**< \brief (USBC_UECON6SET) NAKOUTE Set */\r
+#define USBC_UECON6SET_NAKINES (0x1u << 4) /**< \brief (USBC_UECON6SET) NAKINE Set */\r
+#define USBC_UECON6SET_STALLEDES (0x1u << 6) /**< \brief (USBC_UECON6SET) STALLEDE Set */\r
+#define USBC_UECON6SET_NREPLYS (0x1u << 8) /**< \brief (USBC_UECON6SET) NREPLY Set */\r
+#define USBC_UECON6SET_RAMACERES (0x1u << 11) /**< \brief (USBC_UECON6SET) RAMACERE Set */\r
+#define USBC_UECON6SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UECON6SET) NBUSYBKE Set */\r
+#define USBC_UECON6SET_KILLBKS (0x1u << 13) /**< \brief (USBC_UECON6SET) KILLBK Set */\r
+#define USBC_UECON6SET_NYETDISS (0x1u << 17) /**< \brief (USBC_UECON6SET) NYETDIS Set */\r
+#define USBC_UECON6SET_RSTDTS (0x1u << 18) /**< \brief (USBC_UECON6SET) RSTDT Set */\r
+#define USBC_UECON6SET_STALLRQS (0x1u << 19) /**< \brief (USBC_UECON6SET) STALLRQ Set */\r
+#define USBC_UECON6SET_BUSY0S (0x1u << 24) /**< \brief (USBC_UECON6SET) BUSY0 Set */\r
+#define USBC_UECON6SET_BUSY1S (0x1u << 25) /**< \brief (USBC_UECON6SET) BUSY1 Set */\r
+/* -------- USBC_UECON7SET : (USBC Offset: 0x20C) Endpoint Control Set Register -------- */\r
+#define USBC_UECON7SET_TXINES (0x1u << 0) /**< \brief (USBC_UECON7SET) TXINE Set */\r
+#define USBC_UECON7SET_RXOUTES (0x1u << 1) /**< \brief (USBC_UECON7SET) RXOUTE Set */\r
+#define USBC_UECON7SET_RXSTPES (0x1u << 2) /**< \brief (USBC_UECON7SET) RXSTPE Set */\r
+#define USBC_UECON7SET_NAKOUTES (0x1u << 3) /**< \brief (USBC_UECON7SET) NAKOUTE Set */\r
+#define USBC_UECON7SET_NAKINES (0x1u << 4) /**< \brief (USBC_UECON7SET) NAKINE Set */\r
+#define USBC_UECON7SET_STALLEDES (0x1u << 6) /**< \brief (USBC_UECON7SET) STALLEDE Set */\r
+#define USBC_UECON7SET_NREPLYS (0x1u << 8) /**< \brief (USBC_UECON7SET) NREPLY Set */\r
+#define USBC_UECON7SET_RAMACERES (0x1u << 11) /**< \brief (USBC_UECON7SET) RAMACERE Set */\r
+#define USBC_UECON7SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UECON7SET) NBUSYBKE Set */\r
+#define USBC_UECON7SET_KILLBKS (0x1u << 13) /**< \brief (USBC_UECON7SET) KILLBK Set */\r
+#define USBC_UECON7SET_NYETDISS (0x1u << 17) /**< \brief (USBC_UECON7SET) NYETDIS Set */\r
+#define USBC_UECON7SET_RSTDTS (0x1u << 18) /**< \brief (USBC_UECON7SET) RSTDT Set */\r
+#define USBC_UECON7SET_STALLRQS (0x1u << 19) /**< \brief (USBC_UECON7SET) STALLRQ Set */\r
+#define USBC_UECON7SET_BUSY0S (0x1u << 24) /**< \brief (USBC_UECON7SET) BUSY0 Set */\r
+#define USBC_UECON7SET_BUSY1S (0x1u << 25) /**< \brief (USBC_UECON7SET) BUSY1 Set */\r
+/* -------- USBC_UECON0CLR : (USBC Offset: 0x220) Endpoint Control Clear Register -------- */\r
+#define USBC_UECON0CLR_TXINEC (0x1u << 0) /**< \brief (USBC_UECON0CLR) TXINE Clear */\r
+#define USBC_UECON0CLR_RXOUTEC (0x1u << 1) /**< \brief (USBC_UECON0CLR) RXOUTE Clear */\r
+#define USBC_UECON0CLR_RXSTPEC (0x1u << 2) /**< \brief (USBC_UECON0CLR) RXSTPE Clear */\r
+#define USBC_UECON0CLR_NAKOUTEC (0x1u << 3) /**< \brief (USBC_UECON0CLR) NAKOUTE Clear */\r
+#define USBC_UECON0CLR_NAKINEC (0x1u << 4) /**< \brief (USBC_UECON0CLR) NAKINE Clear */\r
+#define USBC_UECON0CLR_STALLEDEC (0x1u << 6) /**< \brief (USBC_UECON0CLR) STALLEDE Clear */\r
+#define USBC_UECON0CLR_NREPLYC (0x1u << 8) /**< \brief (USBC_UECON0CLR) NREPLY Clear */\r
+#define USBC_UECON0CLR_RAMACEREC (0x1u << 11) /**< \brief (USBC_UECON0CLR) RAMACERE Clear */\r
+#define USBC_UECON0CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UECON0CLR) NBUSYBKE Clear */\r
+#define USBC_UECON0CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UECON0CLR) FIFOCON Clear */\r
+#define USBC_UECON0CLR_NYETDISC (0x1u << 17) /**< \brief (USBC_UECON0CLR) NYETDIS Clear */\r
+#define USBC_UECON0CLR_STALLRQC (0x1u << 19) /**< \brief (USBC_UECON0CLR) STALLRQ Clear */\r
+#define USBC_UECON0CLR_BUSY0C (0x1u << 24) /**< \brief (USBC_UECON0CLR) BUSY0 Clear */\r
+#define USBC_UECON0CLR_BUSY1C (0x1u << 25) /**< \brief (USBC_UECON0CLR) BUSY1 Clear */\r
+/* -------- USBC_UECON1CLR : (USBC Offset: 0x224) TXINE Clear -------- */\r
+#define USBC_UECON1CLR_TXINEC (0x1u << 0) /**< \brief (USBC_UECON1CLR) TXINE Clear */\r
+#define USBC_UECON1CLR_RXOUTEC (0x1u << 1) /**< \brief (USBC_UECON1CLR) RXOUTE Clear */\r
+#define USBC_UECON1CLR_RXSTPEC (0x1u << 2) /**< \brief (USBC_UECON1CLR) RXOUTE Clear */\r
+#define USBC_UECON1CLR_NAKOUTEC (0x1u << 3) /**< \brief (USBC_UECON1CLR) NAKOUTE Clear */\r
+#define USBC_UECON1CLR_NAKINEC (0x1u << 4) /**< \brief (USBC_UECON1CLR) NAKINE Clear */\r
+#define USBC_UECON1CLR_STALLEDEC (0x1u << 6) /**< \brief (USBC_UECON1CLR) RXSTPE Clear */\r
+#define USBC_UECON1CLR_NREPLYC (0x1u << 8) /**< \brief (USBC_UECON1CLR) NREPLY Clear */\r
+#define USBC_UECON1CLR_RAMACEREC (0x1u << 11) /**< \brief (USBC_UECON1CLR) RAMACERE Clear */\r
+#define USBC_UECON1CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UECON1CLR) NBUSYBKE Clear */\r
+#define USBC_UECON1CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UECON1CLR) FIFOCON Clear */\r
+#define USBC_UECON1CLR_NYETDISC (0x1u << 17) /**< \brief (USBC_UECON1CLR) NYETDIS Clear */\r
+#define USBC_UECON1CLR_STALLRQC (0x1u << 19) /**< \brief (USBC_UECON1CLR) STALLEDE Clear */\r
+#define USBC_UECON1CLR_BUSY0C (0x1u << 24) /**< \brief (USBC_UECON1CLR) BUSY0 Clear */\r
+#define USBC_UECON1CLR_BUSY1C (0x1u << 25) /**< \brief (USBC_UECON1CLR) BUSY1 Clear */\r
+/* -------- USBC_UECON2CLR : (USBC Offset: 0x228) TXINE Clear -------- */\r
+#define USBC_UECON2CLR_TXINEC (0x1u << 0) /**< \brief (USBC_UECON2CLR) TXINE Clear */\r
+#define USBC_UECON2CLR_RXOUTEC (0x1u << 1) /**< \brief (USBC_UECON2CLR) RXOUTE Clear */\r
+#define USBC_UECON2CLR_RXSTPEC (0x1u << 2) /**< \brief (USBC_UECON2CLR) RXOUTE Clear */\r
+#define USBC_UECON2CLR_NAKOUTEC (0x1u << 3) /**< \brief (USBC_UECON2CLR) NAKOUTE Clear */\r
+#define USBC_UECON2CLR_NAKINEC (0x1u << 4) /**< \brief (USBC_UECON2CLR) NAKINE Clear */\r
+#define USBC_UECON2CLR_STALLEDEC (0x1u << 6) /**< \brief (USBC_UECON2CLR) RXSTPE Clear */\r
+#define USBC_UECON2CLR_NREPLYC (0x1u << 8) /**< \brief (USBC_UECON2CLR) NREPLY Clear */\r
+#define USBC_UECON2CLR_RAMACEREC (0x1u << 11) /**< \brief (USBC_UECON2CLR) RAMACERE Clear */\r
+#define USBC_UECON2CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UECON2CLR) NBUSYBKE Clear */\r
+#define USBC_UECON2CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UECON2CLR) FIFOCON Clear */\r
+#define USBC_UECON2CLR_NYETDISC (0x1u << 17) /**< \brief (USBC_UECON2CLR) NYETDIS Clear */\r
+#define USBC_UECON2CLR_STALLRQC (0x1u << 19) /**< \brief (USBC_UECON2CLR) STALLEDE Clear */\r
+#define USBC_UECON2CLR_BUSY0C (0x1u << 24) /**< \brief (USBC_UECON2CLR) BUSY0 Clear */\r
+#define USBC_UECON2CLR_BUSY1C (0x1u << 25) /**< \brief (USBC_UECON2CLR) BUSY1 Clear */\r
+/* -------- USBC_UECON3CLR : (USBC Offset: 0x22C) TXINE Clear -------- */\r
+#define USBC_UECON3CLR_TXINEC (0x1u << 0) /**< \brief (USBC_UECON3CLR) TXINE Clear */\r
+#define USBC_UECON3CLR_RXOUTEC (0x1u << 1) /**< \brief (USBC_UECON3CLR) RXOUTE Clear */\r
+#define USBC_UECON3CLR_RXSTPEC (0x1u << 2) /**< \brief (USBC_UECON3CLR) RXOUTE Clear */\r
+#define USBC_UECON3CLR_NAKOUTEC (0x1u << 3) /**< \brief (USBC_UECON3CLR) NAKOUTE Clear */\r
+#define USBC_UECON3CLR_NAKINEC (0x1u << 4) /**< \brief (USBC_UECON3CLR) NAKINE Clear */\r
+#define USBC_UECON3CLR_STALLEDEC (0x1u << 6) /**< \brief (USBC_UECON3CLR) RXSTPE Clear */\r
+#define USBC_UECON3CLR_NREPLYC (0x1u << 8) /**< \brief (USBC_UECON3CLR) NREPLY Clear */\r
+#define USBC_UECON3CLR_RAMACEREC (0x1u << 11) /**< \brief (USBC_UECON3CLR) RAMACERE Clear */\r
+#define USBC_UECON3CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UECON3CLR) NBUSYBKE Clear */\r
+#define USBC_UECON3CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UECON3CLR) FIFOCON Clear */\r
+#define USBC_UECON3CLR_NYETDISC (0x1u << 17) /**< \brief (USBC_UECON3CLR) NYETDIS Clear */\r
+#define USBC_UECON3CLR_STALLRQC (0x1u << 19) /**< \brief (USBC_UECON3CLR) STALLEDE Clear */\r
+#define USBC_UECON3CLR_BUSY0C (0x1u << 24) /**< \brief (USBC_UECON3CLR) BUSY0 Clear */\r
+#define USBC_UECON3CLR_BUSY1C (0x1u << 25) /**< \brief (USBC_UECON3CLR) BUSY1 Clear */\r
+/* -------- USBC_UECON4CLR : (USBC Offset: 0x230) TXINE Clear -------- */\r
+#define USBC_UECON4CLR_TXINEC (0x1u << 0) /**< \brief (USBC_UECON4CLR) TXINE Clear */\r
+#define USBC_UECON4CLR_RXOUTEC (0x1u << 1) /**< \brief (USBC_UECON4CLR) RXOUTE Clear */\r
+#define USBC_UECON4CLR_RXSTPEC (0x1u << 2) /**< \brief (USBC_UECON4CLR) RXOUTE Clear */\r
+#define USBC_UECON4CLR_NAKOUTEC (0x1u << 3) /**< \brief (USBC_UECON4CLR) NAKOUTE Clear */\r
+#define USBC_UECON4CLR_NAKINEC (0x1u << 4) /**< \brief (USBC_UECON4CLR) NAKINE Clear */\r
+#define USBC_UECON4CLR_STALLEDEC (0x1u << 6) /**< \brief (USBC_UECON4CLR) RXSTPE Clear */\r
+#define USBC_UECON4CLR_NREPLYC (0x1u << 8) /**< \brief (USBC_UECON4CLR) NREPLY Clear */\r
+#define USBC_UECON4CLR_RAMACEREC (0x1u << 11) /**< \brief (USBC_UECON4CLR) RAMACERE Clear */\r
+#define USBC_UECON4CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UECON4CLR) NBUSYBKE Clear */\r
+#define USBC_UECON4CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UECON4CLR) FIFOCON Clear */\r
+#define USBC_UECON4CLR_NYETDISC (0x1u << 17) /**< \brief (USBC_UECON4CLR) NYETDIS Clear */\r
+#define USBC_UECON4CLR_STALLRQC (0x1u << 19) /**< \brief (USBC_UECON4CLR) STALLEDE Clear */\r
+#define USBC_UECON4CLR_BUSY0C (0x1u << 24) /**< \brief (USBC_UECON4CLR) BUSY0 Clear */\r
+#define USBC_UECON4CLR_BUSY1C (0x1u << 25) /**< \brief (USBC_UECON4CLR) BUSY1 Clear */\r
+/* -------- USBC_UECON5CLR : (USBC Offset: 0x234) TXINE Clear -------- */\r
+#define USBC_UECON5CLR_TXINEC (0x1u << 0) /**< \brief (USBC_UECON5CLR) TXINE Clear */\r
+#define USBC_UECON5CLR_RXOUTEC (0x1u << 1) /**< \brief (USBC_UECON5CLR) RXOUTE Clear */\r
+#define USBC_UECON5CLR_RXSTPEC (0x1u << 2) /**< \brief (USBC_UECON5CLR) RXOUTE Clear */\r
+#define USBC_UECON5CLR_NAKOUTEC (0x1u << 3) /**< \brief (USBC_UECON5CLR) NAKOUTE Clear */\r
+#define USBC_UECON5CLR_NAKINEC (0x1u << 4) /**< \brief (USBC_UECON5CLR) NAKINE Clear */\r
+#define USBC_UECON5CLR_STALLEDEC (0x1u << 6) /**< \brief (USBC_UECON5CLR) RXSTPE Clear */\r
+#define USBC_UECON5CLR_NREPLYC (0x1u << 8) /**< \brief (USBC_UECON5CLR) NREPLY Clear */\r
+#define USBC_UECON5CLR_RAMACEREC (0x1u << 11) /**< \brief (USBC_UECON5CLR) RAMACERE Clear */\r
+#define USBC_UECON5CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UECON5CLR) NBUSYBKE Clear */\r
+#define USBC_UECON5CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UECON5CLR) FIFOCON Clear */\r
+#define USBC_UECON5CLR_NYETDISC (0x1u << 17) /**< \brief (USBC_UECON5CLR) NYETDIS Clear */\r
+#define USBC_UECON5CLR_STALLRQC (0x1u << 19) /**< \brief (USBC_UECON5CLR) STALLEDE Clear */\r
+#define USBC_UECON5CLR_BUSY0C (0x1u << 24) /**< \brief (USBC_UECON5CLR) BUSY0 Clear */\r
+#define USBC_UECON5CLR_BUSY1C (0x1u << 25) /**< \brief (USBC_UECON5CLR) BUSY1 Clear */\r
+/* -------- USBC_UECON6CLR : (USBC Offset: 0x238) TXINE Clear -------- */\r
+#define USBC_UECON6CLR_TXINEC (0x1u << 0) /**< \brief (USBC_UECON6CLR) TXINE Clear */\r
+#define USBC_UECON6CLR_RXOUTEC (0x1u << 1) /**< \brief (USBC_UECON6CLR) RXOUTE Clear */\r
+#define USBC_UECON6CLR_RXSTPEC (0x1u << 2) /**< \brief (USBC_UECON6CLR) RXOUTE Clear */\r
+#define USBC_UECON6CLR_NAKOUTEC (0x1u << 3) /**< \brief (USBC_UECON6CLR) NAKOUTE Clear */\r
+#define USBC_UECON6CLR_NAKINEC (0x1u << 4) /**< \brief (USBC_UECON6CLR) NAKINE Clear */\r
+#define USBC_UECON6CLR_STALLEDEC (0x1u << 6) /**< \brief (USBC_UECON6CLR) RXSTPE Clear */\r
+#define USBC_UECON6CLR_NREPLYC (0x1u << 8) /**< \brief (USBC_UECON6CLR) NREPLY Clear */\r
+#define USBC_UECON6CLR_RAMACEREC (0x1u << 11) /**< \brief (USBC_UECON6CLR) RAMACERE Clear */\r
+#define USBC_UECON6CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UECON6CLR) NBUSYBKE Clear */\r
+#define USBC_UECON6CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UECON6CLR) FIFOCON Clear */\r
+#define USBC_UECON6CLR_NYETDISC (0x1u << 17) /**< \brief (USBC_UECON6CLR) NYETDIS Clear */\r
+#define USBC_UECON6CLR_STALLRQC (0x1u << 19) /**< \brief (USBC_UECON6CLR) STALLEDE Clear */\r
+#define USBC_UECON6CLR_BUSY0C (0x1u << 24) /**< \brief (USBC_UECON6CLR) BUSY0 Clear */\r
+#define USBC_UECON6CLR_BUSY1C (0x1u << 25) /**< \brief (USBC_UECON6CLR) BUSY1 Clear */\r
+/* -------- USBC_UECON7CLR : (USBC Offset: 0x23C) TXINE Clear -------- */\r
+#define USBC_UECON7CLR_TXINEC (0x1u << 0) /**< \brief (USBC_UECON7CLR) TXINE Clear */\r
+#define USBC_UECON7CLR_RXOUTEC (0x1u << 1) /**< \brief (USBC_UECON7CLR) RXOUTE Clear */\r
+#define USBC_UECON7CLR_RXSTPEC (0x1u << 2) /**< \brief (USBC_UECON7CLR) RXOUTE Clear */\r
+#define USBC_UECON7CLR_NAKOUTEC (0x1u << 3) /**< \brief (USBC_UECON7CLR) NAKOUTE Clear */\r
+#define USBC_UECON7CLR_NAKINEC (0x1u << 4) /**< \brief (USBC_UECON7CLR) NAKINE Clear */\r
+#define USBC_UECON7CLR_STALLEDEC (0x1u << 6) /**< \brief (USBC_UECON7CLR) RXSTPE Clear */\r
+#define USBC_UECON7CLR_NREPLYC (0x1u << 8) /**< \brief (USBC_UECON7CLR) NREPLY Clear */\r
+#define USBC_UECON7CLR_RAMACEREC (0x1u << 11) /**< \brief (USBC_UECON7CLR) RAMACERE Clear */\r
+#define USBC_UECON7CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UECON7CLR) NBUSYBKE Clear */\r
+#define USBC_UECON7CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UECON7CLR) FIFOCON Clear */\r
+#define USBC_UECON7CLR_NYETDISC (0x1u << 17) /**< \brief (USBC_UECON7CLR) NYETDIS Clear */\r
+#define USBC_UECON7CLR_STALLRQC (0x1u << 19) /**< \brief (USBC_UECON7CLR) STALLEDE Clear */\r
+#define USBC_UECON7CLR_BUSY0C (0x1u << 24) /**< \brief (USBC_UECON7CLR) BUSY0 Clear */\r
+#define USBC_UECON7CLR_BUSY1C (0x1u << 25) /**< \brief (USBC_UECON7CLR) BUSY1 Clear */\r
+/* -------- USBC_UHCON : (USBC Offset: 0x400) Host General Control Register -------- */\r
+#define USBC_UHCON_SOFE (0x1u << 8) /**< \brief (USBC_UHCON) SOF Enable */\r
+#define USBC_UHCON_RESET (0x1u << 9) /**< \brief (USBC_UHCON) Send USB Reset */\r
+#define USBC_UHCON_RESUME (0x1u << 10) /**< \brief (USBC_UHCON) Send USB Resume */\r
+#define USBC_UHCON_SPDCONF_Pos 12\r
+#define USBC_UHCON_SPDCONF_Msk (0x3u << USBC_UHCON_SPDCONF_Pos) /**< \brief (USBC_UHCON) Speed Configuration */\r
+#define USBC_UHCON_SPDCONF(value) ((USBC_UHCON_SPDCONF_Msk & ((value) << USBC_UHCON_SPDCONF_Pos)))\r
+#define USBC_UHCON_TSTJ (0x1u << 16) /**< \brief (USBC_UHCON) Test J */\r
+#define USBC_UHCON_TSTK (0x1u << 17) /**< \brief (USBC_UHCON) Test K */\r
+/* -------- USBC_UHINT : (USBC Offset: 0x404) Host Global Interrupt Register -------- */\r
+#define USBC_UHINT_DCONNI (0x1u << 0) /**< \brief (USBC_UHINT) Device Connection Interrupt */\r
+#define USBC_UHINT_DDISCI (0x1u << 1) /**< \brief (USBC_UHINT) Device Disconnection Interrupt */\r
+#define USBC_UHINT_RSTI (0x1u << 2) /**< \brief (USBC_UHINT) USB Reset Sent Interrupt */\r
+#define USBC_UHINT_RSMEDI (0x1u << 3) /**< \brief (USBC_UHINT) Downstream Resume Sent Interrupt */\r
+#define USBC_UHINT_RXRSMI (0x1u << 4) /**< \brief (USBC_UHINT) Upstream Resume Received Interrupt */\r
+#define USBC_UHINT_HSOFI (0x1u << 5) /**< \brief (USBC_UHINT) Host SOF Interrupt */\r
+#define USBC_UHINT_HWUPI (0x1u << 6) /**< \brief (USBC_UHINT) Host Wake-Up Interrupt */\r
+#define USBC_UHINT_P0INT (0x1u << 8) /**< \brief (USBC_UHINT) Pipe 0 Interrupt */\r
+#define USBC_UHINT_P1INT (0x1u << 9) /**< \brief (USBC_UHINT) Pipe 1 Interrupt */\r
+#define USBC_UHINT_P2INT (0x1u << 10) /**< \brief (USBC_UHINT) Pipe 2 Interrupt */\r
+#define USBC_UHINT_P3INT (0x1u << 11) /**< \brief (USBC_UHINT) Pipe 3 Interrupt */\r
+#define USBC_UHINT_P4INT (0x1u << 12) /**< \brief (USBC_UHINT) Pipe 4 Interrupt */\r
+#define USBC_UHINT_P5INT (0x1u << 13) /**< \brief (USBC_UHINT) Pipe 5 Interrupt */\r
+#define USBC_UHINT_P6INT (0x1u << 14) /**< \brief (USBC_UHINT) Pipe 6 Interrupt */\r
+/* -------- USBC_UHINTCLR : (USBC Offset: 0x408) Host Global Interrrupt Clear Register -------- */\r
+#define USBC_UHINTCLR_DCONNIC (0x1u << 0) /**< \brief (USBC_UHINTCLR) DCONNI Clear */\r
+#define USBC_UHINTCLR_DDISCIC (0x1u << 1) /**< \brief (USBC_UHINTCLR) DDISCI Clear */\r
+#define USBC_UHINTCLR_RSTIC (0x1u << 2) /**< \brief (USBC_UHINTCLR) RSTI Clear */\r
+#define USBC_UHINTCLR_RSMEDIC (0x1u << 3) /**< \brief (USBC_UHINTCLR) RSMEDI Clear */\r
+#define USBC_UHINTCLR_RXRSMIC (0x1u << 4) /**< \brief (USBC_UHINTCLR) RXRSMI Clear */\r
+#define USBC_UHINTCLR_HSOFIC (0x1u << 5) /**< \brief (USBC_UHINTCLR) HSOFI Clear */\r
+#define USBC_UHINTCLR_HWUPIC (0x1u << 6) /**< \brief (USBC_UHINTCLR) HWUPI Clear */\r
+/* -------- USBC_UHINTSET : (USBC Offset: 0x40C) Host Global Interrupt Set Register -------- */\r
+#define USBC_UHINTSET_DCONNIS (0x1u << 0) /**< \brief (USBC_UHINTSET) DCONNI Set */\r
+#define USBC_UHINTSET_DDISCIS (0x1u << 1) /**< \brief (USBC_UHINTSET) DDISCI Set */\r
+#define USBC_UHINTSET_RSTIS (0x1u << 2) /**< \brief (USBC_UHINTSET) RSTI Set */\r
+#define USBC_UHINTSET_RSMEDIS (0x1u << 3) /**< \brief (USBC_UHINTSET) RSMEDI Set */\r
+#define USBC_UHINTSET_RXRSMIS (0x1u << 4) /**< \brief (USBC_UHINTSET) RXRSMI Set */\r
+#define USBC_UHINTSET_HSOFIS (0x1u << 5) /**< \brief (USBC_UHINTSET) HSOFI Set */\r
+#define USBC_UHINTSET_HWUPIS (0x1u << 6) /**< \brief (USBC_UHINTSET) HWUPI Set */\r
+/* -------- USBC_UHINTE : (USBC Offset: 0x410) Host Global Interrupt Enable Register -------- */\r
+#define USBC_UHINTE_DCONNIE (0x1u << 0) /**< \brief (USBC_UHINTE) DCONNI Enable */\r
+#define USBC_UHINTE_DDISCIE (0x1u << 1) /**< \brief (USBC_UHINTE) DDISCI Enable */\r
+#define USBC_UHINTE_RSTIE (0x1u << 2) /**< \brief (USBC_UHINTE) RSTI Enable */\r
+#define USBC_UHINTE_RSMEDIE (0x1u << 3) /**< \brief (USBC_UHINTE) RSMEDI Enable */\r
+#define USBC_UHINTE_RXRSMIE (0x1u << 4) /**< \brief (USBC_UHINTE) RXRSMI Enable */\r
+#define USBC_UHINTE_HSOFIE (0x1u << 5) /**< \brief (USBC_UHINTE) HSOFI Enable */\r
+#define USBC_UHINTE_HWUPIE (0x1u << 6) /**< \brief (USBC_UHINTE) HWUPI Enable */\r
+#define USBC_UHINTE_P0INTE (0x1u << 8) /**< \brief (USBC_UHINTE) P0INT Enable */\r
+#define USBC_UHINTE_P1INTE (0x1u << 9) /**< \brief (USBC_UHINTE) P1INT Enable */\r
+#define USBC_UHINTE_P2INTE (0x1u << 10) /**< \brief (USBC_UHINTE) P2INT Enable */\r
+#define USBC_UHINTE_P3INTE (0x1u << 11) /**< \brief (USBC_UHINTE) P3INT Enable */\r
+#define USBC_UHINTE_P4INTE (0x1u << 12) /**< \brief (USBC_UHINTE) P4INT Enable */\r
+#define USBC_UHINTE_P5INTE (0x1u << 13) /**< \brief (USBC_UHINTE) P5INT Enable */\r
+#define USBC_UHINTE_P6INTE (0x1u << 14) /**< \brief (USBC_UHINTE) P6INT Enable */\r
+#define USBC_UHINTE_P7INTE (0x1u << 15) /**< \brief (USBC_UHINTE) P7INT Enable */\r
+/* -------- USBC_UHINTECLR : (USBC Offset: 0x414) Host Global Interrupt Enable Clear Register -------- */\r
+#define USBC_UHINTECLR_DCONNIEC (0x1u << 0) /**< \brief (USBC_UHINTECLR) DCONNIE Clear */\r
+#define USBC_UHINTECLR_DDISCIEC (0x1u << 1) /**< \brief (USBC_UHINTECLR) DDISCIE Clear */\r
+#define USBC_UHINTECLR_RSTIEC (0x1u << 2) /**< \brief (USBC_UHINTECLR) RSTIE Clear */\r
+#define USBC_UHINTECLR_RSMEDIEC (0x1u << 3) /**< \brief (USBC_UHINTECLR) RSMEDIE Clear */\r
+#define USBC_UHINTECLR_RXRSMIEC (0x1u << 4) /**< \brief (USBC_UHINTECLR) RXRSMIE Clear */\r
+#define USBC_UHINTECLR_HSOFIEC (0x1u << 5) /**< \brief (USBC_UHINTECLR) HSOFIE Clear */\r
+#define USBC_UHINTECLR_HWUPIEC (0x1u << 6) /**< \brief (USBC_UHINTECLR) HWUPIE Clear */\r
+#define USBC_UHINTECLR_P0INTEC (0x1u << 8) /**< \brief (USBC_UHINTECLR) P0INTE Clear */\r
+#define USBC_UHINTECLR_P1INTEC (0x1u << 9) /**< \brief (USBC_UHINTECLR) P1INTE Clear */\r
+#define USBC_UHINTECLR_P2INTEC (0x1u << 10) /**< \brief (USBC_UHINTECLR) P2INTE Clear */\r
+#define USBC_UHINTECLR_P3INTEC (0x1u << 11) /**< \brief (USBC_UHINTECLR) P3INTE Clear */\r
+#define USBC_UHINTECLR_P4INTEC (0x1u << 12) /**< \brief (USBC_UHINTECLR) P4INTE Clear */\r
+#define USBC_UHINTECLR_P5INTEC (0x1u << 13) /**< \brief (USBC_UHINTECLR) P5INTE Clear */\r
+#define USBC_UHINTECLR_P6INTEC (0x1u << 14) /**< \brief (USBC_UHINTECLR) P6INTE Clear */\r
+#define USBC_UHINTECLR_P7INTEC (0x1u << 15) /**< \brief (USBC_UHINTECLR) P7INTE Clear */\r
+/* -------- USBC_UHINTESET : (USBC Offset: 0x418) Host Global Interrupt Enable Set Register -------- */\r
+#define USBC_UHINTESET_DCONNIES (0x1u << 0) /**< \brief (USBC_UHINTESET) DCONNIE Set */\r
+#define USBC_UHINTESET_DDISCIES (0x1u << 1) /**< \brief (USBC_UHINTESET) DDISCIE Set */\r
+#define USBC_UHINTESET_RSTIES (0x1u << 2) /**< \brief (USBC_UHINTESET) RSTIE Set */\r
+#define USBC_UHINTESET_RSMEDIES (0x1u << 3) /**< \brief (USBC_UHINTESET) RSMEDIE Set */\r
+#define USBC_UHINTESET_RXRSMIES (0x1u << 4) /**< \brief (USBC_UHINTESET) RXRSMIE Set */\r
+#define USBC_UHINTESET_HSOFIES (0x1u << 5) /**< \brief (USBC_UHINTESET) HSOFIE Set */\r
+#define USBC_UHINTESET_HWUPIES (0x1u << 6) /**< \brief (USBC_UHINTESET) HWUPIE Set */\r
+#define USBC_UHINTESET_P0INTES (0x1u << 8) /**< \brief (USBC_UHINTESET) P0INTE Set */\r
+#define USBC_UHINTESET_P1INTES (0x1u << 9) /**< \brief (USBC_UHINTESET) P1INTE Set */\r
+#define USBC_UHINTESET_P2INTES (0x1u << 10) /**< \brief (USBC_UHINTESET) P2INTE Set */\r
+#define USBC_UHINTESET_P3INTES (0x1u << 11) /**< \brief (USBC_UHINTESET) P3INTE Set */\r
+#define USBC_UHINTESET_P4INTES (0x1u << 12) /**< \brief (USBC_UHINTESET) P4INTE Set */\r
+#define USBC_UHINTESET_P5INTES (0x1u << 13) /**< \brief (USBC_UHINTESET) P5INTE Set */\r
+#define USBC_UHINTESET_P6INTES (0x1u << 14) /**< \brief (USBC_UHINTESET) P6INTE Set */\r
+#define USBC_UHINTESET_P7INTES (0x1u << 15) /**< \brief (USBC_UHINTESET) P7INTE Set */\r
+/* -------- USBC_UPRST : (USBC Offset: 0x41C) Pipe Reset Register -------- */\r
+#define USBC_UPRST_PEN0 (0x1u << 0) /**< \brief (USBC_UPRST) Pipe0 Enable */\r
+#define USBC_UPRST_PEN1 (0x1u << 1) /**< \brief (USBC_UPRST) Pipe1 Enable */\r
+#define USBC_UPRST_PEN2 (0x1u << 2) /**< \brief (USBC_UPRST) Pipe2 Enable */\r
+#define USBC_UPRST_PEN3 (0x1u << 3) /**< \brief (USBC_UPRST) Pipe3 Enable */\r
+#define USBC_UPRST_PEN4 (0x1u << 4) /**< \brief (USBC_UPRST) Pipe4 Enable */\r
+#define USBC_UPRST_PEN5 (0x1u << 5) /**< \brief (USBC_UPRST) Pipe5 Enable */\r
+#define USBC_UPRST_PEN6 (0x1u << 6) /**< \brief (USBC_UPRST) Pipe6 Enable */\r
+#define USBC_UPRST_PEN7 (0x1u << 7) /**< \brief (USBC_UPRST) Pipe7 Enable */\r
+/* -------- USBC_UHFNUM : (USBC Offset: 0x420) Host Frame Number Register -------- */\r
+#define USBC_UHFNUM_MFNUM_Pos 0\r
+#define USBC_UHFNUM_MFNUM_Msk (0x7u << USBC_UHFNUM_MFNUM_Pos) /**< \brief (USBC_UHFNUM) Micro Frame Number */\r
+#define USBC_UHFNUM_MFNUM(value) ((USBC_UHFNUM_MFNUM_Msk & ((value) << USBC_UHFNUM_MFNUM_Pos)))\r
+#define USBC_UHFNUM_FNUM_Pos 3\r
+#define USBC_UHFNUM_FNUM_Msk (0x7FFu << USBC_UHFNUM_FNUM_Pos) /**< \brief (USBC_UHFNUM) Frame Number */\r
+#define USBC_UHFNUM_FNUM(value) ((USBC_UHFNUM_FNUM_Msk & ((value) << USBC_UHFNUM_FNUM_Pos)))\r
+#define USBC_UHFNUM_FLENHIGH_Pos 16\r
+#define USBC_UHFNUM_FLENHIGH_Msk (0xFFu << USBC_UHFNUM_FLENHIGH_Pos) /**< \brief (USBC_UHFNUM) Frame Length */\r
+#define USBC_UHFNUM_FLENHIGH(value) ((USBC_UHFNUM_FLENHIGH_Msk & ((value) << USBC_UHFNUM_FLENHIGH_Pos)))\r
+/* -------- USBC_UHSOFC : (USBC Offset: 0x424) Host Start of Frame Control Register -------- */\r
+#define USBC_UHSOFC_FLENC_Pos 0\r
+#define USBC_UHSOFC_FLENC_Msk (0x3FFFu << USBC_UHSOFC_FLENC_Pos) /**< \brief (USBC_UHSOFC) Frame Length Control */\r
+#define USBC_UHSOFC_FLENC(value) ((USBC_UHSOFC_FLENC_Msk & ((value) << USBC_UHSOFC_FLENC_Pos)))\r
+#define USBC_UHSOFC_FLENCE (0x1u << 16) /**< \brief (USBC_UHSOFC) Frame Length Control Enable */\r
+/* -------- USBC_UPCFG0 : (USBC Offset: 0x500) Pipe Configuration Register -------- */\r
+#define USBC_UPCFG0_PBK (0x1u << 2) /**< \brief (USBC_UPCFG0) Pipe Banks */\r
+#define USBC_UPCFG0_PBK_SINGLE (0x0u << 2) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PSIZE_Pos 4\r
+#define USBC_UPCFG0_PSIZE_Msk (0x7u << USBC_UPCFG0_PSIZE_Pos) /**< \brief (USBC_UPCFG0) Pipe Size */\r
+#define USBC_UPCFG0_PSIZE(value) ((USBC_UPCFG0_PSIZE_Msk & ((value) << USBC_UPCFG0_PSIZE_Pos)))\r
+#define USBC_UPCFG0_PSIZE_8 (0x0u << 4) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PSIZE_16 (0x1u << 4) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PSIZE_32 (0x2u << 4) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PSIZE_64 (0x3u << 4) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PSIZE_128 (0x4u << 4) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PSIZE_256 (0x5u << 4) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PSIZE_512 (0x6u << 4) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PSIZE_1024 (0x7u << 4) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PTOKEN_Pos 8\r
+#define USBC_UPCFG0_PTOKEN_Msk (0x3u << USBC_UPCFG0_PTOKEN_Pos) /**< \brief (USBC_UPCFG0) Pipe Token */\r
+#define USBC_UPCFG0_PTOKEN(value) ((USBC_UPCFG0_PTOKEN_Msk & ((value) << USBC_UPCFG0_PTOKEN_Pos)))\r
+#define USBC_UPCFG0_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PTOKEN_IN (0x1u << 8) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PTOKEN_OUT (0x2u << 8) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PTYPE_Pos 12\r
+#define USBC_UPCFG0_PTYPE_Msk (0x3u << USBC_UPCFG0_PTYPE_Pos) /**< \brief (USBC_UPCFG0) Pipe Type */\r
+#define USBC_UPCFG0_PTYPE(value) ((USBC_UPCFG0_PTYPE_Msk & ((value) << USBC_UPCFG0_PTYPE_Pos)))\r
+#define USBC_UPCFG0_PTYPE_CONTROL (0x0u << 12) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PTYPE_ISOCHRONOUS (0x1u << 12) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PTYPE_BULK (0x2u << 12) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PTYPE_INTERRUPT (0x3u << 12) /**< \brief (USBC_UPCFG0) */\r
+#define USBC_UPCFG0_PINGEN (0x1u << 20) /**< \brief (USBC_UPCFG0) Ping Enable */\r
+#define USBC_UPCFG0_BINTERVAL_Pos 24\r
+#define USBC_UPCFG0_BINTERVAL_Msk (0xFFu << USBC_UPCFG0_BINTERVAL_Pos) /**< \brief (USBC_UPCFG0) binterval parameter */\r
+#define USBC_UPCFG0_BINTERVAL(value) ((USBC_UPCFG0_BINTERVAL_Msk & ((value) << USBC_UPCFG0_BINTERVAL_Pos)))\r
+/* -------- USBC_UPCFG1 : (USBC Offset: 0x504) Pipe Configuration Register -------- */\r
+#define USBC_UPCFG1_PBK (0x1u << 2) /**< \brief (USBC_UPCFG1) Pipe Banks */\r
+#define USBC_UPCFG1_PBK_SINGLE (0x0u << 2) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PSIZE_Pos 4\r
+#define USBC_UPCFG1_PSIZE_Msk (0x7u << USBC_UPCFG1_PSIZE_Pos) /**< \brief (USBC_UPCFG1) Pipe Size */\r
+#define USBC_UPCFG1_PSIZE(value) ((USBC_UPCFG1_PSIZE_Msk & ((value) << USBC_UPCFG1_PSIZE_Pos)))\r
+#define USBC_UPCFG1_PSIZE_8 (0x0u << 4) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PSIZE_16 (0x1u << 4) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PSIZE_32 (0x2u << 4) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PSIZE_64 (0x3u << 4) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PSIZE_128 (0x4u << 4) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PSIZE_256 (0x5u << 4) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PSIZE_512 (0x6u << 4) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PSIZE_1024 (0x7u << 4) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PTOKEN_Pos 8\r
+#define USBC_UPCFG1_PTOKEN_Msk (0x3u << USBC_UPCFG1_PTOKEN_Pos) /**< \brief (USBC_UPCFG1) Pipe Token */\r
+#define USBC_UPCFG1_PTOKEN(value) ((USBC_UPCFG1_PTOKEN_Msk & ((value) << USBC_UPCFG1_PTOKEN_Pos)))\r
+#define USBC_UPCFG1_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PTOKEN_IN (0x1u << 8) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PTOKEN_OUT (0x2u << 8) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PTYPE_Pos 12\r
+#define USBC_UPCFG1_PTYPE_Msk (0x3u << USBC_UPCFG1_PTYPE_Pos) /**< \brief (USBC_UPCFG1) Pipe Type */\r
+#define USBC_UPCFG1_PTYPE(value) ((USBC_UPCFG1_PTYPE_Msk & ((value) << USBC_UPCFG1_PTYPE_Pos)))\r
+#define USBC_UPCFG1_PTYPE_CONTROL (0x0u << 12) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PTYPE_ISOCHRONOUS (0x1u << 12) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PTYPE_BULK (0x2u << 12) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PTYPE_INTERRUPT (0x3u << 12) /**< \brief (USBC_UPCFG1) */\r
+#define USBC_UPCFG1_PINGEN (0x1u << 20) /**< \brief (USBC_UPCFG1) Ping Enable */\r
+#define USBC_UPCFG1_BINTERVAL_Pos 24\r
+#define USBC_UPCFG1_BINTERVAL_Msk (0xFFu << USBC_UPCFG1_BINTERVAL_Pos) /**< \brief (USBC_UPCFG1) binterval parameter */\r
+#define USBC_UPCFG1_BINTERVAL(value) ((USBC_UPCFG1_BINTERVAL_Msk & ((value) << USBC_UPCFG1_BINTERVAL_Pos)))\r
+/* -------- USBC_UPCFG2 : (USBC Offset: 0x508) Pipe Configuration Register -------- */\r
+#define USBC_UPCFG2_PBK (0x1u << 2) /**< \brief (USBC_UPCFG2) Pipe Banks */\r
+#define USBC_UPCFG2_PBK_SINGLE (0x0u << 2) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PSIZE_Pos 4\r
+#define USBC_UPCFG2_PSIZE_Msk (0x7u << USBC_UPCFG2_PSIZE_Pos) /**< \brief (USBC_UPCFG2) Pipe Size */\r
+#define USBC_UPCFG2_PSIZE(value) ((USBC_UPCFG2_PSIZE_Msk & ((value) << USBC_UPCFG2_PSIZE_Pos)))\r
+#define USBC_UPCFG2_PSIZE_8 (0x0u << 4) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PSIZE_16 (0x1u << 4) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PSIZE_32 (0x2u << 4) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PSIZE_64 (0x3u << 4) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PSIZE_128 (0x4u << 4) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PSIZE_256 (0x5u << 4) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PSIZE_512 (0x6u << 4) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PSIZE_1024 (0x7u << 4) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PTOKEN_Pos 8\r
+#define USBC_UPCFG2_PTOKEN_Msk (0x3u << USBC_UPCFG2_PTOKEN_Pos) /**< \brief (USBC_UPCFG2) Pipe Token */\r
+#define USBC_UPCFG2_PTOKEN(value) ((USBC_UPCFG2_PTOKEN_Msk & ((value) << USBC_UPCFG2_PTOKEN_Pos)))\r
+#define USBC_UPCFG2_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PTOKEN_IN (0x1u << 8) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PTOKEN_OUT (0x2u << 8) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PTYPE_Pos 12\r
+#define USBC_UPCFG2_PTYPE_Msk (0x3u << USBC_UPCFG2_PTYPE_Pos) /**< \brief (USBC_UPCFG2) Pipe Type */\r
+#define USBC_UPCFG2_PTYPE(value) ((USBC_UPCFG2_PTYPE_Msk & ((value) << USBC_UPCFG2_PTYPE_Pos)))\r
+#define USBC_UPCFG2_PTYPE_CONTROL (0x0u << 12) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PTYPE_ISOCHRONOUS (0x1u << 12) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PTYPE_BULK (0x2u << 12) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PTYPE_INTERRUPT (0x3u << 12) /**< \brief (USBC_UPCFG2) */\r
+#define USBC_UPCFG2_PINGEN (0x1u << 20) /**< \brief (USBC_UPCFG2) Ping Enable */\r
+#define USBC_UPCFG2_BINTERVAL_Pos 24\r
+#define USBC_UPCFG2_BINTERVAL_Msk (0xFFu << USBC_UPCFG2_BINTERVAL_Pos) /**< \brief (USBC_UPCFG2) binterval parameter */\r
+#define USBC_UPCFG2_BINTERVAL(value) ((USBC_UPCFG2_BINTERVAL_Msk & ((value) << USBC_UPCFG2_BINTERVAL_Pos)))\r
+/* -------- USBC_UPCFG3 : (USBC Offset: 0x50C) Pipe Configuration Register -------- */\r
+#define USBC_UPCFG3_PBK (0x1u << 2) /**< \brief (USBC_UPCFG3) Pipe Banks */\r
+#define USBC_UPCFG3_PBK_SINGLE (0x0u << 2) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PSIZE_Pos 4\r
+#define USBC_UPCFG3_PSIZE_Msk (0x7u << USBC_UPCFG3_PSIZE_Pos) /**< \brief (USBC_UPCFG3) Pipe Size */\r
+#define USBC_UPCFG3_PSIZE(value) ((USBC_UPCFG3_PSIZE_Msk & ((value) << USBC_UPCFG3_PSIZE_Pos)))\r
+#define USBC_UPCFG3_PSIZE_8 (0x0u << 4) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PSIZE_16 (0x1u << 4) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PSIZE_32 (0x2u << 4) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PSIZE_64 (0x3u << 4) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PSIZE_128 (0x4u << 4) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PSIZE_256 (0x5u << 4) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PSIZE_512 (0x6u << 4) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PSIZE_1024 (0x7u << 4) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PTOKEN_Pos 8\r
+#define USBC_UPCFG3_PTOKEN_Msk (0x3u << USBC_UPCFG3_PTOKEN_Pos) /**< \brief (USBC_UPCFG3) Pipe Token */\r
+#define USBC_UPCFG3_PTOKEN(value) ((USBC_UPCFG3_PTOKEN_Msk & ((value) << USBC_UPCFG3_PTOKEN_Pos)))\r
+#define USBC_UPCFG3_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PTOKEN_IN (0x1u << 8) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PTOKEN_OUT (0x2u << 8) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PTYPE_Pos 12\r
+#define USBC_UPCFG3_PTYPE_Msk (0x3u << USBC_UPCFG3_PTYPE_Pos) /**< \brief (USBC_UPCFG3) Pipe Type */\r
+#define USBC_UPCFG3_PTYPE(value) ((USBC_UPCFG3_PTYPE_Msk & ((value) << USBC_UPCFG3_PTYPE_Pos)))\r
+#define USBC_UPCFG3_PTYPE_CONTROL (0x0u << 12) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PTYPE_ISOCHRONOUS (0x1u << 12) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PTYPE_BULK (0x2u << 12) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PTYPE_INTERRUPT (0x3u << 12) /**< \brief (USBC_UPCFG3) */\r
+#define USBC_UPCFG3_PINGEN (0x1u << 20) /**< \brief (USBC_UPCFG3) Ping Enable */\r
+#define USBC_UPCFG3_BINTERVAL_Pos 24\r
+#define USBC_UPCFG3_BINTERVAL_Msk (0xFFu << USBC_UPCFG3_BINTERVAL_Pos) /**< \brief (USBC_UPCFG3) binterval parameter */\r
+#define USBC_UPCFG3_BINTERVAL(value) ((USBC_UPCFG3_BINTERVAL_Msk & ((value) << USBC_UPCFG3_BINTERVAL_Pos)))\r
+/* -------- USBC_UPCFG4 : (USBC Offset: 0x510) Pipe Configuration Register -------- */\r
+#define USBC_UPCFG4_PBK (0x1u << 2) /**< \brief (USBC_UPCFG4) Pipe Banks */\r
+#define USBC_UPCFG4_PBK_SINGLE (0x0u << 2) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PSIZE_Pos 4\r
+#define USBC_UPCFG4_PSIZE_Msk (0x7u << USBC_UPCFG4_PSIZE_Pos) /**< \brief (USBC_UPCFG4) Pipe Size */\r
+#define USBC_UPCFG4_PSIZE(value) ((USBC_UPCFG4_PSIZE_Msk & ((value) << USBC_UPCFG4_PSIZE_Pos)))\r
+#define USBC_UPCFG4_PSIZE_8 (0x0u << 4) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PSIZE_16 (0x1u << 4) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PSIZE_32 (0x2u << 4) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PSIZE_64 (0x3u << 4) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PSIZE_128 (0x4u << 4) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PSIZE_256 (0x5u << 4) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PSIZE_512 (0x6u << 4) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PSIZE_1024 (0x7u << 4) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PTOKEN_Pos 8\r
+#define USBC_UPCFG4_PTOKEN_Msk (0x3u << USBC_UPCFG4_PTOKEN_Pos) /**< \brief (USBC_UPCFG4) Pipe Token */\r
+#define USBC_UPCFG4_PTOKEN(value) ((USBC_UPCFG4_PTOKEN_Msk & ((value) << USBC_UPCFG4_PTOKEN_Pos)))\r
+#define USBC_UPCFG4_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PTOKEN_IN (0x1u << 8) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PTOKEN_OUT (0x2u << 8) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PTYPE_Pos 12\r
+#define USBC_UPCFG4_PTYPE_Msk (0x3u << USBC_UPCFG4_PTYPE_Pos) /**< \brief (USBC_UPCFG4) Pipe Type */\r
+#define USBC_UPCFG4_PTYPE(value) ((USBC_UPCFG4_PTYPE_Msk & ((value) << USBC_UPCFG4_PTYPE_Pos)))\r
+#define USBC_UPCFG4_PTYPE_CONTROL (0x0u << 12) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PTYPE_ISOCHRONOUS (0x1u << 12) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PTYPE_BULK (0x2u << 12) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PTYPE_INTERRUPT (0x3u << 12) /**< \brief (USBC_UPCFG4) */\r
+#define USBC_UPCFG4_PINGEN (0x1u << 20) /**< \brief (USBC_UPCFG4) Ping Enable */\r
+#define USBC_UPCFG4_BINTERVAL_Pos 24\r
+#define USBC_UPCFG4_BINTERVAL_Msk (0xFFu << USBC_UPCFG4_BINTERVAL_Pos) /**< \brief (USBC_UPCFG4) binterval parameter */\r
+#define USBC_UPCFG4_BINTERVAL(value) ((USBC_UPCFG4_BINTERVAL_Msk & ((value) << USBC_UPCFG4_BINTERVAL_Pos)))\r
+/* -------- USBC_UPCFG5 : (USBC Offset: 0x514) Pipe Configuration Register -------- */\r
+#define USBC_UPCFG5_PBK (0x1u << 2) /**< \brief (USBC_UPCFG5) Pipe Banks */\r
+#define USBC_UPCFG5_PBK_SINGLE (0x0u << 2) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PSIZE_Pos 4\r
+#define USBC_UPCFG5_PSIZE_Msk (0x7u << USBC_UPCFG5_PSIZE_Pos) /**< \brief (USBC_UPCFG5) Pipe Size */\r
+#define USBC_UPCFG5_PSIZE(value) ((USBC_UPCFG5_PSIZE_Msk & ((value) << USBC_UPCFG5_PSIZE_Pos)))\r
+#define USBC_UPCFG5_PSIZE_8 (0x0u << 4) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PSIZE_16 (0x1u << 4) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PSIZE_32 (0x2u << 4) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PSIZE_64 (0x3u << 4) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PSIZE_128 (0x4u << 4) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PSIZE_256 (0x5u << 4) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PSIZE_512 (0x6u << 4) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PSIZE_1024 (0x7u << 4) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PTOKEN_Pos 8\r
+#define USBC_UPCFG5_PTOKEN_Msk (0x3u << USBC_UPCFG5_PTOKEN_Pos) /**< \brief (USBC_UPCFG5) Pipe Token */\r
+#define USBC_UPCFG5_PTOKEN(value) ((USBC_UPCFG5_PTOKEN_Msk & ((value) << USBC_UPCFG5_PTOKEN_Pos)))\r
+#define USBC_UPCFG5_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PTOKEN_IN (0x1u << 8) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PTOKEN_OUT (0x2u << 8) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PTYPE_Pos 12\r
+#define USBC_UPCFG5_PTYPE_Msk (0x3u << USBC_UPCFG5_PTYPE_Pos) /**< \brief (USBC_UPCFG5) Pipe Type */\r
+#define USBC_UPCFG5_PTYPE(value) ((USBC_UPCFG5_PTYPE_Msk & ((value) << USBC_UPCFG5_PTYPE_Pos)))\r
+#define USBC_UPCFG5_PTYPE_CONTROL (0x0u << 12) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PTYPE_ISOCHRONOUS (0x1u << 12) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PTYPE_BULK (0x2u << 12) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PTYPE_INTERRUPT (0x3u << 12) /**< \brief (USBC_UPCFG5) */\r
+#define USBC_UPCFG5_PINGEN (0x1u << 20) /**< \brief (USBC_UPCFG5) Ping Enable */\r
+#define USBC_UPCFG5_BINTERVAL_Pos 24\r
+#define USBC_UPCFG5_BINTERVAL_Msk (0xFFu << USBC_UPCFG5_BINTERVAL_Pos) /**< \brief (USBC_UPCFG5) binterval parameter */\r
+#define USBC_UPCFG5_BINTERVAL(value) ((USBC_UPCFG5_BINTERVAL_Msk & ((value) << USBC_UPCFG5_BINTERVAL_Pos)))\r
+/* -------- USBC_UPCFG6 : (USBC Offset: 0x518) Pipe Configuration Register -------- */\r
+#define USBC_UPCFG6_PBK (0x1u << 2) /**< \brief (USBC_UPCFG6) Pipe Banks */\r
+#define USBC_UPCFG6_PBK_SINGLE (0x0u << 2) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PSIZE_Pos 4\r
+#define USBC_UPCFG6_PSIZE_Msk (0x7u << USBC_UPCFG6_PSIZE_Pos) /**< \brief (USBC_UPCFG6) Pipe Size */\r
+#define USBC_UPCFG6_PSIZE(value) ((USBC_UPCFG6_PSIZE_Msk & ((value) << USBC_UPCFG6_PSIZE_Pos)))\r
+#define USBC_UPCFG6_PSIZE_8 (0x0u << 4) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PSIZE_16 (0x1u << 4) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PSIZE_32 (0x2u << 4) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PSIZE_64 (0x3u << 4) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PSIZE_128 (0x4u << 4) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PSIZE_256 (0x5u << 4) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PSIZE_512 (0x6u << 4) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PSIZE_1024 (0x7u << 4) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PTOKEN_Pos 8\r
+#define USBC_UPCFG6_PTOKEN_Msk (0x3u << USBC_UPCFG6_PTOKEN_Pos) /**< \brief (USBC_UPCFG6) Pipe Token */\r
+#define USBC_UPCFG6_PTOKEN(value) ((USBC_UPCFG6_PTOKEN_Msk & ((value) << USBC_UPCFG6_PTOKEN_Pos)))\r
+#define USBC_UPCFG6_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PTOKEN_IN (0x1u << 8) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PTOKEN_OUT (0x2u << 8) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PTYPE_Pos 12\r
+#define USBC_UPCFG6_PTYPE_Msk (0x3u << USBC_UPCFG6_PTYPE_Pos) /**< \brief (USBC_UPCFG6) Pipe Type */\r
+#define USBC_UPCFG6_PTYPE(value) ((USBC_UPCFG6_PTYPE_Msk & ((value) << USBC_UPCFG6_PTYPE_Pos)))\r
+#define USBC_UPCFG6_PTYPE_CONTROL (0x0u << 12) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PTYPE_ISOCHRONOUS (0x1u << 12) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PTYPE_BULK (0x2u << 12) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PTYPE_INTERRUPT (0x3u << 12) /**< \brief (USBC_UPCFG6) */\r
+#define USBC_UPCFG6_PINGEN (0x1u << 20) /**< \brief (USBC_UPCFG6) Ping Enable */\r
+#define USBC_UPCFG6_BINTERVAL_Pos 24\r
+#define USBC_UPCFG6_BINTERVAL_Msk (0xFFu << USBC_UPCFG6_BINTERVAL_Pos) /**< \brief (USBC_UPCFG6) binterval parameter */\r
+#define USBC_UPCFG6_BINTERVAL(value) ((USBC_UPCFG6_BINTERVAL_Msk & ((value) << USBC_UPCFG6_BINTERVAL_Pos)))\r
+/* -------- USBC_UPCFG7 : (USBC Offset: 0x51C) Pipe Configuration Register -------- */\r
+#define USBC_UPCFG7_PBK (0x1u << 2) /**< \brief (USBC_UPCFG7) Pipe Banks */\r
+#define USBC_UPCFG7_PBK_SINGLE (0x0u << 2) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PBK_DOUBLE (0x1u << 2) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PSIZE_Pos 4\r
+#define USBC_UPCFG7_PSIZE_Msk (0x7u << USBC_UPCFG7_PSIZE_Pos) /**< \brief (USBC_UPCFG7) Pipe Size */\r
+#define USBC_UPCFG7_PSIZE(value) ((USBC_UPCFG7_PSIZE_Msk & ((value) << USBC_UPCFG7_PSIZE_Pos)))\r
+#define USBC_UPCFG7_PSIZE_8 (0x0u << 4) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PSIZE_16 (0x1u << 4) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PSIZE_32 (0x2u << 4) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PSIZE_64 (0x3u << 4) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PSIZE_128 (0x4u << 4) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PSIZE_256 (0x5u << 4) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PSIZE_512 (0x6u << 4) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PSIZE_1024 (0x7u << 4) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PTOKEN_Pos 8\r
+#define USBC_UPCFG7_PTOKEN_Msk (0x3u << USBC_UPCFG7_PTOKEN_Pos) /**< \brief (USBC_UPCFG7) Pipe Token */\r
+#define USBC_UPCFG7_PTOKEN(value) ((USBC_UPCFG7_PTOKEN_Msk & ((value) << USBC_UPCFG7_PTOKEN_Pos)))\r
+#define USBC_UPCFG7_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PTOKEN_IN (0x1u << 8) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PTOKEN_OUT (0x2u << 8) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PTYPE_Pos 12\r
+#define USBC_UPCFG7_PTYPE_Msk (0x3u << USBC_UPCFG7_PTYPE_Pos) /**< \brief (USBC_UPCFG7) Pipe Type */\r
+#define USBC_UPCFG7_PTYPE(value) ((USBC_UPCFG7_PTYPE_Msk & ((value) << USBC_UPCFG7_PTYPE_Pos)))\r
+#define USBC_UPCFG7_PTYPE_CONTROL (0x0u << 12) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PTYPE_ISOCHRONOUS (0x1u << 12) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PTYPE_BULK (0x2u << 12) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PTYPE_INTERRUPT (0x3u << 12) /**< \brief (USBC_UPCFG7) */\r
+#define USBC_UPCFG7_PINGEN (0x1u << 20) /**< \brief (USBC_UPCFG7) Ping Enable */\r
+#define USBC_UPCFG7_BINTERVAL_Pos 24\r
+#define USBC_UPCFG7_BINTERVAL_Msk (0xFFu << USBC_UPCFG7_BINTERVAL_Pos) /**< \brief (USBC_UPCFG7) binterval parameter */\r
+#define USBC_UPCFG7_BINTERVAL(value) ((USBC_UPCFG7_BINTERVAL_Msk & ((value) << USBC_UPCFG7_BINTERVAL_Pos)))\r
+/* -------- USBC_UPSTA0 : (USBC Offset: 0x530) Pipe Status Register -------- */\r
+#define USBC_UPSTA0_RXINI (0x1u << 0) /**< \brief (USBC_UPSTA0) Received IN Data Interrupt */\r
+#define USBC_UPSTA0_TXOUTI (0x1u << 1) /**< \brief (USBC_UPSTA0) Transmitted OUT Data Interrupt */\r
+#define USBC_UPSTA0_TXSTPI (0x1u << 2) /**< \brief (USBC_UPSTA0) Transmitted SETUP Interrupt */\r
+#define USBC_UPSTA0_PERRI (0x1u << 3) /**< \brief (USBC_UPSTA0) Pipe Error Interrupt */\r
+#define USBC_UPSTA0_NAKEDI (0x1u << 4) /**< \brief (USBC_UPSTA0) NAKed Interrupt */\r
+#define USBC_UPSTA0_ERRORFI (0x1u << 5) /**< \brief (USBC_UPSTA0) Errorflow Interrupt */\r
+#define USBC_UPSTA0_RXSTALLDI (0x1u << 6) /**< \brief (USBC_UPSTA0) Received STALLed Interrupt */\r
+#define USBC_UPSTA0_DTSEQ_Pos 8\r
+#define USBC_UPSTA0_DTSEQ_Msk (0x3u << USBC_UPSTA0_DTSEQ_Pos) /**< \brief (USBC_UPSTA0) Data Toggle Sequence */\r
+#define USBC_UPSTA0_DTSEQ(value) ((USBC_UPSTA0_DTSEQ_Msk & ((value) << USBC_UPSTA0_DTSEQ_Pos)))\r
+#define USBC_UPSTA0_RAMACERI (0x1u << 10) /**< \brief (USBC_UPSTA0) Ram Access Error Interrupt */\r
+#define USBC_UPSTA0_NBUSYBK_Pos 12\r
+#define USBC_UPSTA0_NBUSYBK_Msk (0x3u << USBC_UPSTA0_NBUSYBK_Pos) /**< \brief (USBC_UPSTA0) Number of Busy Bank */\r
+#define USBC_UPSTA0_NBUSYBK(value) ((USBC_UPSTA0_NBUSYBK_Msk & ((value) << USBC_UPSTA0_NBUSYBK_Pos)))\r
+#define USBC_UPSTA0_CURRBK_Pos 14\r
+#define USBC_UPSTA0_CURRBK_Msk (0x3u << USBC_UPSTA0_CURRBK_Pos) /**< \brief (USBC_UPSTA0) Current Bank */\r
+#define USBC_UPSTA0_CURRBK(value) ((USBC_UPSTA0_CURRBK_Msk & ((value) << USBC_UPSTA0_CURRBK_Pos)))\r
+/* -------- USBC_UPSTA1 : (USBC Offset: 0x534) Pipe Status Register -------- */\r
+#define USBC_UPSTA1_RXINI (0x1u << 0) /**< \brief (USBC_UPSTA1) Received IN Data Interrupt */\r
+#define USBC_UPSTA1_TXOUTI (0x1u << 1) /**< \brief (USBC_UPSTA1) Transmitted OUT Data Interrupt */\r
+#define USBC_UPSTA1_TXSTPI (0x1u << 2) /**< \brief (USBC_UPSTA1) Transmitted SETUP Interrupt */\r
+#define USBC_UPSTA1_PERRI (0x1u << 3) /**< \brief (USBC_UPSTA1) Pipe Error Interrupt */\r
+#define USBC_UPSTA1_NAKEDI (0x1u << 4) /**< \brief (USBC_UPSTA1) NAKed Interrupt */\r
+#define USBC_UPSTA1_ERRORFI (0x1u << 5) /**< \brief (USBC_UPSTA1) Errorflow Interrupt */\r
+#define USBC_UPSTA1_RXSTALLDI (0x1u << 6) /**< \brief (USBC_UPSTA1) Received STALLed Interrupt */\r
+#define USBC_UPSTA1_DTSEQ_Pos 8\r
+#define USBC_UPSTA1_DTSEQ_Msk (0x3u << USBC_UPSTA1_DTSEQ_Pos) /**< \brief (USBC_UPSTA1) Data Toggle Sequence */\r
+#define USBC_UPSTA1_DTSEQ(value) ((USBC_UPSTA1_DTSEQ_Msk & ((value) << USBC_UPSTA1_DTSEQ_Pos)))\r
+#define USBC_UPSTA1_RAMACERI (0x1u << 10) /**< \brief (USBC_UPSTA1) Ram Access Error Interrupt */\r
+#define USBC_UPSTA1_NBUSYBK_Pos 12\r
+#define USBC_UPSTA1_NBUSYBK_Msk (0x3u << USBC_UPSTA1_NBUSYBK_Pos) /**< \brief (USBC_UPSTA1) Number of Busy Bank */\r
+#define USBC_UPSTA1_NBUSYBK(value) ((USBC_UPSTA1_NBUSYBK_Msk & ((value) << USBC_UPSTA1_NBUSYBK_Pos)))\r
+#define USBC_UPSTA1_CURRBK_Pos 14\r
+#define USBC_UPSTA1_CURRBK_Msk (0x3u << USBC_UPSTA1_CURRBK_Pos) /**< \brief (USBC_UPSTA1) Current Bank */\r
+#define USBC_UPSTA1_CURRBK(value) ((USBC_UPSTA1_CURRBK_Msk & ((value) << USBC_UPSTA1_CURRBK_Pos)))\r
+/* -------- USBC_UPSTA2 : (USBC Offset: 0x538) Pipe Status Register -------- */\r
+#define USBC_UPSTA2_RXINI (0x1u << 0) /**< \brief (USBC_UPSTA2) Received IN Data Interrupt */\r
+#define USBC_UPSTA2_TXOUTI (0x1u << 1) /**< \brief (USBC_UPSTA2) Transmitted OUT Data Interrupt */\r
+#define USBC_UPSTA2_TXSTPI (0x1u << 2) /**< \brief (USBC_UPSTA2) Transmitted SETUP Interrupt */\r
+#define USBC_UPSTA2_PERRI (0x1u << 3) /**< \brief (USBC_UPSTA2) Pipe Error Interrupt */\r
+#define USBC_UPSTA2_NAKEDI (0x1u << 4) /**< \brief (USBC_UPSTA2) NAKed Interrupt */\r
+#define USBC_UPSTA2_ERRORFI (0x1u << 5) /**< \brief (USBC_UPSTA2) Errorflow Interrupt */\r
+#define USBC_UPSTA2_RXSTALLDI (0x1u << 6) /**< \brief (USBC_UPSTA2) Received STALLed Interrupt */\r
+#define USBC_UPSTA2_DTSEQ_Pos 8\r
+#define USBC_UPSTA2_DTSEQ_Msk (0x3u << USBC_UPSTA2_DTSEQ_Pos) /**< \brief (USBC_UPSTA2) Data Toggle Sequence */\r
+#define USBC_UPSTA2_DTSEQ(value) ((USBC_UPSTA2_DTSEQ_Msk & ((value) << USBC_UPSTA2_DTSEQ_Pos)))\r
+#define USBC_UPSTA2_RAMACERI (0x1u << 10) /**< \brief (USBC_UPSTA2) Ram Access Error Interrupt */\r
+#define USBC_UPSTA2_NBUSYBK_Pos 12\r
+#define USBC_UPSTA2_NBUSYBK_Msk (0x3u << USBC_UPSTA2_NBUSYBK_Pos) /**< \brief (USBC_UPSTA2) Number of Busy Bank */\r
+#define USBC_UPSTA2_NBUSYBK(value) ((USBC_UPSTA2_NBUSYBK_Msk & ((value) << USBC_UPSTA2_NBUSYBK_Pos)))\r
+#define USBC_UPSTA2_CURRBK_Pos 14\r
+#define USBC_UPSTA2_CURRBK_Msk (0x3u << USBC_UPSTA2_CURRBK_Pos) /**< \brief (USBC_UPSTA2) Current Bank */\r
+#define USBC_UPSTA2_CURRBK(value) ((USBC_UPSTA2_CURRBK_Msk & ((value) << USBC_UPSTA2_CURRBK_Pos)))\r
+/* -------- USBC_UPSTA3 : (USBC Offset: 0x53C) Pipe Status Register -------- */\r
+#define USBC_UPSTA3_RXINI (0x1u << 0) /**< \brief (USBC_UPSTA3) Received IN Data Interrupt */\r
+#define USBC_UPSTA3_TXOUTI (0x1u << 1) /**< \brief (USBC_UPSTA3) Transmitted OUT Data Interrupt */\r
+#define USBC_UPSTA3_TXSTPI (0x1u << 2) /**< \brief (USBC_UPSTA3) Transmitted SETUP Interrupt */\r
+#define USBC_UPSTA3_PERRI (0x1u << 3) /**< \brief (USBC_UPSTA3) Pipe Error Interrupt */\r
+#define USBC_UPSTA3_NAKEDI (0x1u << 4) /**< \brief (USBC_UPSTA3) NAKed Interrupt */\r
+#define USBC_UPSTA3_ERRORFI (0x1u << 5) /**< \brief (USBC_UPSTA3) Errorflow Interrupt */\r
+#define USBC_UPSTA3_RXSTALLDI (0x1u << 6) /**< \brief (USBC_UPSTA3) Received STALLed Interrupt */\r
+#define USBC_UPSTA3_DTSEQ_Pos 8\r
+#define USBC_UPSTA3_DTSEQ_Msk (0x3u << USBC_UPSTA3_DTSEQ_Pos) /**< \brief (USBC_UPSTA3) Data Toggle Sequence */\r
+#define USBC_UPSTA3_DTSEQ(value) ((USBC_UPSTA3_DTSEQ_Msk & ((value) << USBC_UPSTA3_DTSEQ_Pos)))\r
+#define USBC_UPSTA3_RAMACERI (0x1u << 10) /**< \brief (USBC_UPSTA3) Ram Access Error Interrupt */\r
+#define USBC_UPSTA3_NBUSYBK_Pos 12\r
+#define USBC_UPSTA3_NBUSYBK_Msk (0x3u << USBC_UPSTA3_NBUSYBK_Pos) /**< \brief (USBC_UPSTA3) Number of Busy Bank */\r
+#define USBC_UPSTA3_NBUSYBK(value) ((USBC_UPSTA3_NBUSYBK_Msk & ((value) << USBC_UPSTA3_NBUSYBK_Pos)))\r
+#define USBC_UPSTA3_CURRBK_Pos 14\r
+#define USBC_UPSTA3_CURRBK_Msk (0x3u << USBC_UPSTA3_CURRBK_Pos) /**< \brief (USBC_UPSTA3) Current Bank */\r
+#define USBC_UPSTA3_CURRBK(value) ((USBC_UPSTA3_CURRBK_Msk & ((value) << USBC_UPSTA3_CURRBK_Pos)))\r
+/* -------- USBC_UPSTA4 : (USBC Offset: 0x540) Pipe Status Register -------- */\r
+#define USBC_UPSTA4_RXINI (0x1u << 0) /**< \brief (USBC_UPSTA4) Received IN Data Interrupt */\r
+#define USBC_UPSTA4_TXOUTI (0x1u << 1) /**< \brief (USBC_UPSTA4) Transmitted OUT Data Interrupt */\r
+#define USBC_UPSTA4_TXSTPI (0x1u << 2) /**< \brief (USBC_UPSTA4) Transmitted SETUP Interrupt */\r
+#define USBC_UPSTA4_PERRI (0x1u << 3) /**< \brief (USBC_UPSTA4) Pipe Error Interrupt */\r
+#define USBC_UPSTA4_NAKEDI (0x1u << 4) /**< \brief (USBC_UPSTA4) NAKed Interrupt */\r
+#define USBC_UPSTA4_ERRORFI (0x1u << 5) /**< \brief (USBC_UPSTA4) Errorflow Interrupt */\r
+#define USBC_UPSTA4_RXSTALLDI (0x1u << 6) /**< \brief (USBC_UPSTA4) Received STALLed Interrupt */\r
+#define USBC_UPSTA4_DTSEQ_Pos 8\r
+#define USBC_UPSTA4_DTSEQ_Msk (0x3u << USBC_UPSTA4_DTSEQ_Pos) /**< \brief (USBC_UPSTA4) Data Toggle Sequence */\r
+#define USBC_UPSTA4_DTSEQ(value) ((USBC_UPSTA4_DTSEQ_Msk & ((value) << USBC_UPSTA4_DTSEQ_Pos)))\r
+#define USBC_UPSTA4_RAMACERI (0x1u << 10) /**< \brief (USBC_UPSTA4) Ram Access Error Interrupt */\r
+#define USBC_UPSTA4_NBUSYBK_Pos 12\r
+#define USBC_UPSTA4_NBUSYBK_Msk (0x3u << USBC_UPSTA4_NBUSYBK_Pos) /**< \brief (USBC_UPSTA4) Number of Busy Bank */\r
+#define USBC_UPSTA4_NBUSYBK(value) ((USBC_UPSTA4_NBUSYBK_Msk & ((value) << USBC_UPSTA4_NBUSYBK_Pos)))\r
+#define USBC_UPSTA4_CURRBK_Pos 14\r
+#define USBC_UPSTA4_CURRBK_Msk (0x3u << USBC_UPSTA4_CURRBK_Pos) /**< \brief (USBC_UPSTA4) Current Bank */\r
+#define USBC_UPSTA4_CURRBK(value) ((USBC_UPSTA4_CURRBK_Msk & ((value) << USBC_UPSTA4_CURRBK_Pos)))\r
+/* -------- USBC_UPSTA5 : (USBC Offset: 0x544) Pipe Status Register -------- */\r
+#define USBC_UPSTA5_RXINI (0x1u << 0) /**< \brief (USBC_UPSTA5) Received IN Data Interrupt */\r
+#define USBC_UPSTA5_TXOUTI (0x1u << 1) /**< \brief (USBC_UPSTA5) Transmitted OUT Data Interrupt */\r
+#define USBC_UPSTA5_TXSTPI (0x1u << 2) /**< \brief (USBC_UPSTA5) Transmitted SETUP Interrupt */\r
+#define USBC_UPSTA5_PERRI (0x1u << 3) /**< \brief (USBC_UPSTA5) Pipe Error Interrupt */\r
+#define USBC_UPSTA5_NAKEDI (0x1u << 4) /**< \brief (USBC_UPSTA5) NAKed Interrupt */\r
+#define USBC_UPSTA5_ERRORFI (0x1u << 5) /**< \brief (USBC_UPSTA5) Errorflow Interrupt */\r
+#define USBC_UPSTA5_RXSTALLDI (0x1u << 6) /**< \brief (USBC_UPSTA5) Received STALLed Interrupt */\r
+#define USBC_UPSTA5_DTSEQ_Pos 8\r
+#define USBC_UPSTA5_DTSEQ_Msk (0x3u << USBC_UPSTA5_DTSEQ_Pos) /**< \brief (USBC_UPSTA5) Data Toggle Sequence */\r
+#define USBC_UPSTA5_DTSEQ(value) ((USBC_UPSTA5_DTSEQ_Msk & ((value) << USBC_UPSTA5_DTSEQ_Pos)))\r
+#define USBC_UPSTA5_RAMACERI (0x1u << 10) /**< \brief (USBC_UPSTA5) Ram Access Error Interrupt */\r
+#define USBC_UPSTA5_NBUSYBK_Pos 12\r
+#define USBC_UPSTA5_NBUSYBK_Msk (0x3u << USBC_UPSTA5_NBUSYBK_Pos) /**< \brief (USBC_UPSTA5) Number of Busy Bank */\r
+#define USBC_UPSTA5_NBUSYBK(value) ((USBC_UPSTA5_NBUSYBK_Msk & ((value) << USBC_UPSTA5_NBUSYBK_Pos)))\r
+#define USBC_UPSTA5_CURRBK_Pos 14\r
+#define USBC_UPSTA5_CURRBK_Msk (0x3u << USBC_UPSTA5_CURRBK_Pos) /**< \brief (USBC_UPSTA5) Current Bank */\r
+#define USBC_UPSTA5_CURRBK(value) ((USBC_UPSTA5_CURRBK_Msk & ((value) << USBC_UPSTA5_CURRBK_Pos)))\r
+/* -------- USBC_UPSTA6 : (USBC Offset: 0x548) Pipe Status Register -------- */\r
+#define USBC_UPSTA6_RXINI (0x1u << 0) /**< \brief (USBC_UPSTA6) Received IN Data Interrupt */\r
+#define USBC_UPSTA6_TXOUTI (0x1u << 1) /**< \brief (USBC_UPSTA6) Transmitted OUT Data Interrupt */\r
+#define USBC_UPSTA6_TXSTPI (0x1u << 2) /**< \brief (USBC_UPSTA6) Transmitted SETUP Interrupt */\r
+#define USBC_UPSTA6_PERRI (0x1u << 3) /**< \brief (USBC_UPSTA6) Pipe Error Interrupt */\r
+#define USBC_UPSTA6_NAKEDI (0x1u << 4) /**< \brief (USBC_UPSTA6) NAKed Interrupt */\r
+#define USBC_UPSTA6_ERRORFI (0x1u << 5) /**< \brief (USBC_UPSTA6) Errorflow Interrupt */\r
+#define USBC_UPSTA6_RXSTALLDI (0x1u << 6) /**< \brief (USBC_UPSTA6) Received STALLed Interrupt */\r
+#define USBC_UPSTA6_DTSEQ_Pos 8\r
+#define USBC_UPSTA6_DTSEQ_Msk (0x3u << USBC_UPSTA6_DTSEQ_Pos) /**< \brief (USBC_UPSTA6) Data Toggle Sequence */\r
+#define USBC_UPSTA6_DTSEQ(value) ((USBC_UPSTA6_DTSEQ_Msk & ((value) << USBC_UPSTA6_DTSEQ_Pos)))\r
+#define USBC_UPSTA6_RAMACERI (0x1u << 10) /**< \brief (USBC_UPSTA6) Ram Access Error Interrupt */\r
+#define USBC_UPSTA6_NBUSYBK_Pos 12\r
+#define USBC_UPSTA6_NBUSYBK_Msk (0x3u << USBC_UPSTA6_NBUSYBK_Pos) /**< \brief (USBC_UPSTA6) Number of Busy Bank */\r
+#define USBC_UPSTA6_NBUSYBK(value) ((USBC_UPSTA6_NBUSYBK_Msk & ((value) << USBC_UPSTA6_NBUSYBK_Pos)))\r
+#define USBC_UPSTA6_CURRBK_Pos 14\r
+#define USBC_UPSTA6_CURRBK_Msk (0x3u << USBC_UPSTA6_CURRBK_Pos) /**< \brief (USBC_UPSTA6) Current Bank */\r
+#define USBC_UPSTA6_CURRBK(value) ((USBC_UPSTA6_CURRBK_Msk & ((value) << USBC_UPSTA6_CURRBK_Pos)))\r
+/* -------- USBC_UPSTA7 : (USBC Offset: 0x54C) Pipe Status Register -------- */\r
+#define USBC_UPSTA7_RXINI (0x1u << 0) /**< \brief (USBC_UPSTA7) Received IN Data Interrupt */\r
+#define USBC_UPSTA7_TXOUTI (0x1u << 1) /**< \brief (USBC_UPSTA7) Transmitted OUT Data Interrupt */\r
+#define USBC_UPSTA7_TXSTPI (0x1u << 2) /**< \brief (USBC_UPSTA7) Transmitted SETUP Interrupt */\r
+#define USBC_UPSTA7_PERRI (0x1u << 3) /**< \brief (USBC_UPSTA7) Pipe Error Interrupt */\r
+#define USBC_UPSTA7_NAKEDI (0x1u << 4) /**< \brief (USBC_UPSTA7) NAKed Interrupt */\r
+#define USBC_UPSTA7_ERRORFI (0x1u << 5) /**< \brief (USBC_UPSTA7) Errorflow Interrupt */\r
+#define USBC_UPSTA7_RXSTALLDI (0x1u << 6) /**< \brief (USBC_UPSTA7) Received STALLed Interrupt */\r
+#define USBC_UPSTA7_DTSEQ_Pos 8\r
+#define USBC_UPSTA7_DTSEQ_Msk (0x3u << USBC_UPSTA7_DTSEQ_Pos) /**< \brief (USBC_UPSTA7) Data Toggle Sequence */\r
+#define USBC_UPSTA7_DTSEQ(value) ((USBC_UPSTA7_DTSEQ_Msk & ((value) << USBC_UPSTA7_DTSEQ_Pos)))\r
+#define USBC_UPSTA7_RAMACERI (0x1u << 10) /**< \brief (USBC_UPSTA7) Ram Access Error Interrupt */\r
+#define USBC_UPSTA7_NBUSYBK_Pos 12\r
+#define USBC_UPSTA7_NBUSYBK_Msk (0x3u << USBC_UPSTA7_NBUSYBK_Pos) /**< \brief (USBC_UPSTA7) Number of Busy Bank */\r
+#define USBC_UPSTA7_NBUSYBK(value) ((USBC_UPSTA7_NBUSYBK_Msk & ((value) << USBC_UPSTA7_NBUSYBK_Pos)))\r
+#define USBC_UPSTA7_CURRBK_Pos 14\r
+#define USBC_UPSTA7_CURRBK_Msk (0x3u << USBC_UPSTA7_CURRBK_Pos) /**< \brief (USBC_UPSTA7) Current Bank */\r
+#define USBC_UPSTA7_CURRBK(value) ((USBC_UPSTA7_CURRBK_Msk & ((value) << USBC_UPSTA7_CURRBK_Pos)))\r
+/* -------- USBC_UPSTA0CLR : (USBC Offset: 0x560) Pipe Status Clear Register -------- */\r
+#define USBC_UPSTA0CLR_RXINIC (0x1u << 0) /**< \brief (USBC_UPSTA0CLR) RXINI Clear */\r
+#define USBC_UPSTA0CLR_TXOUTIC (0x1u << 1) /**< \brief (USBC_UPSTA0CLR) TXOUTI Clear */\r
+#define USBC_UPSTA0CLR_TXSTPIC (0x1u << 2) /**< \brief (USBC_UPSTA0CLR) TXSTPI Clear */\r
+#define USBC_UPSTA0CLR_PERRIC (0x1u << 3) /**< \brief (USBC_UPSTA0CLR) PERRI Clear */\r
+#define USBC_UPSTA0CLR_NAKEDIC (0x1u << 4) /**< \brief (USBC_UPSTA0CLR) NAKEDI Clear */\r
+#define USBC_UPSTA0CLR_ERRORFIC (0x1u << 5) /**< \brief (USBC_UPSTA0CLR) ERRORFI Clear */\r
+#define USBC_UPSTA0CLR_RXSTALLDIC (0x1u << 6) /**< \brief (USBC_UPSTA0CLR) RXSTALLDI Clear */\r
+#define USBC_UPSTA0CLR_RAMACERIC (0x1u << 10) /**< \brief (USBC_UPSTA0CLR) RAMACERI Clear */\r
+/* -------- USBC_UPSTA1CLR : (USBC Offset: 0x564) Pipe Status Clear Register -------- */\r
+#define USBC_UPSTA1CLR_RXINIC (0x1u << 0) /**< \brief (USBC_UPSTA1CLR) RXINI Clear */\r
+#define USBC_UPSTA1CLR_TXOUTIC (0x1u << 1) /**< \brief (USBC_UPSTA1CLR) TXOUTI Clear */\r
+#define USBC_UPSTA1CLR_TXSTPIC (0x1u << 2) /**< \brief (USBC_UPSTA1CLR) TXSTPI Clear */\r
+#define USBC_UPSTA1CLR_PERRIC (0x1u << 3) /**< \brief (USBC_UPSTA1CLR) PERRI Clear */\r
+#define USBC_UPSTA1CLR_NAKEDIC (0x1u << 4) /**< \brief (USBC_UPSTA1CLR) NAKEDI Clear */\r
+#define USBC_UPSTA1CLR_ERRORFIC (0x1u << 5) /**< \brief (USBC_UPSTA1CLR) ERRORFI Clear */\r
+#define USBC_UPSTA1CLR_RXSTALLDIC (0x1u << 6) /**< \brief (USBC_UPSTA1CLR) RXSTALLDI Clear */\r
+#define USBC_UPSTA1CLR_RAMACERIC (0x1u << 10) /**< \brief (USBC_UPSTA1CLR) RAMACERI Clear */\r
+/* -------- USBC_UPSTA2CLR : (USBC Offset: 0x568) Pipe Status Clear Register -------- */\r
+#define USBC_UPSTA2CLR_RXINIC (0x1u << 0) /**< \brief (USBC_UPSTA2CLR) RXINI Clear */\r
+#define USBC_UPSTA2CLR_TXOUTIC (0x1u << 1) /**< \brief (USBC_UPSTA2CLR) TXOUTI Clear */\r
+#define USBC_UPSTA2CLR_TXSTPIC (0x1u << 2) /**< \brief (USBC_UPSTA2CLR) TXSTPI Clear */\r
+#define USBC_UPSTA2CLR_PERRIC (0x1u << 3) /**< \brief (USBC_UPSTA2CLR) PERRI Clear */\r
+#define USBC_UPSTA2CLR_NAKEDIC (0x1u << 4) /**< \brief (USBC_UPSTA2CLR) NAKEDI Clear */\r
+#define USBC_UPSTA2CLR_ERRORFIC (0x1u << 5) /**< \brief (USBC_UPSTA2CLR) ERRORFI Clear */\r
+#define USBC_UPSTA2CLR_RXSTALLDIC (0x1u << 6) /**< \brief (USBC_UPSTA2CLR) RXSTALLDI Clear */\r
+#define USBC_UPSTA2CLR_RAMACERIC (0x1u << 10) /**< \brief (USBC_UPSTA2CLR) RAMACERI Clear */\r
+/* -------- USBC_UPSTA3CLR : (USBC Offset: 0x56C) Pipe Status Clear Register -------- */\r
+#define USBC_UPSTA3CLR_RXINIC (0x1u << 0) /**< \brief (USBC_UPSTA3CLR) RXINI Clear */\r
+#define USBC_UPSTA3CLR_TXOUTIC (0x1u << 1) /**< \brief (USBC_UPSTA3CLR) TXOUTI Clear */\r
+#define USBC_UPSTA3CLR_TXSTPIC (0x1u << 2) /**< \brief (USBC_UPSTA3CLR) TXSTPI Clear */\r
+#define USBC_UPSTA3CLR_PERRIC (0x1u << 3) /**< \brief (USBC_UPSTA3CLR) PERRI Clear */\r
+#define USBC_UPSTA3CLR_NAKEDIC (0x1u << 4) /**< \brief (USBC_UPSTA3CLR) NAKEDI Clear */\r
+#define USBC_UPSTA3CLR_ERRORFIC (0x1u << 5) /**< \brief (USBC_UPSTA3CLR) ERRORFI Clear */\r
+#define USBC_UPSTA3CLR_RXSTALLDIC (0x1u << 6) /**< \brief (USBC_UPSTA3CLR) RXSTALLDI Clear */\r
+#define USBC_UPSTA3CLR_RAMACERIC (0x1u << 10) /**< \brief (USBC_UPSTA3CLR) RAMACERI Clear */\r
+/* -------- USBC_UPSTA4CLR : (USBC Offset: 0x570) Pipe Status Clear Register -------- */\r
+#define USBC_UPSTA4CLR_RXINIC (0x1u << 0) /**< \brief (USBC_UPSTA4CLR) RXINI Clear */\r
+#define USBC_UPSTA4CLR_TXOUTIC (0x1u << 1) /**< \brief (USBC_UPSTA4CLR) TXOUTI Clear */\r
+#define USBC_UPSTA4CLR_TXSTPIC (0x1u << 2) /**< \brief (USBC_UPSTA4CLR) TXSTPI Clear */\r
+#define USBC_UPSTA4CLR_PERRIC (0x1u << 3) /**< \brief (USBC_UPSTA4CLR) PERRI Clear */\r
+#define USBC_UPSTA4CLR_NAKEDIC (0x1u << 4) /**< \brief (USBC_UPSTA4CLR) NAKEDI Clear */\r
+#define USBC_UPSTA4CLR_ERRORFIC (0x1u << 5) /**< \brief (USBC_UPSTA4CLR) ERRORFI Clear */\r
+#define USBC_UPSTA4CLR_RXSTALLDIC (0x1u << 6) /**< \brief (USBC_UPSTA4CLR) RXSTALLDI Clear */\r
+#define USBC_UPSTA4CLR_RAMACERIC (0x1u << 10) /**< \brief (USBC_UPSTA4CLR) RAMACERI Clear */\r
+/* -------- USBC_UPSTA5CLR : (USBC Offset: 0x574) Pipe Status Clear Register -------- */\r
+#define USBC_UPSTA5CLR_RXINIC (0x1u << 0) /**< \brief (USBC_UPSTA5CLR) RXINI Clear */\r
+#define USBC_UPSTA5CLR_TXOUTIC (0x1u << 1) /**< \brief (USBC_UPSTA5CLR) TXOUTI Clear */\r
+#define USBC_UPSTA5CLR_TXSTPIC (0x1u << 2) /**< \brief (USBC_UPSTA5CLR) TXSTPI Clear */\r
+#define USBC_UPSTA5CLR_PERRIC (0x1u << 3) /**< \brief (USBC_UPSTA5CLR) PERRI Clear */\r
+#define USBC_UPSTA5CLR_NAKEDIC (0x1u << 4) /**< \brief (USBC_UPSTA5CLR) NAKEDI Clear */\r
+#define USBC_UPSTA5CLR_ERRORFIC (0x1u << 5) /**< \brief (USBC_UPSTA5CLR) ERRORFI Clear */\r
+#define USBC_UPSTA5CLR_RXSTALLDIC (0x1u << 6) /**< \brief (USBC_UPSTA5CLR) RXSTALLDI Clear */\r
+#define USBC_UPSTA5CLR_RAMACERIC (0x1u << 10) /**< \brief (USBC_UPSTA5CLR) RAMACERI Clear */\r
+/* -------- USBC_UPSTA6CLR : (USBC Offset: 0x578) Pipe Status Clear Register -------- */\r
+#define USBC_UPSTA6CLR_RXINIC (0x1u << 0) /**< \brief (USBC_UPSTA6CLR) RXINI Clear */\r
+#define USBC_UPSTA6CLR_TXOUTIC (0x1u << 1) /**< \brief (USBC_UPSTA6CLR) TXOUTI Clear */\r
+#define USBC_UPSTA6CLR_TXSTPIC (0x1u << 2) /**< \brief (USBC_UPSTA6CLR) TXSTPI Clear */\r
+#define USBC_UPSTA6CLR_PERRIC (0x1u << 3) /**< \brief (USBC_UPSTA6CLR) PERRI Clear */\r
+#define USBC_UPSTA6CLR_NAKEDIC (0x1u << 4) /**< \brief (USBC_UPSTA6CLR) NAKEDI Clear */\r
+#define USBC_UPSTA6CLR_ERRORFIC (0x1u << 5) /**< \brief (USBC_UPSTA6CLR) ERRORFI Clear */\r
+#define USBC_UPSTA6CLR_RXSTALLDIC (0x1u << 6) /**< \brief (USBC_UPSTA6CLR) RXSTALLDI Clear */\r
+#define USBC_UPSTA6CLR_RAMACERIC (0x1u << 10) /**< \brief (USBC_UPSTA6CLR) RAMACERI Clear */\r
+/* -------- USBC_UPSTA7CLR : (USBC Offset: 0x57C) Pipe Status Clear Register -------- */\r
+#define USBC_UPSTA7CLR_RXINIC (0x1u << 0) /**< \brief (USBC_UPSTA7CLR) RXINI Clear */\r
+#define USBC_UPSTA7CLR_TXOUTIC (0x1u << 1) /**< \brief (USBC_UPSTA7CLR) TXOUTI Clear */\r
+#define USBC_UPSTA7CLR_TXSTPIC (0x1u << 2) /**< \brief (USBC_UPSTA7CLR) TXSTPI Clear */\r
+#define USBC_UPSTA7CLR_PERRIC (0x1u << 3) /**< \brief (USBC_UPSTA7CLR) PERRI Clear */\r
+#define USBC_UPSTA7CLR_NAKEDIC (0x1u << 4) /**< \brief (USBC_UPSTA7CLR) NAKEDI Clear */\r
+#define USBC_UPSTA7CLR_ERRORFIC (0x1u << 5) /**< \brief (USBC_UPSTA7CLR) ERRORFI Clear */\r
+#define USBC_UPSTA7CLR_RXSTALLDIC (0x1u << 6) /**< \brief (USBC_UPSTA7CLR) RXSTALLDI Clear */\r
+#define USBC_UPSTA7CLR_RAMACERIC (0x1u << 10) /**< \brief (USBC_UPSTA7CLR) RAMACERI Clear */\r
+/* -------- USBC_UPSTA0SET : (USBC Offset: 0x590) Pipe Status Set Register -------- */\r
+#define USBC_UPSTA0SET_RXINIS (0x1u << 0) /**< \brief (USBC_UPSTA0SET) RXINI Set */\r
+#define USBC_UPSTA0SET_TXOUTIS (0x1u << 1) /**< \brief (USBC_UPSTA0SET) TXOUTI Set */\r
+#define USBC_UPSTA0SET_TXSTPIS (0x1u << 2) /**< \brief (USBC_UPSTA0SET) TXSTPI Set */\r
+#define USBC_UPSTA0SET_PERRIS (0x1u << 3) /**< \brief (USBC_UPSTA0SET) PERRI Set */\r
+#define USBC_UPSTA0SET_NAKEDIS (0x1u << 4) /**< \brief (USBC_UPSTA0SET) NAKEDI Set */\r
+#define USBC_UPSTA0SET_ERRORFIS (0x1u << 5) /**< \brief (USBC_UPSTA0SET) ERRORFI Set */\r
+#define USBC_UPSTA0SET_RXSTALLDIS (0x1u << 6) /**< \brief (USBC_UPSTA0SET) RXSTALLDI Set */\r
+#define USBC_UPSTA0SET_RAMACERIS (0x1u << 10) /**< \brief (USBC_UPSTA0SET) RAMACERI Set */\r
+/* -------- USBC_UPSTA1SET : (USBC Offset: 0x594) Pipe Status Set Register -------- */\r
+#define USBC_UPSTA1SET_RXINIS (0x1u << 0) /**< \brief (USBC_UPSTA1SET) RXINI Set */\r
+#define USBC_UPSTA1SET_TXOUTIS (0x1u << 1) /**< \brief (USBC_UPSTA1SET) TXOUTI Set */\r
+#define USBC_UPSTA1SET_TXSTPIS (0x1u << 2) /**< \brief (USBC_UPSTA1SET) TXSTPI Set */\r
+#define USBC_UPSTA1SET_PERRIS (0x1u << 3) /**< \brief (USBC_UPSTA1SET) PERRI Set */\r
+#define USBC_UPSTA1SET_NAKEDIS (0x1u << 4) /**< \brief (USBC_UPSTA1SET) NAKEDI Set */\r
+#define USBC_UPSTA1SET_ERRORFIS (0x1u << 5) /**< \brief (USBC_UPSTA1SET) ERRORFI Set */\r
+#define USBC_UPSTA1SET_RXSTALLDIS (0x1u << 6) /**< \brief (USBC_UPSTA1SET) RXSTALLDI Set */\r
+#define USBC_UPSTA1SET_RAMACERIS (0x1u << 10) /**< \brief (USBC_UPSTA1SET) RAMACERI Set */\r
+/* -------- USBC_UPSTA2SET : (USBC Offset: 0x598) Pipe Status Set Register -------- */\r
+#define USBC_UPSTA2SET_RXINIS (0x1u << 0) /**< \brief (USBC_UPSTA2SET) RXINI Set */\r
+#define USBC_UPSTA2SET_TXOUTIS (0x1u << 1) /**< \brief (USBC_UPSTA2SET) TXOUTI Set */\r
+#define USBC_UPSTA2SET_TXSTPIS (0x1u << 2) /**< \brief (USBC_UPSTA2SET) TXSTPI Set */\r
+#define USBC_UPSTA2SET_PERRIS (0x1u << 3) /**< \brief (USBC_UPSTA2SET) PERRI Set */\r
+#define USBC_UPSTA2SET_NAKEDIS (0x1u << 4) /**< \brief (USBC_UPSTA2SET) NAKEDI Set */\r
+#define USBC_UPSTA2SET_ERRORFIS (0x1u << 5) /**< \brief (USBC_UPSTA2SET) ERRORFI Set */\r
+#define USBC_UPSTA2SET_RXSTALLDIS (0x1u << 6) /**< \brief (USBC_UPSTA2SET) RXSTALLDI Set */\r
+#define USBC_UPSTA2SET_RAMACERIS (0x1u << 10) /**< \brief (USBC_UPSTA2SET) RAMACERI Set */\r
+/* -------- USBC_UPSTA3SET : (USBC Offset: 0x59C) Pipe Status Set Register -------- */\r
+#define USBC_UPSTA3SET_RXINIS (0x1u << 0) /**< \brief (USBC_UPSTA3SET) RXINI Set */\r
+#define USBC_UPSTA3SET_TXOUTIS (0x1u << 1) /**< \brief (USBC_UPSTA3SET) TXOUTI Set */\r
+#define USBC_UPSTA3SET_TXSTPIS (0x1u << 2) /**< \brief (USBC_UPSTA3SET) TXSTPI Set */\r
+#define USBC_UPSTA3SET_PERRIS (0x1u << 3) /**< \brief (USBC_UPSTA3SET) PERRI Set */\r
+#define USBC_UPSTA3SET_NAKEDIS (0x1u << 4) /**< \brief (USBC_UPSTA3SET) NAKEDI Set */\r
+#define USBC_UPSTA3SET_ERRORFIS (0x1u << 5) /**< \brief (USBC_UPSTA3SET) ERRORFI Set */\r
+#define USBC_UPSTA3SET_RXSTALLDIS (0x1u << 6) /**< \brief (USBC_UPSTA3SET) RXSTALLDI Set */\r
+#define USBC_UPSTA3SET_RAMACERIS (0x1u << 10) /**< \brief (USBC_UPSTA3SET) RAMACERI Set */\r
+/* -------- USBC_UPSTA4SET : (USBC Offset: 0x5A0) Pipe Status Set Register -------- */\r
+#define USBC_UPSTA4SET_RXINIS (0x1u << 0) /**< \brief (USBC_UPSTA4SET) RXINI Set */\r
+#define USBC_UPSTA4SET_TXOUTIS (0x1u << 1) /**< \brief (USBC_UPSTA4SET) TXOUTI Set */\r
+#define USBC_UPSTA4SET_TXSTPIS (0x1u << 2) /**< \brief (USBC_UPSTA4SET) TXSTPI Set */\r
+#define USBC_UPSTA4SET_PERRIS (0x1u << 3) /**< \brief (USBC_UPSTA4SET) PERRI Set */\r
+#define USBC_UPSTA4SET_NAKEDIS (0x1u << 4) /**< \brief (USBC_UPSTA4SET) NAKEDI Set */\r
+#define USBC_UPSTA4SET_ERRORFIS (0x1u << 5) /**< \brief (USBC_UPSTA4SET) ERRORFI Set */\r
+#define USBC_UPSTA4SET_RXSTALLDIS (0x1u << 6) /**< \brief (USBC_UPSTA4SET) RXSTALLDI Set */\r
+#define USBC_UPSTA4SET_RAMACERIS (0x1u << 10) /**< \brief (USBC_UPSTA4SET) RAMACERI Set */\r
+/* -------- USBC_UPSTA5SET : (USBC Offset: 0x5A4) Pipe Status Set Register -------- */\r
+#define USBC_UPSTA5SET_RXINIS (0x1u << 0) /**< \brief (USBC_UPSTA5SET) RXINI Set */\r
+#define USBC_UPSTA5SET_TXOUTIS (0x1u << 1) /**< \brief (USBC_UPSTA5SET) TXOUTI Set */\r
+#define USBC_UPSTA5SET_TXSTPIS (0x1u << 2) /**< \brief (USBC_UPSTA5SET) TXSTPI Set */\r
+#define USBC_UPSTA5SET_PERRIS (0x1u << 3) /**< \brief (USBC_UPSTA5SET) PERRI Set */\r
+#define USBC_UPSTA5SET_NAKEDIS (0x1u << 4) /**< \brief (USBC_UPSTA5SET) NAKEDI Set */\r
+#define USBC_UPSTA5SET_ERRORFIS (0x1u << 5) /**< \brief (USBC_UPSTA5SET) ERRORFI Set */\r
+#define USBC_UPSTA5SET_RXSTALLDIS (0x1u << 6) /**< \brief (USBC_UPSTA5SET) RXSTALLDI Set */\r
+#define USBC_UPSTA5SET_RAMACERIS (0x1u << 10) /**< \brief (USBC_UPSTA5SET) RAMACERI Set */\r
+/* -------- USBC_UPSTA6SET : (USBC Offset: 0x5A8) Pipe Status Set Register -------- */\r
+#define USBC_UPSTA6SET_RXINIS (0x1u << 0) /**< \brief (USBC_UPSTA6SET) RXINI Set */\r
+#define USBC_UPSTA6SET_TXOUTIS (0x1u << 1) /**< \brief (USBC_UPSTA6SET) TXOUTI Set */\r
+#define USBC_UPSTA6SET_TXSTPIS (0x1u << 2) /**< \brief (USBC_UPSTA6SET) TXSTPI Set */\r
+#define USBC_UPSTA6SET_PERRIS (0x1u << 3) /**< \brief (USBC_UPSTA6SET) PERRI Set */\r
+#define USBC_UPSTA6SET_NAKEDIS (0x1u << 4) /**< \brief (USBC_UPSTA6SET) NAKEDI Set */\r
+#define USBC_UPSTA6SET_ERRORFIS (0x1u << 5) /**< \brief (USBC_UPSTA6SET) ERRORFI Set */\r
+#define USBC_UPSTA6SET_RXSTALLDIS (0x1u << 6) /**< \brief (USBC_UPSTA6SET) RXSTALLDI Set */\r
+#define USBC_UPSTA6SET_RAMACERIS (0x1u << 10) /**< \brief (USBC_UPSTA6SET) RAMACERI Set */\r
+/* -------- USBC_UPSTA7SET : (USBC Offset: 0x5AC) Pipe Status Set Register -------- */\r
+#define USBC_UPSTA7SET_RXINIS (0x1u << 0) /**< \brief (USBC_UPSTA7SET) RXINI Set */\r
+#define USBC_UPSTA7SET_TXOUTIS (0x1u << 1) /**< \brief (USBC_UPSTA7SET) TXOUTI Set */\r
+#define USBC_UPSTA7SET_TXSTPIS (0x1u << 2) /**< \brief (USBC_UPSTA7SET) TXSTPI Set */\r
+#define USBC_UPSTA7SET_PERRIS (0x1u << 3) /**< \brief (USBC_UPSTA7SET) PERRI Set */\r
+#define USBC_UPSTA7SET_NAKEDIS (0x1u << 4) /**< \brief (USBC_UPSTA7SET) NAKEDI Set */\r
+#define USBC_UPSTA7SET_ERRORFIS (0x1u << 5) /**< \brief (USBC_UPSTA7SET) ERRORFI Set */\r
+#define USBC_UPSTA7SET_RXSTALLDIS (0x1u << 6) /**< \brief (USBC_UPSTA7SET) RXSTALLDI Set */\r
+#define USBC_UPSTA7SET_RAMACERIS (0x1u << 10) /**< \brief (USBC_UPSTA7SET) RAMACERI Set */\r
+/* -------- USBC_UPCON0 : (USBC Offset: 0x5C0) Pipe Control Register -------- */\r
+#define USBC_UPCON0_RXINE (0x1u << 0) /**< \brief (USBC_UPCON0) RXIN Interrupt Enable */\r
+#define USBC_UPCON0_TXOUTE (0x1u << 1) /**< \brief (USBC_UPCON0) TXOUT Interrupt Enable */\r
+#define USBC_UPCON0_TXSTPE (0x1u << 2) /**< \brief (USBC_UPCON0) TXSTP Interrupt Enable */\r
+#define USBC_UPCON0_PERRE (0x1u << 3) /**< \brief (USBC_UPCON0) PERR Interrupt Enable */\r
+#define USBC_UPCON0_NAKEDE (0x1u << 4) /**< \brief (USBC_UPCON0) NAKED Interrupt Enable */\r
+#define USBC_UPCON0_ERRORFIE (0x1u << 5) /**< \brief (USBC_UPCON0) ERRORFI Interrupt Enable */\r
+#define USBC_UPCON0_RXSTALLDE (0x1u << 6) /**< \brief (USBC_UPCON0) RXTALLD Interrupt Enable */\r
+#define USBC_UPCON0_RAMACERE (0x1u << 10) /**< \brief (USBC_UPCON0) RAMACER Interrupt Enable */\r
+#define USBC_UPCON0_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UPCON0) NBUSYBKInterrupt Enable */\r
+#define USBC_UPCON0_FIFOCON (0x1u << 14) /**< \brief (USBC_UPCON0) FIFO Control */\r
+#define USBC_UPCON0_PFREEZE (0x1u << 17) /**< \brief (USBC_UPCON0) Pipe Freeze */\r
+#define USBC_UPCON0_INITDTGL (0x1u << 18) /**< \brief (USBC_UPCON0) Data Toggle Initialization */\r
+#define USBC_UPCON0_INITBK (0x1u << 19) /**< \brief (USBC_UPCON0) Bank Initialization */\r
+/* -------- USBC_UPCON1 : (USBC Offset: 0x5C4) Pipe Control Register -------- */\r
+#define USBC_UPCON1_RXINE (0x1u << 0) /**< \brief (USBC_UPCON1) RXIN Interrupt Enable */\r
+#define USBC_UPCON1_TXOUTE (0x1u << 1) /**< \brief (USBC_UPCON1) TXOUT Interrupt Enable */\r
+#define USBC_UPCON1_TXSTPE (0x1u << 2) /**< \brief (USBC_UPCON1) TXSTP Interrupt Enable */\r
+#define USBC_UPCON1_PERRE (0x1u << 3) /**< \brief (USBC_UPCON1) PERR Interrupt Enable */\r
+#define USBC_UPCON1_NAKEDE (0x1u << 4) /**< \brief (USBC_UPCON1) NAKED Interrupt Enable */\r
+#define USBC_UPCON1_ERRORFIE (0x1u << 5) /**< \brief (USBC_UPCON1) ERRORFI Interrupt Enable */\r
+#define USBC_UPCON1_RXSTALLDE (0x1u << 6) /**< \brief (USBC_UPCON1) RXTALLD Interrupt Enable */\r
+#define USBC_UPCON1_RAMACERE (0x1u << 10) /**< \brief (USBC_UPCON1) RAMACER Interrupt Enable */\r
+#define USBC_UPCON1_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UPCON1) NBUSYBKInterrupt Enable */\r
+#define USBC_UPCON1_FIFOCON (0x1u << 14) /**< \brief (USBC_UPCON1) FIFO Control */\r
+#define USBC_UPCON1_PFREEZE (0x1u << 17) /**< \brief (USBC_UPCON1) Pipe Freeze */\r
+#define USBC_UPCON1_INITDTGL (0x1u << 18) /**< \brief (USBC_UPCON1) Data Toggle Initialization */\r
+#define USBC_UPCON1_INITBK (0x1u << 19) /**< \brief (USBC_UPCON1) Bank Initialization */\r
+/* -------- USBC_UPCON2 : (USBC Offset: 0x5C8) Pipe Control Register -------- */\r
+#define USBC_UPCON2_RXINE (0x1u << 0) /**< \brief (USBC_UPCON2) RXIN Interrupt Enable */\r
+#define USBC_UPCON2_TXOUTE (0x1u << 1) /**< \brief (USBC_UPCON2) TXOUT Interrupt Enable */\r
+#define USBC_UPCON2_TXSTPE (0x1u << 2) /**< \brief (USBC_UPCON2) TXSTP Interrupt Enable */\r
+#define USBC_UPCON2_PERRE (0x1u << 3) /**< \brief (USBC_UPCON2) PERR Interrupt Enable */\r
+#define USBC_UPCON2_NAKEDE (0x1u << 4) /**< \brief (USBC_UPCON2) NAKED Interrupt Enable */\r
+#define USBC_UPCON2_ERRORFIE (0x1u << 5) /**< \brief (USBC_UPCON2) ERRORFI Interrupt Enable */\r
+#define USBC_UPCON2_RXSTALLDE (0x1u << 6) /**< \brief (USBC_UPCON2) RXTALLD Interrupt Enable */\r
+#define USBC_UPCON2_RAMACERE (0x1u << 10) /**< \brief (USBC_UPCON2) RAMACER Interrupt Enable */\r
+#define USBC_UPCON2_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UPCON2) NBUSYBKInterrupt Enable */\r
+#define USBC_UPCON2_FIFOCON (0x1u << 14) /**< \brief (USBC_UPCON2) FIFO Control */\r
+#define USBC_UPCON2_PFREEZE (0x1u << 17) /**< \brief (USBC_UPCON2) Pipe Freeze */\r
+#define USBC_UPCON2_INITDTGL (0x1u << 18) /**< \brief (USBC_UPCON2) Data Toggle Initialization */\r
+#define USBC_UPCON2_INITBK (0x1u << 19) /**< \brief (USBC_UPCON2) Bank Initialization */\r
+/* -------- USBC_UPCON3 : (USBC Offset: 0x5CC) Pipe Control Register -------- */\r
+#define USBC_UPCON3_RXINE (0x1u << 0) /**< \brief (USBC_UPCON3) RXIN Interrupt Enable */\r
+#define USBC_UPCON3_TXOUTE (0x1u << 1) /**< \brief (USBC_UPCON3) TXOUT Interrupt Enable */\r
+#define USBC_UPCON3_TXSTPE (0x1u << 2) /**< \brief (USBC_UPCON3) TXSTP Interrupt Enable */\r
+#define USBC_UPCON3_PERRE (0x1u << 3) /**< \brief (USBC_UPCON3) PERR Interrupt Enable */\r
+#define USBC_UPCON3_NAKEDE (0x1u << 4) /**< \brief (USBC_UPCON3) NAKED Interrupt Enable */\r
+#define USBC_UPCON3_ERRORFIE (0x1u << 5) /**< \brief (USBC_UPCON3) ERRORFI Interrupt Enable */\r
+#define USBC_UPCON3_RXSTALLDE (0x1u << 6) /**< \brief (USBC_UPCON3) RXTALLD Interrupt Enable */\r
+#define USBC_UPCON3_RAMACERE (0x1u << 10) /**< \brief (USBC_UPCON3) RAMACER Interrupt Enable */\r
+#define USBC_UPCON3_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UPCON3) NBUSYBKInterrupt Enable */\r
+#define USBC_UPCON3_FIFOCON (0x1u << 14) /**< \brief (USBC_UPCON3) FIFO Control */\r
+#define USBC_UPCON3_PFREEZE (0x1u << 17) /**< \brief (USBC_UPCON3) Pipe Freeze */\r
+#define USBC_UPCON3_INITDTGL (0x1u << 18) /**< \brief (USBC_UPCON3) Data Toggle Initialization */\r
+#define USBC_UPCON3_INITBK (0x1u << 19) /**< \brief (USBC_UPCON3) Bank Initialization */\r
+/* -------- USBC_UPCON4 : (USBC Offset: 0x5D0) Pipe Control Register -------- */\r
+#define USBC_UPCON4_RXINE (0x1u << 0) /**< \brief (USBC_UPCON4) RXIN Interrupt Enable */\r
+#define USBC_UPCON4_TXOUTE (0x1u << 1) /**< \brief (USBC_UPCON4) TXOUT Interrupt Enable */\r
+#define USBC_UPCON4_TXSTPE (0x1u << 2) /**< \brief (USBC_UPCON4) TXSTP Interrupt Enable */\r
+#define USBC_UPCON4_PERRE (0x1u << 3) /**< \brief (USBC_UPCON4) PERR Interrupt Enable */\r
+#define USBC_UPCON4_NAKEDE (0x1u << 4) /**< \brief (USBC_UPCON4) NAKED Interrupt Enable */\r
+#define USBC_UPCON4_ERRORFIE (0x1u << 5) /**< \brief (USBC_UPCON4) ERRORFI Interrupt Enable */\r
+#define USBC_UPCON4_RXSTALLDE (0x1u << 6) /**< \brief (USBC_UPCON4) RXTALLD Interrupt Enable */\r
+#define USBC_UPCON4_RAMACERE (0x1u << 10) /**< \brief (USBC_UPCON4) RAMACER Interrupt Enable */\r
+#define USBC_UPCON4_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UPCON4) NBUSYBKInterrupt Enable */\r
+#define USBC_UPCON4_FIFOCON (0x1u << 14) /**< \brief (USBC_UPCON4) FIFO Control */\r
+#define USBC_UPCON4_PFREEZE (0x1u << 17) /**< \brief (USBC_UPCON4) Pipe Freeze */\r
+#define USBC_UPCON4_INITDTGL (0x1u << 18) /**< \brief (USBC_UPCON4) Data Toggle Initialization */\r
+#define USBC_UPCON4_INITBK (0x1u << 19) /**< \brief (USBC_UPCON4) Bank Initialization */\r
+/* -------- USBC_UPCON5 : (USBC Offset: 0x5D4) Pipe Control Register -------- */\r
+#define USBC_UPCON5_RXINE (0x1u << 0) /**< \brief (USBC_UPCON5) RXIN Interrupt Enable */\r
+#define USBC_UPCON5_TXOUTE (0x1u << 1) /**< \brief (USBC_UPCON5) TXOUT Interrupt Enable */\r
+#define USBC_UPCON5_TXSTPE (0x1u << 2) /**< \brief (USBC_UPCON5) TXSTP Interrupt Enable */\r
+#define USBC_UPCON5_PERRE (0x1u << 3) /**< \brief (USBC_UPCON5) PERR Interrupt Enable */\r
+#define USBC_UPCON5_NAKEDE (0x1u << 4) /**< \brief (USBC_UPCON5) NAKED Interrupt Enable */\r
+#define USBC_UPCON5_ERRORFIE (0x1u << 5) /**< \brief (USBC_UPCON5) ERRORFI Interrupt Enable */\r
+#define USBC_UPCON5_RXSTALLDE (0x1u << 6) /**< \brief (USBC_UPCON5) RXTALLD Interrupt Enable */\r
+#define USBC_UPCON5_RAMACERE (0x1u << 10) /**< \brief (USBC_UPCON5) RAMACER Interrupt Enable */\r
+#define USBC_UPCON5_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UPCON5) NBUSYBKInterrupt Enable */\r
+#define USBC_UPCON5_FIFOCON (0x1u << 14) /**< \brief (USBC_UPCON5) FIFO Control */\r
+#define USBC_UPCON5_PFREEZE (0x1u << 17) /**< \brief (USBC_UPCON5) Pipe Freeze */\r
+#define USBC_UPCON5_INITDTGL (0x1u << 18) /**< \brief (USBC_UPCON5) Data Toggle Initialization */\r
+#define USBC_UPCON5_INITBK (0x1u << 19) /**< \brief (USBC_UPCON5) Bank Initialization */\r
+/* -------- USBC_UPCON6 : (USBC Offset: 0x5D8) Pipe Control Register -------- */\r
+#define USBC_UPCON6_RXINE (0x1u << 0) /**< \brief (USBC_UPCON6) RXIN Interrupt Enable */\r
+#define USBC_UPCON6_TXOUTE (0x1u << 1) /**< \brief (USBC_UPCON6) TXOUT Interrupt Enable */\r
+#define USBC_UPCON6_TXSTPE (0x1u << 2) /**< \brief (USBC_UPCON6) TXSTP Interrupt Enable */\r
+#define USBC_UPCON6_PERRE (0x1u << 3) /**< \brief (USBC_UPCON6) PERR Interrupt Enable */\r
+#define USBC_UPCON6_NAKEDE (0x1u << 4) /**< \brief (USBC_UPCON6) NAKED Interrupt Enable */\r
+#define USBC_UPCON6_ERRORFIE (0x1u << 5) /**< \brief (USBC_UPCON6) ERRORFI Interrupt Enable */\r
+#define USBC_UPCON6_RXSTALLDE (0x1u << 6) /**< \brief (USBC_UPCON6) RXTALLD Interrupt Enable */\r
+#define USBC_UPCON6_RAMACERE (0x1u << 10) /**< \brief (USBC_UPCON6) RAMACER Interrupt Enable */\r
+#define USBC_UPCON6_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UPCON6) NBUSYBKInterrupt Enable */\r
+#define USBC_UPCON6_FIFOCON (0x1u << 14) /**< \brief (USBC_UPCON6) FIFO Control */\r
+#define USBC_UPCON6_PFREEZE (0x1u << 17) /**< \brief (USBC_UPCON6) Pipe Freeze */\r
+#define USBC_UPCON6_INITDTGL (0x1u << 18) /**< \brief (USBC_UPCON6) Data Toggle Initialization */\r
+#define USBC_UPCON6_INITBK (0x1u << 19) /**< \brief (USBC_UPCON6) Bank Initialization */\r
+/* -------- USBC_UPCON7 : (USBC Offset: 0x5DC) Pipe Control Register -------- */\r
+#define USBC_UPCON7_RXINE (0x1u << 0) /**< \brief (USBC_UPCON7) RXIN Interrupt Enable */\r
+#define USBC_UPCON7_TXOUTE (0x1u << 1) /**< \brief (USBC_UPCON7) TXOUT Interrupt Enable */\r
+#define USBC_UPCON7_TXSTPE (0x1u << 2) /**< \brief (USBC_UPCON7) TXSTP Interrupt Enable */\r
+#define USBC_UPCON7_PERRE (0x1u << 3) /**< \brief (USBC_UPCON7) PERR Interrupt Enable */\r
+#define USBC_UPCON7_NAKEDE (0x1u << 4) /**< \brief (USBC_UPCON7) NAKED Interrupt Enable */\r
+#define USBC_UPCON7_ERRORFIE (0x1u << 5) /**< \brief (USBC_UPCON7) ERRORFI Interrupt Enable */\r
+#define USBC_UPCON7_RXSTALLDE (0x1u << 6) /**< \brief (USBC_UPCON7) RXTALLD Interrupt Enable */\r
+#define USBC_UPCON7_RAMACERE (0x1u << 10) /**< \brief (USBC_UPCON7) RAMACER Interrupt Enable */\r
+#define USBC_UPCON7_NBUSYBKE (0x1u << 12) /**< \brief (USBC_UPCON7) NBUSYBKInterrupt Enable */\r
+#define USBC_UPCON7_FIFOCON (0x1u << 14) /**< \brief (USBC_UPCON7) FIFO Control */\r
+#define USBC_UPCON7_PFREEZE (0x1u << 17) /**< \brief (USBC_UPCON7) Pipe Freeze */\r
+#define USBC_UPCON7_INITDTGL (0x1u << 18) /**< \brief (USBC_UPCON7) Data Toggle Initialization */\r
+#define USBC_UPCON7_INITBK (0x1u << 19) /**< \brief (USBC_UPCON7) Bank Initialization */\r
+/* -------- USBC_UPCON0SET : (USBC Offset: 0x5F0) Pipe Control Set Register -------- */\r
+#define USBC_UPCON0SET_RXINES (0x1u << 0) /**< \brief (USBC_UPCON0SET) RXINE Set */\r
+#define USBC_UPCON0SET_TXOUTES (0x1u << 1) /**< \brief (USBC_UPCON0SET) TXOUTE Set */\r
+#define USBC_UPCON0SET_TXSTPES (0x1u << 2) /**< \brief (USBC_UPCON0SET) TXSTPE Set */\r
+#define USBC_UPCON0SET_PERRES (0x1u << 3) /**< \brief (USBC_UPCON0SET) PERRE Set */\r
+#define USBC_UPCON0SET_NAKEDES (0x1u << 4) /**< \brief (USBC_UPCON0SET) NAKEDE Set */\r
+#define USBC_UPCON0SET_ERRORFIES (0x1u << 5) /**< \brief (USBC_UPCON0SET) ERRORFIE Set */\r
+#define USBC_UPCON0SET_RXSTALLDES (0x1u << 6) /**< \brief (USBC_UPCON0SET) RXSTALLDE Set */\r
+#define USBC_UPCON0SET_RAMACERES (0x1u << 10) /**< \brief (USBC_UPCON0SET) RAMACERE Set */\r
+#define USBC_UPCON0SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UPCON0SET) NBUSYBKE Set */\r
+#define USBC_UPCON0SET_FIFOCONS (0x1u << 14) /**< \brief (USBC_UPCON0SET) FIFOCON Set */\r
+#define USBC_UPCON0SET_PFREEZES (0x1u << 17) /**< \brief (USBC_UPCON0SET) PFREEZE Set */\r
+#define USBC_UPCON0SET_INITDTGLS (0x1u << 18) /**< \brief (USBC_UPCON0SET) INITDTGL Set */\r
+#define USBC_UPCON0SET_INITBKS (0x1u << 19) /**< \brief (USBC_UPCON0SET) INITBK Set */\r
+/* -------- USBC_UPCON1SET : (USBC Offset: 0x5F4) Pipe Control Set Register -------- */\r
+#define USBC_UPCON1SET_RXINES (0x1u << 0) /**< \brief (USBC_UPCON1SET) RXINE Set */\r
+#define USBC_UPCON1SET_TXOUTES (0x1u << 1) /**< \brief (USBC_UPCON1SET) TXOUTE Set */\r
+#define USBC_UPCON1SET_TXSTPES (0x1u << 2) /**< \brief (USBC_UPCON1SET) TXSTPE Set */\r
+#define USBC_UPCON1SET_PERRES (0x1u << 3) /**< \brief (USBC_UPCON1SET) PERRE Set */\r
+#define USBC_UPCON1SET_NAKEDES (0x1u << 4) /**< \brief (USBC_UPCON1SET) NAKEDE Set */\r
+#define USBC_UPCON1SET_ERRORFIES (0x1u << 5) /**< \brief (USBC_UPCON1SET) ERRORFIE Set */\r
+#define USBC_UPCON1SET_RXSTALLDES (0x1u << 6) /**< \brief (USBC_UPCON1SET) RXSTALLDE Set */\r
+#define USBC_UPCON1SET_RAMACERES (0x1u << 10) /**< \brief (USBC_UPCON1SET) RAMACERE Set */\r
+#define USBC_UPCON1SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UPCON1SET) NBUSYBKE Set */\r
+#define USBC_UPCON1SET_FIFOCONS (0x1u << 14) /**< \brief (USBC_UPCON1SET) FIFOCON Set */\r
+#define USBC_UPCON1SET_PFREEZES (0x1u << 17) /**< \brief (USBC_UPCON1SET) PFREEZE Set */\r
+#define USBC_UPCON1SET_INITDTGLS (0x1u << 18) /**< \brief (USBC_UPCON1SET) INITDTGL Set */\r
+#define USBC_UPCON1SET_INITBKS (0x1u << 19) /**< \brief (USBC_UPCON1SET) INITBK Set */\r
+/* -------- USBC_UPCON2SET : (USBC Offset: 0x5F8) Pipe Control Set Register -------- */\r
+#define USBC_UPCON2SET_RXINES (0x1u << 0) /**< \brief (USBC_UPCON2SET) RXINE Set */\r
+#define USBC_UPCON2SET_TXOUTES (0x1u << 1) /**< \brief (USBC_UPCON2SET) TXOUTE Set */\r
+#define USBC_UPCON2SET_TXSTPES (0x1u << 2) /**< \brief (USBC_UPCON2SET) TXSTPE Set */\r
+#define USBC_UPCON2SET_PERRES (0x1u << 3) /**< \brief (USBC_UPCON2SET) PERRE Set */\r
+#define USBC_UPCON2SET_NAKEDES (0x1u << 4) /**< \brief (USBC_UPCON2SET) NAKEDE Set */\r
+#define USBC_UPCON2SET_ERRORFIES (0x1u << 5) /**< \brief (USBC_UPCON2SET) ERRORFIE Set */\r
+#define USBC_UPCON2SET_RXSTALLDES (0x1u << 6) /**< \brief (USBC_UPCON2SET) RXSTALLDE Set */\r
+#define USBC_UPCON2SET_RAMACERES (0x1u << 10) /**< \brief (USBC_UPCON2SET) RAMACERE Set */\r
+#define USBC_UPCON2SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UPCON2SET) NBUSYBKE Set */\r
+#define USBC_UPCON2SET_FIFOCONS (0x1u << 14) /**< \brief (USBC_UPCON2SET) FIFOCON Set */\r
+#define USBC_UPCON2SET_PFREEZES (0x1u << 17) /**< \brief (USBC_UPCON2SET) PFREEZE Set */\r
+#define USBC_UPCON2SET_INITDTGLS (0x1u << 18) /**< \brief (USBC_UPCON2SET) INITDTGL Set */\r
+#define USBC_UPCON2SET_INITBKS (0x1u << 19) /**< \brief (USBC_UPCON2SET) INITBK Set */\r
+/* -------- USBC_UPCON3SET : (USBC Offset: 0x5FC) Pipe Control Set Register -------- */\r
+#define USBC_UPCON3SET_RXINES (0x1u << 0) /**< \brief (USBC_UPCON3SET) RXINE Set */\r
+#define USBC_UPCON3SET_TXOUTES (0x1u << 1) /**< \brief (USBC_UPCON3SET) TXOUTE Set */\r
+#define USBC_UPCON3SET_TXSTPES (0x1u << 2) /**< \brief (USBC_UPCON3SET) TXSTPE Set */\r
+#define USBC_UPCON3SET_PERRES (0x1u << 3) /**< \brief (USBC_UPCON3SET) PERRE Set */\r
+#define USBC_UPCON3SET_NAKEDES (0x1u << 4) /**< \brief (USBC_UPCON3SET) NAKEDE Set */\r
+#define USBC_UPCON3SET_ERRORFIES (0x1u << 5) /**< \brief (USBC_UPCON3SET) ERRORFIE Set */\r
+#define USBC_UPCON3SET_RXSTALLDES (0x1u << 6) /**< \brief (USBC_UPCON3SET) RXSTALLDE Set */\r
+#define USBC_UPCON3SET_RAMACERES (0x1u << 10) /**< \brief (USBC_UPCON3SET) RAMACERE Set */\r
+#define USBC_UPCON3SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UPCON3SET) NBUSYBKE Set */\r
+#define USBC_UPCON3SET_FIFOCONS (0x1u << 14) /**< \brief (USBC_UPCON3SET) FIFOCON Set */\r
+#define USBC_UPCON3SET_PFREEZES (0x1u << 17) /**< \brief (USBC_UPCON3SET) PFREEZE Set */\r
+#define USBC_UPCON3SET_INITDTGLS (0x1u << 18) /**< \brief (USBC_UPCON3SET) INITDTGL Set */\r
+#define USBC_UPCON3SET_INITBKS (0x1u << 19) /**< \brief (USBC_UPCON3SET) INITBK Set */\r
+/* -------- USBC_UPCON4SET : (USBC Offset: 0x600) Pipe Control Set Register -------- */\r
+#define USBC_UPCON4SET_RXINES (0x1u << 0) /**< \brief (USBC_UPCON4SET) RXINE Set */\r
+#define USBC_UPCON4SET_TXOUTES (0x1u << 1) /**< \brief (USBC_UPCON4SET) TXOUTE Set */\r
+#define USBC_UPCON4SET_TXSTPES (0x1u << 2) /**< \brief (USBC_UPCON4SET) TXSTPE Set */\r
+#define USBC_UPCON4SET_PERRES (0x1u << 3) /**< \brief (USBC_UPCON4SET) PERRE Set */\r
+#define USBC_UPCON4SET_NAKEDES (0x1u << 4) /**< \brief (USBC_UPCON4SET) NAKEDE Set */\r
+#define USBC_UPCON4SET_ERRORFIES (0x1u << 5) /**< \brief (USBC_UPCON4SET) ERRORFIE Set */\r
+#define USBC_UPCON4SET_RXSTALLDES (0x1u << 6) /**< \brief (USBC_UPCON4SET) RXSTALLDE Set */\r
+#define USBC_UPCON4SET_RAMACERES (0x1u << 10) /**< \brief (USBC_UPCON4SET) RAMACERE Set */\r
+#define USBC_UPCON4SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UPCON4SET) NBUSYBKE Set */\r
+#define USBC_UPCON4SET_FIFOCONS (0x1u << 14) /**< \brief (USBC_UPCON4SET) FIFOCON Set */\r
+#define USBC_UPCON4SET_PFREEZES (0x1u << 17) /**< \brief (USBC_UPCON4SET) PFREEZE Set */\r
+#define USBC_UPCON4SET_INITDTGLS (0x1u << 18) /**< \brief (USBC_UPCON4SET) INITDTGL Set */\r
+#define USBC_UPCON4SET_INITBKS (0x1u << 19) /**< \brief (USBC_UPCON4SET) INITBK Set */\r
+/* -------- USBC_UPCON5SET : (USBC Offset: 0x604) Pipe Control Set Register -------- */\r
+#define USBC_UPCON5SET_RXINES (0x1u << 0) /**< \brief (USBC_UPCON5SET) RXINE Set */\r
+#define USBC_UPCON5SET_TXOUTES (0x1u << 1) /**< \brief (USBC_UPCON5SET) TXOUTE Set */\r
+#define USBC_UPCON5SET_TXSTPES (0x1u << 2) /**< \brief (USBC_UPCON5SET) TXSTPE Set */\r
+#define USBC_UPCON5SET_PERRES (0x1u << 3) /**< \brief (USBC_UPCON5SET) PERRE Set */\r
+#define USBC_UPCON5SET_NAKEDES (0x1u << 4) /**< \brief (USBC_UPCON5SET) NAKEDE Set */\r
+#define USBC_UPCON5SET_ERRORFIES (0x1u << 5) /**< \brief (USBC_UPCON5SET) ERRORFIE Set */\r
+#define USBC_UPCON5SET_RXSTALLDES (0x1u << 6) /**< \brief (USBC_UPCON5SET) RXSTALLDE Set */\r
+#define USBC_UPCON5SET_RAMACERES (0x1u << 10) /**< \brief (USBC_UPCON5SET) RAMACERE Set */\r
+#define USBC_UPCON5SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UPCON5SET) NBUSYBKE Set */\r
+#define USBC_UPCON5SET_FIFOCONS (0x1u << 14) /**< \brief (USBC_UPCON5SET) FIFOCON Set */\r
+#define USBC_UPCON5SET_PFREEZES (0x1u << 17) /**< \brief (USBC_UPCON5SET) PFREEZE Set */\r
+#define USBC_UPCON5SET_INITDTGLS (0x1u << 18) /**< \brief (USBC_UPCON5SET) INITDTGL Set */\r
+#define USBC_UPCON5SET_INITBKS (0x1u << 19) /**< \brief (USBC_UPCON5SET) INITBK Set */\r
+/* -------- USBC_UPCON6SET : (USBC Offset: 0x608) Pipe Control Set Register -------- */\r
+#define USBC_UPCON6SET_RXINES (0x1u << 0) /**< \brief (USBC_UPCON6SET) RXINE Set */\r
+#define USBC_UPCON6SET_TXOUTES (0x1u << 1) /**< \brief (USBC_UPCON6SET) TXOUTE Set */\r
+#define USBC_UPCON6SET_TXSTPES (0x1u << 2) /**< \brief (USBC_UPCON6SET) TXSTPE Set */\r
+#define USBC_UPCON6SET_PERRES (0x1u << 3) /**< \brief (USBC_UPCON6SET) PERRE Set */\r
+#define USBC_UPCON6SET_NAKEDES (0x1u << 4) /**< \brief (USBC_UPCON6SET) NAKEDE Set */\r
+#define USBC_UPCON6SET_ERRORFIES (0x1u << 5) /**< \brief (USBC_UPCON6SET) ERRORFIE Set */\r
+#define USBC_UPCON6SET_RXSTALLDES (0x1u << 6) /**< \brief (USBC_UPCON6SET) RXSTALLDE Set */\r
+#define USBC_UPCON6SET_RAMACERES (0x1u << 10) /**< \brief (USBC_UPCON6SET) RAMACERE Set */\r
+#define USBC_UPCON6SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UPCON6SET) NBUSYBKE Set */\r
+#define USBC_UPCON6SET_FIFOCONS (0x1u << 14) /**< \brief (USBC_UPCON6SET) FIFOCON Set */\r
+#define USBC_UPCON6SET_PFREEZES (0x1u << 17) /**< \brief (USBC_UPCON6SET) PFREEZE Set */\r
+#define USBC_UPCON6SET_INITDTGLS (0x1u << 18) /**< \brief (USBC_UPCON6SET) INITDTGL Set */\r
+#define USBC_UPCON6SET_INITBKS (0x1u << 19) /**< \brief (USBC_UPCON6SET) INITBK Set */\r
+/* -------- USBC_UPCON7SET : (USBC Offset: 0x60C) Pipe Control Set Register -------- */\r
+#define USBC_UPCON7SET_RXINES (0x1u << 0) /**< \brief (USBC_UPCON7SET) RXINE Set */\r
+#define USBC_UPCON7SET_TXOUTES (0x1u << 1) /**< \brief (USBC_UPCON7SET) TXOUTE Set */\r
+#define USBC_UPCON7SET_TXSTPES (0x1u << 2) /**< \brief (USBC_UPCON7SET) TXSTPE Set */\r
+#define USBC_UPCON7SET_PERRES (0x1u << 3) /**< \brief (USBC_UPCON7SET) PERRE Set */\r
+#define USBC_UPCON7SET_NAKEDES (0x1u << 4) /**< \brief (USBC_UPCON7SET) NAKEDE Set */\r
+#define USBC_UPCON7SET_ERRORFIES (0x1u << 5) /**< \brief (USBC_UPCON7SET) ERRORFIE Set */\r
+#define USBC_UPCON7SET_RXSTALLDES (0x1u << 6) /**< \brief (USBC_UPCON7SET) RXSTALLDE Set */\r
+#define USBC_UPCON7SET_RAMACERES (0x1u << 10) /**< \brief (USBC_UPCON7SET) RAMACERE Set */\r
+#define USBC_UPCON7SET_NBUSYBKES (0x1u << 12) /**< \brief (USBC_UPCON7SET) NBUSYBKE Set */\r
+#define USBC_UPCON7SET_FIFOCONS (0x1u << 14) /**< \brief (USBC_UPCON7SET) FIFOCON Set */\r
+#define USBC_UPCON7SET_PFREEZES (0x1u << 17) /**< \brief (USBC_UPCON7SET) PFREEZE Set */\r
+#define USBC_UPCON7SET_INITDTGLS (0x1u << 18) /**< \brief (USBC_UPCON7SET) INITDTGL Set */\r
+#define USBC_UPCON7SET_INITBKS (0x1u << 19) /**< \brief (USBC_UPCON7SET) INITBK Set */\r
+/* -------- USBC_UPCON0CLR : (USBC Offset: 0x620) Pipe Control Clear Register -------- */\r
+#define USBC_UPCON0CLR_RXINEC (0x1u << 0) /**< \brief (USBC_UPCON0CLR) RXINE Clear */\r
+#define USBC_UPCON0CLR_TXOUTEC (0x1u << 1) /**< \brief (USBC_UPCON0CLR) TXOUTE Clear */\r
+#define USBC_UPCON0CLR_TXSTPEC (0x1u << 2) /**< \brief (USBC_UPCON0CLR) TXSTPE Clear */\r
+#define USBC_UPCON0CLR_PERREC (0x1u << 3) /**< \brief (USBC_UPCON0CLR) PERRE Clear */\r
+#define USBC_UPCON0CLR_NAKEDEC (0x1u << 4) /**< \brief (USBC_UPCON0CLR) NAKEDE Clear */\r
+#define USBC_UPCON0CLR_ERRORFIEC (0x1u << 5) /**< \brief (USBC_UPCON0CLR) ERRORFIE Clear */\r
+#define USBC_UPCON0CLR_RXSTALLDEC (0x1u << 6) /**< \brief (USBC_UPCON0CLR) RXTALLDE Clear */\r
+#define USBC_UPCON0CLR_RAMACEREC (0x1u << 10) /**< \brief (USBC_UPCON0CLR) RAMACERE Clear */\r
+#define USBC_UPCON0CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UPCON0CLR) NBUSYBKE Clear */\r
+#define USBC_UPCON0CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UPCON0CLR) FIFOCON Clear */\r
+#define USBC_UPCON0CLR_PFREEZEC (0x1u << 17) /**< \brief (USBC_UPCON0CLR) PFREEZE Clear */\r
+#define USBC_UPCON0CLR_INITDTGLC (0x1u << 18) /**< \brief (USBC_UPCON0CLR) INITDTGL Clear */\r
+#define USBC_UPCON0CLR_INITBKC (0x1u << 19) /**< \brief (USBC_UPCON0CLR) INITBK Clear */\r
+/* -------- USBC_UPCON1CLR : (USBC Offset: 0x624) Pipe Control Clear Register -------- */\r
+#define USBC_UPCON1CLR_RXINEC (0x1u << 0) /**< \brief (USBC_UPCON1CLR) RXINE Clear */\r
+#define USBC_UPCON1CLR_TXOUTEC (0x1u << 1) /**< \brief (USBC_UPCON1CLR) TXOUTE Clear */\r
+#define USBC_UPCON1CLR_TXSTPEC (0x1u << 2) /**< \brief (USBC_UPCON1CLR) TXSTPE Clear */\r
+#define USBC_UPCON1CLR_PERREC (0x1u << 3) /**< \brief (USBC_UPCON1CLR) PERRE Clear */\r
+#define USBC_UPCON1CLR_NAKEDEC (0x1u << 4) /**< \brief (USBC_UPCON1CLR) NAKEDE Clear */\r
+#define USBC_UPCON1CLR_ERRORFIEC (0x1u << 5) /**< \brief (USBC_UPCON1CLR) ERRORFIE Clear */\r
+#define USBC_UPCON1CLR_RXSTALLDEC (0x1u << 6) /**< \brief (USBC_UPCON1CLR) RXTALLDE Clear */\r
+#define USBC_UPCON1CLR_RAMACEREC (0x1u << 10) /**< \brief (USBC_UPCON1CLR) RAMACERE Clear */\r
+#define USBC_UPCON1CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UPCON1CLR) NBUSYBKE Clear */\r
+#define USBC_UPCON1CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UPCON1CLR) FIFOCON Clear */\r
+#define USBC_UPCON1CLR_PFREEZEC (0x1u << 17) /**< \brief (USBC_UPCON1CLR) PFREEZE Clear */\r
+#define USBC_UPCON1CLR_INITDTGLC (0x1u << 18) /**< \brief (USBC_UPCON1CLR) INITDTGL Clear */\r
+#define USBC_UPCON1CLR_INITBKC (0x1u << 19) /**< \brief (USBC_UPCON1CLR) INITBK Clear */\r
+/* -------- USBC_UPCON2CLR : (USBC Offset: 0x628) Pipe Control Clear Register -------- */\r
+#define USBC_UPCON2CLR_RXINEC (0x1u << 0) /**< \brief (USBC_UPCON2CLR) RXINE Clear */\r
+#define USBC_UPCON2CLR_TXOUTEC (0x1u << 1) /**< \brief (USBC_UPCON2CLR) TXOUTE Clear */\r
+#define USBC_UPCON2CLR_TXSTPEC (0x1u << 2) /**< \brief (USBC_UPCON2CLR) TXSTPE Clear */\r
+#define USBC_UPCON2CLR_PERREC (0x1u << 3) /**< \brief (USBC_UPCON2CLR) PERRE Clear */\r
+#define USBC_UPCON2CLR_NAKEDEC (0x1u << 4) /**< \brief (USBC_UPCON2CLR) NAKEDE Clear */\r
+#define USBC_UPCON2CLR_ERRORFIEC (0x1u << 5) /**< \brief (USBC_UPCON2CLR) ERRORFIE Clear */\r
+#define USBC_UPCON2CLR_RXSTALLDEC (0x1u << 6) /**< \brief (USBC_UPCON2CLR) RXTALLDE Clear */\r
+#define USBC_UPCON2CLR_RAMACEREC (0x1u << 10) /**< \brief (USBC_UPCON2CLR) RAMACERE Clear */\r
+#define USBC_UPCON2CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UPCON2CLR) NBUSYBKE Clear */\r
+#define USBC_UPCON2CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UPCON2CLR) FIFOCON Clear */\r
+#define USBC_UPCON2CLR_PFREEZEC (0x1u << 17) /**< \brief (USBC_UPCON2CLR) PFREEZE Clear */\r
+#define USBC_UPCON2CLR_INITDTGLC (0x1u << 18) /**< \brief (USBC_UPCON2CLR) INITDTGL Clear */\r
+#define USBC_UPCON2CLR_INITBKC (0x1u << 19) /**< \brief (USBC_UPCON2CLR) INITBK Clear */\r
+/* -------- USBC_UPCON3CLR : (USBC Offset: 0x62C) Pipe Control Clear Register -------- */\r
+#define USBC_UPCON3CLR_RXINEC (0x1u << 0) /**< \brief (USBC_UPCON3CLR) RXINE Clear */\r
+#define USBC_UPCON3CLR_TXOUTEC (0x1u << 1) /**< \brief (USBC_UPCON3CLR) TXOUTE Clear */\r
+#define USBC_UPCON3CLR_TXSTPEC (0x1u << 2) /**< \brief (USBC_UPCON3CLR) TXSTPE Clear */\r
+#define USBC_UPCON3CLR_PERREC (0x1u << 3) /**< \brief (USBC_UPCON3CLR) PERRE Clear */\r
+#define USBC_UPCON3CLR_NAKEDEC (0x1u << 4) /**< \brief (USBC_UPCON3CLR) NAKEDE Clear */\r
+#define USBC_UPCON3CLR_ERRORFIEC (0x1u << 5) /**< \brief (USBC_UPCON3CLR) ERRORFIE Clear */\r
+#define USBC_UPCON3CLR_RXSTALLDEC (0x1u << 6) /**< \brief (USBC_UPCON3CLR) RXTALLDE Clear */\r
+#define USBC_UPCON3CLR_RAMACEREC (0x1u << 10) /**< \brief (USBC_UPCON3CLR) RAMACERE Clear */\r
+#define USBC_UPCON3CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UPCON3CLR) NBUSYBKE Clear */\r
+#define USBC_UPCON3CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UPCON3CLR) FIFOCON Clear */\r
+#define USBC_UPCON3CLR_PFREEZEC (0x1u << 17) /**< \brief (USBC_UPCON3CLR) PFREEZE Clear */\r
+#define USBC_UPCON3CLR_INITDTGLC (0x1u << 18) /**< \brief (USBC_UPCON3CLR) INITDTGL Clear */\r
+#define USBC_UPCON3CLR_INITBKC (0x1u << 19) /**< \brief (USBC_UPCON3CLR) INITBK Clear */\r
+/* -------- USBC_UPCON4CLR : (USBC Offset: 0x630) Pipe Control Clear Register -------- */\r
+#define USBC_UPCON4CLR_RXINEC (0x1u << 0) /**< \brief (USBC_UPCON4CLR) RXINE Clear */\r
+#define USBC_UPCON4CLR_TXOUTEC (0x1u << 1) /**< \brief (USBC_UPCON4CLR) TXOUTE Clear */\r
+#define USBC_UPCON4CLR_TXSTPEC (0x1u << 2) /**< \brief (USBC_UPCON4CLR) TXSTPE Clear */\r
+#define USBC_UPCON4CLR_PERREC (0x1u << 3) /**< \brief (USBC_UPCON4CLR) PERRE Clear */\r
+#define USBC_UPCON4CLR_NAKEDEC (0x1u << 4) /**< \brief (USBC_UPCON4CLR) NAKEDE Clear */\r
+#define USBC_UPCON4CLR_ERRORFIEC (0x1u << 5) /**< \brief (USBC_UPCON4CLR) ERRORFIE Clear */\r
+#define USBC_UPCON4CLR_RXSTALLDEC (0x1u << 6) /**< \brief (USBC_UPCON4CLR) RXTALLDE Clear */\r
+#define USBC_UPCON4CLR_RAMACEREC (0x1u << 10) /**< \brief (USBC_UPCON4CLR) RAMACERE Clear */\r
+#define USBC_UPCON4CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UPCON4CLR) NBUSYBKE Clear */\r
+#define USBC_UPCON4CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UPCON4CLR) FIFOCON Clear */\r
+#define USBC_UPCON4CLR_PFREEZEC (0x1u << 17) /**< \brief (USBC_UPCON4CLR) PFREEZE Clear */\r
+#define USBC_UPCON4CLR_INITDTGLC (0x1u << 18) /**< \brief (USBC_UPCON4CLR) INITDTGL Clear */\r
+#define USBC_UPCON4CLR_INITBKC (0x1u << 19) /**< \brief (USBC_UPCON4CLR) INITBK Clear */\r
+/* -------- USBC_UPCON5CLR : (USBC Offset: 0x634) Pipe Control Clear Register -------- */\r
+#define USBC_UPCON5CLR_RXINEC (0x1u << 0) /**< \brief (USBC_UPCON5CLR) RXINE Clear */\r
+#define USBC_UPCON5CLR_TXOUTEC (0x1u << 1) /**< \brief (USBC_UPCON5CLR) TXOUTE Clear */\r
+#define USBC_UPCON5CLR_TXSTPEC (0x1u << 2) /**< \brief (USBC_UPCON5CLR) TXSTPE Clear */\r
+#define USBC_UPCON5CLR_PERREC (0x1u << 3) /**< \brief (USBC_UPCON5CLR) PERRE Clear */\r
+#define USBC_UPCON5CLR_NAKEDEC (0x1u << 4) /**< \brief (USBC_UPCON5CLR) NAKEDE Clear */\r
+#define USBC_UPCON5CLR_ERRORFIEC (0x1u << 5) /**< \brief (USBC_UPCON5CLR) ERRORFIE Clear */\r
+#define USBC_UPCON5CLR_RXSTALLDEC (0x1u << 6) /**< \brief (USBC_UPCON5CLR) RXTALLDE Clear */\r
+#define USBC_UPCON5CLR_RAMACEREC (0x1u << 10) /**< \brief (USBC_UPCON5CLR) RAMACERE Clear */\r
+#define USBC_UPCON5CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UPCON5CLR) NBUSYBKE Clear */\r
+#define USBC_UPCON5CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UPCON5CLR) FIFOCON Clear */\r
+#define USBC_UPCON5CLR_PFREEZEC (0x1u << 17) /**< \brief (USBC_UPCON5CLR) PFREEZE Clear */\r
+#define USBC_UPCON5CLR_INITDTGLC (0x1u << 18) /**< \brief (USBC_UPCON5CLR) INITDTGL Clear */\r
+#define USBC_UPCON5CLR_INITBKC (0x1u << 19) /**< \brief (USBC_UPCON5CLR) INITBK Clear */\r
+/* -------- USBC_UPCON6CLR : (USBC Offset: 0x638) Pipe Control Clear Register -------- */\r
+#define USBC_UPCON6CLR_RXINEC (0x1u << 0) /**< \brief (USBC_UPCON6CLR) RXINE Clear */\r
+#define USBC_UPCON6CLR_TXOUTEC (0x1u << 1) /**< \brief (USBC_UPCON6CLR) TXOUTE Clear */\r
+#define USBC_UPCON6CLR_TXSTPEC (0x1u << 2) /**< \brief (USBC_UPCON6CLR) TXSTPE Clear */\r
+#define USBC_UPCON6CLR_PERREC (0x1u << 3) /**< \brief (USBC_UPCON6CLR) PERRE Clear */\r
+#define USBC_UPCON6CLR_NAKEDEC (0x1u << 4) /**< \brief (USBC_UPCON6CLR) NAKEDE Clear */\r
+#define USBC_UPCON6CLR_ERRORFIEC (0x1u << 5) /**< \brief (USBC_UPCON6CLR) ERRORFIE Clear */\r
+#define USBC_UPCON6CLR_RXSTALLDEC (0x1u << 6) /**< \brief (USBC_UPCON6CLR) RXTALLDE Clear */\r
+#define USBC_UPCON6CLR_RAMACEREC (0x1u << 10) /**< \brief (USBC_UPCON6CLR) RAMACERE Clear */\r
+#define USBC_UPCON6CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UPCON6CLR) NBUSYBKE Clear */\r
+#define USBC_UPCON6CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UPCON6CLR) FIFOCON Clear */\r
+#define USBC_UPCON6CLR_PFREEZEC (0x1u << 17) /**< \brief (USBC_UPCON6CLR) PFREEZE Clear */\r
+#define USBC_UPCON6CLR_INITDTGLC (0x1u << 18) /**< \brief (USBC_UPCON6CLR) INITDTGL Clear */\r
+#define USBC_UPCON6CLR_INITBKC (0x1u << 19) /**< \brief (USBC_UPCON6CLR) INITBK Clear */\r
+/* -------- USBC_UPCON7CLR : (USBC Offset: 0x63C) Pipe Control Clear Register -------- */\r
+#define USBC_UPCON7CLR_RXINEC (0x1u << 0) /**< \brief (USBC_UPCON7CLR) RXINE Clear */\r
+#define USBC_UPCON7CLR_TXOUTEC (0x1u << 1) /**< \brief (USBC_UPCON7CLR) TXOUTE Clear */\r
+#define USBC_UPCON7CLR_TXSTPEC (0x1u << 2) /**< \brief (USBC_UPCON7CLR) TXSTPE Clear */\r
+#define USBC_UPCON7CLR_PERREC (0x1u << 3) /**< \brief (USBC_UPCON7CLR) PERRE Clear */\r
+#define USBC_UPCON7CLR_NAKEDEC (0x1u << 4) /**< \brief (USBC_UPCON7CLR) NAKEDE Clear */\r
+#define USBC_UPCON7CLR_ERRORFIEC (0x1u << 5) /**< \brief (USBC_UPCON7CLR) ERRORFIE Clear */\r
+#define USBC_UPCON7CLR_RXSTALLDEC (0x1u << 6) /**< \brief (USBC_UPCON7CLR) RXTALLDE Clear */\r
+#define USBC_UPCON7CLR_RAMACEREC (0x1u << 10) /**< \brief (USBC_UPCON7CLR) RAMACERE Clear */\r
+#define USBC_UPCON7CLR_NBUSYBKEC (0x1u << 12) /**< \brief (USBC_UPCON7CLR) NBUSYBKE Clear */\r
+#define USBC_UPCON7CLR_FIFOCONC (0x1u << 14) /**< \brief (USBC_UPCON7CLR) FIFOCON Clear */\r
+#define USBC_UPCON7CLR_PFREEZEC (0x1u << 17) /**< \brief (USBC_UPCON7CLR) PFREEZE Clear */\r
+#define USBC_UPCON7CLR_INITDTGLC (0x1u << 18) /**< \brief (USBC_UPCON7CLR) INITDTGL Clear */\r
+#define USBC_UPCON7CLR_INITBKC (0x1u << 19) /**< \brief (USBC_UPCON7CLR) INITBK Clear */\r
+/* -------- USBC_UPINRQ0 : (USBC Offset: 0x650) Pipe In Request -------- */\r
+#define USBC_UPINRQ0_INRQ_Pos 0\r
+#define USBC_UPINRQ0_INRQ_Msk (0xFFu << USBC_UPINRQ0_INRQ_Pos) /**< \brief (USBC_UPINRQ0) IN Request Number before Freeze */\r
+#define USBC_UPINRQ0_INRQ(value) ((USBC_UPINRQ0_INRQ_Msk & ((value) << USBC_UPINRQ0_INRQ_Pos)))\r
+#define USBC_UPINRQ0_INMODE (0x1u << 8) /**< \brief (USBC_UPINRQ0) IN Request Mode */\r
+/* -------- USBC_UPINRQ1 : (USBC Offset: 0x654) Pipe In Request -------- */\r
+#define USBC_UPINRQ1_INRQ_Pos 0\r
+#define USBC_UPINRQ1_INRQ_Msk (0xFFu << USBC_UPINRQ1_INRQ_Pos) /**< \brief (USBC_UPINRQ1) IN Request Number before Freeze */\r
+#define USBC_UPINRQ1_INRQ(value) ((USBC_UPINRQ1_INRQ_Msk & ((value) << USBC_UPINRQ1_INRQ_Pos)))\r
+#define USBC_UPINRQ1_INMODE (0x1u << 8) /**< \brief (USBC_UPINRQ1) IN Request Mode */\r
+/* -------- USBC_UPINRQ2 : (USBC Offset: 0x658) Pipe In Request -------- */\r
+#define USBC_UPINRQ2_INRQ_Pos 0\r
+#define USBC_UPINRQ2_INRQ_Msk (0xFFu << USBC_UPINRQ2_INRQ_Pos) /**< \brief (USBC_UPINRQ2) IN Request Number before Freeze */\r
+#define USBC_UPINRQ2_INRQ(value) ((USBC_UPINRQ2_INRQ_Msk & ((value) << USBC_UPINRQ2_INRQ_Pos)))\r
+#define USBC_UPINRQ2_INMODE (0x1u << 8) /**< \brief (USBC_UPINRQ2) IN Request Mode */\r
+/* -------- USBC_UPINRQ3 : (USBC Offset: 0x65C) Pipe In Request -------- */\r
+#define USBC_UPINRQ3_INRQ_Pos 0\r
+#define USBC_UPINRQ3_INRQ_Msk (0xFFu << USBC_UPINRQ3_INRQ_Pos) /**< \brief (USBC_UPINRQ3) IN Request Number before Freeze */\r
+#define USBC_UPINRQ3_INRQ(value) ((USBC_UPINRQ3_INRQ_Msk & ((value) << USBC_UPINRQ3_INRQ_Pos)))\r
+#define USBC_UPINRQ3_INMODE (0x1u << 8) /**< \brief (USBC_UPINRQ3) IN Request Mode */\r
+/* -------- USBC_UPINRQ4 : (USBC Offset: 0x660) Pipe In Request -------- */\r
+#define USBC_UPINRQ4_INRQ_Pos 0\r
+#define USBC_UPINRQ4_INRQ_Msk (0xFFu << USBC_UPINRQ4_INRQ_Pos) /**< \brief (USBC_UPINRQ4) IN Request Number before Freeze */\r
+#define USBC_UPINRQ4_INRQ(value) ((USBC_UPINRQ4_INRQ_Msk & ((value) << USBC_UPINRQ4_INRQ_Pos)))\r
+#define USBC_UPINRQ4_INMODE (0x1u << 8) /**< \brief (USBC_UPINRQ4) IN Request Mode */\r
+/* -------- USBC_UPINRQ5 : (USBC Offset: 0x664) Pipe In Request -------- */\r
+#define USBC_UPINRQ5_INRQ_Pos 0\r
+#define USBC_UPINRQ5_INRQ_Msk (0xFFu << USBC_UPINRQ5_INRQ_Pos) /**< \brief (USBC_UPINRQ5) IN Request Number before Freeze */\r
+#define USBC_UPINRQ5_INRQ(value) ((USBC_UPINRQ5_INRQ_Msk & ((value) << USBC_UPINRQ5_INRQ_Pos)))\r
+#define USBC_UPINRQ5_INMODE (0x1u << 8) /**< \brief (USBC_UPINRQ5) IN Request Mode */\r
+/* -------- USBC_UPINRQ6 : (USBC Offset: 0x668) Pipe In Request -------- */\r
+#define USBC_UPINRQ6_INRQ_Pos 0\r
+#define USBC_UPINRQ6_INRQ_Msk (0xFFu << USBC_UPINRQ6_INRQ_Pos) /**< \brief (USBC_UPINRQ6) IN Request Number before Freeze */\r
+#define USBC_UPINRQ6_INRQ(value) ((USBC_UPINRQ6_INRQ_Msk & ((value) << USBC_UPINRQ6_INRQ_Pos)))\r
+#define USBC_UPINRQ6_INMODE (0x1u << 8) /**< \brief (USBC_UPINRQ6) IN Request Mode */\r
+/* -------- USBC_UPINRQ7 : (USBC Offset: 0x66C) Pipe In Request -------- */\r
+#define USBC_UPINRQ7_INRQ_Pos 0\r
+#define USBC_UPINRQ7_INRQ_Msk (0xFFu << USBC_UPINRQ7_INRQ_Pos) /**< \brief (USBC_UPINRQ7) IN Request Number before Freeze */\r
+#define USBC_UPINRQ7_INRQ(value) ((USBC_UPINRQ7_INRQ_Msk & ((value) << USBC_UPINRQ7_INRQ_Pos)))\r
+#define USBC_UPINRQ7_INMODE (0x1u << 8) /**< \brief (USBC_UPINRQ7) IN Request Mode */\r
+/* -------- USBC_USBCON : (USBC Offset: 0x800) General Control Register -------- */\r
+#define USBC_USBCON_FRZCLK (0x1u << 14) /**< \brief (USBC_USBCON) Freeze USB Clock */\r
+#define USBC_USBCON_USBE (0x1u << 15) /**< \brief (USBC_USBCON) USBC Enable */\r
+#define USBC_USBCON_UIMOD (0x1u << 24) /**< \brief (USBC_USBCON) USBC Mode */\r
+/* -------- USBC_USBSTA : (USBC Offset: 0x804) General Status Register -------- */\r
+#define USBC_USBSTA_VBUSRQ (0x1u << 9) /**< \brief (USBC_USBSTA) VBus Request */\r
+#define USBC_USBSTA_SPEED_Pos 12\r
+#define USBC_USBSTA_SPEED_Msk (0x3u << USBC_USBSTA_SPEED_Pos) /**< \brief (USBC_USBSTA) Speed Status */\r
+#define USBC_USBSTA_SPEED(value) ((USBC_USBSTA_SPEED_Msk & ((value) << USBC_USBSTA_SPEED_Pos)))\r
+#define USBC_USBSTA_SPEED_FULL (0x0u << 12) /**< \brief (USBC_USBSTA) */\r
+#define USBC_USBSTA_SPEED_HIGH (0x1u << 12) /**< \brief (USBC_USBSTA) */\r
+#define USBC_USBSTA_SPEED_LOW (0x2u << 12) /**< \brief (USBC_USBSTA) */\r
+#define USBC_USBSTA_CLKUSABLE (0x1u << 14) /**< \brief (USBC_USBSTA) USB Clock Usable */\r
+#define USBC_USBSTA_SUSPEND (0x1u << 16) /**< \brief (USBC_USBSTA) Suspend module state */\r
+/* -------- USBC_USBSTACLR : (USBC Offset: 0x808) General Status Clear Register -------- */\r
+#define USBC_USBSTACLR_RAMACERIC (0x1u << 8) /**< \brief (USBC_USBSTACLR) RAMACERI Clear */\r
+#define USBC_USBSTACLR_VBUSRQC (0x1u << 9) /**< \brief (USBC_USBSTACLR) VBUSRQ Clear */\r
+/* -------- USBC_USBSTASET : (USBC Offset: 0x80C) General Status Set Register -------- */\r
+#define USBC_USBSTASET_RAMACERIS (0x1u << 8) /**< \brief (USBC_USBSTASET) RAMACERI Set */\r
+#define USBC_USBSTASET_VBUSRQS (0x1u << 9) /**< \brief (USBC_USBSTASET) VBUSRQ Set */\r
+/* -------- USBC_UVERS : (USBC Offset: 0x818) IP Version Register -------- */\r
+#define USBC_UVERS_VERSION_Pos 0\r
+#define USBC_UVERS_VERSION_Msk (0xFFFu << USBC_UVERS_VERSION_Pos) /**< \brief (USBC_UVERS) Version Number */\r
+#define USBC_UVERS_VERSION(value) ((USBC_UVERS_VERSION_Msk & ((value) << USBC_UVERS_VERSION_Pos)))\r
+#define USBC_UVERS_VARIANT_Pos 16\r
+#define USBC_UVERS_VARIANT_Msk (0x7u << USBC_UVERS_VARIANT_Pos) /**< \brief (USBC_UVERS) Variant Number */\r
+#define USBC_UVERS_VARIANT(value) ((USBC_UVERS_VARIANT_Msk & ((value) << USBC_UVERS_VARIANT_Pos)))\r
+/* -------- USBC_UFEATURES : (USBC Offset: 0x81C) IP Features Register -------- */\r
+#define USBC_UFEATURES_EPTNBRMAX_Pos 0\r
+#define USBC_UFEATURES_EPTNBRMAX_Msk (0xFu << USBC_UFEATURES_EPTNBRMAX_Pos) /**< \brief (USBC_UFEATURES) Maximum Number of Pipes/Endpints */\r
+#define USBC_UFEATURES_EPTNBRMAX(value) ((USBC_UFEATURES_EPTNBRMAX_Msk & ((value) << USBC_UFEATURES_EPTNBRMAX_Pos)))\r
+#define USBC_UFEATURES_UTMIMODE (0x1u << 8) /**< \brief (USBC_UFEATURES) UTMI Mode */\r
+/* -------- USBC_UADDRSIZE : (USBC Offset: 0x820) IP PB address size Register -------- */\r
+#define USBC_UADDRSIZE_UADDRSIZE_Pos 0\r
+#define USBC_UADDRSIZE_UADDRSIZE_Msk (0xFFFFFFFFu << USBC_UADDRSIZE_UADDRSIZE_Pos) /**< \brief (USBC_UADDRSIZE) IP PB Address Size */\r
+#define USBC_UADDRSIZE_UADDRSIZE(value) ((USBC_UADDRSIZE_UADDRSIZE_Msk & ((value) << USBC_UADDRSIZE_UADDRSIZE_Pos)))\r
+/* -------- USBC_UNAME1 : (USBC Offset: 0x824) IP Name Part One: HUSB -------- */\r
+#define USBC_UNAME1_UNAME1_Pos 0\r
+#define USBC_UNAME1_UNAME1_Msk (0xFFFFFFFFu << USBC_UNAME1_UNAME1_Pos) /**< \brief (USBC_UNAME1) IP Name Part One */\r
+#define USBC_UNAME1_UNAME1(value) ((USBC_UNAME1_UNAME1_Msk & ((value) << USBC_UNAME1_UNAME1_Pos)))\r
+/* -------- USBC_UNAME2 : (USBC Offset: 0x828) IP Name Part Two: HOST -------- */\r
+#define USBC_UNAME2_UNAME2_Pos 0\r
+#define USBC_UNAME2_UNAME2_Msk (0xFFFFFFFFu << USBC_UNAME2_UNAME2_Pos) /**< \brief (USBC_UNAME2) IP Name Part Two */\r
+#define USBC_UNAME2_UNAME2(value) ((USBC_UNAME2_UNAME2_Msk & ((value) << USBC_UNAME2_UNAME2_Pos)))\r
+/* -------- USBC_USBFSM : (USBC Offset: 0x82C) USB internal finite state machine -------- */\r
+#define USBC_USBFSM_DRDSTATE_Pos 0\r
+#define USBC_USBFSM_DRDSTATE_Msk (0xFu << USBC_USBFSM_DRDSTATE_Pos) /**< \brief (USBC_USBFSM) DualRoleDevice state */\r
+#define USBC_USBFSM_DRDSTATE(value) ((USBC_USBFSM_DRDSTATE_Msk & ((value) << USBC_USBFSM_DRDSTATE_Pos)))\r
+#define USBC_USBFSM_DRDSTATE_A_IDLE (0x0u << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (USBC_USBFSM) */\r
+#define USBC_USBFSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (USBC_USBFSM) */\r
+/* -------- USBC_UDESC : (USBC Offset: 0x830) Endpoint descriptor table -------- */\r
+#define USBC_UDESC_UDESCA_Pos 0\r
+#define USBC_UDESC_UDESCA_Msk (0xFFFFFFFFu << USBC_UDESC_UDESCA_Pos) /**< \brief (USBC_UDESC) USB Descriptor Address */\r
+#define USBC_UDESC_UDESCA(value) ((USBC_UDESC_UDESCA_Msk & ((value) << USBC_UDESC_UDESCA_Pos)))\r
+\r
+/*@}*/\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR WDT */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4L_WDT Watchdog Timer */\r
+/*@{*/\r
+\r
+#define REV_WDT 0x501\r
+\r
+#ifndef __ASSEMBLY__\r
+/** \brief WDT hardware registers */\r
+typedef struct {\r
+ RwReg WDT_CTRL; /**< \brief (WDT Offset: 0x000) Control Register */\r
+ WoReg WDT_CLR; /**< \brief (WDT Offset: 0x004) Clear Register */\r
+ RoReg WDT_SR; /**< \brief (WDT Offset: 0x008) Status Register */\r
+ WoReg WDT_IER; /**< \brief (WDT Offset: 0x00C) Interrupt Enable Register */\r
+ WoReg WDT_IDR; /**< \brief (WDT Offset: 0x010) Interrupt Disable Register */\r
+ RoReg WDT_IMR; /**< \brief (WDT Offset: 0x014) Interrupt Mask Register */\r
+ RoReg WDT_ISR; /**< \brief (WDT Offset: 0x018) Interrupt Status Register */\r
+ WoReg WDT_ICR; /**< \brief (WDT Offset: 0x01C) Interrupt Clear Register */\r
+ RoReg Reserved1[247];\r
+ RoReg WDT_VERSION; /**< \brief (WDT Offset: 0x3FC) Version Register */\r
+} Wdt;\r
+#endif /* __ASSEMBLY__ */\r
+/* -------- WDT_CTRL : (WDT Offset: 0x000) Control Register -------- */\r
+#define WDT_CTRL_EN (0x1u << 0) /**< \brief (WDT_CTRL) WDT Enable */\r
+#define WDT_CTRL_EN_0 (0x0u << 0) /**< \brief (WDT_CTRL) WDT is disabled. */\r
+#define WDT_CTRL_EN_1 (0x1u << 0) /**< \brief (WDT_CTRL) WDT is enabled */\r
+#define WDT_CTRL_DAR (0x1u << 1) /**< \brief (WDT_CTRL) WDT Disable After Reset */\r
+#define WDT_CTRL_MODE (0x1u << 2) /**< \brief (WDT_CTRL) WDT Mode */\r
+#define WDT_CTRL_SFV (0x1u << 3) /**< \brief (WDT_CTRL) WDT Store Final Value */\r
+#define WDT_CTRL_IM (0x1u << 4) /**< \brief (WDT_CTRL) WDT Interruput Mode */\r
+#define WDT_CTRL_FCD (0x1u << 7) /**< \brief (WDT_CTRL) WDT Fuse Calibration Done */\r
+#define WDT_CTRL_PSEL_Pos 8\r
+#define WDT_CTRL_PSEL_Msk (0x1Fu << WDT_CTRL_PSEL_Pos) /**< \brief (WDT_CTRL) Timeout Prescale Select */\r
+#define WDT_CTRL_PSEL(value) ((WDT_CTRL_PSEL_Msk & ((value) << WDT_CTRL_PSEL_Pos)))\r
+#define WDT_CTRL_CSSEL1 (0x1u << 14) /**< \brief (WDT_CTRL) Clock Source Selection1 */\r
+#define WDT_CTRL_CEN (0x1u << 16) /**< \brief (WDT_CTRL) Clock Enable */\r
+#define WDT_CTRL_CSSEL (0x1u << 17) /**< \brief (WDT_CTRL) Clock Source Selection0 */\r
+#define WDT_CTRL_TBAN_Pos 18\r
+#define WDT_CTRL_TBAN_Msk (0x1Fu << WDT_CTRL_TBAN_Pos) /**< \brief (WDT_CTRL) TBAN Prescale Select */\r
+#define WDT_CTRL_TBAN(value) ((WDT_CTRL_TBAN_Msk & ((value) << WDT_CTRL_TBAN_Pos)))\r
+#define WDT_CTRL_KEY_Pos 24\r
+#define WDT_CTRL_KEY_Msk (0xFFu << WDT_CTRL_KEY_Pos) /**< \brief (WDT_CTRL) Key */\r
+#define WDT_CTRL_KEY(value) ((WDT_CTRL_KEY_Msk & ((value) << WDT_CTRL_KEY_Pos)))\r
+/* -------- WDT_CLR : (WDT Offset: 0x004) Clear Register -------- */\r
+#define WDT_CLR_WDTCLR (0x1u << 0) /**< \brief (WDT_CLR) Clear WDT counter */\r
+#define WDT_CLR_KEY_Pos 24\r
+#define WDT_CLR_KEY_Msk (0xFFu << WDT_CLR_KEY_Pos) /**< \brief (WDT_CLR) Key */\r
+#define WDT_CLR_KEY(value) ((WDT_CLR_KEY_Msk & ((value) << WDT_CLR_KEY_Pos)))\r
+/* -------- WDT_SR : (WDT Offset: 0x008) Status Register -------- */\r
+#define WDT_SR_WINDOW (0x1u << 0) /**< \brief (WDT_SR) WDT in window */\r
+#define WDT_SR_CLEARED (0x1u << 1) /**< \brief (WDT_SR) WDT cleared */\r
+/* -------- WDT_IER : (WDT Offset: 0x00C) Interrupt Enable Register -------- */\r
+#define WDT_IER_WINT (0x1u << 2) /**< \brief (WDT_IER) */\r
+/* -------- WDT_IDR : (WDT Offset: 0x010) Interrupt Disable Register -------- */\r
+#define WDT_IDR_WINT (0x1u << 2) /**< \brief (WDT_IDR) */\r
+/* -------- WDT_IMR : (WDT Offset: 0x014) Interrupt Mask Register -------- */\r
+#define WDT_IMR_WINT (0x1u << 2) /**< \brief (WDT_IMR) */\r
+/* -------- WDT_ISR : (WDT Offset: 0x018) Interrupt Status Register -------- */\r
+#define WDT_ISR_WINT (0x1u << 2) /**< \brief (WDT_ISR) */\r
+/* -------- WDT_ICR : (WDT Offset: 0x01C) Interrupt Clear Register -------- */\r
+#define WDT_ICR_WINT (0x1u << 2) /**< \brief (WDT_ICR) */\r
+/* -------- WDT_VERSION : (WDT Offset: 0x3FC) Version Register -------- */\r
+#define WDT_VERSION_VERSION_Pos 0\r
+#define WDT_VERSION_VERSION_Msk (0xFFFu << WDT_VERSION_VERSION_Pos) /**< \brief (WDT_VERSION) Version number */\r
+#define WDT_VERSION_VERSION(value) ((WDT_VERSION_VERSION_Msk & ((value) << WDT_VERSION_VERSION_Pos)))\r
+#define WDT_VERSION_VARIANT_Pos 16\r
+#define WDT_VERSION_VARIANT_Msk (0xFu << WDT_VERSION_VARIANT_Pos) /**< \brief (WDT_VERSION) Variant number */\r
+#define WDT_VERSION_VARIANT(value) ((WDT_VERSION_VARIANT_Msk & ((value) << WDT_VERSION_VARIANT_Pos)))\r
+\r
+/*@}*/\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** REGISTER ACCESS DEFINITIONS FOR SAM4L */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4L_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+/* ========== Register definition for IISC peripheral ========== */\r
+#define REG_IISC_CR REG_ACCESS(WoReg , 0x40004000U) /**< \brief (IISC) Control Register */ \r
+#define REG_IISC_MR REG_ACCESS(RwReg , 0x40004004U) /**< \brief (IISC) Mode Register */ \r
+#define REG_IISC_SR REG_ACCESS(RoReg , 0x40004008U) /**< \brief (IISC) Status Register */ \r
+#define REG_IISC_SCR REG_ACCESS(WoReg , 0x4000400CU) /**< \brief (IISC) Status Clear Register */ \r
+#define REG_IISC_SSR REG_ACCESS(WoReg , 0x40004010U) /**< \brief (IISC) Status Set Register */ \r
+#define REG_IISC_IER REG_ACCESS(WoReg , 0x40004014U) /**< \brief (IISC) Interrupt Enable Register */ \r
+#define REG_IISC_IDR REG_ACCESS(WoReg , 0x40004018U) /**< \brief (IISC) Interrupt Disable Register */ \r
+#define REG_IISC_IMR REG_ACCESS(RoReg , 0x4000401CU) /**< \brief (IISC) Interrupt Mask Register */ \r
+#define REG_IISC_RHR REG_ACCESS(RoReg , 0x40004020U) /**< \brief (IISC) Receive Holding Register */ \r
+#define REG_IISC_THR REG_ACCESS(WoReg , 0x40004024U) /**< \brief (IISC) Transmit Holding Register */ \r
+#define REG_IISC_VERSION REG_ACCESS(RoReg , 0x40004028U) /**< \brief (IISC) Version Register */ \r
+#define REG_IISC_PARAMETER REG_ACCESS(RoReg , 0x4000402CU) /**< \brief (IISC) Parameter Register */ \r
+/* ========== Register definition for SPI peripheral ========== */\r
+#define REG_SPI_CR REG_ACCESS(WoReg , 0x40008000U) /**< \brief (SPI) Control Register */ \r
+#define REG_SPI_MR REG_ACCESS(RwReg , 0x40008004U) /**< \brief (SPI) Mode Register */ \r
+#define REG_SPI_RDR REG_ACCESS(RoReg , 0x40008008U) /**< \brief (SPI) Receive Data Register */ \r
+#define REG_SPI_TDR REG_ACCESS(WoReg , 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ \r
+#define REG_SPI_SR REG_ACCESS(RoReg , 0x40008010U) /**< \brief (SPI) Status Register */ \r
+#define REG_SPI_IER REG_ACCESS(WoReg , 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ \r
+#define REG_SPI_IDR REG_ACCESS(WoReg , 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ \r
+#define REG_SPI_IMR REG_ACCESS(RoReg , 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ \r
+#define REG_SPI_CSR0 REG_ACCESS(RwReg , 0x40008030U) /**< \brief (SPI) Chip Select Register 0 */ \r
+#define REG_SPI_CSR1 REG_ACCESS(RwReg , 0x40008034U) /**< \brief (SPI) Chip Select Register 1 */ \r
+#define REG_SPI_CSR2 REG_ACCESS(RwReg , 0x40008038U) /**< \brief (SPI) Chip Select Register 2 */ \r
+#define REG_SPI_CSR3 REG_ACCESS(RwReg , 0x4000803CU) /**< \brief (SPI) Chip Select Register 3 */ \r
+#define REG_SPI_WPCR REG_ACCESS(RwReg , 0x400080E4U) /**< \brief (SPI) Write Protection control Register */ \r
+#define REG_SPI_WPSR REG_ACCESS(RoReg , 0x400080E8U) /**< \brief (SPI) Write Protection status Register */ \r
+#define REG_SPI_FEATURES REG_ACCESS(RoReg , 0x400080F8U) /**< \brief (SPI) Features Register */ \r
+#define REG_SPI_VERSION REG_ACCESS(RoReg , 0x400080FCU) /**< \brief (SPI) Version Register */ \r
+/* ========== Register definition for TC0 peripheral ========== */\r
+#define REG_TC0_CCR0 REG_ACCESS(WoReg , 0x40010000U) /**< \brief (TC0) Channel Control Register Channel 0 0 */\r
+#define REG_TC0_CMR0 REG_ACCESS(RwReg , 0x40010004U) /**< \brief (TC0) Channel Mode Register Channel 0 0 */\r
+#define REG_TC0_SMC0 REG_ACCESS(RwReg , 0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register 0 */\r
+#define REG_TC0_CV0 REG_ACCESS(RoReg , 0x40010010U) /**< \brief (TC0) Counter Value Channel 0 0 */\r
+#define REG_TC0_RA0 REG_ACCESS(RwReg , 0x40010014U) /**< \brief (TC0) Register A Channel 0 0 */\r
+#define REG_TC0_RB0 REG_ACCESS(RwReg , 0x40010018U) /**< \brief (TC0) Register B Channel 0 0 */\r
+#define REG_TC0_RC0 REG_ACCESS(RwReg , 0x4001001CU) /**< \brief (TC0) Register C Channel 0 0 */\r
+#define REG_TC0_SR0 REG_ACCESS(RoReg , 0x40010020U) /**< \brief (TC0) Status Register Channel 0 0 */\r
+#define REG_TC0_IER0 REG_ACCESS(WoReg , 0x40010024U) /**< \brief (TC0) Interrupt Enable Register Channel 0 0 */\r
+#define REG_TC0_IDR0 REG_ACCESS(WoReg , 0x40010028U) /**< \brief (TC0) Interrupt Disable Register Channel 0 0 */\r
+#define REG_TC0_IMR0 REG_ACCESS(RoReg , 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register Channel 0 0 */\r
+#define REG_TC0_CCR1 REG_ACCESS(WoReg , 0x40010040U) /**< \brief (TC0) Channel Control Register Channel 0 1 */\r
+#define REG_TC0_CMR1 REG_ACCESS(RwReg , 0x40010044U) /**< \brief (TC0) Channel Mode Register Channel 0 1 */\r
+#define REG_TC0_SMC1 REG_ACCESS(RwReg , 0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register 1 */\r
+#define REG_TC0_CV1 REG_ACCESS(RoReg , 0x40010050U) /**< \brief (TC0) Counter Value Channel 0 1 */\r
+#define REG_TC0_RA1 REG_ACCESS(RwReg , 0x40010054U) /**< \brief (TC0) Register A Channel 0 1 */\r
+#define REG_TC0_RB1 REG_ACCESS(RwReg , 0x40010058U) /**< \brief (TC0) Register B Channel 0 1 */\r
+#define REG_TC0_RC1 REG_ACCESS(RwReg , 0x4001005CU) /**< \brief (TC0) Register C Channel 0 1 */\r
+#define REG_TC0_SR1 REG_ACCESS(RoReg , 0x40010060U) /**< \brief (TC0) Status Register Channel 0 1 */\r
+#define REG_TC0_IER1 REG_ACCESS(WoReg , 0x40010064U) /**< \brief (TC0) Interrupt Enable Register Channel 0 1 */\r
+#define REG_TC0_IDR1 REG_ACCESS(WoReg , 0x40010068U) /**< \brief (TC0) Interrupt Disable Register Channel 0 1 */\r
+#define REG_TC0_IMR1 REG_ACCESS(RoReg , 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register Channel 0 1 */\r
+#define REG_TC0_CCR2 REG_ACCESS(WoReg , 0x40010080U) /**< \brief (TC0) Channel Control Register Channel 0 2 */\r
+#define REG_TC0_CMR2 REG_ACCESS(RwReg , 0x40010084U) /**< \brief (TC0) Channel Mode Register Channel 0 2 */\r
+#define REG_TC0_SMC2 REG_ACCESS(RwReg , 0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register 2 */\r
+#define REG_TC0_CV2 REG_ACCESS(RoReg , 0x40010090U) /**< \brief (TC0) Counter Value Channel 0 2 */\r
+#define REG_TC0_RA2 REG_ACCESS(RwReg , 0x40010094U) /**< \brief (TC0) Register A Channel 0 2 */\r
+#define REG_TC0_RB2 REG_ACCESS(RwReg , 0x40010098U) /**< \brief (TC0) Register B Channel 0 2 */\r
+#define REG_TC0_RC2 REG_ACCESS(RwReg , 0x4001009CU) /**< \brief (TC0) Register C Channel 0 2 */\r
+#define REG_TC0_SR2 REG_ACCESS(RoReg , 0x400100A0U) /**< \brief (TC0) Status Register Channel 0 2 */\r
+#define REG_TC0_IER2 REG_ACCESS(WoReg , 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register Channel 0 2 */\r
+#define REG_TC0_IDR2 REG_ACCESS(WoReg , 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register Channel 0 2 */\r
+#define REG_TC0_IMR2 REG_ACCESS(RoReg , 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register Channel 0 2 */\r
+#define REG_TC0_BCR REG_ACCESS(WoReg , 0x400100C0U) /**< \brief (TC0) TC Block Control Register */ \r
+#define REG_TC0_BMR REG_ACCESS(RwReg , 0x400100C4U) /**< \brief (TC0) TC Block Mode Register */ \r
+#define REG_TC0_WPMR REG_ACCESS(RwReg , 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ \r
+#define REG_TC0_FEATURES REG_ACCESS(RoReg , 0x400100F8U) /**< \brief (TC0) Features Register */ \r
+#define REG_TC0_VERSION REG_ACCESS(RoReg , 0x400100FCU) /**< \brief (TC0) Version Register */ \r
+/* ========== Register definition for TC1 peripheral ========== */\r
+#define REG_TC1_CCR0 REG_ACCESS(WoReg , 0x40014000U) /**< \brief (TC1) Channel Control Register Channel 0 0 */\r
+#define REG_TC1_CMR0 REG_ACCESS(RwReg , 0x40014004U) /**< \brief (TC1) Channel Mode Register Channel 0 0 */\r
+#define REG_TC1_SMC0 REG_ACCESS(RwReg , 0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register 0 */\r
+#define REG_TC1_CV0 REG_ACCESS(RoReg , 0x40014010U) /**< \brief (TC1) Counter Value Channel 0 0 */\r
+#define REG_TC1_RA0 REG_ACCESS(RwReg , 0x40014014U) /**< \brief (TC1) Register A Channel 0 0 */\r
+#define REG_TC1_RB0 REG_ACCESS(RwReg , 0x40014018U) /**< \brief (TC1) Register B Channel 0 0 */\r
+#define REG_TC1_RC0 REG_ACCESS(RwReg , 0x4001401CU) /**< \brief (TC1) Register C Channel 0 0 */\r
+#define REG_TC1_SR0 REG_ACCESS(RoReg , 0x40014020U) /**< \brief (TC1) Status Register Channel 0 0 */\r
+#define REG_TC1_IER0 REG_ACCESS(WoReg , 0x40014024U) /**< \brief (TC1) Interrupt Enable Register Channel 0 0 */\r
+#define REG_TC1_IDR0 REG_ACCESS(WoReg , 0x40014028U) /**< \brief (TC1) Interrupt Disable Register Channel 0 0 */\r
+#define REG_TC1_IMR0 REG_ACCESS(RoReg , 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register Channel 0 0 */\r
+#define REG_TC1_CCR1 REG_ACCESS(WoReg , 0x40014040U) /**< \brief (TC1) Channel Control Register Channel 0 1 */\r
+#define REG_TC1_CMR1 REG_ACCESS(RwReg , 0x40014044U) /**< \brief (TC1) Channel Mode Register Channel 0 1 */\r
+#define REG_TC1_SMC1 REG_ACCESS(RwReg , 0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register 1 */\r
+#define REG_TC1_CV1 REG_ACCESS(RoReg , 0x40014050U) /**< \brief (TC1) Counter Value Channel 0 1 */\r
+#define REG_TC1_RA1 REG_ACCESS(RwReg , 0x40014054U) /**< \brief (TC1) Register A Channel 0 1 */\r
+#define REG_TC1_RB1 REG_ACCESS(RwReg , 0x40014058U) /**< \brief (TC1) Register B Channel 0 1 */\r
+#define REG_TC1_RC1 REG_ACCESS(RwReg , 0x4001405CU) /**< \brief (TC1) Register C Channel 0 1 */\r
+#define REG_TC1_SR1 REG_ACCESS(RoReg , 0x40014060U) /**< \brief (TC1) Status Register Channel 0 1 */\r
+#define REG_TC1_IER1 REG_ACCESS(WoReg , 0x40014064U) /**< \brief (TC1) Interrupt Enable Register Channel 0 1 */\r
+#define REG_TC1_IDR1 REG_ACCESS(WoReg , 0x40014068U) /**< \brief (TC1) Interrupt Disable Register Channel 0 1 */\r
+#define REG_TC1_IMR1 REG_ACCESS(RoReg , 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register Channel 0 1 */\r
+#define REG_TC1_CCR2 REG_ACCESS(WoReg , 0x40014080U) /**< \brief (TC1) Channel Control Register Channel 0 2 */\r
+#define REG_TC1_CMR2 REG_ACCESS(RwReg , 0x40014084U) /**< \brief (TC1) Channel Mode Register Channel 0 2 */\r
+#define REG_TC1_SMC2 REG_ACCESS(RwReg , 0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register 2 */\r
+#define REG_TC1_CV2 REG_ACCESS(RoReg , 0x40014090U) /**< \brief (TC1) Counter Value Channel 0 2 */\r
+#define REG_TC1_RA2 REG_ACCESS(RwReg , 0x40014094U) /**< \brief (TC1) Register A Channel 0 2 */\r
+#define REG_TC1_RB2 REG_ACCESS(RwReg , 0x40014098U) /**< \brief (TC1) Register B Channel 0 2 */\r
+#define REG_TC1_RC2 REG_ACCESS(RwReg , 0x4001409CU) /**< \brief (TC1) Register C Channel 0 2 */\r
+#define REG_TC1_SR2 REG_ACCESS(RoReg , 0x400140A0U) /**< \brief (TC1) Status Register Channel 0 2 */\r
+#define REG_TC1_IER2 REG_ACCESS(WoReg , 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register Channel 0 2 */\r
+#define REG_TC1_IDR2 REG_ACCESS(WoReg , 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register Channel 0 2 */\r
+#define REG_TC1_IMR2 REG_ACCESS(RoReg , 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register Channel 0 2 */\r
+#define REG_TC1_BCR REG_ACCESS(WoReg , 0x400140C0U) /**< \brief (TC1) TC Block Control Register */ \r
+#define REG_TC1_BMR REG_ACCESS(RwReg , 0x400140C4U) /**< \brief (TC1) TC Block Mode Register */ \r
+#define REG_TC1_WPMR REG_ACCESS(RwReg , 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ \r
+#define REG_TC1_FEATURES REG_ACCESS(RoReg , 0x400140F8U) /**< \brief (TC1) Features Register */ \r
+#define REG_TC1_VERSION REG_ACCESS(RoReg , 0x400140FCU) /**< \brief (TC1) Version Register */ \r
+/* ========== Register definition for TWIM0 peripheral ========== */\r
+#define REG_TWIM0_CR REG_ACCESS(WoReg , 0x40018000U) /**< \brief (TWIM0) Control Register */ \r
+#define REG_TWIM0_CWGR REG_ACCESS(RwReg , 0x40018004U) /**< \brief (TWIM0) Clock Waveform Generator Register */ \r
+#define REG_TWIM0_SMBTR REG_ACCESS(RwReg , 0x40018008U) /**< \brief (TWIM0) SMBus Timing Register */ \r
+#define REG_TWIM0_CMDR REG_ACCESS(RwReg , 0x4001800CU) /**< \brief (TWIM0) Command Register */ \r
+#define REG_TWIM0_NCMDR REG_ACCESS(RwReg , 0x40018010U) /**< \brief (TWIM0) Next Command Register */ \r
+#define REG_TWIM0_RHR REG_ACCESS(RoReg , 0x40018014U) /**< \brief (TWIM0) Receive Holding Register */ \r
+#define REG_TWIM0_THR REG_ACCESS(WoReg , 0x40018018U) /**< \brief (TWIM0) Transmit Holding Register */ \r
+#define REG_TWIM0_SR REG_ACCESS(RoReg , 0x4001801CU) /**< \brief (TWIM0) Status Register */ \r
+#define REG_TWIM0_IER REG_ACCESS(WoReg , 0x40018020U) /**< \brief (TWIM0) Interrupt Enable Register */ \r
+#define REG_TWIM0_IDR REG_ACCESS(WoReg , 0x40018024U) /**< \brief (TWIM0) Interrupt Disable Register */ \r
+#define REG_TWIM0_IMR REG_ACCESS(RoReg , 0x40018028U) /**< \brief (TWIM0) Interrupt Mask Register */ \r
+#define REG_TWIM0_SCR REG_ACCESS(WoReg , 0x4001802CU) /**< \brief (TWIM0) Status Clear Register */ \r
+#define REG_TWIM0_PR REG_ACCESS(RoReg , 0x40018030U) /**< \brief (TWIM0) Parameter Register */ \r
+#define REG_TWIM0_VR REG_ACCESS(RoReg , 0x40018034U) /**< \brief (TWIM0) Version Register */ \r
+#define REG_TWIM0_HSCWGR REG_ACCESS(RwReg , 0x40018038U) /**< \brief (TWIM0) HS-mode Clock Waveform Generator */ \r
+#define REG_TWIM0_SRR REG_ACCESS(RwReg , 0x4001803CU) /**< \brief (TWIM0) Slew Rate Register */ \r
+#define REG_TWIM0_HSSRR REG_ACCESS(RwReg , 0x40018040U) /**< \brief (TWIM0) HS-mode Slew Rate Register */ \r
+/* ========== Register definition for TWIS0 peripheral ========== */\r
+#define REG_TWIS0_CR REG_ACCESS(RwReg , 0x40018400U) /**< \brief (TWIS0) Control Register */ \r
+#define REG_TWIS0_NBYTES REG_ACCESS(RwReg , 0x40018404U) /**< \brief (TWIS0) NBYTES Register */ \r
+#define REG_TWIS0_TR REG_ACCESS(RwReg , 0x40018408U) /**< \brief (TWIS0) Timing Register */ \r
+#define REG_TWIS0_RHR REG_ACCESS(RoReg , 0x4001840CU) /**< \brief (TWIS0) Receive Holding Register */ \r
+#define REG_TWIS0_THR REG_ACCESS(WoReg , 0x40018410U) /**< \brief (TWIS0) Transmit Holding Register */ \r
+#define REG_TWIS0_PECR REG_ACCESS(RoReg , 0x40018414U) /**< \brief (TWIS0) Packet Error Check Register */ \r
+#define REG_TWIS0_SR REG_ACCESS(RoReg , 0x40018418U) /**< \brief (TWIS0) Status Register */ \r
+#define REG_TWIS0_IER REG_ACCESS(WoReg , 0x4001841CU) /**< \brief (TWIS0) Interrupt Enable Register */ \r
+#define REG_TWIS0_IDR REG_ACCESS(WoReg , 0x40018420U) /**< \brief (TWIS0) Interrupt Disable Register */ \r
+#define REG_TWIS0_IMR REG_ACCESS(RoReg , 0x40018424U) /**< \brief (TWIS0) Interrupt Mask Register */ \r
+#define REG_TWIS0_SCR REG_ACCESS(WoReg , 0x40018428U) /**< \brief (TWIS0) Status Clear Register */ \r
+#define REG_TWIS0_PR REG_ACCESS(RoReg , 0x4001842CU) /**< \brief (TWIS0) Parameter Register */ \r
+#define REG_TWIS0_VR REG_ACCESS(RoReg , 0x40018430U) /**< \brief (TWIS0) Version Register */ \r
+#define REG_TWIS0_HSTR REG_ACCESS(RwReg , 0x40018434U) /**< \brief (TWIS0) HS-mode Timing Register */ \r
+#define REG_TWIS0_SRR REG_ACCESS(RwReg , 0x40018438U) /**< \brief (TWIS0) Slew Rate Register */ \r
+#define REG_TWIS0_HSSRR REG_ACCESS(RwReg , 0x4001843CU) /**< \brief (TWIS0) HS-mode Slew Rate Register */ \r
+/* ========== Register definition for TWIM1 peripheral ========== */\r
+#define REG_TWIM1_CR REG_ACCESS(WoReg , 0x4001C000U) /**< \brief (TWIM1) Control Register */ \r
+#define REG_TWIM1_CWGR REG_ACCESS(RwReg , 0x4001C004U) /**< \brief (TWIM1) Clock Waveform Generator Register */ \r
+#define REG_TWIM1_SMBTR REG_ACCESS(RwReg , 0x4001C008U) /**< \brief (TWIM1) SMBus Timing Register */ \r
+#define REG_TWIM1_CMDR REG_ACCESS(RwReg , 0x4001C00CU) /**< \brief (TWIM1) Command Register */ \r
+#define REG_TWIM1_NCMDR REG_ACCESS(RwReg , 0x4001C010U) /**< \brief (TWIM1) Next Command Register */ \r
+#define REG_TWIM1_RHR REG_ACCESS(RoReg , 0x4001C014U) /**< \brief (TWIM1) Receive Holding Register */ \r
+#define REG_TWIM1_THR REG_ACCESS(WoReg , 0x4001C018U) /**< \brief (TWIM1) Transmit Holding Register */ \r
+#define REG_TWIM1_SR REG_ACCESS(RoReg , 0x4001C01CU) /**< \brief (TWIM1) Status Register */ \r
+#define REG_TWIM1_IER REG_ACCESS(WoReg , 0x4001C020U) /**< \brief (TWIM1) Interrupt Enable Register */ \r
+#define REG_TWIM1_IDR REG_ACCESS(WoReg , 0x4001C024U) /**< \brief (TWIM1) Interrupt Disable Register */ \r
+#define REG_TWIM1_IMR REG_ACCESS(RoReg , 0x4001C028U) /**< \brief (TWIM1) Interrupt Mask Register */ \r
+#define REG_TWIM1_SCR REG_ACCESS(WoReg , 0x4001C02CU) /**< \brief (TWIM1) Status Clear Register */ \r
+#define REG_TWIM1_PR REG_ACCESS(RoReg , 0x4001C030U) /**< \brief (TWIM1) Parameter Register */ \r
+#define REG_TWIM1_VR REG_ACCESS(RoReg , 0x4001C034U) /**< \brief (TWIM1) Version Register */ \r
+#define REG_TWIM1_HSCWGR REG_ACCESS(RwReg , 0x4001C038U) /**< \brief (TWIM1) HS-mode Clock Waveform Generator */ \r
+#define REG_TWIM1_SRR REG_ACCESS(RwReg , 0x4001C03CU) /**< \brief (TWIM1) Slew Rate Register */ \r
+#define REG_TWIM1_HSSRR REG_ACCESS(RwReg , 0x4001C040U) /**< \brief (TWIM1) HS-mode Slew Rate Register */ \r
+/* ========== Register definition for TWIS1 peripheral ========== */\r
+#define REG_TWIS1_CR REG_ACCESS(RwReg , 0x4001C400U) /**< \brief (TWIS1) Control Register */ \r
+#define REG_TWIS1_NBYTES REG_ACCESS(RwReg , 0x4001C404U) /**< \brief (TWIS1) NBYTES Register */ \r
+#define REG_TWIS1_TR REG_ACCESS(RwReg , 0x4001C408U) /**< \brief (TWIS1) Timing Register */ \r
+#define REG_TWIS1_RHR REG_ACCESS(RoReg , 0x4001C40CU) /**< \brief (TWIS1) Receive Holding Register */ \r
+#define REG_TWIS1_THR REG_ACCESS(WoReg , 0x4001C410U) /**< \brief (TWIS1) Transmit Holding Register */ \r
+#define REG_TWIS1_PECR REG_ACCESS(RoReg , 0x4001C414U) /**< \brief (TWIS1) Packet Error Check Register */ \r
+#define REG_TWIS1_SR REG_ACCESS(RoReg , 0x4001C418U) /**< \brief (TWIS1) Status Register */ \r
+#define REG_TWIS1_IER REG_ACCESS(WoReg , 0x4001C41CU) /**< \brief (TWIS1) Interrupt Enable Register */ \r
+#define REG_TWIS1_IDR REG_ACCESS(WoReg , 0x4001C420U) /**< \brief (TWIS1) Interrupt Disable Register */ \r
+#define REG_TWIS1_IMR REG_ACCESS(RoReg , 0x4001C424U) /**< \brief (TWIS1) Interrupt Mask Register */ \r
+#define REG_TWIS1_SCR REG_ACCESS(WoReg , 0x4001C428U) /**< \brief (TWIS1) Status Clear Register */ \r
+#define REG_TWIS1_PR REG_ACCESS(RoReg , 0x4001C42CU) /**< \brief (TWIS1) Parameter Register */ \r
+#define REG_TWIS1_VR REG_ACCESS(RoReg , 0x4001C430U) /**< \brief (TWIS1) Version Register */ \r
+#define REG_TWIS1_HSTR REG_ACCESS(RwReg , 0x4001C434U) /**< \brief (TWIS1) HS-mode Timing Register */ \r
+#define REG_TWIS1_SRR REG_ACCESS(RwReg , 0x4001C438U) /**< \brief (TWIS1) Slew Rate Register */ \r
+#define REG_TWIS1_HSSRR REG_ACCESS(RwReg , 0x4001C43CU) /**< \brief (TWIS1) HS-mode Slew Rate Register */ \r
+/* ========== Register definition for USART0 peripheral ========== */\r
+#define REG_USART0_CR REG_ACCESS(WoReg , 0x40024000U) /**< \brief (USART0) Control Register */ \r
+#define REG_USART0_MR REG_ACCESS(RwReg , 0x40024004U) /**< \brief (USART0) Mode Register */ \r
+#define REG_USART0_IER REG_ACCESS(WoReg , 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ \r
+#define REG_USART0_IDR REG_ACCESS(WoReg , 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ \r
+#define REG_USART0_IMR REG_ACCESS(RoReg , 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ \r
+#define REG_USART0_CSR REG_ACCESS(RoReg , 0x40024014U) /**< \brief (USART0) Channel Status Register */ \r
+#define REG_USART0_RHR REG_ACCESS(RoReg , 0x40024018U) /**< \brief (USART0) Receiver Holding Register */ \r
+#define REG_USART0_THR REG_ACCESS(WoReg , 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ \r
+#define REG_USART0_BRGR REG_ACCESS(RwReg , 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ \r
+#define REG_USART0_RTOR REG_ACCESS(RwReg , 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ \r
+#define REG_USART0_TTGR REG_ACCESS(RwReg , 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ \r
+#define REG_USART0_FIDI REG_ACCESS(RwReg , 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ \r
+#define REG_USART0_NER REG_ACCESS(RoReg , 0x40024044U) /**< \brief (USART0) Number of Errors Register */ \r
+#define REG_USART0_IFR REG_ACCESS(RwReg , 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ \r
+#define REG_USART0_MAN REG_ACCESS(RwReg , 0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ \r
+#define REG_USART0_LINMR REG_ACCESS(RwReg , 0x40024054U) /**< \brief (USART0) LIN Mode Register */ \r
+#define REG_USART0_LINIR REG_ACCESS(RwReg , 0x40024058U) /**< \brief (USART0) LIN Identifier Register */ \r
+#define REG_USART0_LINBRR REG_ACCESS(RoReg , 0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */ \r
+#define REG_USART0_WPMR REG_ACCESS(RwReg , 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ \r
+#define REG_USART0_WPSR REG_ACCESS(RoReg , 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ \r
+#define REG_USART0_VERSION REG_ACCESS(RoReg , 0x400240FCU) /**< \brief (USART0) Version Register */ \r
+/* ========== Register definition for USART1 peripheral ========== */\r
+#define REG_USART1_CR REG_ACCESS(WoReg , 0x40028000U) /**< \brief (USART1) Control Register */ \r
+#define REG_USART1_MR REG_ACCESS(RwReg , 0x40028004U) /**< \brief (USART1) Mode Register */ \r
+#define REG_USART1_IER REG_ACCESS(WoReg , 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ \r
+#define REG_USART1_IDR REG_ACCESS(WoReg , 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ \r
+#define REG_USART1_IMR REG_ACCESS(RoReg , 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ \r
+#define REG_USART1_CSR REG_ACCESS(RoReg , 0x40028014U) /**< \brief (USART1) Channel Status Register */ \r
+#define REG_USART1_RHR REG_ACCESS(RoReg , 0x40028018U) /**< \brief (USART1) Receiver Holding Register */ \r
+#define REG_USART1_THR REG_ACCESS(WoReg , 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ \r
+#define REG_USART1_BRGR REG_ACCESS(RwReg , 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ \r
+#define REG_USART1_RTOR REG_ACCESS(RwReg , 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ \r
+#define REG_USART1_TTGR REG_ACCESS(RwReg , 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ \r
+#define REG_USART1_FIDI REG_ACCESS(RwReg , 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ \r
+#define REG_USART1_NER REG_ACCESS(RoReg , 0x40028044U) /**< \brief (USART1) Number of Errors Register */ \r
+#define REG_USART1_IFR REG_ACCESS(RwReg , 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ \r
+#define REG_USART1_MAN REG_ACCESS(RwReg , 0x40028050U) /**< \brief (USART1) Manchester Configuration Register */ \r
+#define REG_USART1_LINMR REG_ACCESS(RwReg , 0x40028054U) /**< \brief (USART1) LIN Mode Register */ \r
+#define REG_USART1_LINIR REG_ACCESS(RwReg , 0x40028058U) /**< \brief (USART1) LIN Identifier Register */ \r
+#define REG_USART1_LINBRR REG_ACCESS(RoReg , 0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */ \r
+#define REG_USART1_WPMR REG_ACCESS(RwReg , 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ \r
+#define REG_USART1_WPSR REG_ACCESS(RoReg , 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ \r
+#define REG_USART1_VERSION REG_ACCESS(RoReg , 0x400280FCU) /**< \brief (USART1) Version Register */ \r
+/* ========== Register definition for USART2 peripheral ========== */\r
+#define REG_USART2_CR REG_ACCESS(WoReg , 0x4002C000U) /**< \brief (USART2) Control Register */ \r
+#define REG_USART2_MR REG_ACCESS(RwReg , 0x4002C004U) /**< \brief (USART2) Mode Register */ \r
+#define REG_USART2_IER REG_ACCESS(WoReg , 0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */ \r
+#define REG_USART2_IDR REG_ACCESS(WoReg , 0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */ \r
+#define REG_USART2_IMR REG_ACCESS(RoReg , 0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */ \r
+#define REG_USART2_CSR REG_ACCESS(RoReg , 0x4002C014U) /**< \brief (USART2) Channel Status Register */ \r
+#define REG_USART2_RHR REG_ACCESS(RoReg , 0x4002C018U) /**< \brief (USART2) Receiver Holding Register */ \r
+#define REG_USART2_THR REG_ACCESS(WoReg , 0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */ \r
+#define REG_USART2_BRGR REG_ACCESS(RwReg , 0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */ \r
+#define REG_USART2_RTOR REG_ACCESS(RwReg , 0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */ \r
+#define REG_USART2_TTGR REG_ACCESS(RwReg , 0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */ \r
+#define REG_USART2_FIDI REG_ACCESS(RwReg , 0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */ \r
+#define REG_USART2_NER REG_ACCESS(RoReg , 0x4002C044U) /**< \brief (USART2) Number of Errors Register */ \r
+#define REG_USART2_IFR REG_ACCESS(RwReg , 0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */ \r
+#define REG_USART2_MAN REG_ACCESS(RwReg , 0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */ \r
+#define REG_USART2_LINMR REG_ACCESS(RwReg , 0x4002C054U) /**< \brief (USART2) LIN Mode Register */ \r
+#define REG_USART2_LINIR REG_ACCESS(RwReg , 0x4002C058U) /**< \brief (USART2) LIN Identifier Register */ \r
+#define REG_USART2_LINBRR REG_ACCESS(RoReg , 0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */ \r
+#define REG_USART2_WPMR REG_ACCESS(RwReg , 0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */ \r
+#define REG_USART2_WPSR REG_ACCESS(RoReg , 0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */ \r
+#define REG_USART2_VERSION REG_ACCESS(RoReg , 0x4002C0FCU) /**< \brief (USART2) Version Register */ \r
+/* ========== Register definition for USART3 peripheral ========== */\r
+#define REG_USART3_CR REG_ACCESS(WoReg , 0x40030000U) /**< \brief (USART3) Control Register */ \r
+#define REG_USART3_MR REG_ACCESS(RwReg , 0x40030004U) /**< \brief (USART3) Mode Register */ \r
+#define REG_USART3_IER REG_ACCESS(WoReg , 0x40030008U) /**< \brief (USART3) Interrupt Enable Register */ \r
+#define REG_USART3_IDR REG_ACCESS(WoReg , 0x4003000CU) /**< \brief (USART3) Interrupt Disable Register */ \r
+#define REG_USART3_IMR REG_ACCESS(RoReg , 0x40030010U) /**< \brief (USART3) Interrupt Mask Register */ \r
+#define REG_USART3_CSR REG_ACCESS(RoReg , 0x40030014U) /**< \brief (USART3) Channel Status Register */ \r
+#define REG_USART3_RHR REG_ACCESS(RoReg , 0x40030018U) /**< \brief (USART3) Receiver Holding Register */ \r
+#define REG_USART3_THR REG_ACCESS(WoReg , 0x4003001CU) /**< \brief (USART3) Transmitter Holding Register */ \r
+#define REG_USART3_BRGR REG_ACCESS(RwReg , 0x40030020U) /**< \brief (USART3) Baud Rate Generator Register */ \r
+#define REG_USART3_RTOR REG_ACCESS(RwReg , 0x40030024U) /**< \brief (USART3) Receiver Time-out Register */ \r
+#define REG_USART3_TTGR REG_ACCESS(RwReg , 0x40030028U) /**< \brief (USART3) Transmitter Timeguard Register */ \r
+#define REG_USART3_FIDI REG_ACCESS(RwReg , 0x40030040U) /**< \brief (USART3) FI DI Ratio Register */ \r
+#define REG_USART3_NER REG_ACCESS(RoReg , 0x40030044U) /**< \brief (USART3) Number of Errors Register */ \r
+#define REG_USART3_IFR REG_ACCESS(RwReg , 0x4003004CU) /**< \brief (USART3) IrDA Filter Register */ \r
+#define REG_USART3_MAN REG_ACCESS(RwReg , 0x40030050U) /**< \brief (USART3) Manchester Configuration Register */ \r
+#define REG_USART3_LINMR REG_ACCESS(RwReg , 0x40030054U) /**< \brief (USART3) LIN Mode Register */ \r
+#define REG_USART3_LINIR REG_ACCESS(RwReg , 0x40030058U) /**< \brief (USART3) LIN Identifier Register */ \r
+#define REG_USART3_LINBRR REG_ACCESS(RoReg , 0x4003005CU) /**< \brief (USART3) LIN Baud Rate Register */ \r
+#define REG_USART3_WPMR REG_ACCESS(RwReg , 0x400300E4U) /**< \brief (USART3) Write Protect Mode Register */ \r
+#define REG_USART3_WPSR REG_ACCESS(RoReg , 0x400300E8U) /**< \brief (USART3) Write Protect Status Register */ \r
+#define REG_USART3_VERSION REG_ACCESS(RoReg , 0x400300FCU) /**< \brief (USART3) Version Register */ \r
+/* ========== Register definition for ADCIFE peripheral ========== */\r
+#define REG_ADCIFE_CR REG_ACCESS(WoReg , 0x40038000U) /**< \brief (ADCIFE) Control Register */ \r
+#define REG_ADCIFE_CFG REG_ACCESS(RwReg , 0x40038004U) /**< \brief (ADCIFE) Configuration Register */ \r
+#define REG_ADCIFE_SR REG_ACCESS(RoReg , 0x40038008U) /**< \brief (ADCIFE) Status Register */ \r
+#define REG_ADCIFE_SCR REG_ACCESS(WoReg , 0x4003800CU) /**< \brief (ADCIFE) Status Clear Register */ \r
+#define REG_ADCIFE_RTS REG_ACCESS(RwReg , 0x40038010U) /**< \brief (ADCIFE) Resistive Touch Screen Register */ \r
+#define REG_ADCIFE_SEQCFG REG_ACCESS(RwReg , 0x40038014U) /**< \brief (ADCIFE) Sequencer Configuration Register */ \r
+#define REG_ADCIFE_CDMA REG_ACCESS(WoReg , 0x40038018U) /**< \brief (ADCIFE) Configuration Direct Memory Access Register */ \r
+#define REG_ADCIFE_TIM REG_ACCESS(RwReg , 0x4003801CU) /**< \brief (ADCIFE) Timing Configuration Register */ \r
+#define REG_ADCIFE_ITIMER REG_ACCESS(RwReg , 0x40038020U) /**< \brief (ADCIFE) Internal Timer Register */ \r
+#define REG_ADCIFE_WCFG REG_ACCESS(RwReg , 0x40038024U) /**< \brief (ADCIFE) Window Monitor Configuration Register */ \r
+#define REG_ADCIFE_WTH REG_ACCESS(RwReg , 0x40038028U) /**< \brief (ADCIFE) Window Monitor Threshold Configuration Register */ \r
+#define REG_ADCIFE_LCV REG_ACCESS(RoReg , 0x4003802CU) /**< \brief (ADCIFE) Sequencer Last Converted Value Register */ \r
+#define REG_ADCIFE_IER REG_ACCESS(WoReg , 0x40038030U) /**< \brief (ADCIFE) Interrupt Enable Register */ \r
+#define REG_ADCIFE_IDR REG_ACCESS(WoReg , 0x40038034U) /**< \brief (ADCIFE) Interrupt Disable Register */ \r
+#define REG_ADCIFE_IMR REG_ACCESS(RoReg , 0x40038038U) /**< \brief (ADCIFE) Interrupt Mask Register */ \r
+#define REG_ADCIFE_CALIB REG_ACCESS(RwReg , 0x4003803CU) /**< \brief (ADCIFE) Calibration Register */ \r
+#define REG_ADCIFE_VERSION REG_ACCESS(RoReg , 0x40038040U) /**< \brief (ADCIFE) Version Register */ \r
+#define REG_ADCIFE_PARAMETER REG_ACCESS(RoReg , 0x40038044U) /**< \brief (ADCIFE) Parameter Register */ \r
+/* ========== Register definition for DACC peripheral ========== */\r
+#define REG_DACC_CR REG_ACCESS(WoReg , 0x4003C000U) /**< \brief (DACC) Control Register */ \r
+#define REG_DACC_MR REG_ACCESS(RwReg , 0x4003C004U) /**< \brief (DACC) Mode Register */ \r
+#define REG_DACC_CDR REG_ACCESS(WoReg , 0x4003C008U) /**< \brief (DACC) Conversion Data Register */ \r
+#define REG_DACC_IER REG_ACCESS(WoReg , 0x4003C00CU) /**< \brief (DACC) Interrupt Enable Register */ \r
+#define REG_DACC_IDR REG_ACCESS(WoReg , 0x4003C010U) /**< \brief (DACC) Interrupt Disable Register */ \r
+#define REG_DACC_IMR REG_ACCESS(RoReg , 0x4003C014U) /**< \brief (DACC) Interrupt Mask Register */ \r
+#define REG_DACC_ISR REG_ACCESS(RoReg , 0x4003C018U) /**< \brief (DACC) Interrupt Status Register */ \r
+#define REG_DACC_WPMR REG_ACCESS(RwReg , 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode Register */ \r
+#define REG_DACC_WPSR REG_ACCESS(RoReg , 0x4003C0E8U) /**< \brief (DACC) Write Protect Status Register */ \r
+#define REG_DACC_VERSION REG_ACCESS(RoReg , 0x4003C0FCU) /**< \brief (DACC) Version Register */ \r
+/* ========== Register definition for ACIFC peripheral ========== */\r
+#define REG_ACIFC_CTRL REG_ACCESS(RwReg , 0x40040000U) /**< \brief (ACIFC) Control Register */ \r
+#define REG_ACIFC_SR REG_ACCESS(RoReg , 0x40040004U) /**< \brief (ACIFC) Status Register */ \r
+#define REG_ACIFC_IER REG_ACCESS(WoReg , 0x40040010U) /**< \brief (ACIFC) Interrupt Enable Register */ \r
+#define REG_ACIFC_IDR REG_ACCESS(WoReg , 0x40040014U) /**< \brief (ACIFC) Interrupt Disable Register */ \r
+#define REG_ACIFC_IMR REG_ACCESS(RoReg , 0x40040018U) /**< \brief (ACIFC) Interrupt Mask Register */ \r
+#define REG_ACIFC_ISR REG_ACCESS(RoReg , 0x4004001CU) /**< \brief (ACIFC) Interrupt Status Register */ \r
+#define REG_ACIFC_ICR REG_ACCESS(WoReg , 0x40040020U) /**< \brief (ACIFC) Interrupt Status Clear Register */ \r
+#define REG_ACIFC_TR REG_ACCESS(RwReg , 0x40040024U) /**< \brief (ACIFC) Test Register */ \r
+#define REG_ACIFC_PARAMETER REG_ACCESS(RoReg , 0x40040030U) /**< \brief (ACIFC) Parameter Register */ \r
+#define REG_ACIFC_VERSION REG_ACCESS(RoReg , 0x40040034U) /**< \brief (ACIFC) Version Register */ \r
+#define REG_ACIFC_CONFW0 REG_ACCESS(RwReg , 0x40040080U) /**< \brief (ACIFC) Window configuration Register 0 */\r
+#define REG_ACIFC_CONFW1 REG_ACCESS(RwReg , 0x40040084U) /**< \brief (ACIFC) Window configuration Register 1 */\r
+#define REG_ACIFC_CONFW2 REG_ACCESS(RwReg , 0x40040088U) /**< \brief (ACIFC) Window configuration Register 2 */\r
+#define REG_ACIFC_CONFW3 REG_ACCESS(RwReg , 0x4004008CU) /**< \brief (ACIFC) Window configuration Register 3 */\r
+#define REG_ACIFC_CONF0 REG_ACCESS(RwReg , 0x400400D0U) /**< \brief (ACIFC) AC Configuration Register 0 */\r
+#define REG_ACIFC_CONF1 REG_ACCESS(RwReg , 0x400400D4U) /**< \brief (ACIFC) AC Configuration Register 1 */\r
+#define REG_ACIFC_CONF2 REG_ACCESS(RwReg , 0x400400D8U) /**< \brief (ACIFC) AC Configuration Register 2 */\r
+#define REG_ACIFC_CONF3 REG_ACCESS(RwReg , 0x400400DCU) /**< \brief (ACIFC) AC Configuration Register 3 */\r
+#define REG_ACIFC_CONF4 REG_ACCESS(RwReg , 0x400400E0U) /**< \brief (ACIFC) AC Configuration Register 4 */\r
+#define REG_ACIFC_CONF5 REG_ACCESS(RwReg , 0x400400E4U) /**< \brief (ACIFC) AC Configuration Register 5 */\r
+#define REG_ACIFC_CONF6 REG_ACCESS(RwReg , 0x400400E8U) /**< \brief (ACIFC) AC Configuration Register 6 */\r
+#define REG_ACIFC_CONF7 REG_ACCESS(RwReg , 0x400400ECU) /**< \brief (ACIFC) AC Configuration Register 7 */\r
+/* ========== Register definition for GLOC peripheral ========== */\r
+#define REG_GLOC_CR0 REG_ACCESS(RwReg , 0x40060000U) /**< \brief (GLOC) Control Register 0 */\r
+#define REG_GLOC_TRUTH0 REG_ACCESS(RwReg , 0x40060004U) /**< \brief (GLOC) Truth Register 0 */\r
+#define REG_GLOC_CR1 REG_ACCESS(RwReg , 0x40060008U) /**< \brief (GLOC) Control Register 1 */\r
+#define REG_GLOC_TRUTH1 REG_ACCESS(RwReg , 0x4006000CU) /**< \brief (GLOC) Truth Register 1 */\r
+#define REG_GLOC_PARAMETER REG_ACCESS(RoReg , 0x40060038U) /**< \brief (GLOC) Parameter Register */ \r
+#define REG_GLOC_VERSION REG_ACCESS(RoReg , 0x4006003CU) /**< \brief (GLOC) Version Register */ \r
+/* ========== Register definition for ABDACB peripheral ========== */\r
+#define REG_ABDACB_CR REG_ACCESS(RwReg , 0x40064000U) /**< \brief (ABDACB) Control Register */ \r
+#define REG_ABDACB_SDR0 REG_ACCESS(RwReg , 0x40064004U) /**< \brief (ABDACB) Sample Data Register 0 */ \r
+#define REG_ABDACB_SDR1 REG_ACCESS(RwReg , 0x40064008U) /**< \brief (ABDACB) Sample Data Register 1 */ \r
+#define REG_ABDACB_VCR0 REG_ACCESS(RwReg , 0x4006400CU) /**< \brief (ABDACB) Volume Control Register 0 */ \r
+#define REG_ABDACB_VCR1 REG_ACCESS(RwReg , 0x40064010U) /**< \brief (ABDACB) Volume Control Register 1 */ \r
+#define REG_ABDACB_IER REG_ACCESS(WoReg , 0x40064014U) /**< \brief (ABDACB) Interrupt Enable Register */ \r
+#define REG_ABDACB_IDR REG_ACCESS(WoReg , 0x40064018U) /**< \brief (ABDACB) Interupt Disable Register */ \r
+#define REG_ABDACB_IMR REG_ACCESS(RoReg , 0x4006401CU) /**< \brief (ABDACB) Interrupt Mask Register */ \r
+#define REG_ABDACB_SR REG_ACCESS(RoReg , 0x40064020U) /**< \brief (ABDACB) Status Register */ \r
+#define REG_ABDACB_SCR REG_ACCESS(WoReg , 0x40064024U) /**< \brief (ABDACB) Status Clear Register */ \r
+#define REG_ABDACB_PARAMETER REG_ACCESS(RoReg , 0x40064028U) /**< \brief (ABDACB) Parameter Register */ \r
+#define REG_ABDACB_VERSION REG_ACCESS(RoReg , 0x4006402CU) /**< \brief (ABDACB) Version Register */ \r
+/* ========== Register definition for TRNG peripheral ========== */\r
+#define REG_TRNG_CR REG_ACCESS(WoReg , 0x40068000U) /**< \brief (TRNG) Control Register */ \r
+#define REG_TRNG_IER REG_ACCESS(WoReg , 0x40068010U) /**< \brief (TRNG) Interrupt Enable Register */ \r
+#define REG_TRNG_IDR REG_ACCESS(WoReg , 0x40068014U) /**< \brief (TRNG) Interrupt Disable Register */ \r
+#define REG_TRNG_IMR REG_ACCESS(RoReg , 0x40068018U) /**< \brief (TRNG) Interrupt Mask Register */ \r
+#define REG_TRNG_ISR REG_ACCESS(RoReg , 0x4006801CU) /**< \brief (TRNG) Interrupt Status Register */ \r
+#define REG_TRNG_ODATA REG_ACCESS(RoReg , 0x40068050U) /**< \brief (TRNG) Output Data Register */ \r
+#define REG_TRNG_VERSION REG_ACCESS(RoReg , 0x400680FCU) /**< \brief (TRNG) Version Register */ \r
+/* ========== Register definition for PARC peripheral ========== */\r
+#define REG_PARC_CFG REG_ACCESS(RwReg , 0x4006C000U) /**< \brief (PARC) Configuration Register */ \r
+#define REG_PARC_CR REG_ACCESS(RwReg , 0x4006C004U) /**< \brief (PARC) Control Register */ \r
+#define REG_PARC_IER REG_ACCESS(WoReg , 0x4006C008U) /**< \brief (PARC) Interrupt Enable Register */ \r
+#define REG_PARC_IDR REG_ACCESS(WoReg , 0x4006C00CU) /**< \brief (PARC) Interrupt Disable Register */ \r
+#define REG_PARC_IMR REG_ACCESS(RoReg , 0x4006C010U) /**< \brief (PARC) Interrupt Mask Register */ \r
+#define REG_PARC_SR REG_ACCESS(RoReg , 0x4006C014U) /**< \brief (PARC) Status Register */ \r
+#define REG_PARC_ICR REG_ACCESS(WoReg , 0x4006C018U) /**< \brief (PARC) Interrupt Status Clear Register */ \r
+#define REG_PARC_RHR REG_ACCESS(RoReg , 0x4006C01CU) /**< \brief (PARC) Receive Holding Register */ \r
+#define REG_PARC_VERSION REG_ACCESS(RoReg , 0x4006C020U) /**< \brief (PARC) Version Register */ \r
+/* ========== Register definition for CATB peripheral ========== */\r
+#define REG_CATB_CR REG_ACCESS(RwReg , 0x40070000U) /**< \brief (CATB) Control Register */ \r
+#define REG_CATB_CNTCR REG_ACCESS(RwReg , 0x40070004U) /**< \brief (CATB) Counter Control Register */ \r
+#define REG_CATB_IDLE REG_ACCESS(RwReg , 0x40070008U) /**< \brief (CATB) Sensor Idle Level */ \r
+#define REG_CATB_LEVEL REG_ACCESS(RoReg , 0x4007000CU) /**< \brief (CATB) Sensor Relative Level */ \r
+#define REG_CATB_RAW REG_ACCESS(RoReg , 0x40070010U) /**< \brief (CATB) Sensor Raw Value */ \r
+#define REG_CATB_TIMING REG_ACCESS(RwReg , 0x40070014U) /**< \brief (CATB) Filter Timing Register */ \r
+#define REG_CATB_THRESH REG_ACCESS(RwReg , 0x40070018U) /**< \brief (CATB) Threshold Register */ \r
+#define REG_CATB_PINSEL REG_ACCESS(RwReg , 0x4007001CU) /**< \brief (CATB) Pin Selection Register */ \r
+#define REG_CATB_DMA REG_ACCESS(RwReg , 0x40070020U) /**< \brief (CATB) Direct Memory Access Register */ \r
+#define REG_CATB_ISR REG_ACCESS(RoReg , 0x40070024U) /**< \brief (CATB) Interrupt Status Register */ \r
+#define REG_CATB_IER REG_ACCESS(WoReg , 0x40070028U) /**< \brief (CATB) Interrupt Enable Register */ \r
+#define REG_CATB_IDR REG_ACCESS(WoReg , 0x4007002CU) /**< \brief (CATB) Interrupt Disable Register */ \r
+#define REG_CATB_IMR REG_ACCESS(RoReg , 0x40070030U) /**< \brief (CATB) Interrupt Mask Register */ \r
+#define REG_CATB_SCR REG_ACCESS(WoReg , 0x40070034U) /**< \brief (CATB) Status Clear Register */ \r
+#define REG_CATB_INTCH0 REG_ACCESS(RoReg , 0x40070040U) /**< \brief (CATB) In-Touch Status Register 0 0 */\r
+#define REG_CATB_INTCHCLR0 REG_ACCESS(WoReg , 0x40070050U) /**< \brief (CATB) In-Touch Status Clear Register 0 0 */\r
+#define REG_CATB_OUTTCH0 REG_ACCESS(RoReg , 0x40070060U) /**< \brief (CATB) Out-of-Touch Status Register 0 0 */\r
+#define REG_CATB_OUTTCHCLR0 REG_ACCESS(WoReg , 0x40070070U) /**< \brief (CATB) Out-of-Touch Status Clear Register 0 0 */\r
+#define REG_CATB_PARAMETER REG_ACCESS(RoReg , 0x400700F8U) /**< \brief (CATB) Parameter Register */ \r
+#define REG_CATB_VERSION REG_ACCESS(RoReg , 0x400700FCU) /**< \brief (CATB) Version Register */ \r
+/* ========== Register definition for TWIM2 peripheral ========== */\r
+#define REG_TWIM2_CR REG_ACCESS(WoReg , 0x40078000U) /**< \brief (TWIM2) Control Register */ \r
+#define REG_TWIM2_CWGR REG_ACCESS(RwReg , 0x40078004U) /**< \brief (TWIM2) Clock Waveform Generator Register */ \r
+#define REG_TWIM2_SMBTR REG_ACCESS(RwReg , 0x40078008U) /**< \brief (TWIM2) SMBus Timing Register */ \r
+#define REG_TWIM2_CMDR REG_ACCESS(RwReg , 0x4007800CU) /**< \brief (TWIM2) Command Register */ \r
+#define REG_TWIM2_NCMDR REG_ACCESS(RwReg , 0x40078010U) /**< \brief (TWIM2) Next Command Register */ \r
+#define REG_TWIM2_RHR REG_ACCESS(RoReg , 0x40078014U) /**< \brief (TWIM2) Receive Holding Register */ \r
+#define REG_TWIM2_THR REG_ACCESS(WoReg , 0x40078018U) /**< \brief (TWIM2) Transmit Holding Register */ \r
+#define REG_TWIM2_SR REG_ACCESS(RoReg , 0x4007801CU) /**< \brief (TWIM2) Status Register */ \r
+#define REG_TWIM2_IER REG_ACCESS(WoReg , 0x40078020U) /**< \brief (TWIM2) Interrupt Enable Register */ \r
+#define REG_TWIM2_IDR REG_ACCESS(WoReg , 0x40078024U) /**< \brief (TWIM2) Interrupt Disable Register */ \r
+#define REG_TWIM2_IMR REG_ACCESS(RoReg , 0x40078028U) /**< \brief (TWIM2) Interrupt Mask Register */ \r
+#define REG_TWIM2_SCR REG_ACCESS(WoReg , 0x4007802CU) /**< \brief (TWIM2) Status Clear Register */ \r
+#define REG_TWIM2_PR REG_ACCESS(RoReg , 0x40078030U) /**< \brief (TWIM2) Parameter Register */ \r
+#define REG_TWIM2_VR REG_ACCESS(RoReg , 0x40078034U) /**< \brief (TWIM2) Version Register */ \r
+#define REG_TWIM2_HSCWGR REG_ACCESS(RwReg , 0x40078038U) /**< \brief (TWIM2) HS-mode Clock Waveform Generator */ \r
+#define REG_TWIM2_SRR REG_ACCESS(RwReg , 0x4007803CU) /**< \brief (TWIM2) Slew Rate Register */ \r
+#define REG_TWIM2_HSSRR REG_ACCESS(RwReg , 0x40078040U) /**< \brief (TWIM2) HS-mode Slew Rate Register */ \r
+/* ========== Register definition for TWIM3 peripheral ========== */\r
+#define REG_TWIM3_CR REG_ACCESS(WoReg , 0x4007C000U) /**< \brief (TWIM3) Control Register */ \r
+#define REG_TWIM3_CWGR REG_ACCESS(RwReg , 0x4007C004U) /**< \brief (TWIM3) Clock Waveform Generator Register */ \r
+#define REG_TWIM3_SMBTR REG_ACCESS(RwReg , 0x4007C008U) /**< \brief (TWIM3) SMBus Timing Register */ \r
+#define REG_TWIM3_CMDR REG_ACCESS(RwReg , 0x4007C00CU) /**< \brief (TWIM3) Command Register */ \r
+#define REG_TWIM3_NCMDR REG_ACCESS(RwReg , 0x4007C010U) /**< \brief (TWIM3) Next Command Register */ \r
+#define REG_TWIM3_RHR REG_ACCESS(RoReg , 0x4007C014U) /**< \brief (TWIM3) Receive Holding Register */ \r
+#define REG_TWIM3_THR REG_ACCESS(WoReg , 0x4007C018U) /**< \brief (TWIM3) Transmit Holding Register */ \r
+#define REG_TWIM3_SR REG_ACCESS(RoReg , 0x4007C01CU) /**< \brief (TWIM3) Status Register */ \r
+#define REG_TWIM3_IER REG_ACCESS(WoReg , 0x4007C020U) /**< \brief (TWIM3) Interrupt Enable Register */ \r
+#define REG_TWIM3_IDR REG_ACCESS(WoReg , 0x4007C024U) /**< \brief (TWIM3) Interrupt Disable Register */ \r
+#define REG_TWIM3_IMR REG_ACCESS(RoReg , 0x4007C028U) /**< \brief (TWIM3) Interrupt Mask Register */ \r
+#define REG_TWIM3_SCR REG_ACCESS(WoReg , 0x4007C02CU) /**< \brief (TWIM3) Status Clear Register */ \r
+#define REG_TWIM3_PR REG_ACCESS(RoReg , 0x4007C030U) /**< \brief (TWIM3) Parameter Register */ \r
+#define REG_TWIM3_VR REG_ACCESS(RoReg , 0x4007C034U) /**< \brief (TWIM3) Version Register */ \r
+#define REG_TWIM3_HSCWGR REG_ACCESS(RwReg , 0x4007C038U) /**< \brief (TWIM3) HS-mode Clock Waveform Generator */ \r
+#define REG_TWIM3_SRR REG_ACCESS(RwReg , 0x4007C03CU) /**< \brief (TWIM3) Slew Rate Register */ \r
+#define REG_TWIM3_HSSRR REG_ACCESS(RwReg , 0x4007C040U) /**< \brief (TWIM3) HS-mode Slew Rate Register */ \r
+/* ========== Register definition for LCDCA peripheral ========== */\r
+#define REG_LCDCA_CR REG_ACCESS(WoReg , 0x40080000U) /**< \brief (LCDCA) Control Register */ \r
+#define REG_LCDCA_CFG REG_ACCESS(RwReg , 0x40080004U) /**< \brief (LCDCA) Configuration Register */ \r
+#define REG_LCDCA_TIM REG_ACCESS(RwReg , 0x40080008U) /**< \brief (LCDCA) Timing Register */ \r
+#define REG_LCDCA_SR REG_ACCESS(RoReg , 0x4008000CU) /**< \brief (LCDCA) Status Register */ \r
+#define REG_LCDCA_SCR REG_ACCESS(WoReg , 0x40080010U) /**< \brief (LCDCA) Status Clear Register */ \r
+#define REG_LCDCA_DRL0 REG_ACCESS(RwReg , 0x40080014U) /**< \brief (LCDCA) Data Register Low 0 */ \r
+#define REG_LCDCA_DRH0 REG_ACCESS(RwReg , 0x40080018U) /**< \brief (LCDCA) Data Register High 0 */ \r
+#define REG_LCDCA_DRL1 REG_ACCESS(RwReg , 0x4008001CU) /**< \brief (LCDCA) Data Register Low 1 */ \r
+#define REG_LCDCA_DRH1 REG_ACCESS(RwReg , 0x40080020U) /**< \brief (LCDCA) Data Register High 1 */ \r
+#define REG_LCDCA_DRL2 REG_ACCESS(RwReg , 0x40080024U) /**< \brief (LCDCA) Data Register Low 2 */ \r
+#define REG_LCDCA_DRH2 REG_ACCESS(RwReg , 0x40080028U) /**< \brief (LCDCA) Data Register High 2 */ \r
+#define REG_LCDCA_DRL3 REG_ACCESS(RwReg , 0x4008002CU) /**< \brief (LCDCA) Data Register Low 3 */ \r
+#define REG_LCDCA_DRH3 REG_ACCESS(RwReg , 0x40080030U) /**< \brief (LCDCA) Data Register High 3 */ \r
+#define REG_LCDCA_IADR REG_ACCESS(WoReg , 0x40080034U) /**< \brief (LCDCA) Indirect Access Data Register */ \r
+#define REG_LCDCA_BCFG REG_ACCESS(RwReg , 0x40080038U) /**< \brief (LCDCA) Blink Configuration Register */ \r
+#define REG_LCDCA_CSRCFG REG_ACCESS(RwReg , 0x4008003CU) /**< \brief (LCDCA) Circular Shift Register Configuration */ \r
+#define REG_LCDCA_CMCFG REG_ACCESS(RwReg , 0x40080040U) /**< \brief (LCDCA) Character Mapping Configuration Register */ \r
+#define REG_LCDCA_CMDR REG_ACCESS(WoReg , 0x40080044U) /**< \brief (LCDCA) Character Mapping Data Register */ \r
+#define REG_LCDCA_ACMCFG REG_ACCESS(RwReg , 0x40080048U) /**< \brief (LCDCA) Automated Character Mapping Configuration Register */ \r
+#define REG_LCDCA_ACMDR REG_ACCESS(WoReg , 0x4008004CU) /**< \brief (LCDCA) Automated Character Mapping Data Register */ \r
+#define REG_LCDCA_ABMCFG REG_ACCESS(RwReg , 0x40080050U) /**< \brief (LCDCA) Automated Bit Mapping Configuration Register */ \r
+#define REG_LCDCA_ABMDR REG_ACCESS(WoReg , 0x40080054U) /**< \brief (LCDCA) Automated Bit Mapping Data Register */ \r
+#define REG_LCDCA_IER REG_ACCESS(WoReg , 0x40080058U) /**< \brief (LCDCA) Interrupt Enable Register */ \r
+#define REG_LCDCA_IDR REG_ACCESS(WoReg , 0x4008005CU) /**< \brief (LCDCA) Interrupt Disable Register */ \r
+#define REG_LCDCA_IMR REG_ACCESS(RoReg , 0x40080060U) /**< \brief (LCDCA) Interrupt Mask Register */ \r
+#define REG_LCDCA_VERSION REG_ACCESS(RoReg , 0x40080064U) /**< \brief (LCDCA) Version Register */ \r
+/* ========== Register definition for HFLASHC peripheral ========== */\r
+#define REG_HFLASHC_FCR REG_ACCESS(RwReg , 0x400A0000U) /**< \brief (HFLASHC) Flash Controller Control Register */ \r
+#define REG_HFLASHC_FCMD REG_ACCESS(RwReg , 0x400A0004U) /**< \brief (HFLASHC) Flash Controller Command Register */ \r
+#define REG_HFLASHC_FSR REG_ACCESS(RwReg , 0x400A0008U) /**< \brief (HFLASHC) Flash Controller Status Register */ \r
+#define REG_HFLASHC_FPR REG_ACCESS(RoReg , 0x400A000CU) /**< \brief (HFLASHC) Flash Controller Parameter Register */ \r
+#define REG_HFLASHC_VERSION REG_ACCESS(RoReg , 0x400A0010U) /**< \brief (HFLASHC) Flash Controller Version Register */ \r
+#define REG_HFLASHC_FGPFRHI REG_ACCESS(RwReg , 0x400A0014U) /**< \brief (HFLASHC) Flash Controller General Purpose Fuse Register High */ \r
+#define REG_HFLASHC_FGPFRLO REG_ACCESS(RwReg , 0x400A0018U) /**< \brief (HFLASHC) Flash Controller General Purpose Fuse Register Low */ \r
+/* ========== Register definition for HCACHE peripheral ========== */\r
+#define REG_HCACHE_CTRL REG_ACCESS(WoReg , 0x400A0408U) /**< \brief (HCACHE) Control Register */ \r
+#define REG_HCACHE_SR REG_ACCESS(RwReg , 0x400A040CU) /**< \brief (HCACHE) Status Register */ \r
+#define REG_HCACHE_MAINT0 REG_ACCESS(WoReg , 0x400A0420U) /**< \brief (HCACHE) Maintenance Register 0 */ \r
+#define REG_HCACHE_MAINT1 REG_ACCESS(WoReg , 0x400A0424U) /**< \brief (HCACHE) Maintenance Register 1 */ \r
+#define REG_HCACHE_MCFG REG_ACCESS(RwReg , 0x400A0428U) /**< \brief (HCACHE) Monitor Configuration Register */ \r
+#define REG_HCACHE_MEN REG_ACCESS(RwReg , 0x400A042CU) /**< \brief (HCACHE) Monitor Enable Register */ \r
+#define REG_HCACHE_MCTRL REG_ACCESS(WoReg , 0x400A0430U) /**< \brief (HCACHE) Monitor Control Register */ \r
+#define REG_HCACHE_MSR REG_ACCESS(RoReg , 0x400A0434U) /**< \brief (HCACHE) Monitor Status Register */ \r
+#define REG_HCACHE_VERSION REG_ACCESS(RoReg , 0x400A04FCU) /**< \brief (HCACHE) Version Register */ \r
+/* ========== Register definition for HMATRIX peripheral ========== */\r
+#define REG_HMATRIX_MCFG0 REG_ACCESS(RwReg , 0x400A1000U) /**< \brief (HMATRIX) Master Configuration Register 0 0 */\r
+#define REG_HMATRIX_MCFG1 REG_ACCESS(RwReg , 0x400A1004U) /**< \brief (HMATRIX) Master Configuration Register 0 1 */\r
+#define REG_HMATRIX_MCFG2 REG_ACCESS(RwReg , 0x400A1008U) /**< \brief (HMATRIX) Master Configuration Register 0 2 */\r
+#define REG_HMATRIX_MCFG3 REG_ACCESS(RwReg , 0x400A100CU) /**< \brief (HMATRIX) Master Configuration Register 0 3 */\r
+#define REG_HMATRIX_MCFG4 REG_ACCESS(RwReg , 0x400A1010U) /**< \brief (HMATRIX) Master Configuration Register 0 4 */\r
+#define REG_HMATRIX_MCFG5 REG_ACCESS(RwReg , 0x400A1014U) /**< \brief (HMATRIX) Master Configuration Register 0 5 */\r
+#define REG_HMATRIX_MCFG6 REG_ACCESS(RwReg , 0x400A1018U) /**< \brief (HMATRIX) Master Configuration Register 0 6 */\r
+#define REG_HMATRIX_MCFG7 REG_ACCESS(RwReg , 0x400A101CU) /**< \brief (HMATRIX) Master Configuration Register 0 7 */\r
+#define REG_HMATRIX_MCFG8 REG_ACCESS(RwReg , 0x400A1020U) /**< \brief (HMATRIX) Master Configuration Register 0 8 */\r
+#define REG_HMATRIX_MCFG9 REG_ACCESS(RwReg , 0x400A1024U) /**< \brief (HMATRIX) Master Configuration Register 0 9 */\r
+#define REG_HMATRIX_MCFG10 REG_ACCESS(RwReg , 0x400A1028U) /**< \brief (HMATRIX) Master Configuration Register 0 10 */\r
+#define REG_HMATRIX_MCFG11 REG_ACCESS(RwReg , 0x400A102CU) /**< \brief (HMATRIX) Master Configuration Register 0 11 */\r
+#define REG_HMATRIX_MCFG12 REG_ACCESS(RwReg , 0x400A1030U) /**< \brief (HMATRIX) Master Configuration Register 0 12 */\r
+#define REG_HMATRIX_MCFG13 REG_ACCESS(RwReg , 0x400A1034U) /**< \brief (HMATRIX) Master Configuration Register 0 13 */\r
+#define REG_HMATRIX_MCFG14 REG_ACCESS(RwReg , 0x400A1038U) /**< \brief (HMATRIX) Master Configuration Register 0 14 */\r
+#define REG_HMATRIX_MCFG15 REG_ACCESS(RwReg , 0x400A103CU) /**< \brief (HMATRIX) Master Configuration Register 0 15 */\r
+#define REG_HMATRIX_SCFG0 REG_ACCESS(RwReg , 0x400A1040U) /**< \brief (HMATRIX) Slave Configuration Register 0 0 */\r
+#define REG_HMATRIX_SCFG1 REG_ACCESS(RwReg , 0x400A1044U) /**< \brief (HMATRIX) Slave Configuration Register 0 1 */\r
+#define REG_HMATRIX_SCFG2 REG_ACCESS(RwReg , 0x400A1048U) /**< \brief (HMATRIX) Slave Configuration Register 0 2 */\r
+#define REG_HMATRIX_SCFG3 REG_ACCESS(RwReg , 0x400A104CU) /**< \brief (HMATRIX) Slave Configuration Register 0 3 */\r
+#define REG_HMATRIX_SCFG4 REG_ACCESS(RwReg , 0x400A1050U) /**< \brief (HMATRIX) Slave Configuration Register 0 4 */\r
+#define REG_HMATRIX_SCFG5 REG_ACCESS(RwReg , 0x400A1054U) /**< \brief (HMATRIX) Slave Configuration Register 0 5 */\r
+#define REG_HMATRIX_SCFG6 REG_ACCESS(RwReg , 0x400A1058U) /**< \brief (HMATRIX) Slave Configuration Register 0 6 */\r
+#define REG_HMATRIX_SCFG7 REG_ACCESS(RwReg , 0x400A105CU) /**< \brief (HMATRIX) Slave Configuration Register 0 7 */\r
+#define REG_HMATRIX_SCFG8 REG_ACCESS(RwReg , 0x400A1060U) /**< \brief (HMATRIX) Slave Configuration Register 0 8 */\r
+#define REG_HMATRIX_SCFG9 REG_ACCESS(RwReg , 0x400A1064U) /**< \brief (HMATRIX) Slave Configuration Register 0 9 */\r
+#define REG_HMATRIX_SCFG10 REG_ACCESS(RwReg , 0x400A1068U) /**< \brief (HMATRIX) Slave Configuration Register 0 10 */\r
+#define REG_HMATRIX_SCFG11 REG_ACCESS(RwReg , 0x400A106CU) /**< \brief (HMATRIX) Slave Configuration Register 0 11 */\r
+#define REG_HMATRIX_SCFG12 REG_ACCESS(RwReg , 0x400A1070U) /**< \brief (HMATRIX) Slave Configuration Register 0 12 */\r
+#define REG_HMATRIX_SCFG13 REG_ACCESS(RwReg , 0x400A1074U) /**< \brief (HMATRIX) Slave Configuration Register 0 13 */\r
+#define REG_HMATRIX_SCFG14 REG_ACCESS(RwReg , 0x400A1078U) /**< \brief (HMATRIX) Slave Configuration Register 0 14 */\r
+#define REG_HMATRIX_SCFG15 REG_ACCESS(RwReg , 0x400A107CU) /**< \brief (HMATRIX) Slave Configuration Register 0 15 */\r
+#define REG_HMATRIX_PRAS0 REG_ACCESS(RwReg , 0x400A1080U) /**< \brief (HMATRIX) Priority Register A for Slave 0 0 */\r
+#define REG_HMATRIX_PRBS0 REG_ACCESS(RwReg , 0x400A1084U) /**< \brief (HMATRIX) Priority Register B for Slave 0 0 */\r
+#define REG_HMATRIX_PRAS1 REG_ACCESS(RwReg , 0x400A1088U) /**< \brief (HMATRIX) Priority Register A for Slave 0 1 */\r
+#define REG_HMATRIX_PRBS1 REG_ACCESS(RwReg , 0x400A108CU) /**< \brief (HMATRIX) Priority Register B for Slave 0 1 */\r
+#define REG_HMATRIX_PRAS2 REG_ACCESS(RwReg , 0x400A1090U) /**< \brief (HMATRIX) Priority Register A for Slave 0 2 */\r
+#define REG_HMATRIX_PRBS2 REG_ACCESS(RwReg , 0x400A1094U) /**< \brief (HMATRIX) Priority Register B for Slave 0 2 */\r
+#define REG_HMATRIX_PRAS3 REG_ACCESS(RwReg , 0x400A1098U) /**< \brief (HMATRIX) Priority Register A for Slave 0 3 */\r
+#define REG_HMATRIX_PRBS3 REG_ACCESS(RwReg , 0x400A109CU) /**< \brief (HMATRIX) Priority Register B for Slave 0 3 */\r
+#define REG_HMATRIX_PRAS4 REG_ACCESS(RwReg , 0x400A10A0U) /**< \brief (HMATRIX) Priority Register A for Slave 0 4 */\r
+#define REG_HMATRIX_PRBS4 REG_ACCESS(RwReg , 0x400A10A4U) /**< \brief (HMATRIX) Priority Register B for Slave 0 4 */\r
+#define REG_HMATRIX_PRAS5 REG_ACCESS(RwReg , 0x400A10A8U) /**< \brief (HMATRIX) Priority Register A for Slave 0 5 */\r
+#define REG_HMATRIX_PRBS5 REG_ACCESS(RwReg , 0x400A10ACU) /**< \brief (HMATRIX) Priority Register B for Slave 0 5 */\r
+#define REG_HMATRIX_PRAS6 REG_ACCESS(RwReg , 0x400A10B0U) /**< \brief (HMATRIX) Priority Register A for Slave 0 6 */\r
+#define REG_HMATRIX_PRBS6 REG_ACCESS(RwReg , 0x400A10B4U) /**< \brief (HMATRIX) Priority Register B for Slave 0 6 */\r
+#define REG_HMATRIX_PRAS7 REG_ACCESS(RwReg , 0x400A10B8U) /**< \brief (HMATRIX) Priority Register A for Slave 0 7 */\r
+#define REG_HMATRIX_PRBS7 REG_ACCESS(RwReg , 0x400A10BCU) /**< \brief (HMATRIX) Priority Register B for Slave 0 7 */\r
+#define REG_HMATRIX_PRAS8 REG_ACCESS(RwReg , 0x400A10C0U) /**< \brief (HMATRIX) Priority Register A for Slave 0 8 */\r
+#define REG_HMATRIX_PRBS8 REG_ACCESS(RwReg , 0x400A10C4U) /**< \brief (HMATRIX) Priority Register B for Slave 0 8 */\r
+#define REG_HMATRIX_PRAS9 REG_ACCESS(RwReg , 0x400A10C8U) /**< \brief (HMATRIX) Priority Register A for Slave 0 9 */\r
+#define REG_HMATRIX_PRBS9 REG_ACCESS(RwReg , 0x400A10CCU) /**< \brief (HMATRIX) Priority Register B for Slave 0 9 */\r
+#define REG_HMATRIX_PRAS10 REG_ACCESS(RwReg , 0x400A10D0U) /**< \brief (HMATRIX) Priority Register A for Slave 0 10 */\r
+#define REG_HMATRIX_PRBS10 REG_ACCESS(RwReg , 0x400A10D4U) /**< \brief (HMATRIX) Priority Register B for Slave 0 10 */\r
+#define REG_HMATRIX_PRAS11 REG_ACCESS(RwReg , 0x400A10D8U) /**< \brief (HMATRIX) Priority Register A for Slave 0 11 */\r
+#define REG_HMATRIX_PRBS11 REG_ACCESS(RwReg , 0x400A10DCU) /**< \brief (HMATRIX) Priority Register B for Slave 0 11 */\r
+#define REG_HMATRIX_PRAS12 REG_ACCESS(RwReg , 0x400A10E0U) /**< \brief (HMATRIX) Priority Register A for Slave 0 12 */\r
+#define REG_HMATRIX_PRBS12 REG_ACCESS(RwReg , 0x400A10E4U) /**< \brief (HMATRIX) Priority Register B for Slave 0 12 */\r
+#define REG_HMATRIX_PRAS13 REG_ACCESS(RwReg , 0x400A10E8U) /**< \brief (HMATRIX) Priority Register A for Slave 0 13 */\r
+#define REG_HMATRIX_PRBS13 REG_ACCESS(RwReg , 0x400A10ECU) /**< \brief (HMATRIX) Priority Register B for Slave 0 13 */\r
+#define REG_HMATRIX_PRAS14 REG_ACCESS(RwReg , 0x400A10F0U) /**< \brief (HMATRIX) Priority Register A for Slave 0 14 */\r
+#define REG_HMATRIX_PRBS14 REG_ACCESS(RwReg , 0x400A10F4U) /**< \brief (HMATRIX) Priority Register B for Slave 0 14 */\r
+#define REG_HMATRIX_PRAS15 REG_ACCESS(RwReg , 0x400A10F8U) /**< \brief (HMATRIX) Priority Register A for Slave 0 15 */\r
+#define REG_HMATRIX_PRBS15 REG_ACCESS(RwReg , 0x400A10FCU) /**< \brief (HMATRIX) Priority Register B for Slave 0 15 */\r
+#define REG_HMATRIX_MRCR REG_ACCESS(RwReg , 0x400A1100U) /**< \brief (HMATRIX) Master Remap Control Register */ \r
+#define REG_HMATRIX_SFR0 REG_ACCESS(RwReg , 0x400A1110U) /**< \brief (HMATRIX) Special Function Register 0 0 */\r
+#define REG_HMATRIX_SFR1 REG_ACCESS(RwReg , 0x400A1114U) /**< \brief (HMATRIX) Special Function Register 0 1 */\r
+#define REG_HMATRIX_SFR2 REG_ACCESS(RwReg , 0x400A1118U) /**< \brief (HMATRIX) Special Function Register 0 2 */\r
+#define REG_HMATRIX_SFR3 REG_ACCESS(RwReg , 0x400A111CU) /**< \brief (HMATRIX) Special Function Register 0 3 */\r
+#define REG_HMATRIX_SFR4 REG_ACCESS(RwReg , 0x400A1120U) /**< \brief (HMATRIX) Special Function Register 0 4 */\r
+#define REG_HMATRIX_SFR5 REG_ACCESS(RwReg , 0x400A1124U) /**< \brief (HMATRIX) Special Function Register 0 5 */\r
+#define REG_HMATRIX_SFR6 REG_ACCESS(RwReg , 0x400A1128U) /**< \brief (HMATRIX) Special Function Register 0 6 */\r
+#define REG_HMATRIX_SFR7 REG_ACCESS(RwReg , 0x400A112CU) /**< \brief (HMATRIX) Special Function Register 0 7 */\r
+#define REG_HMATRIX_SFR8 REG_ACCESS(RwReg , 0x400A1130U) /**< \brief (HMATRIX) Special Function Register 0 8 */\r
+#define REG_HMATRIX_SFR9 REG_ACCESS(RwReg , 0x400A1134U) /**< \brief (HMATRIX) Special Function Register 0 9 */\r
+#define REG_HMATRIX_SFR10 REG_ACCESS(RwReg , 0x400A1138U) /**< \brief (HMATRIX) Special Function Register 0 10 */\r
+#define REG_HMATRIX_SFR11 REG_ACCESS(RwReg , 0x400A113CU) /**< \brief (HMATRIX) Special Function Register 0 11 */\r
+#define REG_HMATRIX_SFR12 REG_ACCESS(RwReg , 0x400A1140U) /**< \brief (HMATRIX) Special Function Register 0 12 */\r
+#define REG_HMATRIX_SFR13 REG_ACCESS(RwReg , 0x400A1144U) /**< \brief (HMATRIX) Special Function Register 0 13 */\r
+#define REG_HMATRIX_SFR14 REG_ACCESS(RwReg , 0x400A1148U) /**< \brief (HMATRIX) Special Function Register 0 14 */\r
+#define REG_HMATRIX_SFR15 REG_ACCESS(RwReg , 0x400A114CU) /**< \brief (HMATRIX) Special Function Register 0 15 */\r
+/* ========== Register definition for PDCA peripheral ========== */\r
+#define REG_PDCA_MAR0 REG_ACCESS(RwReg , 0x400A2000U) /**< \brief (PDCA) Memory Address Register 0 */\r
+#define REG_PDCA_PSR0 REG_ACCESS(RwReg , 0x400A2004U) /**< \brief (PDCA) Peripheral Select Register 0 */\r
+#define REG_PDCA_TCR0 REG_ACCESS(RwReg , 0x400A2008U) /**< \brief (PDCA) Transfer Counter Register 0 */\r
+#define REG_PDCA_MARR0 REG_ACCESS(RwReg , 0x400A200CU) /**< \brief (PDCA) Memory Address Reload Register 0 */\r
+#define REG_PDCA_TCRR0 REG_ACCESS(RwReg , 0x400A2010U) /**< \brief (PDCA) Transfer Counter Reload Register 0 */\r
+#define REG_PDCA_CR0 REG_ACCESS(WoReg , 0x400A2014U) /**< \brief (PDCA) Control Register 0 */\r
+#define REG_PDCA_MR0 REG_ACCESS(RwReg , 0x400A2018U) /**< \brief (PDCA) Mode Register 0 */\r
+#define REG_PDCA_SR0 REG_ACCESS(RoReg , 0x400A201CU) /**< \brief (PDCA) Status Register 0 */\r
+#define REG_PDCA_IER0 REG_ACCESS(WoReg , 0x400A2020U) /**< \brief (PDCA) Interrupt Enable Register 0 */\r
+#define REG_PDCA_IDR0 REG_ACCESS(WoReg , 0x400A2024U) /**< \brief (PDCA) Interrupt Disable Register 0 */\r
+#define REG_PDCA_IMR0 REG_ACCESS(RoReg , 0x400A2028U) /**< \brief (PDCA) Interrupt Mask Register 0 */\r
+#define REG_PDCA_ISR0 REG_ACCESS(RoReg , 0x400A202CU) /**< \brief (PDCA) Interrupt Status Register 0 */\r
+#define REG_PDCA_MAR1 REG_ACCESS(RwReg , 0x400A2040U) /**< \brief (PDCA) Memory Address Register 1 */\r
+#define REG_PDCA_PSR1 REG_ACCESS(RwReg , 0x400A2044U) /**< \brief (PDCA) Peripheral Select Register 1 */\r
+#define REG_PDCA_TCR1 REG_ACCESS(RwReg , 0x400A2048U) /**< \brief (PDCA) Transfer Counter Register 1 */\r
+#define REG_PDCA_MARR1 REG_ACCESS(RwReg , 0x400A204CU) /**< \brief (PDCA) Memory Address Reload Register 1 */\r
+#define REG_PDCA_TCRR1 REG_ACCESS(RwReg , 0x400A2050U) /**< \brief (PDCA) Transfer Counter Reload Register 1 */\r
+#define REG_PDCA_CR1 REG_ACCESS(WoReg , 0x400A2054U) /**< \brief (PDCA) Control Register 1 */\r
+#define REG_PDCA_MR1 REG_ACCESS(RwReg , 0x400A2058U) /**< \brief (PDCA) Mode Register 1 */\r
+#define REG_PDCA_SR1 REG_ACCESS(RoReg , 0x400A205CU) /**< \brief (PDCA) Status Register 1 */\r
+#define REG_PDCA_IER1 REG_ACCESS(WoReg , 0x400A2060U) /**< \brief (PDCA) Interrupt Enable Register 1 */\r
+#define REG_PDCA_IDR1 REG_ACCESS(WoReg , 0x400A2064U) /**< \brief (PDCA) Interrupt Disable Register 1 */\r
+#define REG_PDCA_IMR1 REG_ACCESS(RoReg , 0x400A2068U) /**< \brief (PDCA) Interrupt Mask Register 1 */\r
+#define REG_PDCA_ISR1 REG_ACCESS(RoReg , 0x400A206CU) /**< \brief (PDCA) Interrupt Status Register 1 */\r
+#define REG_PDCA_MAR2 REG_ACCESS(RwReg , 0x400A2080U) /**< \brief (PDCA) Memory Address Register 2 */\r
+#define REG_PDCA_PSR2 REG_ACCESS(RwReg , 0x400A2084U) /**< \brief (PDCA) Peripheral Select Register 2 */\r
+#define REG_PDCA_TCR2 REG_ACCESS(RwReg , 0x400A2088U) /**< \brief (PDCA) Transfer Counter Register 2 */\r
+#define REG_PDCA_MARR2 REG_ACCESS(RwReg , 0x400A208CU) /**< \brief (PDCA) Memory Address Reload Register 2 */\r
+#define REG_PDCA_TCRR2 REG_ACCESS(RwReg , 0x400A2090U) /**< \brief (PDCA) Transfer Counter Reload Register 2 */\r
+#define REG_PDCA_CR2 REG_ACCESS(WoReg , 0x400A2094U) /**< \brief (PDCA) Control Register 2 */\r
+#define REG_PDCA_MR2 REG_ACCESS(RwReg , 0x400A2098U) /**< \brief (PDCA) Mode Register 2 */\r
+#define REG_PDCA_SR2 REG_ACCESS(RoReg , 0x400A209CU) /**< \brief (PDCA) Status Register 2 */\r
+#define REG_PDCA_IER2 REG_ACCESS(WoReg , 0x400A20A0U) /**< \brief (PDCA) Interrupt Enable Register 2 */\r
+#define REG_PDCA_IDR2 REG_ACCESS(WoReg , 0x400A20A4U) /**< \brief (PDCA) Interrupt Disable Register 2 */\r
+#define REG_PDCA_IMR2 REG_ACCESS(RoReg , 0x400A20A8U) /**< \brief (PDCA) Interrupt Mask Register 2 */\r
+#define REG_PDCA_ISR2 REG_ACCESS(RoReg , 0x400A20ACU) /**< \brief (PDCA) Interrupt Status Register 2 */\r
+#define REG_PDCA_MAR3 REG_ACCESS(RwReg , 0x400A20C0U) /**< \brief (PDCA) Memory Address Register 3 */\r
+#define REG_PDCA_PSR3 REG_ACCESS(RwReg , 0x400A20C4U) /**< \brief (PDCA) Peripheral Select Register 3 */\r
+#define REG_PDCA_TCR3 REG_ACCESS(RwReg , 0x400A20C8U) /**< \brief (PDCA) Transfer Counter Register 3 */\r
+#define REG_PDCA_MARR3 REG_ACCESS(RwReg , 0x400A20CCU) /**< \brief (PDCA) Memory Address Reload Register 3 */\r
+#define REG_PDCA_TCRR3 REG_ACCESS(RwReg , 0x400A20D0U) /**< \brief (PDCA) Transfer Counter Reload Register 3 */\r
+#define REG_PDCA_CR3 REG_ACCESS(WoReg , 0x400A20D4U) /**< \brief (PDCA) Control Register 3 */\r
+#define REG_PDCA_MR3 REG_ACCESS(RwReg , 0x400A20D8U) /**< \brief (PDCA) Mode Register 3 */\r
+#define REG_PDCA_SR3 REG_ACCESS(RoReg , 0x400A20DCU) /**< \brief (PDCA) Status Register 3 */\r
+#define REG_PDCA_IER3 REG_ACCESS(WoReg , 0x400A20E0U) /**< \brief (PDCA) Interrupt Enable Register 3 */\r
+#define REG_PDCA_IDR3 REG_ACCESS(WoReg , 0x400A20E4U) /**< \brief (PDCA) Interrupt Disable Register 3 */\r
+#define REG_PDCA_IMR3 REG_ACCESS(RoReg , 0x400A20E8U) /**< \brief (PDCA) Interrupt Mask Register 3 */\r
+#define REG_PDCA_ISR3 REG_ACCESS(RoReg , 0x400A20ECU) /**< \brief (PDCA) Interrupt Status Register 3 */\r
+#define REG_PDCA_MAR4 REG_ACCESS(RwReg , 0x400A2100U) /**< \brief (PDCA) Memory Address Register 4 */\r
+#define REG_PDCA_PSR4 REG_ACCESS(RwReg , 0x400A2104U) /**< \brief (PDCA) Peripheral Select Register 4 */\r
+#define REG_PDCA_TCR4 REG_ACCESS(RwReg , 0x400A2108U) /**< \brief (PDCA) Transfer Counter Register 4 */\r
+#define REG_PDCA_MARR4 REG_ACCESS(RwReg , 0x400A210CU) /**< \brief (PDCA) Memory Address Reload Register 4 */\r
+#define REG_PDCA_TCRR4 REG_ACCESS(RwReg , 0x400A2110U) /**< \brief (PDCA) Transfer Counter Reload Register 4 */\r
+#define REG_PDCA_CR4 REG_ACCESS(WoReg , 0x400A2114U) /**< \brief (PDCA) Control Register 4 */\r
+#define REG_PDCA_MR4 REG_ACCESS(RwReg , 0x400A2118U) /**< \brief (PDCA) Mode Register 4 */\r
+#define REG_PDCA_SR4 REG_ACCESS(RoReg , 0x400A211CU) /**< \brief (PDCA) Status Register 4 */\r
+#define REG_PDCA_IER4 REG_ACCESS(WoReg , 0x400A2120U) /**< \brief (PDCA) Interrupt Enable Register 4 */\r
+#define REG_PDCA_IDR4 REG_ACCESS(WoReg , 0x400A2124U) /**< \brief (PDCA) Interrupt Disable Register 4 */\r
+#define REG_PDCA_IMR4 REG_ACCESS(RoReg , 0x400A2128U) /**< \brief (PDCA) Interrupt Mask Register 4 */\r
+#define REG_PDCA_ISR4 REG_ACCESS(RoReg , 0x400A212CU) /**< \brief (PDCA) Interrupt Status Register 4 */\r
+#define REG_PDCA_MAR5 REG_ACCESS(RwReg , 0x400A2140U) /**< \brief (PDCA) Memory Address Register 5 */\r
+#define REG_PDCA_PSR5 REG_ACCESS(RwReg , 0x400A2144U) /**< \brief (PDCA) Peripheral Select Register 5 */\r
+#define REG_PDCA_TCR5 REG_ACCESS(RwReg , 0x400A2148U) /**< \brief (PDCA) Transfer Counter Register 5 */\r
+#define REG_PDCA_MARR5 REG_ACCESS(RwReg , 0x400A214CU) /**< \brief (PDCA) Memory Address Reload Register 5 */\r
+#define REG_PDCA_TCRR5 REG_ACCESS(RwReg , 0x400A2150U) /**< \brief (PDCA) Transfer Counter Reload Register 5 */\r
+#define REG_PDCA_CR5 REG_ACCESS(WoReg , 0x400A2154U) /**< \brief (PDCA) Control Register 5 */\r
+#define REG_PDCA_MR5 REG_ACCESS(RwReg , 0x400A2158U) /**< \brief (PDCA) Mode Register 5 */\r
+#define REG_PDCA_SR5 REG_ACCESS(RoReg , 0x400A215CU) /**< \brief (PDCA) Status Register 5 */\r
+#define REG_PDCA_IER5 REG_ACCESS(WoReg , 0x400A2160U) /**< \brief (PDCA) Interrupt Enable Register 5 */\r
+#define REG_PDCA_IDR5 REG_ACCESS(WoReg , 0x400A2164U) /**< \brief (PDCA) Interrupt Disable Register 5 */\r
+#define REG_PDCA_IMR5 REG_ACCESS(RoReg , 0x400A2168U) /**< \brief (PDCA) Interrupt Mask Register 5 */\r
+#define REG_PDCA_ISR5 REG_ACCESS(RoReg , 0x400A216CU) /**< \brief (PDCA) Interrupt Status Register 5 */\r
+#define REG_PDCA_MAR6 REG_ACCESS(RwReg , 0x400A2180U) /**< \brief (PDCA) Memory Address Register 6 */\r
+#define REG_PDCA_PSR6 REG_ACCESS(RwReg , 0x400A2184U) /**< \brief (PDCA) Peripheral Select Register 6 */\r
+#define REG_PDCA_TCR6 REG_ACCESS(RwReg , 0x400A2188U) /**< \brief (PDCA) Transfer Counter Register 6 */\r
+#define REG_PDCA_MARR6 REG_ACCESS(RwReg , 0x400A218CU) /**< \brief (PDCA) Memory Address Reload Register 6 */\r
+#define REG_PDCA_TCRR6 REG_ACCESS(RwReg , 0x400A2190U) /**< \brief (PDCA) Transfer Counter Reload Register 6 */\r
+#define REG_PDCA_CR6 REG_ACCESS(WoReg , 0x400A2194U) /**< \brief (PDCA) Control Register 6 */\r
+#define REG_PDCA_MR6 REG_ACCESS(RwReg , 0x400A2198U) /**< \brief (PDCA) Mode Register 6 */\r
+#define REG_PDCA_SR6 REG_ACCESS(RoReg , 0x400A219CU) /**< \brief (PDCA) Status Register 6 */\r
+#define REG_PDCA_IER6 REG_ACCESS(WoReg , 0x400A21A0U) /**< \brief (PDCA) Interrupt Enable Register 6 */\r
+#define REG_PDCA_IDR6 REG_ACCESS(WoReg , 0x400A21A4U) /**< \brief (PDCA) Interrupt Disable Register 6 */\r
+#define REG_PDCA_IMR6 REG_ACCESS(RoReg , 0x400A21A8U) /**< \brief (PDCA) Interrupt Mask Register 6 */\r
+#define REG_PDCA_ISR6 REG_ACCESS(RoReg , 0x400A21ACU) /**< \brief (PDCA) Interrupt Status Register 6 */\r
+#define REG_PDCA_MAR7 REG_ACCESS(RwReg , 0x400A21C0U) /**< \brief (PDCA) Memory Address Register 7 */\r
+#define REG_PDCA_PSR7 REG_ACCESS(RwReg , 0x400A21C4U) /**< \brief (PDCA) Peripheral Select Register 7 */\r
+#define REG_PDCA_TCR7 REG_ACCESS(RwReg , 0x400A21C8U) /**< \brief (PDCA) Transfer Counter Register 7 */\r
+#define REG_PDCA_MARR7 REG_ACCESS(RwReg , 0x400A21CCU) /**< \brief (PDCA) Memory Address Reload Register 7 */\r
+#define REG_PDCA_TCRR7 REG_ACCESS(RwReg , 0x400A21D0U) /**< \brief (PDCA) Transfer Counter Reload Register 7 */\r
+#define REG_PDCA_CR7 REG_ACCESS(WoReg , 0x400A21D4U) /**< \brief (PDCA) Control Register 7 */\r
+#define REG_PDCA_MR7 REG_ACCESS(RwReg , 0x400A21D8U) /**< \brief (PDCA) Mode Register 7 */\r
+#define REG_PDCA_SR7 REG_ACCESS(RoReg , 0x400A21DCU) /**< \brief (PDCA) Status Register 7 */\r
+#define REG_PDCA_IER7 REG_ACCESS(WoReg , 0x400A21E0U) /**< \brief (PDCA) Interrupt Enable Register 7 */\r
+#define REG_PDCA_IDR7 REG_ACCESS(WoReg , 0x400A21E4U) /**< \brief (PDCA) Interrupt Disable Register 7 */\r
+#define REG_PDCA_IMR7 REG_ACCESS(RoReg , 0x400A21E8U) /**< \brief (PDCA) Interrupt Mask Register 7 */\r
+#define REG_PDCA_ISR7 REG_ACCESS(RoReg , 0x400A21ECU) /**< \brief (PDCA) Interrupt Status Register 7 */\r
+#define REG_PDCA_MAR8 REG_ACCESS(RwReg , 0x400A2200U) /**< \brief (PDCA) Memory Address Register 8 */\r
+#define REG_PDCA_PSR8 REG_ACCESS(RwReg , 0x400A2204U) /**< \brief (PDCA) Peripheral Select Register 8 */\r
+#define REG_PDCA_TCR8 REG_ACCESS(RwReg , 0x400A2208U) /**< \brief (PDCA) Transfer Counter Register 8 */\r
+#define REG_PDCA_MARR8 REG_ACCESS(RwReg , 0x400A220CU) /**< \brief (PDCA) Memory Address Reload Register 8 */\r
+#define REG_PDCA_TCRR8 REG_ACCESS(RwReg , 0x400A2210U) /**< \brief (PDCA) Transfer Counter Reload Register 8 */\r
+#define REG_PDCA_CR8 REG_ACCESS(WoReg , 0x400A2214U) /**< \brief (PDCA) Control Register 8 */\r
+#define REG_PDCA_MR8 REG_ACCESS(RwReg , 0x400A2218U) /**< \brief (PDCA) Mode Register 8 */\r
+#define REG_PDCA_SR8 REG_ACCESS(RoReg , 0x400A221CU) /**< \brief (PDCA) Status Register 8 */\r
+#define REG_PDCA_IER8 REG_ACCESS(WoReg , 0x400A2220U) /**< \brief (PDCA) Interrupt Enable Register 8 */\r
+#define REG_PDCA_IDR8 REG_ACCESS(WoReg , 0x400A2224U) /**< \brief (PDCA) Interrupt Disable Register 8 */\r
+#define REG_PDCA_IMR8 REG_ACCESS(RoReg , 0x400A2228U) /**< \brief (PDCA) Interrupt Mask Register 8 */\r
+#define REG_PDCA_ISR8 REG_ACCESS(RoReg , 0x400A222CU) /**< \brief (PDCA) Interrupt Status Register 8 */\r
+#define REG_PDCA_MAR9 REG_ACCESS(RwReg , 0x400A2240U) /**< \brief (PDCA) Memory Address Register 9 */\r
+#define REG_PDCA_PSR9 REG_ACCESS(RwReg , 0x400A2244U) /**< \brief (PDCA) Peripheral Select Register 9 */\r
+#define REG_PDCA_TCR9 REG_ACCESS(RwReg , 0x400A2248U) /**< \brief (PDCA) Transfer Counter Register 9 */\r
+#define REG_PDCA_MARR9 REG_ACCESS(RwReg , 0x400A224CU) /**< \brief (PDCA) Memory Address Reload Register 9 */\r
+#define REG_PDCA_TCRR9 REG_ACCESS(RwReg , 0x400A2250U) /**< \brief (PDCA) Transfer Counter Reload Register 9 */\r
+#define REG_PDCA_CR9 REG_ACCESS(WoReg , 0x400A2254U) /**< \brief (PDCA) Control Register 9 */\r
+#define REG_PDCA_MR9 REG_ACCESS(RwReg , 0x400A2258U) /**< \brief (PDCA) Mode Register 9 */\r
+#define REG_PDCA_SR9 REG_ACCESS(RoReg , 0x400A225CU) /**< \brief (PDCA) Status Register 9 */\r
+#define REG_PDCA_IER9 REG_ACCESS(WoReg , 0x400A2260U) /**< \brief (PDCA) Interrupt Enable Register 9 */\r
+#define REG_PDCA_IDR9 REG_ACCESS(WoReg , 0x400A2264U) /**< \brief (PDCA) Interrupt Disable Register 9 */\r
+#define REG_PDCA_IMR9 REG_ACCESS(RoReg , 0x400A2268U) /**< \brief (PDCA) Interrupt Mask Register 9 */\r
+#define REG_PDCA_ISR9 REG_ACCESS(RoReg , 0x400A226CU) /**< \brief (PDCA) Interrupt Status Register 9 */\r
+#define REG_PDCA_MAR10 REG_ACCESS(RwReg , 0x400A2280U) /**< \brief (PDCA) Memory Address Register 10 */\r
+#define REG_PDCA_PSR10 REG_ACCESS(RwReg , 0x400A2284U) /**< \brief (PDCA) Peripheral Select Register 10 */\r
+#define REG_PDCA_TCR10 REG_ACCESS(RwReg , 0x400A2288U) /**< \brief (PDCA) Transfer Counter Register 10 */\r
+#define REG_PDCA_MARR10 REG_ACCESS(RwReg , 0x400A228CU) /**< \brief (PDCA) Memory Address Reload Register 10 */\r
+#define REG_PDCA_TCRR10 REG_ACCESS(RwReg , 0x400A2290U) /**< \brief (PDCA) Transfer Counter Reload Register 10 */\r
+#define REG_PDCA_CR10 REG_ACCESS(WoReg , 0x400A2294U) /**< \brief (PDCA) Control Register 10 */\r
+#define REG_PDCA_MR10 REG_ACCESS(RwReg , 0x400A2298U) /**< \brief (PDCA) Mode Register 10 */\r
+#define REG_PDCA_SR10 REG_ACCESS(RoReg , 0x400A229CU) /**< \brief (PDCA) Status Register 10 */\r
+#define REG_PDCA_IER10 REG_ACCESS(WoReg , 0x400A22A0U) /**< \brief (PDCA) Interrupt Enable Register 10 */\r
+#define REG_PDCA_IDR10 REG_ACCESS(WoReg , 0x400A22A4U) /**< \brief (PDCA) Interrupt Disable Register 10 */\r
+#define REG_PDCA_IMR10 REG_ACCESS(RoReg , 0x400A22A8U) /**< \brief (PDCA) Interrupt Mask Register 10 */\r
+#define REG_PDCA_ISR10 REG_ACCESS(RoReg , 0x400A22ACU) /**< \brief (PDCA) Interrupt Status Register 10 */\r
+#define REG_PDCA_MAR11 REG_ACCESS(RwReg , 0x400A22C0U) /**< \brief (PDCA) Memory Address Register 11 */\r
+#define REG_PDCA_PSR11 REG_ACCESS(RwReg , 0x400A22C4U) /**< \brief (PDCA) Peripheral Select Register 11 */\r
+#define REG_PDCA_TCR11 REG_ACCESS(RwReg , 0x400A22C8U) /**< \brief (PDCA) Transfer Counter Register 11 */\r
+#define REG_PDCA_MARR11 REG_ACCESS(RwReg , 0x400A22CCU) /**< \brief (PDCA) Memory Address Reload Register 11 */\r
+#define REG_PDCA_TCRR11 REG_ACCESS(RwReg , 0x400A22D0U) /**< \brief (PDCA) Transfer Counter Reload Register 11 */\r
+#define REG_PDCA_CR11 REG_ACCESS(WoReg , 0x400A22D4U) /**< \brief (PDCA) Control Register 11 */\r
+#define REG_PDCA_MR11 REG_ACCESS(RwReg , 0x400A22D8U) /**< \brief (PDCA) Mode Register 11 */\r
+#define REG_PDCA_SR11 REG_ACCESS(RoReg , 0x400A22DCU) /**< \brief (PDCA) Status Register 11 */\r
+#define REG_PDCA_IER11 REG_ACCESS(WoReg , 0x400A22E0U) /**< \brief (PDCA) Interrupt Enable Register 11 */\r
+#define REG_PDCA_IDR11 REG_ACCESS(WoReg , 0x400A22E4U) /**< \brief (PDCA) Interrupt Disable Register 11 */\r
+#define REG_PDCA_IMR11 REG_ACCESS(RoReg , 0x400A22E8U) /**< \brief (PDCA) Interrupt Mask Register 11 */\r
+#define REG_PDCA_ISR11 REG_ACCESS(RoReg , 0x400A22ECU) /**< \brief (PDCA) Interrupt Status Register 11 */\r
+#define REG_PDCA_MAR12 REG_ACCESS(RwReg , 0x400A2300U) /**< \brief (PDCA) Memory Address Register 12 */\r
+#define REG_PDCA_PSR12 REG_ACCESS(RwReg , 0x400A2304U) /**< \brief (PDCA) Peripheral Select Register 12 */\r
+#define REG_PDCA_TCR12 REG_ACCESS(RwReg , 0x400A2308U) /**< \brief (PDCA) Transfer Counter Register 12 */\r
+#define REG_PDCA_MARR12 REG_ACCESS(RwReg , 0x400A230CU) /**< \brief (PDCA) Memory Address Reload Register 12 */\r
+#define REG_PDCA_TCRR12 REG_ACCESS(RwReg , 0x400A2310U) /**< \brief (PDCA) Transfer Counter Reload Register 12 */\r
+#define REG_PDCA_CR12 REG_ACCESS(WoReg , 0x400A2314U) /**< \brief (PDCA) Control Register 12 */\r
+#define REG_PDCA_MR12 REG_ACCESS(RwReg , 0x400A2318U) /**< \brief (PDCA) Mode Register 12 */\r
+#define REG_PDCA_SR12 REG_ACCESS(RoReg , 0x400A231CU) /**< \brief (PDCA) Status Register 12 */\r
+#define REG_PDCA_IER12 REG_ACCESS(WoReg , 0x400A2320U) /**< \brief (PDCA) Interrupt Enable Register 12 */\r
+#define REG_PDCA_IDR12 REG_ACCESS(WoReg , 0x400A2324U) /**< \brief (PDCA) Interrupt Disable Register 12 */\r
+#define REG_PDCA_IMR12 REG_ACCESS(RoReg , 0x400A2328U) /**< \brief (PDCA) Interrupt Mask Register 12 */\r
+#define REG_PDCA_ISR12 REG_ACCESS(RoReg , 0x400A232CU) /**< \brief (PDCA) Interrupt Status Register 12 */\r
+#define REG_PDCA_MAR13 REG_ACCESS(RwReg , 0x400A2340U) /**< \brief (PDCA) Memory Address Register 13 */\r
+#define REG_PDCA_PSR13 REG_ACCESS(RwReg , 0x400A2344U) /**< \brief (PDCA) Peripheral Select Register 13 */\r
+#define REG_PDCA_TCR13 REG_ACCESS(RwReg , 0x400A2348U) /**< \brief (PDCA) Transfer Counter Register 13 */\r
+#define REG_PDCA_MARR13 REG_ACCESS(RwReg , 0x400A234CU) /**< \brief (PDCA) Memory Address Reload Register 13 */\r
+#define REG_PDCA_TCRR13 REG_ACCESS(RwReg , 0x400A2350U) /**< \brief (PDCA) Transfer Counter Reload Register 13 */\r
+#define REG_PDCA_CR13 REG_ACCESS(WoReg , 0x400A2354U) /**< \brief (PDCA) Control Register 13 */\r
+#define REG_PDCA_MR13 REG_ACCESS(RwReg , 0x400A2358U) /**< \brief (PDCA) Mode Register 13 */\r
+#define REG_PDCA_SR13 REG_ACCESS(RoReg , 0x400A235CU) /**< \brief (PDCA) Status Register 13 */\r
+#define REG_PDCA_IER13 REG_ACCESS(WoReg , 0x400A2360U) /**< \brief (PDCA) Interrupt Enable Register 13 */\r
+#define REG_PDCA_IDR13 REG_ACCESS(WoReg , 0x400A2364U) /**< \brief (PDCA) Interrupt Disable Register 13 */\r
+#define REG_PDCA_IMR13 REG_ACCESS(RoReg , 0x400A2368U) /**< \brief (PDCA) Interrupt Mask Register 13 */\r
+#define REG_PDCA_ISR13 REG_ACCESS(RoReg , 0x400A236CU) /**< \brief (PDCA) Interrupt Status Register 13 */\r
+#define REG_PDCA_MAR14 REG_ACCESS(RwReg , 0x400A2380U) /**< \brief (PDCA) Memory Address Register 14 */\r
+#define REG_PDCA_PSR14 REG_ACCESS(RwReg , 0x400A2384U) /**< \brief (PDCA) Peripheral Select Register 14 */\r
+#define REG_PDCA_TCR14 REG_ACCESS(RwReg , 0x400A2388U) /**< \brief (PDCA) Transfer Counter Register 14 */\r
+#define REG_PDCA_MARR14 REG_ACCESS(RwReg , 0x400A238CU) /**< \brief (PDCA) Memory Address Reload Register 14 */\r
+#define REG_PDCA_TCRR14 REG_ACCESS(RwReg , 0x400A2390U) /**< \brief (PDCA) Transfer Counter Reload Register 14 */\r
+#define REG_PDCA_CR14 REG_ACCESS(WoReg , 0x400A2394U) /**< \brief (PDCA) Control Register 14 */\r
+#define REG_PDCA_MR14 REG_ACCESS(RwReg , 0x400A2398U) /**< \brief (PDCA) Mode Register 14 */\r
+#define REG_PDCA_SR14 REG_ACCESS(RoReg , 0x400A239CU) /**< \brief (PDCA) Status Register 14 */\r
+#define REG_PDCA_IER14 REG_ACCESS(WoReg , 0x400A23A0U) /**< \brief (PDCA) Interrupt Enable Register 14 */\r
+#define REG_PDCA_IDR14 REG_ACCESS(WoReg , 0x400A23A4U) /**< \brief (PDCA) Interrupt Disable Register 14 */\r
+#define REG_PDCA_IMR14 REG_ACCESS(RoReg , 0x400A23A8U) /**< \brief (PDCA) Interrupt Mask Register 14 */\r
+#define REG_PDCA_ISR14 REG_ACCESS(RoReg , 0x400A23ACU) /**< \brief (PDCA) Interrupt Status Register 14 */\r
+#define REG_PDCA_MAR15 REG_ACCESS(RwReg , 0x400A23C0U) /**< \brief (PDCA) Memory Address Register 15 */\r
+#define REG_PDCA_PSR15 REG_ACCESS(RwReg , 0x400A23C4U) /**< \brief (PDCA) Peripheral Select Register 15 */\r
+#define REG_PDCA_TCR15 REG_ACCESS(RwReg , 0x400A23C8U) /**< \brief (PDCA) Transfer Counter Register 15 */\r
+#define REG_PDCA_MARR15 REG_ACCESS(RwReg , 0x400A23CCU) /**< \brief (PDCA) Memory Address Reload Register 15 */\r
+#define REG_PDCA_TCRR15 REG_ACCESS(RwReg , 0x400A23D0U) /**< \brief (PDCA) Transfer Counter Reload Register 15 */\r
+#define REG_PDCA_CR15 REG_ACCESS(WoReg , 0x400A23D4U) /**< \brief (PDCA) Control Register 15 */\r
+#define REG_PDCA_MR15 REG_ACCESS(RwReg , 0x400A23D8U) /**< \brief (PDCA) Mode Register 15 */\r
+#define REG_PDCA_SR15 REG_ACCESS(RoReg , 0x400A23DCU) /**< \brief (PDCA) Status Register 15 */\r
+#define REG_PDCA_IER15 REG_ACCESS(WoReg , 0x400A23E0U) /**< \brief (PDCA) Interrupt Enable Register 15 */\r
+#define REG_PDCA_IDR15 REG_ACCESS(WoReg , 0x400A23E4U) /**< \brief (PDCA) Interrupt Disable Register 15 */\r
+#define REG_PDCA_IMR15 REG_ACCESS(RoReg , 0x400A23E8U) /**< \brief (PDCA) Interrupt Mask Register 15 */\r
+#define REG_PDCA_ISR15 REG_ACCESS(RoReg , 0x400A23ECU) /**< \brief (PDCA) Interrupt Status Register 15 */\r
+#define REG_PDCA_PCONTROL REG_ACCESS(RwReg , 0x400A2800U) /**< \brief (PDCA) Performance Control Register */ \r
+#define REG_PDCA_PRDATA0 REG_ACCESS(RoReg , 0x400A2804U) /**< \brief (PDCA) Channel 0 Read Data Cycles */ \r
+#define REG_PDCA_PRSTALL0 REG_ACCESS(RoReg , 0x400A2808U) /**< \brief (PDCA) Channel 0 Read Stall Cycles */ \r
+#define REG_PDCA_PRLAT0 REG_ACCESS(RoReg , 0x400A280CU) /**< \brief (PDCA) Channel 0 Read Max Latency */ \r
+#define REG_PDCA_PWDATA0 REG_ACCESS(RoReg , 0x400A2810U) /**< \brief (PDCA) Channel 0 Write Data Cycles */ \r
+#define REG_PDCA_PWSTALL0 REG_ACCESS(RoReg , 0x400A2814U) /**< \brief (PDCA) Channel 0 Write Stall Cycles */ \r
+#define REG_PDCA_PWLAT0 REG_ACCESS(RoReg , 0x400A2818U) /**< \brief (PDCA) Channel0 Write Max Latency */ \r
+#define REG_PDCA_PRDATA1 REG_ACCESS(RoReg , 0x400A281CU) /**< \brief (PDCA) Channel 1 Read Data Cycles */ \r
+#define REG_PDCA_PRSTALL1 REG_ACCESS(RoReg , 0x400A2820U) /**< \brief (PDCA) Channel Read Stall Cycles */ \r
+#define REG_PDCA_PRLAT1 REG_ACCESS(RoReg , 0x400A2824U) /**< \brief (PDCA) Channel 1 Read Max Latency */ \r
+#define REG_PDCA_PWDATA1 REG_ACCESS(RoReg , 0x400A2828U) /**< \brief (PDCA) Channel 1 Write Data Cycles */ \r
+#define REG_PDCA_PWSTALL1 REG_ACCESS(RoReg , 0x400A282CU) /**< \brief (PDCA) Channel 1 Write stall Cycles */ \r
+#define REG_PDCA_PWLAT1 REG_ACCESS(RoReg , 0x400A2830U) /**< \brief (PDCA) Channel 1 Read Max Latency */ \r
+#define REG_PDCA_VERSION REG_ACCESS(RoReg , 0x400A2834U) /**< \brief (PDCA) Version Register */ \r
+/* ========== Register definition for SMAP peripheral ========== */\r
+#define REG_SMAP_CR REG_ACCESS(WoReg , 0x400A3000U) /**< \brief (SMAP) Control Register */ \r
+#define REG_SMAP_SR REG_ACCESS(RoReg , 0x400A3004U) /**< \brief (SMAP) Status Register */ \r
+#define REG_SMAP_SCR REG_ACCESS(WoReg , 0x400A3008U) /**< \brief (SMAP) Status Clear Register */ \r
+#define REG_SMAP_ADDR REG_ACCESS(RwReg , 0x400A300CU) /**< \brief (SMAP) Address Register */ \r
+#define REG_SMAP_LENGTH REG_ACCESS(RwReg , 0x400A3010U) /**< \brief (SMAP) Length Register */ \r
+#define REG_SMAP_DATA REG_ACCESS(RwReg , 0x400A3014U) /**< \brief (SMAP) Data Register */ \r
+#define REG_SMAP_VERSION REG_ACCESS(RoReg , 0x400A3028U) /**< \brief (SMAP) VERSION register */ \r
+#define REG_SMAP_CIDR REG_ACCESS(RoReg , 0x400A30F0U) /**< \brief (SMAP) Chip ID Register */ \r
+#define REG_SMAP_EXID REG_ACCESS(RoReg , 0x400A30F4U) /**< \brief (SMAP) Chip ID Extension Register */ \r
+#define REG_SMAP_IDR REG_ACCESS(RoReg , 0x400A30FCU) /**< \brief (SMAP) AP Identification register */ \r
+/* ========== Register definition for CRCCU peripheral ========== */\r
+#define REG_CRCCU_DSCR REG_ACCESS(RwReg , 0x400A4000U) /**< \brief (CRCCU) Descriptor Base Register */ \r
+#define REG_CRCCU_DMAEN REG_ACCESS(WoReg , 0x400A4008U) /**< \brief (CRCCU) DMA Enable Register */ \r
+#define REG_CRCCU_DMADIS REG_ACCESS(WoReg , 0x400A400CU) /**< \brief (CRCCU) DMA Disable Register */ \r
+#define REG_CRCCU_DMASR REG_ACCESS(RoReg , 0x400A4010U) /**< \brief (CRCCU) DMA Status Register */ \r
+#define REG_CRCCU_DMAIER REG_ACCESS(WoReg , 0x400A4014U) /**< \brief (CRCCU) DMA Interrupt Enable Register */ \r
+#define REG_CRCCU_DMAIDR REG_ACCESS(WoReg , 0x400A4018U) /**< \brief (CRCCU) DMA Interrupt Disable Register */ \r
+#define REG_CRCCU_DMAIMR REG_ACCESS(RoReg , 0x400A401CU) /**< \brief (CRCCU) DMA Interrupt Mask Register */ \r
+#define REG_CRCCU_DMAISR REG_ACCESS(RoReg , 0x400A4020U) /**< \brief (CRCCU) DMA Interrupt Status Register */ \r
+#define REG_CRCCU_CR REG_ACCESS(WoReg , 0x400A4034U) /**< \brief (CRCCU) Control Register */ \r
+#define REG_CRCCU_MR REG_ACCESS(RwReg , 0x400A4038U) /**< \brief (CRCCU) Mode Register */ \r
+#define REG_CRCCU_SR REG_ACCESS(RoReg , 0x400A403CU) /**< \brief (CRCCU) Status Register */ \r
+#define REG_CRCCU_IER REG_ACCESS(WoReg , 0x400A4040U) /**< \brief (CRCCU) Interrupt Enable Register */ \r
+#define REG_CRCCU_IDR REG_ACCESS(WoReg , 0x400A4044U) /**< \brief (CRCCU) Interrupt Disable Register */ \r
+#define REG_CRCCU_IMR REG_ACCESS(RoReg , 0x400A4048U) /**< \brief (CRCCU) Interrupt Mask Register */ \r
+#define REG_CRCCU_ISR REG_ACCESS(RoReg , 0x400A404CU) /**< \brief (CRCCU) Interrupt Status Register */ \r
+#define REG_CRCCU_VERSION REG_ACCESS(RoReg , 0x400A40FCU) /**< \brief (CRCCU) Version Register */ \r
+/* ========== Register definition for USBC peripheral ========== */\r
+#define REG_USBC_UDCON REG_ACCESS(RwReg , 0x400A5000U) /**< \brief (USBC) Device General Control Register */ \r
+#define REG_USBC_UDINT REG_ACCESS(RoReg , 0x400A5004U) /**< \brief (USBC) Device Global Interupt Register */ \r
+#define REG_USBC_UDINTCLR REG_ACCESS(WoReg , 0x400A5008U) /**< \brief (USBC) Device Global Interrupt Clear Register */ \r
+#define REG_USBC_UDINTSET REG_ACCESS(WoReg , 0x400A500CU) /**< \brief (USBC) Device Global Interrupt Set Regsiter */ \r
+#define REG_USBC_UDINTE REG_ACCESS(RoReg , 0x400A5010U) /**< \brief (USBC) Device Global Interrupt Enable Register */ \r
+#define REG_USBC_UDINTECLR REG_ACCESS(WoReg , 0x400A5014U) /**< \brief (USBC) Device Global Interrupt Enable Clear Register */ \r
+#define REG_USBC_UDINTESET REG_ACCESS(WoReg , 0x400A5018U) /**< \brief (USBC) Device Global Interrupt Enable Set Register */ \r
+#define REG_USBC_UERST REG_ACCESS(RwReg , 0x400A501CU) /**< \brief (USBC) Endpoint Enable/Reset Register */ \r
+#define REG_USBC_UDFNUM REG_ACCESS(RoReg , 0x400A5020U) /**< \brief (USBC) Device Frame Number Register */ \r
+#define REG_USBC_UECFG0 REG_ACCESS(RwReg , 0x400A5100U) /**< \brief (USBC) Endpoint Configuration Register */ \r
+#define REG_USBC_UECFG1 REG_ACCESS(RwReg , 0x400A5104U) /**< \brief (USBC) Endpoint Configuration Register */ \r
+#define REG_USBC_UECFG2 REG_ACCESS(RwReg , 0x400A5108U) /**< \brief (USBC) Endpoint Configuration Register */ \r
+#define REG_USBC_UECFG3 REG_ACCESS(RwReg , 0x400A510CU) /**< \brief (USBC) Endpoint Configuration Register */ \r
+#define REG_USBC_UECFG4 REG_ACCESS(RwReg , 0x400A5110U) /**< \brief (USBC) Endpoint Configuration Register */ \r
+#define REG_USBC_UECFG5 REG_ACCESS(RwReg , 0x400A5114U) /**< \brief (USBC) Endpoint Configuration Register */ \r
+#define REG_USBC_UECFG6 REG_ACCESS(RwReg , 0x400A5118U) /**< \brief (USBC) Endpoint Configuration Register */ \r
+#define REG_USBC_UECFG7 REG_ACCESS(RwReg , 0x400A511CU) /**< \brief (USBC) Endpoint Configuration Register */ \r
+#define REG_USBC_UESTA0 REG_ACCESS(RoReg , 0x400A5130U) /**< \brief (USBC) Endpoint Status Register */ \r
+#define REG_USBC_UESTA1 REG_ACCESS(RoReg , 0x400A5134U) /**< \brief (USBC) Endpoint Status Register */ \r
+#define REG_USBC_UESTA2 REG_ACCESS(RoReg , 0x400A5138U) /**< \brief (USBC) Endpoint Status Register */ \r
+#define REG_USBC_UESTA3 REG_ACCESS(RoReg , 0x400A513CU) /**< \brief (USBC) Endpoint Status Register */ \r
+#define REG_USBC_UESTA4 REG_ACCESS(RoReg , 0x400A5140U) /**< \brief (USBC) Endpoint Status Register */ \r
+#define REG_USBC_UESTA5 REG_ACCESS(RoReg , 0x400A5144U) /**< \brief (USBC) Endpoint Status Register */ \r
+#define REG_USBC_UESTA6 REG_ACCESS(RoReg , 0x400A5148U) /**< \brief (USBC) Endpoint Status Register */ \r
+#define REG_USBC_UESTA7 REG_ACCESS(RoReg , 0x400A514CU) /**< \brief (USBC) Endpoint Status Register */ \r
+#define REG_USBC_UESTA0CLR REG_ACCESS(WoReg , 0x400A5160U) /**< \brief (USBC) Endpoint Status Clear Register */ \r
+#define REG_USBC_UESTA1CLR REG_ACCESS(WoReg , 0x400A5164U) /**< \brief (USBC) Endpoint Status Clear Register */ \r
+#define REG_USBC_UESTA2CLR REG_ACCESS(WoReg , 0x400A5168U) /**< \brief (USBC) Endpoint Status Clear Register */ \r
+#define REG_USBC_UESTA3CLR REG_ACCESS(WoReg , 0x400A516CU) /**< \brief (USBC) Endpoint Status Clear Register */ \r
+#define REG_USBC_UESTA4CLR REG_ACCESS(WoReg , 0x400A5170U) /**< \brief (USBC) Endpoint Status Clear Register */ \r
+#define REG_USBC_UESTA5CLR REG_ACCESS(WoReg , 0x400A5174U) /**< \brief (USBC) Endpoint Status Clear Register */ \r
+#define REG_USBC_UESTA6CLR REG_ACCESS(WoReg , 0x400A5178U) /**< \brief (USBC) Endpoint Status Clear Register */ \r
+#define REG_USBC_UESTA7CLR REG_ACCESS(WoReg , 0x400A517CU) /**< \brief (USBC) Endpoint Status Clear Register */ \r
+#define REG_USBC_UESTA0SET REG_ACCESS(WoReg , 0x400A5190U) /**< \brief (USBC) Endpoint Status Set Register */ \r
+#define REG_USBC_UESTA1SET REG_ACCESS(WoReg , 0x400A5194U) /**< \brief (USBC) Endpoint Status Set Register */ \r
+#define REG_USBC_UESTA2SET REG_ACCESS(WoReg , 0x400A5198U) /**< \brief (USBC) Endpoint Status Set Register */ \r
+#define REG_USBC_UESTA3SET REG_ACCESS(WoReg , 0x400A519CU) /**< \brief (USBC) Endpoint Status Set Register */ \r
+#define REG_USBC_UESTA4SET REG_ACCESS(WoReg , 0x400A51A0U) /**< \brief (USBC) Endpoint Status Set Register */ \r
+#define REG_USBC_UESTA5SET REG_ACCESS(WoReg , 0x400A51A4U) /**< \brief (USBC) Endpoint Status Set Register */ \r
+#define REG_USBC_UESTA6SET REG_ACCESS(WoReg , 0x400A51A8U) /**< \brief (USBC) Endpoint Status Set Register */ \r
+#define REG_USBC_UESTA7SET REG_ACCESS(WoReg , 0x400A51ACU) /**< \brief (USBC) Endpoint Status Set Register */ \r
+#define REG_USBC_UECON0 REG_ACCESS(RoReg , 0x400A51C0U) /**< \brief (USBC) Endpoint Control Register */ \r
+#define REG_USBC_UECON1 REG_ACCESS(RoReg , 0x400A51C4U) /**< \brief (USBC) Endpoint Control Register */ \r
+#define REG_USBC_UECON2 REG_ACCESS(RoReg , 0x400A51C8U) /**< \brief (USBC) Endpoint Control Register */ \r
+#define REG_USBC_UECON3 REG_ACCESS(RoReg , 0x400A51CCU) /**< \brief (USBC) Endpoint Control Register */ \r
+#define REG_USBC_UECON4 REG_ACCESS(RoReg , 0x400A51D0U) /**< \brief (USBC) Endpoint Control Register */ \r
+#define REG_USBC_UECON5 REG_ACCESS(RoReg , 0x400A51D4U) /**< \brief (USBC) Endpoint Control Register */ \r
+#define REG_USBC_UECON6 REG_ACCESS(RoReg , 0x400A51D8U) /**< \brief (USBC) Endpoint Control Register */ \r
+#define REG_USBC_UECON7 REG_ACCESS(RoReg , 0x400A51DCU) /**< \brief (USBC) Endpoint Control Register */ \r
+#define REG_USBC_UECON0SET REG_ACCESS(WoReg , 0x400A51F0U) /**< \brief (USBC) Endpoint Control Set Register */ \r
+#define REG_USBC_UECON1SET REG_ACCESS(WoReg , 0x400A51F4U) /**< \brief (USBC) Endpoint Control Set Register */ \r
+#define REG_USBC_UECON2SET REG_ACCESS(WoReg , 0x400A51F8U) /**< \brief (USBC) Endpoint Control Set Register */ \r
+#define REG_USBC_UECON3SET REG_ACCESS(WoReg , 0x400A51FCU) /**< \brief (USBC) Endpoint Control Set Register */ \r
+#define REG_USBC_UECON4SET REG_ACCESS(WoReg , 0x400A5200U) /**< \brief (USBC) Endpoint Control Set Register */ \r
+#define REG_USBC_UECON5SET REG_ACCESS(WoReg , 0x400A5204U) /**< \brief (USBC) Endpoint Control Set Register */ \r
+#define REG_USBC_UECON6SET REG_ACCESS(WoReg , 0x400A5208U) /**< \brief (USBC) Endpoint Control Set Register */ \r
+#define REG_USBC_UECON7SET REG_ACCESS(WoReg , 0x400A520CU) /**< \brief (USBC) Endpoint Control Set Register */ \r
+#define REG_USBC_UECON0CLR REG_ACCESS(WoReg , 0x400A5220U) /**< \brief (USBC) Endpoint Control Clear Register */ \r
+#define REG_USBC_UECON1CLR REG_ACCESS(WoReg , 0x400A5224U) /**< \brief (USBC) TXINE Clear */ \r
+#define REG_USBC_UECON2CLR REG_ACCESS(WoReg , 0x400A5228U) /**< \brief (USBC) TXINE Clear */ \r
+#define REG_USBC_UECON3CLR REG_ACCESS(WoReg , 0x400A522CU) /**< \brief (USBC) TXINE Clear */ \r
+#define REG_USBC_UECON4CLR REG_ACCESS(WoReg , 0x400A5230U) /**< \brief (USBC) TXINE Clear */ \r
+#define REG_USBC_UECON5CLR REG_ACCESS(WoReg , 0x400A5234U) /**< \brief (USBC) TXINE Clear */ \r
+#define REG_USBC_UECON6CLR REG_ACCESS(WoReg , 0x400A5238U) /**< \brief (USBC) TXINE Clear */ \r
+#define REG_USBC_UECON7CLR REG_ACCESS(WoReg , 0x400A523CU) /**< \brief (USBC) TXINE Clear */ \r
+#define REG_USBC_UHCON REG_ACCESS(RwReg , 0x400A5400U) /**< \brief (USBC) Host General Control Register */ \r
+#define REG_USBC_UHINT REG_ACCESS(RoReg , 0x400A5404U) /**< \brief (USBC) Host Global Interrupt Register */ \r
+#define REG_USBC_UHINTCLR REG_ACCESS(WoReg , 0x400A5408U) /**< \brief (USBC) Host Global Interrrupt Clear Register */ \r
+#define REG_USBC_UHINTSET REG_ACCESS(WoReg , 0x400A540CU) /**< \brief (USBC) Host Global Interrupt Set Register */ \r
+#define REG_USBC_UHINTE REG_ACCESS(RoReg , 0x400A5410U) /**< \brief (USBC) Host Global Interrupt Enable Register */ \r
+#define REG_USBC_UHINTECLR REG_ACCESS(WoReg , 0x400A5414U) /**< \brief (USBC) Host Global Interrupt Enable Clear Register */ \r
+#define REG_USBC_UHINTESET REG_ACCESS(WoReg , 0x400A5418U) /**< \brief (USBC) Host Global Interrupt Enable Set Register */ \r
+#define REG_USBC_UPRST REG_ACCESS(RwReg , 0x400A541CU) /**< \brief (USBC) Pipe Reset Register */ \r
+#define REG_USBC_UHFNUM REG_ACCESS(RwReg , 0x400A5420U) /**< \brief (USBC) Host Frame Number Register */ \r
+#define REG_USBC_UHSOFC REG_ACCESS(RwReg , 0x400A5424U) /**< \brief (USBC) Host Start of Frame Control Register */ \r
+#define REG_USBC_UPCFG0 REG_ACCESS(RwReg , 0x400A5500U) /**< \brief (USBC) Pipe Configuration Register */ \r
+#define REG_USBC_UPCFG1 REG_ACCESS(RwReg , 0x400A5504U) /**< \brief (USBC) Pipe Configuration Register */ \r
+#define REG_USBC_UPCFG2 REG_ACCESS(RwReg , 0x400A5508U) /**< \brief (USBC) Pipe Configuration Register */ \r
+#define REG_USBC_UPCFG3 REG_ACCESS(RwReg , 0x400A550CU) /**< \brief (USBC) Pipe Configuration Register */ \r
+#define REG_USBC_UPCFG4 REG_ACCESS(RwReg , 0x400A5510U) /**< \brief (USBC) Pipe Configuration Register */ \r
+#define REG_USBC_UPCFG5 REG_ACCESS(RwReg , 0x400A5514U) /**< \brief (USBC) Pipe Configuration Register */ \r
+#define REG_USBC_UPCFG6 REG_ACCESS(RwReg , 0x400A5518U) /**< \brief (USBC) Pipe Configuration Register */ \r
+#define REG_USBC_UPCFG7 REG_ACCESS(RwReg , 0x400A551CU) /**< \brief (USBC) Pipe Configuration Register */ \r
+#define REG_USBC_UPSTA0 REG_ACCESS(RoReg , 0x400A5530U) /**< \brief (USBC) Pipe Status Register */ \r
+#define REG_USBC_UPSTA1 REG_ACCESS(RoReg , 0x400A5534U) /**< \brief (USBC) Pipe Status Register */ \r
+#define REG_USBC_UPSTA2 REG_ACCESS(RoReg , 0x400A5538U) /**< \brief (USBC) Pipe Status Register */ \r
+#define REG_USBC_UPSTA3 REG_ACCESS(RoReg , 0x400A553CU) /**< \brief (USBC) Pipe Status Register */ \r
+#define REG_USBC_UPSTA4 REG_ACCESS(RoReg , 0x400A5540U) /**< \brief (USBC) Pipe Status Register */ \r
+#define REG_USBC_UPSTA5 REG_ACCESS(RoReg , 0x400A5544U) /**< \brief (USBC) Pipe Status Register */ \r
+#define REG_USBC_UPSTA6 REG_ACCESS(RoReg , 0x400A5548U) /**< \brief (USBC) Pipe Status Register */ \r
+#define REG_USBC_UPSTA7 REG_ACCESS(RoReg , 0x400A554CU) /**< \brief (USBC) Pipe Status Register */ \r
+#define REG_USBC_UPSTA0CLR REG_ACCESS(WoReg , 0x400A5560U) /**< \brief (USBC) Pipe Status Clear Register */ \r
+#define REG_USBC_UPSTA1CLR REG_ACCESS(WoReg , 0x400A5564U) /**< \brief (USBC) Pipe Status Clear Register */ \r
+#define REG_USBC_UPSTA2CLR REG_ACCESS(WoReg , 0x400A5568U) /**< \brief (USBC) Pipe Status Clear Register */ \r
+#define REG_USBC_UPSTA3CLR REG_ACCESS(WoReg , 0x400A556CU) /**< \brief (USBC) Pipe Status Clear Register */ \r
+#define REG_USBC_UPSTA4CLR REG_ACCESS(WoReg , 0x400A5570U) /**< \brief (USBC) Pipe Status Clear Register */ \r
+#define REG_USBC_UPSTA5CLR REG_ACCESS(WoReg , 0x400A5574U) /**< \brief (USBC) Pipe Status Clear Register */ \r
+#define REG_USBC_UPSTA6CLR REG_ACCESS(WoReg , 0x400A5578U) /**< \brief (USBC) Pipe Status Clear Register */ \r
+#define REG_USBC_UPSTA7CLR REG_ACCESS(WoReg , 0x400A557CU) /**< \brief (USBC) Pipe Status Clear Register */ \r
+#define REG_USBC_UPSTA0SET REG_ACCESS(WoReg , 0x400A5590U) /**< \brief (USBC) Pipe Status Set Register */ \r
+#define REG_USBC_UPSTA1SET REG_ACCESS(WoReg , 0x400A5594U) /**< \brief (USBC) Pipe Status Set Register */ \r
+#define REG_USBC_UPSTA2SET REG_ACCESS(WoReg , 0x400A5598U) /**< \brief (USBC) Pipe Status Set Register */ \r
+#define REG_USBC_UPSTA3SET REG_ACCESS(WoReg , 0x400A559CU) /**< \brief (USBC) Pipe Status Set Register */ \r
+#define REG_USBC_UPSTA4SET REG_ACCESS(WoReg , 0x400A55A0U) /**< \brief (USBC) Pipe Status Set Register */ \r
+#define REG_USBC_UPSTA5SET REG_ACCESS(WoReg , 0x400A55A4U) /**< \brief (USBC) Pipe Status Set Register */ \r
+#define REG_USBC_UPSTA6SET REG_ACCESS(WoReg , 0x400A55A8U) /**< \brief (USBC) Pipe Status Set Register */ \r
+#define REG_USBC_UPSTA7SET REG_ACCESS(WoReg , 0x400A55ACU) /**< \brief (USBC) Pipe Status Set Register */ \r
+#define REG_USBC_UPCON0 REG_ACCESS(RoReg , 0x400A55C0U) /**< \brief (USBC) Pipe Control Register */ \r
+#define REG_USBC_UPCON1 REG_ACCESS(RoReg , 0x400A55C4U) /**< \brief (USBC) Pipe Control Register */ \r
+#define REG_USBC_UPCON2 REG_ACCESS(RoReg , 0x400A55C8U) /**< \brief (USBC) Pipe Control Register */ \r
+#define REG_USBC_UPCON3 REG_ACCESS(RoReg , 0x400A55CCU) /**< \brief (USBC) Pipe Control Register */ \r
+#define REG_USBC_UPCON4 REG_ACCESS(RoReg , 0x400A55D0U) /**< \brief (USBC) Pipe Control Register */ \r
+#define REG_USBC_UPCON5 REG_ACCESS(RoReg , 0x400A55D4U) /**< \brief (USBC) Pipe Control Register */ \r
+#define REG_USBC_UPCON6 REG_ACCESS(RoReg , 0x400A55D8U) /**< \brief (USBC) Pipe Control Register */ \r
+#define REG_USBC_UPCON7 REG_ACCESS(RoReg , 0x400A55DCU) /**< \brief (USBC) Pipe Control Register */ \r
+#define REG_USBC_UPCON0SET REG_ACCESS(WoReg , 0x400A55F0U) /**< \brief (USBC) Pipe Control Set Register */ \r
+#define REG_USBC_UPCON1SET REG_ACCESS(WoReg , 0x400A55F4U) /**< \brief (USBC) Pipe Control Set Register */ \r
+#define REG_USBC_UPCON2SET REG_ACCESS(WoReg , 0x400A55F8U) /**< \brief (USBC) Pipe Control Set Register */ \r
+#define REG_USBC_UPCON3SET REG_ACCESS(WoReg , 0x400A55FCU) /**< \brief (USBC) Pipe Control Set Register */ \r
+#define REG_USBC_UPCON4SET REG_ACCESS(WoReg , 0x400A5600U) /**< \brief (USBC) Pipe Control Set Register */ \r
+#define REG_USBC_UPCON5SET REG_ACCESS(WoReg , 0x400A5604U) /**< \brief (USBC) Pipe Control Set Register */ \r
+#define REG_USBC_UPCON6SET REG_ACCESS(WoReg , 0x400A5608U) /**< \brief (USBC) Pipe Control Set Register */ \r
+#define REG_USBC_UPCON7SET REG_ACCESS(WoReg , 0x400A560CU) /**< \brief (USBC) Pipe Control Set Register */ \r
+#define REG_USBC_UPCON0CLR REG_ACCESS(WoReg , 0x400A5620U) /**< \brief (USBC) Pipe Control Clear Register */ \r
+#define REG_USBC_UPCON1CLR REG_ACCESS(WoReg , 0x400A5624U) /**< \brief (USBC) Pipe Control Clear Register */ \r
+#define REG_USBC_UPCON2CLR REG_ACCESS(WoReg , 0x400A5628U) /**< \brief (USBC) Pipe Control Clear Register */ \r
+#define REG_USBC_UPCON3CLR REG_ACCESS(WoReg , 0x400A562CU) /**< \brief (USBC) Pipe Control Clear Register */ \r
+#define REG_USBC_UPCON4CLR REG_ACCESS(WoReg , 0x400A5630U) /**< \brief (USBC) Pipe Control Clear Register */ \r
+#define REG_USBC_UPCON5CLR REG_ACCESS(WoReg , 0x400A5634U) /**< \brief (USBC) Pipe Control Clear Register */ \r
+#define REG_USBC_UPCON6CLR REG_ACCESS(WoReg , 0x400A5638U) /**< \brief (USBC) Pipe Control Clear Register */ \r
+#define REG_USBC_UPCON7CLR REG_ACCESS(WoReg , 0x400A563CU) /**< \brief (USBC) Pipe Control Clear Register */ \r
+#define REG_USBC_UPINRQ0 REG_ACCESS(RwReg , 0x400A5650U) /**< \brief (USBC) Pipe In Request */ \r
+#define REG_USBC_UPINRQ1 REG_ACCESS(RwReg , 0x400A5654U) /**< \brief (USBC) Pipe In Request */ \r
+#define REG_USBC_UPINRQ2 REG_ACCESS(RwReg , 0x400A5658U) /**< \brief (USBC) Pipe In Request */ \r
+#define REG_USBC_UPINRQ3 REG_ACCESS(RwReg , 0x400A565CU) /**< \brief (USBC) Pipe In Request */ \r
+#define REG_USBC_UPINRQ4 REG_ACCESS(RwReg , 0x400A5660U) /**< \brief (USBC) Pipe In Request */ \r
+#define REG_USBC_UPINRQ5 REG_ACCESS(RwReg , 0x400A5664U) /**< \brief (USBC) Pipe In Request */ \r
+#define REG_USBC_UPINRQ6 REG_ACCESS(RwReg , 0x400A5668U) /**< \brief (USBC) Pipe In Request */ \r
+#define REG_USBC_UPINRQ7 REG_ACCESS(RwReg , 0x400A566CU) /**< \brief (USBC) Pipe In Request */ \r
+#define REG_USBC_USBCON REG_ACCESS(RwReg , 0x400A5800U) /**< \brief (USBC) General Control Register */ \r
+#define REG_USBC_USBSTA REG_ACCESS(RoReg , 0x400A5804U) /**< \brief (USBC) General Status Register */ \r
+#define REG_USBC_USBSTACLR REG_ACCESS(WoReg , 0x400A5808U) /**< \brief (USBC) General Status Clear Register */ \r
+#define REG_USBC_USBSTASET REG_ACCESS(WoReg , 0x400A580CU) /**< \brief (USBC) General Status Set Register */ \r
+#define REG_USBC_UVERS REG_ACCESS(RoReg , 0x400A5818U) /**< \brief (USBC) IP Version Register */ \r
+#define REG_USBC_UFEATURES REG_ACCESS(RoReg , 0x400A581CU) /**< \brief (USBC) IP Features Register */ \r
+#define REG_USBC_UADDRSIZE REG_ACCESS(RoReg , 0x400A5820U) /**< \brief (USBC) IP PB address size Register */ \r
+#define REG_USBC_UNAME1 REG_ACCESS(RoReg , 0x400A5824U) /**< \brief (USBC) IP Name Part One: HUSB */ \r
+#define REG_USBC_UNAME2 REG_ACCESS(RoReg , 0x400A5828U) /**< \brief (USBC) IP Name Part Two: HOST */ \r
+#define REG_USBC_USBFSM REG_ACCESS(RoReg , 0x400A582CU) /**< \brief (USBC) USB internal finite state machine */ \r
+#define REG_USBC_UDESC REG_ACCESS(RwReg , 0x400A5830U) /**< \brief (USBC) Endpoint descriptor table */ \r
+/* ========== Register definition for PEVC peripheral ========== */\r
+#define REG_PEVC_CHSR REG_ACCESS(RoReg , 0x400A6000U) /**< \brief (PEVC) Channel Status Register */ \r
+#define REG_PEVC_CHER REG_ACCESS(WoReg , 0x400A6004U) /**< \brief (PEVC) Channel Enable Register */ \r
+#define REG_PEVC_CHDR REG_ACCESS(WoReg , 0x400A6008U) /**< \brief (PEVC) Channel Disable Register */ \r
+#define REG_PEVC_SEV REG_ACCESS(WoReg , 0x400A6010U) /**< \brief (PEVC) Software Event */ \r
+#define REG_PEVC_BUSY REG_ACCESS(RoReg , 0x400A6014U) /**< \brief (PEVC) Channel / User Busy */ \r
+#define REG_PEVC_TRIER REG_ACCESS(WoReg , 0x400A6020U) /**< \brief (PEVC) Trigger Interrupt Mask Enable Register */ \r
+#define REG_PEVC_TRIDR REG_ACCESS(WoReg , 0x400A6024U) /**< \brief (PEVC) Trigger Interrupt Mask Disable Register */ \r
+#define REG_PEVC_TRIMR REG_ACCESS(RoReg , 0x400A6028U) /**< \brief (PEVC) Trigger Interrupt Mask Register */ \r
+#define REG_PEVC_TRSR REG_ACCESS(RoReg , 0x400A6030U) /**< \brief (PEVC) Trigger Status Register */ \r
+#define REG_PEVC_TRSCR REG_ACCESS(WoReg , 0x400A6034U) /**< \brief (PEVC) Trigger Status Clear Register */ \r
+#define REG_PEVC_OVIER REG_ACCESS(WoReg , 0x400A6040U) /**< \brief (PEVC) Overrun Interrupt Mask Enable Register */ \r
+#define REG_PEVC_OVIDR REG_ACCESS(WoReg , 0x400A6044U) /**< \brief (PEVC) Overrun Interrupt Mask Disable Register */ \r
+#define REG_PEVC_OVIMR REG_ACCESS(RoReg , 0x400A6048U) /**< \brief (PEVC) Overrun Interrupt Mask Register */ \r
+#define REG_PEVC_OVSR REG_ACCESS(RoReg , 0x400A6050U) /**< \brief (PEVC) Overrun Status Register */ \r
+#define REG_PEVC_OVSCR REG_ACCESS(WoReg , 0x400A6054U) /**< \brief (PEVC) Overrun Status Clear Register */ \r
+#define REG_PEVC_CHMX0 REG_ACCESS(RwReg , 0x400A6100U) /**< \brief (PEVC) Channel Multiplexer 0 0 */\r
+#define REG_PEVC_CHMX1 REG_ACCESS(RwReg , 0x400A6104U) /**< \brief (PEVC) Channel Multiplexer 0 1 */\r
+#define REG_PEVC_CHMX2 REG_ACCESS(RwReg , 0x400A6108U) /**< \brief (PEVC) Channel Multiplexer 0 2 */\r
+#define REG_PEVC_CHMX3 REG_ACCESS(RwReg , 0x400A610CU) /**< \brief (PEVC) Channel Multiplexer 0 3 */\r
+#define REG_PEVC_CHMX4 REG_ACCESS(RwReg , 0x400A6110U) /**< \brief (PEVC) Channel Multiplexer 0 4 */\r
+#define REG_PEVC_CHMX5 REG_ACCESS(RwReg , 0x400A6114U) /**< \brief (PEVC) Channel Multiplexer 0 5 */\r
+#define REG_PEVC_CHMX6 REG_ACCESS(RwReg , 0x400A6118U) /**< \brief (PEVC) Channel Multiplexer 0 6 */\r
+#define REG_PEVC_CHMX7 REG_ACCESS(RwReg , 0x400A611CU) /**< \brief (PEVC) Channel Multiplexer 0 7 */\r
+#define REG_PEVC_CHMX8 REG_ACCESS(RwReg , 0x400A6120U) /**< \brief (PEVC) Channel Multiplexer 0 8 */\r
+#define REG_PEVC_CHMX9 REG_ACCESS(RwReg , 0x400A6124U) /**< \brief (PEVC) Channel Multiplexer 0 9 */\r
+#define REG_PEVC_CHMX10 REG_ACCESS(RwReg , 0x400A6128U) /**< \brief (PEVC) Channel Multiplexer 0 10 */\r
+#define REG_PEVC_CHMX11 REG_ACCESS(RwReg , 0x400A612CU) /**< \brief (PEVC) Channel Multiplexer 0 11 */\r
+#define REG_PEVC_CHMX12 REG_ACCESS(RwReg , 0x400A6130U) /**< \brief (PEVC) Channel Multiplexer 0 12 */\r
+#define REG_PEVC_CHMX13 REG_ACCESS(RwReg , 0x400A6134U) /**< \brief (PEVC) Channel Multiplexer 0 13 */\r
+#define REG_PEVC_CHMX14 REG_ACCESS(RwReg , 0x400A6138U) /**< \brief (PEVC) Channel Multiplexer 0 14 */\r
+#define REG_PEVC_CHMX15 REG_ACCESS(RwReg , 0x400A613CU) /**< \brief (PEVC) Channel Multiplexer 0 15 */\r
+#define REG_PEVC_CHMX16 REG_ACCESS(RwReg , 0x400A6140U) /**< \brief (PEVC) Channel Multiplexer 0 16 */\r
+#define REG_PEVC_CHMX17 REG_ACCESS(RwReg , 0x400A6144U) /**< \brief (PEVC) Channel Multiplexer 0 17 */\r
+#define REG_PEVC_CHMX18 REG_ACCESS(RwReg , 0x400A6148U) /**< \brief (PEVC) Channel Multiplexer 0 18 */\r
+#define REG_PEVC_EVS0 REG_ACCESS(RwReg , 0x400A6200U) /**< \brief (PEVC) Event Shaper 0 0 */\r
+#define REG_PEVC_EVS1 REG_ACCESS(RwReg , 0x400A6204U) /**< \brief (PEVC) Event Shaper 0 1 */\r
+#define REG_PEVC_EVS2 REG_ACCESS(RwReg , 0x400A6208U) /**< \brief (PEVC) Event Shaper 0 2 */\r
+#define REG_PEVC_EVS3 REG_ACCESS(RwReg , 0x400A620CU) /**< \brief (PEVC) Event Shaper 0 3 */\r
+#define REG_PEVC_EVS4 REG_ACCESS(RwReg , 0x400A6210U) /**< \brief (PEVC) Event Shaper 0 4 */\r
+#define REG_PEVC_EVS5 REG_ACCESS(RwReg , 0x400A6214U) /**< \brief (PEVC) Event Shaper 0 5 */\r
+#define REG_PEVC_EVS6 REG_ACCESS(RwReg , 0x400A6218U) /**< \brief (PEVC) Event Shaper 0 6 */\r
+#define REG_PEVC_EVS7 REG_ACCESS(RwReg , 0x400A621CU) /**< \brief (PEVC) Event Shaper 0 7 */\r
+#define REG_PEVC_EVS8 REG_ACCESS(RwReg , 0x400A6220U) /**< \brief (PEVC) Event Shaper 0 8 */\r
+#define REG_PEVC_EVS9 REG_ACCESS(RwReg , 0x400A6224U) /**< \brief (PEVC) Event Shaper 0 9 */\r
+#define REG_PEVC_EVS10 REG_ACCESS(RwReg , 0x400A6228U) /**< \brief (PEVC) Event Shaper 0 10 */\r
+#define REG_PEVC_EVS11 REG_ACCESS(RwReg , 0x400A622CU) /**< \brief (PEVC) Event Shaper 0 11 */\r
+#define REG_PEVC_EVS12 REG_ACCESS(RwReg , 0x400A6230U) /**< \brief (PEVC) Event Shaper 0 12 */\r
+#define REG_PEVC_EVS13 REG_ACCESS(RwReg , 0x400A6234U) /**< \brief (PEVC) Event Shaper 0 13 */\r
+#define REG_PEVC_EVS14 REG_ACCESS(RwReg , 0x400A6238U) /**< \brief (PEVC) Event Shaper 0 14 */\r
+#define REG_PEVC_EVS15 REG_ACCESS(RwReg , 0x400A623CU) /**< \brief (PEVC) Event Shaper 0 15 */\r
+#define REG_PEVC_EVS16 REG_ACCESS(RwReg , 0x400A6240U) /**< \brief (PEVC) Event Shaper 0 16 */\r
+#define REG_PEVC_EVS17 REG_ACCESS(RwReg , 0x400A6244U) /**< \brief (PEVC) Event Shaper 0 17 */\r
+#define REG_PEVC_EVS18 REG_ACCESS(RwReg , 0x400A6248U) /**< \brief (PEVC) Event Shaper 0 18 */\r
+#define REG_PEVC_EVS19 REG_ACCESS(RwReg , 0x400A624CU) /**< \brief (PEVC) Event Shaper 0 19 */\r
+#define REG_PEVC_EVS20 REG_ACCESS(RwReg , 0x400A6250U) /**< \brief (PEVC) Event Shaper 0 20 */\r
+#define REG_PEVC_EVS21 REG_ACCESS(RwReg , 0x400A6254U) /**< \brief (PEVC) Event Shaper 0 21 */\r
+#define REG_PEVC_EVS22 REG_ACCESS(RwReg , 0x400A6258U) /**< \brief (PEVC) Event Shaper 0 22 */\r
+#define REG_PEVC_EVS23 REG_ACCESS(RwReg , 0x400A625CU) /**< \brief (PEVC) Event Shaper 0 23 */\r
+#define REG_PEVC_EVS24 REG_ACCESS(RwReg , 0x400A6260U) /**< \brief (PEVC) Event Shaper 0 24 */\r
+#define REG_PEVC_EVS25 REG_ACCESS(RwReg , 0x400A6264U) /**< \brief (PEVC) Event Shaper 0 25 */\r
+#define REG_PEVC_EVS26 REG_ACCESS(RwReg , 0x400A6268U) /**< \brief (PEVC) Event Shaper 0 26 */\r
+#define REG_PEVC_EVS27 REG_ACCESS(RwReg , 0x400A626CU) /**< \brief (PEVC) Event Shaper 0 27 */\r
+#define REG_PEVC_EVS28 REG_ACCESS(RwReg , 0x400A6270U) /**< \brief (PEVC) Event Shaper 0 28 */\r
+#define REG_PEVC_EVS29 REG_ACCESS(RwReg , 0x400A6274U) /**< \brief (PEVC) Event Shaper 0 29 */\r
+#define REG_PEVC_EVS30 REG_ACCESS(RwReg , 0x400A6278U) /**< \brief (PEVC) Event Shaper 0 30 */\r
+#define REG_PEVC_IGFDR REG_ACCESS(RwReg , 0x400A6300U) /**< \brief (PEVC) Input Glitch Filter Divider Register */ \r
+#define REG_PEVC_PARAMETER REG_ACCESS(RoReg , 0x400A63F8U) /**< \brief (PEVC) Parameter */ \r
+#define REG_PEVC_VERSION REG_ACCESS(RoReg , 0x400A63FCU) /**< \brief (PEVC) Version */ \r
+/* ========== Register definition for AESA peripheral ========== */\r
+#define REG_AESA_CTRL REG_ACCESS(RwReg , 0x400B0000U) /**< \brief (AESA) Control Register */ \r
+#define REG_AESA_MODE REG_ACCESS(RwReg , 0x400B0004U) /**< \brief (AESA) Mode Register */ \r
+#define REG_AESA_DATABUFPTR REG_ACCESS(RwReg , 0x400B0008U) /**< \brief (AESA) Data Buffer Pointer Register */ \r
+#define REG_AESA_SR REG_ACCESS(RoReg , 0x400B000CU) /**< \brief (AESA) Status Register */ \r
+#define REG_AESA_IER REG_ACCESS(WoReg , 0x400B0010U) /**< \brief (AESA) Interrupt Enable Register */ \r
+#define REG_AESA_IDR REG_ACCESS(WoReg , 0x400B0014U) /**< \brief (AESA) Interrupt Disable Register */ \r
+#define REG_AESA_IMR REG_ACCESS(RoReg , 0x400B0018U) /**< \brief (AESA) Interrupt Mask Register */ \r
+#define REG_AESA_KEY0 REG_ACCESS(WoReg , 0x400B0020U) /**< \brief (AESA) Key Register 0 0 */\r
+#define REG_AESA_KEY1 REG_ACCESS(WoReg , 0x400B0024U) /**< \brief (AESA) Key Register 0 1 */\r
+#define REG_AESA_KEY2 REG_ACCESS(WoReg , 0x400B0028U) /**< \brief (AESA) Key Register 0 2 */\r
+#define REG_AESA_KEY3 REG_ACCESS(WoReg , 0x400B002CU) /**< \brief (AESA) Key Register 0 3 */\r
+#define REG_AESA_KEY4 REG_ACCESS(WoReg , 0x400B0030U) /**< \brief (AESA) Key Register 0 4 */\r
+#define REG_AESA_KEY5 REG_ACCESS(WoReg , 0x400B0034U) /**< \brief (AESA) Key Register 0 5 */\r
+#define REG_AESA_KEY6 REG_ACCESS(WoReg , 0x400B0038U) /**< \brief (AESA) Key Register 0 6 */\r
+#define REG_AESA_KEY7 REG_ACCESS(WoReg , 0x400B003CU) /**< \brief (AESA) Key Register 0 7 */\r
+#define REG_AESA_INITVECT0 REG_ACCESS(WoReg , 0x400B0040U) /**< \brief (AESA) Initialization Vector Register 0 0 */\r
+#define REG_AESA_INITVECT1 REG_ACCESS(WoReg , 0x400B0044U) /**< \brief (AESA) Initialization Vector Register 0 1 */\r
+#define REG_AESA_INITVECT2 REG_ACCESS(WoReg , 0x400B0048U) /**< \brief (AESA) Initialization Vector Register 0 2 */\r
+#define REG_AESA_INITVECT3 REG_ACCESS(WoReg , 0x400B004CU) /**< \brief (AESA) Initialization Vector Register 0 3 */\r
+#define REG_AESA_IDATA REG_ACCESS(WoReg , 0x400B0050U) /**< \brief (AESA) Input Data Register */ \r
+#define REG_AESA_ODATA REG_ACCESS(RoReg , 0x400B0060U) /**< \brief (AESA) Output Data Register */ \r
+#define REG_AESA_DRNGSEED REG_ACCESS(WoReg , 0x400B0070U) /**< \brief (AESA) DRNG Seed Register */ \r
+#define REG_AESA_PARAMETER REG_ACCESS(RoReg , 0x400B00F8U) /**< \brief (AESA) Parameter Register */ \r
+#define REG_AESA_VERSION REG_ACCESS(RoReg , 0x400B00FCU) /**< \brief (AESA) Version Register */ \r
+/* ========== Register definition for PM peripheral ========== */\r
+#define REG_PM_MCCTRL REG_ACCESS(RwReg , 0x400E0000U) /**< \brief (PM) Main Clock Control */ \r
+#define REG_PM_CPUSEL REG_ACCESS(RwReg , 0x400E0004U) /**< \brief (PM) CPU Clock Select */ \r
+#define REG_PM_PBASEL REG_ACCESS(RwReg , 0x400E000CU) /**< \brief (PM) PBA Clock Select */ \r
+#define REG_PM_PBBSEL REG_ACCESS(RwReg , 0x400E0010U) /**< \brief (PM) PBB Clock Select */ \r
+#define REG_PM_PBCSEL REG_ACCESS(RwReg , 0x400E0014U) /**< \brief (PM) PBC Clock Select */ \r
+#define REG_PM_PBDSEL REG_ACCESS(RwReg , 0x400E0018U) /**< \brief (PM) PBD Clock Select */ \r
+#define REG_PM_CPUMASK REG_ACCESS(RwReg , 0x400E0020U) /**< \brief (PM) CPU Mask */ \r
+#define REG_PM_HSBMASK REG_ACCESS(RwReg , 0x400E0024U) /**< \brief (PM) HSB Mask */ \r
+#define REG_PM_PBAMASK REG_ACCESS(RwReg , 0x400E0028U) /**< \brief (PM) PBA Mask */ \r
+#define REG_PM_PBBMASK REG_ACCESS(RwReg , 0x400E002CU) /**< \brief (PM) PBB Mask */ \r
+#define REG_PM_PBCMASK REG_ACCESS(RwReg , 0x400E0030U) /**< \brief (PM) PBC Mask */ \r
+#define REG_PM_PBDMASK REG_ACCESS(RwReg , 0x400E0034U) /**< \brief (PM) PBD Mask */ \r
+#define REG_PM_PBADIVMASK REG_ACCESS(RwReg , 0x400E0040U) /**< \brief (PM) PBA Divided Clock Mask */ \r
+#define REG_PM_CFDCTRL REG_ACCESS(RwReg , 0x400E0054U) /**< \brief (PM) Clock Failure Detector Control */ \r
+#define REG_PM_UNLOCK REG_ACCESS(WoReg , 0x400E0058U) /**< \brief (PM) Unlock Register */ \r
+#define REG_PM_IER REG_ACCESS(WoReg , 0x400E00C0U) /**< \brief (PM) Interrupt Enable Register */ \r
+#define REG_PM_IDR REG_ACCESS(WoReg , 0x400E00C4U) /**< \brief (PM) Interrupt Disable Register */ \r
+#define REG_PM_IMR REG_ACCESS(RoReg , 0x400E00C8U) /**< \brief (PM) Interrupt Mask Register */ \r
+#define REG_PM_ISR REG_ACCESS(RoReg , 0x400E00CCU) /**< \brief (PM) Interrupt Status Register */ \r
+#define REG_PM_ICR REG_ACCESS(WoReg , 0x400E00D0U) /**< \brief (PM) Interrupt Clear Register */ \r
+#define REG_PM_SR REG_ACCESS(RoReg , 0x400E00D4U) /**< \brief (PM) Status Register */ \r
+#define REG_PM_PPCR REG_ACCESS(RwReg , 0x400E0160U) /**< \brief (PM) Peripheral Power Control Register */ \r
+#define REG_PM_RCAUSE REG_ACCESS(RoReg , 0x400E0180U) /**< \brief (PM) Reset Cause Register */ \r
+#define REG_PM_WCAUSE REG_ACCESS(RoReg , 0x400E0184U) /**< \brief (PM) Wake Cause Register */ \r
+#define REG_PM_AWEN REG_ACCESS(RwReg , 0x400E0188U) /**< \brief (PM) Asynchronous Wake Enable */ \r
+#define REG_PM_OBS REG_ACCESS(RwReg , 0x400E0190U) /**< \brief (PM) Obsvervability */ \r
+#define REG_PM_FASTSLEEP REG_ACCESS(RwReg , 0x400E0194U) /**< \brief (PM) Fast Sleep Register */ \r
+#define REG_PM_CONFIG REG_ACCESS(RoReg , 0x400E03F8U) /**< \brief (PM) Configuration Register */ \r
+#define REG_PM_VERSION REG_ACCESS(RoReg , 0x400E03FCU) /**< \brief (PM) Version Register */ \r
+/* ========== Register definition for CHIPID peripheral ========== */\r
+#define REG_CHIPID_CIDR REG_ACCESS(RoReg , 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ \r
+#define REG_CHIPID_EXID REG_ACCESS(RoReg , 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ \r
+/* ========== Register definition for SCIF peripheral ========== */\r
+#define REG_SCIF_IER REG_ACCESS(WoReg , 0x400E0800U) /**< \brief (SCIF) Interrupt Enable Register */ \r
+#define REG_SCIF_IDR REG_ACCESS(WoReg , 0x400E0804U) /**< \brief (SCIF) Interrupt Disable Register */ \r
+#define REG_SCIF_IMR REG_ACCESS(RoReg , 0x400E0808U) /**< \brief (SCIF) Interrupt Mask Register */ \r
+#define REG_SCIF_ISR REG_ACCESS(RoReg , 0x400E080CU) /**< \brief (SCIF) Interrupt Status Register */ \r
+#define REG_SCIF_ICR REG_ACCESS(WoReg , 0x400E0810U) /**< \brief (SCIF) Interrupt Clear Register */ \r
+#define REG_SCIF_PCLKSR REG_ACCESS(RoReg , 0x400E0814U) /**< \brief (SCIF) Power and Clocks Status Register */ \r
+#define REG_SCIF_UNLOCK REG_ACCESS(WoReg , 0x400E0818U) /**< \brief (SCIF) Unlock Register */ \r
+#define REG_SCIF_CSCR REG_ACCESS(RwReg , 0x400E081CU) /**< \brief (SCIF) Chip Specific Configuration Register */ \r
+#define REG_SCIF_OSCCTRL0 REG_ACCESS(RwReg , 0x400E0820U) /**< \brief (SCIF) Oscillator Control Register */ \r
+#define REG_SCIF_PLL0 REG_ACCESS(RwReg , 0x400E0824U) /**< \brief (SCIF) PLL0 Control Register 0 */\r
+#define REG_SCIF_DFLL0CONF REG_ACCESS(RwReg , 0x400E0828U) /**< \brief (SCIF) DFLL0 Config Register */ \r
+#define REG_SCIF_DFLL0VAL REG_ACCESS(RwReg , 0x400E082CU) /**< \brief (SCIF) DFLL Value Register */ \r
+#define REG_SCIF_DFLL0MUL REG_ACCESS(RwReg , 0x400E0830U) /**< \brief (SCIF) DFLL0 Multiplier Register */ \r
+#define REG_SCIF_DFLL0STEP REG_ACCESS(RwReg , 0x400E0834U) /**< \brief (SCIF) DFLL0 Step Register */ \r
+#define REG_SCIF_DFLL0SSG REG_ACCESS(RwReg , 0x400E0838U) /**< \brief (SCIF) DFLL0 Spread Spectrum Generator Control Register */ \r
+#define REG_SCIF_DFLL0RATIO REG_ACCESS(RoReg , 0x400E083CU) /**< \brief (SCIF) DFLL0 Ratio Registe */ \r
+#define REG_SCIF_DFLL0SYNC REG_ACCESS(WoReg , 0x400E0840U) /**< \brief (SCIF) DFLL0 Synchronization Register */ \r
+#define REG_SCIF_RCCR REG_ACCESS(RwReg , 0x400E0844U) /**< \brief (SCIF) System RC Oscillator Calibration Register */ \r
+#define REG_SCIF_RCFASTCFG REG_ACCESS(RwReg , 0x400E0848U) /**< \brief (SCIF) 4/8/12 MHz RC Oscillator Configuration\r
+Register */ \r
+#define REG_SCIF_RCFASTSR REG_ACCESS(RwReg , 0x400E084CU) /**< \brief (SCIF) 4/8/12 MHz RC Oscillator Status Register */ \r
+#define REG_SCIF_RC80MCR REG_ACCESS(RwReg , 0x400E0850U) /**< \brief (SCIF) 80 MHz RC Oscillator Register */ \r
+#define REG_SCIF_HRPCR REG_ACCESS(RwReg , 0x400E0864U) /**< \brief (SCIF) High Resolution Prescaler Control Register */ \r
+#define REG_SCIF_FPCR REG_ACCESS(RwReg , 0x400E0868U) /**< \brief (SCIF) Fractional Prescaler Control Register */ \r
+#define REG_SCIF_FPMUL REG_ACCESS(RwReg , 0x400E086CU) /**< \brief (SCIF) Fractional Prescaler Multiplier Register */ \r
+#define REG_SCIF_FPDIV REG_ACCESS(RwReg , 0x400E0870U) /**< \brief (SCIF) Fractional Prescaler DIVIDER Register */ \r
+#define REG_SCIF_GCCTRL0 REG_ACCESS(RwReg , 0x400E0874U) /**< \brief (SCIF) Generic Clock Control 0 */\r
+#define REG_SCIF_GCCTRL1 REG_ACCESS(RwReg , 0x400E0878U) /**< \brief (SCIF) Generic Clock Control 1 */\r
+#define REG_SCIF_GCCTRL2 REG_ACCESS(RwReg , 0x400E087CU) /**< \brief (SCIF) Generic Clock Control 2 */\r
+#define REG_SCIF_GCCTRL3 REG_ACCESS(RwReg , 0x400E0880U) /**< \brief (SCIF) Generic Clock Control 3 */\r
+#define REG_SCIF_GCCTRL4 REG_ACCESS(RwReg , 0x400E0884U) /**< \brief (SCIF) Generic Clock Control 4 */\r
+#define REG_SCIF_GCCTRL5 REG_ACCESS(RwReg , 0x400E0888U) /**< \brief (SCIF) Generic Clock Control 5 */\r
+#define REG_SCIF_GCCTRL6 REG_ACCESS(RwReg , 0x400E088CU) /**< \brief (SCIF) Generic Clock Control 6 */\r
+#define REG_SCIF_GCCTRL7 REG_ACCESS(RwReg , 0x400E0890U) /**< \brief (SCIF) Generic Clock Control 7 */\r
+#define REG_SCIF_GCCTRL8 REG_ACCESS(RwReg , 0x400E0894U) /**< \brief (SCIF) Generic Clock Control 8 */\r
+#define REG_SCIF_GCCTRL9 REG_ACCESS(RwReg , 0x400E0898U) /**< \brief (SCIF) Generic Clock Control 9 */\r
+#define REG_SCIF_GCCTRL10 REG_ACCESS(RwReg , 0x400E089CU) /**< \brief (SCIF) Generic Clock Control 10 */\r
+#define REG_SCIF_GCCTRL11 REG_ACCESS(RwReg , 0x400E08A0U) /**< \brief (SCIF) Generic Clock Control 11 */\r
+#define REG_SCIF_RCFASTVERSION REG_ACCESS(RoReg , 0x400E0BD8U) /**< \brief (SCIF) 4/8/12 MHz RC Oscillator Version Register */ \r
+#define REG_SCIF_GCLKPRESCVERSION REG_ACCESS(RoReg , 0x400E0BDCU) /**< \brief (SCIF) Generic Clock Prescaler Version Register */ \r
+#define REG_SCIF_PLLIFAVERSION REG_ACCESS(RoReg , 0x400E0BE0U) /**< \brief (SCIF) PLL Version Register */ \r
+#define REG_SCIF_OSCIFAVERSION REG_ACCESS(RoReg , 0x400E0BE4U) /**< \brief (SCIF) Oscillator 0 Version Register */ \r
+#define REG_SCIF_DFLLIFBVERSION REG_ACCESS(RoReg , 0x400E0BE8U) /**< \brief (SCIF) DFLL Version Register */ \r
+#define REG_SCIF_RCOSCIFAVERSION REG_ACCESS(RoReg , 0x400E0BECU) /**< \brief (SCIF) System RC Oscillator Version Register */ \r
+#define REG_SCIF_FLOVERSION REG_ACCESS(RoReg , 0x400E0BF0U) /**< \brief (SCIF) Frequency Locked Oscillator Version Register */ \r
+#define REG_SCIF_RC80MVERSION REG_ACCESS(RoReg , 0x400E0BF4U) /**< \brief (SCIF) 80MHz RC Oscillator Version Register */ \r
+#define REG_SCIF_GCLKIFVERSION REG_ACCESS(RoReg , 0x400E0BF8U) /**< \brief (SCIF) Generic Clock Version Register */ \r
+#define REG_SCIF_VERSION REG_ACCESS(RoReg , 0x400E0BFCU) /**< \brief (SCIF) SCIF Version Register */ \r
+/* ========== Register definition for FREQM peripheral ========== */\r
+#define REG_FREQM_CTRL REG_ACCESS(WoReg , 0x400E0C00U) /**< \brief (FREQM) Control register */ \r
+#define REG_FREQM_MODE REG_ACCESS(RwReg , 0x400E0C04U) /**< \brief (FREQM) Mode register */ \r
+#define REG_FREQM_STATUS REG_ACCESS(RoReg , 0x400E0C08U) /**< \brief (FREQM) Status register */ \r
+#define REG_FREQM_VALUE REG_ACCESS(RoReg , 0x400E0C0CU) /**< \brief (FREQM) Value register */ \r
+#define REG_FREQM_IER REG_ACCESS(WoReg , 0x400E0C10U) /**< \brief (FREQM) Interrupt Enable Register */ \r
+#define REG_FREQM_IDR REG_ACCESS(WoReg , 0x400E0C14U) /**< \brief (FREQM) Interrupt Diable Register */ \r
+#define REG_FREQM_IMR REG_ACCESS(RoReg , 0x400E0C18U) /**< \brief (FREQM) Interrupt Mask Register */ \r
+#define REG_FREQM_ISR REG_ACCESS(RoReg , 0x400E0C1CU) /**< \brief (FREQM) Interrupt Status Register */ \r
+#define REG_FREQM_ICR REG_ACCESS(WoReg , 0x400E0C20U) /**< \brief (FREQM) Interrupt Clear Register */ \r
+#define REG_FREQM_VERSION REG_ACCESS(RoReg , 0x400E0FFCU) /**< \brief (FREQM) Version Register */ \r
+/* ========== Register definition for GPIO peripheral ========== */\r
+#define REG_GPIO_GPER0 REG_ACCESS(RwReg , 0x400E1000U) /**< \brief (GPIO) GPIO Enable Register 0 */\r
+#define REG_GPIO_GPERS0 REG_ACCESS(WoReg , 0x400E1004U) /**< \brief (GPIO) GPIO Enable Register - Set 0 */\r
+#define REG_GPIO_GPERC0 REG_ACCESS(WoReg , 0x400E1008U) /**< \brief (GPIO) GPIO Enable Register - Clear 0 */\r
+#define REG_GPIO_GPERT0 REG_ACCESS(WoReg , 0x400E100CU) /**< \brief (GPIO) GPIO Enable Register - Toggle 0 */\r
+#define REG_GPIO_PMR00 REG_ACCESS(RwReg , 0x400E1010U) /**< \brief (GPIO) Peripheral Mux Register 0 0 */\r
+#define REG_GPIO_PMR0S0 REG_ACCESS(WoReg , 0x400E1014U) /**< \brief (GPIO) Peripheral Mux Register 0 - Set 0 */\r
+#define REG_GPIO_PMR0C0 REG_ACCESS(WoReg , 0x400E1018U) /**< \brief (GPIO) Peripheral Mux Register 0 - Clear 0 */\r
+#define REG_GPIO_PMR0T0 REG_ACCESS(WoReg , 0x400E101CU) /**< \brief (GPIO) Peripheral Mux Register 0 - Toggle 0 */\r
+#define REG_GPIO_PMR10 REG_ACCESS(RwReg , 0x400E1020U) /**< \brief (GPIO) Peripheral Mux Register 1 0 */\r
+#define REG_GPIO_PMR1S0 REG_ACCESS(WoReg , 0x400E1024U) /**< \brief (GPIO) Peripheral Mux Register 1 - Set 0 */\r
+#define REG_GPIO_PMR1C0 REG_ACCESS(WoReg , 0x400E1028U) /**< \brief (GPIO) Peripheral Mux Register 1 - Clear 0 */\r
+#define REG_GPIO_PMR1T0 REG_ACCESS(WoReg , 0x400E102CU) /**< \brief (GPIO) Peripheral Mux Register 1 - Toggle 0 */\r
+#define REG_GPIO_PMR20 REG_ACCESS(RwReg , 0x400E1030U) /**< \brief (GPIO) Peripheral Mux Register 2 0 */\r
+#define REG_GPIO_PMR2S0 REG_ACCESS(WoReg , 0x400E1034U) /**< \brief (GPIO) Peripheral Mux Register 2 - Set 0 */\r
+#define REG_GPIO_PMR2C0 REG_ACCESS(WoReg , 0x400E1038U) /**< \brief (GPIO) Peripheral Mux Register 2 - Clear 0 */\r
+#define REG_GPIO_PMR2T0 REG_ACCESS(WoReg , 0x400E103CU) /**< \brief (GPIO) Peripheral Mux Register 2 - Toggle 0 */\r
+#define REG_GPIO_ODER0 REG_ACCESS(RwReg , 0x400E1040U) /**< \brief (GPIO) Output Driver Enable Register 0 */\r
+#define REG_GPIO_ODERS0 REG_ACCESS(WoReg , 0x400E1044U) /**< \brief (GPIO) Output Driver Enable Register - Set 0 */\r
+#define REG_GPIO_ODERC0 REG_ACCESS(WoReg , 0x400E1048U) /**< \brief (GPIO) Output Driver Enable Register - Clear 0 */\r
+#define REG_GPIO_ODERT0 REG_ACCESS(WoReg , 0x400E104CU) /**< \brief (GPIO) Output Driver Enable Register - Toggle 0 */\r
+#define REG_GPIO_OVR0 REG_ACCESS(RwReg , 0x400E1050U) /**< \brief (GPIO) Output Value Register 0 */\r
+#define REG_GPIO_OVRS0 REG_ACCESS(WoReg , 0x400E1054U) /**< \brief (GPIO) Output Value Register - Set 0 */\r
+#define REG_GPIO_OVRC0 REG_ACCESS(WoReg , 0x400E1058U) /**< \brief (GPIO) Output Value Register - Clear 0 */\r
+#define REG_GPIO_OVRT0 REG_ACCESS(WoReg , 0x400E105CU) /**< \brief (GPIO) Output Value Register - Toggle 0 */\r
+#define REG_GPIO_PVR0 REG_ACCESS(RoReg , 0x400E1060U) /**< \brief (GPIO) Pin Value Register 0 */\r
+#define REG_GPIO_PUER0 REG_ACCESS(RwReg , 0x400E1070U) /**< \brief (GPIO) Pull-up Enable Register 0 */\r
+#define REG_GPIO_PUERS0 REG_ACCESS(WoReg , 0x400E1074U) /**< \brief (GPIO) Pull-up Enable Register - Set 0 */\r
+#define REG_GPIO_PUERC0 REG_ACCESS(WoReg , 0x400E1078U) /**< \brief (GPIO) Pull-up Enable Register - Clear 0 */\r
+#define REG_GPIO_PUERT0 REG_ACCESS(WoReg , 0x400E107CU) /**< \brief (GPIO) Pull-up Enable Register - Toggle 0 */\r
+#define REG_GPIO_PDER0 REG_ACCESS(RwReg , 0x400E1080U) /**< \brief (GPIO) Pull-down Enable Register 0 */\r
+#define REG_GPIO_PDERS0 REG_ACCESS(WoReg , 0x400E1084U) /**< \brief (GPIO) Pull-down Enable Register - Set 0 */\r
+#define REG_GPIO_PDERC0 REG_ACCESS(WoReg , 0x400E1088U) /**< \brief (GPIO) Pull-down Enable Register - Clear 0 */\r
+#define REG_GPIO_PDERT0 REG_ACCESS(WoReg , 0x400E108CU) /**< \brief (GPIO) Pull-down Enable Register - Toggle 0 */\r
+#define REG_GPIO_IER0 REG_ACCESS(RwReg , 0x400E1090U) /**< \brief (GPIO) Interrupt Enable Register 0 */\r
+#define REG_GPIO_IERS0 REG_ACCESS(WoReg , 0x400E1094U) /**< \brief (GPIO) Interrupt Enable Register - Set 0 */\r
+#define REG_GPIO_IERC0 REG_ACCESS(WoReg , 0x400E1098U) /**< \brief (GPIO) Interrupt Enable Register - Clear 0 */\r
+#define REG_GPIO_IERT0 REG_ACCESS(WoReg , 0x400E109CU) /**< \brief (GPIO) Interrupt Enable Register - Toggle 0 */\r
+#define REG_GPIO_IMR00 REG_ACCESS(RwReg , 0x400E10A0U) /**< \brief (GPIO) Interrupt Mode Register 0 0 */\r
+#define REG_GPIO_IMR0S0 REG_ACCESS(WoReg , 0x400E10A4U) /**< \brief (GPIO) Interrupt Mode Register 0 - Set 0 */\r
+#define REG_GPIO_IMR0C0 REG_ACCESS(WoReg , 0x400E10A8U) /**< \brief (GPIO) Interrupt Mode Register 0 - Clear 0 */\r
+#define REG_GPIO_IMR0T0 REG_ACCESS(WoReg , 0x400E10ACU) /**< \brief (GPIO) Interrupt Mode Register 0 - Toggle 0 */\r
+#define REG_GPIO_IMR10 REG_ACCESS(RwReg , 0x400E10B0U) /**< \brief (GPIO) Interrupt Mode Register 1 0 */\r
+#define REG_GPIO_IMR1S0 REG_ACCESS(WoReg , 0x400E10B4U) /**< \brief (GPIO) Interrupt Mode Register 1 - Set 0 */\r
+#define REG_GPIO_IMR1C0 REG_ACCESS(WoReg , 0x400E10B8U) /**< \brief (GPIO) Interrupt Mode Register 1 - Clear 0 */\r
+#define REG_GPIO_IMR1T0 REG_ACCESS(WoReg , 0x400E10BCU) /**< \brief (GPIO) Interrupt Mode Register 1 - Toggle 0 */\r
+#define REG_GPIO_GFER0 REG_ACCESS(RwReg , 0x400E10C0U) /**< \brief (GPIO) Glitch Filter Enable Register 0 */\r
+#define REG_GPIO_GFERS0 REG_ACCESS(WoReg , 0x400E10C4U) /**< \brief (GPIO) Glitch Filter Enable Register - Set 0 */\r
+#define REG_GPIO_GFERC0 REG_ACCESS(WoReg , 0x400E10C8U) /**< \brief (GPIO) Glitch Filter Enable Register - Clear 0 */\r
+#define REG_GPIO_GFERT0 REG_ACCESS(WoReg , 0x400E10CCU) /**< \brief (GPIO) Glitch Filter Enable Register - Toggle 0 */\r
+#define REG_GPIO_IFR0 REG_ACCESS(RoReg , 0x400E10D0U) /**< \brief (GPIO) Interrupt Flag Register 0 */\r
+#define REG_GPIO_IFRC0 REG_ACCESS(WoReg , 0x400E10D8U) /**< \brief (GPIO) Interrupt Flag Register - Clear 0 */\r
+#define REG_GPIO_ODMER0 REG_ACCESS(RwReg , 0x400E10E0U) /**< \brief (GPIO) Open Drain Mode Register 0 */\r
+#define REG_GPIO_ODMERS0 REG_ACCESS(WoReg , 0x400E10E4U) /**< \brief (GPIO) Open Drain Mode Register - Set 0 */\r
+#define REG_GPIO_ODMERC0 REG_ACCESS(WoReg , 0x400E10E8U) /**< \brief (GPIO) Open Drain Mode Register - Clear 0 */\r
+#define REG_GPIO_ODMERT0 REG_ACCESS(WoReg , 0x400E10ECU) /**< \brief (GPIO) Open Drain Mode Register - Toggle 0 */\r
+#define REG_GPIO_ODCR00 REG_ACCESS(RwReg , 0x400E1100U) /**< \brief (GPIO) Output Driving Capability Register 0 0 */\r
+#define REG_GPIO_ODCR0S0 REG_ACCESS(RwReg , 0x400E1104U) /**< \brief (GPIO) Output Driving Capability Register 0 - Set 0 */\r
+#define REG_GPIO_ODCR0C0 REG_ACCESS(RwReg , 0x400E1108U) /**< \brief (GPIO) Output Driving Capability Register 0 - Clear 0 */\r
+#define REG_GPIO_ODCR0T0 REG_ACCESS(RwReg , 0x400E110CU) /**< \brief (GPIO) Output Driving Capability Register 0 - Toggle 0 */\r
+#define REG_GPIO_ODCR10 REG_ACCESS(RwReg , 0x400E1110U) /**< \brief (GPIO) Output Driving Capability Register 1 0 */\r
+#define REG_GPIO_ODCR1S0 REG_ACCESS(RwReg , 0x400E1114U) /**< \brief (GPIO) Output Driving Capability Register 1 - Set 0 */\r
+#define REG_GPIO_ODCR1C0 REG_ACCESS(RwReg , 0x400E1118U) /**< \brief (GPIO) Output Driving Capability Register 1 - Clear 0 */\r
+#define REG_GPIO_ODCR1T0 REG_ACCESS(RwReg , 0x400E111CU) /**< \brief (GPIO) Output Driving Capability Register 1 - Toggle 0 */\r
+#define REG_GPIO_OSRR00 REG_ACCESS(RwReg , 0x400E1130U) /**< \brief (GPIO) Output Slew Rate Register 0 0 */\r
+#define REG_GPIO_OSRR0S0 REG_ACCESS(RwReg , 0x400E1134U) /**< \brief (GPIO) Output Slew Rate Register 0 - Set 0 */\r
+#define REG_GPIO_OSRR0C0 REG_ACCESS(RwReg , 0x400E1138U) /**< \brief (GPIO) Output Slew Rate Register 0 - Clear 0 */\r
+#define REG_GPIO_OSRR0T0 REG_ACCESS(RwReg , 0x400E113CU) /**< \brief (GPIO) Output Slew Rate Register 0 - Toggle 0 */\r
+#define REG_GPIO_STER0 REG_ACCESS(RwReg , 0x400E1160U) /**< \brief (GPIO) Schmitt Trigger Enable Register 0 */\r
+#define REG_GPIO_STERS0 REG_ACCESS(RwReg , 0x400E1164U) /**< \brief (GPIO) Schmitt Trigger Enable Register - Set 0 */\r
+#define REG_GPIO_STERC0 REG_ACCESS(RwReg , 0x400E1168U) /**< \brief (GPIO) Schmitt Trigger Enable Register - Clear 0 */\r
+#define REG_GPIO_STERT0 REG_ACCESS(RwReg , 0x400E116CU) /**< \brief (GPIO) Schmitt Trigger Enable Register - Toggle 0 */\r
+#define REG_GPIO_EVER0 REG_ACCESS(RwReg , 0x400E1180U) /**< \brief (GPIO) Event Enable Register 0 */\r
+#define REG_GPIO_EVERS0 REG_ACCESS(WoReg , 0x400E1184U) /**< \brief (GPIO) Event Enable Register - Set 0 */\r
+#define REG_GPIO_EVERC0 REG_ACCESS(WoReg , 0x400E1188U) /**< \brief (GPIO) Event Enable Register - Clear 0 */\r
+#define REG_GPIO_EVERT0 REG_ACCESS(WoReg , 0x400E118CU) /**< \brief (GPIO) Event Enable Register - Toggle 0 */\r
+#define REG_GPIO_LOCK0 REG_ACCESS(RwReg , 0x400E11A0U) /**< \brief (GPIO) Lock Register 0 */\r
+#define REG_GPIO_LOCKS0 REG_ACCESS(WoReg , 0x400E11A4U) /**< \brief (GPIO) Lock Register - Set 0 */\r
+#define REG_GPIO_LOCKC0 REG_ACCESS(WoReg , 0x400E11A8U) /**< \brief (GPIO) Lock Register - Clear 0 */\r
+#define REG_GPIO_LOCKT0 REG_ACCESS(WoReg , 0x400E11ACU) /**< \brief (GPIO) Lock Register - Toggle 0 */\r
+#define REG_GPIO_UNLOCK0 REG_ACCESS(WoReg , 0x400E11E0U) /**< \brief (GPIO) Unlock Register 0 */\r
+#define REG_GPIO_ASR0 REG_ACCESS(RwReg , 0x400E11E4U) /**< \brief (GPIO) Access Status Register 0 */\r
+#define REG_GPIO_PARAMETER0 REG_ACCESS(RoReg , 0x400E11F8U) /**< \brief (GPIO) Parameter Register 0 */\r
+#define REG_GPIO_VERSION0 REG_ACCESS(RoReg , 0x400E11FCU) /**< \brief (GPIO) Version Register 0 */\r
+#define REG_GPIO_GPER1 REG_ACCESS(RwReg , 0x400E1200U) /**< \brief (GPIO) GPIO Enable Register 1 */\r
+#define REG_GPIO_GPERS1 REG_ACCESS(WoReg , 0x400E1204U) /**< \brief (GPIO) GPIO Enable Register - Set 1 */\r
+#define REG_GPIO_GPERC1 REG_ACCESS(WoReg , 0x400E1208U) /**< \brief (GPIO) GPIO Enable Register - Clear 1 */\r
+#define REG_GPIO_GPERT1 REG_ACCESS(WoReg , 0x400E120CU) /**< \brief (GPIO) GPIO Enable Register - Toggle 1 */\r
+#define REG_GPIO_PMR01 REG_ACCESS(RwReg , 0x400E1210U) /**< \brief (GPIO) Peripheral Mux Register 0 1 */\r
+#define REG_GPIO_PMR0S1 REG_ACCESS(WoReg , 0x400E1214U) /**< \brief (GPIO) Peripheral Mux Register 0 - Set 1 */\r
+#define REG_GPIO_PMR0C1 REG_ACCESS(WoReg , 0x400E1218U) /**< \brief (GPIO) Peripheral Mux Register 0 - Clear 1 */\r
+#define REG_GPIO_PMR0T1 REG_ACCESS(WoReg , 0x400E121CU) /**< \brief (GPIO) Peripheral Mux Register 0 - Toggle 1 */\r
+#define REG_GPIO_PMR11 REG_ACCESS(RwReg , 0x400E1220U) /**< \brief (GPIO) Peripheral Mux Register 1 1 */\r
+#define REG_GPIO_PMR1S1 REG_ACCESS(WoReg , 0x400E1224U) /**< \brief (GPIO) Peripheral Mux Register 1 - Set 1 */\r
+#define REG_GPIO_PMR1C1 REG_ACCESS(WoReg , 0x400E1228U) /**< \brief (GPIO) Peripheral Mux Register 1 - Clear 1 */\r
+#define REG_GPIO_PMR1T1 REG_ACCESS(WoReg , 0x400E122CU) /**< \brief (GPIO) Peripheral Mux Register 1 - Toggle 1 */\r
+#define REG_GPIO_PMR21 REG_ACCESS(RwReg , 0x400E1230U) /**< \brief (GPIO) Peripheral Mux Register 2 1 */\r
+#define REG_GPIO_PMR2S1 REG_ACCESS(WoReg , 0x400E1234U) /**< \brief (GPIO) Peripheral Mux Register 2 - Set 1 */\r
+#define REG_GPIO_PMR2C1 REG_ACCESS(WoReg , 0x400E1238U) /**< \brief (GPIO) Peripheral Mux Register 2 - Clear 1 */\r
+#define REG_GPIO_PMR2T1 REG_ACCESS(WoReg , 0x400E123CU) /**< \brief (GPIO) Peripheral Mux Register 2 - Toggle 1 */\r
+#define REG_GPIO_ODER1 REG_ACCESS(RwReg , 0x400E1240U) /**< \brief (GPIO) Output Driver Enable Register 1 */\r
+#define REG_GPIO_ODERS1 REG_ACCESS(WoReg , 0x400E1244U) /**< \brief (GPIO) Output Driver Enable Register - Set 1 */\r
+#define REG_GPIO_ODERC1 REG_ACCESS(WoReg , 0x400E1248U) /**< \brief (GPIO) Output Driver Enable Register - Clear 1 */\r
+#define REG_GPIO_ODERT1 REG_ACCESS(WoReg , 0x400E124CU) /**< \brief (GPIO) Output Driver Enable Register - Toggle 1 */\r
+#define REG_GPIO_OVR1 REG_ACCESS(RwReg , 0x400E1250U) /**< \brief (GPIO) Output Value Register 1 */\r
+#define REG_GPIO_OVRS1 REG_ACCESS(WoReg , 0x400E1254U) /**< \brief (GPIO) Output Value Register - Set 1 */\r
+#define REG_GPIO_OVRC1 REG_ACCESS(WoReg , 0x400E1258U) /**< \brief (GPIO) Output Value Register - Clear 1 */\r
+#define REG_GPIO_OVRT1 REG_ACCESS(WoReg , 0x400E125CU) /**< \brief (GPIO) Output Value Register - Toggle 1 */\r
+#define REG_GPIO_PVR1 REG_ACCESS(RoReg , 0x400E1260U) /**< \brief (GPIO) Pin Value Register 1 */\r
+#define REG_GPIO_PUER1 REG_ACCESS(RwReg , 0x400E1270U) /**< \brief (GPIO) Pull-up Enable Register 1 */\r
+#define REG_GPIO_PUERS1 REG_ACCESS(WoReg , 0x400E1274U) /**< \brief (GPIO) Pull-up Enable Register - Set 1 */\r
+#define REG_GPIO_PUERC1 REG_ACCESS(WoReg , 0x400E1278U) /**< \brief (GPIO) Pull-up Enable Register - Clear 1 */\r
+#define REG_GPIO_PUERT1 REG_ACCESS(WoReg , 0x400E127CU) /**< \brief (GPIO) Pull-up Enable Register - Toggle 1 */\r
+#define REG_GPIO_PDER1 REG_ACCESS(RwReg , 0x400E1280U) /**< \brief (GPIO) Pull-down Enable Register 1 */\r
+#define REG_GPIO_PDERS1 REG_ACCESS(WoReg , 0x400E1284U) /**< \brief (GPIO) Pull-down Enable Register - Set 1 */\r
+#define REG_GPIO_PDERC1 REG_ACCESS(WoReg , 0x400E1288U) /**< \brief (GPIO) Pull-down Enable Register - Clear 1 */\r
+#define REG_GPIO_PDERT1 REG_ACCESS(WoReg , 0x400E128CU) /**< \brief (GPIO) Pull-down Enable Register - Toggle 1 */\r
+#define REG_GPIO_IER1 REG_ACCESS(RwReg , 0x400E1290U) /**< \brief (GPIO) Interrupt Enable Register 1 */\r
+#define REG_GPIO_IERS1 REG_ACCESS(WoReg , 0x400E1294U) /**< \brief (GPIO) Interrupt Enable Register - Set 1 */\r
+#define REG_GPIO_IERC1 REG_ACCESS(WoReg , 0x400E1298U) /**< \brief (GPIO) Interrupt Enable Register - Clear 1 */\r
+#define REG_GPIO_IERT1 REG_ACCESS(WoReg , 0x400E129CU) /**< \brief (GPIO) Interrupt Enable Register - Toggle 1 */\r
+#define REG_GPIO_IMR01 REG_ACCESS(RwReg , 0x400E12A0U) /**< \brief (GPIO) Interrupt Mode Register 0 1 */\r
+#define REG_GPIO_IMR0S1 REG_ACCESS(WoReg , 0x400E12A4U) /**< \brief (GPIO) Interrupt Mode Register 0 - Set 1 */\r
+#define REG_GPIO_IMR0C1 REG_ACCESS(WoReg , 0x400E12A8U) /**< \brief (GPIO) Interrupt Mode Register 0 - Clear 1 */\r
+#define REG_GPIO_IMR0T1 REG_ACCESS(WoReg , 0x400E12ACU) /**< \brief (GPIO) Interrupt Mode Register 0 - Toggle 1 */\r
+#define REG_GPIO_IMR11 REG_ACCESS(RwReg , 0x400E12B0U) /**< \brief (GPIO) Interrupt Mode Register 1 1 */\r
+#define REG_GPIO_IMR1S1 REG_ACCESS(WoReg , 0x400E12B4U) /**< \brief (GPIO) Interrupt Mode Register 1 - Set 1 */\r
+#define REG_GPIO_IMR1C1 REG_ACCESS(WoReg , 0x400E12B8U) /**< \brief (GPIO) Interrupt Mode Register 1 - Clear 1 */\r
+#define REG_GPIO_IMR1T1 REG_ACCESS(WoReg , 0x400E12BCU) /**< \brief (GPIO) Interrupt Mode Register 1 - Toggle 1 */\r
+#define REG_GPIO_GFER1 REG_ACCESS(RwReg , 0x400E12C0U) /**< \brief (GPIO) Glitch Filter Enable Register 1 */\r
+#define REG_GPIO_GFERS1 REG_ACCESS(WoReg , 0x400E12C4U) /**< \brief (GPIO) Glitch Filter Enable Register - Set 1 */\r
+#define REG_GPIO_GFERC1 REG_ACCESS(WoReg , 0x400E12C8U) /**< \brief (GPIO) Glitch Filter Enable Register - Clear 1 */\r
+#define REG_GPIO_GFERT1 REG_ACCESS(WoReg , 0x400E12CCU) /**< \brief (GPIO) Glitch Filter Enable Register - Toggle 1 */\r
+#define REG_GPIO_IFR1 REG_ACCESS(RoReg , 0x400E12D0U) /**< \brief (GPIO) Interrupt Flag Register 1 */\r
+#define REG_GPIO_IFRC1 REG_ACCESS(WoReg , 0x400E12D8U) /**< \brief (GPIO) Interrupt Flag Register - Clear 1 */\r
+#define REG_GPIO_ODMER1 REG_ACCESS(RwReg , 0x400E12E0U) /**< \brief (GPIO) Open Drain Mode Register 1 */\r
+#define REG_GPIO_ODMERS1 REG_ACCESS(WoReg , 0x400E12E4U) /**< \brief (GPIO) Open Drain Mode Register - Set 1 */\r
+#define REG_GPIO_ODMERC1 REG_ACCESS(WoReg , 0x400E12E8U) /**< \brief (GPIO) Open Drain Mode Register - Clear 1 */\r
+#define REG_GPIO_ODMERT1 REG_ACCESS(WoReg , 0x400E12ECU) /**< \brief (GPIO) Open Drain Mode Register - Toggle 1 */\r
+#define REG_GPIO_ODCR01 REG_ACCESS(RwReg , 0x400E1300U) /**< \brief (GPIO) Output Driving Capability Register 0 1 */\r
+#define REG_GPIO_ODCR0S1 REG_ACCESS(RwReg , 0x400E1304U) /**< \brief (GPIO) Output Driving Capability Register 0 - Set 1 */\r
+#define REG_GPIO_ODCR0C1 REG_ACCESS(RwReg , 0x400E1308U) /**< \brief (GPIO) Output Driving Capability Register 0 - Clear 1 */\r
+#define REG_GPIO_ODCR0T1 REG_ACCESS(RwReg , 0x400E130CU) /**< \brief (GPIO) Output Driving Capability Register 0 - Toggle 1 */\r
+#define REG_GPIO_ODCR11 REG_ACCESS(RwReg , 0x400E1310U) /**< \brief (GPIO) Output Driving Capability Register 1 1 */\r
+#define REG_GPIO_ODCR1S1 REG_ACCESS(RwReg , 0x400E1314U) /**< \brief (GPIO) Output Driving Capability Register 1 - Set 1 */\r
+#define REG_GPIO_ODCR1C1 REG_ACCESS(RwReg , 0x400E1318U) /**< \brief (GPIO) Output Driving Capability Register 1 - Clear 1 */\r
+#define REG_GPIO_ODCR1T1 REG_ACCESS(RwReg , 0x400E131CU) /**< \brief (GPIO) Output Driving Capability Register 1 - Toggle 1 */\r
+#define REG_GPIO_OSRR01 REG_ACCESS(RwReg , 0x400E1330U) /**< \brief (GPIO) Output Slew Rate Register 0 1 */\r
+#define REG_GPIO_OSRR0S1 REG_ACCESS(RwReg , 0x400E1334U) /**< \brief (GPIO) Output Slew Rate Register 0 - Set 1 */\r
+#define REG_GPIO_OSRR0C1 REG_ACCESS(RwReg , 0x400E1338U) /**< \brief (GPIO) Output Slew Rate Register 0 - Clear 1 */\r
+#define REG_GPIO_OSRR0T1 REG_ACCESS(RwReg , 0x400E133CU) /**< \brief (GPIO) Output Slew Rate Register 0 - Toggle 1 */\r
+#define REG_GPIO_STER1 REG_ACCESS(RwReg , 0x400E1360U) /**< \brief (GPIO) Schmitt Trigger Enable Register 1 */\r
+#define REG_GPIO_STERS1 REG_ACCESS(RwReg , 0x400E1364U) /**< \brief (GPIO) Schmitt Trigger Enable Register - Set 1 */\r
+#define REG_GPIO_STERC1 REG_ACCESS(RwReg , 0x400E1368U) /**< \brief (GPIO) Schmitt Trigger Enable Register - Clear 1 */\r
+#define REG_GPIO_STERT1 REG_ACCESS(RwReg , 0x400E136CU) /**< \brief (GPIO) Schmitt Trigger Enable Register - Toggle 1 */\r
+#define REG_GPIO_EVER1 REG_ACCESS(RwReg , 0x400E1380U) /**< \brief (GPIO) Event Enable Register 1 */\r
+#define REG_GPIO_EVERS1 REG_ACCESS(WoReg , 0x400E1384U) /**< \brief (GPIO) Event Enable Register - Set 1 */\r
+#define REG_GPIO_EVERC1 REG_ACCESS(WoReg , 0x400E1388U) /**< \brief (GPIO) Event Enable Register - Clear 1 */\r
+#define REG_GPIO_EVERT1 REG_ACCESS(WoReg , 0x400E138CU) /**< \brief (GPIO) Event Enable Register - Toggle 1 */\r
+#define REG_GPIO_LOCK1 REG_ACCESS(RwReg , 0x400E13A0U) /**< \brief (GPIO) Lock Register 1 */\r
+#define REG_GPIO_LOCKS1 REG_ACCESS(WoReg , 0x400E13A4U) /**< \brief (GPIO) Lock Register - Set 1 */\r
+#define REG_GPIO_LOCKC1 REG_ACCESS(WoReg , 0x400E13A8U) /**< \brief (GPIO) Lock Register - Clear 1 */\r
+#define REG_GPIO_LOCKT1 REG_ACCESS(WoReg , 0x400E13ACU) /**< \brief (GPIO) Lock Register - Toggle 1 */\r
+#define REG_GPIO_UNLOCK1 REG_ACCESS(WoReg , 0x400E13E0U) /**< \brief (GPIO) Unlock Register 1 */\r
+#define REG_GPIO_ASR1 REG_ACCESS(RwReg , 0x400E13E4U) /**< \brief (GPIO) Access Status Register 1 */\r
+#define REG_GPIO_PARAMETER1 REG_ACCESS(RoReg , 0x400E13F8U) /**< \brief (GPIO) Parameter Register 1 */\r
+#define REG_GPIO_VERSION1 REG_ACCESS(RoReg , 0x400E13FCU) /**< \brief (GPIO) Version Register 1 */\r
+#define REG_GPIO_GPER2 REG_ACCESS(RwReg , 0x400E1400U) /**< \brief (GPIO) GPIO Enable Register 2 */\r
+#define REG_GPIO_GPERS2 REG_ACCESS(WoReg , 0x400E1404U) /**< \brief (GPIO) GPIO Enable Register - Set 2 */\r
+#define REG_GPIO_GPERC2 REG_ACCESS(WoReg , 0x400E1408U) /**< \brief (GPIO) GPIO Enable Register - Clear 2 */\r
+#define REG_GPIO_GPERT2 REG_ACCESS(WoReg , 0x400E140CU) /**< \brief (GPIO) GPIO Enable Register - Toggle 2 */\r
+#define REG_GPIO_PMR02 REG_ACCESS(RwReg , 0x400E1410U) /**< \brief (GPIO) Peripheral Mux Register 0 2 */\r
+#define REG_GPIO_PMR0S2 REG_ACCESS(WoReg , 0x400E1414U) /**< \brief (GPIO) Peripheral Mux Register 0 - Set 2 */\r
+#define REG_GPIO_PMR0C2 REG_ACCESS(WoReg , 0x400E1418U) /**< \brief (GPIO) Peripheral Mux Register 0 - Clear 2 */\r
+#define REG_GPIO_PMR0T2 REG_ACCESS(WoReg , 0x400E141CU) /**< \brief (GPIO) Peripheral Mux Register 0 - Toggle 2 */\r
+#define REG_GPIO_PMR12 REG_ACCESS(RwReg , 0x400E1420U) /**< \brief (GPIO) Peripheral Mux Register 1 2 */\r
+#define REG_GPIO_PMR1S2 REG_ACCESS(WoReg , 0x400E1424U) /**< \brief (GPIO) Peripheral Mux Register 1 - Set 2 */\r
+#define REG_GPIO_PMR1C2 REG_ACCESS(WoReg , 0x400E1428U) /**< \brief (GPIO) Peripheral Mux Register 1 - Clear 2 */\r
+#define REG_GPIO_PMR1T2 REG_ACCESS(WoReg , 0x400E142CU) /**< \brief (GPIO) Peripheral Mux Register 1 - Toggle 2 */\r
+#define REG_GPIO_PMR22 REG_ACCESS(RwReg , 0x400E1430U) /**< \brief (GPIO) Peripheral Mux Register 2 2 */\r
+#define REG_GPIO_PMR2S2 REG_ACCESS(WoReg , 0x400E1434U) /**< \brief (GPIO) Peripheral Mux Register 2 - Set 2 */\r
+#define REG_GPIO_PMR2C2 REG_ACCESS(WoReg , 0x400E1438U) /**< \brief (GPIO) Peripheral Mux Register 2 - Clear 2 */\r
+#define REG_GPIO_PMR2T2 REG_ACCESS(WoReg , 0x400E143CU) /**< \brief (GPIO) Peripheral Mux Register 2 - Toggle 2 */\r
+#define REG_GPIO_ODER2 REG_ACCESS(RwReg , 0x400E1440U) /**< \brief (GPIO) Output Driver Enable Register 2 */\r
+#define REG_GPIO_ODERS2 REG_ACCESS(WoReg , 0x400E1444U) /**< \brief (GPIO) Output Driver Enable Register - Set 2 */\r
+#define REG_GPIO_ODERC2 REG_ACCESS(WoReg , 0x400E1448U) /**< \brief (GPIO) Output Driver Enable Register - Clear 2 */\r
+#define REG_GPIO_ODERT2 REG_ACCESS(WoReg , 0x400E144CU) /**< \brief (GPIO) Output Driver Enable Register - Toggle 2 */\r
+#define REG_GPIO_OVR2 REG_ACCESS(RwReg , 0x400E1450U) /**< \brief (GPIO) Output Value Register 2 */\r
+#define REG_GPIO_OVRS2 REG_ACCESS(WoReg , 0x400E1454U) /**< \brief (GPIO) Output Value Register - Set 2 */\r
+#define REG_GPIO_OVRC2 REG_ACCESS(WoReg , 0x400E1458U) /**< \brief (GPIO) Output Value Register - Clear 2 */\r
+#define REG_GPIO_OVRT2 REG_ACCESS(WoReg , 0x400E145CU) /**< \brief (GPIO) Output Value Register - Toggle 2 */\r
+#define REG_GPIO_PVR2 REG_ACCESS(RoReg , 0x400E1460U) /**< \brief (GPIO) Pin Value Register 2 */\r
+#define REG_GPIO_PUER2 REG_ACCESS(RwReg , 0x400E1470U) /**< \brief (GPIO) Pull-up Enable Register 2 */\r
+#define REG_GPIO_PUERS2 REG_ACCESS(WoReg , 0x400E1474U) /**< \brief (GPIO) Pull-up Enable Register - Set 2 */\r
+#define REG_GPIO_PUERC2 REG_ACCESS(WoReg , 0x400E1478U) /**< \brief (GPIO) Pull-up Enable Register - Clear 2 */\r
+#define REG_GPIO_PUERT2 REG_ACCESS(WoReg , 0x400E147CU) /**< \brief (GPIO) Pull-up Enable Register - Toggle 2 */\r
+#define REG_GPIO_PDER2 REG_ACCESS(RwReg , 0x400E1480U) /**< \brief (GPIO) Pull-down Enable Register 2 */\r
+#define REG_GPIO_PDERS2 REG_ACCESS(WoReg , 0x400E1484U) /**< \brief (GPIO) Pull-down Enable Register - Set 2 */\r
+#define REG_GPIO_PDERC2 REG_ACCESS(WoReg , 0x400E1488U) /**< \brief (GPIO) Pull-down Enable Register - Clear 2 */\r
+#define REG_GPIO_PDERT2 REG_ACCESS(WoReg , 0x400E148CU) /**< \brief (GPIO) Pull-down Enable Register - Toggle 2 */\r
+#define REG_GPIO_IER2 REG_ACCESS(RwReg , 0x400E1490U) /**< \brief (GPIO) Interrupt Enable Register 2 */\r
+#define REG_GPIO_IERS2 REG_ACCESS(WoReg , 0x400E1494U) /**< \brief (GPIO) Interrupt Enable Register - Set 2 */\r
+#define REG_GPIO_IERC2 REG_ACCESS(WoReg , 0x400E1498U) /**< \brief (GPIO) Interrupt Enable Register - Clear 2 */\r
+#define REG_GPIO_IERT2 REG_ACCESS(WoReg , 0x400E149CU) /**< \brief (GPIO) Interrupt Enable Register - Toggle 2 */\r
+#define REG_GPIO_IMR02 REG_ACCESS(RwReg , 0x400E14A0U) /**< \brief (GPIO) Interrupt Mode Register 0 2 */\r
+#define REG_GPIO_IMR0S2 REG_ACCESS(WoReg , 0x400E14A4U) /**< \brief (GPIO) Interrupt Mode Register 0 - Set 2 */\r
+#define REG_GPIO_IMR0C2 REG_ACCESS(WoReg , 0x400E14A8U) /**< \brief (GPIO) Interrupt Mode Register 0 - Clear 2 */\r
+#define REG_GPIO_IMR0T2 REG_ACCESS(WoReg , 0x400E14ACU) /**< \brief (GPIO) Interrupt Mode Register 0 - Toggle 2 */\r
+#define REG_GPIO_IMR12 REG_ACCESS(RwReg , 0x400E14B0U) /**< \brief (GPIO) Interrupt Mode Register 1 2 */\r
+#define REG_GPIO_IMR1S2 REG_ACCESS(WoReg , 0x400E14B4U) /**< \brief (GPIO) Interrupt Mode Register 1 - Set 2 */\r
+#define REG_GPIO_IMR1C2 REG_ACCESS(WoReg , 0x400E14B8U) /**< \brief (GPIO) Interrupt Mode Register 1 - Clear 2 */\r
+#define REG_GPIO_IMR1T2 REG_ACCESS(WoReg , 0x400E14BCU) /**< \brief (GPIO) Interrupt Mode Register 1 - Toggle 2 */\r
+#define REG_GPIO_GFER2 REG_ACCESS(RwReg , 0x400E14C0U) /**< \brief (GPIO) Glitch Filter Enable Register 2 */\r
+#define REG_GPIO_GFERS2 REG_ACCESS(WoReg , 0x400E14C4U) /**< \brief (GPIO) Glitch Filter Enable Register - Set 2 */\r
+#define REG_GPIO_GFERC2 REG_ACCESS(WoReg , 0x400E14C8U) /**< \brief (GPIO) Glitch Filter Enable Register - Clear 2 */\r
+#define REG_GPIO_GFERT2 REG_ACCESS(WoReg , 0x400E14CCU) /**< \brief (GPIO) Glitch Filter Enable Register - Toggle 2 */\r
+#define REG_GPIO_IFR2 REG_ACCESS(RoReg , 0x400E14D0U) /**< \brief (GPIO) Interrupt Flag Register 2 */\r
+#define REG_GPIO_IFRC2 REG_ACCESS(WoReg , 0x400E14D8U) /**< \brief (GPIO) Interrupt Flag Register - Clear 2 */\r
+#define REG_GPIO_ODMER2 REG_ACCESS(RwReg , 0x400E14E0U) /**< \brief (GPIO) Open Drain Mode Register 2 */\r
+#define REG_GPIO_ODMERS2 REG_ACCESS(WoReg , 0x400E14E4U) /**< \brief (GPIO) Open Drain Mode Register - Set 2 */\r
+#define REG_GPIO_ODMERC2 REG_ACCESS(WoReg , 0x400E14E8U) /**< \brief (GPIO) Open Drain Mode Register - Clear 2 */\r
+#define REG_GPIO_ODMERT2 REG_ACCESS(WoReg , 0x400E14ECU) /**< \brief (GPIO) Open Drain Mode Register - Toggle 2 */\r
+#define REG_GPIO_ODCR02 REG_ACCESS(RwReg , 0x400E1500U) /**< \brief (GPIO) Output Driving Capability Register 0 2 */\r
+#define REG_GPIO_ODCR0S2 REG_ACCESS(RwReg , 0x400E1504U) /**< \brief (GPIO) Output Driving Capability Register 0 - Set 2 */\r
+#define REG_GPIO_ODCR0C2 REG_ACCESS(RwReg , 0x400E1508U) /**< \brief (GPIO) Output Driving Capability Register 0 - Clear 2 */\r
+#define REG_GPIO_ODCR0T2 REG_ACCESS(RwReg , 0x400E150CU) /**< \brief (GPIO) Output Driving Capability Register 0 - Toggle 2 */\r
+#define REG_GPIO_ODCR12 REG_ACCESS(RwReg , 0x400E1510U) /**< \brief (GPIO) Output Driving Capability Register 1 2 */\r
+#define REG_GPIO_ODCR1S2 REG_ACCESS(RwReg , 0x400E1514U) /**< \brief (GPIO) Output Driving Capability Register 1 - Set 2 */\r
+#define REG_GPIO_ODCR1C2 REG_ACCESS(RwReg , 0x400E1518U) /**< \brief (GPIO) Output Driving Capability Register 1 - Clear 2 */\r
+#define REG_GPIO_ODCR1T2 REG_ACCESS(RwReg , 0x400E151CU) /**< \brief (GPIO) Output Driving Capability Register 1 - Toggle 2 */\r
+#define REG_GPIO_OSRR02 REG_ACCESS(RwReg , 0x400E1530U) /**< \brief (GPIO) Output Slew Rate Register 0 2 */\r
+#define REG_GPIO_OSRR0S2 REG_ACCESS(RwReg , 0x400E1534U) /**< \brief (GPIO) Output Slew Rate Register 0 - Set 2 */\r
+#define REG_GPIO_OSRR0C2 REG_ACCESS(RwReg , 0x400E1538U) /**< \brief (GPIO) Output Slew Rate Register 0 - Clear 2 */\r
+#define REG_GPIO_OSRR0T2 REG_ACCESS(RwReg , 0x400E153CU) /**< \brief (GPIO) Output Slew Rate Register 0 - Toggle 2 */\r
+#define REG_GPIO_STER2 REG_ACCESS(RwReg , 0x400E1560U) /**< \brief (GPIO) Schmitt Trigger Enable Register 2 */\r
+#define REG_GPIO_STERS2 REG_ACCESS(RwReg , 0x400E1564U) /**< \brief (GPIO) Schmitt Trigger Enable Register - Set 2 */\r
+#define REG_GPIO_STERC2 REG_ACCESS(RwReg , 0x400E1568U) /**< \brief (GPIO) Schmitt Trigger Enable Register - Clear 2 */\r
+#define REG_GPIO_STERT2 REG_ACCESS(RwReg , 0x400E156CU) /**< \brief (GPIO) Schmitt Trigger Enable Register - Toggle 2 */\r
+#define REG_GPIO_EVER2 REG_ACCESS(RwReg , 0x400E1580U) /**< \brief (GPIO) Event Enable Register 2 */\r
+#define REG_GPIO_EVERS2 REG_ACCESS(WoReg , 0x400E1584U) /**< \brief (GPIO) Event Enable Register - Set 2 */\r
+#define REG_GPIO_EVERC2 REG_ACCESS(WoReg , 0x400E1588U) /**< \brief (GPIO) Event Enable Register - Clear 2 */\r
+#define REG_GPIO_EVERT2 REG_ACCESS(WoReg , 0x400E158CU) /**< \brief (GPIO) Event Enable Register - Toggle 2 */\r
+#define REG_GPIO_LOCK2 REG_ACCESS(RwReg , 0x400E15A0U) /**< \brief (GPIO) Lock Register 2 */\r
+#define REG_GPIO_LOCKS2 REG_ACCESS(WoReg , 0x400E15A4U) /**< \brief (GPIO) Lock Register - Set 2 */\r
+#define REG_GPIO_LOCKC2 REG_ACCESS(WoReg , 0x400E15A8U) /**< \brief (GPIO) Lock Register - Clear 2 */\r
+#define REG_GPIO_LOCKT2 REG_ACCESS(WoReg , 0x400E15ACU) /**< \brief (GPIO) Lock Register - Toggle 2 */\r
+#define REG_GPIO_UNLOCK2 REG_ACCESS(WoReg , 0x400E15E0U) /**< \brief (GPIO) Unlock Register 2 */\r
+#define REG_GPIO_ASR2 REG_ACCESS(RwReg , 0x400E15E4U) /**< \brief (GPIO) Access Status Register 2 */\r
+#define REG_GPIO_PARAMETER2 REG_ACCESS(RoReg , 0x400E15F8U) /**< \brief (GPIO) Parameter Register 2 */\r
+#define REG_GPIO_VERSION2 REG_ACCESS(RoReg , 0x400E15FCU) /**< \brief (GPIO) Version Register 2 */\r
+/* ========== Register definition for BPM peripheral ========== */\r
+#define REG_BPM_IER REG_ACCESS(WoReg , 0x400F0000U) /**< \brief (BPM) Interrupt Enable Register */ \r
+#define REG_BPM_IDR REG_ACCESS(WoReg , 0x400F0004U) /**< \brief (BPM) Interrupt Disable Register */ \r
+#define REG_BPM_IMR REG_ACCESS(RoReg , 0x400F0008U) /**< \brief (BPM) Interrupt Mask Register */ \r
+#define REG_BPM_ISR REG_ACCESS(RoReg , 0x400F000CU) /**< \brief (BPM) Interrupt Status Register */ \r
+#define REG_BPM_ICR REG_ACCESS(WoReg , 0x400F0010U) /**< \brief (BPM) Interrupt Clear Register */ \r
+#define REG_BPM_SR REG_ACCESS(RoReg , 0x400F0014U) /**< \brief (BPM) Status Register */ \r
+#define REG_BPM_UNLOCK REG_ACCESS(WoReg , 0x400F0018U) /**< \brief (BPM) Unlock Register */ \r
+#define REG_BPM_PMCON REG_ACCESS(RwReg , 0x400F001CU) /**< \brief (BPM) Power Mode Control Register */ \r
+#define REG_BPM_BKUPWCAUSE REG_ACCESS(RoReg , 0x400F0028U) /**< \brief (BPM) Backup Wake up Cause Register */ \r
+#define REG_BPM_BKUPWEN REG_ACCESS(RwReg , 0x400F002CU) /**< \brief (BPM) Backup Wake up Enable Register */ \r
+#define REG_BPM_BKUPPMUX REG_ACCESS(RwReg , 0x400F0030U) /**< \brief (BPM) Backup Pin Muxing Register */ \r
+#define REG_BPM_IORET REG_ACCESS(RwReg , 0x400F0034U) /**< \brief (BPM) Input Output Retention Register */ \r
+#define REG_BPM_BPR REG_ACCESS(RwReg , 0x400F0040U) /**< \brief (BPM) Bypass Register */ \r
+#define REG_BPM_FWRUNPS REG_ACCESS(RoReg , 0x400F0044U) /**< \brief (BPM) Factory Word Run PS Register */ \r
+#define REG_BPM_FWPSAVEPS REG_ACCESS(RoReg , 0x400F0048U) /**< \brief (BPM) Factory Word Power Save PS Register */ \r
+#define REG_BPM_VERSION REG_ACCESS(RoReg , 0x400F00FCU) /**< \brief (BPM) Version Register */ \r
+/* ========== Register definition for BSCIF peripheral ========== */\r
+#define REG_BSCIF_IER REG_ACCESS(WoReg , 0x400F0400U) /**< \brief (BSCIF) Interrupt Enable Register */ \r
+#define REG_BSCIF_IDR REG_ACCESS(WoReg , 0x400F0404U) /**< \brief (BSCIF) Interrupt Disable Register */ \r
+#define REG_BSCIF_IMR REG_ACCESS(RoReg , 0x400F0408U) /**< \brief (BSCIF) Interrupt Mask Register */ \r
+#define REG_BSCIF_ISR REG_ACCESS(RoReg , 0x400F040CU) /**< \brief (BSCIF) Interrupt Status Register */ \r
+#define REG_BSCIF_ICR REG_ACCESS(WoReg , 0x400F0410U) /**< \brief (BSCIF) Interrupt Clear Register */ \r
+#define REG_BSCIF_PCLKSR REG_ACCESS(RoReg , 0x400F0414U) /**< \brief (BSCIF) Power and Clocks Status Register */ \r
+#define REG_BSCIF_UNLOCK REG_ACCESS(WoReg , 0x400F0418U) /**< \brief (BSCIF) Unlock Register */ \r
+#define REG_BSCIF_CSCR REG_ACCESS(RwReg , 0x400F041CU) /**< \brief (BSCIF) Chip Specific Configuration Register */ \r
+#define REG_BSCIF_OSCCTRL32 REG_ACCESS(RwReg , 0x400F0420U) /**< \brief (BSCIF) Oscillator 32 Control Register */ \r
+#define REG_BSCIF_RC32KCR REG_ACCESS(RwReg , 0x400F0424U) /**< \brief (BSCIF) 32 kHz RC Oscillator Control Register */ \r
+#define REG_BSCIF_RC32KTUNE REG_ACCESS(RwReg , 0x400F0428U) /**< \brief (BSCIF) 32kHz RC Oscillator Tuning Register */ \r
+#define REG_BSCIF_BOD33CTRL REG_ACCESS(RwReg , 0x400F042CU) /**< \brief (BSCIF) BOD33 Control Register */ \r
+#define REG_BSCIF_BOD33LEVEL REG_ACCESS(RwReg , 0x400F0430U) /**< \brief (BSCIF) BOD33 Level Register */ \r
+#define REG_BSCIF_BOD33SAMPLING REG_ACCESS(RwReg , 0x400F0434U) /**< \brief (BSCIF) BOD33 Sampling Control Register */ \r
+#define REG_BSCIF_BOD18CTRL REG_ACCESS(RwReg , 0x400F0438U) /**< \brief (BSCIF) BOD18 Control Register */ \r
+#define REG_BSCIF_BOD18LEVEL REG_ACCESS(RwReg , 0x400F043CU) /**< \brief (BSCIF) BOD18 Level Register */ \r
+#define REG_BSCIF_VREGCR REG_ACCESS(RwReg , 0x400F0444U) /**< \brief (BSCIF) Voltage Regulator Configuration Register */ \r
+#define REG_BSCIF_VREGNCSR REG_ACCESS(RwReg , 0x400F044CU) /**< \brief (BSCIF) Normal Mode Control and Status Register */ \r
+#define REG_BSCIF_VREGLPCSR REG_ACCESS(RwReg , 0x400F0450U) /**< \brief (BSCIF) LP Mode Control and Status Register */ \r
+#define REG_BSCIF_RC1MCR REG_ACCESS(RwReg , 0x400F0458U) /**< \brief (BSCIF) 1MHz RC Clock Configuration Register */ \r
+#define REG_BSCIF_BGCR REG_ACCESS(RwReg , 0x400F045CU) /**< \brief (BSCIF) Bandgap Calibration Register */ \r
+#define REG_BSCIF_BGCTRL REG_ACCESS(RwReg , 0x400F0460U) /**< \brief (BSCIF) Bandgap Control Register */ \r
+#define REG_BSCIF_BGSR REG_ACCESS(RoReg , 0x400F0464U) /**< \brief (BSCIF) Bandgap Status Register */ \r
+#define REG_BSCIF_BR0 REG_ACCESS(RwReg , 0x400F0478U) /**< \brief (BSCIF) Backup Register 0 */\r
+#define REG_BSCIF_BR1 REG_ACCESS(RwReg , 0x400F047CU) /**< \brief (BSCIF) Backup Register 1 */\r
+#define REG_BSCIF_BR2 REG_ACCESS(RwReg , 0x400F0480U) /**< \brief (BSCIF) Backup Register 2 */\r
+#define REG_BSCIF_BR3 REG_ACCESS(RwReg , 0x400F0484U) /**< \brief (BSCIF) Backup Register 3 */\r
+#define REG_BSCIF_BRIFBVERSION REG_ACCESS(RoReg , 0x400F07E4U) /**< \brief (BSCIF) Backup Register Interface Version Register */ \r
+#define REG_BSCIF_BGREFIFBVERSION REG_ACCESS(RoReg , 0x400F07E8U) /**< \brief (BSCIF) BGREFIFB Version Register */ \r
+#define REG_BSCIF_VREGIFGVERSION REG_ACCESS(RoReg , 0x400F07ECU) /**< \brief (BSCIF) VREGIFA Version Register */ \r
+#define REG_BSCIF_BODIFCVERSION REG_ACCESS(RoReg , 0x400F07F0U) /**< \brief (BSCIF) BODIFC Version Register */ \r
+#define REG_BSCIF_RC32KIFBVERSION REG_ACCESS(RoReg , 0x400F07F4U) /**< \brief (BSCIF) 32 kHz RC Oscillator Version Register */ \r
+#define REG_BSCIF_OSC32IFAVERSION REG_ACCESS(RoReg , 0x400F07F8U) /**< \brief (BSCIF) 32 KHz Oscillator Version Register */ \r
+#define REG_BSCIF_VERSION REG_ACCESS(RoReg , 0x400F07FCU) /**< \brief (BSCIF) BSCIF Version Register */ \r
+/* ========== Register definition for AST peripheral ========== */\r
+#define REG_AST_CR REG_ACCESS(RwReg , 0x400F0800U) /**< \brief (AST) Control Register */ \r
+#define REG_AST_CV REG_ACCESS(RwReg , 0x400F0804U) /**< \brief (AST) Counter Value */ \r
+#define REG_AST_SR REG_ACCESS(RoReg , 0x400F0808U) /**< \brief (AST) Status Register */ \r
+#define REG_AST_SCR REG_ACCESS(WoReg , 0x400F080CU) /**< \brief (AST) Status Clear Register */ \r
+#define REG_AST_IER REG_ACCESS(WoReg , 0x400F0810U) /**< \brief (AST) Interrupt Enable Register */ \r
+#define REG_AST_IDR REG_ACCESS(WoReg , 0x400F0814U) /**< \brief (AST) Interrupt Disable Register */ \r
+#define REG_AST_IMR REG_ACCESS(RoReg , 0x400F0818U) /**< \brief (AST) Interrupt Mask Register */ \r
+#define REG_AST_WER REG_ACCESS(RwReg , 0x400F081CU) /**< \brief (AST) Wake Enable Register */ \r
+#define REG_AST_AR0 REG_ACCESS(RwReg , 0x400F0820U) /**< \brief (AST) Alarm Register 0 */ \r
+#define REG_AST_AR1 REG_ACCESS(RwReg , 0x400F0824U) /**< \brief (AST) Alarm Register 1 */ \r
+#define REG_AST_PIR0 REG_ACCESS(RwReg , 0x400F0830U) /**< \brief (AST) Periodic Interval Register 0 */ \r
+#define REG_AST_PIR1 REG_ACCESS(RwReg , 0x400F0834U) /**< \brief (AST) Periodic Interval Register 1 */ \r
+#define REG_AST_CLOCK REG_ACCESS(RwReg , 0x400F0840U) /**< \brief (AST) Clock Control Register */ \r
+#define REG_AST_DTR REG_ACCESS(RwReg , 0x400F0844U) /**< \brief (AST) Digital Tuner Register */ \r
+#define REG_AST_EVE REG_ACCESS(WoReg , 0x400F0848U) /**< \brief (AST) Event Enable Register */ \r
+#define REG_AST_EVD REG_ACCESS(WoReg , 0x400F084CU) /**< \brief (AST) Event Disable Register */ \r
+#define REG_AST_EVM REG_ACCESS(RoReg , 0x400F0850U) /**< \brief (AST) Event Mask Register */ \r
+#define REG_AST_CALV REG_ACCESS(RwReg , 0x400F0854U) /**< \brief (AST) Calendar Value */ \r
+#define REG_AST_PARAMETER REG_ACCESS(RoReg , 0x400F08F0U) /**< \brief (AST) Parameter Register */ \r
+#define REG_AST_VERSION REG_ACCESS(RoReg , 0x400F08FCU) /**< \brief (AST) Version Register */ \r
+/* ========== Register definition for WDT peripheral ========== */\r
+#define REG_WDT_CTRL REG_ACCESS(RwReg , 0x400F0C00U) /**< \brief (WDT) Control Register */ \r
+#define REG_WDT_CLR REG_ACCESS(WoReg , 0x400F0C04U) /**< \brief (WDT) Clear Register */ \r
+#define REG_WDT_SR REG_ACCESS(RoReg , 0x400F0C08U) /**< \brief (WDT) Status Register */ \r
+#define REG_WDT_IER REG_ACCESS(WoReg , 0x400F0C0CU) /**< \brief (WDT) Interrupt Enable Register */ \r
+#define REG_WDT_IDR REG_ACCESS(WoReg , 0x400F0C10U) /**< \brief (WDT) Interrupt Disable Register */ \r
+#define REG_WDT_IMR REG_ACCESS(RoReg , 0x400F0C14U) /**< \brief (WDT) Interrupt Mask Register */ \r
+#define REG_WDT_ISR REG_ACCESS(RoReg , 0x400F0C18U) /**< \brief (WDT) Interrupt Status Register */ \r
+#define REG_WDT_ICR REG_ACCESS(WoReg , 0x400F0C1CU) /**< \brief (WDT) Interrupt Clear Register */ \r
+#define REG_WDT_VERSION REG_ACCESS(RoReg , 0x400F0FFCU) /**< \brief (WDT) Version Register */ \r
+/* ========== Register definition for EIC peripheral ========== */\r
+#define REG_EIC_IER REG_ACCESS(WoReg , 0x400F1000U) /**< \brief (EIC) Interrupt Enable Register */ \r
+#define REG_EIC_IDR REG_ACCESS(WoReg , 0x400F1004U) /**< \brief (EIC) Interrupt Disable Register */ \r
+#define REG_EIC_IMR REG_ACCESS(RoReg , 0x400F1008U) /**< \brief (EIC) Interrupt Mask Register */ \r
+#define REG_EIC_ISR REG_ACCESS(RoReg , 0x400F100CU) /**< \brief (EIC) Interrupt Status Register */ \r
+#define REG_EIC_ICR REG_ACCESS(WoReg , 0x400F1010U) /**< \brief (EIC) Interrupt Clear Register */ \r
+#define REG_EIC_MODE REG_ACCESS(RwReg , 0x400F1014U) /**< \brief (EIC) Mode Register */ \r
+#define REG_EIC_EDGE REG_ACCESS(RwReg , 0x400F1018U) /**< \brief (EIC) Edge Register */ \r
+#define REG_EIC_LEVEL REG_ACCESS(RwReg , 0x400F101CU) /**< \brief (EIC) Level Register */ \r
+#define REG_EIC_FILTER REG_ACCESS(RwReg , 0x400F1020U) /**< \brief (EIC) Filter Register */ \r
+#define REG_EIC_ASYNC REG_ACCESS(RwReg , 0x400F1028U) /**< \brief (EIC) Asynchronous Register */ \r
+#define REG_EIC_EN REG_ACCESS(WoReg , 0x400F1030U) /**< \brief (EIC) Enable Register */ \r
+#define REG_EIC_DIS REG_ACCESS(WoReg , 0x400F1034U) /**< \brief (EIC) Disable Register */ \r
+#define REG_EIC_CTRL REG_ACCESS(RoReg , 0x400F1038U) /**< \brief (EIC) Control Register */ \r
+#define REG_EIC_VERSION REG_ACCESS(RoReg , 0x400F13FCU) /**< \brief (EIC) Version Register */ \r
+/* ========== Register definition for PICOUART peripheral ========== */\r
+#define REG_PICOUART_CR REG_ACCESS(WoReg , 0x400F1400U) /**< \brief (PICOUART) Control Register */ \r
+#define REG_PICOUART_CFG REG_ACCESS(RwReg , 0x400F1404U) /**< \brief (PICOUART) Configuration Register */ \r
+#define REG_PICOUART_SR REG_ACCESS(RoReg , 0x400F1408U) /**< \brief (PICOUART) Status Register */ \r
+#define REG_PICOUART_RHR REG_ACCESS(RoReg , 0x400F140CU) /**< \brief (PICOUART) Receive Holding Register */ \r
+#define REG_PICOUART_VERSION REG_ACCESS(RoReg , 0x400F1420U) /**< \brief (PICOUART) Version Register */ \r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** NUMBER OF PERIPHERAL INSTANCES FOR SAM4L */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4L_inst_num Number of Peripheral Instances */\r
+/*@{*/\r
+\r
+#define ABDACB_INST_NUM 1 /**< \brief Audio Bitstream DAC instances */\r
+#define ACIFC_INST_NUM 1 /**< \brief Analog Comparator Interface instances */\r
+#define ADCIFE_INST_NUM 1 /**< \brief ADC controller interface instances */\r
+#define AESA_INST_NUM 1 /**< \brief Advanced Encryption Standard instances */\r
+#define AST_INST_NUM 1 /**< \brief Asynchronous Timer instances */\r
+#define BPM_INST_NUM 1 /**< \brief Backup Power Manager instances */\r
+#define BSCIF_INST_NUM 1 /**< \brief Backup System Control Interface instances */\r
+#define CATB_INST_NUM 1 /**< \brief Capacitive Touch Module B instances */\r
+#define CHIPID_INST_NUM 1 /**< \brief Chip ID Registers instances */\r
+#define CRCCU_INST_NUM 1 /**< \brief CRC Calculation Unit instances */\r
+#define DACC_INST_NUM 1 /**< \brief DAC Controller instances */\r
+#define EIC_INST_NUM 1 /**< \brief External Interrupt Controller instances */\r
+#define FLASHCALW_INST_NUM 1 /**< \brief Flash Controller instances */\r
+#define FREQM_INST_NUM 1 /**< \brief Frequency Meter instances */\r
+#define GLOC_INST_NUM 1 /**< \brief Glue Logic Controller instances */\r
+#define GPIO_INST_NUM 1 /**< \brief General-Purpose Input/Output Controller instances */\r
+#define HCACHE_INST_NUM 1 /**< \brief Cortex M I&D Cache Controller instances */\r
+#define HMATRIXB_INST_NUM 1 /**< \brief HSB Matrix instances */\r
+#define IISC_INST_NUM 1 /**< \brief Inter-IC Sound (I2S) Controller instances */\r
+#define LCDCA_INST_NUM 1 /**< \brief LCD Controller instances */\r
+#define PARC_INST_NUM 1 /**< \brief Parallel Capture instances */\r
+#define PDCA_INST_NUM 1 /**< \brief Peripheral DMA Controller instances */\r
+#define PEVC_INST_NUM 1 /**< \brief Peripheral Event Controller instances */\r
+#define PICOUART_INST_NUM 1 /**< \brief Pico UART instances */\r
+#define PM_INST_NUM 1 /**< \brief Power Manager instances */\r
+#define SCIF_INST_NUM 1 /**< \brief System Control Interface instances */\r
+#define SMAP_INST_NUM 1 /**< \brief System Manager Access Port instances */\r
+#define SPI_INST_NUM 1 /**< \brief Serial Peripheral Interface instances */\r
+#define TC_INST_NUM 2 /**< \brief Timer/Counter instances */\r
+#define TRNG_INST_NUM 1 /**< \brief True Random Number Generator instances */\r
+#define TWIM_INST_NUM 4 /**< \brief Two-wire Master Interface instances */\r
+#define TWIS_INST_NUM 2 /**< \brief Two-wire Slave Interface instances */\r
+#define USART_INST_NUM 4 /**< \brief Universal Synchronous Asynchronous Receiver Transmitter instances */\r
+#define USBC_INST_NUM 1 /**< \brief USB 2.0 Interface instances */\r
+#define WDT_INST_NUM 1 /**< \brief Watchdog Timer instances */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** PERIPHERAL ID DEFINITIONS FOR SAM4L */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4L_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_IISC ( 0) /**< \brief Inter-IC Sound (I2S) Controller (IISC) */\r
+#define ID_SPI ( 1) /**< \brief Serial Peripheral Interface (SPI) */\r
+#define ID_TC0 ( 2) /**< \brief Timer/Counter TC (TC0) */\r
+#define ID_TC1 ( 3) /**< \brief Timer/Counter TC (TC1) */\r
+#define ID_TWIM0 ( 4) /**< \brief Two-wire Master Interface TWIM (TWIM0) */\r
+#define ID_TWIS0 ( 5) /**< \brief Two-wire Slave Interface TWIS (TWIS0) */\r
+#define ID_TWIM1 ( 6) /**< \brief Two-wire Master Interface TWIM (TWIM1) */\r
+#define ID_TWIS1 ( 7) /**< \brief Two-wire Slave Interface TWIS (TWIS1) */\r
+#define ID_USART0 ( 8) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter USART (USART0) */\r
+#define ID_USART1 ( 9) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter USART (USART1) */\r
+#define ID_USART2 (10) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter USART (USART2) */\r
+#define ID_USART3 (11) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter USART (USART3) */\r
+#define ID_ADCIFE (12) /**< \brief ADC controller interface (ADCIFE) */\r
+#define ID_DACC (13) /**< \brief DAC Controller (DACC) */\r
+#define ID_ACIFC (14) /**< \brief Analog Comparator Interface (ACIFC) */\r
+#define ID_GLOC (15) /**< \brief Glue Logic Controller (GLOC) */\r
+#define ID_ABDACB (16) /**< \brief Audio Bitstream DAC (ABDACB) */\r
+#define ID_TRNG (17) /**< \brief True Random Number Generator (TRNG) */\r
+#define ID_PARC (18) /**< \brief Parallel Capture (PARC) */\r
+#define ID_CATB (19) /**< \brief Capacitive Touch Module B (CATB) */\r
+#define ID_TWIM2 (20) /**< \brief Two-wire Master Interface TWIM (TWIM2) */\r
+#define ID_TWIM3 (21) /**< \brief Two-wire Master Interface TWIM (TWIM3) */\r
+#define ID_LCDCA (22) /**< \brief LCD Controller (LCDCA) */\r
+#define ID_HFLASHC (23) /**< \brief Flash Controller (HFLASHC) */\r
+#define ID_HCACHE (24) /**< \brief Cortex M I&D Cache Controller (HCACHE) */\r
+#define ID_HMATRIX (25) /**< \brief HSB Matrix (HMATRIX) */\r
+#define ID_PDCA (26) /**< \brief Peripheral DMA Controller (PDCA) */\r
+#define ID_SMAP (27) /**< \brief System Manager Access Port (SMAP) */\r
+#define ID_CRCCU (28) /**< \brief CRC Calculation Unit (CRCCU) */\r
+#define ID_USBC (29) /**< \brief USB 2.0 Interface (USBC) */\r
+#define ID_PEVC (30) /**< \brief Peripheral Event Controller (PEVC) */\r
+#define ID_AESA (31) /**< \brief Advanced Encryption Standard (AESA) */\r
+#define ID_PM (32) /**< \brief Power Manager (PM) */\r
+#define ID_CHIPID (33) /**< \brief Chip ID Registers (CHIPID) */\r
+#define ID_SCIF (34) /**< \brief System Control Interface (SCIF) */\r
+#define ID_FREQM (35) /**< \brief Frequency Meter (FREQM) */\r
+#define ID_GPIO (36) /**< \brief General-Purpose Input/Output Controller (GPIO) */\r
+#define ID_BPM (37) /**< \brief Backup Power Manager (BPM) */\r
+#define ID_BSCIF (38) /**< \brief Backup System Control Interface (BSCIF) */\r
+#define ID_AST (39) /**< \brief Asynchronous Timer (AST) */\r
+#define ID_WDT (40) /**< \brief Watchdog Timer (WDT) */\r
+#define ID_EIC (41) /**< \brief External Interrupt Controller (EIC) */\r
+#define ID_PICOUART (42) /**< \brief Pico UART (PICOUART) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** BASE ADDRESS DEFINITIONS FOR SAM4L */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4L_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#define ABDACB_ADDR (0x40064000U) /**< \brief (ABDACB) Base Address */\r
+#define ABDACB CAST(Abdacb, ABDACB_ADDR) \r
+#define ACIFC_ADDR (0x40040000U) /**< \brief (ACIFC) Base Address */\r
+#define ACIFC CAST(Acifc, ACIFC_ADDR) \r
+#define ADCIFE_ADDR (0x40038000U) /**< \brief (ADCIFE) Base Address */\r
+#define ADCIFE CAST(Adcife, ADCIFE_ADDR) \r
+#define AESA_ADDR (0x400B0000U) /**< \brief (AESA) Base Address */\r
+#define AESA CAST(Aesa, AESA_ADDR) \r
+#define AST_ADDR (0x400F0800U) /**< \brief (AST) Base Address */\r
+#define AST CAST(Ast, AST_ADDR) \r
+#define BPM_ADDR (0x400F0000U) /**< \brief (BPM) Base Address */\r
+#define BPM CAST(Bpm, BPM_ADDR) \r
+#define BSCIF_ADDR (0x400F0400U) /**< \brief (BSCIF) Base Address */\r
+#define BSCIF CAST(Bscif, BSCIF_ADDR) \r
+#define CATB_ADDR (0x40070000U) /**< \brief (CATB) Base Address */\r
+#define CATB CAST(Catb, CATB_ADDR) \r
+#define CHIPID_ADDR (0x400E0400U) /**< \brief (CHIPID) Base Address */\r
+#define CHIPID CAST(Chipid, CHIPID_ADDR) \r
+#define CRCCU_ADDR (0x400A4000U) /**< \brief (CRCCU) Base Address */\r
+#define CRCCU CAST(Crccu, CRCCU_ADDR) \r
+#define DACC_ADDR (0x4003C000U) /**< \brief (DACC) Base Address */\r
+#define DACC CAST(Dacc, DACC_ADDR) \r
+#define EIC_ADDR (0x400F1000U) /**< \brief (EIC) Base Address */\r
+#define EIC CAST(Eic, EIC_ADDR) \r
+#define HFLASHC_ADDR (0x400A0000U) /**< \brief (HFLASHC) Base Address */\r
+#define HFLASHC CAST(Flashcalw, HFLASHC_ADDR) \r
+#define FREQM_ADDR (0x400E0C00U) /**< \brief (FREQM) Base Address */\r
+#define FREQM CAST(Freqm, FREQM_ADDR) \r
+#define GLOC_ADDR (0x40060000U) /**< \brief (GLOC) Base Address */\r
+#define GLOC CAST(Gloc, GLOC_ADDR) \r
+#define GPIO_ADDR (0x400E1000U) /**< \brief (GPIO) Base Address */\r
+#define GPIO CAST(Gpio, GPIO_ADDR) \r
+#define HCACHE_ADDR (0x400A0400U) /**< \brief (HCACHE) Base Address */\r
+#define HCACHE CAST(Hcache, HCACHE_ADDR) \r
+#define HMATRIX_ADDR (0x400A1000U) /**< \brief (HMATRIX) Base Address */\r
+#define HMATRIX CAST(Hmatrixb, HMATRIX_ADDR) \r
+#define IISC_ADDR (0x40004000U) /**< \brief (IISC) Base Address */\r
+#define IISC CAST(Iisc, IISC_ADDR) \r
+#define LCDCA_ADDR (0x40080000U) /**< \brief (LCDCA) Base Address */\r
+#define LCDCA CAST(Lcdca, LCDCA_ADDR) \r
+#define PARC_ADDR (0x4006C000U) /**< \brief (PARC) Base Address */\r
+#define PARC CAST(Parc, PARC_ADDR) \r
+#define PDCA_ADDR (0x400A2000U) /**< \brief (PDCA) Base Address */\r
+#define PDCA CAST(Pdca, PDCA_ADDR) \r
+#define PEVC_ADDR (0x400A6000U) /**< \brief (PEVC) Base Address */\r
+#define PEVC CAST(Pevc, PEVC_ADDR) \r
+#define PICOUART_ADDR (0x400F1400U) /**< \brief (PICOUART) Base Address */\r
+#define PICOUART CAST(Picouart, PICOUART_ADDR) \r
+#define PM_ADDR (0x400E0000U) /**< \brief (PM) Base Address */\r
+#define PM CAST(Pm, PM_ADDR) \r
+#define SCIF_ADDR (0x400E0800U) /**< \brief (SCIF) Base Address */\r
+#define SCIF CAST(Scif, SCIF_ADDR) \r
+#define SMAP_ADDR (0x400A3000U) /**< \brief (SMAP) Base Address */\r
+#define SMAP CAST(Smap, SMAP_ADDR) \r
+#define SPI_ADDR (0x40008000U) /**< \brief (SPI) Base Address */\r
+#define SPI CAST(Spi, SPI_ADDR) \r
+#define TC0_ADDR (0x40010000U) /**< \brief (TC0) Base Address */\r
+#define TC0 CAST(Tc, TC0_ADDR) \r
+#define TC1_ADDR (0x40014000U) /**< \brief (TC1) Base Address */\r
+#define TC1 CAST(Tc, TC1_ADDR) \r
+#define TRNG_ADDR (0x40068000U) /**< \brief (TRNG) Base Address */\r
+#define TRNG CAST(Trng, TRNG_ADDR) \r
+#define TWIM0_ADDR (0x40018000U) /**< \brief (TWIM0) Base Address */\r
+#define TWIM0 CAST(Twim, TWIM0_ADDR) \r
+#define TWIM1_ADDR (0x4001C000U) /**< \brief (TWIM1) Base Address */\r
+#define TWIM1 CAST(Twim, TWIM1_ADDR) \r
+#define TWIM2_ADDR (0x40078000U) /**< \brief (TWIM2) Base Address */\r
+#define TWIM2 CAST(Twim, TWIM2_ADDR) \r
+#define TWIM3_ADDR (0x4007C000U) /**< \brief (TWIM3) Base Address */\r
+#define TWIM3 CAST(Twim, TWIM3_ADDR) \r
+#define TWIS0_ADDR (0x40018400U) /**< \brief (TWIS0) Base Address */\r
+#define TWIS0 CAST(Twis, TWIS0_ADDR) \r
+#define TWIS1_ADDR (0x4001C400U) /**< \brief (TWIS1) Base Address */\r
+#define TWIS1 CAST(Twis, TWIS1_ADDR) \r
+#define USART0_ADDR (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART0 CAST(Usart, USART0_ADDR) \r
+#define USART1_ADDR (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART1 CAST(Usart, USART1_ADDR) \r
+#define USART2_ADDR (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define USART2 CAST(Usart, USART2_ADDR) \r
+#define USART3_ADDR (0x40030000U) /**< \brief (USART3) Base Address */\r
+#define USART3 CAST(Usart, USART3_ADDR) \r
+#define USBC_ADDR (0x400A5000U) /**< \brief (USBC) Base Address */\r
+#define USBC CAST(Usbc, USBC_ADDR) \r
+#define WDT_ADDR (0x400F0C00U) /**< \brief (WDT) Base Address */\r
+#define WDT CAST(Wdt, WDT_ADDR) \r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** INSTANCE PARAMETERS DEFINITIONS FOR SAM4L */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4L_parameters Instance Parameters Definitions */\r
+/*@{*/\r
+\r
+/* ========== Instance parameters for ABDACB peripheral ========== */\r
+#define ABDACB_GCLK_NUM 6\r
+#define ABDACB_PDCA_ID_TX_CH0 31\r
+#define ABDACB_PDCA_ID_TX_CH1 32\r
+/* ========== Instance parameters for ADCIFE peripheral ========== */\r
+#define ADCIFE_CHANNELS 16\r
+#define ADCIFE_CHANNEL_MSB 15\r
+#define ADCIFE_EXT_TRIGGERS_MSB 0\r
+#define ADCIFE_GCLK_NUM 10\r
+#define ADCIFE_PDCA_ID_RX 11\r
+#define ADCIFE_PDCA_ID_TX 29\r
+#define ADCIFE_REG_RX LCV\r
+#define ADCIFE_REG_TX CDMA\r
+/* ========== Instance parameters for AESA peripheral ========== */\r
+#define AESA_DMAC_ID_RX \r
+#define AESA_DMAC_ID_TX \r
+#define AESA_GCLK_NUM 4\r
+#define AESA_PDCA_ID_RX 17\r
+#define AESA_PDCA_ID_TX 36\r
+/* ========== Instance parameters for AST peripheral ========== */\r
+#define AST_CLK1K 4\r
+#define AST_CLK32 1\r
+#define AST_GCLK_NUM 2\r
+#define AST_GENCLK 3\r
+#define AST_PB 2\r
+#define AST_RCOSC 0\r
+/* ========== Instance parameters for BPM peripheral ========== */\r
+#define BPM_BKUPPMUX_MSB 9\r
+#define BPM_BKUPWEN_AST 1\r
+#define BPM_BKUPWEN_BOD18 4\r
+#define BPM_BKUPWEN_BOD33 3\r
+#define BPM_BKUPWEN_EIC 0\r
+#define BPM_BKUPWEN_MSB 5\r
+#define BPM_BKUPWEN_PICOUART 5\r
+#define BPM_BKUPWEN_WDT 2\r
+/* ========== Instance parameters for BSCIF peripheral ========== */\r
+#define BSCIF_BGBUF_NUM 6\r
+#define BSCIF_BOD18_IMPLEMENTED 0\r
+#define BSCIF_BOD33_IMPLEMENTED 0\r
+#define BSCIF_BOD50_IMPLEMENTED 0\r
+#define BSCIF_BR_NUM 4\r
+/* ========== Instance parameters for CATB peripheral ========== */\r
+#define CATB_GCLK_NUM 3\r
+#define CATB_PDCA_ID_RX 12\r
+#define CATB_PDCA_ID_TX 30\r
+#define CATB_SENSORS_MSB 31\r
+#define CATB_STATUS_REG_NUMBER 1\r
+/* ========== Instance parameters for DACC peripheral ========== */\r
+#define DACC_DACC_EXT_TRIG_MSB 0\r
+#define DACC_DAC_RES_MSB 9\r
+#define DACC_PDCA_ID_TX 35\r
+/* ========== Instance parameters for EIC peripheral ========== */\r
+#define EIC_STD_NUM 8\r
+/* ========== Instance parameters for FREQM peripheral ========== */\r
+#define FREQM_CPU 0\r
+#define FREQM_CRIPOSC 10\r
+#define FREQM_DFLL0 9\r
+#define FREQM_FLO_JITTER 27\r
+#define FREQM_GENCLK0 11\r
+#define FREQM_GENCLK1 12\r
+#define FREQM_GENCLK2 13\r
+#define FREQM_GENCLK3 14\r
+#define FREQM_GENCLK4 15\r
+#define FREQM_GENCLK5 16\r
+#define FREQM_GENCLK6 17\r
+#define FREQM_GENCLK7 18\r
+#define FREQM_GENCLK8 19\r
+#define FREQM_GENCLK9 20\r
+#define FREQM_GENCLK10 21\r
+#define FREQM_HSB 1\r
+#define FREQM_NUM_CLK 28\r
+#define FREQM_NUM_REF_CLK 4\r
+#define FREQM_OSC0 6\r
+#define FREQM_OSC32 7\r
+#define FREQM_PBA 2\r
+#define FREQM_PBB 3\r
+#define FREQM_PBC 4\r
+#define FREQM_PLL0 26\r
+#define FREQM_RCFAST 24\r
+#define FREQM_RCOSC 8\r
+#define FREQM_RC1M 25\r
+#define FREQM_RC32K 7\r
+#define FREQM_RC80M 23\r
+#define FREQM_REFSEL_BITS 2\r
+#define FREQM_REF_OSC32 1\r
+#define FREQM_REF_RCOSC 0\r
+/* ========== Instance parameters for GLOC peripheral ========== */\r
+#define GLOC_GCLK_NUM 5\r
+#define GLOC_LUTS 2\r
+/* ========== Instance parameters for GPIO peripheral ========== */\r
+#define GPIO_GPIO_IRQ_MSB 11\r
+#define GPIO_GPIO_MAX_IRQ_MSB 11\r
+#define GPIO_GPIO_PADDR_BITS 11\r
+#define GPIO_GPIO_PINS_MSB 95\r
+#define GPIO_IRQS_PER_GROUP 8\r
+#define GPIO_NUMBER_OF_PINS 96\r
+#define GPIO_PADDR_MSB 10\r
+#define GPIO_PDATA_MSB 31\r
+#define GPIO_PORT_LENGTH 3\r
+/* ========== Instance parameters for HMATRIX ========== */\r
+#define HMATRIX_SLAVE_FLASH 0\r
+#define HMATRIX_SLAVE_HTOP0 1\r
+#define HMATRIX_SLAVE_HTOP1 2\r
+#define HMATRIX_SLAVE_HTOP2 3\r
+#define HMATRIX_SLAVE_HTOP3 4\r
+#define HMATRIX_SLAVE_HRAMC0 5\r
+#define HMATRIX_SLAVE_HRAMC1 6\r
+#define HMATRIX_SLAVE_AESA 7\r
+#define HMATRIX_SLAVE_NUM 8\r
+\r
+#define HMATRIX_MASTER_CPU_IDCODE 0\r
+#define HMATRIX_MASTER_CPU_SYS 1\r
+#define HMATRIX_MASTER_SMAP 2\r
+#define HMATRIX_MASTER_PDCA 3\r
+#define HMATRIX_MASTER_USBC_MASTER 4\r
+#define HMATRIX_MASTER_CRCCU 5\r
+#define HMATRIX_MASTER_NUM 6\r
+/* ========== Instance parameters for IISC peripheral ========== */\r
+#define IISC_GCLK_NUM 6\r
+#define IISC_PDCA_ID_RX 14\r
+#define IISC_PDCA_ID_RX_1 15\r
+#define IISC_PDCA_ID_TX 33\r
+#define IISC_PDCA_ID_TX_1 34\r
+/* ========== Instance parameters for LCDCA peripheral ========== */\r
+#define LCDCA_PDCA_ID_TX_ABM 38\r
+#define LCDCA_PDCA_ID_TX_ACM 37\r
+/* ========== Instance parameters for PARC peripheral ========== */\r
+#define PARC_PDCA_ID_RX 16\r
+/* ========== Instance parameters for PDCA peripheral ========== */\r
+#define PDCA_CHANNEL_LENGTH 16\r
+#define PDCA_CLK_AHB_ID 0\r
+#define PDCA_MON_CH0_IMPL 0\r
+#define PDCA_MON_CH1_IMPL 0\r
+/* ========== Instance parameters for PEVC peripheral ========== */\r
+#define PEVC_EVIN_BITS 31\r
+#define PEVC_GCLK_NUM_0 8\r
+#define PEVC_GCLK_NUM_1 9\r
+#define PEVC_GCLK_NUM_LSB 8\r
+#define PEVC_GCLK_NUM_MSB 9\r
+#define PEVC_GCLK_NUM_SIZE 2\r
+#define PEVC_PADS_BITS 4\r
+#define PEVC_TRIGOUT_BITS 19\r
+\r
+// GENERATORS\r
+#define PEVC_ID_GEN_PAD_0 0 /* EVS IGF */\r
+#define PEVC_ID_GEN_PAD_1 1 /* EVS IGF */\r
+#define PEVC_ID_GEN_PAD_2 2 /* EVS IGF */\r
+#define PEVC_ID_GEN_PAD_3 3 /* EVS IGF */\r
+#define PEVC_ID_GEN_GCLK_0 4 /* EVS */\r
+#define PEVC_ID_GEN_GCLK_1 5 /* EVS */\r
+#define PEVC_ID_GEN_AST_0 6 /* EVS */\r
+#define PEVC_ID_GEN_AST_1 7 /* EVS */\r
+#define PEVC_ID_GEN_AST_2 8 /* EVS */\r
+#define PEVC_ID_GEN_AST_3 9 /* EVS */\r
+#define PEVC_ID_GEN_AST_4 10 /* EVS */\r
+#define PEVC_ID_GEN_ACIFC_CHANNEL_POSITIVE_0 11\r
+#define PEVC_ID_GEN_ACIFC_CHANNEL_POSITIVE_1 12\r
+#define PEVC_ID_GEN_ACIFC_CHANNEL_POSITIVE_2 13\r
+#define PEVC_ID_GEN_ACIFC_CHANNEL_POSITIVE_3 14\r
+#define PEVC_ID_GEN_ACIFC_CHANNEL_NEGATIVE_0 15\r
+#define PEVC_ID_GEN_ACIFC_CHANNEL_NEGATIVE_1 16\r
+#define PEVC_ID_GEN_ACIFC_CHANNEL_NEGATIVE_2 17\r
+#define PEVC_ID_GEN_ACIFC_CHANNEL_NEGATIVE_3 18\r
+#define PEVC_ID_GEN_ACIFC_WINDOW_0 19\r
+#define PEVC_ID_GEN_ACIFC_WINDOW_1 20\r
+#define PEVC_ID_GEN_TC0_A0 21 /* EVS */\r
+#define PEVC_ID_GEN_TC0_A1 22 /* EVS */\r
+#define PEVC_ID_GEN_TC0_A2 23 /* EVS */\r
+#define PEVC_ID_GEN_TC0_B0 24 /* EVS */\r
+#define PEVC_ID_GEN_TC0_B1 25 /* EVS */\r
+#define PEVC_ID_GEN_TC0_B2 26 /* EVS */\r
+#define PEVC_ID_GEN_ADCIFE_WM 27\r
+#define PEVC_ID_GEN_ADCIFE_EOC 28\r
+#define PEVC_ID_GEN_VREGIFG_SSWRDY 29\r
+#define PEVC_ID_GEN_PICOUART 30 /* EVS */\r
+\r
+#define PEVC_CHMX0_EVMX_SIZE_IMPL 5\r
+#define PEVC_CHMX0_EVMX_MASK_IMPL 0x0000001F\r
+\r
+#define PEVC_EVS_IMPL 0b1000111111000000000011111111111\r
+#define PEVC_IGF_IMPL 0b0000000000000000000000000001111\r
+\r
+// USERS / CHANNELS\r
+#define PEVC_ID_USER_PDCA_0 0\r
+#define PEVC_ID_USER_PDCA_1 1\r
+#define PEVC_ID_USER_PDCA_2 2\r
+#define PEVC_ID_USER_PDCA_3 3\r
+#define PEVC_ID_USER_ADCIFE_SOC 4\r
+#define PEVC_ID_USER_DACC_CONV 5\r
+#define PEVC_ID_USER_CATB 6\r
+#define PEVC_ID_USER_TC1_A0 8\r
+#define PEVC_ID_USER_TC1_A1 9\r
+#define PEVC_ID_USER_TC1_A2 10\r
+#define PEVC_ID_USER_TC1_B0 11\r
+#define PEVC_ID_USER_TC1_B1 12\r
+#define PEVC_ID_USER_TC1_B2 13\r
+#define PEVC_ID_USER_ACIFC 14\r
+#define PEVC_ID_USER_PARC_START 15\r
+#define PEVC_ID_USER_PARC_STOP 16\r
+#define PEVC_ID_USER_VREGIFG_SSWREQ 17\r
+#define PEVC_ID_USER_VREGIFG_SSWDIS 18\r
+/* ========== Instance parameters for PM peripheral ========== */\r
+#define PM_AWEN_LCDCA 7\r
+#define PM_AWEN_PICOUART 6\r
+#define PM_AWEN_TWIS0 0\r
+#define PM_AWEN_TWIS1 1\r
+#define PM_AWEN_USBC 2\r
+#define PM_MCCTRL_MCSEL_DFLL0 3\r
+#define PM_MCCTRL_MCSEL_FLO 7\r
+#define PM_MCCTRL_MCSEL_OSC0 1\r
+#define PM_MCCTRL_MCSEL_PLL0 2\r
+#define PM_MCCTRL_MCSEL_RCFAST 5\r
+#define PM_MCCTRL_MCSEL_RC1M 6\r
+#define PM_MCCTRL_MCSEL_RC80M 4\r
+#define PM_MCCTRL_MCSEL_SLOW 0\r
+#define PM_PM_CLK_APB_NUM 4\r
+#define PM_PPCR_FLASH_WAIT_BGREF_MASK 512\r
+#define PM_PPCR_FLASH_WAIT_BOD18_MASK 1024\r
+/* ========== Instance parameters for SCIF peripheral ========== */\r
+#define SCIF_BOD33_IMPLEMENTED 0\r
+#define SCIF_BOD50_IMPLEMENTED 0\r
+#define SCIF_BR_NUM 0\r
+#define SCIF_DFLL_CALIB_MSB 3\r
+#define SCIF_DFLL_COARSE_MSB 4\r
+#define SCIF_DFLL_FINE_MSB 7\r
+#define SCIF_DFLL_RANGE_MSB 1\r
+#define SCIF_GCLK_EXTCLK_MSB 3\r
+#define SCIF_GCLK_IN_MSB 1\r
+#define SCIF_GCLK_IN_NUM 2\r
+#define SCIF_GCLK_MSB 10\r
+#define SCIF_GCLK_NUM 12\r
+#define SCIF_GCLK_NUM_DFLL_REF 0\r
+#define SCIF_GCLK_NUM_DFLL_SSG 1\r
+#define SCIF_GCLK_NUM_EXTCLK_0 0\r
+#define SCIF_GCLK_NUM_EXTCLK_1 1\r
+#define SCIF_GCLK_NUM_EXTCLK_2 2\r
+#define SCIF_GCLK_NUM_EXTCLK_3 3\r
+#define SCIF_GCLK_NUM_EXTCLK_LSB 0\r
+#define SCIF_GCLK_NUM_EXTCLK_MSB 3\r
+#define SCIF_GCLK_NUM_EXTCLK_SIZE 4\r
+#define SCIF_GCLK_NUM_FLO 4\r
+#define SCIF_GCLK_NUM_MASTER 11\r
+#define SCIF_GCLK_NUM_PLL 9\r
+#define SCIF_GCLK_NUM_RC32KIFB_REF 5\r
+#define SCIF_GC_USES_CLK_CPU 7\r
+#define SCIF_GC_USES_CLK_HSB 8\r
+#define SCIF_GC_USES_CLK_PBA 9\r
+#define SCIF_GC_USES_CLK_PBB 10\r
+#define SCIF_GC_USES_CLK_PBC 11\r
+#define SCIF_GC_USES_CLK_PBD 12\r
+#define SCIF_GC_USES_CLK_SLOW 0\r
+#define SCIF_GC_USES_CLK_1K 15\r
+#define SCIF_GC_USES_CLK_32 1\r
+#define SCIF_GC_USES_DFLL0 2\r
+#define SCIF_GC_USES_FLO 14\r
+#define SCIF_GC_USES_GCLKPRESC_FP 18\r
+#define SCIF_GC_USES_GCLKPRESC_HRP 17\r
+#define SCIF_GC_USES_GCLK_IN0 19\r
+#define SCIF_GC_USES_GCLK_IN1 20\r
+#define SCIF_GC_USES_MASTER 21\r
+#define SCIF_GC_USES_OSC0 3\r
+#define SCIF_GC_USES_PLL0 16\r
+#define SCIF_GC_USES_RCFAST 5\r
+#define SCIF_GC_USES_RC1M 6\r
+#define SCIF_GC_USES_RC32K 13\r
+#define SCIF_GC_USES_RC80M 4\r
+#define SCIF_OSC_NUM 1\r
+#define SCIF_PLL_NUM 1\r
+#define SCIF_RCFAST_CALIBRATION_MSB 6\r
+#define SCIF_RCFAST_FRANGE_MSB 1\r
+#define SCIF_RC80M_CALIBRATION_MSB 1\r
+/* ========== Instance parameters for SPI peripheral ========== */\r
+#define SPI_CS_MSB 3\r
+#define SPI_PDCA_ID_RX 4\r
+#define SPI_PDCA_ID_TX 22\r
+/* ========== Instance parameters for TC0 peripheral ========== */\r
+#define TC0_CLK_DIV1 gen_clk_tc0\r
+#define TC0_CLK_DIV2 2\r
+#define TC0_CLK_DIV3 8\r
+#define TC0_CLK_DIV4 32\r
+#define TC0_CLK_DIV5 128\r
+#define TC0_GCLK_NUM 5\r
+/* ========== Instance parameters for TC1 peripheral ========== */\r
+#define TC1_CLK_DIV1 gen_clk_tc1\r
+#define TC1_CLK_DIV2 2\r
+#define TC1_CLK_DIV3 8\r
+#define TC1_CLK_DIV4 32\r
+#define TC1_CLK_DIV5 128\r
+#define TC1_GCLK_NUM 8\r
+/* ========== Instance parameters for TWIM0 peripheral ========== */\r
+#define TWIM0_PDCA_ID_RX 5\r
+#define TWIM0_PDCA_ID_TX 23\r
+/* ========== Instance parameters for TWIM1 peripheral ========== */\r
+#define TWIM1_PDCA_ID_RX 6\r
+#define TWIM1_PDCA_ID_TX 24\r
+/* ========== Instance parameters for TWIM2 peripheral ========== */\r
+#define TWIM2_PDCA_ID_RX 7\r
+#define TWIM2_PDCA_ID_TX 25\r
+/* ========== Instance parameters for TWIM3 peripheral ========== */\r
+#define TWIM3_PDCA_ID_RX 8\r
+#define TWIM3_PDCA_ID_TX 26\r
+/* ========== Instance parameters for TWIS0 peripheral ========== */\r
+#define TWIS0_PDCA_ID_RX 9\r
+#define TWIS0_PDCA_ID_TX 27\r
+/* ========== Instance parameters for TWIS1 peripheral ========== */\r
+#define TWIS1_PDCA_ID_RX 10\r
+#define TWIS1_PDCA_ID_TX 28\r
+/* ========== Instance parameters for USART0 peripheral ========== */\r
+#define USART0_CLK_DIV 8\r
+#define USART0_PDCA_ID_RX 0\r
+#define USART0_PDCA_ID_TX 18\r
+/* ========== Instance parameters for USART1 peripheral ========== */\r
+#define USART1_CLK_DIV 8\r
+#define USART1_PDCA_ID_RX 1\r
+#define USART1_PDCA_ID_TX 19\r
+/* ========== Instance parameters for USART2 peripheral ========== */\r
+#define USART2_CLK_DIV 8\r
+#define USART2_PDCA_ID_RX 2\r
+#define USART2_PDCA_ID_TX 20\r
+/* ========== Instance parameters for USART3 peripheral ========== */\r
+#define USART3_CLK_DIV 8\r
+#define USART3_PDCA_ID_RX 3\r
+#define USART3_PDCA_ID_TX 21\r
+/* ========== Instance parameters for USBC peripheral ========== */\r
+#define USBC_EPT_NBR 7\r
+#define USBC_GCLK_NUM 7\r
+#define USBC_HOST_IMPLEMENTED 1\r
+#define USBC_OTG_IMPLEMENTED \r
+#define USBC_USB_UTMI_IMPLEMENTED \r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** GPIO DEFINITIONS FOR SAM4L */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4L_gpio GPIO Definitions */\r
+/*@{*/\r
+\r
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */\r
+#define GPIO_PA00 (1u << 0) /**< \brief GPIO Mask for PA00 */\r
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */\r
+#define GPIO_PA01 (1u << 1) /**< \brief GPIO Mask for PA01 */\r
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */\r
+#define GPIO_PA02 (1u << 2) /**< \brief GPIO Mask for PA02 */\r
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */\r
+#define GPIO_PA03 (1u << 3) /**< \brief GPIO Mask for PA03 */\r
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */\r
+#define GPIO_PA04 (1u << 4) /**< \brief GPIO Mask for PA04 */\r
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */\r
+#define GPIO_PA05 (1u << 5) /**< \brief GPIO Mask for PA05 */\r
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */\r
+#define GPIO_PA06 (1u << 6) /**< \brief GPIO Mask for PA06 */\r
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */\r
+#define GPIO_PA07 (1u << 7) /**< \brief GPIO Mask for PA07 */\r
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */\r
+#define GPIO_PA08 (1u << 8) /**< \brief GPIO Mask for PA08 */\r
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */\r
+#define GPIO_PA09 (1u << 9) /**< \brief GPIO Mask for PA09 */\r
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */\r
+#define GPIO_PA10 (1u << 10) /**< \brief GPIO Mask for PA10 */\r
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */\r
+#define GPIO_PA11 (1u << 11) /**< \brief GPIO Mask for PA11 */\r
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */\r
+#define GPIO_PA12 (1u << 12) /**< \brief GPIO Mask for PA12 */\r
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */\r
+#define GPIO_PA13 (1u << 13) /**< \brief GPIO Mask for PA13 */\r
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */\r
+#define GPIO_PA14 (1u << 14) /**< \brief GPIO Mask for PA14 */\r
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */\r
+#define GPIO_PA15 (1u << 15) /**< \brief GPIO Mask for PA15 */\r
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */\r
+#define GPIO_PA16 (1u << 16) /**< \brief GPIO Mask for PA16 */\r
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */\r
+#define GPIO_PA17 (1u << 17) /**< \brief GPIO Mask for PA17 */\r
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */\r
+#define GPIO_PA18 (1u << 18) /**< \brief GPIO Mask for PA18 */\r
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */\r
+#define GPIO_PA19 (1u << 19) /**< \brief GPIO Mask for PA19 */\r
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */\r
+#define GPIO_PA20 (1u << 20) /**< \brief GPIO Mask for PA20 */\r
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */\r
+#define GPIO_PA21 (1u << 21) /**< \brief GPIO Mask for PA21 */\r
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */\r
+#define GPIO_PA22 (1u << 22) /**< \brief GPIO Mask for PA22 */\r
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */\r
+#define GPIO_PA23 (1u << 23) /**< \brief GPIO Mask for PA23 */\r
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */\r
+#define GPIO_PA24 (1u << 24) /**< \brief GPIO Mask for PA24 */\r
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */\r
+#define GPIO_PA25 (1u << 25) /**< \brief GPIO Mask for PA25 */\r
+#define PIN_PA26 26 /**< \brief Pin Number for PA26 */\r
+#define GPIO_PA26 (1u << 26) /**< \brief GPIO Mask for PA26 */\r
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */\r
+#define GPIO_PA27 (1u << 27) /**< \brief GPIO Mask for PA27 */\r
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */\r
+#define GPIO_PA28 (1u << 28) /**< \brief GPIO Mask for PA28 */\r
+#define PIN_PA29 29 /**< \brief Pin Number for PA29 */\r
+#define GPIO_PA29 (1u << 29) /**< \brief GPIO Mask for PA29 */\r
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */\r
+#define GPIO_PA30 (1u << 30) /**< \brief GPIO Mask for PA30 */\r
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */\r
+#define GPIO_PA31 (1u << 31) /**< \brief GPIO Mask for PA31 */\r
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */\r
+#define GPIO_PB00 (1u << 0) /**< \brief GPIO Mask for PB00 */\r
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */\r
+#define GPIO_PB01 (1u << 1) /**< \brief GPIO Mask for PB01 */\r
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */\r
+#define GPIO_PB02 (1u << 2) /**< \brief GPIO Mask for PB02 */\r
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */\r
+#define GPIO_PB03 (1u << 3) /**< \brief GPIO Mask for PB03 */\r
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */\r
+#define GPIO_PB04 (1u << 4) /**< \brief GPIO Mask for PB04 */\r
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */\r
+#define GPIO_PB05 (1u << 5) /**< \brief GPIO Mask for PB05 */\r
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */\r
+#define GPIO_PB06 (1u << 6) /**< \brief GPIO Mask for PB06 */\r
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */\r
+#define GPIO_PB07 (1u << 7) /**< \brief GPIO Mask for PB07 */\r
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */\r
+#define GPIO_PB08 (1u << 8) /**< \brief GPIO Mask for PB08 */\r
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */\r
+#define GPIO_PB09 (1u << 9) /**< \brief GPIO Mask for PB09 */\r
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */\r
+#define GPIO_PB10 (1u << 10) /**< \brief GPIO Mask for PB10 */\r
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */\r
+#define GPIO_PB11 (1u << 11) /**< \brief GPIO Mask for PB11 */\r
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */\r
+#define GPIO_PB12 (1u << 12) /**< \brief GPIO Mask for PB12 */\r
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */\r
+#define GPIO_PB13 (1u << 13) /**< \brief GPIO Mask for PB13 */\r
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */\r
+#define GPIO_PB14 (1u << 14) /**< \brief GPIO Mask for PB14 */\r
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */\r
+#define GPIO_PB15 (1u << 15) /**< \brief GPIO Mask for PB15 */\r
+#define PIN_PC00 64 /**< \brief Pin Number for PC00 */\r
+#define GPIO_PC00 (1u << 0) /**< \brief GPIO Mask for PC00 */\r
+#define PIN_PC01 65 /**< \brief Pin Number for PC01 */\r
+#define GPIO_PC01 (1u << 1) /**< \brief GPIO Mask for PC01 */\r
+#define PIN_PC02 66 /**< \brief Pin Number for PC02 */\r
+#define GPIO_PC02 (1u << 2) /**< \brief GPIO Mask for PC02 */\r
+#define PIN_PC03 67 /**< \brief Pin Number for PC03 */\r
+#define GPIO_PC03 (1u << 3) /**< \brief GPIO Mask for PC03 */\r
+#define PIN_PC04 68 /**< \brief Pin Number for PC04 */\r
+#define GPIO_PC04 (1u << 4) /**< \brief GPIO Mask for PC04 */\r
+#define PIN_PC05 69 /**< \brief Pin Number for PC05 */\r
+#define GPIO_PC05 (1u << 5) /**< \brief GPIO Mask for PC05 */\r
+#define PIN_PC06 70 /**< \brief Pin Number for PC06 */\r
+#define GPIO_PC06 (1u << 6) /**< \brief GPIO Mask for PC06 */\r
+#define PIN_PC07 71 /**< \brief Pin Number for PC07 */\r
+#define GPIO_PC07 (1u << 7) /**< \brief GPIO Mask for PC07 */\r
+#define PIN_PC08 72 /**< \brief Pin Number for PC08 */\r
+#define GPIO_PC08 (1u << 8) /**< \brief GPIO Mask for PC08 */\r
+#define PIN_PC09 73 /**< \brief Pin Number for PC09 */\r
+#define GPIO_PC09 (1u << 9) /**< \brief GPIO Mask for PC09 */\r
+#define PIN_PC10 74 /**< \brief Pin Number for PC10 */\r
+#define GPIO_PC10 (1u << 10) /**< \brief GPIO Mask for PC10 */\r
+#define PIN_PC11 75 /**< \brief Pin Number for PC11 */\r
+#define GPIO_PC11 (1u << 11) /**< \brief GPIO Mask for PC11 */\r
+#define PIN_PC12 76 /**< \brief Pin Number for PC12 */\r
+#define GPIO_PC12 (1u << 12) /**< \brief GPIO Mask for PC12 */\r
+#define PIN_PC13 77 /**< \brief Pin Number for PC13 */\r
+#define GPIO_PC13 (1u << 13) /**< \brief GPIO Mask for PC13 */\r
+#define PIN_PC14 78 /**< \brief Pin Number for PC14 */\r
+#define GPIO_PC14 (1u << 14) /**< \brief GPIO Mask for PC14 */\r
+#define PIN_PC15 79 /**< \brief Pin Number for PC15 */\r
+#define GPIO_PC15 (1u << 15) /**< \brief GPIO Mask for PC15 */\r
+#define PIN_PC16 80 /**< \brief Pin Number for PC16 */\r
+#define GPIO_PC16 (1u << 16) /**< \brief GPIO Mask for PC16 */\r
+#define PIN_PC17 81 /**< \brief Pin Number for PC17 */\r
+#define GPIO_PC17 (1u << 17) /**< \brief GPIO Mask for PC17 */\r
+#define PIN_PC18 82 /**< \brief Pin Number for PC18 */\r
+#define GPIO_PC18 (1u << 18) /**< \brief GPIO Mask for PC18 */\r
+#define PIN_PC19 83 /**< \brief Pin Number for PC19 */\r
+#define GPIO_PC19 (1u << 19) /**< \brief GPIO Mask for PC19 */\r
+#define PIN_PC20 84 /**< \brief Pin Number for PC20 */\r
+#define GPIO_PC20 (1u << 20) /**< \brief GPIO Mask for PC20 */\r
+#define PIN_PC21 85 /**< \brief Pin Number for PC21 */\r
+#define GPIO_PC21 (1u << 21) /**< \brief GPIO Mask for PC21 */\r
+#define PIN_PC22 86 /**< \brief Pin Number for PC22 */\r
+#define GPIO_PC22 (1u << 22) /**< \brief GPIO Mask for PC22 */\r
+#define PIN_PC23 87 /**< \brief Pin Number for PC23 */\r
+#define GPIO_PC23 (1u << 23) /**< \brief GPIO Mask for PC23 */\r
+#define PIN_PC24 88 /**< \brief Pin Number for PC24 */\r
+#define GPIO_PC24 (1u << 24) /**< \brief GPIO Mask for PC24 */\r
+#define PIN_PC25 89 /**< \brief Pin Number for PC25 */\r
+#define GPIO_PC25 (1u << 25) /**< \brief GPIO Mask for PC25 */\r
+#define PIN_PC26 90 /**< \brief Pin Number for PC26 */\r
+#define GPIO_PC26 (1u << 26) /**< \brief GPIO Mask for PC26 */\r
+#define PIN_PC27 91 /**< \brief Pin Number for PC27 */\r
+#define GPIO_PC27 (1u << 27) /**< \brief GPIO Mask for PC27 */\r
+#define PIN_PC28 92 /**< \brief Pin Number for PC28 */\r
+#define GPIO_PC28 (1u << 28) /**< \brief GPIO Mask for PC28 */\r
+#define PIN_PC29 93 /**< \brief Pin Number for PC29 */\r
+#define GPIO_PC29 (1u << 29) /**< \brief GPIO Mask for PC29 */\r
+#define PIN_PC30 94 /**< \brief Pin Number for PC30 */\r
+#define GPIO_PC30 (1u << 30) /**< \brief GPIO Mask for PC30 */\r
+#define PIN_PC31 95 /**< \brief Pin Number for PC31 */\r
+#define GPIO_PC31 (1u << 31) /**< \brief GPIO Mask for PC31 */\r
+/* ========== GPIO definition for ABDACB peripheral ========== */\r
+#define PIN_PA31C_ABDACB_CLK 31 /**< \brief ABDACB signal: CLK on PA31 mux C */\r
+#define MUX_PA31C_ABDACB_CLK 2\r
+#define GPIO_PA31C_ABDACB_CLK (1u << 31)\r
+#define PIN_PC12C_ABDACB_CLK 76 /**< \brief ABDACB signal: CLK on PC12 mux C */\r
+#define MUX_PC12C_ABDACB_CLK 2\r
+#define GPIO_PC12C_ABDACB_CLK (1u << 12)\r
+#define PIN_PA27C_ABDACB_DAC0 27 /**< \brief ABDACB signal: DAC0 on PA27 mux C */\r
+#define MUX_PA27C_ABDACB_DAC0 2\r
+#define GPIO_PA27C_ABDACB_DAC0 (1u << 27)\r
+#define PIN_PB02C_ABDACB_DAC0 34 /**< \brief ABDACB signal: DAC0 on PB02 mux C */\r
+#define MUX_PB02C_ABDACB_DAC0 2\r
+#define GPIO_PB02C_ABDACB_DAC0 (1u << 2)\r
+#define PIN_PC09C_ABDACB_DAC0 73 /**< \brief ABDACB signal: DAC0 on PC09 mux C */\r
+#define MUX_PC09C_ABDACB_DAC0 2\r
+#define GPIO_PC09C_ABDACB_DAC0 (1u << 9)\r
+#define PIN_PA17B_ABDACB_DAC0 17 /**< \brief ABDACB signal: DAC0 on PA17 mux B */\r
+#define MUX_PA17B_ABDACB_DAC0 1\r
+#define GPIO_PA17B_ABDACB_DAC0 (1u << 17)\r
+#define PIN_PA29C_ABDACB_DAC1 29 /**< \brief ABDACB signal: DAC1 on PA29 mux C */\r
+#define MUX_PA29C_ABDACB_DAC1 2\r
+#define GPIO_PA29C_ABDACB_DAC1 (1u << 29)\r
+#define PIN_PB04C_ABDACB_DAC1 36 /**< \brief ABDACB signal: DAC1 on PB04 mux C */\r
+#define MUX_PB04C_ABDACB_DAC1 2\r
+#define GPIO_PB04C_ABDACB_DAC1 (1u << 4)\r
+#define PIN_PC13C_ABDACB_DAC1 77 /**< \brief ABDACB signal: DAC1 on PC13 mux C */\r
+#define MUX_PC13C_ABDACB_DAC1 2\r
+#define GPIO_PC13C_ABDACB_DAC1 (1u << 13)\r
+#define PIN_PA19B_ABDACB_DAC1 19 /**< \brief ABDACB signal: DAC1 on PA19 mux B */\r
+#define MUX_PA19B_ABDACB_DAC1 1\r
+#define GPIO_PA19B_ABDACB_DAC1 (1u << 19)\r
+#define PIN_PA28C_ABDACB_DACN0 28 /**< \brief ABDACB signal: DACN0 on PA28 mux C */\r
+#define MUX_PA28C_ABDACB_DACN0 2\r
+#define GPIO_PA28C_ABDACB_DACN0 (1u << 28)\r
+#define PIN_PB03C_ABDACB_DACN0 35 /**< \brief ABDACB signal: DACN0 on PB03 mux C */\r
+#define MUX_PB03C_ABDACB_DACN0 2\r
+#define GPIO_PB03C_ABDACB_DACN0 (1u << 3)\r
+#define PIN_PC10C_ABDACB_DACN0 74 /**< \brief ABDACB signal: DACN0 on PC10 mux C */\r
+#define MUX_PC10C_ABDACB_DACN0 2\r
+#define GPIO_PC10C_ABDACB_DACN0 (1u << 10)\r
+#define PIN_PA18B_ABDACB_DACN0 18 /**< \brief ABDACB signal: DACN0 on PA18 mux B */\r
+#define MUX_PA18B_ABDACB_DACN0 1\r
+#define GPIO_PA18B_ABDACB_DACN0 (1u << 18)\r
+#define PIN_PA30C_ABDACB_DACN1 30 /**< \brief ABDACB signal: DACN1 on PA30 mux C */\r
+#define MUX_PA30C_ABDACB_DACN1 2\r
+#define GPIO_PA30C_ABDACB_DACN1 (1u << 30)\r
+#define PIN_PB05C_ABDACB_DACN1 37 /**< \brief ABDACB signal: DACN1 on PB05 mux C */\r
+#define MUX_PB05C_ABDACB_DACN1 2\r
+#define GPIO_PB05C_ABDACB_DACN1 (1u << 5)\r
+#define PIN_PC14C_ABDACB_DACN1 78 /**< \brief ABDACB signal: DACN1 on PC14 mux C */\r
+#define MUX_PC14C_ABDACB_DACN1 2\r
+#define GPIO_PC14C_ABDACB_DACN1 (1u << 14)\r
+#define PIN_PA20B_ABDACB_DACN1 20 /**< \brief ABDACB signal: DACN1 on PA20 mux B */\r
+#define MUX_PA20B_ABDACB_DACN1 1\r
+#define GPIO_PA20B_ABDACB_DACN1 (1u << 20)\r
+/* ========== GPIO definition for ACIFC peripheral ========== */\r
+#define PIN_PA06E_ACIFC_ACAN0 6 /**< \brief ACIFC signal: ACAN0 on PA06 mux E */\r
+#define MUX_PA06E_ACIFC_ACAN0 4\r
+#define GPIO_PA06E_ACIFC_ACAN0 (1u << 6)\r
+#define PIN_PC09E_ACIFC_ACAN1 73 /**< \brief ACIFC signal: ACAN1 on PC09 mux E */\r
+#define MUX_PC09E_ACIFC_ACAN1 4\r
+#define GPIO_PC09E_ACIFC_ACAN1 (1u << 9)\r
+#define PIN_PA07E_ACIFC_ACAP0 7 /**< \brief ACIFC signal: ACAP0 on PA07 mux E */\r
+#define MUX_PA07E_ACIFC_ACAP0 4\r
+#define GPIO_PA07E_ACIFC_ACAP0 (1u << 7)\r
+#define PIN_PC10E_ACIFC_ACAP1 74 /**< \brief ACIFC signal: ACAP1 on PC10 mux E */\r
+#define MUX_PC10E_ACIFC_ACAP1 4\r
+#define GPIO_PC10E_ACIFC_ACAP1 (1u << 10)\r
+#define PIN_PB02E_ACIFC_ACBN0 34 /**< \brief ACIFC signal: ACBN0 on PB02 mux E */\r
+#define MUX_PB02E_ACIFC_ACBN0 4\r
+#define GPIO_PB02E_ACIFC_ACBN0 (1u << 2)\r
+#define PIN_PC13E_ACIFC_ACBN1 77 /**< \brief ACIFC signal: ACBN1 on PC13 mux E */\r
+#define MUX_PC13E_ACIFC_ACBN1 4\r
+#define GPIO_PC13E_ACIFC_ACBN1 (1u << 13)\r
+#define PIN_PB03E_ACIFC_ACBP0 35 /**< \brief ACIFC signal: ACBP0 on PB03 mux E */\r
+#define MUX_PB03E_ACIFC_ACBP0 4\r
+#define GPIO_PB03E_ACIFC_ACBP0 (1u << 3)\r
+#define PIN_PC14E_ACIFC_ACBP1 78 /**< \brief ACIFC signal: ACBP1 on PC14 mux E */\r
+#define MUX_PC14E_ACIFC_ACBP1 4\r
+#define GPIO_PC14E_ACIFC_ACBP1 (1u << 14)\r
+/* ========== GPIO definition for ADCIFE peripheral ========== */\r
+#define PIN_PA04A_ADCIFE_AD0 4 /**< \brief ADCIFE signal: AD0 on PA04 mux A */\r
+#define MUX_PA04A_ADCIFE_AD0 0\r
+#define GPIO_PA04A_ADCIFE_AD0 (1u << 4)\r
+#define PIN_PA05A_ADCIFE_AD1 5 /**< \brief ADCIFE signal: AD1 on PA05 mux A */\r
+#define MUX_PA05A_ADCIFE_AD1 0\r
+#define GPIO_PA05A_ADCIFE_AD1 (1u << 5)\r
+#define PIN_PA07A_ADCIFE_AD2 7 /**< \brief ADCIFE signal: AD2 on PA07 mux A */\r
+#define MUX_PA07A_ADCIFE_AD2 0\r
+#define GPIO_PA07A_ADCIFE_AD2 (1u << 7)\r
+#define PIN_PB02A_ADCIFE_AD3 34 /**< \brief ADCIFE signal: AD3 on PB02 mux A */\r
+#define MUX_PB02A_ADCIFE_AD3 0\r
+#define GPIO_PB02A_ADCIFE_AD3 (1u << 2)\r
+#define PIN_PB03A_ADCIFE_AD4 35 /**< \brief ADCIFE signal: AD4 on PB03 mux A */\r
+#define MUX_PB03A_ADCIFE_AD4 0\r
+#define GPIO_PB03A_ADCIFE_AD4 (1u << 3)\r
+#define PIN_PB04A_ADCIFE_AD5 36 /**< \brief ADCIFE signal: AD5 on PB04 mux A */\r
+#define MUX_PB04A_ADCIFE_AD5 0\r
+#define GPIO_PB04A_ADCIFE_AD5 (1u << 4)\r
+#define PIN_PB05A_ADCIFE_AD6 37 /**< \brief ADCIFE signal: AD6 on PB05 mux A */\r
+#define MUX_PB05A_ADCIFE_AD6 0\r
+#define GPIO_PB05A_ADCIFE_AD6 (1u << 5)\r
+#define PIN_PC07A_ADCIFE_AD7 71 /**< \brief ADCIFE signal: AD7 on PC07 mux A */\r
+#define MUX_PC07A_ADCIFE_AD7 0\r
+#define GPIO_PC07A_ADCIFE_AD7 (1u << 7)\r
+#define PIN_PC08A_ADCIFE_AD8 72 /**< \brief ADCIFE signal: AD8 on PC08 mux A */\r
+#define MUX_PC08A_ADCIFE_AD8 0\r
+#define GPIO_PC08A_ADCIFE_AD8 (1u << 8)\r
+#define PIN_PC09A_ADCIFE_AD9 73 /**< \brief ADCIFE signal: AD9 on PC09 mux A */\r
+#define MUX_PC09A_ADCIFE_AD9 0\r
+#define GPIO_PC09A_ADCIFE_AD9 (1u << 9)\r
+#define PIN_PC10A_ADCIFE_AD10 74 /**< \brief ADCIFE signal: AD10 on PC10 mux A */\r
+#define MUX_PC10A_ADCIFE_AD10 0\r
+#define GPIO_PC10A_ADCIFE_AD10 (1u << 10)\r
+#define PIN_PC11A_ADCIFE_AD11 75 /**< \brief ADCIFE signal: AD11 on PC11 mux A */\r
+#define MUX_PC11A_ADCIFE_AD11 0\r
+#define GPIO_PC11A_ADCIFE_AD11 (1u << 11)\r
+#define PIN_PC12A_ADCIFE_AD12 76 /**< \brief ADCIFE signal: AD12 on PC12 mux A */\r
+#define MUX_PC12A_ADCIFE_AD12 0\r
+#define GPIO_PC12A_ADCIFE_AD12 (1u << 12)\r
+#define PIN_PC13A_ADCIFE_AD13 77 /**< \brief ADCIFE signal: AD13 on PC13 mux A */\r
+#define MUX_PC13A_ADCIFE_AD13 0\r
+#define GPIO_PC13A_ADCIFE_AD13 (1u << 13)\r
+#define PIN_PC14A_ADCIFE_AD14 78 /**< \brief ADCIFE signal: AD14 on PC14 mux A */\r
+#define MUX_PC14A_ADCIFE_AD14 0\r
+#define GPIO_PC14A_ADCIFE_AD14 (1u << 14)\r
+#define PIN_PA05E_ADCIFE_TRIGGER 5 /**< \brief ADCIFE signal: TRIGGER on PA05 mux E */\r
+#define MUX_PA05E_ADCIFE_TRIGGER 4\r
+#define GPIO_PA05E_ADCIFE_TRIGGER (1u << 5)\r
+/* ========== GPIO definition for CATB peripheral ========== */\r
+#define PIN_PA02G_CATB_DIS 2 /**< \brief CATB signal: DIS on PA02 mux G */\r
+#define MUX_PA02G_CATB_DIS 6\r
+#define GPIO_PA02G_CATB_DIS (1u << 2)\r
+#define PIN_PA12G_CATB_DIS 12 /**< \brief CATB signal: DIS on PA12 mux G */\r
+#define MUX_PA12G_CATB_DIS 6\r
+#define GPIO_PA12G_CATB_DIS (1u << 12)\r
+#define PIN_PA23G_CATB_DIS 23 /**< \brief CATB signal: DIS on PA23 mux G */\r
+#define MUX_PA23G_CATB_DIS 6\r
+#define GPIO_PA23G_CATB_DIS (1u << 23)\r
+#define PIN_PA31G_CATB_DIS 31 /**< \brief CATB signal: DIS on PA31 mux G */\r
+#define MUX_PA31G_CATB_DIS 6\r
+#define GPIO_PA31G_CATB_DIS (1u << 31)\r
+#define PIN_PB03G_CATB_DIS 35 /**< \brief CATB signal: DIS on PB03 mux G */\r
+#define MUX_PB03G_CATB_DIS 6\r
+#define GPIO_PB03G_CATB_DIS (1u << 3)\r
+#define PIN_PB12G_CATB_DIS 44 /**< \brief CATB signal: DIS on PB12 mux G */\r
+#define MUX_PB12G_CATB_DIS 6\r
+#define GPIO_PB12G_CATB_DIS (1u << 12)\r
+#define PIN_PC05G_CATB_DIS 69 /**< \brief CATB signal: DIS on PC05 mux G */\r
+#define MUX_PC05G_CATB_DIS 6\r
+#define GPIO_PC05G_CATB_DIS (1u << 5)\r
+#define PIN_PC14G_CATB_DIS 78 /**< \brief CATB signal: DIS on PC14 mux G */\r
+#define MUX_PC14G_CATB_DIS 6\r
+#define GPIO_PC14G_CATB_DIS (1u << 14)\r
+#define PIN_PC23G_CATB_DIS 87 /**< \brief CATB signal: DIS on PC23 mux G */\r
+#define MUX_PC23G_CATB_DIS 6\r
+#define GPIO_PC23G_CATB_DIS (1u << 23)\r
+#define PIN_PA04G_CATB_SENSE0 4 /**< \brief CATB signal: SENSE0 on PA04 mux G */\r
+#define MUX_PA04G_CATB_SENSE0 6\r
+#define GPIO_PA04G_CATB_SENSE0 (1u << 4)\r
+#define PIN_PA27G_CATB_SENSE0 27 /**< \brief CATB signal: SENSE0 on PA27 mux G */\r
+#define MUX_PA27G_CATB_SENSE0 6\r
+#define GPIO_PA27G_CATB_SENSE0 (1u << 27)\r
+#define PIN_PB13G_CATB_SENSE0 45 /**< \brief CATB signal: SENSE0 on PB13 mux G */\r
+#define MUX_PB13G_CATB_SENSE0 6\r
+#define GPIO_PB13G_CATB_SENSE0 (1u << 13)\r
+#define PIN_PA05G_CATB_SENSE1 5 /**< \brief CATB signal: SENSE1 on PA05 mux G */\r
+#define MUX_PA05G_CATB_SENSE1 6\r
+#define GPIO_PA05G_CATB_SENSE1 (1u << 5)\r
+#define PIN_PA28G_CATB_SENSE1 28 /**< \brief CATB signal: SENSE1 on PA28 mux G */\r
+#define MUX_PA28G_CATB_SENSE1 6\r
+#define GPIO_PA28G_CATB_SENSE1 (1u << 28)\r
+#define PIN_PB14G_CATB_SENSE1 46 /**< \brief CATB signal: SENSE1 on PB14 mux G */\r
+#define MUX_PB14G_CATB_SENSE1 6\r
+#define GPIO_PB14G_CATB_SENSE1 (1u << 14)\r
+#define PIN_PA06G_CATB_SENSE2 6 /**< \brief CATB signal: SENSE2 on PA06 mux G */\r
+#define MUX_PA06G_CATB_SENSE2 6\r
+#define GPIO_PA06G_CATB_SENSE2 (1u << 6)\r
+#define PIN_PA29G_CATB_SENSE2 29 /**< \brief CATB signal: SENSE2 on PA29 mux G */\r
+#define MUX_PA29G_CATB_SENSE2 6\r
+#define GPIO_PA29G_CATB_SENSE2 (1u << 29)\r
+#define PIN_PB15G_CATB_SENSE2 47 /**< \brief CATB signal: SENSE2 on PB15 mux G */\r
+#define MUX_PB15G_CATB_SENSE2 6\r
+#define GPIO_PB15G_CATB_SENSE2 (1u << 15)\r
+#define PIN_PA07G_CATB_SENSE3 7 /**< \brief CATB signal: SENSE3 on PA07 mux G */\r
+#define MUX_PA07G_CATB_SENSE3 6\r
+#define GPIO_PA07G_CATB_SENSE3 (1u << 7)\r
+#define PIN_PA30G_CATB_SENSE3 30 /**< \brief CATB signal: SENSE3 on PA30 mux G */\r
+#define MUX_PA30G_CATB_SENSE3 6\r
+#define GPIO_PA30G_CATB_SENSE3 (1u << 30)\r
+#define PIN_PC00G_CATB_SENSE3 64 /**< \brief CATB signal: SENSE3 on PC00 mux G */\r
+#define MUX_PC00G_CATB_SENSE3 6\r
+#define GPIO_PC00G_CATB_SENSE3 (1u << 0)\r
+#define PIN_PA08G_CATB_SENSE4 8 /**< \brief CATB signal: SENSE4 on PA08 mux G */\r
+#define MUX_PA08G_CATB_SENSE4 6\r
+#define GPIO_PA08G_CATB_SENSE4 (1u << 8)\r
+#define PIN_PC01G_CATB_SENSE4 65 /**< \brief CATB signal: SENSE4 on PC01 mux G */\r
+#define MUX_PC01G_CATB_SENSE4 6\r
+#define GPIO_PC01G_CATB_SENSE4 (1u << 1)\r
+#define PIN_PA09G_CATB_SENSE5 9 /**< \brief CATB signal: SENSE5 on PA09 mux G */\r
+#define MUX_PA09G_CATB_SENSE5 6\r
+#define GPIO_PA09G_CATB_SENSE5 (1u << 9)\r
+#define PIN_PC02G_CATB_SENSE5 66 /**< \brief CATB signal: SENSE5 on PC02 mux G */\r
+#define MUX_PC02G_CATB_SENSE5 6\r
+#define GPIO_PC02G_CATB_SENSE5 (1u << 2)\r
+#define PIN_PA10G_CATB_SENSE6 10 /**< \brief CATB signal: SENSE6 on PA10 mux G */\r
+#define MUX_PA10G_CATB_SENSE6 6\r
+#define GPIO_PA10G_CATB_SENSE6 (1u << 10)\r
+#define PIN_PC03G_CATB_SENSE6 67 /**< \brief CATB signal: SENSE6 on PC03 mux G */\r
+#define MUX_PC03G_CATB_SENSE6 6\r
+#define GPIO_PC03G_CATB_SENSE6 (1u << 3)\r
+#define PIN_PA11G_CATB_SENSE7 11 /**< \brief CATB signal: SENSE7 on PA11 mux G */\r
+#define MUX_PA11G_CATB_SENSE7 6\r
+#define GPIO_PA11G_CATB_SENSE7 (1u << 11)\r
+#define PIN_PC04G_CATB_SENSE7 68 /**< \brief CATB signal: SENSE7 on PC04 mux G */\r
+#define MUX_PC04G_CATB_SENSE7 6\r
+#define GPIO_PC04G_CATB_SENSE7 (1u << 4)\r
+#define PIN_PA13G_CATB_SENSE8 13 /**< \brief CATB signal: SENSE8 on PA13 mux G */\r
+#define MUX_PA13G_CATB_SENSE8 6\r
+#define GPIO_PA13G_CATB_SENSE8 (1u << 13)\r
+#define PIN_PC06G_CATB_SENSE8 70 /**< \brief CATB signal: SENSE8 on PC06 mux G */\r
+#define MUX_PC06G_CATB_SENSE8 6\r
+#define GPIO_PC06G_CATB_SENSE8 (1u << 6)\r
+#define PIN_PA14G_CATB_SENSE9 14 /**< \brief CATB signal: SENSE9 on PA14 mux G */\r
+#define MUX_PA14G_CATB_SENSE9 6\r
+#define GPIO_PA14G_CATB_SENSE9 (1u << 14)\r
+#define PIN_PC07G_CATB_SENSE9 71 /**< \brief CATB signal: SENSE9 on PC07 mux G */\r
+#define MUX_PC07G_CATB_SENSE9 6\r
+#define GPIO_PC07G_CATB_SENSE9 (1u << 7)\r
+#define PIN_PA15G_CATB_SENSE10 15 /**< \brief CATB signal: SENSE10 on PA15 mux G */\r
+#define MUX_PA15G_CATB_SENSE10 6\r
+#define GPIO_PA15G_CATB_SENSE10 (1u << 15)\r
+#define PIN_PC08G_CATB_SENSE10 72 /**< \brief CATB signal: SENSE10 on PC08 mux G */\r
+#define MUX_PC08G_CATB_SENSE10 6\r
+#define GPIO_PC08G_CATB_SENSE10 (1u << 8)\r
+#define PIN_PA16G_CATB_SENSE11 16 /**< \brief CATB signal: SENSE11 on PA16 mux G */\r
+#define MUX_PA16G_CATB_SENSE11 6\r
+#define GPIO_PA16G_CATB_SENSE11 (1u << 16)\r
+#define PIN_PC09G_CATB_SENSE11 73 /**< \brief CATB signal: SENSE11 on PC09 mux G */\r
+#define MUX_PC09G_CATB_SENSE11 6\r
+#define GPIO_PC09G_CATB_SENSE11 (1u << 9)\r
+#define PIN_PA17G_CATB_SENSE12 17 /**< \brief CATB signal: SENSE12 on PA17 mux G */\r
+#define MUX_PA17G_CATB_SENSE12 6\r
+#define GPIO_PA17G_CATB_SENSE12 (1u << 17)\r
+#define PIN_PC10G_CATB_SENSE12 74 /**< \brief CATB signal: SENSE12 on PC10 mux G */\r
+#define MUX_PC10G_CATB_SENSE12 6\r
+#define GPIO_PC10G_CATB_SENSE12 (1u << 10)\r
+#define PIN_PA18G_CATB_SENSE13 18 /**< \brief CATB signal: SENSE13 on PA18 mux G */\r
+#define MUX_PA18G_CATB_SENSE13 6\r
+#define GPIO_PA18G_CATB_SENSE13 (1u << 18)\r
+#define PIN_PC11G_CATB_SENSE13 75 /**< \brief CATB signal: SENSE13 on PC11 mux G */\r
+#define MUX_PC11G_CATB_SENSE13 6\r
+#define GPIO_PC11G_CATB_SENSE13 (1u << 11)\r
+#define PIN_PA19G_CATB_SENSE14 19 /**< \brief CATB signal: SENSE14 on PA19 mux G */\r
+#define MUX_PA19G_CATB_SENSE14 6\r
+#define GPIO_PA19G_CATB_SENSE14 (1u << 19)\r
+#define PIN_PC12G_CATB_SENSE14 76 /**< \brief CATB signal: SENSE14 on PC12 mux G */\r
+#define MUX_PC12G_CATB_SENSE14 6\r
+#define GPIO_PC12G_CATB_SENSE14 (1u << 12)\r
+#define PIN_PA20G_CATB_SENSE15 20 /**< \brief CATB signal: SENSE15 on PA20 mux G */\r
+#define MUX_PA20G_CATB_SENSE15 6\r
+#define GPIO_PA20G_CATB_SENSE15 (1u << 20)\r
+#define PIN_PC13G_CATB_SENSE15 77 /**< \brief CATB signal: SENSE15 on PC13 mux G */\r
+#define MUX_PC13G_CATB_SENSE15 6\r
+#define GPIO_PC13G_CATB_SENSE15 (1u << 13)\r
+#define PIN_PA21G_CATB_SENSE16 21 /**< \brief CATB signal: SENSE16 on PA21 mux G */\r
+#define MUX_PA21G_CATB_SENSE16 6\r
+#define GPIO_PA21G_CATB_SENSE16 (1u << 21)\r
+#define PIN_PC15G_CATB_SENSE16 79 /**< \brief CATB signal: SENSE16 on PC15 mux G */\r
+#define MUX_PC15G_CATB_SENSE16 6\r
+#define GPIO_PC15G_CATB_SENSE16 (1u << 15)\r
+#define PIN_PA22G_CATB_SENSE17 22 /**< \brief CATB signal: SENSE17 on PA22 mux G */\r
+#define MUX_PA22G_CATB_SENSE17 6\r
+#define GPIO_PA22G_CATB_SENSE17 (1u << 22)\r
+#define PIN_PC16G_CATB_SENSE17 80 /**< \brief CATB signal: SENSE17 on PC16 mux G */\r
+#define MUX_PC16G_CATB_SENSE17 6\r
+#define GPIO_PC16G_CATB_SENSE17 (1u << 16)\r
+#define PIN_PA24G_CATB_SENSE18 24 /**< \brief CATB signal: SENSE18 on PA24 mux G */\r
+#define MUX_PA24G_CATB_SENSE18 6\r
+#define GPIO_PA24G_CATB_SENSE18 (1u << 24)\r
+#define PIN_PC17G_CATB_SENSE18 81 /**< \brief CATB signal: SENSE18 on PC17 mux G */\r
+#define MUX_PC17G_CATB_SENSE18 6\r
+#define GPIO_PC17G_CATB_SENSE18 (1u << 17)\r
+#define PIN_PA25G_CATB_SENSE19 25 /**< \brief CATB signal: SENSE19 on PA25 mux G */\r
+#define MUX_PA25G_CATB_SENSE19 6\r
+#define GPIO_PA25G_CATB_SENSE19 (1u << 25)\r
+#define PIN_PC18G_CATB_SENSE19 82 /**< \brief CATB signal: SENSE19 on PC18 mux G */\r
+#define MUX_PC18G_CATB_SENSE19 6\r
+#define GPIO_PC18G_CATB_SENSE19 (1u << 18)\r
+#define PIN_PA26G_CATB_SENSE20 26 /**< \brief CATB signal: SENSE20 on PA26 mux G */\r
+#define MUX_PA26G_CATB_SENSE20 6\r
+#define GPIO_PA26G_CATB_SENSE20 (1u << 26)\r
+#define PIN_PC19G_CATB_SENSE20 83 /**< \brief CATB signal: SENSE20 on PC19 mux G */\r
+#define MUX_PC19G_CATB_SENSE20 6\r
+#define GPIO_PC19G_CATB_SENSE20 (1u << 19)\r
+#define PIN_PB00G_CATB_SENSE21 32 /**< \brief CATB signal: SENSE21 on PB00 mux G */\r
+#define MUX_PB00G_CATB_SENSE21 6\r
+#define GPIO_PB00G_CATB_SENSE21 (1u << 0)\r
+#define PIN_PC20G_CATB_SENSE21 84 /**< \brief CATB signal: SENSE21 on PC20 mux G */\r
+#define MUX_PC20G_CATB_SENSE21 6\r
+#define GPIO_PC20G_CATB_SENSE21 (1u << 20)\r
+#define PIN_PB01G_CATB_SENSE22 33 /**< \brief CATB signal: SENSE22 on PB01 mux G */\r
+#define MUX_PB01G_CATB_SENSE22 6\r
+#define GPIO_PB01G_CATB_SENSE22 (1u << 1)\r
+#define PIN_PC21G_CATB_SENSE22 85 /**< \brief CATB signal: SENSE22 on PC21 mux G */\r
+#define MUX_PC21G_CATB_SENSE22 6\r
+#define GPIO_PC21G_CATB_SENSE22 (1u << 21)\r
+#define PIN_PB02G_CATB_SENSE23 34 /**< \brief CATB signal: SENSE23 on PB02 mux G */\r
+#define MUX_PB02G_CATB_SENSE23 6\r
+#define GPIO_PB02G_CATB_SENSE23 (1u << 2)\r
+#define PIN_PC22G_CATB_SENSE23 86 /**< \brief CATB signal: SENSE23 on PC22 mux G */\r
+#define MUX_PC22G_CATB_SENSE23 6\r
+#define GPIO_PC22G_CATB_SENSE23 (1u << 22)\r
+#define PIN_PB04G_CATB_SENSE24 36 /**< \brief CATB signal: SENSE24 on PB04 mux G */\r
+#define MUX_PB04G_CATB_SENSE24 6\r
+#define GPIO_PB04G_CATB_SENSE24 (1u << 4)\r
+#define PIN_PC24G_CATB_SENSE24 88 /**< \brief CATB signal: SENSE24 on PC24 mux G */\r
+#define MUX_PC24G_CATB_SENSE24 6\r
+#define GPIO_PC24G_CATB_SENSE24 (1u << 24)\r
+#define PIN_PB05G_CATB_SENSE25 37 /**< \brief CATB signal: SENSE25 on PB05 mux G */\r
+#define MUX_PB05G_CATB_SENSE25 6\r
+#define GPIO_PB05G_CATB_SENSE25 (1u << 5)\r
+#define PIN_PC25G_CATB_SENSE25 89 /**< \brief CATB signal: SENSE25 on PC25 mux G */\r
+#define MUX_PC25G_CATB_SENSE25 6\r
+#define GPIO_PC25G_CATB_SENSE25 (1u << 25)\r
+#define PIN_PB06G_CATB_SENSE26 38 /**< \brief CATB signal: SENSE26 on PB06 mux G */\r
+#define MUX_PB06G_CATB_SENSE26 6\r
+#define GPIO_PB06G_CATB_SENSE26 (1u << 6)\r
+#define PIN_PC26G_CATB_SENSE26 90 /**< \brief CATB signal: SENSE26 on PC26 mux G */\r
+#define MUX_PC26G_CATB_SENSE26 6\r
+#define GPIO_PC26G_CATB_SENSE26 (1u << 26)\r
+#define PIN_PB07G_CATB_SENSE27 39 /**< \brief CATB signal: SENSE27 on PB07 mux G */\r
+#define MUX_PB07G_CATB_SENSE27 6\r
+#define GPIO_PB07G_CATB_SENSE27 (1u << 7)\r
+#define PIN_PC27G_CATB_SENSE27 91 /**< \brief CATB signal: SENSE27 on PC27 mux G */\r
+#define MUX_PC27G_CATB_SENSE27 6\r
+#define GPIO_PC27G_CATB_SENSE27 (1u << 27)\r
+#define PIN_PB08G_CATB_SENSE28 40 /**< \brief CATB signal: SENSE28 on PB08 mux G */\r
+#define MUX_PB08G_CATB_SENSE28 6\r
+#define GPIO_PB08G_CATB_SENSE28 (1u << 8)\r
+#define PIN_PC28G_CATB_SENSE28 92 /**< \brief CATB signal: SENSE28 on PC28 mux G */\r
+#define MUX_PC28G_CATB_SENSE28 6\r
+#define GPIO_PC28G_CATB_SENSE28 (1u << 28)\r
+#define PIN_PB09G_CATB_SENSE29 41 /**< \brief CATB signal: SENSE29 on PB09 mux G */\r
+#define MUX_PB09G_CATB_SENSE29 6\r
+#define GPIO_PB09G_CATB_SENSE29 (1u << 9)\r
+#define PIN_PC29G_CATB_SENSE29 93 /**< \brief CATB signal: SENSE29 on PC29 mux G */\r
+#define MUX_PC29G_CATB_SENSE29 6\r
+#define GPIO_PC29G_CATB_SENSE29 (1u << 29)\r
+#define PIN_PB10G_CATB_SENSE30 42 /**< \brief CATB signal: SENSE30 on PB10 mux G */\r
+#define MUX_PB10G_CATB_SENSE30 6\r
+#define GPIO_PB10G_CATB_SENSE30 (1u << 10)\r
+#define PIN_PC30G_CATB_SENSE30 94 /**< \brief CATB signal: SENSE30 on PC30 mux G */\r
+#define MUX_PC30G_CATB_SENSE30 6\r
+#define GPIO_PC30G_CATB_SENSE30 (1u << 30)\r
+#define PIN_PB11G_CATB_SENSE31 43 /**< \brief CATB signal: SENSE31 on PB11 mux G */\r
+#define MUX_PB11G_CATB_SENSE31 6\r
+#define GPIO_PB11G_CATB_SENSE31 (1u << 11)\r
+#define PIN_PC31G_CATB_SENSE31 95 /**< \brief CATB signal: SENSE31 on PC31 mux G */\r
+#define MUX_PC31G_CATB_SENSE31 6\r
+#define GPIO_PC31G_CATB_SENSE31 (1u << 31)\r
+/* ========== GPIO definition for DACC peripheral ========== */\r
+#define PIN_PB04E_DACC_EXT_TRIG0 36 /**< \brief DACC signal: EXT_TRIG0 on PB04 mux E */\r
+#define MUX_PB04E_DACC_EXT_TRIG0 4\r
+#define GPIO_PB04E_DACC_EXT_TRIG0 (1u << 4)\r
+#define PIN_PA06A_DACC_VOUT 6 /**< \brief DACC signal: VOUT on PA06 mux A */\r
+#define MUX_PA06A_DACC_VOUT 0\r
+#define GPIO_PA06A_DACC_VOUT (1u << 6)\r
+/* ========== GPIO definition for EIC peripheral ========== */\r
+#define PIN_PB01C_EIC_EXTINT0 33 /**< \brief EIC signal: EXTINT0 on PB01 mux C */\r
+#define MUX_PB01C_EIC_EXTINT0 2\r
+#define GPIO_PB01C_EIC_EXTINT0 (1u << 1)\r
+#define PIN_PA06C_EIC_EXTINT1 6 /**< \brief EIC signal: EXTINT1 on PA06 mux C */\r
+#define MUX_PA06C_EIC_EXTINT1 2\r
+#define GPIO_PA06C_EIC_EXTINT1 (1u << 6)\r
+#define PIN_PA16C_EIC_EXTINT1 16 /**< \brief EIC signal: EXTINT1 on PA16 mux C */\r
+#define MUX_PA16C_EIC_EXTINT1 2\r
+#define GPIO_PA16C_EIC_EXTINT1 (1u << 16)\r
+#define PIN_PC24B_EIC_EXTINT1 88 /**< \brief EIC signal: EXTINT1 on PC24 mux B */\r
+#define MUX_PC24B_EIC_EXTINT1 1\r
+#define GPIO_PC24B_EIC_EXTINT1 (1u << 24)\r
+#define PIN_PA04C_EIC_EXTINT2 4 /**< \brief EIC signal: EXTINT2 on PA04 mux C */\r
+#define MUX_PA04C_EIC_EXTINT2 2\r
+#define GPIO_PA04C_EIC_EXTINT2 (1u << 4)\r
+#define PIN_PA17C_EIC_EXTINT2 17 /**< \brief EIC signal: EXTINT2 on PA17 mux C */\r
+#define MUX_PA17C_EIC_EXTINT2 2\r
+#define GPIO_PA17C_EIC_EXTINT2 (1u << 17)\r
+#define PIN_PC25B_EIC_EXTINT2 89 /**< \brief EIC signal: EXTINT2 on PC25 mux B */\r
+#define MUX_PC25B_EIC_EXTINT2 1\r
+#define GPIO_PC25B_EIC_EXTINT2 (1u << 25)\r
+#define PIN_PA05C_EIC_EXTINT3 5 /**< \brief EIC signal: EXTINT3 on PA05 mux C */\r
+#define MUX_PA05C_EIC_EXTINT3 2\r
+#define GPIO_PA05C_EIC_EXTINT3 (1u << 5)\r
+#define PIN_PA18C_EIC_EXTINT3 18 /**< \brief EIC signal: EXTINT3 on PA18 mux C */\r
+#define MUX_PA18C_EIC_EXTINT3 2\r
+#define GPIO_PA18C_EIC_EXTINT3 (1u << 18)\r
+#define PIN_PC26B_EIC_EXTINT3 90 /**< \brief EIC signal: EXTINT3 on PC26 mux B */\r
+#define MUX_PC26B_EIC_EXTINT3 1\r
+#define GPIO_PC26B_EIC_EXTINT3 (1u << 26)\r
+#define PIN_PA07C_EIC_EXTINT4 7 /**< \brief EIC signal: EXTINT4 on PA07 mux C */\r
+#define MUX_PA07C_EIC_EXTINT4 2\r
+#define GPIO_PA07C_EIC_EXTINT4 (1u << 7)\r
+#define PIN_PA19C_EIC_EXTINT4 19 /**< \brief EIC signal: EXTINT4 on PA19 mux C */\r
+#define MUX_PA19C_EIC_EXTINT4 2\r
+#define GPIO_PA19C_EIC_EXTINT4 (1u << 19)\r
+#define PIN_PC27B_EIC_EXTINT4 91 /**< \brief EIC signal: EXTINT4 on PC27 mux B */\r
+#define MUX_PC27B_EIC_EXTINT4 1\r
+#define GPIO_PC27B_EIC_EXTINT4 (1u << 27)\r
+#define PIN_PA20C_EIC_EXTINT5 20 /**< \brief EIC signal: EXTINT5 on PA20 mux C */\r
+#define MUX_PA20C_EIC_EXTINT5 2\r
+#define GPIO_PA20C_EIC_EXTINT5 (1u << 20)\r
+#define PIN_PC03B_EIC_EXTINT5 67 /**< \brief EIC signal: EXTINT5 on PC03 mux B */\r
+#define MUX_PC03B_EIC_EXTINT5 1\r
+#define GPIO_PC03B_EIC_EXTINT5 (1u << 3)\r
+#define PIN_PA21C_EIC_EXTINT6 21 /**< \brief EIC signal: EXTINT6 on PA21 mux C */\r
+#define MUX_PA21C_EIC_EXTINT6 2\r
+#define GPIO_PA21C_EIC_EXTINT6 (1u << 21)\r
+#define PIN_PC04B_EIC_EXTINT6 68 /**< \brief EIC signal: EXTINT6 on PC04 mux B */\r
+#define MUX_PC04B_EIC_EXTINT6 1\r
+#define GPIO_PC04B_EIC_EXTINT6 (1u << 4)\r
+#define PIN_PA22C_EIC_EXTINT7 22 /**< \brief EIC signal: EXTINT7 on PA22 mux C */\r
+#define MUX_PA22C_EIC_EXTINT7 2\r
+#define GPIO_PA22C_EIC_EXTINT7 (1u << 22)\r
+#define PIN_PC05B_EIC_EXTINT7 69 /**< \brief EIC signal: EXTINT7 on PC05 mux B */\r
+#define MUX_PC05B_EIC_EXTINT7 1\r
+#define GPIO_PC05B_EIC_EXTINT7 (1u << 5)\r
+#define PIN_PA23C_EIC_EXTINT8 23 /**< \brief EIC signal: EXTINT8 on PA23 mux C */\r
+#define MUX_PA23C_EIC_EXTINT8 2\r
+#define GPIO_PA23C_EIC_EXTINT8 (1u << 23)\r
+#define PIN_PC06B_EIC_EXTINT8 70 /**< \brief EIC signal: EXTINT8 on PC06 mux B */\r
+#define MUX_PC06B_EIC_EXTINT8 1\r
+#define GPIO_PC06B_EIC_EXTINT8 (1u << 6)\r
+/* ========== GPIO definition for GLOC peripheral ========== */\r
+#define PIN_PA06D_GLOC_IN0 6 /**< \brief GLOC signal: IN0 on PA06 mux D */\r
+#define MUX_PA06D_GLOC_IN0 3\r
+#define GPIO_PA06D_GLOC_IN0 (1u << 6)\r
+#define PIN_PA20D_GLOC_IN0 20 /**< \brief GLOC signal: IN0 on PA20 mux D */\r
+#define MUX_PA20D_GLOC_IN0 3\r
+#define GPIO_PA20D_GLOC_IN0 (1u << 20)\r
+#define PIN_PA04D_GLOC_IN1 4 /**< \brief GLOC signal: IN1 on PA04 mux D */\r
+#define MUX_PA04D_GLOC_IN1 3\r
+#define GPIO_PA04D_GLOC_IN1 (1u << 4)\r
+#define PIN_PA21D_GLOC_IN1 21 /**< \brief GLOC signal: IN1 on PA21 mux D */\r
+#define MUX_PA21D_GLOC_IN1 3\r
+#define GPIO_PA21D_GLOC_IN1 (1u << 21)\r
+#define PIN_PA05D_GLOC_IN2 5 /**< \brief GLOC signal: IN2 on PA05 mux D */\r
+#define MUX_PA05D_GLOC_IN2 3\r
+#define GPIO_PA05D_GLOC_IN2 (1u << 5)\r
+#define PIN_PA22D_GLOC_IN2 22 /**< \brief GLOC signal: IN2 on PA22 mux D */\r
+#define MUX_PA22D_GLOC_IN2 3\r
+#define GPIO_PA22D_GLOC_IN2 (1u << 22)\r
+#define PIN_PA07D_GLOC_IN3 7 /**< \brief GLOC signal: IN3 on PA07 mux D */\r
+#define MUX_PA07D_GLOC_IN3 3\r
+#define GPIO_PA07D_GLOC_IN3 (1u << 7)\r
+#define PIN_PA23D_GLOC_IN3 23 /**< \brief GLOC signal: IN3 on PA23 mux D */\r
+#define MUX_PA23D_GLOC_IN3 3\r
+#define GPIO_PA23D_GLOC_IN3 (1u << 23)\r
+#define PIN_PA27D_GLOC_IN4 27 /**< \brief GLOC signal: IN4 on PA27 mux D */\r
+#define MUX_PA27D_GLOC_IN4 3\r
+#define GPIO_PA27D_GLOC_IN4 (1u << 27)\r
+#define PIN_PC15D_GLOC_IN4 79 /**< \brief GLOC signal: IN4 on PC15 mux D */\r
+#define MUX_PC15D_GLOC_IN4 3\r
+#define GPIO_PC15D_GLOC_IN4 (1u << 15)\r
+#define PIN_PB06C_GLOC_IN4 38 /**< \brief GLOC signal: IN4 on PB06 mux C */\r
+#define MUX_PB06C_GLOC_IN4 2\r
+#define GPIO_PB06C_GLOC_IN4 (1u << 6)\r
+#define PIN_PC28C_GLOC_IN4 92 /**< \brief GLOC signal: IN4 on PC28 mux C */\r
+#define MUX_PC28C_GLOC_IN4 2\r
+#define GPIO_PC28C_GLOC_IN4 (1u << 28)\r
+#define PIN_PA28D_GLOC_IN5 28 /**< \brief GLOC signal: IN5 on PA28 mux D */\r
+#define MUX_PA28D_GLOC_IN5 3\r
+#define GPIO_PA28D_GLOC_IN5 (1u << 28)\r
+#define PIN_PC16D_GLOC_IN5 80 /**< \brief GLOC signal: IN5 on PC16 mux D */\r
+#define MUX_PC16D_GLOC_IN5 3\r
+#define GPIO_PC16D_GLOC_IN5 (1u << 16)\r
+#define PIN_PB07C_GLOC_IN5 39 /**< \brief GLOC signal: IN5 on PB07 mux C */\r
+#define MUX_PB07C_GLOC_IN5 2\r
+#define GPIO_PB07C_GLOC_IN5 (1u << 7)\r
+#define PIN_PC29C_GLOC_IN5 93 /**< \brief GLOC signal: IN5 on PC29 mux C */\r
+#define MUX_PC29C_GLOC_IN5 2\r
+#define GPIO_PC29C_GLOC_IN5 (1u << 29)\r
+#define PIN_PA29D_GLOC_IN6 29 /**< \brief GLOC signal: IN6 on PA29 mux D */\r
+#define MUX_PA29D_GLOC_IN6 3\r
+#define GPIO_PA29D_GLOC_IN6 (1u << 29)\r
+#define PIN_PC17D_GLOC_IN6 81 /**< \brief GLOC signal: IN6 on PC17 mux D */\r
+#define MUX_PC17D_GLOC_IN6 3\r
+#define GPIO_PC17D_GLOC_IN6 (1u << 17)\r
+#define PIN_PB08C_GLOC_IN6 40 /**< \brief GLOC signal: IN6 on PB08 mux C */\r
+#define MUX_PB08C_GLOC_IN6 2\r
+#define GPIO_PB08C_GLOC_IN6 (1u << 8)\r
+#define PIN_PC30C_GLOC_IN6 94 /**< \brief GLOC signal: IN6 on PC30 mux C */\r
+#define MUX_PC30C_GLOC_IN6 2\r
+#define GPIO_PC30C_GLOC_IN6 (1u << 30)\r
+#define PIN_PA30D_GLOC_IN7 30 /**< \brief GLOC signal: IN7 on PA30 mux D */\r
+#define MUX_PA30D_GLOC_IN7 3\r
+#define GPIO_PA30D_GLOC_IN7 (1u << 30)\r
+#define PIN_PC18D_GLOC_IN7 82 /**< \brief GLOC signal: IN7 on PC18 mux D */\r
+#define MUX_PC18D_GLOC_IN7 3\r
+#define GPIO_PC18D_GLOC_IN7 (1u << 18)\r
+#define PIN_PB09C_GLOC_IN7 41 /**< \brief GLOC signal: IN7 on PB09 mux C */\r
+#define MUX_PB09C_GLOC_IN7 2\r
+#define GPIO_PB09C_GLOC_IN7 (1u << 9)\r
+#define PIN_PA08D_GLOC_OUT0 8 /**< \brief GLOC signal: OUT0 on PA08 mux D */\r
+#define MUX_PA08D_GLOC_OUT0 3\r
+#define GPIO_PA08D_GLOC_OUT0 (1u << 8)\r
+#define PIN_PA24D_GLOC_OUT0 24 /**< \brief GLOC signal: OUT0 on PA24 mux D */\r
+#define MUX_PA24D_GLOC_OUT0 3\r
+#define GPIO_PA24D_GLOC_OUT0 (1u << 24)\r
+#define PIN_PA31D_GLOC_OUT1 31 /**< \brief GLOC signal: OUT1 on PA31 mux D */\r
+#define MUX_PA31D_GLOC_OUT1 3\r
+#define GPIO_PA31D_GLOC_OUT1 (1u << 31)\r
+#define PIN_PC19D_GLOC_OUT1 83 /**< \brief GLOC signal: OUT1 on PC19 mux D */\r
+#define MUX_PC19D_GLOC_OUT1 3\r
+#define GPIO_PC19D_GLOC_OUT1 (1u << 19)\r
+#define PIN_PB10C_GLOC_OUT1 42 /**< \brief GLOC signal: OUT1 on PB10 mux C */\r
+#define MUX_PB10C_GLOC_OUT1 2\r
+#define GPIO_PB10C_GLOC_OUT1 (1u << 10)\r
+#define PIN_PC31C_GLOC_OUT1 95 /**< \brief GLOC signal: OUT1 on PC31 mux C */\r
+#define MUX_PC31C_GLOC_OUT1 2\r
+#define GPIO_PC31C_GLOC_OUT1 (1u << 31)\r
+/* ========== GPIO definition for IISC peripheral ========== */\r
+#define PIN_PB05D_IISC_IMCK 37 /**< \brief IISC signal: IMCK on PB05 mux D */\r
+#define MUX_PB05D_IISC_IMCK 3\r
+#define GPIO_PB05D_IISC_IMCK (1u << 5)\r
+#define PIN_PC14D_IISC_IMCK 78 /**< \brief IISC signal: IMCK on PC14 mux D */\r
+#define MUX_PC14D_IISC_IMCK 3\r
+#define GPIO_PC14D_IISC_IMCK (1u << 14)\r
+#define PIN_PA31B_IISC_IMCK 31 /**< \brief IISC signal: IMCK on PA31 mux B */\r
+#define MUX_PA31B_IISC_IMCK 1\r
+#define GPIO_PA31B_IISC_IMCK (1u << 31)\r
+#define PIN_PB02D_IISC_ISCK 34 /**< \brief IISC signal: ISCK on PB02 mux D */\r
+#define MUX_PB02D_IISC_ISCK 3\r
+#define GPIO_PB02D_IISC_ISCK (1u << 2)\r
+#define PIN_PC09D_IISC_ISCK 73 /**< \brief IISC signal: ISCK on PC09 mux D */\r
+#define MUX_PC09D_IISC_ISCK 3\r
+#define GPIO_PC09D_IISC_ISCK (1u << 9)\r
+#define PIN_PA27B_IISC_ISCK 27 /**< \brief IISC signal: ISCK on PA27 mux B */\r
+#define MUX_PA27B_IISC_ISCK 1\r
+#define GPIO_PA27B_IISC_ISCK (1u << 27)\r
+#define PIN_PB03D_IISC_ISDI 35 /**< \brief IISC signal: ISDI on PB03 mux D */\r
+#define MUX_PB03D_IISC_ISDI 3\r
+#define GPIO_PB03D_IISC_ISDI (1u << 3)\r
+#define PIN_PC10D_IISC_ISDI 74 /**< \brief IISC signal: ISDI on PC10 mux D */\r
+#define MUX_PC10D_IISC_ISDI 3\r
+#define GPIO_PC10D_IISC_ISDI (1u << 10)\r
+#define PIN_PA28B_IISC_ISDI 28 /**< \brief IISC signal: ISDI on PA28 mux B */\r
+#define MUX_PA28B_IISC_ISDI 1\r
+#define GPIO_PA28B_IISC_ISDI (1u << 28)\r
+#define PIN_PB04D_IISC_ISDO 36 /**< \brief IISC signal: ISDO on PB04 mux D */\r
+#define MUX_PB04D_IISC_ISDO 3\r
+#define GPIO_PB04D_IISC_ISDO (1u << 4)\r
+#define PIN_PC13D_IISC_ISDO 77 /**< \brief IISC signal: ISDO on PC13 mux D */\r
+#define MUX_PC13D_IISC_ISDO 3\r
+#define GPIO_PC13D_IISC_ISDO (1u << 13)\r
+#define PIN_PA30B_IISC_ISDO 30 /**< \brief IISC signal: ISDO on PA30 mux B */\r
+#define MUX_PA30B_IISC_ISDO 1\r
+#define GPIO_PA30B_IISC_ISDO (1u << 30)\r
+#define PIN_PB06D_IISC_IWS 38 /**< \brief IISC signal: IWS on PB06 mux D */\r
+#define MUX_PB06D_IISC_IWS 3\r
+#define GPIO_PB06D_IISC_IWS (1u << 6)\r
+#define PIN_PC12D_IISC_IWS 76 /**< \brief IISC signal: IWS on PC12 mux D */\r
+#define MUX_PC12D_IISC_IWS 3\r
+#define GPIO_PC12D_IISC_IWS (1u << 12)\r
+#define PIN_PA29B_IISC_IWS 29 /**< \brief IISC signal: IWS on PA29 mux B */\r
+#define MUX_PA29B_IISC_IWS 1\r
+#define GPIO_PA29B_IISC_IWS (1u << 29)\r
+/* ========== GPIO definition for LCDCA peripheral ========== */\r
+#define PIN_PA12F_LCDCA_COM0 12 /**< \brief LCDCA signal: COM0 on PA12 mux F */\r
+#define MUX_PA12F_LCDCA_COM0 5\r
+#define GPIO_PA12F_LCDCA_COM0 (1u << 12)\r
+#define PIN_PA11F_LCDCA_COM1 11 /**< \brief LCDCA signal: COM1 on PA11 mux F */\r
+#define MUX_PA11F_LCDCA_COM1 5\r
+#define GPIO_PA11F_LCDCA_COM1 (1u << 11)\r
+#define PIN_PA10F_LCDCA_COM2 10 /**< \brief LCDCA signal: COM2 on PA10 mux F */\r
+#define MUX_PA10F_LCDCA_COM2 5\r
+#define GPIO_PA10F_LCDCA_COM2 (1u << 10)\r
+#define PIN_PA09F_LCDCA_COM3 9 /**< \brief LCDCA signal: COM3 on PA09 mux F */\r
+#define MUX_PA09F_LCDCA_COM3 5\r
+#define GPIO_PA09F_LCDCA_COM3 (1u << 9)\r
+#define PIN_PC15F_LCDCA_SEG0 79 /**< \brief LCDCA signal: SEG0 on PC15 mux F */\r
+#define MUX_PC15F_LCDCA_SEG0 5\r
+#define GPIO_PC15F_LCDCA_SEG0 (1u << 15)\r
+#define PIN_PC16F_LCDCA_SEG1 80 /**< \brief LCDCA signal: SEG1 on PC16 mux F */\r
+#define MUX_PC16F_LCDCA_SEG1 5\r
+#define GPIO_PC16F_LCDCA_SEG1 (1u << 16)\r
+#define PIN_PC17F_LCDCA_SEG2 81 /**< \brief LCDCA signal: SEG2 on PC17 mux F */\r
+#define MUX_PC17F_LCDCA_SEG2 5\r
+#define GPIO_PC17F_LCDCA_SEG2 (1u << 17)\r
+#define PIN_PC18F_LCDCA_SEG3 82 /**< \brief LCDCA signal: SEG3 on PC18 mux F */\r
+#define MUX_PC18F_LCDCA_SEG3 5\r
+#define GPIO_PC18F_LCDCA_SEG3 (1u << 18)\r
+#define PIN_PC19F_LCDCA_SEG4 83 /**< \brief LCDCA signal: SEG4 on PC19 mux F */\r
+#define MUX_PC19F_LCDCA_SEG4 5\r
+#define GPIO_PC19F_LCDCA_SEG4 (1u << 19)\r
+#define PIN_PA13F_LCDCA_SEG5 13 /**< \brief LCDCA signal: SEG5 on PA13 mux F */\r
+#define MUX_PA13F_LCDCA_SEG5 5\r
+#define GPIO_PA13F_LCDCA_SEG5 (1u << 13)\r
+#define PIN_PA14F_LCDCA_SEG6 14 /**< \brief LCDCA signal: SEG6 on PA14 mux F */\r
+#define MUX_PA14F_LCDCA_SEG6 5\r
+#define GPIO_PA14F_LCDCA_SEG6 (1u << 14)\r
+#define PIN_PA15F_LCDCA_SEG7 15 /**< \brief LCDCA signal: SEG7 on PA15 mux F */\r
+#define MUX_PA15F_LCDCA_SEG7 5\r
+#define GPIO_PA15F_LCDCA_SEG7 (1u << 15)\r
+#define PIN_PA16F_LCDCA_SEG8 16 /**< \brief LCDCA signal: SEG8 on PA16 mux F */\r
+#define MUX_PA16F_LCDCA_SEG8 5\r
+#define GPIO_PA16F_LCDCA_SEG8 (1u << 16)\r
+#define PIN_PA17F_LCDCA_SEG9 17 /**< \brief LCDCA signal: SEG9 on PA17 mux F */\r
+#define MUX_PA17F_LCDCA_SEG9 5\r
+#define GPIO_PA17F_LCDCA_SEG9 (1u << 17)\r
+#define PIN_PC20F_LCDCA_SEG10 84 /**< \brief LCDCA signal: SEG10 on PC20 mux F */\r
+#define MUX_PC20F_LCDCA_SEG10 5\r
+#define GPIO_PC20F_LCDCA_SEG10 (1u << 20)\r
+#define PIN_PC21F_LCDCA_SEG11 85 /**< \brief LCDCA signal: SEG11 on PC21 mux F */\r
+#define MUX_PC21F_LCDCA_SEG11 5\r
+#define GPIO_PC21F_LCDCA_SEG11 (1u << 21)\r
+#define PIN_PC22F_LCDCA_SEG12 86 /**< \brief LCDCA signal: SEG12 on PC22 mux F */\r
+#define MUX_PC22F_LCDCA_SEG12 5\r
+#define GPIO_PC22F_LCDCA_SEG12 (1u << 22)\r
+#define PIN_PC23F_LCDCA_SEG13 87 /**< \brief LCDCA signal: SEG13 on PC23 mux F */\r
+#define MUX_PC23F_LCDCA_SEG13 5\r
+#define GPIO_PC23F_LCDCA_SEG13 (1u << 23)\r
+#define PIN_PB08F_LCDCA_SEG14 40 /**< \brief LCDCA signal: SEG14 on PB08 mux F */\r
+#define MUX_PB08F_LCDCA_SEG14 5\r
+#define GPIO_PB08F_LCDCA_SEG14 (1u << 8)\r
+#define PIN_PB09F_LCDCA_SEG15 41 /**< \brief LCDCA signal: SEG15 on PB09 mux F */\r
+#define MUX_PB09F_LCDCA_SEG15 5\r
+#define GPIO_PB09F_LCDCA_SEG15 (1u << 9)\r
+#define PIN_PB10F_LCDCA_SEG16 42 /**< \brief LCDCA signal: SEG16 on PB10 mux F */\r
+#define MUX_PB10F_LCDCA_SEG16 5\r
+#define GPIO_PB10F_LCDCA_SEG16 (1u << 10)\r
+#define PIN_PB11F_LCDCA_SEG17 43 /**< \brief LCDCA signal: SEG17 on PB11 mux F */\r
+#define MUX_PB11F_LCDCA_SEG17 5\r
+#define GPIO_PB11F_LCDCA_SEG17 (1u << 11)\r
+#define PIN_PA18F_LCDCA_SEG18 18 /**< \brief LCDCA signal: SEG18 on PA18 mux F */\r
+#define MUX_PA18F_LCDCA_SEG18 5\r
+#define GPIO_PA18F_LCDCA_SEG18 (1u << 18)\r
+#define PIN_PA19F_LCDCA_SEG19 19 /**< \brief LCDCA signal: SEG19 on PA19 mux F */\r
+#define MUX_PA19F_LCDCA_SEG19 5\r
+#define GPIO_PA19F_LCDCA_SEG19 (1u << 19)\r
+#define PIN_PA20F_LCDCA_SEG20 20 /**< \brief LCDCA signal: SEG20 on PA20 mux F */\r
+#define MUX_PA20F_LCDCA_SEG20 5\r
+#define GPIO_PA20F_LCDCA_SEG20 (1u << 20)\r
+#define PIN_PB07F_LCDCA_SEG21 39 /**< \brief LCDCA signal: SEG21 on PB07 mux F */\r
+#define MUX_PB07F_LCDCA_SEG21 5\r
+#define GPIO_PB07F_LCDCA_SEG21 (1u << 7)\r
+#define PIN_PB06F_LCDCA_SEG22 38 /**< \brief LCDCA signal: SEG22 on PB06 mux F */\r
+#define MUX_PB06F_LCDCA_SEG22 5\r
+#define GPIO_PB06F_LCDCA_SEG22 (1u << 6)\r
+#define PIN_PA08F_LCDCA_SEG23 8 /**< \brief LCDCA signal: SEG23 on PA08 mux F */\r
+#define MUX_PA08F_LCDCA_SEG23 5\r
+#define GPIO_PA08F_LCDCA_SEG23 (1u << 8)\r
+#define PIN_PC24F_LCDCA_SEG24 88 /**< \brief LCDCA signal: SEG24 on PC24 mux F */\r
+#define MUX_PC24F_LCDCA_SEG24 5\r
+#define GPIO_PC24F_LCDCA_SEG24 (1u << 24)\r
+#define PIN_PC25F_LCDCA_SEG25 89 /**< \brief LCDCA signal: SEG25 on PC25 mux F */\r
+#define MUX_PC25F_LCDCA_SEG25 5\r
+#define GPIO_PC25F_LCDCA_SEG25 (1u << 25)\r
+#define PIN_PC26F_LCDCA_SEG26 90 /**< \brief LCDCA signal: SEG26 on PC26 mux F */\r
+#define MUX_PC26F_LCDCA_SEG26 5\r
+#define GPIO_PC26F_LCDCA_SEG26 (1u << 26)\r
+#define PIN_PC27F_LCDCA_SEG27 91 /**< \brief LCDCA signal: SEG27 on PC27 mux F */\r
+#define MUX_PC27F_LCDCA_SEG27 5\r
+#define GPIO_PC27F_LCDCA_SEG27 (1u << 27)\r
+#define PIN_PC28F_LCDCA_SEG28 92 /**< \brief LCDCA signal: SEG28 on PC28 mux F */\r
+#define MUX_PC28F_LCDCA_SEG28 5\r
+#define GPIO_PC28F_LCDCA_SEG28 (1u << 28)\r
+#define PIN_PC29F_LCDCA_SEG29 93 /**< \brief LCDCA signal: SEG29 on PC29 mux F */\r
+#define MUX_PC29F_LCDCA_SEG29 5\r
+#define GPIO_PC29F_LCDCA_SEG29 (1u << 29)\r
+#define PIN_PC30F_LCDCA_SEG30 94 /**< \brief LCDCA signal: SEG30 on PC30 mux F */\r
+#define MUX_PC30F_LCDCA_SEG30 5\r
+#define GPIO_PC30F_LCDCA_SEG30 (1u << 30)\r
+#define PIN_PC31F_LCDCA_SEG31 95 /**< \brief LCDCA signal: SEG31 on PC31 mux F */\r
+#define MUX_PC31F_LCDCA_SEG31 5\r
+#define GPIO_PC31F_LCDCA_SEG31 (1u << 31)\r
+#define PIN_PB12F_LCDCA_SEG32 44 /**< \brief LCDCA signal: SEG32 on PB12 mux F */\r
+#define MUX_PB12F_LCDCA_SEG32 5\r
+#define GPIO_PB12F_LCDCA_SEG32 (1u << 12)\r
+#define PIN_PB13F_LCDCA_SEG33 45 /**< \brief LCDCA signal: SEG33 on PB13 mux F */\r
+#define MUX_PB13F_LCDCA_SEG33 5\r
+#define GPIO_PB13F_LCDCA_SEG33 (1u << 13)\r
+#define PIN_PA21F_LCDCA_SEG34 21 /**< \brief LCDCA signal: SEG34 on PA21 mux F */\r
+#define MUX_PA21F_LCDCA_SEG34 5\r
+#define GPIO_PA21F_LCDCA_SEG34 (1u << 21)\r
+#define PIN_PA22F_LCDCA_SEG35 22 /**< \brief LCDCA signal: SEG35 on PA22 mux F */\r
+#define MUX_PA22F_LCDCA_SEG35 5\r
+#define GPIO_PA22F_LCDCA_SEG35 (1u << 22)\r
+#define PIN_PB14F_LCDCA_SEG36 46 /**< \brief LCDCA signal: SEG36 on PB14 mux F */\r
+#define MUX_PB14F_LCDCA_SEG36 5\r
+#define GPIO_PB14F_LCDCA_SEG36 (1u << 14)\r
+#define PIN_PB15F_LCDCA_SEG37 47 /**< \brief LCDCA signal: SEG37 on PB15 mux F */\r
+#define MUX_PB15F_LCDCA_SEG37 5\r
+#define GPIO_PB15F_LCDCA_SEG37 (1u << 15)\r
+#define PIN_PA23F_LCDCA_SEG38 23 /**< \brief LCDCA signal: SEG38 on PA23 mux F */\r
+#define MUX_PA23F_LCDCA_SEG38 5\r
+#define GPIO_PA23F_LCDCA_SEG38 (1u << 23)\r
+#define PIN_PA24F_LCDCA_SEG39 24 /**< \brief LCDCA signal: SEG39 on PA24 mux F */\r
+#define MUX_PA24F_LCDCA_SEG39 5\r
+#define GPIO_PA24F_LCDCA_SEG39 (1u << 24)\r
+/* ========== GPIO definition for PARC peripheral ========== */\r
+#define PIN_PA17D_PARC_PCCK 17 /**< \brief PARC signal: PCCK on PA17 mux D */\r
+#define MUX_PA17D_PARC_PCCK 3\r
+#define GPIO_PA17D_PARC_PCCK (1u << 17)\r
+#define PIN_PC21D_PARC_PCCK 85 /**< \brief PARC signal: PCCK on PC21 mux D */\r
+#define MUX_PC21D_PARC_PCCK 3\r
+#define GPIO_PC21D_PARC_PCCK (1u << 21)\r
+#define PIN_PA09D_PARC_PCDATA0 9 /**< \brief PARC signal: PCDATA0 on PA09 mux D */\r
+#define MUX_PA09D_PARC_PCDATA0 3\r
+#define GPIO_PA09D_PARC_PCDATA0 (1u << 9)\r
+#define PIN_PC24D_PARC_PCDATA0 88 /**< \brief PARC signal: PCDATA0 on PC24 mux D */\r
+#define MUX_PC24D_PARC_PCDATA0 3\r
+#define GPIO_PC24D_PARC_PCDATA0 (1u << 24)\r
+#define PIN_PA10D_PARC_PCDATA1 10 /**< \brief PARC signal: PCDATA1 on PA10 mux D */\r
+#define MUX_PA10D_PARC_PCDATA1 3\r
+#define GPIO_PA10D_PARC_PCDATA1 (1u << 10)\r
+#define PIN_PC25D_PARC_PCDATA1 89 /**< \brief PARC signal: PCDATA1 on PC25 mux D */\r
+#define MUX_PC25D_PARC_PCDATA1 3\r
+#define GPIO_PC25D_PARC_PCDATA1 (1u << 25)\r
+#define PIN_PA11D_PARC_PCDATA2 11 /**< \brief PARC signal: PCDATA2 on PA11 mux D */\r
+#define MUX_PA11D_PARC_PCDATA2 3\r
+#define GPIO_PA11D_PARC_PCDATA2 (1u << 11)\r
+#define PIN_PC26D_PARC_PCDATA2 90 /**< \brief PARC signal: PCDATA2 on PC26 mux D */\r
+#define MUX_PC26D_PARC_PCDATA2 3\r
+#define GPIO_PC26D_PARC_PCDATA2 (1u << 26)\r
+#define PIN_PA12D_PARC_PCDATA3 12 /**< \brief PARC signal: PCDATA3 on PA12 mux D */\r
+#define MUX_PA12D_PARC_PCDATA3 3\r
+#define GPIO_PA12D_PARC_PCDATA3 (1u << 12)\r
+#define PIN_PC27D_PARC_PCDATA3 91 /**< \brief PARC signal: PCDATA3 on PC27 mux D */\r
+#define MUX_PC27D_PARC_PCDATA3 3\r
+#define GPIO_PC27D_PARC_PCDATA3 (1u << 27)\r
+#define PIN_PA13D_PARC_PCDATA4 13 /**< \brief PARC signal: PCDATA4 on PA13 mux D */\r
+#define MUX_PA13D_PARC_PCDATA4 3\r
+#define GPIO_PA13D_PARC_PCDATA4 (1u << 13)\r
+#define PIN_PC28D_PARC_PCDATA4 92 /**< \brief PARC signal: PCDATA4 on PC28 mux D */\r
+#define MUX_PC28D_PARC_PCDATA4 3\r
+#define GPIO_PC28D_PARC_PCDATA4 (1u << 28)\r
+#define PIN_PA14D_PARC_PCDATA5 14 /**< \brief PARC signal: PCDATA5 on PA14 mux D */\r
+#define MUX_PA14D_PARC_PCDATA5 3\r
+#define GPIO_PA14D_PARC_PCDATA5 (1u << 14)\r
+#define PIN_PC29D_PARC_PCDATA5 93 /**< \brief PARC signal: PCDATA5 on PC29 mux D */\r
+#define MUX_PC29D_PARC_PCDATA5 3\r
+#define GPIO_PC29D_PARC_PCDATA5 (1u << 29)\r
+#define PIN_PA15D_PARC_PCDATA6 15 /**< \brief PARC signal: PCDATA6 on PA15 mux D */\r
+#define MUX_PA15D_PARC_PCDATA6 3\r
+#define GPIO_PA15D_PARC_PCDATA6 (1u << 15)\r
+#define PIN_PC30D_PARC_PCDATA6 94 /**< \brief PARC signal: PCDATA6 on PC30 mux D */\r
+#define MUX_PC30D_PARC_PCDATA6 3\r
+#define GPIO_PC30D_PARC_PCDATA6 (1u << 30)\r
+#define PIN_PA16D_PARC_PCDATA7 16 /**< \brief PARC signal: PCDATA7 on PA16 mux D */\r
+#define MUX_PA16D_PARC_PCDATA7 3\r
+#define GPIO_PA16D_PARC_PCDATA7 (1u << 16)\r
+#define PIN_PC31D_PARC_PCDATA7 95 /**< \brief PARC signal: PCDATA7 on PC31 mux D */\r
+#define MUX_PC31D_PARC_PCDATA7 3\r
+#define GPIO_PC31D_PARC_PCDATA7 (1u << 31)\r
+#define PIN_PA18D_PARC_PCEN1 18 /**< \brief PARC signal: PCEN1 on PA18 mux D */\r
+#define MUX_PA18D_PARC_PCEN1 3\r
+#define GPIO_PA18D_PARC_PCEN1 (1u << 18)\r
+#define PIN_PC22D_PARC_PCEN1 86 /**< \brief PARC signal: PCEN1 on PC22 mux D */\r
+#define MUX_PC22D_PARC_PCEN1 3\r
+#define GPIO_PC22D_PARC_PCEN1 (1u << 22)\r
+#define PIN_PA19D_PARC_PCEN2 19 /**< \brief PARC signal: PCEN2 on PA19 mux D */\r
+#define MUX_PA19D_PARC_PCEN2 3\r
+#define GPIO_PA19D_PARC_PCEN2 (1u << 19)\r
+#define PIN_PC23D_PARC_PCEN2 87 /**< \brief PARC signal: PCEN2 on PC23 mux D */\r
+#define MUX_PC23D_PARC_PCEN2 3\r
+#define GPIO_PC23D_PARC_PCEN2 (1u << 23)\r
+/* ========== GPIO definition for PEVC peripheral ========== */\r
+#define PIN_PA08C_PEVC_PAD_EVT0 8 /**< \brief PEVC signal: PAD_EVT0 on PA08 mux C */\r
+#define MUX_PA08C_PEVC_PAD_EVT0 2\r
+#define GPIO_PA08C_PEVC_PAD_EVT0 (1u << 8)\r
+#define PIN_PB12C_PEVC_PAD_EVT0 44 /**< \brief PEVC signal: PAD_EVT0 on PB12 mux C */\r
+#define MUX_PB12C_PEVC_PAD_EVT0 2\r
+#define GPIO_PB12C_PEVC_PAD_EVT0 (1u << 12)\r
+#define PIN_PC07C_PEVC_PAD_EVT0 71 /**< \brief PEVC signal: PAD_EVT0 on PC07 mux C */\r
+#define MUX_PC07C_PEVC_PAD_EVT0 2\r
+#define GPIO_PC07C_PEVC_PAD_EVT0 (1u << 7)\r
+#define PIN_PC24C_PEVC_PAD_EVT0 88 /**< \brief PEVC signal: PAD_EVT0 on PC24 mux C */\r
+#define MUX_PC24C_PEVC_PAD_EVT0 2\r
+#define GPIO_PC24C_PEVC_PAD_EVT0 (1u << 24)\r
+#define PIN_PA09C_PEVC_PAD_EVT1 9 /**< \brief PEVC signal: PAD_EVT1 on PA09 mux C */\r
+#define MUX_PA09C_PEVC_PAD_EVT1 2\r
+#define GPIO_PA09C_PEVC_PAD_EVT1 (1u << 9)\r
+#define PIN_PB13C_PEVC_PAD_EVT1 45 /**< \brief PEVC signal: PAD_EVT1 on PB13 mux C */\r
+#define MUX_PB13C_PEVC_PAD_EVT1 2\r
+#define GPIO_PB13C_PEVC_PAD_EVT1 (1u << 13)\r
+#define PIN_PC08C_PEVC_PAD_EVT1 72 /**< \brief PEVC signal: PAD_EVT1 on PC08 mux C */\r
+#define MUX_PC08C_PEVC_PAD_EVT1 2\r
+#define GPIO_PC08C_PEVC_PAD_EVT1 (1u << 8)\r
+#define PIN_PC25C_PEVC_PAD_EVT1 89 /**< \brief PEVC signal: PAD_EVT1 on PC25 mux C */\r
+#define MUX_PC25C_PEVC_PAD_EVT1 2\r
+#define GPIO_PC25C_PEVC_PAD_EVT1 (1u << 25)\r
+#define PIN_PA10C_PEVC_PAD_EVT2 10 /**< \brief PEVC signal: PAD_EVT2 on PA10 mux C */\r
+#define MUX_PA10C_PEVC_PAD_EVT2 2\r
+#define GPIO_PA10C_PEVC_PAD_EVT2 (1u << 10)\r
+#define PIN_PC11C_PEVC_PAD_EVT2 75 /**< \brief PEVC signal: PAD_EVT2 on PC11 mux C */\r
+#define MUX_PC11C_PEVC_PAD_EVT2 2\r
+#define GPIO_PC11C_PEVC_PAD_EVT2 (1u << 11)\r
+#define PIN_PC26C_PEVC_PAD_EVT2 90 /**< \brief PEVC signal: PAD_EVT2 on PC26 mux C */\r
+#define MUX_PC26C_PEVC_PAD_EVT2 2\r
+#define GPIO_PC26C_PEVC_PAD_EVT2 (1u << 26)\r
+#define PIN_PB09B_PEVC_PAD_EVT2 41 /**< \brief PEVC signal: PAD_EVT2 on PB09 mux B */\r
+#define MUX_PB09B_PEVC_PAD_EVT2 1\r
+#define GPIO_PB09B_PEVC_PAD_EVT2 (1u << 9)\r
+#define PIN_PA11C_PEVC_PAD_EVT3 11 /**< \brief PEVC signal: PAD_EVT3 on PA11 mux C */\r
+#define MUX_PA11C_PEVC_PAD_EVT3 2\r
+#define GPIO_PA11C_PEVC_PAD_EVT3 (1u << 11)\r
+#define PIN_PC27C_PEVC_PAD_EVT3 91 /**< \brief PEVC signal: PAD_EVT3 on PC27 mux C */\r
+#define MUX_PC27C_PEVC_PAD_EVT3 2\r
+#define GPIO_PC27C_PEVC_PAD_EVT3 (1u << 27)\r
+#define PIN_PB10B_PEVC_PAD_EVT3 42 /**< \brief PEVC signal: PAD_EVT3 on PB10 mux B */\r
+#define MUX_PB10B_PEVC_PAD_EVT3 1\r
+#define GPIO_PB10B_PEVC_PAD_EVT3 (1u << 10)\r
+/* ========== GPIO definition for SCIF peripheral ========== */\r
+#define PIN_PA19E_SCIF_GCLK0 19 /**< \brief SCIF signal: GCLK0 on PA19 mux E */\r
+#define MUX_PA19E_SCIF_GCLK0 4\r
+#define GPIO_PA19E_SCIF_GCLK0 (1u << 19)\r
+#define PIN_PB10E_SCIF_GCLK0 42 /**< \brief SCIF signal: GCLK0 on PB10 mux E */\r
+#define MUX_PB10E_SCIF_GCLK0 4\r
+#define GPIO_PB10E_SCIF_GCLK0 (1u << 10)\r
+#define PIN_PC26E_SCIF_GCLK0 90 /**< \brief SCIF signal: GCLK0 on PC26 mux E */\r
+#define MUX_PC26E_SCIF_GCLK0 4\r
+#define GPIO_PC26E_SCIF_GCLK0 (1u << 26)\r
+#define PIN_PA02A_SCIF_GCLK0 2 /**< \brief SCIF signal: GCLK0 on PA02 mux A */\r
+#define MUX_PA02A_SCIF_GCLK0 0\r
+#define GPIO_PA02A_SCIF_GCLK0 (1u << 2)\r
+#define PIN_PA20E_SCIF_GCLK1 20 /**< \brief SCIF signal: GCLK1 on PA20 mux E */\r
+#define MUX_PA20E_SCIF_GCLK1 4\r
+#define GPIO_PA20E_SCIF_GCLK1 (1u << 20)\r
+#define PIN_PB11E_SCIF_GCLK1 43 /**< \brief SCIF signal: GCLK1 on PB11 mux E */\r
+#define MUX_PB11E_SCIF_GCLK1 4\r
+#define GPIO_PB11E_SCIF_GCLK1 (1u << 11)\r
+#define PIN_PC27E_SCIF_GCLK1 91 /**< \brief SCIF signal: GCLK1 on PC27 mux E */\r
+#define MUX_PC27E_SCIF_GCLK1 4\r
+#define GPIO_PC27E_SCIF_GCLK1 (1u << 27)\r
+#define PIN_PB12E_SCIF_GCLK2 44 /**< \brief SCIF signal: GCLK2 on PB12 mux E */\r
+#define MUX_PB12E_SCIF_GCLK2 4\r
+#define GPIO_PB12E_SCIF_GCLK2 (1u << 12)\r
+#define PIN_PC28E_SCIF_GCLK2 92 /**< \brief SCIF signal: GCLK2 on PC28 mux E */\r
+#define MUX_PC28E_SCIF_GCLK2 4\r
+#define GPIO_PC28E_SCIF_GCLK2 (1u << 28)\r
+#define PIN_PB13E_SCIF_GCLK3 45 /**< \brief SCIF signal: GCLK3 on PB13 mux E */\r
+#define MUX_PB13E_SCIF_GCLK3 4\r
+#define GPIO_PB13E_SCIF_GCLK3 (1u << 13)\r
+#define PIN_PC29E_SCIF_GCLK3 93 /**< \brief SCIF signal: GCLK3 on PC29 mux E */\r
+#define MUX_PC29E_SCIF_GCLK3 4\r
+#define GPIO_PC29E_SCIF_GCLK3 (1u << 29)\r
+#define PIN_PA23E_SCIF_GCLK_IN0 23 /**< \brief SCIF signal: GCLK_IN0 on PA23 mux E */\r
+#define MUX_PA23E_SCIF_GCLK_IN0 4\r
+#define GPIO_PA23E_SCIF_GCLK_IN0 (1u << 23)\r
+#define PIN_PB14E_SCIF_GCLK_IN0 46 /**< \brief SCIF signal: GCLK_IN0 on PB14 mux E */\r
+#define MUX_PB14E_SCIF_GCLK_IN0 4\r
+#define GPIO_PB14E_SCIF_GCLK_IN0 (1u << 14)\r
+#define PIN_PC30E_SCIF_GCLK_IN0 94 /**< \brief SCIF signal: GCLK_IN0 on PC30 mux E */\r
+#define MUX_PC30E_SCIF_GCLK_IN0 4\r
+#define GPIO_PC30E_SCIF_GCLK_IN0 (1u << 30)\r
+#define PIN_PA24E_SCIF_GCLK_IN1 24 /**< \brief SCIF signal: GCLK_IN1 on PA24 mux E */\r
+#define MUX_PA24E_SCIF_GCLK_IN1 4\r
+#define GPIO_PA24E_SCIF_GCLK_IN1 (1u << 24)\r
+#define PIN_PB15E_SCIF_GCLK_IN1 47 /**< \brief SCIF signal: GCLK_IN1 on PB15 mux E */\r
+#define MUX_PB15E_SCIF_GCLK_IN1 4\r
+#define GPIO_PB15E_SCIF_GCLK_IN1 (1u << 15)\r
+#define PIN_PC31E_SCIF_GCLK_IN1 95 /**< \brief SCIF signal: GCLK_IN1 on PC31 mux E */\r
+#define MUX_PC31E_SCIF_GCLK_IN1 4\r
+#define GPIO_PC31E_SCIF_GCLK_IN1 (1u << 31)\r
+/* ========== GPIO definition for SPI peripheral ========== */\r
+#define PIN_PA03B_SPI_MISO 3 /**< \brief SPI signal: MISO on PA03 mux B */\r
+#define MUX_PA03B_SPI_MISO 1\r
+#define GPIO_PA03B_SPI_MISO (1u << 3)\r
+#define PIN_PB14B_SPI_MISO 46 /**< \brief SPI signal: MISO on PB14 mux B */\r
+#define MUX_PB14B_SPI_MISO 1\r
+#define GPIO_PB14B_SPI_MISO (1u << 14)\r
+#define PIN_PC28B_SPI_MISO 92 /**< \brief SPI signal: MISO on PC28 mux B */\r
+#define MUX_PC28B_SPI_MISO 1\r
+#define GPIO_PC28B_SPI_MISO (1u << 28)\r
+#define PIN_PA21A_SPI_MISO 21 /**< \brief SPI signal: MISO on PA21 mux A */\r
+#define MUX_PA21A_SPI_MISO 0\r
+#define GPIO_PA21A_SPI_MISO (1u << 21)\r
+#define PIN_PA27A_SPI_MISO 27 /**< \brief SPI signal: MISO on PA27 mux A */\r
+#define MUX_PA27A_SPI_MISO 0\r
+#define GPIO_PA27A_SPI_MISO (1u << 27)\r
+#define PIN_PC04A_SPI_MISO 68 /**< \brief SPI signal: MISO on PC04 mux A */\r
+#define MUX_PC04A_SPI_MISO 0\r
+#define GPIO_PC04A_SPI_MISO (1u << 4)\r
+#define PIN_PB15B_SPI_MOSI 47 /**< \brief SPI signal: MOSI on PB15 mux B */\r
+#define MUX_PB15B_SPI_MOSI 1\r
+#define GPIO_PB15B_SPI_MOSI (1u << 15)\r
+#define PIN_PC29B_SPI_MOSI 93 /**< \brief SPI signal: MOSI on PC29 mux B */\r
+#define MUX_PC29B_SPI_MOSI 1\r
+#define GPIO_PC29B_SPI_MOSI (1u << 29)\r
+#define PIN_PA22A_SPI_MOSI 22 /**< \brief SPI signal: MOSI on PA22 mux A */\r
+#define MUX_PA22A_SPI_MOSI 0\r
+#define GPIO_PA22A_SPI_MOSI (1u << 22)\r
+#define PIN_PA28A_SPI_MOSI 28 /**< \brief SPI signal: MOSI on PA28 mux A */\r
+#define MUX_PA28A_SPI_MOSI 0\r
+#define GPIO_PA28A_SPI_MOSI (1u << 28)\r
+#define PIN_PC05A_SPI_MOSI 69 /**< \brief SPI signal: MOSI on PC05 mux A */\r
+#define MUX_PC05A_SPI_MOSI 0\r
+#define GPIO_PC05A_SPI_MOSI (1u << 5)\r
+#define PIN_PA02B_SPI_NPCS0 2 /**< \brief SPI signal: NPCS0 on PA02 mux B */\r
+#define MUX_PA02B_SPI_NPCS0 1\r
+#define GPIO_PA02B_SPI_NPCS0 (1u << 2)\r
+#define PIN_PC31B_SPI_NPCS0 95 /**< \brief SPI signal: NPCS0 on PC31 mux B */\r
+#define MUX_PC31B_SPI_NPCS0 1\r
+#define GPIO_PC31B_SPI_NPCS0 (1u << 31)\r
+#define PIN_PA24A_SPI_NPCS0 24 /**< \brief SPI signal: NPCS0 on PA24 mux A */\r
+#define MUX_PA24A_SPI_NPCS0 0\r
+#define GPIO_PA24A_SPI_NPCS0 (1u << 24)\r
+#define PIN_PA30A_SPI_NPCS0 30 /**< \brief SPI signal: NPCS0 on PA30 mux A */\r
+#define MUX_PA30A_SPI_NPCS0 0\r
+#define GPIO_PA30A_SPI_NPCS0 (1u << 30)\r
+#define PIN_PC03A_SPI_NPCS0 67 /**< \brief SPI signal: NPCS0 on PC03 mux A */\r
+#define MUX_PC03A_SPI_NPCS0 0\r
+#define GPIO_PC03A_SPI_NPCS0 (1u << 3)\r
+#define PIN_PA13C_SPI_NPCS1 13 /**< \brief SPI signal: NPCS1 on PA13 mux C */\r
+#define MUX_PA13C_SPI_NPCS1 2\r
+#define GPIO_PA13C_SPI_NPCS1 (1u << 13)\r
+#define PIN_PB13B_SPI_NPCS1 45 /**< \brief SPI signal: NPCS1 on PB13 mux B */\r
+#define MUX_PB13B_SPI_NPCS1 1\r
+#define GPIO_PB13B_SPI_NPCS1 (1u << 13)\r
+#define PIN_PA31A_SPI_NPCS1 31 /**< \brief SPI signal: NPCS1 on PA31 mux A */\r
+#define MUX_PA31A_SPI_NPCS1 0\r
+#define GPIO_PA31A_SPI_NPCS1 (1u << 31)\r
+#define PIN_PC02A_SPI_NPCS1 66 /**< \brief SPI signal: NPCS1 on PC02 mux A */\r
+#define MUX_PC02A_SPI_NPCS1 0\r
+#define GPIO_PC02A_SPI_NPCS1 (1u << 2)\r
+#define PIN_PA14C_SPI_NPCS2 14 /**< \brief SPI signal: NPCS2 on PA14 mux C */\r
+#define MUX_PA14C_SPI_NPCS2 2\r
+#define GPIO_PA14C_SPI_NPCS2 (1u << 14)\r
+#define PIN_PB11B_SPI_NPCS2 43 /**< \brief SPI signal: NPCS2 on PB11 mux B */\r
+#define MUX_PB11B_SPI_NPCS2 1\r
+#define GPIO_PB11B_SPI_NPCS2 (1u << 11)\r
+#define PIN_PC00A_SPI_NPCS2 64 /**< \brief SPI signal: NPCS2 on PC00 mux A */\r
+#define MUX_PC00A_SPI_NPCS2 0\r
+#define GPIO_PC00A_SPI_NPCS2 (1u << 0)\r
+#define PIN_PA15C_SPI_NPCS3 15 /**< \brief SPI signal: NPCS3 on PA15 mux C */\r
+#define MUX_PA15C_SPI_NPCS3 2\r
+#define GPIO_PA15C_SPI_NPCS3 (1u << 15)\r
+#define PIN_PB12B_SPI_NPCS3 44 /**< \brief SPI signal: NPCS3 on PB12 mux B */\r
+#define MUX_PB12B_SPI_NPCS3 1\r
+#define GPIO_PB12B_SPI_NPCS3 (1u << 12)\r
+#define PIN_PC01A_SPI_NPCS3 65 /**< \brief SPI signal: NPCS3 on PC01 mux A */\r
+#define MUX_PC01A_SPI_NPCS3 0\r
+#define GPIO_PC01A_SPI_NPCS3 (1u << 1)\r
+#define PIN_PC30B_SPI_SCK 94 /**< \brief SPI signal: SCK on PC30 mux B */\r
+#define MUX_PC30B_SPI_SCK 1\r
+#define GPIO_PC30B_SPI_SCK (1u << 30)\r
+#define PIN_PA23A_SPI_SCK 23 /**< \brief SPI signal: SCK on PA23 mux A */\r
+#define MUX_PA23A_SPI_SCK 0\r
+#define GPIO_PA23A_SPI_SCK (1u << 23)\r
+#define PIN_PA29A_SPI_SCK 29 /**< \brief SPI signal: SCK on PA29 mux A */\r
+#define MUX_PA29A_SPI_SCK 0\r
+#define GPIO_PA29A_SPI_SCK (1u << 29)\r
+#define PIN_PC06A_SPI_SCK 70 /**< \brief SPI signal: SCK on PC06 mux A */\r
+#define MUX_PC06A_SPI_SCK 0\r
+#define GPIO_PC06A_SPI_SCK (1u << 6)\r
+/* ========== GPIO definition for TC0 peripheral ========== */\r
+#define PIN_PB07D_TC0_A0 39 /**< \brief TC0 signal: A0 on PB07 mux D */\r
+#define MUX_PB07D_TC0_A0 3\r
+#define GPIO_PB07D_TC0_A0 (1u << 7)\r
+#define PIN_PA08B_TC0_A0 8 /**< \brief TC0 signal: A0 on PA08 mux B */\r
+#define MUX_PA08B_TC0_A0 1\r
+#define GPIO_PA08B_TC0_A0 (1u << 8)\r
+#define PIN_PB09D_TC0_A1 41 /**< \brief TC0 signal: A1 on PB09 mux D */\r
+#define MUX_PB09D_TC0_A1 3\r
+#define GPIO_PB09D_TC0_A1 (1u << 9)\r
+#define PIN_PA10B_TC0_A1 10 /**< \brief TC0 signal: A1 on PA10 mux B */\r
+#define MUX_PA10B_TC0_A1 1\r
+#define GPIO_PA10B_TC0_A1 (1u << 10)\r
+#define PIN_PB11D_TC0_A2 43 /**< \brief TC0 signal: A2 on PB11 mux D */\r
+#define MUX_PB11D_TC0_A2 3\r
+#define GPIO_PB11D_TC0_A2 (1u << 11)\r
+#define PIN_PA12B_TC0_A2 12 /**< \brief TC0 signal: A2 on PA12 mux B */\r
+#define MUX_PA12B_TC0_A2 1\r
+#define GPIO_PA12B_TC0_A2 (1u << 12)\r
+#define PIN_PB08D_TC0_B0 40 /**< \brief TC0 signal: B0 on PB08 mux D */\r
+#define MUX_PB08D_TC0_B0 3\r
+#define GPIO_PB08D_TC0_B0 (1u << 8)\r
+#define PIN_PA09B_TC0_B0 9 /**< \brief TC0 signal: B0 on PA09 mux B */\r
+#define MUX_PA09B_TC0_B0 1\r
+#define GPIO_PA09B_TC0_B0 (1u << 9)\r
+#define PIN_PB10D_TC0_B1 42 /**< \brief TC0 signal: B1 on PB10 mux D */\r
+#define MUX_PB10D_TC0_B1 3\r
+#define GPIO_PB10D_TC0_B1 (1u << 10)\r
+#define PIN_PA11B_TC0_B1 11 /**< \brief TC0 signal: B1 on PA11 mux B */\r
+#define MUX_PA11B_TC0_B1 1\r
+#define GPIO_PA11B_TC0_B1 (1u << 11)\r
+#define PIN_PB12D_TC0_B2 44 /**< \brief TC0 signal: B2 on PB12 mux D */\r
+#define MUX_PB12D_TC0_B2 3\r
+#define GPIO_PB12D_TC0_B2 (1u << 12)\r
+#define PIN_PA13B_TC0_B2 13 /**< \brief TC0 signal: B2 on PA13 mux B */\r
+#define MUX_PA13B_TC0_B2 1\r
+#define GPIO_PA13B_TC0_B2 (1u << 13)\r
+#define PIN_PB13D_TC0_CLK0 45 /**< \brief TC0 signal: CLK0 on PB13 mux D */\r
+#define MUX_PB13D_TC0_CLK0 3\r
+#define GPIO_PB13D_TC0_CLK0 (1u << 13)\r
+#define PIN_PA14B_TC0_CLK0 14 /**< \brief TC0 signal: CLK0 on PA14 mux B */\r
+#define MUX_PA14B_TC0_CLK0 1\r
+#define GPIO_PA14B_TC0_CLK0 (1u << 14)\r
+#define PIN_PB14D_TC0_CLK1 46 /**< \brief TC0 signal: CLK1 on PB14 mux D */\r
+#define MUX_PB14D_TC0_CLK1 3\r
+#define GPIO_PB14D_TC0_CLK1 (1u << 14)\r
+#define PIN_PA15B_TC0_CLK1 15 /**< \brief TC0 signal: CLK1 on PA15 mux B */\r
+#define MUX_PA15B_TC0_CLK1 1\r
+#define GPIO_PA15B_TC0_CLK1 (1u << 15)\r
+#define PIN_PB15D_TC0_CLK2 47 /**< \brief TC0 signal: CLK2 on PB15 mux D */\r
+#define MUX_PB15D_TC0_CLK2 3\r
+#define GPIO_PB15D_TC0_CLK2 (1u << 15)\r
+#define PIN_PA16B_TC0_CLK2 16 /**< \brief TC0 signal: CLK2 on PA16 mux B */\r
+#define MUX_PA16B_TC0_CLK2 1\r
+#define GPIO_PA16B_TC0_CLK2 (1u << 16)\r
+/* ========== GPIO definition for TC1 peripheral ========== */\r
+#define PIN_PC00D_TC1_A0 64 /**< \brief TC1 signal: A0 on PC00 mux D */\r
+#define MUX_PC00D_TC1_A0 3\r
+#define GPIO_PC00D_TC1_A0 (1u << 0)\r
+#define PIN_PC15A_TC1_A0 79 /**< \brief TC1 signal: A0 on PC15 mux A */\r
+#define MUX_PC15A_TC1_A0 0\r
+#define GPIO_PC15A_TC1_A0 (1u << 15)\r
+#define PIN_PC02D_TC1_A1 66 /**< \brief TC1 signal: A1 on PC02 mux D */\r
+#define MUX_PC02D_TC1_A1 3\r
+#define GPIO_PC02D_TC1_A1 (1u << 2)\r
+#define PIN_PC17A_TC1_A1 81 /**< \brief TC1 signal: A1 on PC17 mux A */\r
+#define MUX_PC17A_TC1_A1 0\r
+#define GPIO_PC17A_TC1_A1 (1u << 17)\r
+#define PIN_PC04D_TC1_A2 68 /**< \brief TC1 signal: A2 on PC04 mux D */\r
+#define MUX_PC04D_TC1_A2 3\r
+#define GPIO_PC04D_TC1_A2 (1u << 4)\r
+#define PIN_PC19A_TC1_A2 83 /**< \brief TC1 signal: A2 on PC19 mux A */\r
+#define MUX_PC19A_TC1_A2 0\r
+#define GPIO_PC19A_TC1_A2 (1u << 19)\r
+#define PIN_PC01D_TC1_B0 65 /**< \brief TC1 signal: B0 on PC01 mux D */\r
+#define MUX_PC01D_TC1_B0 3\r
+#define GPIO_PC01D_TC1_B0 (1u << 1)\r
+#define PIN_PC16A_TC1_B0 80 /**< \brief TC1 signal: B0 on PC16 mux A */\r
+#define MUX_PC16A_TC1_B0 0\r
+#define GPIO_PC16A_TC1_B0 (1u << 16)\r
+#define PIN_PC03D_TC1_B1 67 /**< \brief TC1 signal: B1 on PC03 mux D */\r
+#define MUX_PC03D_TC1_B1 3\r
+#define GPIO_PC03D_TC1_B1 (1u << 3)\r
+#define PIN_PC18A_TC1_B1 82 /**< \brief TC1 signal: B1 on PC18 mux A */\r
+#define MUX_PC18A_TC1_B1 0\r
+#define GPIO_PC18A_TC1_B1 (1u << 18)\r
+#define PIN_PC05D_TC1_B2 69 /**< \brief TC1 signal: B2 on PC05 mux D */\r
+#define MUX_PC05D_TC1_B2 3\r
+#define GPIO_PC05D_TC1_B2 (1u << 5)\r
+#define PIN_PC20A_TC1_B2 84 /**< \brief TC1 signal: B2 on PC20 mux A */\r
+#define MUX_PC20A_TC1_B2 0\r
+#define GPIO_PC20A_TC1_B2 (1u << 20)\r
+#define PIN_PC06D_TC1_CLK0 70 /**< \brief TC1 signal: CLK0 on PC06 mux D */\r
+#define MUX_PC06D_TC1_CLK0 3\r
+#define GPIO_PC06D_TC1_CLK0 (1u << 6)\r
+#define PIN_PC21A_TC1_CLK0 85 /**< \brief TC1 signal: CLK0 on PC21 mux A */\r
+#define MUX_PC21A_TC1_CLK0 0\r
+#define GPIO_PC21A_TC1_CLK0 (1u << 21)\r
+#define PIN_PC07D_TC1_CLK1 71 /**< \brief TC1 signal: CLK1 on PC07 mux D */\r
+#define MUX_PC07D_TC1_CLK1 3\r
+#define GPIO_PC07D_TC1_CLK1 (1u << 7)\r
+#define PIN_PC22A_TC1_CLK1 86 /**< \brief TC1 signal: CLK1 on PC22 mux A */\r
+#define MUX_PC22A_TC1_CLK1 0\r
+#define GPIO_PC22A_TC1_CLK1 (1u << 22)\r
+#define PIN_PC08D_TC1_CLK2 72 /**< \brief TC1 signal: CLK2 on PC08 mux D */\r
+#define MUX_PC08D_TC1_CLK2 3\r
+#define GPIO_PC08D_TC1_CLK2 (1u << 8)\r
+#define PIN_PC23A_TC1_CLK2 87 /**< \brief TC1 signal: CLK2 on PC23 mux A */\r
+#define MUX_PC23A_TC1_CLK2 0\r
+#define GPIO_PC23A_TC1_CLK2 (1u << 23)\r
+/* ========== GPIO definition for TWIMS0 peripheral ========== */\r
+#define PIN_PA24B_TWIMS0_TWCK 24 /**< \brief TWIMS0 signal: TWCK on PA24 mux B */\r
+#define MUX_PA24B_TWIMS0_TWCK 1\r
+#define GPIO_PA24B_TWIMS0_TWCK (1u << 24)\r
+#define PIN_PA23B_TWIMS0_TWD 23 /**< \brief TWIMS0 signal: TWD on PA23 mux B */\r
+#define MUX_PA23B_TWIMS0_TWD 1\r
+#define GPIO_PA23B_TWIMS0_TWD (1u << 23)\r
+/* ========== GPIO definition for TWIMS1 peripheral ========== */\r
+#define PIN_PB01A_TWIMS1_TWCK 33 /**< \brief TWIMS1 signal: TWCK on PB01 mux A */\r
+#define MUX_PB01A_TWIMS1_TWCK 0\r
+#define GPIO_PB01A_TWIMS1_TWCK (1u << 1)\r
+#define PIN_PB00A_TWIMS1_TWD 32 /**< \brief TWIMS1 signal: TWD on PB00 mux A */\r
+#define MUX_PB00A_TWIMS1_TWD 0\r
+#define GPIO_PB00A_TWIMS1_TWD (1u << 0)\r
+/* ========== GPIO definition for TWIMS2 peripheral ========== */\r
+#define PIN_PA22E_TWIMS2_TWCK 22 /**< \brief TWIMS2 signal: TWCK on PA22 mux E */\r
+#define MUX_PA22E_TWIMS2_TWCK 4\r
+#define GPIO_PA22E_TWIMS2_TWCK (1u << 22)\r
+#define PIN_PA21E_TWIMS2_TWD 21 /**< \brief TWIMS2 signal: TWD on PA21 mux E */\r
+#define MUX_PA21E_TWIMS2_TWD 4\r
+#define GPIO_PA21E_TWIMS2_TWD (1u << 21)\r
+/* ========== GPIO definition for TWIMS3 peripheral ========== */\r
+#define PIN_PB15C_TWIMS3_TWCK 47 /**< \brief TWIMS3 signal: TWCK on PB15 mux C */\r
+#define MUX_PB15C_TWIMS3_TWCK 2\r
+#define GPIO_PB15C_TWIMS3_TWCK (1u << 15)\r
+#define PIN_PB14C_TWIMS3_TWD 46 /**< \brief TWIMS3 signal: TWD on PB14 mux C */\r
+#define MUX_PB14C_TWIMS3_TWD 2\r
+#define GPIO_PB14C_TWIMS3_TWD (1u << 14)\r
+/* ========== GPIO definition for USART0 peripheral ========== */\r
+#define PIN_PA04B_USART0_CLK 4 /**< \brief USART0 signal: CLK on PA04 mux B */\r
+#define MUX_PA04B_USART0_CLK 1\r
+#define GPIO_PA04B_USART0_CLK (1u << 4)\r
+#define PIN_PC00B_USART0_CLK 64 /**< \brief USART0 signal: CLK on PC00 mux B */\r
+#define MUX_PC00B_USART0_CLK 1\r
+#define GPIO_PC00B_USART0_CLK (1u << 0)\r
+#define PIN_PA10A_USART0_CLK 10 /**< \brief USART0 signal: CLK on PA10 mux A */\r
+#define MUX_PA10A_USART0_CLK 0\r
+#define GPIO_PA10A_USART0_CLK (1u << 10)\r
+#define PIN_PB13A_USART0_CLK 45 /**< \brief USART0 signal: CLK on PB13 mux A */\r
+#define MUX_PB13A_USART0_CLK 0\r
+#define GPIO_PB13A_USART0_CLK (1u << 13)\r
+#define PIN_PC02B_USART0_CTS 66 /**< \brief USART0 signal: CTS on PC02 mux B */\r
+#define MUX_PC02B_USART0_CTS 1\r
+#define GPIO_PC02B_USART0_CTS (1u << 2)\r
+#define PIN_PA09A_USART0_CTS 9 /**< \brief USART0 signal: CTS on PA09 mux A */\r
+#define MUX_PA09A_USART0_CTS 0\r
+#define GPIO_PA09A_USART0_CTS (1u << 9)\r
+#define PIN_PB11A_USART0_CTS 43 /**< \brief USART0 signal: CTS on PB11 mux A */\r
+#define MUX_PB11A_USART0_CTS 0\r
+#define GPIO_PB11A_USART0_CTS (1u << 11)\r
+#define PIN_PA06B_USART0_RTS 6 /**< \brief USART0 signal: RTS on PA06 mux B */\r
+#define MUX_PA06B_USART0_RTS 1\r
+#define GPIO_PA06B_USART0_RTS (1u << 6)\r
+#define PIN_PC01B_USART0_RTS 65 /**< \brief USART0 signal: RTS on PC01 mux B */\r
+#define MUX_PC01B_USART0_RTS 1\r
+#define GPIO_PC01B_USART0_RTS (1u << 1)\r
+#define PIN_PA08A_USART0_RTS 8 /**< \brief USART0 signal: RTS on PA08 mux A */\r
+#define MUX_PA08A_USART0_RTS 0\r
+#define GPIO_PA08A_USART0_RTS (1u << 8)\r
+#define PIN_PB12A_USART0_RTS 44 /**< \brief USART0 signal: RTS on PB12 mux A */\r
+#define MUX_PB12A_USART0_RTS 0\r
+#define GPIO_PB12A_USART0_RTS (1u << 12)\r
+#define PIN_PC02C_USART0_RXD 66 /**< \brief USART0 signal: RXD on PC02 mux C */\r
+#define MUX_PC02C_USART0_RXD 2\r
+#define GPIO_PC02C_USART0_RXD (1u << 2)\r
+#define PIN_PA05B_USART0_RXD 5 /**< \brief USART0 signal: RXD on PA05 mux B */\r
+#define MUX_PA05B_USART0_RXD 1\r
+#define GPIO_PA05B_USART0_RXD (1u << 5)\r
+#define PIN_PB00B_USART0_RXD 32 /**< \brief USART0 signal: RXD on PB00 mux B */\r
+#define MUX_PB00B_USART0_RXD 1\r
+#define GPIO_PB00B_USART0_RXD (1u << 0)\r
+#define PIN_PA11A_USART0_RXD 11 /**< \brief USART0 signal: RXD on PA11 mux A */\r
+#define MUX_PA11A_USART0_RXD 0\r
+#define GPIO_PA11A_USART0_RXD (1u << 11)\r
+#define PIN_PB14A_USART0_RXD 46 /**< \brief USART0 signal: RXD on PB14 mux A */\r
+#define MUX_PB14A_USART0_RXD 0\r
+#define GPIO_PB14A_USART0_RXD (1u << 14)\r
+#define PIN_PC03C_USART0_TXD 67 /**< \brief USART0 signal: TXD on PC03 mux C */\r
+#define MUX_PC03C_USART0_TXD 2\r
+#define GPIO_PC03C_USART0_TXD (1u << 3)\r
+#define PIN_PA07B_USART0_TXD 7 /**< \brief USART0 signal: TXD on PA07 mux B */\r
+#define MUX_PA07B_USART0_TXD 1\r
+#define GPIO_PA07B_USART0_TXD (1u << 7)\r
+#define PIN_PB01B_USART0_TXD 33 /**< \brief USART0 signal: TXD on PB01 mux B */\r
+#define MUX_PB01B_USART0_TXD 1\r
+#define GPIO_PB01B_USART0_TXD (1u << 1)\r
+#define PIN_PA12A_USART0_TXD 12 /**< \brief USART0 signal: TXD on PA12 mux A */\r
+#define MUX_PA12A_USART0_TXD 0\r
+#define GPIO_PA12A_USART0_TXD (1u << 12)\r
+#define PIN_PB15A_USART0_TXD 47 /**< \brief USART0 signal: TXD on PB15 mux A */\r
+#define MUX_PB15A_USART0_TXD 0\r
+#define GPIO_PB15A_USART0_TXD (1u << 15)\r
+/* ========== GPIO definition for USART1 peripheral ========== */\r
+#define PIN_PB03B_USART1_CLK 35 /**< \brief USART1 signal: CLK on PB03 mux B */\r
+#define MUX_PB03B_USART1_CLK 1\r
+#define GPIO_PB03B_USART1_CLK (1u << 3)\r
+#define PIN_PA14A_USART1_CLK 14 /**< \brief USART1 signal: CLK on PA14 mux A */\r
+#define MUX_PA14A_USART1_CLK 0\r
+#define GPIO_PA14A_USART1_CLK (1u << 14)\r
+#define PIN_PC25A_USART1_CLK 89 /**< \brief USART1 signal: CLK on PC25 mux A */\r
+#define MUX_PC25A_USART1_CLK 0\r
+#define GPIO_PC25A_USART1_CLK (1u << 25)\r
+#define PIN_PA21B_USART1_CTS 21 /**< \brief USART1 signal: CTS on PA21 mux B */\r
+#define MUX_PA21B_USART1_CTS 1\r
+#define GPIO_PA21B_USART1_CTS (1u << 21)\r
+#define PIN_PB02B_USART1_RTS 34 /**< \brief USART1 signal: RTS on PB02 mux B */\r
+#define MUX_PB02B_USART1_RTS 1\r
+#define GPIO_PB02B_USART1_RTS (1u << 2)\r
+#define PIN_PA13A_USART1_RTS 13 /**< \brief USART1 signal: RTS on PA13 mux A */\r
+#define MUX_PA13A_USART1_RTS 0\r
+#define GPIO_PA13A_USART1_RTS (1u << 13)\r
+#define PIN_PC24A_USART1_RTS 88 /**< \brief USART1 signal: RTS on PC24 mux A */\r
+#define MUX_PC24A_USART1_RTS 0\r
+#define GPIO_PC24A_USART1_RTS (1u << 24)\r
+#define PIN_PB04B_USART1_RXD 36 /**< \brief USART1 signal: RXD on PB04 mux B */\r
+#define MUX_PB04B_USART1_RXD 1\r
+#define GPIO_PB04B_USART1_RXD (1u << 4)\r
+#define PIN_PA15A_USART1_RXD 15 /**< \brief USART1 signal: RXD on PA15 mux A */\r
+#define MUX_PA15A_USART1_RXD 0\r
+#define GPIO_PA15A_USART1_RXD (1u << 15)\r
+#define PIN_PC26A_USART1_RXD 90 /**< \brief USART1 signal: RXD on PC26 mux A */\r
+#define MUX_PC26A_USART1_RXD 0\r
+#define GPIO_PC26A_USART1_RXD (1u << 26)\r
+#define PIN_PB05B_USART1_TXD 37 /**< \brief USART1 signal: TXD on PB05 mux B */\r
+#define MUX_PB05B_USART1_TXD 1\r
+#define GPIO_PB05B_USART1_TXD (1u << 5)\r
+#define PIN_PA16A_USART1_TXD 16 /**< \brief USART1 signal: TXD on PA16 mux A */\r
+#define MUX_PA16A_USART1_TXD 0\r
+#define GPIO_PA16A_USART1_TXD (1u << 16)\r
+#define PIN_PC27A_USART1_TXD 91 /**< \brief USART1 signal: TXD on PC27 mux A */\r
+#define MUX_PC27A_USART1_TXD 0\r
+#define GPIO_PC27A_USART1_TXD (1u << 27)\r
+/* ========== GPIO definition for USART2 peripheral ========== */\r
+#define PIN_PC08B_USART2_CLK 72 /**< \brief USART2 signal: CLK on PC08 mux B */\r
+#define MUX_PC08B_USART2_CLK 1\r
+#define GPIO_PC08B_USART2_CLK (1u << 8)\r
+#define PIN_PA18A_USART2_CLK 18 /**< \brief USART2 signal: CLK on PA18 mux A */\r
+#define MUX_PA18A_USART2_CLK 0\r
+#define GPIO_PA18A_USART2_CLK (1u << 18)\r
+#define PIN_PC08E_USART2_CTS 72 /**< \brief USART2 signal: CTS on PC08 mux E */\r
+#define MUX_PC08E_USART2_CTS 4\r
+#define GPIO_PC08E_USART2_CTS (1u << 8)\r
+#define PIN_PA22B_USART2_CTS 22 /**< \brief USART2 signal: CTS on PA22 mux B */\r
+#define MUX_PA22B_USART2_CTS 1\r
+#define GPIO_PA22B_USART2_CTS (1u << 22)\r
+#define PIN_PC07B_USART2_RTS 71 /**< \brief USART2 signal: RTS on PC07 mux B */\r
+#define MUX_PC07B_USART2_RTS 1\r
+#define GPIO_PC07B_USART2_RTS (1u << 7)\r
+#define PIN_PA17A_USART2_RTS 17 /**< \brief USART2 signal: RTS on PA17 mux A */\r
+#define MUX_PA17A_USART2_RTS 0\r
+#define GPIO_PA17A_USART2_RTS (1u << 17)\r
+#define PIN_PA25B_USART2_RXD 25 /**< \brief USART2 signal: RXD on PA25 mux B */\r
+#define MUX_PA25B_USART2_RXD 1\r
+#define GPIO_PA25B_USART2_RXD (1u << 25)\r
+#define PIN_PC11B_USART2_RXD 75 /**< \brief USART2 signal: RXD on PC11 mux B */\r
+#define MUX_PC11B_USART2_RXD 1\r
+#define GPIO_PC11B_USART2_RXD (1u << 11)\r
+#define PIN_PA19A_USART2_RXD 19 /**< \brief USART2 signal: RXD on PA19 mux A */\r
+#define MUX_PA19A_USART2_RXD 0\r
+#define GPIO_PA19A_USART2_RXD (1u << 19)\r
+#define PIN_PA26B_USART2_TXD 26 /**< \brief USART2 signal: TXD on PA26 mux B */\r
+#define MUX_PA26B_USART2_TXD 1\r
+#define GPIO_PA26B_USART2_TXD (1u << 26)\r
+#define PIN_PC12B_USART2_TXD 76 /**< \brief USART2 signal: TXD on PC12 mux B */\r
+#define MUX_PC12B_USART2_TXD 1\r
+#define GPIO_PC12B_USART2_TXD (1u << 12)\r
+#define PIN_PA20A_USART2_TXD 20 /**< \brief USART2 signal: TXD on PA20 mux A */\r
+#define MUX_PA20A_USART2_TXD 0\r
+#define GPIO_PA20A_USART2_TXD (1u << 20)\r
+/* ========== GPIO definition for USART3 peripheral ========== */\r
+#define PIN_PA29E_USART3_CLK 29 /**< \brief USART3 signal: CLK on PA29 mux E */\r
+#define MUX_PA29E_USART3_CLK 4\r
+#define GPIO_PA29E_USART3_CLK (1u << 29)\r
+#define PIN_PC14B_USART3_CLK 78 /**< \brief USART3 signal: CLK on PC14 mux B */\r
+#define MUX_PC14B_USART3_CLK 1\r
+#define GPIO_PC14B_USART3_CLK (1u << 14)\r
+#define PIN_PB08A_USART3_CLK 40 /**< \brief USART3 signal: CLK on PB08 mux A */\r
+#define MUX_PB08A_USART3_CLK 0\r
+#define GPIO_PB08A_USART3_CLK (1u << 8)\r
+#define PIN_PC31A_USART3_CLK 95 /**< \brief USART3 signal: CLK on PC31 mux A */\r
+#define MUX_PC31A_USART3_CLK 0\r
+#define GPIO_PC31A_USART3_CLK (1u << 31)\r
+#define PIN_PA28E_USART3_CTS 28 /**< \brief USART3 signal: CTS on PA28 mux E */\r
+#define MUX_PA28E_USART3_CTS 4\r
+#define GPIO_PA28E_USART3_CTS (1u << 28)\r
+#define PIN_PB07A_USART3_CTS 39 /**< \brief USART3 signal: CTS on PB07 mux A */\r
+#define MUX_PB07A_USART3_CTS 0\r
+#define GPIO_PB07A_USART3_CTS (1u << 7)\r
+#define PIN_PA27E_USART3_RTS 27 /**< \brief USART3 signal: RTS on PA27 mux E */\r
+#define MUX_PA27E_USART3_RTS 4\r
+#define GPIO_PA27E_USART3_RTS (1u << 27)\r
+#define PIN_PC13B_USART3_RTS 77 /**< \brief USART3 signal: RTS on PC13 mux B */\r
+#define MUX_PC13B_USART3_RTS 1\r
+#define GPIO_PC13B_USART3_RTS (1u << 13)\r
+#define PIN_PB06A_USART3_RTS 38 /**< \brief USART3 signal: RTS on PB06 mux A */\r
+#define MUX_PB06A_USART3_RTS 0\r
+#define GPIO_PB06A_USART3_RTS (1u << 6)\r
+#define PIN_PC30A_USART3_RTS 94 /**< \brief USART3 signal: RTS on PC30 mux A */\r
+#define MUX_PC30A_USART3_RTS 0\r
+#define GPIO_PC30A_USART3_RTS (1u << 30)\r
+#define PIN_PA30E_USART3_RXD 30 /**< \brief USART3 signal: RXD on PA30 mux E */\r
+#define MUX_PA30E_USART3_RXD 4\r
+#define GPIO_PA30E_USART3_RXD (1u << 30)\r
+#define PIN_PC09B_USART3_RXD 73 /**< \brief USART3 signal: RXD on PC09 mux B */\r
+#define MUX_PC09B_USART3_RXD 1\r
+#define GPIO_PC09B_USART3_RXD (1u << 9)\r
+#define PIN_PB09A_USART3_RXD 41 /**< \brief USART3 signal: RXD on PB09 mux A */\r
+#define MUX_PB09A_USART3_RXD 0\r
+#define GPIO_PB09A_USART3_RXD (1u << 9)\r
+#define PIN_PC28A_USART3_RXD 92 /**< \brief USART3 signal: RXD on PC28 mux A */\r
+#define MUX_PC28A_USART3_RXD 0\r
+#define GPIO_PC28A_USART3_RXD (1u << 28)\r
+#define PIN_PA31E_USART3_TXD 31 /**< \brief USART3 signal: TXD on PA31 mux E */\r
+#define MUX_PA31E_USART3_TXD 4\r
+#define GPIO_PA31E_USART3_TXD (1u << 31)\r
+#define PIN_PC10B_USART3_TXD 74 /**< \brief USART3 signal: TXD on PC10 mux B */\r
+#define MUX_PC10B_USART3_TXD 1\r
+#define GPIO_PC10B_USART3_TXD (1u << 10)\r
+#define PIN_PB10A_USART3_TXD 42 /**< \brief USART3 signal: TXD on PB10 mux A */\r
+#define MUX_PB10A_USART3_TXD 0\r
+#define GPIO_PB10A_USART3_TXD (1u << 10)\r
+#define PIN_PC29A_USART3_TXD 93 /**< \brief USART3 signal: TXD on PC29 mux A */\r
+#define MUX_PC29A_USART3_TXD 0\r
+#define GPIO_PC29A_USART3_TXD (1u << 29)\r
+/* ========== GPIO definition for USBC peripheral ========== */\r
+#define PIN_PA25A_USBC_DM 25 /**< \brief USBC signal: DM on PA25 mux A */\r
+#define MUX_PA25A_USBC_DM 0\r
+#define GPIO_PA25A_USBC_DM (1u << 25)\r
+#define PIN_PA26A_USBC_DP 26 /**< \brief USBC signal: DP on PA26 mux A */\r
+#define MUX_PA26A_USBC_DP 0\r
+#define GPIO_PA26A_USBC_DP (1u << 26)\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** MEMORY MAPPING DEFINITIONS FOR SAM4L */\r
+/* ************************************************************************** */\r
+\r
+#if defined __SAM4LC2A__\r
+ #define FLASH_SIZE 0x20000 /* 128 kB */\r
+ #define FLASH_PAGE_SIZE 512\r
+ #define FLASH_NB_OF_PAGES 256\r
+ #define FLASH_USER_PAGE_SIZE 512\r
+ #define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+ #define HRAMC1_SIZE 0xc00 /* 3 kB */\r
+\r
+#elif defined __SAM4LC2B__\r
+ #define FLASH_SIZE 0x20000 /* 128 kB */\r
+ #define FLASH_PAGE_SIZE 512\r
+ #define FLASH_NB_OF_PAGES 256\r
+ #define FLASH_USER_PAGE_SIZE 512\r
+ #define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+ #define HRAMC1_SIZE 0xc00 /* 3 kB */\r
+\r
+#elif defined __SAM4LC2C__\r
+ #define FLASH_SIZE 0x20000 /* 128 kB */\r
+ #define FLASH_PAGE_SIZE 512\r
+ #define FLASH_NB_OF_PAGES 256\r
+ #define FLASH_USER_PAGE_SIZE 512\r
+ #define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+ #define HRAMC1_SIZE 0xc00 /* 3 kB */\r
+\r
+#elif defined __SAM4LC4A__\r
+ #define FLASH_SIZE 0x40000 /* 256 kB */\r
+ #define FLASH_PAGE_SIZE 512\r
+ #define FLASH_NB_OF_PAGES 512\r
+ #define FLASH_USER_PAGE_SIZE 512\r
+ #define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+ #define HRAMC1_SIZE 0xc00 /* 3 kB */\r
+\r
+#elif defined __SAM4LC4B__\r
+ #define FLASH_SIZE 0x40000 /* 256 kB */\r
+ #define FLASH_PAGE_SIZE 512\r
+ #define FLASH_NB_OF_PAGES 512\r
+ #define FLASH_USER_PAGE_SIZE 512\r
+ #define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+ #define HRAMC1_SIZE 0xc00 /* 3 kB */\r
+\r
+#elif defined __SAM4LC4C__\r
+ #define FLASH_SIZE 0x40000 /* 256 kB */\r
+ #define FLASH_PAGE_SIZE 512\r
+ #define FLASH_NB_OF_PAGES 512\r
+ #define FLASH_USER_PAGE_SIZE 512\r
+ #define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+ #define HRAMC1_SIZE 0xc00 /* 3 kB */\r
+\r
+#elif defined __SAM4LS2A__\r
+ #define FLASH_SIZE 0x20000 /* 128 kB */\r
+ #define FLASH_PAGE_SIZE 512\r
+ #define FLASH_NB_OF_PAGES 256\r
+ #define FLASH_USER_PAGE_SIZE 512\r
+ #define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+ #define HRAMC1_SIZE 0xc00 /* 3 kB */\r
+\r
+#elif defined __SAM4LS2B__\r
+ #define FLASH_SIZE 0x20000 /* 128 kB */\r
+ #define FLASH_PAGE_SIZE 512\r
+ #define FLASH_NB_OF_PAGES 256\r
+ #define FLASH_USER_PAGE_SIZE 512\r
+ #define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+ #define HRAMC1_SIZE 0xc00 /* 3 kB */\r
+\r
+#elif defined __SAM4LS2C__\r
+ #define FLASH_SIZE 0x20000 /* 128 kB */\r
+ #define FLASH_PAGE_SIZE 512\r
+ #define FLASH_NB_OF_PAGES 256\r
+ #define FLASH_USER_PAGE_SIZE 512\r
+ #define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+ #define HRAMC1_SIZE 0xc00 /* 3 kB */\r
+\r
+#elif defined __SAM4LS4A__\r
+ #define FLASH_SIZE 0x40000 /* 256 kB */\r
+ #define FLASH_PAGE_SIZE 512\r
+ #define FLASH_NB_OF_PAGES 512\r
+ #define FLASH_USER_PAGE_SIZE 512\r
+ #define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+ #define HRAMC1_SIZE 0xc00 /* 3 kB */\r
+\r
+#elif defined __SAM4LS4B__\r
+ #define FLASH_SIZE 0x40000 /* 256 kB */\r
+ #define FLASH_PAGE_SIZE 512\r
+ #define FLASH_NB_OF_PAGES 512\r
+ #define FLASH_USER_PAGE_SIZE 512\r
+ #define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+ #define HRAMC1_SIZE 0xc00 /* 3 kB */\r
+\r
+#elif defined __SAM4LS4C__\r
+ #define FLASH_SIZE 0x40000 /* 256 kB */\r
+ #define FLASH_PAGE_SIZE 512\r
+ #define FLASH_NB_OF_PAGES 512\r
+ #define FLASH_USER_PAGE_SIZE 512\r
+ #define HRAMC0_SIZE 0x8000 /* 32 kB */\r
+ #define HRAMC1_SIZE 0xc00 /* 3 kB */\r
+#else\r
+ #error Library does not support the specified device.\r
+#endif\r
+\r
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */\r
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */\r
+#define HRAMC0_ADDR (0x20000000u) /**< HRAMC0 base address */\r
+#define HRAMC1_ADDR (0x21000000u) /**< HRAMC1 base address */\r
+\r
+#include "sam4l_patch_asf.h"\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* SAM4L_H */\r
projects / freertos / commitdiff