--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32h7xx_hal_dma_ex.c\r
+ * @author MCD Application Team\r
+ * @brief DMA Extension HAL module driver\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the DMA Extension peripheral:\r
+ * + Extended features functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The DMA Extension HAL driver can be used as follows:\r
+ (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function\r
+ for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.\r
+\r
+ (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.\r
+ (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.\r
+ Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used\r
+ to respectively enable/disable the request generator.\r
+\r
+ (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from\r
+ the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .\r
+ As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be\r
+ called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project\r
+ (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)\r
+\r
+ -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.\r
+ -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.\r
+ -@- In Multi (Double) buffer mode, it is possible to update the base address for\r
+ the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.\r
+ -@- Multi (Double) buffer mode is possible with DMA and BDMA instances.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32h7xx_hal.h"\r
+\r
+/** @addtogroup STM32H7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMAEx DMAEx\r
+ * @brief DMA Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private Constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup DMAEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup DMAEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+\r
+/** @addtogroup DMAEx_Exported_Functions_Group1\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the source, destination address and data length and\r
+ Start MultiBuffer DMA transfer\r
+ (+) Configure the source, destination address and data length and\r
+ Start MultiBuffer DMA transfer with interrupt\r
+ (+) Change on the fly the memory0 or memory1 address.\r
+ (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.\r
+ (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.\r
+ (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used\r
+ to respectively enable/disable the request generator.\r
+ (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from\r
+ the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Starts the multi_buffer DMA Transfer.\r
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+\r
+ /* Memory-to-memory transfer not supported in double buffering mode */\r
+ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Enable the Double buffer mode */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;\r
+\r
+ /* Calculate the interrupt clear flag register (IFCR) base address */\r
+ ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));\r
+\r
+ /* Clear all flags */\r
+ *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+ else /* BDMA instance(s) */\r
+ {\r
+ /* Enable the Double buffer mode */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;\r
+\r
+ /* Calculate the interrupt clear flag register (IFCR) base address */\r
+ ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));\r
+\r
+ /* Clear all flags */\r
+ *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+\r
+ /* Configure the source, destination address and the data length */\r
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ /* Clear the DMAMUX synchro overrun flag */\r
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+ if(hdma->DMAmuxRequestGen != 0U)\r
+ {\r
+ /* Clear the DMAMUX request generator overrun flag */\r
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+ }\r
+\r
+ /* Enable the peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Set the error code to busy */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));\r
+\r
+ /* Memory-to-memory transfer not supported in double buffering mode */\r
+ if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Enable the Double buffer mode */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;\r
+\r
+ /* Calculate the interrupt clear flag register (IFCR) base address */\r
+ ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));\r
+\r
+ /* Clear all flags */\r
+ *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+ else /* BDMA instance(s) */\r
+ {\r
+ /* Enable the Double buffer mode */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;\r
+\r
+ /* Calculate the interrupt clear flag register (IFCR) base address */\r
+ ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));\r
+\r
+ /* Clear all flags */\r
+ *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);\r
+ }\r
+\r
+ /* Configure the source, destination address and the data length */\r
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ /* Clear the DMAMUX synchro overrun flag */\r
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+ if(hdma->DMAmuxRequestGen != 0U)\r
+ {\r
+ /* Clear the DMAMUX request generator overrun flag */\r
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+ }\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Enable Common interrupts*/\r
+ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;\r
+\r
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r
+ {\r
+ /*Enable Half Transfer IT if corresponding Callback is set*/\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;\r
+ }\r
+ }\r
+ else /* BDMA instance(s) */\r
+ {\r
+ /* Enable Common interrupts*/\r
+ MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));\r
+\r
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r
+ {\r
+ /*Enable Half Transfer IT if corresponding Callback is set*/\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE;\r
+ }\r
+ }\r
+\r
+ /* Check if DMAMUX Synchronization is enabled*/\r
+ if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)\r
+ {\r
+ /* Enable DMAMUX sync overrun IT*/\r
+ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;\r
+ }\r
+\r
+ if(hdma->DMAmuxRequestGen != 0U)\r
+ {\r
+ /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/\r
+ /* enable the request gen overrun IT*/\r
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;\r
+ }\r
+\r
+ /* Enable the peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Set the error code to busy */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Change the memory0 or memory1 address on the fly.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param Address: The new address\r
+ * @param memory: the memory to be changed, This parameter can be one of\r
+ * the following values:\r
+ * MEMORY0 /\r
+ * MEMORY1\r
+ * @note The MEMORY0 address can be changed only when the current transfer use\r
+ * MEMORY1 and the MEMORY1 address can be changed only when the current\r
+ * transfer use MEMORY0.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)\r
+{\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ if(memory == MEMORY0)\r
+ {\r
+ /* change the memory0 address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address;\r
+ }\r
+ else\r
+ {\r
+ /* change the memory1 address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address;\r
+ }\r
+ }\r
+ else /* BDMA instance(s) */\r
+ {\r
+ if(memory == MEMORY0)\r
+ {\r
+ /* change the memory0 address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = Address;\r
+ }\r
+ else\r
+ {\r
+ /* change the memory1 address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = Address;\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance).\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)\r
+{\r
+ uint32_t syncSignalID = 0;\r
+ uint32_t syncPolarity = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));\r
+ assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));\r
+ assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));\r
+ assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));\r
+\r
+ if(pSyncConfig->SyncEnable == ENABLE)\r
+ {\r
+ assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));\r
+ }\r
+ syncSignalID = pSyncConfig->SyncSignalID;\r
+ syncPolarity = pSyncConfig->SyncPolarity;\r
+ }\r
+\r
+ /*Check if the DMA state is ready */\r
+ if(hdma->State == HAL_DMA_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ /* Disable the synchronization and event generation before applying a new config */\r
+ CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));\r
+\r
+ /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/\r
+ MODIFY_REG( hdma->DMAmuxChannel->CCR, \\r
+ (~DMAMUX_CxCR_DMAREQ_ID) , \\r
+ (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos) | \\r
+ ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \\r
+ syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \\r
+ ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));\r
+\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Set the error code to busy */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;\r
+\r
+ /* Return error status */\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMAMUX request generator block used by the given DMA stream (instance).\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :\r
+ * contains the request generator parameters.\r
+ *\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)\r
+{\r
+ HAL_StatusTypeDef status;\r
+ HAL_DMA_StateTypeDef temp_state = hdma->State;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));\r
+\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));\r
+ }\r
+\r
+\r
+ assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));\r
+ assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));\r
+\r
+ /* check if the DMA state is ready\r
+ and DMA is using a DMAMUX request generator block\r
+ */\r
+ if(hdma->DMAmuxRequestGen == 0U)\r
+ {\r
+ /* Set the error code to busy */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_PARAM;\r
+\r
+ /* error status */\r
+ status = HAL_ERROR;\r
+ }\r
+ else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))\r
+ {\r
+ /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ /* Set the request generator new parameters */\r
+ hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \\r
+ ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \\r
+ pRequestGeneratorConfig->Polarity;\r
+ /* Process Locked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Set the error code to busy */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;\r
+\r
+ /* error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Enable the DMAMUX request generator block used by the given DMA stream (instance).\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));\r
+\r
+ /* check if the DMA state is ready\r
+ and DMA is using a DMAMUX request generator block */\r
+ if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))\r
+ {\r
+ /* Enable the request generator*/\r
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable the DMAMUX request generator block used by the given DMA stream (instance).\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));\r
+\r
+ /* check if the DMA state is ready\r
+ and DMA is using a DMAMUX request generator block */\r
+ if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))\r
+ {\r
+ /* Disable the request generator*/\r
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Handles DMAMUX interrupt request.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval None\r
+ */\r
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* Check for DMAMUX Synchronization overrun */\r
+ if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)\r
+ {\r
+ /* Disable the synchro overrun interrupt */\r
+ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;\r
+\r
+ /* Clear the DMAMUX synchro overrun flag */\r
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;\r
+\r
+ if(hdma->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error callback */\r
+ hdma->XferErrorCallback(hdma);\r
+ }\r
+ }\r
+\r
+ if(hdma->DMAmuxRequestGen != 0)\r
+ {\r
+ /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */\r
+ if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)\r
+ {\r
+ /* Disable the request gen overrun interrupt */\r
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;\r
+\r
+ /* Clear the DMAMUX request generator overrun flag */\r
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;\r
+\r
+ if(hdma->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error callback */\r
+ hdma->XferErrorCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMAEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the DMA Transfer parameter.\r
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress: The source memory Buffer address\r
+ * @param DstAddress: The destination memory Buffer address\r
+ * @param DataLength: The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */\r
+ {\r
+ /* Configure DMA Stream data length */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;\r
+\r
+ /* Peripheral to Memory */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ {\r
+ /* Configure DMA Stream destination address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;\r
+\r
+ /* Configure DMA Stream source address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;\r
+ }\r
+ /* Memory to Peripheral */\r
+ else\r
+ {\r
+ /* Configure DMA Stream source address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;\r
+ }\r
+ }\r
+ else /* BDMA instance(s) */\r
+ {\r
+ /* Configure DMA Stream data length */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;\r
+\r
+ /* Peripheral to Memory */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ {\r
+ /* Configure DMA Stream destination address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;\r
+\r
+ /* Configure DMA Stream source address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;\r
+ }\r
+ /* Memory to Peripheral */\r
+ else\r
+ {\r
+ /* Configure DMA Stream source address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;\r
+\r
+ /* Configure DMA Stream destination address */\r
+ ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff