--- /dev/null
+/**************************************************************************//**\r
+ * @file dac_reg.h\r
+ * @version V1.00\r
+ * @brief DAC register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __DAC_REG_H__\r
+#define __DAC_REG_H__\r
+\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Digital to Analog Converter -------------------------*/\r
+/**\r
+ @addtogroup DAC Digital to Analog Converter(DAC)\r
+ Memory Mapped Structure for DAC Controller\r
+@{ */\r
+\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+\r
+ /**\r
+ * @var DAC_T::CTL\r
+ * Offset: 0x00 DAC Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |DACEN |DAC Enable Bit\r
+ * | | |0 = DAC is Disabled.\r
+ * | | |1 = DAC is Enabled.\r
+ * |[1] |DACIEN |DAC Interrupt Enable Bit\r
+ * | | |0 = Interrupt is Disabled.\r
+ * | | |1 = Interrupt is Enabled.\r
+ * |[2] |DMAEN |DMA Mode Enable Bit\r
+ * | | |0 = DMA mode Disabled.\r
+ * | | |1 = DMA mode Enabled.\r
+ * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit\r
+ * | | |0 = DMA under-run interrupt Disabled.\r
+ * | | |1 = DMA under-run interrupt Enabled.\r
+ * |[4] |TRGEN |Trigger Mode Enable Bit\r
+ * | | |0 = DAC event trigger mode Disabled.\r
+ * | | |1 = DAC event trigger mode Enabled.\r
+ * |[7:5] |TRGSEL |Trigger Source Selection\r
+ * | | |000 = Software trigger.\r
+ * | | |001 = External pin DAC0_ST trigger.\r
+ * | | |010 = Timer 0 trigger.\r
+ * | | |011 = Timer 1 trigger.\r
+ * | | |100 = Timer 2 trigger.\r
+ * | | |101 = Timer 3 trigger.\r
+ * | | |110 = EPWM0 trigger.\r
+ * | | |111 = EPWM1 trigger.\r
+ * |[8] |BYPASS |Bypass Buffer Mode\r
+ * | | |0 = Output voltage buffer Enabled.\r
+ * | | |1 = Output voltage buffer Disabled.\r
+ * |[10] |LALIGN |DAC Data Left-aligned Enabled Control\r
+ * | | |0 = Right alignment.\r
+ * | | |1 = Left alignment.\r
+ * |[13:12] |ETRGSEL |External Pin Trigger Selection\r
+ * | | |00 = Low level trigger.\r
+ * | | |01 = High level trigger.\r
+ * | | |10 = Falling edge trigger.\r
+ * | | |11 = Rising edge trigger.\r
+ * |[15:14] |BWSEL |DAC Data Bit-width Selection\r
+ * | | |00 = data is 12 bits.\r
+ * | | |01 = data is 8 bits.\r
+ * | | |Others = reserved.\r
+ * |[16] |GRPEN |DAC Group Mode Enable Bit\r
+ * | | |0 = DAC0 and DAC1 are not grouped.\r
+ * | | |1 = DAC0 and DAC1 are grouped.\r
+ * @var DAC_T::SWTRG\r
+ * Offset: 0x04 DAC Software Trigger Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SWTRG |Software Trigger\r
+ * | | |0 = Software trigger Disabled.\r
+ * | | |1 = Software trigger Enabled.\r
+ * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.\r
+ * @var DAC_T::DAT\r
+ * Offset: 0x08 DAC Data Holding Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |DACDAT |DAC 12-bit Holding Data\r
+ * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output.\r
+ * | | |The unused bits (DACDAT[3:0] in left-alignment mode and DACDAT[15:12] in right alignment mode) are ignored by DAC controller hardware.\r
+ * | | |12 bit left alignment: user has to load data into DACDAT[15:4] bits.\r
+ * | | |12 bit right alignment: user has to load data into DACDAT[11:0] bits.\r
+ * @var DAC_T::DATOUT\r
+ * Offset: 0x0C DAC Data Output Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[11:0] |DATOUT |DAC 12-bit Output Data\r
+ * | | |These bits are current digital data for DAC output conversion.\r
+ * | | |It is loaded from DAC_DAT register and user cannot write it directly.\r
+ * @var DAC_T::STATUS\r
+ * Offset: 0x10 DAC Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |FINISH |DAC Conversion Complete Finish Flag\r
+ * | | |0 = DAC is in conversion state.\r
+ * | | |1 = DAC conversion finish.\r
+ * | | |This bit set to 1 when conversion time counter counts to SETTLET.\r
+ * | | |It is cleared to 0 when DAC starts a new conversion.\r
+ * | | |User writes 1 to clear this bit to 0.\r
+ * |[1] |DMAUDR |DMA Under-run Interrupt Flag\r
+ * | | |0 = No DMA under-run error condition occurred.\r
+ * | | |1 = DMA under-run error condition occurred.\r
+ * | | |User writes 1 to clear this bit.\r
+ * |[8] |BUSY |DAC Busy Flag (Read Only)\r
+ * | | |0 = DAC is ready for next conversion.\r
+ * | | |1 = DAC is busy in conversion.\r
+ * | | |This is read only bit.\r
+ * @var DAC_T::TCTL\r
+ * Offset: 0x14 DAC Timing Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[9:0] |SETTLET |DAC Output Settling Time\r
+ * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\r
+ * | | |For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x40.\r
+ */\r
+ __IO uint32_t CTL; /*!< [0x0000] DAC Control Register */\r
+ __IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */\r
+ __IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */\r
+ __I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */\r
+ __IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */\r
+ __IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */\r
+\r
+} DAC_T;\r
+\r
+/**\r
+ @addtogroup DAC_CONST DAC Bit Field Definition\r
+ Constant Definitions for DAC Controller\r
+@{ */\r
+\r
+#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */\r
+#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */\r
+\r
+#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */\r
+#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */\r
+\r
+#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */\r
+#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */\r
+\r
+#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */\r
+#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */\r
+\r
+#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */\r
+#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */\r
+\r
+#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */\r
+#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */\r
+\r
+#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */\r
+#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */\r
+\r
+#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */\r
+#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */\r
+\r
+#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */\r
+#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */\r
+\r
+#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */\r
+#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */\r
+\r
+#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */\r
+#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */\r
+\r
+#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */\r
+#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */\r
+\r
+#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */\r
+#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */\r
+\r
+#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */\r
+#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */\r
+\r
+#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */\r
+#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */\r
+\r
+#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */\r
+#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */\r
+\r
+#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */\r
+#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */\r
+\r
+#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */\r
+#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */\r
+\r
+/**@}*/ /* DAC_CONST */\r
+/**@}*/ /* end of DAC register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __DAC_REG_H__ */\r
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