--- /dev/null
+/* ----------------------------------------------------------------------\r
+ * Project: CMSIS DSP Library\r
+ * Title: arm_common_tables.h\r
+ * Description: Extern declaration for common tables\r
+ *\r
+ * $Date: 27. January 2017\r
+ * $Revision: V.1.5.1\r
+ *\r
+ * Target Processor: Cortex-M cores\r
+ * -------------------------------------------------------------------- */\r
+/*\r
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef _ARM_COMMON_TABLES_H\r
+#define _ARM_COMMON_TABLES_H\r
+\r
+#include "arm_math.h"\r
+\r
+extern const uint16_t armBitRevTable[1024];\r
+extern const q15_t armRecipTableQ15[64];\r
+extern const q31_t armRecipTableQ31[64];\r
+extern const float32_t twiddleCoef_16[32];\r
+extern const float32_t twiddleCoef_32[64];\r
+extern const float32_t twiddleCoef_64[128];\r
+extern const float32_t twiddleCoef_128[256];\r
+extern const float32_t twiddleCoef_256[512];\r
+extern const float32_t twiddleCoef_512[1024];\r
+extern const float32_t twiddleCoef_1024[2048];\r
+extern const float32_t twiddleCoef_2048[4096];\r
+extern const float32_t twiddleCoef_4096[8192];\r
+#define twiddleCoef twiddleCoef_4096\r
+extern const q31_t twiddleCoef_16_q31[24];\r
+extern const q31_t twiddleCoef_32_q31[48];\r
+extern const q31_t twiddleCoef_64_q31[96];\r
+extern const q31_t twiddleCoef_128_q31[192];\r
+extern const q31_t twiddleCoef_256_q31[384];\r
+extern const q31_t twiddleCoef_512_q31[768];\r
+extern const q31_t twiddleCoef_1024_q31[1536];\r
+extern const q31_t twiddleCoef_2048_q31[3072];\r
+extern const q31_t twiddleCoef_4096_q31[6144];\r
+extern const q15_t twiddleCoef_16_q15[24];\r
+extern const q15_t twiddleCoef_32_q15[48];\r
+extern const q15_t twiddleCoef_64_q15[96];\r
+extern const q15_t twiddleCoef_128_q15[192];\r
+extern const q15_t twiddleCoef_256_q15[384];\r
+extern const q15_t twiddleCoef_512_q15[768];\r
+extern const q15_t twiddleCoef_1024_q15[1536];\r
+extern const q15_t twiddleCoef_2048_q15[3072];\r
+extern const q15_t twiddleCoef_4096_q15[6144];\r
+extern const float32_t twiddleCoef_rfft_32[32];\r
+extern const float32_t twiddleCoef_rfft_64[64];\r
+extern const float32_t twiddleCoef_rfft_128[128];\r
+extern const float32_t twiddleCoef_rfft_256[256];\r
+extern const float32_t twiddleCoef_rfft_512[512];\r
+extern const float32_t twiddleCoef_rfft_1024[1024];\r
+extern const float32_t twiddleCoef_rfft_2048[2048];\r
+extern const float32_t twiddleCoef_rfft_4096[4096];\r
+\r
+/* floating-point bit reversal tables */\r
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)\r
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)\r
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)\r
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)\r
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)\r
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)\r
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)\r
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)\r
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)\r
+\r
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];\r
+\r
+/* fixed-point bit reversal tables */\r
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)\r
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)\r
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)\r
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)\r
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)\r
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)\r
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)\r
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)\r
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)\r
+\r
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];\r
+\r
+/* Tables for Fast Math Sine and Cosine */\r
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];\r
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];\r
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];\r
+\r
+#endif /* ARM_COMMON_TABLES_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+ * Project: CMSIS DSP Library\r
+ * Title: arm_const_structs.h\r
+ * Description: Constant structs that are initialized for user convenience.\r
+ * For example, some can be given as arguments to the arm_cfft_f32() function.\r
+ *\r
+ * $Date: 27. January 2017\r
+ * $Revision: V.1.5.1\r
+ *\r
+ * Target Processor: Cortex-M cores\r
+ * -------------------------------------------------------------------- */\r
+/*\r
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef _ARM_CONST_STRUCTS_H\r
+#define _ARM_CONST_STRUCTS_H\r
+\r
+#include "arm_math.h"\r
+#include "arm_common_tables.h"\r
+\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;\r
+\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;\r
+\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;\r
+\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+ * Project: CMSIS DSP Library\r
+ * Title: arm_math.h\r
+ * Description: Public header file for CMSIS DSP Library\r
+ *\r
+ * $Date: 27. January 2017\r
+ * $Revision: V.1.5.1\r
+ *\r
+ * Target Processor: Cortex-M cores\r
+ * -------------------------------------------------------------------- */\r
+/*\r
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+/**\r
+ \mainpage CMSIS DSP Software Library\r
+ *\r
+ * Introduction\r
+ * ------------\r
+ *\r
+ * This user manual describes the CMSIS DSP software library,\r
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
+ *\r
+ * The library is divided into a number of functions each covering a specific category:\r
+ * - Basic math functions\r
+ * - Fast math functions\r
+ * - Complex math functions\r
+ * - Filters\r
+ * - Matrix functions\r
+ * - Transforms\r
+ * - Motor control functions\r
+ * - Statistical functions\r
+ * - Support functions\r
+ * - Interpolation functions\r
+ *\r
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
+ * 32-bit integer and 32-bit floating-point values.\r
+ *\r
+ * Using the Library\r
+ * ------------\r
+ *\r
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
+ * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)\r
+ * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)\r
+ * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)\r
+ * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)\r
+ * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)\r
+ * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)\r
+ * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)\r
+ * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)\r
+ * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)\r
+ * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)\r
+ * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)\r
+ * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)\r
+ * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)\r
+ * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)\r
+ * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)\r
+ * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)\r
+ * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)\r
+ * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)\r
+ * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)\r
+ *\r
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r
+ * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or\r
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\r
+ * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.\r
+ * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.\r
+ * \r
+ *\r
+ * Examples\r
+ * --------\r
+ *\r
+ * The library ships with a number of examples which demonstrate how to use the library functions.\r
+ *\r
+ * Toolchain Support\r
+ * ------------\r
+ *\r
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0\r
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
+ *\r
+ * Building the Library\r
+ * ------------\r
+ *\r
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.\r
+ * - arm_cortexM_math.uvprojx\r
+ *\r
+ *\r
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.\r
+ *\r
+ * Pre-processor Macros\r
+ * ------------\r
+ *\r
+ * Each library project have differant pre-processor macros.\r
+ *\r
+ * - UNALIGNED_SUPPORT_DISABLE:\r
+ *\r
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access\r
+ *\r
+ * - ARM_MATH_BIG_ENDIAN:\r
+ *\r
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
+ *\r
+ * - ARM_MATH_MATRIX_CHECK:\r
+ *\r
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\r
+ *\r
+ * - ARM_MATH_ROUNDING:\r
+ *\r
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions\r
+ *\r
+ * - ARM_MATH_CMx:\r
+ *\r
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and\r
+ * ARM_MATH_CM7 for building the library on cortex-M7.\r
+ *\r
+ * - ARM_MATH_ARMV8MxL:\r
+ *\r
+ * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library\r
+ * on ARMv8M Mainline target.\r
+ *\r
+ * - __FPU_PRESENT:\r
+ *\r
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.\r
+ *\r
+ * - __DSP_PRESENT:\r
+ *\r
+ * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.\r
+ *\r
+ * <hr>\r
+ * CMSIS-DSP in ARM::CMSIS Pack\r
+ * -----------------------------\r
+ *\r
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\r
+ * |File/Folder |Content |\r
+ * |------------------------------|------------------------------------------------------------------------|\r
+ * |\b CMSIS\\Documentation\\DSP | This documentation |\r
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |\r
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |\r
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |\r
+ *\r
+ * <hr>\r
+ * Revision History of CMSIS-DSP\r
+ * ------------\r
+ * Please refer to \ref ChangeLog_pg.\r
+ *\r
+ * Copyright Notice\r
+ * ------------\r
+ *\r
+ * Copyright (C) 2010-2015 ARM Limited. All rights reserved.\r
+ */\r
+\r
+\r
+/**\r
+ * @defgroup groupMath Basic Math Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFastMath Fast Math Functions\r
+ * This set of functions provides a fast approximation to sine, cosine, and square root.\r
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
+ * operate on individual values and not arrays.\r
+ * There are separate functions for Q15, Q31, and floating-point data.\r
+ *\r
+ */\r
+\r
+/**\r
+ * @defgroup groupCmplxMath Complex Math Functions\r
+ * This set of functions operates on complex data vectors.\r
+ * The data in the complex arrays is stored in an interleaved fashion\r
+ * (real, imag, real, imag, ...).\r
+ * In the API functions, the number of samples in a complex array refers\r
+ * to the number of complex values; the array contains twice this number of\r
+ * real values.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFilters Filtering Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupMatrix Matrix Functions\r
+ *\r
+ * This set of functions provides basic matrix math operations.\r
+ * The functions operate on matrix data structures. For example,\r
+ * the type\r
+ * definition for the floating-point matrix structure is shown\r
+ * below:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows; // number of rows of the matrix.\r
+ * uint16_t numCols; // number of columns of the matrix.\r
+ * float32_t *pData; // points to the data of the matrix.\r
+ * } arm_matrix_instance_f32;\r
+ * </pre>\r
+ * There are similar definitions for Q15 and Q31 data types.\r
+ *\r
+ * The structure specifies the size of the matrix and then points to\r
+ * an array of data. The array is of size <code>numRows X numCols</code>\r
+ * and the values are arranged in row order. That is, the\r
+ * matrix element (i, j) is stored at:\r
+ * <pre>\r
+ * pData[i*numCols + j]\r
+ * </pre>\r
+ *\r
+ * \par Init Functions\r
+ * There is an associated initialization function for each type of matrix\r
+ * data structure.\r
+ * The initialization function sets the values of the internal structure fields.\r
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.\r
+ *\r
+ * \par\r
+ * Use of the initialization function is optional. However, if initialization function is used\r
+ * then the instance structure cannot be placed into a const data section.\r
+ * To place the instance structure in a const data\r
+ * section, manually initialize the data structure. For example:\r
+ * <pre>\r
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
+ * </pre>\r
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
+ * specifies the number of columns, and <code>pData</code> points to the\r
+ * data array.\r
+ *\r
+ * \par Size Checking\r
+ * By default all of the matrix functions perform size checking on the input and\r
+ * output matrices. For example, the matrix addition function verifies that the\r
+ * two input matrices and the output matrix all have the same number of rows and\r
+ * columns. If the size check fails the functions return:\r
+ * <pre>\r
+ * ARM_MATH_SIZE_MISMATCH\r
+ * </pre>\r
+ * Otherwise the functions return\r
+ * <pre>\r
+ * ARM_MATH_SUCCESS\r
+ * </pre>\r
+ * There is some overhead associated with this matrix size checking.\r
+ * The matrix size checking is enabled via the \#define\r
+ * <pre>\r
+ * ARM_MATH_MATRIX_CHECK\r
+ * </pre>\r
+ * within the library project settings. By default this macro is defined\r
+ * and size checking is enabled. By changing the project settings and\r
+ * undefining this macro size checking is eliminated and the functions\r
+ * run a bit faster. With size checking disabled the functions always\r
+ * return <code>ARM_MATH_SUCCESS</code>.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupTransforms Transform Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupController Controller Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupStats Statistics Functions\r
+ */\r
+/**\r
+ * @defgroup groupSupport Support Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupInterpolation Interpolation Functions\r
+ * These functions perform 1- and 2-dimensional interpolation of data.\r
+ * Linear interpolation is used for 1-dimensional data and\r
+ * bilinear interpolation is used for 2-dimensional data.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupExamples Examples\r
+ */\r
+#ifndef _ARM_MATH_H\r
+#define _ARM_MATH_H\r
+\r
+/* Compiler specific diagnostic adjustment */\r
+#if defined ( __CC_ARM )\r
+\r
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+\r
+#elif defined ( __GNUC__ )\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+\r
+#elif defined ( __ICCARM__ )\r
+\r
+#elif defined ( __TI_ARM__ )\r
+\r
+#elif defined ( __CSMC__ )\r
+\r
+#elif defined ( __TASKING__ )\r
+\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+\r
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r
+\r
+#if defined(ARM_MATH_CM7)\r
+ #include "core_cm7.h"\r
+ #define ARM_MATH_DSP\r
+#elif defined (ARM_MATH_CM4)\r
+ #include "core_cm4.h"\r
+ #define ARM_MATH_DSP\r
+#elif defined (ARM_MATH_CM3)\r
+ #include "core_cm3.h"\r
+#elif defined (ARM_MATH_CM0)\r
+ #include "core_cm0.h"\r
+ #define ARM_MATH_CM0_FAMILY\r
+#elif defined (ARM_MATH_CM0PLUS)\r
+ #include "core_cm0plus.h"\r
+ #define ARM_MATH_CM0_FAMILY\r
+#elif defined (ARM_MATH_ARMV8MBL)\r
+ #include "core_armv8mbl.h"\r
+ #define ARM_MATH_CM0_FAMILY\r
+#elif defined (ARM_MATH_ARMV8MML)\r
+ #include "core_armv8mml.h"\r
+ #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))\r
+ #define ARM_MATH_DSP\r
+ #endif\r
+#else\r
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"\r
+#endif\r
+\r
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r
+#include "string.h"\r
+#include "math.h"\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Macros required for reciprocal calculation in Normalized LMS\r
+ */\r
+\r
+#define DELTA_Q31 (0x100)\r
+#define DELTA_Q15 0x5\r
+#define INDEX_MASK 0x0000003F\r
+#ifndef PI\r
+ #define PI 3.14159265358979f\r
+#endif\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Fast math approximations\r
+ */\r
+\r
+#define FAST_MATH_TABLE_SIZE 512\r
+#define FAST_MATH_Q31_SHIFT (32 - 10)\r
+#define FAST_MATH_Q15_SHIFT (16 - 10)\r
+#define CONTROLLER_Q31_SHIFT (32 - 9)\r
+#define TABLE_SPACING_Q31 0x400000\r
+#define TABLE_SPACING_Q15 0x80\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Controller functions\r
+ */\r
+ /* 1.31(q31) Fixed value of 2/360 */\r
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
+#define INPUT_SPACING 0xB60B61\r
+\r
+ /**\r
+ * @brief Macro for Unaligned Support\r
+ */\r
+#ifndef UNALIGNED_SUPPORT_DISABLE\r
+ #define ALIGN4\r
+#else\r
+ #if defined (__GNUC__)\r
+ #define ALIGN4 __attribute__((aligned(4)))\r
+ #else\r
+ #define ALIGN4 __align(4)\r
+ #endif\r
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */\r
+\r
+ /**\r
+ * @brief Error status returned by some functions in the library.\r
+ */\r
+\r
+ typedef enum\r
+ {\r
+ ARM_MATH_SUCCESS = 0, /**< No error */\r
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
+ } arm_status;\r
+\r
+ /**\r
+ * @brief 8-bit fractional data type in 1.7 format.\r
+ */\r
+ typedef int8_t q7_t;\r
+\r
+ /**\r
+ * @brief 16-bit fractional data type in 1.15 format.\r
+ */\r
+ typedef int16_t q15_t;\r
+\r
+ /**\r
+ * @brief 32-bit fractional data type in 1.31 format.\r
+ */\r
+ typedef int32_t q31_t;\r
+\r
+ /**\r
+ * @brief 64-bit fractional data type in 1.63 format.\r
+ */\r
+ typedef int64_t q63_t;\r
+\r
+ /**\r
+ * @brief 32-bit floating-point type definition.\r
+ */\r
+ typedef float float32_t;\r
+\r
+ /**\r
+ * @brief 64-bit floating-point type definition.\r
+ */\r
+ typedef double float64_t;\r
+\r
+ /**\r
+ * @brief definition to read/write two 16 bit values.\r
+ */\r
+#if defined ( __CC_ARM )\r
+ #define __SIMD32_TYPE int32_t __packed\r
+ #define CMSIS_UNUSED __attribute__((unused))\r
+ #define CMSIS_INLINE __attribute__((always_inline))\r
+\r
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+ #define __SIMD32_TYPE int32_t\r
+ #define CMSIS_UNUSED __attribute__((unused))\r
+ #define CMSIS_INLINE __attribute__((always_inline))\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __SIMD32_TYPE int32_t\r
+ #define CMSIS_UNUSED __attribute__((unused))\r
+ #define CMSIS_INLINE __attribute__((always_inline))\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __SIMD32_TYPE int32_t __packed\r
+ #define CMSIS_UNUSED\r
+ #define CMSIS_INLINE\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #define __SIMD32_TYPE int32_t\r
+ #define CMSIS_UNUSED __attribute__((unused))\r
+ #define CMSIS_INLINE\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __SIMD32_TYPE int32_t\r
+ #define CMSIS_UNUSED\r
+ #define CMSIS_INLINE\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __SIMD32_TYPE __unaligned int32_t\r
+ #define CMSIS_UNUSED\r
+ #define CMSIS_INLINE\r
+\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))\r
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))\r
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))\r
+#define __SIMD64(addr) (*(int64_t **) & (addr))\r
+\r
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r
+#if !defined (ARM_MATH_DSP)\r
+ /**\r
+ * @brief definition to pack two 16 bit values.\r
+ */\r
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \\r
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )\r
+\r
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r
+#endif /* !defined (ARM_MATH_DSP) */\r
+\r
+ /**\r
+ * @brief definition to pack four 8 bit values.\r
+ */\r
+#ifndef ARM_MATH_BIG_ENDIAN\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
+#else\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
+\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q31 values.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q15 values.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q7 values.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q15 values.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
+ */\r
+\r
+ CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(\r
+ q63_t x,\r
+ q31_t y)\r
+ {\r
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
+ (((q63_t) (x >> 32) * y)));\r
+ }\r
+\r
+/*\r
+ #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )\r
+ #define __CLZ __clz\r
+ #endif\r
+ */\r
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */\r
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(\r
+ q31_t data);\r
+\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(\r
+ q31_t data)\r
+ {\r
+ uint32_t count = 0;\r
+ uint32_t mask = 0x80000000;\r
+\r
+ while ((data & mask) == 0)\r
+ {\r
+ count += 1u;\r
+ mask = mask >> 1u;\r
+ }\r
+\r
+ return (count);\r
+ }\r
+#endif\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\r
+ */\r
+\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(\r
+ q31_t in,\r
+ q31_t * dst,\r
+ q31_t * pRecipTable)\r
+ {\r
+ q31_t out;\r
+ uint32_t tempVal;\r
+ uint32_t index, i;\r
+ uint32_t signBits;\r
+\r
+ if (in > 0)\r
+ {\r
+ signBits = ((uint32_t) (__CLZ( in) - 1));\r
+ }\r
+ else\r
+ {\r
+ signBits = ((uint32_t) (__CLZ(-in) - 1));\r
+ }\r
+\r
+ /* Convert input sample to 1.31 format */\r
+ in = (in << signBits);\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = (uint32_t)(in >> 24);\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.31 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0u; i < 2u; i++)\r
+ {\r
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);\r
+ tempVal = 0x7FFFFFFFu - tempVal;\r
+ /* 1.31 with exp 1 */\r
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */\r
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1u);\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(\r
+ q15_t in,\r
+ q15_t * dst,\r
+ q15_t * pRecipTable)\r
+ {\r
+ q15_t out = 0;\r
+ uint32_t tempVal = 0;\r
+ uint32_t index = 0, i = 0;\r
+ uint32_t signBits = 0;\r
+\r
+ if (in > 0)\r
+ {\r
+ signBits = ((uint32_t)(__CLZ( in) - 17));\r
+ }\r
+ else\r
+ {\r
+ signBits = ((uint32_t)(__CLZ(-in) - 17));\r
+ }\r
+\r
+ /* Convert input sample to 1.15 format */\r
+ in = (in << signBits);\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = (uint32_t)(in >> 8);\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.15 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0u; i < 2u; i++)\r
+ {\r
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);\r
+ tempVal = 0x7FFFu - tempVal;\r
+ /* 1.15 with exp 1 */\r
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1);\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinisic function for only M0 processors\r
+ */\r
+#if defined(ARM_MATH_CM0_FAMILY)\r
+ CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(\r
+ q31_t x,\r
+ uint32_t y)\r
+ {\r
+ int32_t posMax, negMin;\r
+ uint32_t i;\r
+\r
+ posMax = 1;\r
+ for (i = 0; i < (y - 1); i++)\r
+ {\r
+ posMax = posMax * 2;\r
+ }\r
+\r
+ if (x > 0)\r
+ {\r
+ posMax = (posMax - 1);\r
+\r
+ if (x > posMax)\r
+ {\r
+ x = posMax;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ negMin = -posMax;\r
+\r
+ if (x < negMin)\r
+ {\r
+ x = negMin;\r
+ }\r
+ }\r
+ return (x);\r
+ }\r
+#endif /* end of ARM_MATH_CM0_FAMILY */\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinsic function for M3 and M0 processors\r
+ */\r
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r
+#if !defined (ARM_MATH_DSP)\r
+\r
+ /*\r
+ * @brief C custom defined QADD8 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s, t, u;\r
+\r
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;\r
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;\r
+\r
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSUB8 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s, t, u;\r
+\r
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;\r
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;\r
+\r
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */\r
+ q31_t r = 0, s = 0;\r
+\r
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SHADD16 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSUB16 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SHSUB16 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QASX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SHASX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSAX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SHSAX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMUSDX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUADX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QADD for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE int32_t __QADD(\r
+ int32_t x,\r
+ int32_t y)\r
+ {\r
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSUB for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(\r
+ int32_t x,\r
+ int32_t y)\r
+ {\r
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLAD for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint32_t sum)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ( ((q31_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLADX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint32_t sum)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ( ((q31_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLSDX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint32_t sum)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ( ((q31_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLALD for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint64_t sum)\r
+ {\r
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */\r
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ( ((q63_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLALDX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint64_t sum)\r
+ {\r
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */\r
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ( ((q63_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMUAD for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMUSD for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SXTB16 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(\r
+ uint32_t x)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |\r
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMMLA for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(\r
+ int32_t x,\r
+ int32_t y,\r
+ int32_t sum)\r
+ {\r
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));\r
+ }\r
+\r
+#if 0\r
+ /*\r
+ * @brief C custom defined PKHBT for unavailable DSP extension\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint32_t leftshift)\r
+ {\r
+ return ( ((x ) & 0x0000FFFFUL) |\r
+ ((y << leftshift) & 0xFFFF0000UL) );\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined PKHTB for unavailable DSP extension\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint32_t rightshift)\r
+ {\r
+ return ( ((x ) & 0xFFFF0000UL) |\r
+ ((y >> rightshift) & 0x0000FFFFUL) );\r
+ }\r
+#endif\r
+\r
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r
+#endif /* !defined (ARM_MATH_DSP) */\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q7;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 FIR filter.\r
+ * @param[in] S points to an instance of the Q7 FIR filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_q7(\r
+ const arm_fir_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 FIR filter.\r
+ * @param[in,out] S points to an instance of the Q7 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed.\r
+ */\r
+ void arm_fir_init_q7(\r
+ arm_fir_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR filter.\r
+ * @param[in] S points to an instance of the Q15 FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_fast_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR filter.\r
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>numTaps</code> is not a supported value.\r
+ */\r
+ arm_status arm_fir_init_q15(\r
+ arm_fir_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR filter.\r
+ * @param[in] S points to an instance of the Q31 FIR filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q31 FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_fast_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR filter.\r
+ * @param[in,out] S points to an instance of the Q31 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ */\r
+ void arm_fir_init_q31(\r
+ arm_fir_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR filter.\r
+ * @param[in] S points to an instance of the floating-point FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_f32(\r
+ const arm_fir_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR filter.\r
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ */\r
+ void arm_fir_init_f32(\r
+ arm_fir_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+ } arm_biquad_casd_df1_inst_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+ } arm_biquad_casd_df1_inst_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_casd_df1_inst_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 Biquad cascade filter.\r
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ */\r
+ void arm_biquad_cascade_df1_init_q15(\r
+ arm_biquad_casd_df1_inst_q15 * S,\r
+ uint8_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_fast_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 Biquad cascade filter\r
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_fast_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ */\r
+ void arm_biquad_cascade_df1_init_q31(\r
+ arm_biquad_casd_df1_inst_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point Biquad cascade filter.\r
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_f32(\r
+ const arm_biquad_casd_df1_inst_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ */\r
+ void arm_biquad_cascade_df1_init_f32(\r
+ arm_biquad_casd_df1_inst_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float32_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float64_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f64;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 matrix structure.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q15_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 matrix structure.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q31_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_q31;\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix addition.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_add_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix addition.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_add_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix addition.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_add_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point, complex, matrix multiplication.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_cmplx_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15, complex, matrix multiplication.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_cmplx_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pScratch);\r
+\r
+\r
+ /**\r
+ * @brief Q31, complex, matrix multiplication.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_cmplx_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix transpose.\r
+ * @param[in] pSrc points to the input matrix\r
+ * @param[out] pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_trans_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix transpose.\r
+ * @param[in] pSrc points to the input matrix\r
+ * @param[out] pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_trans_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix transpose.\r
+ * @param[in] pSrc points to the input matrix\r
+ * @param[out] pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_trans_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix multiplication\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @param[in] pState points to the array for storing intermediate results\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @param[in] pState points to the array for storing intermediate results\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_mult_fast_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_mult_fast_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix subtraction\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_sub_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix subtraction\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_sub_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix subtraction\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_sub_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix scaling.\r
+ * @param[in] pSrc points to the input matrix\r
+ * @param[in] scale scale factor\r
+ * @param[out] pDst points to the output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_scale_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ float32_t scale,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix scaling.\r
+ * @param[in] pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_scale_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ q15_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix scaling.\r
+ * @param[in] pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_scale_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ q31_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix initialization.\r
+ * @param[in,out] S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] pData points to the matrix data array.\r
+ */\r
+ void arm_mat_init_q31(\r
+ arm_matrix_instance_q31 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q31_t * pData);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix initialization.\r
+ * @param[in,out] S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] pData points to the matrix data array.\r
+ */\r
+ void arm_mat_init_q15(\r
+ arm_matrix_instance_q15 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q15_t * pData);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix initialization.\r
+ * @param[in,out] S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] pData points to the matrix data array.\r
+ */\r
+ void arm_mat_init_f32(\r
+ arm_matrix_instance_f32 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ float32_t * pData);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+#if !defined (ARM_MATH_DSP)\r
+ q15_t A1;\r
+ q15_t A2;\r
+#else\r
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
+#endif\r
+ q15_t state[3]; /**< The state array of length 3. */\r
+ q15_t Kp; /**< The proportional gain. */\r
+ q15_t Ki; /**< The integral gain. */\r
+ q15_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ q31_t A2; /**< The derived gain, A2 = Kd . */\r
+ q31_t state[3]; /**< The state array of length 3. */\r
+ q31_t Kp; /**< The proportional gain. */\r
+ q31_t Ki; /**< The integral gain. */\r
+ q31_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ float32_t A2; /**< The derived gain, A2 = Kd . */\r
+ float32_t state[3]; /**< The state array of length 3. */\r
+ float32_t Kp; /**< The proportional gain. */\r
+ float32_t Ki; /**< The integral gain. */\r
+ float32_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point PID Control.\r
+ * @param[in,out] S points to an instance of the PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ */\r
+ void arm_pid_init_f32(\r
+ arm_pid_instance_f32 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the floating-point PID Control.\r
+ * @param[in,out] S is an instance of the floating-point PID Control structure\r
+ */\r
+ void arm_pid_reset_f32(\r
+ arm_pid_instance_f32 * S);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 PID Control.\r
+ * @param[in,out] S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ */\r
+ void arm_pid_init_q31(\r
+ arm_pid_instance_q31 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the Q31 PID Control.\r
+ * @param[in,out] S points to an instance of the Q31 PID Control structure\r
+ */\r
+\r
+ void arm_pid_reset_q31(\r
+ arm_pid_instance_q31 * S);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 PID Control.\r
+ * @param[in,out] S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ */\r
+ void arm_pid_init_q15(\r
+ arm_pid_instance_q15 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the Q15 PID Control.\r
+ * @param[in,out] S points to an instance of the q15 PID Control structure\r
+ */\r
+ void arm_pid_reset_q15(\r
+ arm_pid_instance_q15 * S);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Linear Interpolate function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t nValues; /**< nValues */\r
+ float32_t x1; /**< x1 */\r
+ float32_t xSpacing; /**< xSpacing */\r
+ float32_t *pYData; /**< pointer to the table of Y values */\r
+ } arm_linear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point bilinear interpolation function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ float32_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 bilinear interpolation function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q31_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q15_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q7_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q7;\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector multiplication.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_mult_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q15 vector multiplication.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_mult_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q31 vector multiplication.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_mult_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point vector multiplication.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_mult_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix2_instance_q15;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_q15(\r
+ arm_cfft_radix2_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_q15(\r
+ const arm_cfft_radix2_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q15;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_q15(\r
+ arm_cfft_radix4_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_q15(\r
+ const arm_cfft_radix4_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix2_instance_q31;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_q31(\r
+ arm_cfft_radix2_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_q31(\r
+ const arm_cfft_radix2_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q31;\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_q31(\r
+ const arm_cfft_radix4_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_q31(\r
+ arm_cfft_radix4_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix2_instance_f32;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_f32(\r
+ arm_cfft_radix2_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_f32(\r
+ const arm_cfft_radix2_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix4_instance_f32;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_f32(\r
+ arm_cfft_radix4_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_f32(\r
+ const arm_cfft_radix4_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_q15;\r
+\r
+void arm_cfft_q15(\r
+ const arm_cfft_instance_q15 * S,\r
+ q15_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_q31;\r
+\r
+void arm_cfft_q31(\r
+ const arm_cfft_instance_q31 * S,\r
+ q31_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_f32;\r
+\r
+ void arm_cfft_f32(\r
+ const arm_cfft_instance_f32 * S,\r
+ float32_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q15;\r
+\r
+ arm_status arm_rfft_init_q15(\r
+ arm_rfft_instance_q15 * S,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_q15(\r
+ const arm_rfft_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q31;\r
+\r
+ arm_status arm_rfft_init_q31(\r
+ arm_rfft_instance_q31 * S,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_q31(\r
+ const arm_rfft_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint16_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_f32;\r
+\r
+ arm_status arm_rfft_init_f32(\r
+ arm_rfft_instance_f32 * S,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_f32(\r
+ const arm_rfft_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+typedef struct\r
+ {\r
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */\r
+ uint16_t fftLenRFFT; /**< length of the real sequence */\r
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */\r
+ } arm_rfft_fast_instance_f32 ;\r
+\r
+arm_status arm_rfft_fast_init_f32 (\r
+ arm_rfft_fast_instance_f32 * S,\r
+ uint16_t fftLen);\r
+\r
+void arm_rfft_fast_f32(\r
+ arm_rfft_fast_instance_f32 * S,\r
+ float32_t * p, float32_t * pOut,\r
+ uint8_t ifftFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ float32_t normalize; /**< normalizing factor. */\r
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ float32_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point DCT4/IDCT4.\r
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.\r
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
+ */\r
+ arm_status arm_dct4_init_f32(\r
+ arm_dct4_instance_f32 * S,\r
+ arm_rfft_instance_f32 * S_RFFT,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ float32_t normalize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point DCT4/IDCT4.\r
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
+ */\r
+ void arm_dct4_f32(\r
+ const arm_dct4_instance_f32 * S,\r
+ float32_t * pState,\r
+ float32_t * pInlineBuffer);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q31_t normalize; /**< normalizing factor. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q31_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q31;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 DCT4/IDCT4.\r
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.\r
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+ arm_status arm_dct4_init_q31(\r
+ arm_dct4_instance_q31 * S,\r
+ arm_rfft_instance_q31 * S_RFFT,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q31_t normalize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 DCT4/IDCT4.\r
+ * @param[in] S points to an instance of the Q31 DCT4 structure.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
+ */\r
+ void arm_dct4_q31(\r
+ const arm_dct4_instance_q31 * S,\r
+ q31_t * pState,\r
+ q31_t * pInlineBuffer);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q15_t normalize; /**< normalizing factor. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q15_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 DCT4/IDCT4.\r
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.\r
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+ arm_status arm_dct4_init_q15(\r
+ arm_dct4_instance_q15 * S,\r
+ arm_rfft_instance_q15 * S_RFFT,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q15_t normalize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 DCT4/IDCT4.\r
+ * @param[in] S points to an instance of the Q15 DCT4 structure.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
+ */\r
+ void arm_dct4_q15(\r
+ const arm_dct4_instance_q15 * S,\r
+ q15_t * pState,\r
+ q15_t * pInlineBuffer);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point vector addition.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_add_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector addition.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_add_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q15 vector addition.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_add_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q31 vector addition.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_add_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point vector subtraction.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_sub_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector subtraction.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_sub_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q15 vector subtraction.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_sub_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q31 vector subtraction.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_sub_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Multiplies a floating-point vector by a scalar.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] scale scale factor to be applied\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_scale_f32(\r
+ float32_t * pSrc,\r
+ float32_t scale,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Multiplies a Q7 vector by a scalar.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_scale_q7(\r
+ q7_t * pSrc,\r
+ q7_t scaleFract,\r
+ int8_t shift,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Multiplies a Q15 vector by a scalar.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_scale_q15(\r
+ q15_t * pSrc,\r
+ q15_t scaleFract,\r
+ int8_t shift,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Multiplies a Q31 vector by a scalar.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_scale_q31(\r
+ q31_t * pSrc,\r
+ q31_t scaleFract,\r
+ int8_t shift,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector absolute value.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[out] pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_abs_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point vector absolute value.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[out] pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_abs_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q15 vector absolute value.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[out] pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_abs_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q31 vector absolute value.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[out] pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_abs_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Dot product of floating-point vectors.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] result output result returned here\r
+ */\r
+ void arm_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t blockSize,\r
+ float32_t * result);\r
+\r
+\r
+ /**\r
+ * @brief Dot product of Q7 vectors.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] result output result returned here\r
+ */\r
+ void arm_dot_prod_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q31_t * result);\r
+\r
+\r
+ /**\r
+ * @brief Dot product of Q15 vectors.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] result output result returned here\r
+ */\r
+ void arm_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+\r
+ /**\r
+ * @brief Dot product of Q31 vectors.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] result output result returned here\r
+ */\r
+ void arm_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_shift_q7(\r
+ q7_t * pSrc,\r
+ int8_t shiftBits,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_shift_q15(\r
+ q15_t * pSrc,\r
+ int8_t shiftBits,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_shift_q31(\r
+ q31_t * pSrc,\r
+ int8_t shiftBits,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a floating-point vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_offset_f32(\r
+ float32_t * pSrc,\r
+ float32_t offset,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q7 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_offset_q7(\r
+ q7_t * pSrc,\r
+ q7_t offset,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q15 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_offset_q15(\r
+ q15_t * pSrc,\r
+ q15_t offset,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q31 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_offset_q31(\r
+ q31_t * pSrc,\r
+ q31_t offset,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Negates the elements of a floating-point vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_negate_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q7 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_negate_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q15 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_negate_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q31 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_negate_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Copies the elements of a floating-point vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_copy_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q7 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_copy_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q15 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_copy_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q31 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_copy_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fills a constant value into a floating-point vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_fill_f32(\r
+ float32_t value,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q7 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_fill_q7(\r
+ q7_t value,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q15 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_fill_q15(\r
+ q15_t value,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q31 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_fill_q31(\r
+ q31_t value,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Convolution of floating-point sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ */\r
+ void arm_conv_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+/**\r
+ * @brief Convolution of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ */\r
+ void arm_conv_fast_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ */\r
+ void arm_conv_opt_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of floating-point sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_fast_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q7 sequences\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_opt_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+/**\r
+ * @brief Partial convolution of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR decimator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR decimator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR decimator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR decimator.\r
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_f32(\r
+ const arm_fir_decimate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR decimator.\r
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+ arm_status arm_fir_decimate_init_f32(\r
+ arm_fir_decimate_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator.\r
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_fast_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR decimator.\r
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+ arm_status arm_fir_decimate_init_q15(\r
+ arm_fir_decimate_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator.\r
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_q31(\r
+ const arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_fast_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR decimator.\r
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+ arm_status arm_fir_decimate_init_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR interpolator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR interpolator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR interpolator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
+ } arm_fir_interpolate_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR interpolator.\r
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_interpolate_q15(\r
+ const arm_fir_interpolate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR interpolator.\r
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+ arm_status arm_fir_interpolate_init_q15(\r
+ arm_fir_interpolate_instance_q15 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR interpolator.\r
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_interpolate_q31(\r
+ const arm_fir_interpolate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR interpolator.\r
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+ arm_status arm_fir_interpolate_init_q31(\r
+ arm_fir_interpolate_instance_q31 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR interpolator.\r
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_interpolate_f32(\r
+ const arm_fir_interpolate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR interpolator.\r
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+ arm_status arm_fir_interpolate_init_f32(\r
+ arm_fir_interpolate_instance_f32 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
+ } arm_biquad_cas_df1_32x64_ins_q31;\r
+\r
+\r
+ /**\r
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cas_df1_32x64_q31(\r
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
+ */\r
+ void arm_biquad_cas_df1_32x64_init_q31(\r
+ arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q63_t * pState,\r
+ uint8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_stereo_df2T_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f64;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] S points to an instance of the filter data structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df2T_f32(\r
+ const arm_biquad_cascade_df2T_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels\r
+ * @param[in] S points to an instance of the filter data structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_stereo_df2T_f32(\r
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] S points to an instance of the filter data structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df2T_f64(\r
+ const arm_biquad_cascade_df2T_instance_f64 * S,\r
+ float64_t * pSrc,\r
+ float64_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ */\r
+ void arm_biquad_cascade_df2T_init_f32(\r
+ arm_biquad_cascade_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ */\r
+ void arm_biquad_cascade_stereo_df2T_init_f32(\r
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ */\r
+ void arm_biquad_cascade_df2T_init_f64(\r
+ arm_biquad_cascade_df2T_instance_f64 * S,\r
+ uint8_t numStages,\r
+ float64_t * pCoeffs,\r
+ float64_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR lattice filter.\r
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages.\r
+ */\r
+ void arm_fir_lattice_init_q15(\r
+ arm_fir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR lattice filter.\r
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_lattice_q15(\r
+ const arm_fir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR lattice filter.\r
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages.\r
+ */\r
+ void arm_fir_lattice_init_q31(\r
+ arm_fir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR lattice filter.\r
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_lattice_q31(\r
+ const arm_fir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Initialization function for the floating-point FIR lattice filter.\r
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages.\r
+ */\r
+ void arm_fir_lattice_init_f32(\r
+ arm_fir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR lattice filter.\r
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_lattice_f32(\r
+ const arm_fir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point IIR lattice filter.\r
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_f32(\r
+ const arm_iir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point IIR lattice filter.\r
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_init_f32(\r
+ arm_iir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pkCoeffs,\r
+ float32_t * pvCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 IIR lattice filter.\r
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_q31(\r
+ const arm_iir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 IIR lattice filter.\r
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_init_q31(\r
+ arm_iir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pkCoeffs,\r
+ q31_t * pvCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 IIR lattice filter.\r
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_q15(\r
+ const arm_iir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Initialization function for the Q15 IIR lattice filter.\r
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process per call.\r
+ */\r
+ void arm_iir_lattice_init_q15(\r
+ arm_iir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pkCoeffs,\r
+ q15_t * pvCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that controls filter coefficient updates. */\r
+ } arm_lms_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for floating-point LMS filter.\r
+ * @param[in] S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_f32(\r
+ const arm_lms_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point LMS filter.\r
+ * @param[in] S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to the coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_init_f32(\r
+ arm_lms_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+ } arm_lms_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 LMS filter.\r
+ * @param[in] S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to the coefficient buffer.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ */\r
+ void arm_lms_init_q15(\r
+ arm_lms_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for Q15 LMS filter.\r
+ * @param[in] S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_q15(\r
+ const arm_lms_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+ } arm_lms_instance_q31;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for Q31 LMS filter.\r
+ * @param[in] S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_q31(\r
+ const arm_lms_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 LMS filter.\r
+ * @param[in] S points to an instance of the Q31 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ */\r
+ void arm_lms_init_q31(\r
+ arm_lms_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that control filter coefficient updates. */\r
+ float32_t energy; /**< saves previous frame energy. */\r
+ float32_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for floating-point normalized LMS filter.\r
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_norm_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point normalized LMS filter.\r
+ * @param[in] S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_norm_init_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
+ q31_t energy; /**< saves previous frame energy. */\r
+ q31_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q31;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for Q31 normalized LMS filter.\r
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_norm_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 normalized LMS filter.\r
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ */\r
+ void arm_lms_norm_init_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< Number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
+ q15_t energy; /**< saves previous frame energy. */\r
+ q15_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for Q15 normalized LMS filter.\r
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_norm_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q15 normalized LMS filter.\r
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ */\r
+ void arm_lms_norm_init_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of floating-point sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+ void arm_correlate_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ */\r
+ void arm_correlate_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+\r
+ void arm_correlate_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+\r
+ void arm_correlate_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ */\r
+ void arm_correlate_fast_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+ void arm_correlate_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+ void arm_correlate_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ */\r
+ void arm_correlate_opt_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+ void arm_correlate_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q7;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point sparse FIR filter.\r
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_sparse_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ float32_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point sparse FIR filter.\r
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] pCoeffs points to the array of filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ */\r
+ void arm_fir_sparse_init_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 sparse FIR filter.\r
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_sparse_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ q31_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 sparse FIR filter.\r
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] pCoeffs points to the array of filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ */\r
+ void arm_fir_sparse_init_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 sparse FIR filter.\r
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_sparse_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ q15_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 sparse FIR filter.\r
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] pCoeffs points to the array of filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ */\r
+ void arm_fir_sparse_init_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 sparse FIR filter.\r
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_sparse_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ q7_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 sparse FIR filter.\r
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] pCoeffs points to the array of filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ */\r
+ void arm_fir_sparse_init_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point sin_cos function.\r
+ * @param[in] theta input value in degrees\r
+ * @param[out] pSinVal points to the processed sine output.\r
+ * @param[out] pCosVal points to the processed cos output.\r
+ */\r
+ void arm_sin_cos_f32(\r
+ float32_t theta,\r
+ float32_t * pSinVal,\r
+ float32_t * pCosVal);\r
+\r
+\r
+ /**\r
+ * @brief Q31 sin_cos function.\r
+ * @param[in] theta scaled input value in degrees\r
+ * @param[out] pSinVal points to the processed sine output.\r
+ * @param[out] pCosVal points to the processed cosine output.\r
+ */\r
+ void arm_sin_cos_q31(\r
+ q31_t theta,\r
+ q31_t * pSinVal,\r
+ q31_t * pCosVal);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex conjugate.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_conj_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex conjugate.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_conj_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex conjugate.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_conj_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude squared\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_squared_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude squared\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_squared_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude squared\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_squared_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup PID PID Motor Control\r
+ *\r
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control\r
+ * loop mechanism widely used in industrial control systems.\r
+ * A PID controller is the most commonly used type of feedback controller.\r
+ *\r
+ * This set of functions implements (PID) controllers\r
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
+ * of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
+ * is the input sample value. The functions return the output value.\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
+ * A0 = Kp + Ki + Kd\r
+ * A1 = (-Kp ) - (2 * Kd )\r
+ * A2 = Kd </pre>\r
+ *\r
+ * \par\r
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
+ *\r
+ * \par\r
+ * \image html PID.gif "Proportional Integral Derivative Controller"\r
+ *\r
+ * \par\r
+ * The PID controller calculates an "error" value as the difference between\r
+ * the measured output and the reference input.\r
+ * The controller attempts to minimize the error by adjusting the process control inputs.\r
+ * The proportional value determines the reaction to the current error,\r
+ * the integral value determines the reaction based on the sum of recent errors,\r
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
+ *\r
+ * \par Instance Structure\r
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r
+ * A separate instance structure must be defined for each PID Controller.\r
+ * There are separate instance structure declarations for each of the 3 supported data types.\r
+ *\r
+ * \par Reset Functions\r
+ * There is also an associated reset function for each data type which clears the state array.\r
+ *\r
+ * \par Initialization Functions\r
+ * There is also an associated initialization function for each data type.\r
+ * The initialization function performs the following operations:\r
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
+ * - Zeros out the values in the state buffer.\r
+ *\r
+ * \par\r
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r
+ *\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.\r
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup PID\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point PID Control.\r
+ * @param[in,out] S is an instance of the floating-point PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(\r
+ arm_pid_instance_f32 * S,\r
+ float32_t in)\r
+ {\r
+ float32_t out;\r
+\r
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
+ out = (S->A0 * in) +\r
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q31 PID Control.\r
+ * @param[in,out] S points to an instance of the Q31 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 64-bit accumulator.\r
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r
+ * Thus, if the accumulator result overflows it wraps around rather than clip.\r
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(\r
+ arm_pid_instance_q31 * S,\r
+ q31_t in)\r
+ {\r
+ q63_t acc;\r
+ q31_t out;\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q63_t) S->A0 * in;\r
+\r
+ /* acc += A1 * x[n-1] */\r
+ acc += (q63_t) S->A1 * S->state[0];\r
+\r
+ /* acc += A2 * x[n-2] */\r
+ acc += (q63_t) S->A2 * S->state[1];\r
+\r
+ /* convert output to 1.31 format to add y[n-1] */\r
+ out = (q31_t) (acc >> 31u);\r
+\r
+ /* out += y[n-1] */\r
+ out += S->state[2];\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Process function for the Q15 PID Control.\r
+ * @param[in,out] S points to an instance of the Q15 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using a 64-bit internal accumulator.\r
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(\r
+ arm_pid_instance_q15 * S,\r
+ q15_t in)\r
+ {\r
+ q63_t acc;\r
+ q15_t out;\r
+\r
+#if defined (ARM_MATH_DSP)\r
+ __SIMD32_TYPE *vstate;\r
+\r
+ /* Implementation of PID controller */\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ vstate = __SIMD32_CONST(S->state);\r
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);\r
+#else\r
+ /* acc = A0 * x[n] */\r
+ acc = ((q31_t) S->A0) * in;\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc += (q31_t) S->A1 * S->state[0];\r
+ acc += (q31_t) S->A2 * S->state[1];\r
+#endif\r
+\r
+ /* acc += y[n-1] */\r
+ acc += (q31_t) S->state[2] << 15;\r
+\r
+ /* saturate the output */\r
+ out = (q15_t) (__SSAT((acc >> 15), 16));\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+ }\r
+\r
+ /**\r
+ * @} end of PID group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+ arm_status arm_mat_inverse_f32(\r
+ const arm_matrix_instance_f32 * src,\r
+ arm_matrix_instance_f32 * dst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+ arm_status arm_mat_inverse_f64(\r
+ const arm_matrix_instance_f64 * src,\r
+ arm_matrix_instance_f64 * dst);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup clarke Vector Clarke Transform\r
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
+ * \image html clarke.gif Stator current space vector and its components in (a,b).\r
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeFormula.gif\r
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point Clarke transform\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(\r
+ float32_t Ia,\r
+ float32_t Ib,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Clarke transform for Q31 version\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(\r
+ q31_t Ia,\r
+ q31_t Ib,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
+\r
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
+\r
+ /* pIbeta is calculated by adding the intermediate products */\r
+ *pIbeta = __QADD(product1, product2);\r
+ }\r
+\r
+ /**\r
+ * @} end of clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q31 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_q7_to_q31(\r
+ q7_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_clarke Vector Inverse Clarke Transform\r
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeInvFormula.gif\r
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Clarke transform\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pIa,\r
+ float32_t * pIb)\r
+ {\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Inverse Clarke transform for Q31 version\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the subtraction, hence there is no risk of overflow.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pIa,\r
+ q31_t * pIb)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
+\r
+ /* pIb is calculated by subtracting the products */\r
+ *pIb = __QSUB(product2, product1);\r
+ }\r
+\r
+ /**\r
+ * @} end of inv_clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q15 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_q7_to_q15(\r
+ q7_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup park Vector Park Transform\r
+ *\r
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r
+ * from the stationary to the moving reference frame and control the spatial relationship between\r
+ * the stator vector current and rotor flux vector.\r
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r
+ * current vector and the relationship from the two reference frames:\r
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkFormula.gif\r
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Park transform\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] pId points to output rotor reference frame d\r
+ * @param[out] pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ *\r
+ * The function implements the forward Park transform.\r
+ *\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_park_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pId,\r
+ float32_t * pIq,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
+ *pId = Ialpha * cosVal + Ibeta * sinVal;\r
+\r
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Park transform for Q31 version\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] pId points to output rotor reference frame d\r
+ * @param[out] pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_park_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pId,\r
+ q31_t * pIq,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Ialpha * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Ialpha * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pId by adding the two intermediate products 1 and 2 */\r
+ *pId = __QADD(product1, product2);\r
+\r
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
+ *pIq = __QSUB(product4, product3);\r
+ }\r
+\r
+ /**\r
+ * @} end of park group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q7_to_float(\r
+ q7_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_park Vector Inverse Park transform\r
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkInvFormula.gif\r
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Park transform\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(\r
+ float32_t Id,\r
+ float32_t Iq,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
+ *pIalpha = Id * cosVal - Iq * sinVal;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
+ *pIbeta = Id * sinVal + Iq * cosVal;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Inverse Park transform for Q31 version\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(\r
+ q31_t Id,\r
+ q31_t Iq,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Id * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Id * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
+ *pIalpha = __QSUB(product1, product2);\r
+\r
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
+ *pIbeta = __QADD(product4, product3);\r
+ }\r
+\r
+ /**\r
+ * @} end of Inverse park group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q31_to_float(\r
+ q31_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup LinearInterpolate Linear Interpolation\r
+ *\r
+ * Linear interpolation is a method of curve fitting using linear polynomials.\r
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
+ *\r
+ * \par\r
+ * \image html LinearInterp.gif "Linear interpolation"\r
+ *\r
+ * \par\r
+ * A Linear Interpolate function calculates an output value(y), for the input(x)\r
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
+ * where x0, x1 are nearest values of input x\r
+ * y0, y1 are nearest values to output y\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * This set of functions implements Linear interpolation process\r
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
+ * sample of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
+ * <code>x</code> is the input sample value. The functions returns the output value.\r
+ *\r
+ * \par\r
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table\r
+ * if x is below input range and returns last value of table if x is above range.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup LinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point Linear Interpolation Function.\r
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure\r
+ * @param[in] x input sample to process\r
+ * @return y processed output sample.\r
+ *\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(\r
+ arm_linear_interp_instance_f32 * S,\r
+ float32_t x)\r
+ {\r
+ float32_t y;\r
+ float32_t x0, x1; /* Nearest input values */\r
+ float32_t y0, y1; /* Nearest output values */\r
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
+ int32_t i; /* Index variable */\r
+ float32_t *pYData = S->pYData; /* pointer to output table */\r
+\r
+ /* Calculation of index */\r
+ i = (int32_t) ((x - S->x1) / xSpacing);\r
+\r
+ if (i < 0)\r
+ {\r
+ /* Iniatilize output for below specified range as least output value of table */\r
+ y = pYData[0];\r
+ }\r
+ else if ((uint32_t)i >= S->nValues)\r
+ {\r
+ /* Iniatilize output for above specified range as last output value of table */\r
+ y = pYData[S->nValues - 1];\r
+ }\r
+ else\r
+ {\r
+ /* Calculation of nearest input values */\r
+ x0 = S->x1 + i * xSpacing;\r
+ x1 = S->x1 + (i + 1) * xSpacing;\r
+\r
+ /* Read of nearest output values */\r
+ y0 = pYData[i];\r
+ y1 = pYData[i + 1];\r
+\r
+ /* Calculation of output */\r
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\r
+\r
+ }\r
+\r
+ /* returns output value */\r
+ return (y);\r
+ }\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q31 Linear Interpolation Function.\r
+ * @param[in] pYData pointer to Q31 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(\r
+ q31_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q31_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & (q31_t)0xFFF00000) >> 20);\r
+\r
+ if (index >= (int32_t)(nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else if (index < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* shift left by 11 to keep fract in 1.31 format */\r
+ fract = (x & 0x000FFFFF) << 11;\r
+\r
+ /* Read two nearest output values from the index in 1.31(q31) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
+\r
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
+\r
+ /* Convert y to 1.31 format */\r
+ return (y << 1u);\r
+ }\r
+ }\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q15 Linear Interpolation Function.\r
+ * @param[in] pYData pointer to Q15 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(\r
+ q15_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q63_t y; /* output */\r
+ q15_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & (int32_t)0xFFF00000) >> 20);\r
+\r
+ if (index >= (int32_t)(nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else if (index < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
+ y = ((q63_t) y0 * (0xFFFFF - fract));\r
+\r
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
+ y += ((q63_t) y1 * (fract));\r
+\r
+ /* convert y to 1.15 format */\r
+ return (q15_t) (y >> 20);\r
+ }\r
+ }\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q7 Linear Interpolation Function.\r
+ * @param[in] pYData pointer to Q7 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(\r
+ q7_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q7_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ uint32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ if (x < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ index = (x >> 20) & 0xfff;\r
+\r
+ if (index >= (nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index and are in 1.7(q7) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1];\r
+\r
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
+ y = ((y0 * (0xFFFFF - fract)));\r
+\r
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
+ y += (y1 * fract);\r
+\r
+ /* convert y to 1.7(q7) format */\r
+ return (q7_t) (y >> 20);\r
+ }\r
+ }\r
+\r
+ /**\r
+ * @} end of LinearInterpolate group\r
+ */\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return sin(x).\r
+ */\r
+ float32_t arm_sin_f32(\r
+ float32_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+ q31_t arm_sin_q31(\r
+ q31_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+ q15_t arm_sin_q15(\r
+ q15_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return cos(x).\r
+ */\r
+ float32_t arm_cos_f32(\r
+ float32_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+ q31_t arm_cos_q31(\r
+ q31_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+ q15_t arm_cos_q15(\r
+ q15_t x);\r
+\r
+\r
+ /**\r
+ * @ingroup groupFastMath\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup SQRT Square Root\r
+ *\r
+ * Computes the square root of a number.\r
+ * There are separate functions for Q15, Q31, and floating-point data types.\r
+ * The square root function is computed using the Newton-Raphson algorithm.\r
+ * This is an iterative algorithm of the form:\r
+ * <pre>\r
+ * x1 = x0 - f(x0)/f'(x0)\r
+ * </pre>\r
+ * where <code>x1</code> is the current estimate,\r
+ * <code>x0</code> is the previous estimate, and\r
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
+ * For the square root function, the algorithm reduces to:\r
+ * <pre>\r
+ * x0 = in/2 [initial guess]\r
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
+ * </pre>\r
+ */\r
+\r
+\r
+ /**\r
+ * @addtogroup SQRT\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point square root function.\r
+ * @param[in] in input value.\r
+ * @param[out] pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(\r
+ float32_t in,\r
+ float32_t * pOut)\r
+ {\r
+ if (in >= 0.0f)\r
+ {\r
+\r
+#if (__FPU_USED == 1) && defined ( __CC_ARM )\r
+ *pOut = __sqrtf(in);\r
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\r
+ *pOut = __builtin_sqrtf(in);\r
+#elif (__FPU_USED == 1) && defined(__GNUC__)\r
+ *pOut = __builtin_sqrtf(in);\r
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)\r
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));\r
+#else\r
+ *pOut = sqrtf(in);\r
+#endif\r
+\r
+ return (ARM_MATH_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ *pOut = 0.0f;\r
+ return (ARM_MATH_ARGUMENT_ERROR);\r
+ }\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q31 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r
+ * @param[out] pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q31(\r
+ q31_t in,\r
+ q31_t * pOut);\r
+\r
+\r
+ /**\r
+ * @brief Q15 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r
+ * @param[out] pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q15(\r
+ q15_t in,\r
+ q15_t * pOut);\r
+\r
+ /**\r
+ * @} end of SQRT group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular write function.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const int32_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if (wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = (uint16_t)wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular Read function.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ int32_t * dst,\r
+ int32_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if (dst == (int32_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if (rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q15 Circular write function.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q15_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if (wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = (uint16_t)wOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q15 Circular Read function.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q15_t * dst,\r
+ q15_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if (dst == (q15_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if (rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular write function.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q7_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if (wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = (uint16_t)wOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular Read function.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q7_t * dst,\r
+ q7_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if (dst == (q7_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if (rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_power_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_power_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_power_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_power_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Mean value of a Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_mean_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Mean value of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_mean_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Mean value of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_mean_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Mean value of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_mean_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Variance of the elements of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_var_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_var_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_var_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_rms_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_rms_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_rms_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_std_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_std_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_std_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex dot product\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] realResult real part of the result returned here\r
+ * @param[out] imagResult imaginary part of the result returned here\r
+ */\r
+ void arm_cmplx_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q31_t * realResult,\r
+ q31_t * imagResult);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex dot product\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] realResult real part of the result returned here\r
+ * @param[out] imagResult imaginary part of the result returned here\r
+ */\r
+ void arm_cmplx_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q63_t * realResult,\r
+ q63_t * imagResult);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex dot product\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] realResult real part of the result returned here\r
+ * @param[out] imagResult imaginary part of the result returned here\r
+ */\r
+ void arm_cmplx_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t numSamples,\r
+ float32_t * realResult,\r
+ float32_t * imagResult);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex-by-real multiplication\r
+ * @param[in] pSrcCmplx points to the complex input vector\r
+ * @param[in] pSrcReal points to the real input vector\r
+ * @param[out] pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ */\r
+ void arm_cmplx_mult_real_q15(\r
+ q15_t * pSrcCmplx,\r
+ q15_t * pSrcReal,\r
+ q15_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex-by-real multiplication\r
+ * @param[in] pSrcCmplx points to the complex input vector\r
+ * @param[in] pSrcReal points to the real input vector\r
+ * @param[out] pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ */\r
+ void arm_cmplx_mult_real_q31(\r
+ q31_t * pSrcCmplx,\r
+ q31_t * pSrcReal,\r
+ q31_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-real multiplication\r
+ * @param[in] pSrcCmplx points to the complex input vector\r
+ * @param[in] pSrcReal points to the real input vector\r
+ * @param[out] pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ */\r
+ void arm_cmplx_mult_real_f32(\r
+ float32_t * pSrcCmplx,\r
+ float32_t * pSrcReal,\r
+ float32_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Minimum value of a Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] result is output pointer\r
+ * @param[in] index is the array index of the minimum value in the input buffer.\r
+ */\r
+ void arm_min_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * result,\r
+ uint32_t * index);\r
+\r
+\r
+ /**\r
+ * @brief Minimum value of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output pointer\r
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.\r
+ */\r
+ void arm_min_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+ /**\r
+ * @brief Minimum value of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output pointer\r
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.\r
+ */\r
+ void arm_min_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+ /**\r
+ * @brief Minimum value of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output pointer\r
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.\r
+ */\r
+ void arm_min_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+/**\r
+ * @brief Maximum value of a Q7 vector.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] pResult maximum value returned here\r
+ * @param[out] pIndex index of maximum value returned here\r
+ */\r
+ void arm_max_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+/**\r
+ * @brief Maximum value of a Q15 vector.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] pResult maximum value returned here\r
+ * @param[out] pIndex index of maximum value returned here\r
+ */\r
+ void arm_max_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+/**\r
+ * @brief Maximum value of a Q31 vector.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] pResult maximum value returned here\r
+ * @param[out] pIndex index of maximum value returned here\r
+ */\r
+ void arm_max_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+/**\r
+ * @brief Maximum value of a floating-point vector.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] pResult maximum value returned here\r
+ * @param[out] pIndex index of maximum value returned here\r
+ */\r
+ void arm_max_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex-by-complex multiplication\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_mult_cmplx_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex-by-complex multiplication\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_mult_cmplx_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-complex multiplication\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_mult_cmplx_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q31 vector.\r
+ * @param[in] pSrc points to the floating-point input vector\r
+ * @param[out] pDst points to the Q31 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ */\r
+ void arm_float_to_q31(\r
+ float32_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q15 vector.\r
+ * @param[in] pSrc points to the floating-point input vector\r
+ * @param[out] pDst points to the Q15 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ */\r
+ void arm_float_to_q15(\r
+ float32_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q7 vector.\r
+ * @param[in] pSrc points to the floating-point input vector\r
+ * @param[out] pDst points to the Q7 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ */\r
+ void arm_float_to_q7(\r
+ float32_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q31_to_q15(\r
+ q31_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q31_to_q7(\r
+ q31_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q15_to_float(\r
+ q15_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q15_to_q31(\r
+ q15_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q15_to_q7(\r
+ q15_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup BilinearInterpolate Bilinear Interpolation\r
+ *\r
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
+ * determines values between the grid points.\r
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
+ * Bilinear interpolation is often used in image processing to rescale images.\r
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
+ *\r
+ * <b>Algorithm</b>\r
+ * \par\r
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
+ * For floating-point, the instance structure is defined as:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows;\r
+ * uint16_t numCols;\r
+ * float32_t *pData;\r
+ * } arm_bilinear_interp_instance_f32;\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * where <code>numRows</code> specifies the number of rows in the table;\r
+ * <code>numCols</code> specifies the number of columns in the table;\r
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
+ *\r
+ * \par\r
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
+ * <pre>\r
+ * XF = floor(x)\r
+ * YF = floor(y)\r
+ * </pre>\r
+ * \par\r
+ * The interpolated output point is computed as:\r
+ * <pre>\r
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
+ * </pre>\r
+ * Note that the coordinates (x, y) contain integer and fractional components.\r
+ * The integer components specify which portion of the table to use while the\r
+ * fractional components control the interpolation processor.\r
+ *\r
+ * \par\r
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup BilinearInterpolate\r
+ * @{\r
+ */\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point bilinear interpolation.\r
+ * @param[in,out] S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate.\r
+ * @param[in] Y interpolation coordinate.\r
+ * @return out interpolated value.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(\r
+ const arm_bilinear_interp_instance_f32 * S,\r
+ float32_t X,\r
+ float32_t Y)\r
+ {\r
+ float32_t out;\r
+ float32_t f00, f01, f10, f11;\r
+ float32_t *pData = S->pData;\r
+ int32_t xIndex, yIndex, index;\r
+ float32_t xdiff, ydiff;\r
+ float32_t b1, b2, b3, b4;\r
+\r
+ xIndex = (int32_t) X;\r
+ yIndex = (int32_t) Y;\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* Calculation of index for two nearest points in X-direction */\r
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in X-direction */\r
+ f00 = pData[index];\r
+ f01 = pData[index + 1];\r
+\r
+ /* Calculation of index for two nearest points in Y-direction */\r
+ index = (xIndex - 1) + (yIndex) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in Y-direction */\r
+ f10 = pData[index];\r
+ f11 = pData[index + 1];\r
+\r
+ /* Calculation of intermediate values */\r
+ b1 = f00;\r
+ b2 = f01 - f00;\r
+ b3 = f10 - f00;\r
+ b4 = f00 - f01 - f10 + f11;\r
+\r
+ /* Calculation of fractional part in X */\r
+ xdiff = X - xIndex;\r
+\r
+ /* Calculation of fractional part in Y */\r
+ ydiff = Y - yIndex;\r
+\r
+ /* Calculation of bi-linear interpolated output */\r
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
+\r
+ /* return to application */\r
+ return (out);\r
+ }\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Q31 bilinear interpolation.\r
+ * @param[in,out] S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(\r
+ arm_bilinear_interp_instance_q31 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q31_t out; /* Temporary output */\r
+ q31_t acc = 0; /* output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q31_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q31_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left xfract by 11 to keep 1.31 format */\r
+ xfract = (X & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];\r
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left yfract by 11 to keep 1.31 format */\r
+ yfract = (Y & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];\r
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* Convert acc to 1.31(q31) format */\r
+ return ((q31_t)(acc << 2));\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q15 bilinear interpolation.\r
+ * @param[in,out] S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(\r
+ arm_bilinear_interp_instance_q15 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q15_t x1, x2, y1, y2; /* Nearest output values */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q15_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];\r
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];\r
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
+\r
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc = ((q63_t) out * (0xFFFFF - yfract));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r
+ acc += ((q63_t) out * (xfract));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* acc is in 13.51 format and down shift acc by 36 times */\r
+ /* Convert out to 1.15 format */\r
+ return ((q15_t)(acc >> 36));\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 bilinear interpolation.\r
+ * @param[in,out] S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(\r
+ arm_bilinear_interp_instance_q7 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q7_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q7_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & (q31_t)0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];\r
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & (q31_t)0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];\r
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
+ out = ((x1 * (0xFFFFF - xfract)));\r
+ acc = (((q63_t) out * (0xFFFFF - yfract)));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
+ out = ((x2 * (0xFFFFF - yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y1 * (0xFFFFF - xfract)));\r
+ acc += (((q63_t) out * (yfract)));\r
+\r
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y2 * (yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
+ return ((q7_t)(acc >> 40));\r
+ }\r
+\r
+ /**\r
+ * @} end of BilinearInterpolate group\r
+ */\r
+\r
+\r
+/* SMMLAR */\r
+#define multAcc_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
+\r
+/* SMMLSR */\r
+#define multSub_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
+\r
+/* SMMULR */\r
+#define mult_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\r
+\r
+/* SMMLA */\r
+#define multAcc_32x32_keep32(a, x, y) \\r
+ a += (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+/* SMMLS */\r
+#define multSub_32x32_keep32(a, x, y) \\r
+ a -= (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+/* SMMUL */\r
+#define mult_32x32_keep32(a, x, y) \\r
+ a = (q31_t) (((q63_t) x * y ) >> 32)\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ /* Enter low optimization region - place directly above function definition */\r
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("push") \\r
+ _Pragma ("O1")\r
+ #else\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #endif\r
+\r
+ /* Exit low optimization region - place directly after end of function definition */\r
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\r
+ #define LOW_OPTIMIZATION_EXIT \\r
+ _Pragma ("pop")\r
+ #else\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #endif\r
+\r
+ /* Enter low optimization region - place directly above function definition */\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+\r
+ /* Exit low optimization region - place directly after end of function definition */\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ __attribute__(( optimize("-O1") ))\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __ICCARM__ )\r
+ /* Enter low optimization region - place directly above function definition */\r
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("optimize=low")\r
+ #else\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #endif\r
+\r
+ /* Exit low optimization region - place directly after end of function definition */\r
+ #define LOW_OPTIMIZATION_EXIT\r
+\r
+ /* Enter low optimization region - place directly above function definition */\r
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("optimize=low")\r
+ #else\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #endif\r
+\r
+ /* Exit low optimization region - place directly after end of function definition */\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/* Compiler specific diagnostic adjustment */\r
+#if defined ( __CC_ARM )\r
+\r
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+\r
+#elif defined ( __GNUC__ )\r
+#pragma GCC diagnostic pop\r
+\r
+#elif defined ( __ICCARM__ )\r
+\r
+#elif defined ( __TI_ARM__ )\r
+\r
+#elif defined ( __CSMC__ )\r
+\r
+#elif defined ( __TASKING__ )\r
+\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+#endif /* _ARM_MATH_H */\r
+\r
+/**\r
+ *\r
+ * End of file.\r
+ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_armcc.h\r
+ * @brief CMSIS compiler ARMCC (ARM compiler V5) header file\r
+ * @version V5.0.2\r
+ * @date 13. February 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_ARMCC_H\r
+#define __CMSIS_ARMCC_H\r
+\r
+\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* CMSIS compiler control architecture macros */\r
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \\r
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )\r
+ #define __ARM_ARCH_6M__ 1\r
+#endif\r
+\r
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))\r
+ #define __ARM_ARCH_7M__ 1\r
+#endif\r
+\r
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))\r
+ #define __ARM_ARCH_7EM__ 1\r
+#endif\r
+\r
+ /* __ARM_ARCH_8M_BASE__ not applicable */\r
+ /* __ARM_ARCH_8M_MAIN__ not applicable */\r
+\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE __inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static __inline\r
+#endif\r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __declspec(noreturn)\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT __packed struct\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION __packed union\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __enable_irq(); */\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePriMax __ASM("basepri_max");\r
+ __regBasePriMax = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1U);\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#else\r
+ (void)fpscr;\r
+#endif\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+#define __ISB() do {\\r
+ __schedule_barrier();\\r
+ __isb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() do {\\r
+ __schedule_barrier();\\r
+ __dsb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() do {\\r
+ __schedule_barrier();\\r
+ __dmb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in integer value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in two unsigned short values.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Reverse byte order in signed short value\r
+ \details Reverses the byte order in a signed short value with sign extension to integer.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __breakpoint(value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+ #define __RBIT __rbit\r
+#else\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+#else\r
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXB(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXH(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXW(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r
+{\r
+ rrx r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRBT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRHT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRT(value, ptr) __strt(value, ptr)\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
+ ((int64_t)(ARG3) << 32U) ) >> 32U))\r
+\r
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCC_H */\r
--- /dev/null
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
+ * @version V5.0.3
+ * @date 27. March 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+/* #define __get_FPSCR __builtin_arm_get_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+/* #define __set_FPSCR __builtin_arm_set_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
+#else
+ (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __builtin_bswap32
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
--- /dev/null
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.0.2
+ * @date 13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * ARM Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+
+ #include <cmsis_iar.h>
+
+ /* CMSIS compiler control architecture macros */
+ #if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
+ #ifndef __ARM_ARCH_6M__
+ #define __ARM_ARCH_6M__ 1
+ #endif
+ #elif (__CORE__ == __ARM7M__)
+ #ifndef __ARM_ARCH_7M__
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #elif (__CORE__ == __ARM7EM__)
+ #ifndef __ARM_ARCH_7EM__
+ #define __ARM_ARCH_7EM__ 1
+ #endif
+ #endif
+
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __noreturn
+ #endif
+ #ifndef __USED
+ #define __USED __root
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ __packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ //#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ //#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+ // Workaround for missing __CLZ intrinsic in
+ // various versions of the IAR compilers.
+ // __IAR_FEATURE_CLZ__ should be defined by
+ // the compiler that supports __CLZ internally.
+ #if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
+ __STATIC_INLINE uint32_t __CLZ(uint32_t data)
+ {
+ if (data == 0u) { return 32u; }
+
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while ((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+ }
+ #endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include <cmsis_ccs.h>
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_gcc.h\r
+ * @brief CMSIS compiler GCC header file\r
+ * @version V5.0.2\r
+ * @date 13. February 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_GCC_H\r
+#define __CMSIS_GCC_H\r
+\r
+/* ignore some GCC warnings */\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+\r
+/* Fallback for __has_builtin */\r
+#ifndef __has_builtin\r
+ #define __has_builtin(x) (0)\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+#endif\r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((noreturn))\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Control Register (non-secure)\r
+ \details Returns the content of the non-secure Control Register when in secure mode.\r
+ \return non-secure Control Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Control Register (non-secure)\r
+ \details Writes the given value to the non-secure Control Register when in secure state.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \return PSP Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \return MSP Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
+}\r
+#endif\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
+ \return SP Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
+ \param [in] topOfStack Stack Pointer value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
+{\r
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Priority Mask (non-secure)\r
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+ \return Priority Mask value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Priority Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Base Priority (non-secure)\r
+ \details Returns the current value of the non-secure Base Priority register when in secure state.\r
+ \return Base Priority register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Base Priority (non-secure)\r
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Fault Mask (non-secure)\r
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Fault Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+/**\r
+ \brief Get Process Stack Pointer Limit\r
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
+ \return PSPLIM Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \\r
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Get Process Stack Pointer Limit (non-secure)\r
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \return PSPLIM Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer Limit\r
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
+{\r
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
+}\r
+\r
+\r
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \\r
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
+{\r
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer Limit\r
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
+ \return MSPLIM Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
+\r
+ return(result);\r
+}\r
+\r
+\r
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \\r
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Get Main Stack Pointer Limit (non-secure)\r
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
+ \return MSPLIM Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer Limit\r
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
+{\r
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
+}\r
+\r
+\r
+#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \\r
+ (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Set Main Stack Pointer Limit (non-secure)\r
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
+{\r
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
+ return __builtin_arm_get_fpscr();\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#endif\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
+ __builtin_arm_set_fpscr(fpscr);\r
+#else\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");\r
+#endif\r
+#else\r
+ (void)fpscr;\r
+#endif\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r
+//{\r
+// __ASM volatile ("nop");\r
+//}\r
+#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r
+//{\r
+// __ASM volatile ("wfi");\r
+//}\r
+#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r
+//{\r
+// __ASM volatile ("wfe");\r
+//}\r
+#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r
+//{\r
+// __ASM volatile ("sev");\r
+//}\r
+#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in integer value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in two unsigned short values.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order in signed short value\r
+ \details Reverses the byte order in a signed short value with sign extension to integer.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (short)__builtin_bswap16(value);\r
+#else\r
+ int32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+#else\r
+ int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __builtin_clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief Load-Acquire (8 bit)\r
+ \details Executes a LDAB instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (16 bit)\r
+ \details Executes a LDAH instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (32 bit)\r
+ \details Executes a LDA instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (8 bit)\r
+ \details Executes a STLB instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (16 bit)\r
+ \details Executes a STLH instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (32 bit)\r
+ \details Executes a STL instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (8 bit)\r
+ \details Executes a LDAB exclusive instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (16 bit)\r
+ \details Executes a LDAH exclusive instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (32 bit)\r
+ \details Executes a LDA exclusive instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (8 bit)\r
+ \details Executes a STLB exclusive instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (16 bit)\r
+ \details Executes a STLH exclusive instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (32 bit)\r
+ \details Executes a STL exclusive instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#if 0\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+#endif\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__ARM_FEATURE_DSP == 1) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#pragma GCC diagnostic pop\r
+\r
+#endif /* __CMSIS_GCC_H */\r
--- /dev/null
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_armv8mbl.h\r
+ * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File\r
+ * @version V5.0.2\r
+ * @date 19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_ARMV8MBL_H_GENERIC\r
+#define __CORE_ARMV8MBL_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_ARMv8MBL\r
+ @{\r
+ */\r
+ \r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS definitions */\r
+#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \\r
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M ( 2U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MBL_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT\r
+#define __CORE_ARMV8MBL_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __ARMv8MBL_REV\r
+ #define __ARMv8MBL_REV 0x0000U\r
+ #warning "__ARMv8MBL_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0U\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ETM_PRESENT\r
+ #define __ETM_PRESENT 0U\r
+ #warning "__ETM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MTB_PRESENT\r
+ #define __MTB_PRESENT 0U\r
+ #warning "__MTB_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group ARMv8MBL */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ uint32_t RESERVED0[6U];\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ uint32_t RESERVED0[7U];\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#endif\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */\r
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */\r
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ If VTOR is not present address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**
+ * @file core_armv8mml.h
+ * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MML
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS ARMv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (81U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MML_REV
+ #define __ARMv8MML_REV 0x0000U
+ #warning "__ARMv8MML_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0.h\r
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
+ * @version V5.0.2\r
+ * @date 19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM0_H_GENERIC\r
+#define __CORE_CM0_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M0\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+/* CMSIS CM0 definitions */\r
+#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0_H_DEPENDANT\r
+#define __CORE_CM0_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0_REV\r
+ #define __CM0_REV 0x0000U\r
+ #warning "__CM0_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M0 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31U];\r
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31U];\r
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31U];\r
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31U];\r
+ uint32_t RESERVED4[64U];\r
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ uint32_t RESERVED0;\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+ Therefore they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */\r
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ Address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0plus.h\r
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r
+ * @version V5.0.2\r
+ * @date 19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM0PLUS_H_GENERIC\r
+#define __CORE_CM0PLUS_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex-M0+\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+/* CMSIS CM0+ definitions */\r
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0PLUS_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0PLUS_H_DEPENDANT\r
+#define __CORE_CM0PLUS_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0PLUS_REV\r
+ #define __CM0PLUS_REV 0x0000U\r
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0U\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex-M0+ */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31U];\r
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31U];\r
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31U];\r
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31U];\r
+ uint32_t RESERVED4[64U];\r
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+ Therefore they are not covered by the Cortex-M0+ header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */\r
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ If VTOR is not present address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**
+ * @file core_cm23.h
+ * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M23
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (23U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM23_REV
+ #define __CM23_REV 0x0000U
+ #warning "__CM23_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V5.0.2\r
+ * @date 19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M3\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+/* CMSIS CM3 definitions */\r
+#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (3U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM3_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM3_H_DEPENDANT\r
+#define __CORE_CM3_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM3_REV\r
+ #define __CM3_REV 0x0200U\r
+ #warning "__CM3_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M3 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */\r
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#else\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1[1U];\r
+#endif\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**
+ * @file core_cm33.h
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M33
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM33_REV
+ #define __CM33_REV 0x0000U
+ #warning "__CM33_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V5.0.2\r
+ * @date 19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M4\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (4U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM4_REV\r
+ #define __CM4_REV 0x0000U\r
+ #warning "__CM4_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M4 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm7.h\r
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
+ * @version V5.0.2\r
+ * @date 19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM7_H_GENERIC\r
+#define __CORE_CM7_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M7\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS CM7 definitions */\r
+#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (7U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM7_H_DEPENDANT\r
+#define __CORE_CM7_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM7_REV\r
+ #define __CM7_REV 0x0000U\r
+ #warning "__CM7_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ICACHE_PRESENT\r
+ #define __ICACHE_PRESENT 0U\r
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DCACHE_PRESENT\r
+ #define __DCACHE_PRESENT 0U\r
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DTCM_PRESENT\r
+ #define __DTCM_PRESENT 0U\r
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M7 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ uint32_t RESERVED3[93U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */\r
+\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */\r
+\r
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */\r
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */\r
+\r
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */\r
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED3[981U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/* Media and FP Feature Register 2 Definitions */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = SCB->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+ {\r
+ return 2U; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## Cache functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
+ \brief Functions that configure Instruction and Data cache.\r
+ @{\r
+ */\r
+\r
+/* Cache Size ID Register Macros */\r
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )\r
+\r
+\r
+/**\r
+ \brief Enable I-Cache\r
+ \details Turns on I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableICache (void)\r
+{\r
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable I-Cache\r
+ \details Turns off I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableICache (void)\r
+{\r
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */\r
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Invalidate I-Cache\r
+ \details Invalidates I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateICache (void)\r
+{\r
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0UL;\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable D-Cache\r
+ \details Turns on D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+ __DSB();\r
+\r
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable D-Cache\r
+ \details Turns off D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ register uint32_t ccsidr;\r
+ register uint32_t sets;\r
+ register uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean & invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Invalidate D-Cache\r
+ \details Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Clean D-Cache\r
+ \details Cleans D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Clean & Invalidate D-Cache\r
+ \details Cleans and Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean & invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Invalidate by address\r
+ \details Invalidates D-Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t)addr;\r
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCIMVAC = op_addr;\r
+ op_addr += (uint32_t)linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Clean by address\r
+ \details Cleans D-Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCMVAC = op_addr;\r
+ op_addr += (uint32_t)linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Clean and Invalidate by address\r
+ \details Cleans and invalidates D_Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCIMVAC = op_addr;\r
+ op_addr += (uint32_t)linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_CacheFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_sc000.h\r
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File\r
+ * @version V5.0.2\r
+ * @date 19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_SC000_H_GENERIC\r
+#define __CORE_SC000_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup SC000\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS SC000 definitions */\r
+#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\r
+ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC (000U) /*!< Cortex secure core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC000_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC000_H_DEPENDANT\r
+#define __CORE_SC000_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __SC000_REV\r
+ #define __SC000_REV 0x0000U\r
+ #warning "__SC000_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group SC000 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31U];\r
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31U];\r
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31U];\r
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31U];\r
+ uint32_t RESERVED4[64U];\r
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ uint32_t RESERVED1[154U];\r
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+ Therefore they are not covered by the SC000 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */\r
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC000_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_sc300.h\r
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File\r
+ * @version V5.0.2\r
+ * @date 19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_SC300_H_GENERIC\r
+#define __CORE_SC300_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup SC3000\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS SC300 definitions */\r
+#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\r
+ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC (300U) /*!< Cortex secure core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC300_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC300_H_DEPENDANT\r
+#define __CORE_SC300_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __SC300_REV\r
+ #define __SC300_REV 0x0000U\r
+ #warning "__SC300_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group SC300 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ uint32_t RESERVED1[129U];\r
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ uint32_t RESERVED1[1U];\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC300_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for ARMv7 MPU
+ * @version V5.0.2
+ * @date 09. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
+
+#define ARM_MPU_AP_NONE 0u
+#define ARM_MPU_AP_PRIV 1u
+#define ARM_MPU_AP_URO 2u
+#define ARM_MPU_AP_FULL 3u
+#define ARM_MPU_AP_PRO 5u
+#define ARM_MPU_AP_RO 6u
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos))
+
+/**
+* MPU Region Attribut and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ((DisableExec << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ ((AccessPermission << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ ((TypeExtField << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ ((IsShareable << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ ((IsCacheable << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ ((IsBufferable << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
+ ((SubRegionDisable << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
+ ((Size << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
+ ((1UL << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk)
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct _ARM_MPU_Region_t {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable()
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0u;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0u; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u);
+}
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * $Date: 21. September 2016
+ * $Revision: V1.0
+ *
+ * Project: TrustZone for ARMv8-M
+ * Title: Context Management for ARMv8-M TrustZone
+ *
+ * Version 1.0
+ * Initial Release
+ *---------------------------------------------------------------------------*/
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include <stdint.h>
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H
--- /dev/null
+/**************************************************************************//**\r
+ * @file M2351.h\r
+ * @version V1.0\r
+ * @brief Peripheral Access Layer Header File\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+\r
+/**\r
+ \mainpage Introduction\r
+ *\r
+ *\r
+ * This user manual describes the usage of M2351 device driver\r
+ *\r
+ * <b>Disclaimer</b>\r
+ *\r
+ * The Software is furnished "AS IS", without warranty as to performance or results, and\r
+ * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all\r
+ * warranties, express, implied or otherwise, with regard to the Software, its use, or\r
+ * operation, including without limitation any and all warranties of merchantability, fitness\r
+ * for a particular purpose, and non-infringement of intellectual property rights.\r
+ *\r
+ * <b>Copyright Notice</b>\r
+ *\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ */\r
+\r
+\r
+#ifndef __M2351_H__\r
+#define __M2351_H__\r
+\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/******************************************************************************/\r
+/* Processor and Core Peripherals */\r
+/******************************************************************************/\r
+/** @addtogroup CMSIS_Device CMSIS Definitions\r
+ Configuration of the Cortex-M23 Processor and Core Peripherals\r
+ @{\r
+*/\r
+\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ---------- Interrupt Number Definition -----------------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+/**\r
+ * @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.\r
+ */\r
+typedef enum IRQn\r
+{\r
+ /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 3 Cortex-M23 Hard Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M23 SV Call Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M23 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M23 System Tick Interrupt */\r
+\r
+ /****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/\r
+\r
+ BOD_IRQn = 0, /*!< Brown Out detection Interrupt */\r
+ IRC_IRQn = 1, /*!< Internal RC Interrupt */\r
+ PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */\r
+ RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */\r
+ CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */\r
+ ISP_IRQn = 5, /*!< FMC ISP Interrupt */\r
+ RTC_IRQn = 6, /*!< Real Time Clock Interrupt */\r
+ TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */\r
+ WDT_IRQn = 8, /*!< Watchdog Timer Interrupt */\r
+ WWDT_IRQn = 9, /*!< Window Watchdog Timer Interrupt */\r
+ EINT0_IRQn = 10, /*!< External Input 0 Interrupt */\r
+ EINT1_IRQn = 11, /*!< External Input 1 Interrupt */\r
+ EINT2_IRQn = 12, /*!< External Input 2 Interrupt */\r
+ EINT3_IRQn = 13, /*!< External Input 3 Interrupt */\r
+ EINT4_IRQn = 14, /*!< External Input 4 Interrupt */\r
+ EINT5_IRQn = 15, /*!< External Input 5 Interrupt */\r
+ GPA_IRQn = 16, /*!< GPIO Port A Interrupt */\r
+ GPB_IRQn = 17, /*!< GPIO Port B Interrupt */\r
+ GPC_IRQn = 18, /*!< GPIO Port C Interrupt */\r
+ GPD_IRQn = 19, /*!< GPIO Port D Interrupt */\r
+ GPE_IRQn = 20, /*!< GPIO Port E Interrupt */\r
+ GPF_IRQn = 21, /*!< GPIO Port F Interrupt */\r
+ QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */\r
+ SPI0_IRQn = 23, /*!< SPI0 Interrupt */\r
+ BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */\r
+ EPWM0_P0_IRQn = 25, /*!< EPWM0P0 Interrupt */\r
+ EPWM0_P1_IRQn = 26, /*!< EPWM0P1 Interrupt */\r
+ EPWM0_P2_IRQn = 27, /*!< EPWM0P2 Interrupt */\r
+ BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */\r
+ EPWM1_P0_IRQn = 29, /*!< EPWM1P0 Interrupt */\r
+ EPWM1_P1_IRQn = 30, /*!< EPWM1P1 Interrupt */\r
+ EPWM1_P2_IRQn = 31, /*!< EPWM1P2 Interrupt */\r
+ TMR0_IRQn = 32, /*!< Timer 0 Interrupt */\r
+ TMR1_IRQn = 33, /*!< Timer 1 Interrupt */\r
+ TMR2_IRQn = 34, /*!< Timer 2 Interrupt */\r
+ TMR3_IRQn = 35, /*!< Timer 3 Interrupt */\r
+ UART0_IRQn = 36, /*!< UART 0 Interrupt */\r
+ UART1_IRQn = 37, /*!< UART 1 Interrupt */\r
+ I2C0_IRQn = 38, /*!< I2C 0 Interrupt */\r
+ I2C1_IRQn = 39, /*!< I2C 1 Interrupt */\r
+ PDMA0_IRQn = 40, /*!< Peripheral DMA 0 Interrupt */\r
+ DAC_IRQn = 41, /*!< DAC Interrupt */\r
+ EADC0_IRQn = 42, /*!< EADC Source 0 Interrupt */\r
+ EADC1_IRQn = 43, /*!< EADC Source 1 Interrupt */\r
+ ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */\r
+ EADC2_IRQn = 46, /*!< EADC Source 2 Interrupt */\r
+ EADC3_IRQn = 47, /*!< EADC Source 3 Interrupt */\r
+ UART2_IRQn = 48, /*!< UART2 Interrupt */\r
+ UART3_IRQn = 49, /*!< UART3 Interrupt */\r
+ SPI1_IRQn = 51, /*!< SPI1 Interrupt */\r
+ SPI2_IRQn = 52, /*!< SPI2 Interrupt */\r
+ USBD_IRQn = 53, /*!< USB device Interrupt */\r
+ USBH_IRQn = 54, /*!< USB host Interrupt */\r
+ USBOTG_IRQn = 55, /*!< USB OTG Interrupt */\r
+ CAN0_IRQn = 56, /*!< CAN0 Interrupt */\r
+ SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */\r
+ SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */\r
+ SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */\r
+ SPI3_IRQn = 62, /*!< SPI3 Interrupt */\r
+ SDH0_IRQn = 64, /*!< SDH0 Interrupt */\r
+ I2S0_IRQn = 68, /*!< I2S0 Interrupt */\r
+ CRPT_IRQn = 71, /*!< CRPT Interrupt */\r
+ GPG_IRQn = 72, /*!< GPIO Port G Interrupt */\r
+ EINT6_IRQn = 73, /*!< External Input 6 Interrupt */\r
+ UART4_IRQn = 74, /*!< UART4 Interrupt */\r
+ UART5_IRQn = 75, /*!< UART5 Interrupt */\r
+ USCI0_IRQn = 76, /*!< USCI0 Interrupt */\r
+ USCI1_IRQn = 77, /*!< USCI1 Interrupt */\r
+ BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */\r
+ BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */\r
+ I2C2_IRQn = 82, /*!< I2C2 Interrupt */\r
+ QEI0_IRQn = 84, /*!< QEI0 Interrupt */\r
+ QEI1_IRQn = 85, /*!< QEI1 Interrupt */\r
+ ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */\r
+ ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */\r
+ GPH_IRQn = 88, /*!< GPIO Port H Interrupt */\r
+ EINT7_IRQn = 89, /*!< External Input 7 Interrupt */\r
+ PDMA1_IRQn = 98, /*!< Peripheral DMA 1 Interrupt */\r
+ SCU_IRQn = 99, /*!< SCU Interrupt */\r
+ TRNG_IRQn = 101 /*!< TRNG interrupt */\r
+\r
+\r
+} IRQn_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Processor and Core Peripheral Section ================ */\r
+/* ================================================================================ */\r
+\r
+/* ------- Start of section using anonymous unions and disabling warnings ------- */\r
+#if defined (__CC_ARM)\r
+#pragma push\r
+#pragma anon_unions\r
+#elif defined (__ICCARM__)\r
+#pragma language=extended\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+#pragma clang diagnostic push\r
+#pragma clang diagnostic ignored "-Wc11-extensions"\r
+#pragma clang diagnostic ignored "-Wreserved-id-macro"\r
+#elif defined (__GNUC__)\r
+/* anonymous unions are enabled by default */\r
+#elif defined (__TMS470__)\r
+/* anonymous unions are enabled by default */\r
+#elif defined (__TASKING__)\r
+#pragma warning 586\r
+#elif defined (__CSMC__)\r
+/* anonymous unions are enabled by default */\r
+#else\r
+#warning Not supported compiler type\r
+#endif\r
+\r
+\r
+/* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */\r
+#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */\r
+#define __SAU_PRESENT 1U /* SAU present */\r
+#define __SAUREGION_PRESENT 1U /* SAU present */\r
+#define __MPU_PRESENT 1U /* MPU present */\r
+#define __VTOR_PRESENT 1U /* VTOR present */\r
+#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */\r
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */\r
+#define USE_ASSERT 0U /* Define to use Assert function or not */\r
+\r
+/*@}*/ /* end of group CMSIS */\r
+\r
+\r
+#include "core_armv8mbl.h" /* Processor and core peripherals */\r
+#include "system_M2351.h" /* System Header */\r
+\r
+/**\r
+ * Initialize the system clock\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the micro controller system\r
+ * Initialize the PLL and update the SystemFrequency variable\r
+ */\r
+extern void SystemInit(void);\r
+\r
+\r
+/******************************************************************************/\r
+/* Device Specific Peripheral registers structures */\r
+/******************************************************************************/\r
+\r
+\r
+#include "acmp_reg.h"\r
+#include "bpwm_reg.h"\r
+#include "can_reg.h"\r
+#include "clk_reg.h"\r
+#include "crc_reg.h"\r
+#include "dac_reg.h"\r
+#include "eadc_reg.h"\r
+#include "ebi_reg.h"\r
+#include "ecap_reg.h"\r
+#include "fmc_reg.h"\r
+#include "gpio_reg.h"\r
+#include "hdiv_reg.h"\r
+#include "i2c_reg.h"\r
+#include "i2s_reg.h"\r
+#include "pdma_reg.h"\r
+#include "epwm_reg.h"\r
+#include "qei_reg.h"\r
+#include "rtc_reg.h"\r
+#include "sc_reg.h"\r
+#include "scu_reg.h"\r
+#include "sdh_reg.h"\r
+#include "qspi_reg.h"\r
+#include "spi_reg.h"\r
+#include "sys_reg.h"\r
+#include "timer_reg.h"\r
+#include "trng_reg.h"\r
+#include "uart_reg.h"\r
+#include "ui2c_reg.h"\r
+#include "usbh_reg.h"\r
+#include "usbd_reg.h"\r
+#include "otg_reg.h"\r
+#include "crpt_reg.h"\r
+#include "uspi_reg.h"\r
+#include "uuart_reg.h"\r
+#include "wdt_reg.h"\r
+#include "wwdt_reg.h"\r
+\r
+\r
+/******************************************************************************/\r
+/* Peripheral memory map */\r
+/******************************************************************************/\r
+/** @addtogroup PERIPHERAL_BASE Peripheral Memory Base\r
+ Memory Mapped Structure for Series Peripheral\r
+ @{\r
+ */\r
+\r
+\r
+/* Peripheral and SRAM base address */\r
+#define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */\r
+#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */\r
+#define NS_OFFSET (0x10000000UL)\r
+\r
+/* Peripheral memory map */\r
+#define AHBPERIPH_BASE PERIPH_BASE\r
+#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000UL)\r
+\r
+/*!< AHB peripherals */\r
+#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL)\r
+#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL)\r
+#define INT_BASE (AHBPERIPH_BASE + 0x00300UL)\r
+#define GPIO_BASE (AHBPERIPH_BASE + 0x04000UL)\r
+#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL)\r
+#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL)\r
+#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL)\r
+#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL)\r
+#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL)\r
+#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL)\r
+#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL)\r
+#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL)\r
+#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)\r
+#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)\r
+#define PDMA0_BASE (AHBPERIPH_BASE + 0x08000UL)\r
+#define PDMA1_BASE (AHBPERIPH_BASE + 0x18000UL)\r
+#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL)\r
+#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL)\r
+#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL)\r
+#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL)\r
+#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL)\r
+#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL)\r
+#define CRPT_BASE (AHBPERIPH_BASE + 0x32000UL)\r
+#define SCU_BASE (AHBPERIPH_BASE + 0x2F000UL)\r
+\r
+/*!< APB peripherals */\r
+#define WDT_BASE (APBPERIPH_BASE + 0x00000UL)\r
+#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL)\r
+#define RTC_BASE (APBPERIPH_BASE + 0x01000UL)\r
+#define EADC_BASE (APBPERIPH_BASE + 0x03000UL)\r
+#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL)\r
+#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL)\r
+#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL)\r
+#define I2S0_BASE (APBPERIPH_BASE + 0x08000UL)\r
+#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL)\r
+#define TMR01_BASE (APBPERIPH_BASE + 0x10000UL)\r
+#define TMR23_BASE (APBPERIPH_BASE + 0x11000UL)\r
+#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL)\r
+#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL)\r
+#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL)\r
+#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL)\r
+#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL)\r
+#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL)\r
+#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL)\r
+#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL)\r
+#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL)\r
+#define UART0_BASE (APBPERIPH_BASE + 0x30000UL)\r
+#define UART0_BASE (APBPERIPH_BASE + 0x30000UL)\r
+#define UART1_BASE (APBPERIPH_BASE + 0x31000UL)\r
+#define UART2_BASE (APBPERIPH_BASE + 0x32000UL)\r
+#define UART3_BASE (APBPERIPH_BASE + 0x33000UL)\r
+#define UART4_BASE (APBPERIPH_BASE + 0x34000UL)\r
+#define UART5_BASE (APBPERIPH_BASE + 0x35000UL)\r
+#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL)\r
+#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL)\r
+#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL)\r
+#define SC0_BASE (APBPERIPH_BASE + 0x50000UL)\r
+#define SC1_BASE (APBPERIPH_BASE + 0x51000UL)\r
+#define SC2_BASE (APBPERIPH_BASE + 0x52000UL)\r
+#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL)\r
+#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL)\r
+#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL)\r
+#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL)\r
+#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL)\r
+#define TRNG_BASE (APBPERIPH_BASE + 0x79000UL)\r
+#define USBD_BASE (APBPERIPH_BASE + 0x80000UL)\r
+#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL)\r
+#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL)\r
+\r
+\r
+/**@}*/ /* PERIPHERAL */\r
+\r
+/******************************************************************************/\r
+/* Peripheral declaration */\r
+/******************************************************************************/\r
+\r
+/** @addtogroup PMODULE Peripheral Pointer\r
+ The Declaration of Peripheral Pointer\r
+ @{\r
+ */\r
+\r
+/** @addtogroup PMODULE_S Secure Peripheral Pointer\r
+ The Declaration of Secure Peripheral Pointer\r
+ @{\r
+*/\r
+\r
+\r
+#define PA ((GPIO_T *) GPIOA_BASE) /*!< GPIO PORTA Pointer */\r
+#define PB ((GPIO_T *) GPIOB_BASE) /*!< GPIO PORTB Pointer */\r
+#define PC ((GPIO_T *) GPIOC_BASE) /*!< GPIO PORTC Pointer */\r
+#define PD ((GPIO_T *) GPIOD_BASE) /*!< GPIO PORTD Pointer */\r
+#define PE ((GPIO_T *) GPIOE_BASE) /*!< GPIO PORTE Pointer */\r
+#define PF ((GPIO_T *) GPIOF_BASE) /*!< GPIO PORTF Pointer */\r
+#define PG ((GPIO_T *) GPIOG_BASE) /*!< GPIO PORTG Pointer */\r
+#define PH ((GPIO_T *) GPIOH_BASE) /*!< GPIO PORTH Pointer */\r
+\r
+#define UART0 ((UART_T *) UART0_BASE) /*!< UART0 Pointer */\r
+#define UART1 ((UART_T *) UART1_BASE) /*!< UART1 Pointer */\r
+#define UART2 ((UART_T *) UART2_BASE) /*!< UART2 Pointer */\r
+#define UART3 ((UART_T *) UART3_BASE) /*!< UART3 Pointer */\r
+#define UART4 ((UART_T *) UART4_BASE) /*!< UART4 Pointer */\r
+#define UART5 ((UART_T *) UART5_BASE) /*!< UART5 Pointer */\r
+\r
+\r
+#define TIMER0 ((TIMER_T *) TMR01_BASE) /*!< TIMER0 Pointer */\r
+#define TIMER1 ((TIMER_T *) (TMR01_BASE + 0x100UL)) /*!< TIMER1 Pointer */\r
+#define TIMER2 ((TIMER_T *) TMR23_BASE) /*!< TIMER2 Pointer */\r
+#define TIMER3 ((TIMER_T *) (TMR23_BASE + 0x100UL)) /*!< TIMER3 Pointer */\r
+\r
+#define WDT ((WDT_T *) WDT_BASE) /*!< Watch Dog Timer Pointer */\r
+\r
+#define WWDT ((WWDT_T *) WWDT_BASE) /*!< Window Watch Dog Timer Pointer */\r
+\r
+#define QSPI0 ((QSPI_T *) QSPI0_BASE) /*!< QSPI0 Pointer */\r
+#define SPI0 ((SPI_T *) SPI0_BASE) /*!< SPI0 Pointer */\r
+#define SPI1 ((SPI_T *) SPI1_BASE) /*!< SPI1 Pointer */\r
+#define SPI2 ((SPI_T *) SPI2_BASE) /*!< SPI2 Pointer */\r
+#define SPI3 ((SPI_T *) SPI3_BASE) /*!< SPI3 Pointer */\r
+\r
+#define I2S0 ((I2S_T *) I2S0_BASE) /*!< I2S0 Pointer */\r
+\r
+#define I2C0 ((I2C_T *) I2C0_BASE) /*!< I2C0 Pointer */\r
+#define I2C1 ((I2C_T *) I2C1_BASE) /*!< I2C1 Pointer */\r
+#define I2C2 ((I2C_T *) I2C2_BASE) /*!< I2C1 Pointer */\r
+\r
+#define QEI0 ((QEI_T *) QEI0_BASE) /*!< QEI0 Pointer */\r
+#define QEI1 ((QEI_T *) QEI1_BASE) /*!< QEI1 Pointer */\r
+\r
+#define RTC ((RTC_T *) RTC_BASE) /*!< RTC Pointer */\r
+\r
+#define ACMP01 ((ACMP_T *) ACMP01_BASE) /*!< ACMP01 Pointer */\r
+\r
+#define CLK ((CLK_T *) CLK_BASE) /*!< System Clock Controller Pointer */\r
+\r
+#define DAC0 ((DAC_T *) DAC0_BASE) /*!< DAC0 Pointer */\r
+#define DAC1 ((DAC_T *) DAC1_BASE) /*!< DAC1 Pointer */\r
+\r
+#define EADC ((EADC_T *) EADC_BASE) /*!< EADC Pointer */\r
+\r
+#define SYS ((SYS_T *) SYS_BASE) /*!< System Global Controller Pointer */\r
+\r
+#define SYSINT ((SYS_INT_T *) INT_BASE) /*!< Interrupt Source Controller Pointer */\r
+\r
+#define FMC ((FMC_T *) FMC_BASE) /*!< Flash Memory Controller */\r
+\r
+#define SDH0 ((SDH_T *) SDH0_BASE)\r
+\r
+#define CRPT ((CRPT_T *) CRPT_BASE) /*!< Crypto Accelerator Pointer */\r
+#define TRNG ((TRNG_T *)TRNG_BASE) /*!< True Random Number Pointer */\r
+\r
+#define BPWM0 ((BPWM_T *) BPWM0_BASE) /*!< BPWM0 Pointer */\r
+#define BPWM1 ((BPWM_T *) BPWM1_BASE) /*!< BPWM1 Pointer */\r
+\r
+#define EPWM0 ((EPWM_T *) EPWM0_BASE) /*!< EPWM0 Pointer */\r
+#define EPWM1 ((EPWM_T *) EPWM1_BASE) /*!< EPWM1 Pointer */\r
+\r
+#define SC0 ((SC_T *) SC0_BASE) /*!< SC0 Pointer */\r
+#define SC1 ((SC_T *) SC1_BASE) /*!< SC1 Pointer */\r
+#define SC2 ((SC_T *) SC2_BASE) /*!< SC2 Pointer */\r
+\r
+#define EBI ((EBI_T *) EBI_BASE) /*!< EBI Pointer */\r
+\r
+#define CRC ((CRC_T *) CRC_BASE) /*!< CRC Pointer */\r
+\r
+#define USBD ((USBD_T *) USBD_BASE) /*!< USB Device Pointer */\r
+#define USBH ((USBH_T *) USBH_BASE) /*!< USBH Pointer */\r
+#define OTG ((OTG_T *) OTG_BASE) /*!< OTG Pointer */\r
+\r
+#define PDMA0 ((PDMA_T *) PDMA0_BASE) /*!< PDMA0 Pointer */\r
+#define PDMA1 ((PDMA_T *) PDMA1_BASE) /*!< PDMA1 Pointer */\r
+\r
+#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Pointer */\r
+#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Pointer */\r
+#define UI2C2 ((UI2C_T *) USCI2_BASE) /*!< UI2C2 Pointer */\r
+\r
+#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Pointer */\r
+#define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Pointer */\r
+\r
+#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Pointer */\r
+#define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Pointer */\r
+\r
+#define SCU ((SCU_T *) SCU_BASE) /*!< SCU Pointer */\r
+#define ECAP0 ((ECAP_T *) ECAP0_BASE) /*!< ECAP0 Pointer */\r
+#define ECAP1 ((ECAP_T *) ECAP1_BASE) /*!< ECAP1 Pointer */\r
+\r
+#define CAN0 ((CAN_T *)CAN0_BASE) /*!< CAN0 Pointer */\r
+\r
+\r
+\r
+\r
+/**@}*/ /* end of group PMODULE_S */\r
+\r
+/** @addtogroup PMODULE_NS Non-secure Peripheral Pointer\r
+ The Declaration of Non-secure Peripheral Pointer\r
+ @{\r
+*/\r
+\r
+\r
+#define PA_NS ((GPIO_T *) (GPIOA_BASE+NS_OFFSET)) /*!< GPIO PORTA Pointer */\r
+#define PB_NS ((GPIO_T *) (GPIOB_BASE+NS_OFFSET)) /*!< GPIO PORTB Pointer */\r
+#define PC_NS ((GPIO_T *) (GPIOC_BASE+NS_OFFSET)) /*!< GPIO PORTC Pointer */\r
+#define PD_NS ((GPIO_T *) (GPIOD_BASE+NS_OFFSET)) /*!< GPIO PORTD Pointer */\r
+#define PE_NS ((GPIO_T *) (GPIOE_BASE+NS_OFFSET)) /*!< GPIO PORTE Pointer */\r
+#define PF_NS ((GPIO_T *) (GPIOF_BASE+NS_OFFSET)) /*!< GPIO PORTF Pointer */\r
+#define PG_NS ((GPIO_T *) (GPIOG_BASE+NS_OFFSET)) /*!< GPIO PORTG Pointer */\r
+#define PH_NS ((GPIO_T *) (GPIOH_BASE+NS_OFFSET)) /*!< GPIO PORTH Pointer */\r
+#define UART0_NS ((UART_T *) (UART0_BASE+NS_OFFSET)) /*!< UART0 Pointer */\r
+#define UART1_NS ((UART_T *) (UART1_BASE+NS_OFFSET)) /*!< UART1 Pointer */\r
+#define UART2_NS ((UART_T *) (UART2_BASE+NS_OFFSET)) /*!< UART2 Pointer */\r
+#define UART3_NS ((UART_T *) (UART3_BASE+NS_OFFSET)) /*!< UART3 Pointer */\r
+#define UART4_NS ((UART_T *) (UART4_BASE+NS_OFFSET)) /*!< UART4 Pointer */\r
+#define UART5_NS ((UART_T *) (UART5_BASE+NS_OFFSET)) /*!< UART5 Pointer */\r
+#define TIMER2_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET)) /*!< TIMER2 Pointer */\r
+#define TIMER3_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET+0x100UL)) /*!< TIMER3 Pointer */\r
+#define QSPI0_NS ((QSPI_T *) (QSPI0_BASE+NS_OFFSET)) /*!< QSPI0 Pointer */\r
+#define SPI0_NS ((SPI_T *) (SPI0_BASE+NS_OFFSET)) /*!< SPI0 Pointer */\r
+#define SPI1_NS ((SPI_T *) (SPI1_BASE+NS_OFFSET)) /*!< SPI1 Pointer */\r
+#define SPI2_NS ((SPI_T *) (SPI2_BASE+NS_OFFSET)) /*!< SPI2 Pointer */\r
+#define SPI3_NS ((SPI_T *) (SPI3_BASE+NS_OFFSET)) /*!< SPI3 Pointer */\r
+#define I2S0_NS ((I2S_T *) (I2S0_BASE+NS_OFFSET)) /*!< I2S0 Pointer */\r
+#define I2C0_NS ((I2C_T *) (I2C0_BASE+NS_OFFSET)) /*!< I2C0 Pointer */\r
+#define I2C1_NS ((I2C_T *) (I2C1_BASE+NS_OFFSET)) /*!< I2C1 Pointer */\r
+#define I2C2_NS ((I2C_T *) (I2C2_BASE+NS_OFFSET)) /*!< I2C1 Pointer */\r
+#define QEI0_NS ((QEI_T *) (QEI0_BASE+NS_OFFSET)) /*!< QEI0 Pointer */\r
+#define QEI1_NS ((QEI_T *) (QEI1_BASE+NS_OFFSET)) /*!< QEI1 Pointer */\r
+#define RTC_NS ((RTC_T *) (RTC_BASE +NS_OFFSET)) /*!< RTC Pointer */\r
+#define ACMP01_NS ((ACMP_T *) (ACMP01_BASE+NS_OFFSET)) /*!< ACMP01 Pointer */\r
+#define DAC0_NS ((DAC_T *) (DAC0_BASE+NS_OFFSET)) /*!< DAC0 Pointer */\r
+#define DAC1_NS ((DAC_T *) (DAC1_BASE+NS_OFFSET)) /*!< DAC1 Pointer */\r
+#define EADC_NS ((EADC_T *) (EADC_BASE+NS_OFFSET)) /*!< EADC Pointer */\r
+#define SDH0_NS ((SDH_T *) (SDH0_BASE +NS_OFFSET))\r
+#define CRPT_NS ((CRPT_T *) (CRPT_BASE +NS_OFFSET))\r
+#define TRNG_NS ((TRNG_T *) (TRNG_BASE +NS_OFFSET)) /*!< Random Number Generator Pointer */\r
+#define BPWM0_NS ((BPWM_T *) (BPWM0_BASE+NS_OFFSET)) /*!< BPWM0 Pointer */\r
+#define BPWM1_NS ((BPWM_T *) (BPWM1_BASE+NS_OFFSET)) /*!< BPWM1 Pointer */\r
+#define EPWM0_NS ((EPWM_T *) (EPWM0_BASE+NS_OFFSET)) /*!< EPWM0 Pointer */\r
+#define EPWM1_NS ((EPWM_T *) (EPWM1_BASE+NS_OFFSET)) /*!< EPWM1 Pointer */\r
+#define SC0_NS ((SC_T *) (SC0_BASE +NS_OFFSET)) /*!< SC0 Pointer */\r
+#define SC1_NS ((SC_T *) (SC1_BASE +NS_OFFSET)) /*!< SC1 Pointer */\r
+#define SC2_NS ((SC_T *) (SC2_BASE +NS_OFFSET)) /*!< SC2 Pointer */\r
+#define EBI_NS ((EBI_T *) (EBI_BASE +NS_OFFSET)) /*!< EBI Pointer */\r
+#define CRC_NS ((CRC_T *) (CRC_BASE +NS_OFFSET)) /*!< CRC Pointer */\r
+#define USBD_NS ((USBD_T *) (USBD_BASE +NS_OFFSET)) /*!< USB Device Pointer */\r
+#define USBH_NS ((USBH_T *) (USBH_BASE +NS_OFFSET)) /*!< USBH Pointer */\r
+#define OTG_NS ((OTG_T *) (OTG_BASE +NS_OFFSET)) /*!< OTG Pointer */\r
+#define PDMA1_NS ((PDMA_T *) (PDMA1_BASE +NS_OFFSET)) /*!< PDMA1 Pointer */\r
+#define UI2C0_NS ((UI2C_T *) (USCI0_BASE +NS_OFFSET)) /*!< UI2C0 Pointer */\r
+#define UI2C1_NS ((UI2C_T *) (USCI1_BASE +NS_OFFSET)) /*!< UI2C1 Pointer */\r
+#define UI2C2_NS ((UI2C_T *) (USCI2_BASE +NS_OFFSET)) /*!< UI2C2 Pointer */\r
+#define USPI0_NS ((USPI_T *) (USCI0_BASE +NS_OFFSET)) /*!< USPI0 Pointer */\r
+#define USPI1_NS ((USPI_T *) (USCI1_BASE +NS_OFFSET)) /*!< USPI1 Pointer */\r
+#define UUART0_NS ((UUART_T *) (USCI0_BASE+NS_OFFSET)) /*!< UUART0 Pointer */\r
+#define UUART1_NS ((UUART_T *) (USCI1_BASE+NS_OFFSET)) /*!< UUART1 Pointer */\r
+#define SCU_NS ((SCU_T *) (SCU_BASE +NS_OFFSET)) /*!< SCU Pointer */\r
+#define ECAP0_NS ((ECAP_T *) (ECAP0_BASE+NS_OFFSET)) /*!< ECAP0 Pointer */\r
+#define ECAP1_NS ((ECAP_T *) (ECAP1_BASE+NS_OFFSET)) /*!< ECAP1 Pointer */\r
+#define CAN0_NS ((CAN_T *) (CAN0_BASE +NS_OFFSET)) /*!< CAN0 Pointer */\r
+\r
+/**@}*/ /* end of group PMODULE_NS */\r
+/**@}*/ /* end of group PMODULE */\r
+\r
+/* -------------------- End of section using anonymous unions ------------------- */\r
+#if defined (__CC_ARM)\r
+#pragma pop\r
+#elif defined (__ICCARM__)\r
+/* leave anonymous unions enabled */\r
+#elif (__ARMCC_VERSION >= 6010050)\r
+#pragma clang diagnostic pop\r
+#elif defined (__GNUC__)\r
+/* anonymous unions are enabled by default */\r
+#elif defined (__TMS470__)\r
+/* anonymous unions are enabled by default */\r
+#elif defined (__TASKING__)\r
+#pragma warning restore\r
+#elif defined (__CSMC__)\r
+/* anonymous unions are enabled by default */\r
+#else\r
+#warning Not supported compiler type\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+/*=============================================================================*/\r
+typedef volatile unsigned char vu8;\r
+typedef volatile unsigned long vu32;\r
+typedef volatile unsigned short vu16;\r
+#define M8(adr) (*((vu8 *) (adr)))\r
+#define M16(adr) (*((vu16 *) (adr)))\r
+#define M32(adr) (*((vu32 *) (adr)))\r
+\r
+#define outpw(port,value) (*((volatile unsigned int *)(port))=(value))\r
+#define inpw(port) ((*((volatile unsigned int *)(port))))\r
+#define outpb(port,value) (*((volatile unsigned char *)(port))=(value))\r
+#define inpb(port) ((*((volatile unsigned char *)(port))))\r
+#define outps(port,value) (*((volatile unsigned short *)(port))=(value))\r
+#define inps(port) ((*((volatile unsigned short *)(port))))\r
+\r
+#define outp32(port,value) (*((volatile unsigned int *)(port))=(value))\r
+#define inp32(port) ((*((volatile unsigned int *)(port))))\r
+#define outp8(port,value) (*((volatile unsigned char *)(port))=(value))\r
+#define inp8(port) ((*((volatile unsigned char *)(port))))\r
+#define outp16(port,value) (*((volatile unsigned short *)(port))=(value))\r
+#define inp16(port) ((*((volatile unsigned short *)(port))))\r
+\r
+\r
+#define E_SUCCESS 0\r
+\r
+#define TRUE (1L)\r
+#define FALSE (0L)\r
+\r
+#define ENABLE 1\r
+#define DISABLE 0\r
+\r
+/* Bit Mask Definitions */\r
+#define BIT0 0x00000001UL\r
+#define BIT1 0x00000002UL\r
+#define BIT2 0x00000004UL\r
+#define BIT3 0x00000008UL\r
+#define BIT4 0x00000010UL\r
+#define BIT5 0x00000020UL\r
+#define BIT6 0x00000040UL\r
+#define BIT7 0x00000080UL\r
+#define BIT8 0x00000100UL\r
+#define BIT9 0x00000200UL\r
+#define BIT10 0x00000400UL\r
+#define BIT11 0x00000800UL\r
+#define BIT12 0x00001000UL\r
+#define BIT13 0x00002000UL\r
+#define BIT14 0x00004000UL\r
+#define BIT15 0x00008000UL\r
+#define BIT16 0x00010000UL\r
+#define BIT17 0x00020000UL\r
+#define BIT18 0x00040000UL\r
+#define BIT19 0x00080000UL\r
+#define BIT20 0x00100000UL\r
+#define BIT21 0x00200000UL\r
+#define BIT22 0x00400000UL\r
+#define BIT23 0x00800000UL\r
+#define BIT24 0x01000000UL\r
+#define BIT25 0x02000000UL\r
+#define BIT26 0x04000000UL\r
+#define BIT27 0x08000000UL\r
+#define BIT28 0x10000000UL\r
+#define BIT29 0x20000000UL\r
+#define BIT30 0x40000000UL\r
+#define BIT31 0x80000000UL\r
+\r
+\r
+/* Byte Mask Definitions */\r
+#define BYTE0_Msk (0x000000FFUL)\r
+#define BYTE1_Msk (0x0000FF00UL)\r
+#define BYTE2_Msk (0x00FF0000UL)\r
+#define BYTE3_Msk (0xFF000000UL)\r
+\r
+#define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */\r
+#define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8UL) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */\r
+#define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16UL) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */\r
+#define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24UL) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */\r
+\r
+\r
+/******************************************************************************/\r
+/* Peripheral header files */\r
+/******************************************************************************/\r
+#include "sys.h"\r
+#include "clk.h"\r
+#include "dac.h"\r
+#include "eadc.h"\r
+#include "ebi.h"\r
+#include "ecap.h"\r
+#include "fmc.h"\r
+#include "gpio.h"\r
+#include "i2c.h"\r
+#include "i2s.h"\r
+#include "bpwm.h"\r
+#include "epwm.h"\r
+#include "qspi.h"\r
+#include "spi.h"\r
+#include "timer.h"\r
+#include "timer_pwm.h"\r
+#include "wdt.h"\r
+#include "wwdt.h"\r
+#include "rtc.h"\r
+#include "uart.h"\r
+#include "acmp.h"\r
+#include "crc.h"\r
+#include "usbd.h"\r
+#include "otg.h"\r
+#include "pdma.h"\r
+#include "ebi.h"\r
+#include "crypto.h"\r
+#include "sc.h"\r
+#include "scuart.h"\r
+#include "usci_spi.h"\r
+#include "usci_uart.h"\r
+#include "usci_i2c.h"\r
+#include "sdh.h"\r
+#include "qei.h"\r
+#include "can.h"\r
+#include "scu.h"\r
+#include "mkromlib.h"\r
+\r
+#endif /* __M2351_H__ */\r
+\r
+\r
+/* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file NuMicro.h\r
+ * @version V1.00\r
+ * @brief NuMicro peripheral access layer header file.\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __NUMICRO_H__\r
+#define __NUMICRO_H__\r
+\r
+#include "M2351.h"\r
+\r
+#endif /* __NUMICRO_H__ */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file acmp_reg.h\r
+ * @version V1.00\r
+ * @brief ACMP register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __ACMP_REG_H__\r
+#define __ACMP_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- Analog Comparator Controller -------------------------*/\r
+/**\r
+ @addtogroup ACMP Analog Comparator Controller(ACMP)\r
+ Memory Mapped Structure for ACMP Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var ACMP_T::CTL\r
+ * Offset: 0x00 Analog Comparator 0 Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ACMPEN |Comparator Enable Bit\r
+ * | | |0 = Comparator 0 Disabled.\r
+ * | | |1 = Comparator 0 Enabled.\r
+ * | | |\r
+ * |[1] |ACMPIE |Comparator Interrupt Enable Bit\r
+ * | | |0 = Comparator 0 interrupt Disabled.\r
+ * | | |1 = Comparator 0 interrupt Enabled\r
+ * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.\r
+ * | | |\r
+ * |[2] |HYSEN |Comparator Hysteresis Enable Bit\r
+ * | | |0 = Comparator 0 hysteresis Disabled.\r
+ * | | |1 = Comparator 0 hysteresis Enabled.\r
+ * | | |Note: If HYSEN = 0, user can adjust HYS by HYSSEL.\r
+ * | | |Note: If HYSEN = 1, HYSSEL is invalid. The Hysteresis is fixed to 30mV.\r
+ * |[3] |ACMPOINV |Comparator Output Inverse\r
+ * | | |0 = Comparator 0 output inverse Disabled.\r
+ * | | |1 = Comparator 0 output inverse Enabled.\r
+ * | | |\r
+ * |[5:4] |NEGSEL |Comparator Negative Input Selection\r
+ * | | |00 = ACMP0_N pin.\r
+ * | | |01 = Internal comparator reference voltage (CRV).\r
+ * | | |10 = Band-gap voltage.\r
+ * | | |11 = DAC output.\r
+ * | | |\r
+ * |[7:6] |POSSEL |Comparator Positive Input Selection\r
+ * | | |00 = Input from ACMP0_P0.\r
+ * | | |01 = Input from ACMP0_P1.\r
+ * | | |10 = Input from ACMP0_P2.\r
+ * | | |11 = Input from ACMP0_P3.\r
+ * | | |\r
+ * |[9:8] |INTPOL |Interrupt Condition Polarity Selection\r
+ * | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected.\r
+ * | | |00 = Rising edge or falling edge.\r
+ * | | |01 = Rising edge.\r
+ * | | |10 = Falling edge.\r
+ * | | |11 = Reserved.\r
+ * | | |\r
+ * |[12] |OUTSEL |Comparator Output Select\r
+ * | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.\r
+ * | | |1 = Comparator 0 output to ACMP0_O pin is from filter output.\r
+ * | | |\r
+ * |[15:13] |FILTSEL |Comparator Output Filter Count Selection\r
+ * | | |000 = Filter function is Disabled.\r
+ * | | |001 = ACMP0 output is sampled 1 consecutive PCLK.\r
+ * | | |010 = ACMP0 output is sampled 2 consecutive PCLKs.\r
+ * | | |011 = ACMP0 output is sampled 4 consecutive PCLKs.\r
+ * | | |100 = ACMP0 output is sampled 8 consecutive PCLKs.\r
+ * | | |101 = ACMP0 output is sampled 16 consecutive PCLKs.\r
+ * | | |110 = ACMP0 output is sampled 32 consecutive PCLKs.\r
+ * | | |111 = ACMP0 output is sampled 64 consecutive PCLKs.\r
+ * | | |\r
+ * |[16] |WKEN |Power-down Wake-up Enable Bit\r
+ * | | |0 = Wake-up function Disabled.\r
+ * | | |1 = Wake-up function Enabled.\r
+ * | | |\r
+ * |[17] |WLATEN |Window Latch Mode Enable Bit\r
+ * | | |0 = Window Latch Mode Disabled.\r
+ * | | |1 = Window Latch Mode Enabled.\r
+ * | | |\r
+ * |[18] |WCMPSEL |Window Compare Mode Selection\r
+ * | | |0 = Window Compare Mode Disabled.\r
+ * | | |1 = Window Compare Mode is Selected.\r
+ * | | |\r
+ * |[25:24] |HYSSEL |Hysteresis Mode Selection\r
+ * | | |00 = Hysteresis is 0mV.\r
+ * | | |01 = Hysteresis is 10mV.\r
+ * | | |10 = Hysteresis is 20mV.\r
+ * | | |11 = Hysteresis is 30mV.\r
+ * | | |\r
+ * |[29:28] |MODESEL |Propagation Delay Mode Selection\r
+ * | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA.\r
+ * | | |01 = Max propagation delay is 2uS, operation current is 3uA.\r
+ * | | |10 = Max propagation delay is 600nS, operation current is 10uA.\r
+ * | | |11 = Max propagation delay is 200nS, operation current is 75uA.\r
+ * | | |\r
+\r
+ * @var ACMP_T::STATUS\r
+ * Offset: 0x08 Analog Comparator Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag\r
+ * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output\r
+ * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.\r
+ * | | |Note: Write 1 to clear this bit to 0.\r
+ * | | |\r
+ * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag\r
+ * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output\r
+ * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.\r
+ * | | |Note: Write 1 to clear this bit to 0.\r
+ * | | |\r
+ * |[4] |ACMPO0 |Comparator 0 Output\r
+ * | | |Synchronized to the PCLK to allow reading by software\r
+ * | | |Cleared when the comparator 0 is disabled, i.e\r
+ * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.\r
+ * | | |\r
+ * |[5] |ACMPO1 |Comparator 1 Output\r
+ * | | |Synchronized to the PCLK to allow reading by software\r
+ * | | |Cleared when the comparator 1 is disabled, i.e\r
+ * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.\r
+ * | | |\r
+ * |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag\r
+ * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\r
+ * | | |0 = No power-down wake-up occurred.\r
+ * | | |1 = Power-down wake-up occurred.\r
+ * | | |Note: Write 1 to clear this bit to 0.\r
+ * | | |\r
+ * |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag\r
+ * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\r
+ * | | |0 = No power-down wake-up occurred.\r
+ * | | |1 = Power-down wake-up occurred.\r
+ * | | |Note: Write 1 to clear this bit to 0.\r
+ * | | |\r
+ * |[12] |ACMPS0 |Comparator 0 Status\r
+ * | | |Synchronized to the PCLK to allow reading by software\r
+ * | | |Cleared when the comparator 0 is disabled, i.e\r
+ * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.\r
+ * |[13] |ACMPS1 |Comparator 1 Status\r
+ * | | |Synchronized to the PCLK to allow reading by software\r
+ * | | |Cleared when the comparator 1 is disabled, i.e\r
+ * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.\r
+ * |[16] |ACMPWO |Comparator Window Output\r
+ * | | |This bit shows the output status of window compare mode\r
+ * | | |0 = The positive input voltage is outside the window.\r
+ * | | |1 = The positive input voltage is in the window.\r
+ * | | |\r
+ * @var ACMP_T::VREF\r
+ * Offset: 0x0C Analog Comparator Reference Voltage Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |CRVCTL |Comparator Reference Voltage Setting\r
+ * | | |CRV = CRV source voltage * (1/6+CRVCTL/24).\r
+ * | | |\r
+ * |[6] |CRVSSEL |CRV Source Voltage Selection\r
+ * | | |0 = VDDA is selected as CRV source voltage.\r
+ * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.\r
+ * | | |\r
+ */\r
+ __IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0~1 Control Register */\r
+ __IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */\r
+ __IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */\r
+\r
+} ACMP_T;\r
+\r
+/**\r
+ @addtogroup ACMP_CONST ACMP Bit Field Definition\r
+ Constant Definitions for ACMP Controller\r
+@{ */\r
+\r
+#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */\r
+#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */\r
+\r
+#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */\r
+#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */\r
+\r
+#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */\r
+#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */\r
+\r
+#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */\r
+#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */\r
+\r
+#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */\r
+#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */\r
+\r
+#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */\r
+#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */\r
+\r
+#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */\r
+#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */\r
+\r
+#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */\r
+#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */\r
+\r
+#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */\r
+#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */\r
+\r
+#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */\r
+#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */\r
+\r
+#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */\r
+#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */\r
+\r
+#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */\r
+#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */\r
+\r
+#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */\r
+#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */\r
+\r
+#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */\r
+#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */\r
+\r
+#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */\r
+#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */\r
+\r
+#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */\r
+#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */\r
+\r
+#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */\r
+#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */\r
+\r
+#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */\r
+#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */\r
+\r
+#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */\r
+#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */\r
+\r
+#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */\r
+#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */\r
+\r
+#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */\r
+#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */\r
+\r
+#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */\r
+#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */\r
+\r
+#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */\r
+#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */\r
+\r
+#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */\r
+#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */\r
+\r
+#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */\r
+#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */\r
+\r
+/**@}*/ /* ACMP_CONST */\r
+/**@}*/ /* end of ACMP register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __ACMP_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file bpwm_reg.h\r
+ * @version V1.00\r
+ * @brief BPWM register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __BPWM_REG_H__\r
+#define __BPWM_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- Basic Pulse Width Modulation Controller -------------------------*/\r
+/**\r
+ @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM)\r
+ Memory Mapped Structure for BPWM Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+ /**\r
+ * @var BCAPDAT_T::RCAPDAT\r
+ * Offset: 0x20C BPWM Rising Capture Data Register 0~5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only)\r
+ * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.\r
+ * @var BCAPDAT_T::FCAPDAT\r
+ * Offset: 0x210 BPWM Falling Capture Data Register 0~5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only)\r
+ * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.\r
+ */\r
+ __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */\r
+ __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */\r
+} BCAPDAT_T;\r
+\r
+\r
+typedef struct\r
+{\r
+ /**\r
+ * @var BPWM_T::CTL0\r
+ * Offset: 0x00 BPWM Control Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CTRLD0 |Center Re-load\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period\r
+ * | | |CMPDAT will load to CMPBUF at the center point of a period\r
+ * |[1] |CTRLD1 |Center Re-load\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period\r
+ * | | |CMPDAT will load to CMPBUF at the center point of a period\r
+ * |[2] |CTRLD2 |Center Re-load\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period\r
+ * | | |CMPDAT will load to CMPBUF at the center point of a period\r
+ * |[3] |CTRLD3 |Center Re-load\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period\r
+ * | | |CMPDAT will load to CMPBUF at the center point of a period\r
+ * |[4] |CTRLD4 |Center Re-load\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period\r
+ * | | |CMPDAT will load to CMPBUF at the center point of a period\r
+ * |[5] |CTRLD5 |Center Re-load\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period\r
+ * | | |CMPDAT will load to CMPBUF at the center point of a period\r
+ * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S)\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = PERIOD will load to PBUF at the end point of each period\r
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.\r
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.\r
+ * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.\r
+ * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S)\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = PERIOD will load to PBUF at the end point of each period\r
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.\r
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.\r
+ * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.\r
+ * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S)\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = PERIOD will load to PBUF at the end point of each period\r
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.\r
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.\r
+ * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.\r
+ * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S)\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = PERIOD will load to PBUF at the end point of each period\r
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.\r
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.\r
+ * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.\r
+ * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S)\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = PERIOD will load to PBUF at the end point of each period\r
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.\r
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.\r
+ * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.\r
+ * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S)\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = PERIOD will load to PBUF at the end point of each period\r
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.\r
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.\r
+ * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.\r
+ * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)\r
+ * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.\r
+ * | | |0 = ICE debug mode counter halt Disable.\r
+ * | | |1 = ICE debug mode counter halt Enable.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)\r
+ * | | |0 = ICE debug mode acknowledgement effects BPWM output.\r
+ * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged.\r
+ * | | |1 = ICE debug mode acknowledgement Disabled.\r
+ * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * @var BPWM_T::CTL1\r
+ * Offset: 0x04 BPWM Control Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0\r
+ * | | |Each bit n controls corresponding BPWM channel n.\r
+ * | | |00 = Up counter type (supports in capture mode).\r
+ * | | |01 = Down count type (supports in capture mode).\r
+ * | | |10 = Up-down counter type.\r
+ * | | |11 = Reserved.\r
+ * @var BPWM_T::CLKSRC\r
+ * Offset: 0x10 BPWM Clock Source Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select\r
+ * | | |000 = BPWMx_CLK, x denotes 0 or 1.\r
+ * | | |001 = TIMER0 overflow.\r
+ * | | |010 = TIMER1 overflow.\r
+ * | | |011 = TIMER2 overflow.\r
+ * | | |100 = TIMER3 overflow.\r
+ * | | |Others = Reserved.\r
+ * @var BPWM_T::CLKPSC\r
+ * Offset: 0x14 BPWM Clock Prescale Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[11:0] |CLKPSC |BPWM Counter Clock Prescale\r
+ * | | |The clock of BPWM counter is decided by clock prescaler\r
+ * | | |Each BPWM pair share one BPWM counter clock prescaler\r
+ * | | |The clock of BPWM counter is divided by (CLKPSC+ 1)\r
+ * @var BPWM_T::CNTEN\r
+ * Offset: 0x20 BPWM Counter Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit\r
+ * | | |0 = BPWM Counter and clock prescaler stop running.\r
+ * | | |1 = BPWM Counter and clock prescaler start running.\r
+ * @var BPWM_T::CNTCLR\r
+ * Offset: 0x24 BPWM Clear Counter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0\r
+ * | | |It is automatically cleared by hardware.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear 16-bit BPWM counter to 0000H.\r
+ * @var BPWM_T::PERIOD\r
+ * Offset: 0x30 BPWM Period Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |PERIOD |BPWM Period Register\r
+ * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.\r
+ * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.\r
+ * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period.\r
+ * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.\r
+ * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period.\r
+ * @var BPWM_T::CMPDAT[6]\r
+ * Offset: 0x50 BPWM Comparator Register 0~5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |CMPDAT |BPWM Comparator Register\r
+ * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC.\r
+ * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.\r
+ * @var BPWM_T::CNT\r
+ * Offset: 0x90 BPWM Counter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |CNT |BPWM Data Register (Read Only)\r
+ * | | |User can monitor CNTR to know the current value in 16-bit period counter.\r
+ * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only)\r
+ * | | |0 = Counter is Down count.\r
+ * | | |1 = Counter is UP count.\r
+ * @var BPWM_T::WGCTL0\r
+ * Offset: 0xB0 BPWM Generation Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |ZPCTL0 |BPWM Zero Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM zero point output Low.\r
+ * | | |10 = BPWM zero point output High.\r
+ * | | |11 = BPWM zero point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter count to zero.\r
+ * |[3:2] |ZPCTL1 |BPWM Zero Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM zero point output Low.\r
+ * | | |10 = BPWM zero point output High.\r
+ * | | |11 = BPWM zero point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter count to zero.\r
+ * |[5:4] |ZPCTL2 |BPWM Zero Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM zero point output Low.\r
+ * | | |10 = BPWM zero point output High.\r
+ * | | |11 = BPWM zero point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter count to zero.\r
+ * |[7:6] |ZPCTL3 |BPWM Zero Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM zero point output Low.\r
+ * | | |10 = BPWM zero point output High.\r
+ * | | |11 = BPWM zero point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter count to zero.\r
+ * |[9:8] |ZPCTL4 |BPWM Zero Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM zero point output Low.\r
+ * | | |10 = BPWM zero point output High.\r
+ * | | |11 = BPWM zero point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter count to zero.\r
+ * |[11:10] |ZPCTL5 |BPWM Zero Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM zero point output Low.\r
+ * | | |10 = BPWM zero point output High.\r
+ * | | |11 = BPWM zero point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter count to zero.\r
+ * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM period (center) point output Low.\r
+ * | | |10 = BPWM period (center) point output High.\r
+ * | | |11 = BPWM period (center) point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).\r
+ * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.\r
+ * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM period (center) point output Low.\r
+ * | | |10 = BPWM period (center) point output High.\r
+ * | | |11 = BPWM period (center) point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).\r
+ * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.\r
+ * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM period (center) point output Low.\r
+ * | | |10 = BPWM period (center) point output High.\r
+ * | | |11 = BPWM period (center) point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).\r
+ * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.\r
+ * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM period (center) point output Low.\r
+ * | | |10 = BPWM period (center) point output High.\r
+ * | | |11 = BPWM period (center) point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).\r
+ * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.\r
+ * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM period (center) point output Low.\r
+ * | | |10 = BPWM period (center) point output High.\r
+ * | | |11 = BPWM period (center) point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).\r
+ * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.\r
+ * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM period (center) point output Low.\r
+ * | | |10 = BPWM period (center) point output High.\r
+ * | | |11 = BPWM period (center) point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).\r
+ * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.\r
+ * @var BPWM_T::WGCTL1\r
+ * Offset: 0xB4 BPWM Generation Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM compare up point output Low.\r
+ * | | |10 = BPWM compare up point output High.\r
+ * | | |11 = BPWM compare up point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter up count to CMPDAT.\r
+ * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM compare up point output Low.\r
+ * | | |10 = BPWM compare up point output High.\r
+ * | | |11 = BPWM compare up point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter up count to CMPDAT.\r
+ * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM compare up point output Low.\r
+ * | | |10 = BPWM compare up point output High.\r
+ * | | |11 = BPWM compare up point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter up count to CMPDAT.\r
+ * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM compare up point output Low.\r
+ * | | |10 = BPWM compare up point output High.\r
+ * | | |11 = BPWM compare up point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter up count to CMPDAT.\r
+ * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM compare up point output Low.\r
+ * | | |10 = BPWM compare up point output High.\r
+ * | | |11 = BPWM compare up point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter up count to CMPDAT.\r
+ * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM compare up point output Low.\r
+ * | | |10 = BPWM compare up point output High.\r
+ * | | |11 = BPWM compare up point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter up count to CMPDAT.\r
+ * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM compare down point output Low.\r
+ * | | |10 = BPWM compare down point output High.\r
+ * | | |11 = BPWM compare down point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter down count to CMPDAT.\r
+ * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM compare down point output Low.\r
+ * | | |10 = BPWM compare down point output High.\r
+ * | | |11 = BPWM compare down point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter down count to CMPDAT.\r
+ * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM compare down point output Low.\r
+ * | | |10 = BPWM compare down point output High.\r
+ * | | |11 = BPWM compare down point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter down count to CMPDAT.\r
+ * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM compare down point output Low.\r
+ * | | |10 = BPWM compare down point output High.\r
+ * | | |11 = BPWM compare down point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter down count to CMPDAT.\r
+ * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM compare down point output Low.\r
+ * | | |10 = BPWM compare down point output High.\r
+ * | | |11 = BPWM compare down point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter down count to CMPDAT.\r
+ * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = BPWM compare down point output Low.\r
+ * | | |10 = BPWM compare down point output High.\r
+ * | | |11 = BPWM compare down point output Toggle.\r
+ * | | |BPWM can control output level when BPWM counter down count to CMPDAT.\r
+ * @var BPWM_T::MSKEN\r
+ * Offset: 0xB8 BPWM Mask Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |MSKEN0 |BPWM Mask Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |The BPWM output signal will be masked when this bit is enabled\r
+ * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.\r
+ * | | |0 = BPWM output signal is non-masked.\r
+ * | | |1 = BPWM output signal is masked and output MSKDATn data.\r
+ * |[1] |MSKEN1 |BPWM Mask Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |The BPWM output signal will be masked when this bit is enabled\r
+ * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.\r
+ * | | |0 = BPWM output signal is non-masked.\r
+ * | | |1 = BPWM output signal is masked and output MSKDATn data.\r
+ * |[2] |MSKEN2 |BPWM Mask Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |The BPWM output signal will be masked when this bit is enabled\r
+ * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.\r
+ * | | |0 = BPWM output signal is non-masked.\r
+ * | | |1 = BPWM output signal is masked and output MSKDATn data.\r
+ * |[3] |MSKEN3 |BPWM Mask Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |The BPWM output signal will be masked when this bit is enabled\r
+ * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.\r
+ * | | |0 = BPWM output signal is non-masked.\r
+ * | | |1 = BPWM output signal is masked and output MSKDATn data.\r
+ * |[4] |MSKEN4 |BPWM Mask Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |The BPWM output signal will be masked when this bit is enabled\r
+ * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.\r
+ * | | |0 = BPWM output signal is non-masked.\r
+ * | | |1 = BPWM output signal is masked and output MSKDATn data.\r
+ * |[5] |MSKEN5 |BPWM Mask Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |The BPWM output signal will be masked when this bit is enabled\r
+ * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.\r
+ * | | |0 = BPWM output signal is non-masked.\r
+ * | | |1 = BPWM output signal is masked and output MSKDATn data.\r
+ * @var BPWM_T::MSK\r
+ * Offset: 0xBC BPWM Mask Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |MSKDAT0 |BPWM Mask Data Bit\r
+ * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Output logic low to BPWMn.\r
+ * | | |1 = Output logic high to BPWMn.\r
+ * |[1] |MSKDAT1 |BPWM Mask Data Bit\r
+ * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Output logic low to BPWMn.\r
+ * | | |1 = Output logic high to BPWMn.\r
+ * |[2] |MSKDAT2 |BPWM Mask Data Bit\r
+ * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Output logic low to BPWMn.\r
+ * | | |1 = Output logic high to BPWMn.\r
+ * |[3] |MSKDAT3 |BPWM Mask Data Bit\r
+ * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Output logic low to BPWMn.\r
+ * | | |1 = Output logic high to BPWMn.\r
+ * |[4] |MSKDAT4 |BPWM Mask Data Bit\r
+ * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Output logic low to BPWMn.\r
+ * | | |1 = Output logic high to BPWMn.\r
+ * |[5] |MSKDAT5 |BPWM Mask Data Bit\r
+ * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Output logic low to BPWMn.\r
+ * | | |1 = Output logic high to BPWMn.\r
+ * @var BPWM_T::POLCTL\r
+ * Offset: 0xD4 BPWM Pin Polar Inverse Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PINV0 |BPWM PIN Polar Inverse Control\r
+ * | | |The register controls polarity state of BPWM output\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM output polar inverse Disabled.\r
+ * | | |1 = BPWM output polar inverse Enabled.\r
+ * |[1] |PINV1 |BPWM PIN Polar Inverse Control\r
+ * | | |The register controls polarity state of BPWM output\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM output polar inverse Disabled.\r
+ * | | |1 = BPWM output polar inverse Enabled.\r
+ * |[2] |PINV2 |BPWM PIN Polar Inverse Control\r
+ * | | |The register controls polarity state of BPWM output\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM output polar inverse Disabled.\r
+ * | | |1 = BPWM output polar inverse Enabled.\r
+ * |[3] |PINV3 |BPWM PIN Polar Inverse Control\r
+ * | | |The register controls polarity state of BPWM output\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM output polar inverse Disabled.\r
+ * | | |1 = BPWM output polar inverse Enabled.\r
+ * |[4] |PINV4 |BPWM PIN Polar Inverse Control\r
+ * | | |The register controls polarity state of BPWM output\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM output polar inverse Disabled.\r
+ * | | |1 = BPWM output polar inverse Enabled.\r
+ * |[5] |PINV5 |BPWM PIN Polar Inverse Control\r
+ * | | |The register controls polarity state of BPWM output\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM output polar inverse Disabled.\r
+ * | | |1 = BPWM output polar inverse Enabled.\r
+ * @var BPWM_T::POEN\r
+ * Offset: 0xD8 BPWM Output Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |POEN0 |BPWM Pin Output Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM pin at tri-state.\r
+ * | | |1 = BPWM pin in output mode.\r
+ * |[1] |POEN1 |BPWM Pin Output Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM pin at tri-state.\r
+ * | | |1 = BPWM pin in output mode.\r
+ * |[2] |POEN2 |BPWM Pin Output Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM pin at tri-state.\r
+ * | | |1 = BPWM pin in output mode.\r
+ * |[3] |POEN3 |BPWM Pin Output Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM pin at tri-state.\r
+ * | | |1 = BPWM pin in output mode.\r
+ * |[4] |POEN4 |BPWM Pin Output Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM pin at tri-state.\r
+ * | | |1 = BPWM pin in output mode.\r
+ * |[5] |POEN5 |BPWM Pin Output Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM pin at tri-state.\r
+ * | | |1 = BPWM pin in output mode.\r
+ * @var BPWM_T::INTEN\r
+ * Offset: 0xE0 BPWM Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit\r
+ * | | |0 = Zero point interrupt Disabled.\r
+ * | | |1 = Zero point interrupt Enabled.\r
+ * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit\r
+ * | | |0 = Period point interrupt Disabled.\r
+ * | | |1 = Period point interrupt Enabled.\r
+ * | | |Note: When up-down counter type period point means center point.\r
+ * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * @var BPWM_T::INTSTS\r
+ * Offset: 0xE8 BPWM Interrupt Flag Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0\r
+ * | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero.\r
+ * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0\r
+ * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero.\r
+ * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag\r
+ * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\r
+ * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag\r
+ * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\r
+ * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag\r
+ * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\r
+ * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag\r
+ * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\r
+ * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag\r
+ * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\r
+ * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag\r
+ * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\r
+ * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\r
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\r
+ * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\r
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\r
+ * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\r
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\r
+ * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\r
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\r
+ * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\r
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\r
+ * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\r
+ * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\r
+ * @var BPWM_T::EADCTS0\r
+ * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select\r
+ * | | |0000 = BPWM_CH0 zero point.\r
+ * | | |0001 = BPWM_CH0 period point.\r
+ * | | |0010 = BPWM_CH0 zero or period point.\r
+ * | | |0011 = BPWM_CH0 up-count CMPDAT point.\r
+ * | | |0100 = BPWM_CH0 down-count CMPDAT point.\r
+ * | | |0101 = Reserved.\r
+ * | | |0110 = Reserved.\r
+ * | | |0111 = Reserved.\r
+ * | | |1000 = BPWM_CH1 up-count CMPDAT point.\r
+ * | | |1001 = BPWM_CH1 down-count CMPDAT point.\r
+ * | | |Others reserved\r
+ * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit\r
+ * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select\r
+ * | | |0000 = BPWM_CH0 zero point.\r
+ * | | |0001 = BPWM_CH0 period point.\r
+ * | | |0010 = BPWM_CH0 zero or period point.\r
+ * | | |0011 = BPWM_CH0 up-count CMPDAT point.\r
+ * | | |0100 = BPWM_CH0 down-count CMPDAT point.\r
+ * | | |0101 = Reserved.\r
+ * | | |0110 = Reserved.\r
+ * | | |0111 = Reserved.\r
+ * | | |1000 = BPWM_CH1 up-count CMPDAT point.\r
+ * | | |1001 = BPWM_CH1 down-count CMPDAT point.\r
+ * | | |Others reserved\r
+ * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit\r
+ * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select\r
+ * | | |0000 = BPWM_CH2 zero point.\r
+ * | | |0001 = BPWM_CH2 period point.\r
+ * | | |0010 = BPWM_CH2 zero or period point.\r
+ * | | |0011 = BPWM_CH2 up-count CMPDAT point.\r
+ * | | |0100 = BPWM_CH2 down-count CMPDAT point.\r
+ * | | |0101 = Reserved.\r
+ * | | |0110 = Reserved.\r
+ * | | |0111 = Reserved.\r
+ * | | |1000 = BPWM_CH3 up-count CMPDAT point.\r
+ * | | |1001 = BPWM_CH3 down-count CMPDAT point.\r
+ * | | |Others reserved\r
+ * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit\r
+ * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select\r
+ * | | |0000 = BPWM_CH2 zero point.\r
+ * | | |0001 = BPWM_CH2 period point.\r
+ * | | |0010 = BPWM_CH2 zero or period point.\r
+ * | | |0011 = BPWM_CH2 up-count CMPDAT point.\r
+ * | | |0100 = BPWM_CH2 down-count CMPDAT point.\r
+ * | | |0101 = Reserved.\r
+ * | | |0110 = Reserved.\r
+ * | | |0111 = Reserved.\r
+ * | | |1000 = BPWM_CH3 up-count CMPDAT point.\r
+ * | | |1001 = BPWM_CH3 down-count CMPDAT point.\r
+ * | | |Others reserved.\r
+ * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit\r
+ * @var BPWM_T::EADCTS1\r
+ * Offset: 0xFC BPWM Trigger EADC Source Select Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select\r
+ * | | |0000 = BPWM_CH4 zero point.\r
+ * | | |0001 = BPWM_CH4 period point.\r
+ * | | |0010 = BPWM_CH4 zero or period point.\r
+ * | | |0011 = BPWM_CH4 up-count CMPDAT point.\r
+ * | | |0100 = BPWM_CH4 down-count CMPDAT point.\r
+ * | | |0101 = Reserved.\r
+ * | | |0110 = Reserved.\r
+ * | | |0111 = Reserved.\r
+ * | | |1000 = BPWM_CH5 up-count CMPDAT point.\r
+ * | | |1001 = BPWM_CH5 down-count CMPDAT point.\r
+ * | | |Others reserved\r
+ * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit\r
+ * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select\r
+ * | | |0000 = BPWM_CH4 zero point.\r
+ * | | |0001 = BPWM_CH4 period point.\r
+ * | | |0010 = BPWM_CH4 zero or period point.\r
+ * | | |0011 = BPWM_CH4 up-count CMPDAT point.\r
+ * | | |0100 = BPWM_CH4 down-count CMPDAT point.\r
+ * | | |0101 = Reserved.\r
+ * | | |0110 = Reserved.\r
+ * | | |0111 = Reserved.\r
+ * | | |1000 = BPWM_CH5 up-count CMPDAT point.\r
+ * | | |1001 = BPWM_CH5 down-count CMPDAT point.\r
+ * | | |Others reserved\r
+ * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit\r
+ * @var BPWM_T::SSCTL\r
+ * Offset: 0x110 BPWM Synchronous Start Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit\r
+ * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).\r
+ * | | |0 = BPWM synchronous start function Disabled.\r
+ * | | |1 = BPWM synchronous start function Enabled.\r
+ * |[9:8] |SSRC |BPWM Synchronous Start Source Select\r
+ * | | |00 = Synchronous start source come from PWM0.\r
+ * | | |01 = Synchronous start source come from PWM1.\r
+ * | | |10 = Synchronous start source come from BPWM0.\r
+ * | | |11 = Synchronous start source come from BPWM1.\r
+ * @var BPWM_T::SSTRG\r
+ * Offset: 0x114 BPWM Synchronous Start Trigger Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only)\r
+ * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\r
+ * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.\r
+ * @var BPWM_T::STATUS\r
+ * Offset: 0x120 BPWM Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status\r
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.\r
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.\r
+ * |[16] |EADCTRG0 |EADC Start of Conversion Status\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.\r
+ * |[17] |EADCTRG1 |EADC Start of Conversion Status\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.\r
+ * |[18] |EADCTRG2 |EADC Start of Conversion Status\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.\r
+ * |[19] |EADCTRG3 |EADC Start of Conversion Status\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.\r
+ * |[20] |EADCTRG4 |EADC Start of Conversion Status\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.\r
+ * |[21] |EADCTRG5 |EADC Start of Conversion Status\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.\r
+ * @var BPWM_T::CAPINEN\r
+ * Offset: 0x200 BPWM Capture Input Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CAPINEN0 |Capture Input Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM Channel capture input path Disabled\r
+ * | | |The input of BPWM channel capture function is always regarded as 0.\r
+ * | | |1 = BPWM Channel capture input path Enabled\r
+ * | | |The input of BPWM channel capture function comes from correlative multifunction pin.\r
+ * |[1] |CAPINEN1 |Capture Input Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM Channel capture input path Disabled\r
+ * | | |The input of BPWM channel capture function is always regarded as 0.\r
+ * | | |1 = BPWM Channel capture input path Enabled\r
+ * | | |The input of BPWM channel capture function comes from correlative multifunction pin.\r
+ * |[2] |CAPINEN2 |Capture Input Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM Channel capture input path Disabled\r
+ * | | |The input of BPWM channel capture function is always regarded as 0.\r
+ * | | |1 = BPWM Channel capture input path Enabled\r
+ * | | |The input of BPWM channel capture function comes from correlative multifunction pin.\r
+ * |[3] |CAPINEN3 |Capture Input Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM Channel capture input path Disabled\r
+ * | | |The input of BPWM channel capture function is always regarded as 0.\r
+ * | | |1 = BPWM Channel capture input path Enabled\r
+ * | | |The input of BPWM channel capture function comes from correlative multifunction pin.\r
+ * |[4] |CAPINEN4 |Capture Input Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM Channel capture input path Disabled\r
+ * | | |The input of BPWM channel capture function is always regarded as 0.\r
+ * | | |1 = BPWM Channel capture input path Enabled\r
+ * | | |The input of BPWM channel capture function comes from correlative multifunction pin.\r
+ * |[5] |CAPINEN5 |Capture Input Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = BPWM Channel capture input path Disabled\r
+ * | | |The input of BPWM channel capture function is always regarded as 0.\r
+ * | | |1 = BPWM Channel capture input path Enabled\r
+ * | | |The input of BPWM channel capture function comes from correlative multifunction pin.\r
+ * @var BPWM_T::CAPCTL\r
+ * Offset: 0x204 BPWM Capture Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CAPEN0 |Capture Function Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.\r
+ * | | |1 = Capture function Enabled\r
+ * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).\r
+ * |[1] |CAPEN1 |Capture Function Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.\r
+ * | | |1 = Capture function Enabled\r
+ * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).\r
+ * |[2] |CAPEN2 |Capture Function Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.\r
+ * | | |1 = Capture function Enabled\r
+ * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).\r
+ * |[3] |CAPEN3 |Capture Function Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.\r
+ * | | |1 = Capture function Enabled\r
+ * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).\r
+ * |[4] |CAPEN4 |Capture Function Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.\r
+ * | | |1 = Capture function Enabled\r
+ * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).\r
+ * |[5] |CAPEN5 |Capture Function Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.\r
+ * | | |1 = Capture function Enabled\r
+ * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).\r
+ * |[8] |CAPINV0 |Capture Inverter Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture source inverter Disabled.\r
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.\r
+ * |[9] |CAPINV1 |Capture Inverter Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture source inverter Disabled.\r
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.\r
+ * |[10] |CAPINV2 |Capture Inverter Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture source inverter Disabled.\r
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.\r
+ * |[11] |CAPINV3 |Capture Inverter Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture source inverter Disabled.\r
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.\r
+ * |[12] |CAPINV4 |Capture Inverter Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture source inverter Disabled.\r
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.\r
+ * |[13] |CAPINV5 |Capture Inverter Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture source inverter Disabled.\r
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.\r
+ * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Rising capture reload counter Disabled.\r
+ * | | |1 = Rising capture reload counter Enabled.\r
+ * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Rising capture reload counter Disabled.\r
+ * | | |1 = Rising capture reload counter Enabled.\r
+ * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Rising capture reload counter Disabled.\r
+ * | | |1 = Rising capture reload counter Enabled.\r
+ * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Rising capture reload counter Disabled.\r
+ * | | |1 = Rising capture reload counter Enabled.\r
+ * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Rising capture reload counter Disabled.\r
+ * | | |1 = Rising capture reload counter Enabled.\r
+ * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Rising capture reload counter Disabled.\r
+ * | | |1 = Rising capture reload counter Enabled.\r
+ * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Falling capture reload counter Disabled.\r
+ * | | |1 = Falling capture reload counter Enabled.\r
+ * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Falling capture reload counter Disabled.\r
+ * | | |1 = Falling capture reload counter Enabled.\r
+ * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Falling capture reload counter Disabled.\r
+ * | | |1 = Falling capture reload counter Enabled.\r
+ * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Falling capture reload counter Disabled.\r
+ * | | |1 = Falling capture reload counter Enabled.\r
+ * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Falling capture reload counter Disabled.\r
+ * | | |1 = Falling capture reload counter Enabled.\r
+ * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Falling capture reload counter Disabled.\r
+ * | | |1 = Falling capture reload counter Enabled.\r
+ * @var BPWM_T::CAPSTS\r
+ * Offset: 0x208 BPWM Capture Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.\r
+ * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.\r
+ * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.\r
+ * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.\r
+ * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.\r
+ * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.\r
+ * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.\r
+ * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.\r
+ * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.\r
+ * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.\r
+ * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.\r
+ * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.\r
+ * @var BPWM_T::CAPIEN\r
+ * Offset: 0x250 BPWM Capture Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture rising edge latch interrupt Disabled.\r
+ * | | |1 = Capture rising edge latch interrupt Enabled.\r
+ * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits\r
+ * | | |Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = Capture falling edge latch interrupt Disabled.\r
+ * | | |1 = Capture falling edge latch interrupt Enabled.\r
+ * @var BPWM_T::CAPIF\r
+ * Offset: 0x254 BPWM Capture Interrupt Flag Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = No capture rising latch condition happened.\r
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.\r
+ * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = No capture rising latch condition happened.\r
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.\r
+ * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = No capture rising latch condition happened.\r
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.\r
+ * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = No capture rising latch condition happened.\r
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.\r
+ * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = No capture rising latch condition happened.\r
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.\r
+ * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = No capture rising latch condition happened.\r
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.\r
+ * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = No capture falling latch condition happened.\r
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.\r
+ * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = No capture falling latch condition happened.\r
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.\r
+ * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = No capture falling latch condition happened.\r
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.\r
+ * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = No capture falling latch condition happened.\r
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.\r
+ * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = No capture falling latch condition happened.\r
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.\r
+ * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\r
+ * | | |0 = No capture falling latch condition happened.\r
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.\r
+ * @var BPWM_T::PBUF\r
+ * Offset: 0x304 BPWM PERIOD Buffer\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |PBUF |BPWM Period Buffer (Read Only)\r
+ * | | |Used as PERIOD active register.\r
+ * @var BPWM_T::CMPBUF[6]\r
+ * Offset: 0x31C BPWM CMPDAT 0~5 Buffer\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only)\r
+ * | | |Used as CMP active register.\r
+ */\r
+ __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */\r
+ __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */\r
+ __I uint32_t RESERVED0[2];\r
+ __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */\r
+ __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */\r
+ __I uint32_t RESERVED1[2];\r
+ __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */\r
+ __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */\r
+ __I uint32_t RESERVED2[2];\r
+ __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */\r
+ __I uint32_t RESERVED3[7];\r
+ __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] BPWM Comparator Register 0~5 */\r
+ __I uint32_t RESERVED4[10];\r
+ __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */\r
+ __I uint32_t RESERVED5[7];\r
+ __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */\r
+ __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */\r
+ __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */\r
+ __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */\r
+ __I uint32_t RESERVED6[5];\r
+ __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */\r
+ __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */\r
+ __I uint32_t RESERVED7[1];\r
+ __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */\r
+ __I uint32_t RESERVED8[1];\r
+ __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */\r
+ __I uint32_t RESERVED9[3];\r
+ __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */\r
+ __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */\r
+ __I uint32_t RESERVED10[4];\r
+ __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */\r
+ __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */\r
+ __I uint32_t RESERVED11[2];\r
+ __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */\r
+ __I uint32_t RESERVED12[55];\r
+ __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */\r
+ __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */\r
+ __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */\r
+ BCAPDAT_T CAPDAT[6]; /*!< [0x020c~0x0238] BPWM Rising and Falling Capture Data Register 0~5 */\r
+ __I uint32_t RESERVED13[5];\r
+ __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */\r
+ __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */\r
+ __I uint32_t RESERVED14[43];\r
+ __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */\r
+ __I uint32_t RESERVED15[5];\r
+ __I uint32_t CMPBUF[6]; /*!< [0x031c~0x0330] BPWM CMPDAT 0~5 Buffer */\r
+\r
+} BPWM_T;\r
+\r
+/**\r
+ @addtogroup BPWM_CONST BPWM Bit Field Definition\r
+ Constant Definitions for BPWM Controller\r
+@{ */\r
+\r
+#define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */\r
+#define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */\r
+\r
+#define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */\r
+#define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */\r
+\r
+#define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */\r
+#define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */\r
+\r
+#define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */\r
+#define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */\r
+\r
+#define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */\r
+#define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */\r
+\r
+#define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */\r
+#define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */\r
+\r
+#define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */\r
+#define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */\r
+\r
+#define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */\r
+#define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */\r
+\r
+#define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */\r
+#define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */\r
+\r
+#define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */\r
+#define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */\r
+\r
+#define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */\r
+#define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */\r
+\r
+#define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */\r
+#define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */\r
+\r
+#define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */\r
+#define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */\r
+\r
+#define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */\r
+#define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */\r
+\r
+#define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */\r
+#define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */\r
+\r
+#define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */\r
+#define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */\r
+\r
+#define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */\r
+#define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */\r
+\r
+#define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */\r
+#define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */\r
+\r
+#define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */\r
+#define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */\r
+\r
+#define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */\r
+#define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */\r
+\r
+#define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */\r
+#define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */\r
+\r
+#define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */\r
+#define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */\r
+\r
+#define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */\r
+#define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */\r
+\r
+#define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */\r
+#define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */\r
+\r
+#define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */\r
+#define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */\r
+\r
+#define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */\r
+#define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */\r
+\r
+#define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */\r
+#define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */\r
+\r
+#define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */\r
+#define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */\r
+\r
+#define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */\r
+#define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */\r
+\r
+#define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */\r
+#define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */\r
+\r
+#define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */\r
+#define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */\r
+\r
+#define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */\r
+#define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */\r
+\r
+#define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */\r
+#define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */\r
+\r
+#define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */\r
+#define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */\r
+\r
+#define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */\r
+#define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */\r
+\r
+#define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */\r
+#define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */\r
+\r
+#define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */\r
+#define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */\r
+\r
+#define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */\r
+#define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */\r
+\r
+#define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */\r
+#define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */\r
+\r
+#define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */\r
+#define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */\r
+\r
+#define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */\r
+#define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */\r
+\r
+#define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */\r
+#define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */\r
+\r
+#define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */\r
+#define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */\r
+\r
+#define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */\r
+#define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */\r
+\r
+#define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */\r
+#define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */\r
+\r
+#define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */\r
+#define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */\r
+\r
+#define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */\r
+#define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */\r
+\r
+#define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */\r
+#define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */\r
+\r
+#define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */\r
+#define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */\r
+\r
+#define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */\r
+#define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */\r
+\r
+#define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */\r
+#define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */\r
+\r
+#define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */\r
+#define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */\r
+\r
+#define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */\r
+#define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */\r
+\r
+#define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */\r
+#define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */\r
+\r
+#define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */\r
+#define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */\r
+\r
+#define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */\r
+#define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */\r
+\r
+#define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */\r
+#define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */\r
+\r
+#define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */\r
+#define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */\r
+\r
+#define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */\r
+#define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */\r
+\r
+#define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */\r
+#define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */\r
+\r
+#define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */\r
+#define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */\r
+\r
+#define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */\r
+#define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */\r
+\r
+#define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */\r
+#define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */\r
+\r
+#define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */\r
+#define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */\r
+\r
+#define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */\r
+#define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */\r
+\r
+#define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */\r
+#define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */\r
+\r
+#define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */\r
+#define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */\r
+\r
+#define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */\r
+#define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */\r
+\r
+#define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */\r
+#define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */\r
+\r
+#define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */\r
+#define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */\r
+\r
+#define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */\r
+#define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */\r
+\r
+#define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */\r
+#define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */\r
+\r
+#define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */\r
+#define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */\r
+\r
+#define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */\r
+#define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */\r
+\r
+#define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */\r
+#define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */\r
+\r
+#define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */\r
+#define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */\r
+\r
+#define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */\r
+#define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */\r
+\r
+#define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */\r
+#define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */\r
+\r
+#define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */\r
+#define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */\r
+\r
+#define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */\r
+#define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */\r
+\r
+#define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */\r
+#define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */\r
+\r
+#define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */\r
+#define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */\r
+\r
+#define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */\r
+#define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */\r
+\r
+#define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */\r
+#define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */\r
+\r
+#define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */\r
+#define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */\r
+\r
+#define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */\r
+#define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */\r
+\r
+#define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */\r
+#define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */\r
+\r
+#define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */\r
+#define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */\r
+\r
+#define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */\r
+#define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */\r
+\r
+#define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */\r
+#define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */\r
+\r
+#define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */\r
+#define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */\r
+\r
+#define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */\r
+#define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */\r
+\r
+#define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */\r
+#define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */\r
+\r
+#define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */\r
+#define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */\r
+\r
+#define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */\r
+#define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */\r
+\r
+#define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */\r
+#define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */\r
+\r
+#define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */\r
+#define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */\r
+\r
+#define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */\r
+#define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */\r
+\r
+#define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */\r
+#define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */\r
+\r
+#define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */\r
+#define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */\r
+\r
+#define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */\r
+#define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */\r
+\r
+#define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */\r
+#define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */\r
+\r
+#define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */\r
+#define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */\r
+\r
+#define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */\r
+#define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */\r
+\r
+#define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */\r
+#define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */\r
+\r
+#define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */\r
+#define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */\r
+\r
+#define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */\r
+#define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */\r
+\r
+#define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */\r
+#define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */\r
+\r
+#define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */\r
+#define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */\r
+\r
+#define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */\r
+#define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */\r
+\r
+#define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */\r
+#define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */\r
+\r
+#define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */\r
+#define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */\r
+\r
+#define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */\r
+#define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */\r
+\r
+#define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */\r
+#define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */\r
+\r
+#define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */\r
+#define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */\r
+\r
+#define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */\r
+#define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */\r
+\r
+#define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */\r
+#define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */\r
+\r
+#define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */\r
+#define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */\r
+\r
+#define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */\r
+#define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */\r
+\r
+#define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */\r
+#define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */\r
+\r
+#define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */\r
+#define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */\r
+\r
+#define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */\r
+#define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */\r
+\r
+#define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */\r
+#define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */\r
+\r
+#define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */\r
+#define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */\r
+\r
+#define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */\r
+#define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */\r
+\r
+#define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */\r
+#define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */\r
+\r
+#define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */\r
+#define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */\r
+\r
+#define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */\r
+#define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */\r
+\r
+#define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */\r
+#define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */\r
+\r
+#define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */\r
+#define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */\r
+\r
+#define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */\r
+#define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */\r
+\r
+#define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */\r
+#define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */\r
+\r
+#define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */\r
+#define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */\r
+\r
+#define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */\r
+#define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */\r
+\r
+#define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */\r
+#define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */\r
+\r
+#define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */\r
+#define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */\r
+\r
+#define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */\r
+#define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */\r
+\r
+#define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */\r
+#define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */\r
+\r
+#define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */\r
+#define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */\r
+\r
+#define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */\r
+#define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */\r
+\r
+#define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */\r
+#define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */\r
+\r
+#define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */\r
+#define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */\r
+\r
+#define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */\r
+#define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */\r
+\r
+#define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */\r
+#define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */\r
+\r
+#define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */\r
+#define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */\r
+\r
+#define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */\r
+#define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */\r
+\r
+#define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */\r
+#define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */\r
+\r
+#define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */\r
+#define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */\r
+\r
+#define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */\r
+#define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */\r
+\r
+#define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */\r
+#define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */\r
+\r
+#define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */\r
+#define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */\r
+\r
+#define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */\r
+#define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */\r
+\r
+#define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */\r
+#define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */\r
+\r
+#define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */\r
+#define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */\r
+\r
+#define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */\r
+#define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */\r
+\r
+#define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */\r
+#define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */\r
+\r
+#define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */\r
+#define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */\r
+\r
+#define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */\r
+#define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */\r
+\r
+#define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */\r
+#define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */\r
+\r
+#define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */\r
+#define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */\r
+\r
+#define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */\r
+#define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */\r
+\r
+#define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */\r
+#define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */\r
+\r
+#define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */\r
+#define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */\r
+\r
+#define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */\r
+#define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */\r
+\r
+#define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */\r
+#define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */\r
+\r
+#define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */\r
+#define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */\r
+\r
+#define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */\r
+#define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */\r
+\r
+#define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */\r
+#define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */\r
+\r
+#define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */\r
+#define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */\r
+\r
+#define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */\r
+#define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */\r
+\r
+#define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */\r
+#define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */\r
+\r
+#define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */\r
+#define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */\r
+\r
+#define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */\r
+#define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */\r
+\r
+#define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */\r
+#define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */\r
+\r
+#define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */\r
+#define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */\r
+\r
+#define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */\r
+#define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */\r
+\r
+#define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */\r
+#define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */\r
+\r
+#define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */\r
+#define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */\r
+\r
+#define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */\r
+#define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */\r
+\r
+#define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */\r
+#define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */\r
+\r
+#define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */\r
+#define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */\r
+\r
+#define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */\r
+#define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */\r
+\r
+#define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */\r
+#define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */\r
+\r
+#define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */\r
+#define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */\r
+\r
+#define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */\r
+#define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */\r
+\r
+#define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */\r
+#define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */\r
+\r
+#define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */\r
+#define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */\r
+\r
+#define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */\r
+#define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */\r
+\r
+#define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */\r
+#define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */\r
+\r
+#define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */\r
+#define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */\r
+\r
+#define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */\r
+#define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */\r
+\r
+#define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */\r
+#define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */\r
+\r
+#define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */\r
+#define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */\r
+\r
+#define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */\r
+#define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */\r
+\r
+#define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */\r
+#define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */\r
+\r
+#define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */\r
+#define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */\r
+\r
+#define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */\r
+#define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */\r
+\r
+#define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */\r
+#define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */\r
+\r
+#define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */\r
+#define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */\r
+\r
+#define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */\r
+#define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */\r
+\r
+#define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */\r
+#define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */\r
+\r
+#define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */\r
+#define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */\r
+\r
+#define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */\r
+#define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */\r
+\r
+#define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */\r
+#define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */\r
+\r
+#define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */\r
+#define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */\r
+\r
+#define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */\r
+#define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */\r
+\r
+#define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */\r
+#define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */\r
+\r
+#define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */\r
+#define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */\r
+\r
+#define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */\r
+#define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */\r
+\r
+#define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */\r
+#define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */\r
+\r
+#define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */\r
+#define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */\r
+\r
+#define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */\r
+#define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */\r
+\r
+#define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */\r
+#define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */\r
+\r
+#define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */\r
+#define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */\r
+\r
+#define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */\r
+#define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */\r
+\r
+#define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */\r
+#define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */\r
+\r
+#define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */\r
+#define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */\r
+\r
+#define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */\r
+#define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */\r
+\r
+#define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */\r
+#define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */\r
+\r
+#define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */\r
+#define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */\r
+\r
+#define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */\r
+#define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */\r
+\r
+#define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */\r
+#define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */\r
+\r
+#define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */\r
+#define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */\r
+\r
+/**@}*/ /* BPWM_CONST */\r
+/**@}*/ /* end of BPWM register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __BPWM_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file can_reg.h\r
+ * @version V1.00\r
+ * @brief CAN register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __CAN_REG_H__\r
+#define __CAN_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- Controller Area Network Controller -------------------------*/\r
+/**\r
+ @addtogroup CAN Controller Area Network Controller(CAN)\r
+ Memory Mapped Structure for CAN Controller\r
+@{ */\r
+\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+\r
+ /**\r
+ * @var CAN_IF_T::CREQ\r
+ * Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[5:0] |MessageNumber|Message Number\r
+ * | | |0x01-0x20: Valid Message Number, the Message Object in the Message\r
+ * | | |RAM is selected for data transfer.\r
+ * | | |0x00: Not a valid Message Number, interpreted as 0x20.\r
+ * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.\r
+ * |[15] |Busy |Busy Flag\r
+ * | | |0 = Read/write action has finished.\r
+ * | | |1 = Writing to the IFn Command Request Register is in progress.\r
+ * | | |This bit can only be read by the software.\r
+ * @var CAN_IF_T::CMASK\r
+ * Offset: 0x24, 0x84 IFn Command Mask Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |DAT_B |Access Data Bytes [7:4]\r
+ * | | |Write Operation:\r
+ * | | |0 = Data Bytes [7:4] unchanged.\r
+ * | | |1 = Transfer Data Bytes [7:4] to Message Object.\r
+ * | | |Read Operation:\r
+ * | | |0 = Data Bytes [7:4] unchanged.\r
+ * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.\r
+ * |[1] |DAT_A |Access Data Bytes [3:0]\r
+ * | | |Write Operation:\r
+ * | | |0 = Data Bytes [3:0] unchanged.\r
+ * | | |1 = Transfer Data Bytes [3:0] to Message Object.\r
+ * | | |Read Operation:\r
+ * | | |0 = Data Bytes [3:0] unchanged.\r
+ * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.\r
+ * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation\r
+ * | | |0 = TxRqst bit unchanged.\r
+ * | | |1 = Set TxRqst bit.\r
+ * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.\r
+ * | | |Access New Data Bit when Read Operation.\r
+ * | | |0 = NewDat bit remains unchanged.\r
+ * | | |1 = Clear NewDat bit in the Message Object.\r
+ * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.\r
+ * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.\r
+ * |[3] |ClrIntPnd |Clear Interrupt Pending Bit\r
+ * | | |Write Operation:\r
+ * | | |When writing to a Message Object, this bit is ignored.\r
+ * | | |Read Operation:\r
+ * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.\r
+ * | | |1 = Clear IntPnd bit in the Message Object.\r
+ * |[4] |Control |Control Access Control Bits\r
+ * | | |Write Operation:\r
+ * | | |0 = Control Bits unchanged.\r
+ * | | |1 = Transfer Control Bits to Message Object.\r
+ * | | |Read Operation:\r
+ * | | |0 = Control Bits unchanged.\r
+ * | | |1 = Transfer Control Bits to IFn Message Buffer Register.\r
+ * |[5] |Arb |Access Arbitration Bits\r
+ * | | |Write Operation:\r
+ * | | |0 = Arbitration bits unchanged.\r
+ * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.\r
+ * | | |Read Operation:\r
+ * | | |0 = Arbitration bits unchanged.\r
+ * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.\r
+ * |[6] |Mask |Access Mask Bits\r
+ * | | |Write Operation:\r
+ * | | |0 = Mask bits unchanged.\r
+ * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.\r
+ * | | |Read Operation:\r
+ * | | |0 = Mask bits unchanged.\r
+ * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.\r
+ * |[7] |WR_RD |Write / Read Mode\r
+ * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.\r
+ * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.\r
+ * @var CAN_IF_T::MASK1\r
+ * Offset: 0x28, 0x88 IFn Mask 1 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |Msk[15:0] |Identifier Mask 15-0\r
+ * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.\r
+ * | | |1 = The corresponding identifier bit is used for acceptance filtering.\r
+ * @var CAN_IF_T::MASK2\r
+ * Offset: 0x2C, 0x8C IFn Mask 2 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[12:0] |Msk[28:16]|Identifier Mask 28-16\r
+ * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.\r
+ * | | |1 = The corresponding identifier bit is used for acceptance filtering.\r
+ * |[14] |MDir |Mask Message Direction\r
+ * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.\r
+ * | | |1 = The message direction bit (Dir) is used for acceptance filtering.\r
+ * |[15] |MXtd |Mask Extended Identifier\r
+ * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.\r
+ * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.\r
+ * | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).\r
+ * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.\r
+ * @var CAN_IF_T::ARB1\r
+ * Offset: 0x30, 0x90 IFn Arbitration 1 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |ID[15:0] |Message Identifier 15-0\r
+ * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").\r
+ * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")\r
+ * @var CAN_IF_T::ARB2\r
+ * Offset: 0x34, 0x94 IFn Arbitration 2 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[12:0] |ID[28:16] |Message Identifier 28-16\r
+ * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").\r
+ * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")\r
+ * |[13] |Dir |Message Direction\r
+ * | | |0 = Direction is receive.\r
+ * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.\r
+ * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.\r
+ * | | |1 = Direction is transmit.\r
+ * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame.\r
+ * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).\r
+ * |[14] |Xtd |Extended Identifier\r
+ * | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object.\r
+ * | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object.\r
+ * |[15] |MsgVal |Message Valid\r
+ * | | |0 = The Message Object is ignored by the Message Handler.\r
+ * | | |1 = The Message Object is configured and should be considered by the Message Handler.\r
+ * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).\r
+ * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.\r
+ * @var CAN_IF_T::MCON\r
+ * Offset: 0x38, 0x98 IFn Message Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |DLC |Data Length Code\r
+ * | | |0-8: Data Frame has 0-8 data bytes.\r
+ * | | |9-15: Data Frame has 8 data bytes\r
+ * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.\r
+ * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.\r
+ * | | |Data 0: 1st data byte of a CAN Data Frame\r
+ * | | |Data 1: 2nd data byte of a CAN Data Frame\r
+ * | | |Data 2: 3rd data byte of a CAN Data Frame\r
+ * | | |Data 3: 4th data byte of a CAN Data Frame\r
+ * | | |Data 4: 5th data byte of a CAN Data Frame\r
+ * | | |Data 5: 6th data byte of a CAN Data Frame\r
+ * | | |Data 6: 7th data byte of a CAN Data Frame\r
+ * | | |Data 7 : 8th data byte of a CAN Data Frame\r
+ * | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.\r
+ * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.\r
+ * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.\r
+ * |[7] |EoB |End Of Buffer\r
+ * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.\r
+ * | | |1 = Single Message Object or last Message Object of a FIFO Buffer.\r
+ * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.\r
+ * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.\r
+ * |[8] |TxRqst |Transmit Request\r
+ * | | |0 = This Message Object is not waiting for transmission.\r
+ * | | |1 = The transmission of this Message Object is requested and is not yet done.\r
+ * |[9] |RmtEn |Remote Enable Control\r
+ * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.\r
+ * | | |1 = At the reception of a Remote Frame, TxRqst is set.\r
+ * |[10] |RxIE |Receive Interrupt Enable Control\r
+ * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.\r
+ * | | |1 = IntPnd will be set after a successful reception of a frame.\r
+ * |[11] |TxIE |Transmit Interrupt Enable Control\r
+ * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.\r
+ * | | |1 = IntPnd will be set after a successful transmission of a frame.\r
+ * |[12] |UMask |Use Acceptance Mask\r
+ * | | |0 = Mask ignored.\r
+ * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.\r
+ * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.\r
+ * |[13] |IntPnd |Interrupt Pending\r
+ * | | |0 = This message object is not the source of an interrupt.\r
+ * | | |1 = This message object is the source of an interrupt.\r
+ * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.\r
+ * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).\r
+ * | | |0 = No message lost since last time this bit was reset by the CPU.\r
+ * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.\r
+ * |[15] |NewDat |New Data\r
+ * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.\r
+ * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.\r
+ * @var CAN_IF_T::DAT_A1\r
+ * Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |Data0 |Data Byte 0\r
+ * | | |1st data byte of a CAN Data Frame\r
+ * |[15:8] |Data1 |Data Byte 1\r
+ * | | |2nd data byte of a CAN Data Frame\r
+ * @var CAN_IF_T::DAT_A2\r
+ * Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |Data2 |Data Byte 2\r
+ * | | |3rd data byte of CAN Data Frame\r
+ * |[15:8] |Data3 |Data Byte 3\r
+ * | | |4th data byte of CAN Data Frame\r
+ * @var CAN_IF_T::DAT_B1\r
+ * Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |Data4 |Data Byte 4\r
+ * | | |5th data byte of CAN Data Frame\r
+ * |[15:8] |Data5 |Data Byte 5\r
+ * | | |6th data byte of CAN Data Frame\r
+ * @var CAN_IF_T::DAT_B2\r
+ * Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |Data6 |Data Byte 6\r
+ * | | |7th data byte of CAN Data Frame.\r
+ * |[15:8] |Data7 |Data Byte 7\r
+ * | | |8th data byte of CAN Data Frame.\r
+ */\r
+\r
+ __IO uint32_t CREQ; /* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers */\r
+ __IO uint32_t CMASK; /* Offset: 0x24, 0x84 IFn Command Mask Register */\r
+ __IO uint32_t MASK1; /* Offset: 0x28, 0x88 IFn Mask 1 Register */\r
+ __IO uint32_t MASK2; /* Offset: 0x2C, 0x8C IFn Mask 2 Register */\r
+ __IO uint32_t ARB1; /* Offset: 0x30, 0x90 IFn Arbitration 1 Register */\r
+ __IO uint32_t ARB2; /* Offset: 0x34, 0x94 IFn Arbitration 2 Register */\r
+ __IO uint32_t MCON; /* Offset: 0x38, 0x98 IFn Message Control Register */\r
+ __IO uint32_t DAT_A1; /* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) */\r
+ __IO uint32_t DAT_A2; /* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) */\r
+ __IO uint32_t DAT_B1; /* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) */\r
+ __IO uint32_t DAT_B2; /* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) */\r
+ __I uint32_t RESERVE0[13];\r
+\r
+} CAN_IF_T;\r
+\r
+\r
+\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+\r
+ /**\r
+ * @var CAN_T::CON\r
+ * Offset: 0x00 Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |Init |Init Initialization\r
+ * | | |0 = Normal Operation.\r
+ * | | |1 = Initialization is started.\r
+ * |[1] |IE |Module Interrupt Enable Control\r
+ * | | |0 = Disabled.\r
+ * | | |1 = Enabled.\r
+ * |[2] |SIE |Status Change Interrupt Enable Control\r
+ * | | |0 = Disabled - No Status Change Interrupt will be generated.\r
+ * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.\r
+ * |[3] |EIE |Error Interrupt Enable Control\r
+ * | | |0 = Disabled - No Error Status Interrupt will be generated.\r
+ * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.\r
+ * |[5] |DAR |Automatic Re-Transmission Disable Control\r
+ * | | |0 = Automatic Retransmission of disturbed messages enabled.\r
+ * | | |1 = Automatic Retransmission disabled.\r
+ * |[6] |CCE |Configuration Change Enable Control\r
+ * | | |0 = No write access to the Bit Timing Register.\r
+ * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).\r
+ * |[7] |Test |Test Mode Enable Control\r
+ * | | |0 = Normal Operation.\r
+ * | | |1 = Test Mode.\r
+ * @var CAN_T::STATUS\r
+ * Offset: 0x04 Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)\r
+ * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.\r
+ * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.\r
+ * | | |The unused code '7' may be written by the CPU to check for updates.\r
+ * | | |The following table describes the error code.\r
+ * |[3] |TxOK |Transmitted A Message Successfully\r
+ * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.\r
+ * | | |This bit is never reset by the CAN Core.\r
+ * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.\r
+ * |[4] |RxOK |Received A Message Successfully\r
+ * | | |0 = No message has been successfully received since this bit was last reset by the CPU.\r
+ * | | |This bit is never reset by the CAN Core.\r
+ * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).\r
+ * |[5] |EPass |Error Passive (Read Only)\r
+ * | | |0 = The CAN Core is error active.\r
+ * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.\r
+ * |[6] |EWarn |Error Warning Status (Read Only)\r
+ * | | |0 = Both error counters are below the error warning limit of 96.\r
+ * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.\r
+ * |[7] |BOff |Bus-Off Status (Read Only)\r
+ * | | |0 = The CAN module is not in bus-off state.\r
+ * | | |1 = The CAN module is in bus-off state.\r
+ * @var CAN_T::ERR\r
+ * Offset: 0x08 Error Counter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |TEC |Transmit Error Counter\r
+ * | | |Actual state of the Transmit Error Counter. Values between 0 and 255.\r
+ * |[14:8] |REC |Receive Error Counter\r
+ * | | |Actual state of the Receive Error Counter. Values between 0 and 127.\r
+ * |[15] |RP |Receive Error Passive\r
+ * | | |0 = The Receive Error Counter is below the error passive level.\r
+ * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.\r
+ * @var CAN_T::BTIME\r
+ * Offset: 0x0C Bit Timing Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[5:0] |BRP |Baud Rate Prescaler\r
+ * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.\r
+ * | | |The bit time is built up from a multiple of this quanta.\r
+ * | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].\r
+ * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.\r
+ * |[7:6] |SJW |(Re)Synchronization Jump Width\r
+ * | | |0x0-0x3: Valid programmed values are [0 ... 3].\r
+ * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.\r
+ * |[11:8] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg\r
+ * | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15].\r
+ * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.\r
+ * |[14:12] |TSeg2 |Time Segment After Sample Point\r
+ * | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7].\r
+ * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.\r
+ * @var CAN_T::IIDR\r
+ * Offset: 0x10 Interrupt Identifier Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt)\r
+ * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.\r
+ * | | |An interrupt remains pending until the application software has cleared it.\r
+ * | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.\r
+ * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.\r
+ * | | |The Status Interrupt has the highest priority.\r
+ * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.\r
+ * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).\r
+ * | | |The Status Interrupt is cleared by reading the Status Register.\r
+ * @var CAN_T::TEST\r
+ * Offset: 0x14 Test Register (Register Map Note 1)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |Res |Reserved\r
+ * | | |There are reserved bits.\r
+ * | | |These bits are always read as '0' and must always be written with '0'.\r
+ * |[2] |Basic |Basic Mode\r
+ * | | |0 = Basic Mode disabled.\r
+ * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.\r
+ * |[3] |Silent |Silent Mode\r
+ * | | |0 = Normal operation.\r
+ * | | |1 = The module is in Silent Mode.\r
+ * |[4] |LBack |Loop Back Mode Enable Control\r
+ * | | |0 = Loop Back Mode is disabled.\r
+ * | | |1 = Loop Back Mode is enabled.\r
+ * |[6:5] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin\r
+ * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.\r
+ * | | |01 = Sample Point can be monitored at CAN_TX pin.\r
+ * | | |10 = CAN_TX pin drives a dominant ('0') value.\r
+ * | | |11 = CAN_TX pin drives a recessive ('1') value.\r
+ * |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only)\r
+ * | | |0 = The CAN bus is dominant (CAN_RX = '0').\r
+ * | | |1 = The CAN bus is recessive (CAN_RX = '1').\r
+ * @var CAN_T::BRPE\r
+ * Offset: 0x18 Baud Rate Prescaler Extension Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension\r
+ * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.\r
+ * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.\r
+ * @var CAN_T::IF\r
+ * Offset: 0x20~0xFC CAN Interface Registers\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * CAN interface structure. Refer to \ref CAN_IF_T for detail information.\r
+ *\r
+ * @var CAN_T::TXREQ1\r
+ * Offset: 0x100 Transmission Request Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects)\r
+ * | | |0 = This Message Object is not waiting for transmission.\r
+ * | | |1 = The transmission of this Message Object is requested and is not yet done.\r
+ * | | |These bits are read only.\r
+ * @var CAN_T::TXREQ2\r
+ * Offset: 0x104 Transmission Request Register 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects)\r
+ * | | |0 = This Message Object is not waiting for transmission.\r
+ * | | |1 = The transmission of this Message Object is requested and is not yet done.\r
+ * | | |These bits are read only.\r
+ * @var CAN_T::NDAT1\r
+ * Offset: 0x120 New Data Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects)\r
+ * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.\r
+ * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.\r
+ * @var CAN_T::NDAT2\r
+ * Offset: 0x124 New Data Register 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects)\r
+ * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.\r
+ * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.\r
+ * @var CAN_T::IPND1\r
+ * Offset: 0x140 Interrupt Pending Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects)\r
+ * | | |0 = This message object is not the source of an interrupt.\r
+ * | | |1 = This message object is the source of an interrupt.\r
+ * @var CAN_T::IPND2\r
+ * Offset: 0x144 Interrupt Pending Register 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects)\r
+ * | | |0 = This message object is not the source of an interrupt.\r
+ * | | |1 = This message object is the source of an interrupt.\r
+ * @var CAN_T::MVLD1\r
+ * Offset: 0x160 Message Valid Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only)\r
+ * | | |0 = This Message Object is ignored by the Message Handler.\r
+ * | | |1 = This Message Object is configured and should be considered by the Message Handler.\r
+ * | | |Ex.\r
+ * | | |CAN_MVLD1[0] means Message object No.1 is valid or not.\r
+ * | | |If CAN_MVLD1[0] is set, message object No.1 is configured.\r
+ * @var CAN_T::MVLD2\r
+ * Offset: 0x164 Message Valid Register 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)\r
+ * | | |0 = This Message Object is ignored by the Message Handler.\r
+ * | | |1 = This Message Object is configured and should be considered by the Message Handler.\r
+ * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.\r
+ * | | |If CAN_MVLD2[15] is set, message object No.32 is configured.\r
+ * @var CAN_T::WU_EN\r
+ * Offset: 0x168 Wake-up Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WAKUP_EN |Wake-Up Enable Control\r
+ * | | |0 = The wake-up function Disabled.\r
+ * | | |1 = The wake-up function Enabled.\r
+ * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.\r
+ * @var CAN_T::WU_STATUS\r
+ * Offset: 0x16C Wake-up Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WAKUP_STS |Wake-Up Status\r
+ * | | |0 = No wake-up event occurred.\r
+ * | | |1 = Wake-up event occurred.\r
+ * | | |Note: This bit can be cleared by writing '0'.\r
+ */\r
+\r
+ __IO uint32_t CON; /* Offset: 0x00 Control Register */\r
+ __IO uint32_t STATUS; /* Offset: 0x04 Status Register */\r
+ __I uint32_t ERR; /* Offset: 0x08 Error Counter Register */\r
+ __IO uint32_t BTIME; /* Offset: 0x0C Bit Timing Register */\r
+ __I uint32_t IIDR; /* Offset: 0x10 Interrupt Identifier Register */\r
+ __IO uint32_t TEST; /* Offset: 0x14 Test Register (Register Map Note 1) */\r
+ __IO uint32_t BRPE; /* Offset: 0x18 Baud Rate Prescaler Extension Register */\r
+ __I uint32_t RESERVE0[1];\r
+ __IO CAN_IF_T IF[2]; /* Offset: 0x20~0xFC CAN Interface Registers */\r
+ __I uint32_t RESERVE1[8];\r
+ __I uint32_t TXREQ1; /* Offset: 0x100 Transmission Request Register 1 */\r
+ __I uint32_t TXREQ2; /* Offset: 0x104 Transmission Request Register 2 */\r
+ __I uint32_t RESERVE3[6];\r
+ __I uint32_t NDAT1; /* Offset: 0x120 New Data Register 1 */\r
+ __I uint32_t NDAT2; /* Offset: 0x124 New Data Register 2 */\r
+ __I uint32_t RESERVE4[6];\r
+ __I uint32_t IPND1; /* Offset: 0x140 Interrupt Pending Register 1 */\r
+ __I uint32_t IPND2; /* Offset: 0x144 Interrupt Pending Register 2 */\r
+ __I uint32_t RESERVE5[6];\r
+ __I uint32_t MVLD1; /* Offset: 0x160 Message Valid Register 1 */\r
+ __I uint32_t MVLD2; /* Offset: 0x164 Message Valid Register 2 */\r
+ __IO uint32_t WU_EN; /* Offset: 0x168 Wake-up Enable Register */\r
+ __IO uint32_t WU_STATUS; /* Offset: 0x16C Wake-up Status Register */\r
+\r
+} CAN_T;\r
+\r
+\r
+\r
+/**\r
+ @addtogroup CAN_CONST CAN Bit Field Definition\r
+ Constant Definitions for CAN Controller\r
+@{ */\r
+/* CAN CON Bit Field Definitions */\r
+#define CAN_CON_TEST_Pos 7 /*!< CAN_T::CON: TEST Position */\r
+#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: TEST Mask */\r
+\r
+#define CAN_CON_CCE_Pos 6 /*!< CAN_T::CON: CCE Position */\r
+#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */\r
+\r
+#define CAN_CON_DAR_Pos 5 /*!< CAN_T::CON: DAR Position */\r
+#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */\r
+\r
+#define CAN_CON_EIE_Pos 3 /*!< CAN_T::CON: EIE Position */\r
+#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */\r
+\r
+#define CAN_CON_SIE_Pos 2 /*!< CAN_T::CON: SIE Position */\r
+#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */\r
+\r
+#define CAN_CON_IE_Pos 1 /*!< CAN_T::CON: IE Position */\r
+#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */\r
+\r
+#define CAN_CON_INIT_Pos 0 /*!< CAN_T::CON: INIT Position */\r
+#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: INIT Mask */\r
+\r
+/* CAN STATUS Bit Field Definitions */\r
+#define CAN_STATUS_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */\r
+#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */\r
+\r
+#define CAN_STATUS_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */\r
+#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */\r
+\r
+#define CAN_STATUS_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */\r
+#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */\r
+\r
+#define CAN_STATUS_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */\r
+#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */\r
+\r
+#define CAN_STATUS_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */\r
+#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */\r
+\r
+#define CAN_STATUS_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */\r
+#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */\r
+\r
+/* CAN ERR Bit Field Definitions */\r
+#define CAN_ERR_RP_Pos 15 /*!< CAN_T::ERR: RP Position */\r
+#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */\r
+\r
+#define CAN_ERR_REC_Pos 8 /*!< CAN_T::ERR: REC Position */\r
+#define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */\r
+\r
+#define CAN_ERR_TEC_Pos 0 /*!< CAN_T::ERR: TEC Position */\r
+#define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */\r
+\r
+/* CAN BTIME Bit Field Definitions */\r
+#define CAN_BTIME_TSEG2_Pos 12 /*!< CAN_T::BTIME: TSEG2 Position */\r
+#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSEG2 Mask */\r
+\r
+#define CAN_BTIME_TSEG1_Pos 8 /*!< CAN_T::BTIME: TSEG1 Position */\r
+#define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSEG1 Mask */\r
+\r
+#define CAN_BTIME_SJW_Pos 6 /*!< CAN_T::BTIME: SJW Position */\r
+#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */\r
+\r
+#define CAN_BTIME_BRP_Pos 0 /*!< CAN_T::BTIME: BRP Position */\r
+#define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */\r
+\r
+/* CAN IIDR Bit Field Definitions */\r
+#define CAN_IIDR_INTID_Pos 0 /*!< CAN_T::IIDR: INTID Position */\r
+#define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: INTID Mask */\r
+\r
+/* CAN TEST Bit Field Definitions */\r
+#define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */\r
+#define CAN_TEST_RX_Msk (0x1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */\r
+\r
+#define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */\r
+#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */\r
+\r
+#define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */\r
+#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */\r
+\r
+#define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */\r
+#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */\r
+\r
+#define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */\r
+#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */\r
+\r
+/* CAN BPRE Bit Field Definitions */\r
+#define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */\r
+#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */\r
+\r
+/* CAN IFn_CREQ Bit Field Definitions */\r
+#define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_IF_T::CREQ: BUSY Position */\r
+#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: BUSY Mask */\r
+\r
+#define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_IF_T::CREQ: MSGNUM Position */\r
+#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MSGNUM Mask */\r
+\r
+/* CAN IFn_CMASK Bit Field Definitions */\r
+#define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_IF_T::CMASK: WRRD Position */\r
+#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WRRD Mask */\r
+\r
+#define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_IF_T::CMASK: MASK Position */\r
+#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: MASK Mask */\r
+\r
+#define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_IF_T::CMASK: ARB Position */\r
+#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: ARB Mask */\r
+\r
+#define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_IF_T::CMASK: CONTROL Position */\r
+#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: CONTROL Mask */\r
+\r
+#define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_IF_T::CMASK: CLRINTPND Position */\r
+#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: CLRINTPND Mask */\r
+\r
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */\r
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask */\r
+\r
+#define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_IF_T::CMASK: DATAA Position */\r
+#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DATAA Mask */\r
+\r
+#define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_IF_T::CMASK: DATAB Position */\r
+#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DATAB Mask */\r
+\r
+/* CAN IFn_MASK1 Bit Field Definitions */\r
+#define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_IF_T::MASK1: MSK Position */\r
+#define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_IF_T::MASK1: MSK Mask */\r
+\r
+/* CAN IFn_MASK2 Bit Field Definitions */\r
+#define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN_IF_T::MASK2: MXTD Position */\r
+#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXTD Mask */\r
+\r
+#define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN_IF_T::MASK2: MDIR Position */\r
+#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDIR Mask */\r
+\r
+#define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN_IF_T::MASK2: MSK Position */\r
+#define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN_IF_T::MASK2: MSK Mask */\r
+\r
+/* CAN IFn_ARB1 Bit Field Definitions */\r
+#define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_IF_T::ARB1: ID Position */\r
+#define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */\r
+\r
+/* CAN IFn_ARB2 Bit Field Definitions */\r
+#define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN_IF_T::ARB2: MSGVAL Position */\r
+#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MSGVAL Mask */\r
+\r
+#define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN_IF_T::ARB2: XTD Position */\r
+#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: XTD Mask */\r
+\r
+#define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN_IF_T::ARB2: DIR Position */\r
+#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: DIR Mask */\r
+\r
+#define CAN_IF_ARB2_ID_Pos 0 /*!< CAN_IF_T::ARB2: ID Position */\r
+#define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */\r
+\r
+/* CAN IFn_MCON Bit Field Definitions */\r
+#define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN_IF_T::MCON: NEWDAT Position */\r
+#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NEWDAT Mask */\r
+\r
+#define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN_IF_T::MCON: MSGLST Position */\r
+#define CAN_IF_MCON_MSGLST_Msk (0x1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN_IF_T::MCON: MSGLST Mask */\r
+\r
+#define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN_IF_T::MCON: INTPND Position */\r
+#define CAN_IF_MCON_INTPND_Msk (0x1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN_IF_T::MCON: INTPND Mask */\r
+\r
+#define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN_IF_T::MCON: UMASK Position */\r
+#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMASK Mask */\r
+\r
+#define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN_IF_T::MCON: TXIE Position */\r
+#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TXIE Mask */\r
+\r
+#define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN_IF_T::MCON: RXIE Position */\r
+#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RXIE Mask */\r
+\r
+#define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN_IF_T::MCON: RMTEN Position */\r
+#define CAN_IF_MCON_RMTEN_Msk (0x1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN_IF_T::MCON: RMTEN Mask */\r
+\r
+#define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN_IF_T::MCON: TXRQST Position */\r
+#define CAN_IF_MCON_TXRQST_Msk (0x1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN_IF_T::MCON: TXRQST Mask */\r
+\r
+#define CAN_IF_MCON_EOB_Pos 7 /*!< CAN_IF_T::MCON: EOB Position */\r
+#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EOB Mask */\r
+\r
+#define CAN_IF_MCON_DLC_Pos 0 /*!< CAN_IF_T::MCON: DLC Position */\r
+#define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */\r
+\r
+/* CAN IFn_DATA_A1 Bit Field Definitions */\r
+#define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN_IF_T::DATAA1: DATA1 Position */\r
+#define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DATAA1: DATA1 Mask */\r
+\r
+#define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN_IF_T::DATAA1: DATA0 Position */\r
+#define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DATAA1: DATA0 Mask */\r
+\r
+/* CAN IFn_DATA_A2 Bit Field Definitions */\r
+#define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN_IF_T::DATAA1: DATA3 Position */\r
+#define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DATAA1: DATA3 Mask */\r
+\r
+#define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN_IF_T::DATAA1: DATA2 Position */\r
+#define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DATAA1: DATA2 Mask */\r
+\r
+/* CAN IFn_DATA_B1 Bit Field Definitions */\r
+#define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN_IF_T::DATAB1: DATA5 Position */\r
+#define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DATAB1: DATA5 Mask */\r
+\r
+#define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN_IF_T::DATAB1: DATA4 Position */\r
+#define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DATAB1: DATA4 Mask */\r
+\r
+/* CAN IFn_DATA_B2 Bit Field Definitions */\r
+#define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN_IF_T::DATAB2: DATA7 Position */\r
+#define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DATAB2: DATA7 Mask */\r
+\r
+#define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN_IF_T::DATAB2: DATA6 Position */\r
+#define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DATAB2: DATA6 Mask */\r
+\r
+/* CAN IFn_TXRQST1 Bit Field Definitions */\r
+#define CAN_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::TXRQST1: TXRQST Position */\r
+#define CAN_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_TXRQST1_TXRQST_Pos) /*!< CAN_T::TXRQST1: TXRQST Mask */\r
+\r
+/* CAN IFn_TXRQST2 Bit Field Definitions */\r
+#define CAN_TXRQST2_TXRQST_Pos 0 /*!< CAN_T::TXRQST2: TXRQST Position */\r
+#define CAN_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_TXRQST2_TXRQST_Pos) /*!< CAN_T::TXRQST2: TXRQST Mask */\r
+\r
+/* CAN IFn_NDAT1 Bit Field Definitions */\r
+#define CAN_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::NDAT1: NEWDATA Position */\r
+#define CAN_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_NDAT1_NEWDATA_Pos) /*!< CAN_T::NDAT1: NEWDATA Mask */\r
+\r
+/* CAN IFn_NDAT2 Bit Field Definitions */\r
+#define CAN_NDAT2_NEWDATA_Pos 0 /*!< CAN_T::NDAT2: NEWDATA Position */\r
+#define CAN_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_NDAT2_NEWDATA_Pos) /*!< CAN_T::NDAT2: NEWDATA Mask */\r
+\r
+/* CAN IFn_IPND1 Bit Field Definitions */\r
+#define CAN_IPND1_INTPND_Pos 0 /*!< CAN_T::IPND1: INTPND Position */\r
+#define CAN_IPND1_INTPND_Msk (0xFFFFul << CAN_IPND1_INTPND_Pos) /*!< CAN_T::IPND1: INTPND Mask */\r
+\r
+/* CAN IFn_IPND2 Bit Field Definitions */\r
+#define CAN_IPND2_INTPND_Pos 0 /*!< CAN_T::IPND2: INTPND Position */\r
+#define CAN_IPND2_INTPND_Msk (0xFFFFul << CAN_IPND2_INTPND_Pos) /*!< CAN_T::IPND2: INTPND Mask */\r
+\r
+/* CAN IFn_MVLD1 Bit Field Definitions */\r
+#define CAN_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::MVLD1: MSGVAL Position */\r
+#define CAN_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_MVLD1_MSGVAL_Pos) /*!< CAN_T::MVLD1: MSGVAL Mask */\r
+\r
+/* CAN IFn_MVLD2 Bit Field Definitions */\r
+#define CAN_MVLD2_MSGVAL_Pos 0 /*!< CAN_T::MVLD2: MSGVAL Position */\r
+#define CAN_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_MVLD2_MSGVAL_Pos) /*!< CAN_T::MVLD2: MSGVAL Mask */\r
+\r
+/* CAN WUEN Bit Field Definitions */\r
+#define CAN_WU_EN_WAKUP_EN_Pos 0 /*!< CAN_T::WU_EN: WAKUP_EN Position */\r
+#define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */\r
+\r
+/* CAN WUSTATUS Bit Field Definitions */\r
+#define CAN_WU_STATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WU_STATUS: WAKUP_STS Position */\r
+#define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */\r
+\r
+\r
+/**@}*/ /* CAN_CONST */\r
+/**@}*/ /* end of CAN register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __CAN_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file clk_reg.h\r
+ * @version V1.00\r
+ * @brief CLK register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __CLK_REG_H__\r
+#define __CLK_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- System Clock Controller -------------------------*/\r
+/**\r
+ @addtogroup CLK System Clock Controller(CLK)\r
+ Memory Mapped Structure for CLK Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+ /**\r
+ * @var CLK_T::PWRCTL\r
+ * Offset: 0x00 System Power-down Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |HXTEN |HXT Enable Bit (Write Protect)\r
+ * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled.\r
+ * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled.\r
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * | | |Note2: HXT cannot be disabled and HXTEN will always read as 1 if HCLK clock source is selected from HXT or PLL (clock source from HXT).\r
+ * |[1] |LXTEN |LXT Enable Bit (Write Protect)\r
+ * | | |0 = 32.768 kHz external low speed crystal (extLXT) Disabled.\r
+ * | | |1 = 32.768 kHz external low speed crystal (extLXT) Enabled.\r
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * | | |Note2: LXT cannot be disabled and LXTEN will always read as 1 if HCLK clock source is selected from LXT when the LXT clock source is selected as extLXT by setting C32KS(RTC_LXTCTL[7]) to 1.\r
+ * |[2] |HIRCEN |HIRC Enable Bit (Write Protect)\r
+ * | | |The HCLK default clock source is from HIRC and this bit default value is 1.\r
+ * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled.\r
+ * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled.\r
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * | | |Note2: HIRC cannot be disabled and HIRCEN will always read as 1 if Flash access cycle auto-tuning function is enabled or HCLK clock source is selected from HIRC or PLL (clock source from HIRC).\r
+ * | | |Flash access cycle auto-tuning function can be disabled by setting FADIS (FMC_CYCCTL[8]).\r
+ * |[3] |LIRCEN |LIRC Enable Bit (Write Protect)\r
+ * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled.\r
+ * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled.\r
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * | | |Note2: LIRC cannot be disabled and LIRCEN will always read as 1 if HCLK clock source is selected from LIRC.\r
+ * | | |Note3: If CWDTEN(CONFIG[31,4:3]) is set to 111, LIRC clock can be enabled or disabled by setting LIRCEN(CLK_PWRCTL[3]).\r
+ * | | |If CWDTEN(CONFIG0[31,4:3]) is not set to 111, LIRC cannot be disabled in normal mode and LIRCEN will always read as 1\r
+ * | | |In Power-down mode, LIRC clock is controlled by LIRCEN(CLK_PWRCTL[3]) and CWDTPDEN (CONFIG0[30]) setting.\r
+ * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\r
+ * | | |0 = Power-down mode wake-up interrupt Disabled.\r
+ * | | |1 = Power-down mode wake-up interrupt Enabled.\r
+ * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high, after resume from Power-down mode.\r
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status\r
+ * | | |Set by Power-down wake-up event, it indicates that resume from Power-down mode.\r
+ * | | |The flag is set if the EINT7~0, GPIO, UART0~5, USBH, USBD, OTG, CAN0, BOD, ACMP, WDT, SDH0, TMR0~3, I2C0~2, USCI0~1, RTC wake-up occurred.\r
+ * | | |Note1: Write 1 to clear the bit to 0.\r
+ * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.\r
+ * |[7] |PDEN |System Power-down Enable (Write Protect)\r
+ * | | |When this bit is set to 1, Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\r
+ * | | |When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.\r
+ * | | |In Power-down mode, HXT, HIRC, HIRC48, PLL and system clock will be disabled and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.\r
+ * | | |0 = Chip operating normally or chip in idle mode because of WFI command.\r
+ * | | |1 = Chip waits CPU sleep command WFI and then enters Power-down mode.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect)\r
+ * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally.\r
+ * | | |If gain control is enabled, crystal will consume more power than gain control off.\r
+ * | | |00 = HXT frequency is lower than from 8 MHz.\r
+ * | | |01 = HXT frequency is from 8 MHz to 12 MHz.\r
+ * | | |10 = HXT frequency is from 12 MHz to 16 MHz.\r
+ * | | |11 = HXT frequency is higher than 16 MHz.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect)\r
+ * | | |0 = Select INV type.\r
+ * | | |1 = Select GM type.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect)\r
+ * | | |0 = HXT Crystal TURBO mode disabled.\r
+ * | | |1 = HXT Crystal TURBO mode enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[18] |HIRC48EN |HIRC48 Enable Bit (Write Protect)\r
+ * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48) Disabled.\r
+ * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48) Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * @var CLK_T::AHBCLK\r
+ * Offset: 0x04 AHB Devices Clock Enable Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PDMA0CKEN |PDMA0 Controller Clock Enable Bit (Secure)\r
+ * | | |0 = PDMA0 peripheral clock Disabled.\r
+ * | | |1 = PDMA0 peripheral clock Enabled.\r
+ * |[1] |PDMA1CKEN |PDMA1 Controller Clock Enable Bit\r
+ * | | |0 = PDMA1 peripheral clock Disabled.\r
+ * | | |1 = PDMA1 peripheral clock Enabled.\r
+ * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit\r
+ * | | |0 = Flash ISP peripheral clock Disabled.\r
+ * | | |1 = Flash ISP peripheral clock Enabled.\r
+ * |[3] |EBICKEN |EBI Controller Clock Enable Bit\r
+ * | | |0 = EBI peripheral clock Disabled.\r
+ * | | |1 = EBI peripheral clock Enabled.\r
+ * |[6] |SDH0CKEN |SDHOST0 Controller Clock Enable Bit\r
+ * | | |0 = SDHOST0 peripheral clock Disabled.\r
+ * | | |1 = SDHOST0 peripheral clock Enabled.\r
+ * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit\r
+ * | | |0 = CRC peripheral clock Disabled.\r
+ * | | |1 = CRC peripheral clock Enabled.\r
+ * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit\r
+ * | | |0 = Cryptographic Accelerator clock Disabled.\r
+ * | | |1 = Cryptographic Accelerator clock Enabled.\r
+ * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode\r
+ * | | |0 = FMC clock Disabled when chip is under IDLE mode.\r
+ * | | |1 = FMC clock Enabled when chip is under IDLE mode.\r
+ * |[16] |USBHCKEN |USB HOST 1.1 Controller Clock Enable Bit\r
+ * | | |0 = USB HOST 1.1 peripheral clock Disabled.\r
+ * | | |1 = USB HOST 1.1 peripheral clock Enabled.\r
+ * @var CLK_T::APBCLK0\r
+ * Offset: 0x08 APB Devices Clock Enable Control Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect)\r
+ * | | |0 = Watchdog timer clock Disabled.\r
+ * | | |1 = Watchdog timer clock Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit\r
+ * | | |This bit is used to control the RTC APB clock only.\r
+ * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8])\r
+ * | | |It can be selected to 32.768 kHz external low speed crystal (LXT) or 10 kHz internal low speed RC oscillator (LIRC).\r
+ * | | |0 = RTC clock Disabled.\r
+ * | | |1 = RTC clock Enabled.\r
+ * |[2] |TMR0CKEN |Timer0 Clock Enable Bit\r
+ * | | |0 = Timer0 clock Disabled.\r
+ * | | |1 = Timer0 clock Enabled.\r
+ * |[3] |TMR1CKEN |Timer1 Clock Enable Bit\r
+ * | | |0 = Timer1 clock Disabled.\r
+ * | | |1 = Timer1 clock Enabled.\r
+ * |[4] |TMR2CKEN |Timer2 Clock Enable Bit\r
+ * | | |0 = Timer2 clock Disabled.\r
+ * | | |1 = Timer2 clock Enabled.\r
+ * |[5] |TMR3CKEN |Timer3 Clock Enable Bit\r
+ * | | |0 = Timer3 clock Disabled.\r
+ * | | |1 = Timer3 clock Enabled.\r
+ * |[6] |CLKOCKEN |CLKO Clock Enable Bit\r
+ * | | |0 = CLKO clock Disabled.\r
+ * | | |1 = CLKO clock Enabled.\r
+ * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit\r
+ * | | |0 = Analog comparator 0/1 clock Disabled.\r
+ * | | |1 = Analog comparator 0/1 clock Enabled.\r
+ * |[8] |I2C0CKEN |I2C0 Clock Enable Bit\r
+ * | | |0 = I2C0 clock Disabled.\r
+ * | | |1 = I2C0 clock Enabled.\r
+ * |[9] |I2C1CKEN |I2C1 Clock Enable Bit\r
+ * | | |0 = I2C1 clock Disabled.\r
+ * | | |1 = I2C1 clock Enabled.\r
+ * |[10] |I2C2CKEN |I2C2 Clock Enable Bit\r
+ * | | |0 = I2C2 clock Disabled.\r
+ * | | |1 = I2C2 clock Enabled.\r
+ * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit\r
+ * | | |0 = QSPI0 clock Disabled.\r
+ * | | |1 = QSPI0 clock Enabled.\r
+ * |[13] |SPI0CKEN |SPI0 Clock Enable Bit\r
+ * | | |0 = SPI0 clock Disabled.\r
+ * | | |1 = SPI0 clock Enabled.\r
+ * |[14] |SPI1CKEN |SPI1 Clock Enable Bit\r
+ * | | |0 = SPI1 clock Disabled.\r
+ * | | |1 = SPI1 clock Enabled.\r
+ * |[15] |SPI2CKEN |SPI2 Clock Enable Bit\r
+ * | | |0 = SPI2 clock Disabled.\r
+ * | | |1 = SPI2 clock Enabled.\r
+ * |[16] |UART0CKEN |UART0 Clock Enable Bit\r
+ * | | |0 = UART0 clock Disabled.\r
+ * | | |1 = UART0 clock Enabled.\r
+ * |[17] |UART1CKEN |UART1 Clock Enable Bit\r
+ * | | |0 = UART1 clock Disabled.\r
+ * | | |1 = UART1 clock Enabled.\r
+ * |[18] |UART2CKEN |UART2 Clock Enable Bit\r
+ * | | |0 = UART2 clock Disabled.\r
+ * | | |1 = UART2 clock Enabled.\r
+ * |[19] |UART3CKEN |UART3 Clock Enable Bit\r
+ * | | |0 = UART3 clock Disabled.\r
+ * | | |1 = UART3 clock Enabled.\r
+ * |[20] |UART4CKEN |UART4 Clock Enable Bit\r
+ * | | |0 = UART4 clock Disabled.\r
+ * | | |1 = UART4 clock Enabled.\r
+ * |[21] |UART5CKEN |UART5 Clock Enable Bit\r
+ * | | |0 = UART5 clock Disabled.\r
+ * | | |1 = UART5 clock Enabled.\r
+ * |[24] |CAN0CKEN |CAN0 Clock Enable Bit\r
+ * | | |0 = CAN0 clock Disabled.\r
+ * | | |1 = CAN0 clock Enabled.\r
+ * |[26] |OTGCKEN |USB OTG Clock Enable Bit\r
+ * | | |0 = USB OTG clock Disabled.\r
+ * | | |1 = USB OTG clock Enabled.\r
+ * |[27] |USBDCKEN |USB Device Clock Enable Bit\r
+ * | | |0 = USB Device clock Disabled.\r
+ * | | |1 = USB Device clock Enabled.\r
+ * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit\r
+ * | | |0 = EADC clock Disabled.\r
+ * | | |1 = EADC clock Enabled.\r
+ * |[29] |I2S0CKEN |I2S0 Clock Enable Bit\r
+ * | | |0 = I2S0 Clock Disabled.\r
+ * | | |1 = I2S0 Clock Enabled.\r
+ * @var CLK_T::APBCLK1\r
+ * Offset: 0x0C APB Devices Clock Enable Control Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SC0CKEN |Smart Card 0 (SC0) Clock Enable Bit\r
+ * | | |0 = SC0 clock Disabled.\r
+ * | | |1 = SC0 clock Enabled.\r
+ * |[1] |SC1CKEN |Smart Card 1 (SC1) Clock Enable Bit\r
+ * | | |0 = SC1 clock Disabled.\r
+ * | | |1 = SC1 clock Enabled.\r
+ * |[2] |SC2CKEN |Smart Card 2 (SC2) Clock Enable Bit\r
+ * | | |0 = SC2 clock Disabled.\r
+ * | | |1 = SC2 clock Enabled.\r
+ * |[6] |SPI3CKEN |SPI3 Clock Enable Bit\r
+ * | | |0 = SPI3 clock Disabled.\r
+ * | | |1 = SPI3 clock Enabled.\r
+ * |[8] |USCI0CKEN |USCI0 Clock Enable Bit\r
+ * | | |0 = USCI0 clock Disabled.\r
+ * | | |1 = USCI0 clock Enabled.\r
+ * |[9] |USCI1CKEN |USCI1 Clock Enable Bit\r
+ * | | |0 = USCI1 clock Disabled.\r
+ * | | |1 = USCI1 clock Enabled.\r
+ * |[12] |DACCKEN |DAC Clock Enable Bit\r
+ * | | |0 = DAC clock Disabled.\r
+ * | | |1 = DAC clock Enabled.\r
+ * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit\r
+ * | | |0 = EPWM0 clock Disabled.\r
+ * | | |1 = EPWM0 clock Enabled.\r
+ * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit\r
+ * | | |0 = EPWM1 clock Disabled.\r
+ * | | |1 = EPWM1 clock Enabled.\r
+ * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit\r
+ * | | |0 = BPWM0 clock Disabled.\r
+ * | | |1 = BPWM0 clock Enabled.\r
+ * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit\r
+ * | | |0 = BPWM1 clock Disabled.\r
+ * | | |1 = BPWM1 clock Enabled.\r
+ * |[22] |QEI0CKEN |QEI0 Clock Enable Bit\r
+ * | | |0 = QEI0 clock Disabled.\r
+ * | | |1 = QEI0 clock Enabled.\r
+ * |[23] |QEI1CKEN |QEI1 Clock Enable Bit\r
+ * | | |0 = QEI1 clock Disabled.\r
+ * | | |1 = QEI1 clock Enabled.\r
+ * |[25] |TRNGCKEN |TRNG Clock Enable Bit\r
+ * | | |0 = TRNG clock Disabled.\r
+ * | | |1 = TRNG clock Enabled.\r
+ * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit\r
+ * | | |0 = ECAP0 clock Disabled.\r
+ * | | |1 = ECAP0 clock Enabled.\r
+ * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit\r
+ * | | |0 = ECAP1 clock Disabled.\r
+ * | | |1 = ECAP1 clock Enabled.\r
+ * @var CLK_T::CLKSEL0\r
+ * Offset: 0x10 Clock Source Select Control Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect)\r
+ * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.\r
+ * | | |000 = Clock source from HXT.\r
+ * | | |001 = Clock source from LXT.\r
+ * | | |010 = Clock source from PLL.\r
+ * | | |011 = Clock source from LIRC.\r
+ * | | |100 = Reserved.\r
+ * | | |101 = Clock source from HIRC48.\r
+ * | | |111 = Clock source from HIRC.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[5:3] |STCLKSEL |SysTick Clock Source Selection (Write Protect)\r
+ * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below.\r
+ * | | |000 = Clock source from HXT.\r
+ * | | |001 = Clock source from LXT.\r
+ * | | |010 = Clock source from HXT/2.\r
+ * | | |011 = Clock source from HCLK/2.\r
+ * | | |111 = Clock source from HIRC/2.\r
+ * | | |Others = Reserved.\r
+ * | | |Note1: if SysTick clock source is not from HCLK (i.e SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[8] |USBSEL |USB Clock Source Selection (Write Protect)\r
+ * | | |0 = Clock source from HIRC48.\r
+ * | | |1 = Clock source from PLL.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[21:20] |SDH0SEL |SDHOST0 Peripheral Clock Source Selection (Write Protect)\r
+ * | | |00 = Clock source from HXT clock.\r
+ * | | |01 = Clock source from PLL clock.\r
+ * | | |10 = Clock source from HCLK.\r
+ * | | |11 = Clock source from HIRC clock.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * @var CLK_T::CLKSEL1\r
+ * Offset: 0x14 Clock Source Select Control Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect)\r
+ * | | |Others = Reserved.\r
+ * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |10 = Clock source from HCLK/2048.\r
+ * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection\r
+ * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |010 = Clock source from PCLK0.\r
+ * | | |011 = Clock source from external clock TM0 pin.\r
+ * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).\r
+ * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * | | |Others = Reserved.\r
+ * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection\r
+ * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |010 = Clock source from PCLK0.\r
+ * | | |011 = Clock source from external clock TM1 pin.\r
+ * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).\r
+ * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * | | |Others = Reserved.\r
+ * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection\r
+ * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |010 = Clock source from PCLK1.\r
+ * | | |011 = Clock source from external clock TM2 pin.\r
+ * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).\r
+ * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * | | |Others = Reserved.\r
+ * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection\r
+ * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |010 = Clock source from PCLK1.\r
+ * | | |011 = Clock source from external clock TM3 pin.\r
+ * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).\r
+ * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * | | |Others = Reserved.\r
+ * |[25:24] |UART0SEL |UART0 Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[27:26] |UART1SEL |UART1 Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[29:28] |CLKOSEL |Clock Output Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |10 = Clock source from HCLK.\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection (Write Protect)\r
+ * | | |10 = Clock source from HCLK/2048.\r
+ * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).\r
+ * | | |Others = Reserved.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * @var CLK_T::CLKSEL2\r
+ * Offset: 0x18 Clock Source Select Control Register 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |EPWM0SEL |EPWM0 Clock Source Selection (Read Only)\r
+ * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL.\r
+ * | | |1 = Clock source from PCLK0.\r
+ * |[1] |EPWM1SEL |EPWM1 Clock Source Selection (Read Only)\r
+ * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL.\r
+ * | | |1 = Clock source from PCLK1.\r
+ * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from PCLK0.\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[5:4] |SPI0SEL |SPI0 Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from PCLK1.\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[7:6] |SPI1SEL |SPI1 Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from PCLK0.\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[8] |BPWM0SEL |BPWM0 Clock Source Selection (Read Only)\r
+ * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL.\r
+ * | | |1 = Clock source from PCLK0.\r
+ * |[9] |BPWM1SEL |BPWM1 Clock Source Selection (Read Only)\r
+ * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL.\r
+ * | | |1 = Clock source from PCLK1.\r
+ * |[11:10] |SPI2SEL |SPI2 Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from PCLK1.\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[13:12] |SPI3SEL |SPI3 Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from PCLK0.\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * @var CLK_T::CLKSEL3\r
+ * Offset: 0x1C Clock Source Select Control Register 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |SC0SEL |Smart Card 0 (SC0) Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from PCLK0.\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[3:2] |SC1SEL |Smart Card 1 (SC1) Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from PCLK1.\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[5:4] |SC2SEL |Smart Card 2 (SC2) Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from PCLK0.\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[8] |RTCSEL |RTC Clock Source Selection\r
+ * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).\r
+ * |[17:16] |I2S0SEL |I2S0 Clock Source Selection\r
+ * | | |00 = Clock source from HXT clock.\r
+ * | | |01 = Clock source from PLL clock.\r
+ * | | |10 = Clock source from PCLK0.\r
+ * | | |11 = Clock source from HIRC clock.\r
+ * |[25:24] |UART2SEL |UART2 Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[27:26] |UART3SEL |UART3 Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[29:28] |UART4SEL |UART4 Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * |[31:30] |UART5SEL |UART5 Clock Source Selection\r
+ * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).\r
+ * | | |01 = Clock source from PLL.\r
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).\r
+ * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).\r
+ * @var CLK_T::CLKDIV0\r
+ * Offset: 0x20 Clock Divider Number Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |HCLKDIV |HCLK Clock Divide Number from HCLK Clock Source\r
+ * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).\r
+ * |[7:4] |USBDIV |USB Clock Divide Number from PLL Clock\r
+ * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1).\r
+ * |[11:8] |UART0DIV |UART0 Clock Divide Number from UART0 Clock Source\r
+ * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1).\r
+ * |[15:12] |UART1DIV |UART1 Clock Divide Number from UART1 Clock Source\r
+ * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1).\r
+ * |[23:16] |EADCDIV |EADC Clock Divide Number from EADC Clock Source\r
+ * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).\r
+ * |[31:24] |SDH0DIV |SDHOST0 Clock Divide Number from SDHOST0 Clock Source\r
+ * | | |SDHOST0 clock frequency = (SDHOST0 clock source frequency) / (SDH0DIV + 1).\r
+ * @var CLK_T::CLKDIV1\r
+ * Offset: 0x24 Clock Divider Number Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |SC0DIV |Smart Card 0 (SC0) Clock Divide Number from SC0 Clock Source\r
+ * | | |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1).\r
+ * |[15:8] |SC1DIV |Smart Card 1 (SC1) Clock Divide Number from SC1 Clock Source\r
+ * | | |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1).\r
+ * |[23:16] |SC2DIV |Smart Card 2 (SC2) Clock Divide Number from SC2 Clock Source\r
+ * | | |SC2 clock frequency = (SC2 clock source frequency) / (SC2DIV + 1).\r
+ * @var CLK_T::CLKDIV4\r
+ * Offset: 0x30 Clock Divider Number Register 4\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |UART2DIV |UART2 Clock Divide Number from UART2 Clock Source\r
+ * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1).\r
+ * |[7:4] |UART3DIV |UART3 Clock Divide Number from UART3 Clock Source\r
+ * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1).\r
+ * |[11:8] |UART4DIV |UART4 Clock Divide Number from UART4 Clock Source\r
+ * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1).\r
+ * |[15:12] |UART5DIV |UART5 Clock Divide Number from UART5 Clock Source\r
+ * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1).\r
+ * @var CLK_T::PCLKDIV\r
+ * Offset: 0x34 APB Clock Divider Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |APB0DIV |APB0 Clock Divider\r
+ * | | |APB0 clock can be divided from HCLK.\r
+ * | | |000 = PCLK0 frequency is HCLK.\r
+ * | | |001 = PCLK0 frequency is 1/2 HCLK.\r
+ * | | |010 = PCLK0 frequency is 1/4 HCLK.\r
+ * | | |011 = PCLK0 frequency is 1/8 HCLK.\r
+ * | | |100 = PCLK0 frequency is 1/16 HCLK.\r
+ * | | |101 = PCLK0 frequency is 1/32 HCLK.\r
+ * | | |Others = Reserved.\r
+ * |[6:4] |APB1DIV |APB1 Clock Divider\r
+ * | | |APB1 clock can be divided from HCLK.\r
+ * | | |000 = PCLK1 frequency is HCLK.\r
+ * | | |001 = PCLK1 frequency is 1/2 HCLK.\r
+ * | | |010 = PCLK1 frequency is 1/4 HCLK.\r
+ * | | |011 = PCLK1 frequency is 1/8 HCLK.\r
+ * | | |100 = PCLK1 frequency is 1/16 HCLK.\r
+ * | | |101 = PCLK1 frequency is 1/32 HCLK.\r
+ * | | |Others = Reserved.\r
+ * @var CLK_T::PLLCTL\r
+ * Offset: 0x40 PLL Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect)\r
+ * | | |Refer to the PLL formulas.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[13:9] |INDIV |PLL Input Divider Control (Write Protect)\r
+ * | | |Refer to the PLL formulas.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect)\r
+ * | | |Refer to the PLL formulas.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[16] |PD |Power-down Mode (Write Protect)\r
+ * | | |0 = PLL is enable (in normal mode).\r
+ * | | |1 = PLL is disable (in Power-down mode) (default).\r
+ * | | |Note1: If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\r
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[17] |BP |PLL Bypass Control (Write Protect)\r
+ * | | |0 = PLL is in normal mode (default).\r
+ * | | |1 = PLL clock output is same as PLL input clock FIN.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[18] |OE |PLL OE (FOUT Enable) Control (Write Protect)\r
+ * | | |0 = PLL FOUT Enabled.\r
+ * | | |1 = PLL FOUT is fixed low.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect)\r
+ * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT).\r
+ * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC).\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect)\r
+ * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz).\r
+ * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz).\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * @var CLK_T::STATUS\r
+ * Offset: 0x50 Clock Status Monitor Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only)\r
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled.\r
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled.\r
+ * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only)\r
+ * | | |LXT clock source can be selected as extLXT or LIRC32 by setting C32KS(RTC_LXTCTL[7]). \r
+ * | | |If C32KS is set to 0 the LXT stable flag is set when extLXT clock source is stable. \r
+ * | | |If C32KS is set to 1 the LXT stable flag is set when LIRC32 clock source is stable.\r
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled.\r
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled.\r
+ * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only)\r
+ * | | |0 = Internal PLL clock is not stable or disabled.\r
+ * | | |1 = Internal PLL clock is stable and enabled.\r
+ * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only)\r
+ * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled.\r
+ * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled.\r
+ * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only)\r
+ * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled.\r
+ * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled.\r
+ * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only)\r
+ * | | |This bit is updated when software switches system clock source.\r
+ * | | |If switch target clock is stable, this bit will be set to 0.\r
+ * | | |If switch target clock is not stable, this bit will be set to 1.\r
+ * | | |0 = Clock switching success.\r
+ * | | |1 = Clock switching failure.\r
+ * | | |Note: This bit is read only.\r
+ * | | |After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware.\r
+ * |[8] |EXTLXTSTB |EXTLXT Clock Source Stable Flag (Read Only)\r
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is not stable or disabled.\r
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is stable and enabled.\r
+ * |[9] |LIRC32STB |LIRC32 Clock Source Stable Flag (Read Only)\r
+ * | | |0 = 32 kHz internal low speed RC oscillator (LIRC32) clock is not stable or disabled.\r
+ * | | |1 = 32 kHz internal low speed RC oscillator (LIRC32) clock is stable and enabled.\r
+ * @var CLK_T::CLKOCTL\r
+ * Offset: 0x60 Clock Output Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |FREQSEL |Clock Output Frequency Selection\r
+ * | | |The formula of output frequency is Fout = Fin/2^(N+1).\r
+ * | | |Fin is the input clock frequency.\r
+ * | | |Fout is the frequency of divider output clock.\r
+ * | | |N is the 4-bit value of FREQSEL[3:0].\r
+ * |[4] |CLKOEN |Clock Output Enable Bit\r
+ * | | |0 = Clock Output function Disabled.\r
+ * | | |1 = Clock Output function Enabled.\r
+ * |[5] |DIV1EN |Clock Output Divide One Enable Bit\r
+ * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL.\r
+ * | | |1 = Clock Output will output clock with source frequency.\r
+ * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit\r
+ * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled.\r
+ * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled.\r
+ * @var CLK_T::CLKDCTL\r
+ * Offset: 0x70 Clock Fail Detector Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit\r
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled.\r
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled.\r
+ * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit\r
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled.\r
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled.\r
+ * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit\r
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled.\r
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled.\r
+ * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit\r
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled.\r
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled.\r
+ * |[16] |HXTFQDEN |HXT Clock Frequency Monitor Enable Bit\r
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled.\r
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled.\r
+ * |[17] |HXTFQIEN |HXT Clock Frequency Monitor Interrupt Enable Bit\r
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled.\r
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled.\r
+ * @var CLK_T::CLKDSTS\r
+ * Offset: 0x74 Clock Fail Detector Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect)\r
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal.\r
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops.\r
+ * | | |Note1: Write 1 to clear the bit to 0.\r
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect)\r
+ * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal.\r
+ * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops.\r
+ * | | |Note1: Write 1 to clear the bit to 0.\r
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[8] |HXTFQIF |HXT Clock Frequency Monitor Interrupt Flag (Write Protect)\r
+ * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal.\r
+ * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal.\r
+ * | | |Note1: Write 1 to clear the bit to 0.\r
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * @var CLK_T::CDUPB\r
+ * Offset: 0x78 Clock Frequency Detector Upper Boundary Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[9:0] |UPERBD |HXT Clock Frequency Detector Upper Boundary\r
+ * | | |The bits define the high value of frequency monitor window.\r
+ * | | |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.\r
+ * @var CLK_T::CDLOWB\r
+ * Offset: 0x7C Clock Frequency Detector Lower Boundary Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[9:0] |LOWERBD |HXT Clock Frequency Detector Lower Boundary\r
+ * | | |The bits define the low value of frequency monitor window.\r
+ * | | |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.\r
+ * @var CLK_T::PMUCTL\r
+ * Offset: 0x90 Power Manager Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect)\r
+ * | | |These bits control chip Power-down mode grade selection when CPU execute WFI/WFE instruction.\r
+ * | | |000 = Power-down mode is selected (PD).\r
+ * | | |001 = Low leakage Power-down mode is selected (LLPD).\r
+ * | | |010 = Fast wake-up Power-down (FWPD).\r
+ * | | |011 = Ultra low leakage Power-down mode is selected (ULLPD).\r
+ * | | |100 = Standby Power-down mode is selected (SPD).\r
+ * | | |101 = Reserved.\r
+ * | | |110 = Deep Power-down mode is selected (DPD).\r
+ * | | |111 = Reserved.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[8] |WKTMREN |Wake-up Timer Enable Bit (Write Protect)\r
+ * | | |0 = Wake-up timer Disable in Deep Power-down mode or Standby Power-down mode.\r
+ * | | |1 = Wake-up timer Enabled in Deep Power-down mode or Standby Power-down mode.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect)\r
+ * | | |These bits control wake-up timer time-out interval when chip under Deep Power-down mode or Standby Power-down mode.\r
+ * | | |000 = Time-out interval is 128 LIRC clocks (12.8ms).\r
+ * | | |001 = Time-out interval is 256 LIRC clocks (25.6ms).\r
+ * | | |010 = Time-out interval is 512 LIRC clocks (51.2ms).\r
+ * | | |011 = Time-out interval is 1024 LIRC clocks (102.4ms).\r
+ * | | |100 = Time-out interval is 4096 LIRC clocks (409.6ms).\r
+ * | | |101 = Time-out interval is 8192 LIRC clocks (819.2ms).\r
+ * | | |110 = Time-out interval is 16384 LIRC clocks (1638.4ms).\r
+ * | | |111 = Time-out interval is 65536 LIRC clocks (6553.6ms).\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect)\r
+ * | | |00 = Wake-up pin Disable in Deep Power-down mode.\r
+ * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode.\r
+ * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode.\r
+ * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect)\r
+ * | | |0 = ACMP wake-up Disable in Standby Power-down mode.\r
+ * | | |1 = ACMP wake-up Enabled in Standby Power-down mode.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect)\r
+ * | | |This is a protected register. Please refer to open lock sequence to program it.\r
+ * | | |0 = RTC wake-up Disable in Deep Power-down mode or Standby Power-down mode.\r
+ * | | |1 = RTC wake-up Enabled in Deep Power-down mode or Standby Power-down mode.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * @var CLK_T::PMUSTS\r
+ * @var CLK_T::PMUSTS\r
+ * Offset: 0x94 Power Manager Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PINWK |Pin Wake-up Flag (Read Only)\r
+ * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPC.0).\r
+ * | | |This flag is cleared when DPD mode is entered.\r
+ * |[1] |TMRWK |Timer Wake-up Flag (Read Only)\r
+ * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out.\r
+ * | | |This flag is cleared when DPD or SPD mode is entered.\r
+ * |[2] |RTCWK |RTC Wake-up Flag (Read Only)\r
+ * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened.\r
+ * | | |This flag is cleared when DPD or SPD mode is entered.\r
+ * |[8] |GPAWK |GPA Wake-up Flag (Read Only)\r
+ * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPA group pins.\r
+ * | | |This flag is cleared when SPD mode is entered.\r
+ * |[9] |GPBWK |GPB Wake-up Flag (Read Only)\r
+ * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPB group pins.\r
+ * | | |This flag is cleared when SPD mode is entered.\r
+ * |[10] |GPCWK |GPC Wake-up Flag (Read Only)\r
+ * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPC group pins.\r
+ * | | |This flag is cleared when SPD mode is entered.\r
+ * |[11] |GPDWK |GPD Wake-up Flag (Read Only)\r
+ * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPD group pins.\r
+ * | | |This flag is cleared when SPD mode is entered.\r
+ * |[12] |LVRWK |LVR Wake-up Flag (Read Only)\r
+ * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a LVR happened.\r
+ * | | |This flag is cleared when SPD mode is entered.\r
+ * |[13] |BODWK |BOD Wake-up Flag (Read Only)\r
+ * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a BOD happened.\r
+ * | | |This flag is cleared when SPD mode is entered.\r
+ * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only)\r
+ * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a ACMP transition.\r
+ * | | |This flag is cleared when SPD mode is entered.\r
+ * |[31] |CLRWK |Clear Wake-up Flag\r
+ * | | |0 = No clear.\r
+ * | | |1 = Clear all wake-up flag.\r
+ * | | |Note: This bit is auto cleared by hardware.\r
+ * @var CLK_T::SWKDBCTL\r
+ * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection\r
+ * | | |0000 = Sample wake-up input once per 1 clocks.\r
+ * | | |0001 = Sample wake-up input once per 2 clocks.\r
+ * | | |0010 = Sample wake-up input once per 4 clocks.\r
+ * | | |0011 = Sample wake-up input once per 8 clocks.\r
+ * | | |0100 = Sample wake-up input once per 16 clocks.\r
+ * | | |0101 = Sample wake-up input once per 32 clocks.\r
+ * | | |0110 = Sample wake-up input once per 64 clocks.\r
+ * | | |0111 = Sample wake-up input once per 128 clocks.\r
+ * | | |1000 = Sample wake-up input once per 256 clocks.\r
+ * | | |1001 = Sample wake-up input once per 2*256 clocks.\r
+ * | | |1010 = Sample wake-up input once per 4*256 clocks.\r
+ * | | |1011 = Sample wake-up input once per 8*256 clocks.\r
+ * | | |1100 = Sample wake-up input once per 16*256 clocks.\r
+ * | | |1101 = Sample wake-up input once per 32*256 clocks.\r
+ * | | |1110 = Sample wake-up input once per 64*256 clocks.\r
+ * | | |1111 = Sample wake-up input once per 128*256 clocks.\r
+ * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).\r
+ * @var CLK_T::PASWKCTL\r
+ * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit\r
+ * | | |0 = GPA group pin wake-up function ddisabled.\r
+ * | | |1 = GPA group pin wake-up function Enabled.\r
+ * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit\r
+ * | | |0 = GPA group pin rising edge wake-up function Disabled.\r
+ * | | |1 = GPA group pin rising edge wake-up function Enabled.\r
+ * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit\r
+ * | | |0 = GPA group pin falling edge wake-up function Disabled.\r
+ * | | |1 = GPA group pin falling edge wake-up function Enabled.\r
+ * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select\r
+ * | | |0000 = GPA.0 wake-up function enabled.\r
+ * | | |0001 = GPA.1 wake-up function enabled.\r
+ * | | |0010 = GPA.2 wake-up function enabled.\r
+ * | | |0011 = GPA.3 wake-up function enabled.\r
+ * | | |0100 = GPA.4 wake-up function enabled.\r
+ * | | |0101 = GPA.5 wake-up function enabled.\r
+ * | | |0110 = GPA.6 wake-up function enabled.\r
+ * | | |0111 = GPA.7 wake-up function enabled.\r
+ * | | |1000 = GPA.8 wake-up function enabled.\r
+ * | | |1001 = GPA.9 wake-up function enabled.\r
+ * | | |1010 = GPA.10 wake-up function enabled.\r
+ * | | |1011 = GPA.11 wake-up function enabled.\r
+ * | | |1100 = GPA.12 wake-up function enabled.\r
+ * | | |1101 = GPA.13 wake-up function enabled.\r
+ * | | |1110 = GPA.14 wake-up function enabled.\r
+ * | | |1111 = GPA.15 wake-up function enabled.\r
+ * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit\r
+ * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO.\r
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. \r
+ * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).\r
+ * | | |0 = Standby power-down wake-up pin De-bounce function Disable.\r
+ * | | |1 = Standby power-down wake-up pin De-bounce function Enable.\r
+ * | | |The de-bounce function is valid only for edge triggered.\r
+ * @var CLK_T::PBSWKCTL\r
+ * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit\r
+ * | | |0 = GPB group pin wake-up function Disabled.\r
+ * | | |1 = GPB group pin wake-up function Enabled.\r
+ * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit\r
+ * | | |0 = GPB group pin rising edge wake-up function Disabled.\r
+ * | | |1 = GPB group pin rising edge wake-up function Enabled.\r
+ * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit\r
+ * | | |0 = GPB group pin falling edge wake-up function Disabled.\r
+ * | | |1 = GPB group pin falling edge wake-up function Enabled.\r
+ * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select\r
+ * | | |0000 = GPB.0 wake-up function enabled.\r
+ * | | |0001 = GPB.1 wake-up function enabled.\r
+ * | | |0010 = GPB.2 wake-up function enabled.\r
+ * | | |0011 = GPB.3 wake-up function enabled.\r
+ * | | |0100 = GPB.4 wake-up function enabled.\r
+ * | | |0101 = GPB.5 wake-up function enabled.\r
+ * | | |0110 = GPB.6 wake-up function enabled.\r
+ * | | |0111 = GPB.7 wake-up function enabled.\r
+ * | | |1000 = GPB.8 wake-up function enabled.\r
+ * | | |1001 = GPB.9 wake-up function enabled.\r
+ * | | |1010 = GPB.10 wake-up function enabled.\r
+ * | | |1011 = GPB.11 wake-up function enabled.\r
+ * | | |1100 = GPB.12 wake-up function enabled.\r
+ * | | |1101 = GPB.13 wake-up function enabled.\r
+ * | | |1110 = GPB.14 wake-up function enabled.\r
+ * | | |1111 = GPB.15 wake-up function enabled.\r
+ * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit\r
+ * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO.\r
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.\r
+ * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).\r
+ * | | |0 = Standby power-down wake-up pin De-bounce function Disable.\r
+ * | | |1 = Standby power-down wake-up pin De-bounce function Enable.\r
+ * | | |The de-bounce function is valid only for edge triggered.\r
+ * @var CLK_T::PCSWKCTL\r
+ * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit\r
+ * | | |0 = GPC group pin wake-up function Disabled.\r
+ * | | |1 = GPC group pin wake-up function Enabled.\r
+ * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit\r
+ * | | |0 = GPC group pin rising edge wake-up function Disabled.\r
+ * | | |1 = GPC group pin rising edge wake-up function Enabled.\r
+ * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit\r
+ * | | |0 = GPC group pin falling edge wake-up function Disabled.\r
+ * | | |1 = GPC group pin falling edge wake-up function Enabled.\r
+ * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select\r
+ * | | |0000 = GPC.0 wake-up function enabled.\r
+ * | | |0001 = GPC.1 wake-up function enabled.\r
+ * | | |0010 = GPC.2 wake-up function enabled.\r
+ * | | |0011 = GPC.3 wake-up function enabled.\r
+ * | | |0100 = GPC.4 wake-up function enabled.\r
+ * | | |0101 = GPC.5 wake-up function enabled.\r
+ * | | |0110 = GPC.6 wake-up function enabled.\r
+ * | | |0111 = GPC.7 wake-up function enabled.\r
+ * | | |1000 = GPC.8 wake-up function enabled.\r
+ * | | |1001 = GPC.9 wake-up function enabled.\r
+ * | | |1010 = GPC.10 wake-up function enabled.\r
+ * | | |1011 = GPC.11 wake-up function enabled.\r
+ * | | |1100 = GPC.12 wake-up function enabled.\r
+ * | | |1101 = GPC.13 wake-up function enabled.\r
+ * | | |1110 = Reserved.\r
+ * | | |1111 = Reserved.\r
+ * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit\r
+ * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO.\r
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.\r
+ * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).\r
+ * | | |0 = Standby power-down wake-up pin De-bounce function Disable.\r
+ * | | |1 = Standby power-down wake-up pin De-bounce function Enable.\r
+ * | | |The de-bounce function is valid only for edge triggered.\r
+ * @var CLK_T::PDSWKCTL\r
+ * Offset: 0xAC GPD Standby Power-down Wake-up Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit\r
+ * | | |0 = GPD group pin wake-up function Disabled.\r
+ * | | |1 = GPD group pin wake-up function Enabled.\r
+ * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit\r
+ * | | |0 = GPD group pin rising edge wake-up function Disabled.\r
+ * | | |1 = GPD group pin rising edge wake-up function Enabled.\r
+ * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit\r
+ * | | |0 = GPD group pin falling edge wake-up function Disabled.\r
+ * | | |1 = GPD group pin falling edge wake-up function Enabled.\r
+ * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select\r
+ * | | |0000 = GPD.0 wake-up function enabled.\r
+ * | | |0001 = GPD.1 wake-up function enabled.\r
+ * | | |0010 = GPD.2 wake-up function enabled.\r
+ * | | |0011 = GPD.3 wake-up function enabled.\r
+ * | | |0100 = GPD.4 wake-up function enabled.\r
+ * | | |0101 = GPD.5 wake-up function enabled.\r
+ * | | |0110 = GPD.6 wake-up function enabled.\r
+ * | | |0111 = GPD.7 wake-up function enabled.\r
+ * | | |1000 = GPD.8 wake-up function enabled.\r
+ * | | |1001 = GPD.9 wake-up function enabled.\r
+ * | | |1010 = GPD.10 wake-up function enabled.\r
+ * | | |1011 = GPD.11 wake-up function enabled.\r
+ * | | |1100 = GPD.12 wake-up function enabled.\r
+ * | | |1101 = GPD.13 wake-up function enabled.\r
+ * | | |1110 = GPD.14 wake-up function enabled.\r
+ * | | |1111 = Reserved.\r
+ * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit\r
+ * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO.\r
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.\r
+ * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).\r
+ * | | |0 = Standby power-down wake-up pin De-bounce function Disable.\r
+ * | | |1 = Standby power-down wake-up pin De-bounce function Enable.\r
+ * | | |The de-bounce function is valid only for edge triggered.\r
+ * @var CLK_T::IOPDCTL\r
+ * Offset: 0xB0 GPIO Standby Power-down Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |IOHR |GPIO Hold Release\r
+ * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status.\r
+ * | | |After chip was waked up from standby Power-down mode, the I/O still keeps hold status until user sets this bit to release I/O hold status.\r
+ * | | |Note: This bit is auto cleared by hardware.\r
+ * @var CLK_T::HXTFSEL\r
+ * Offset: 0xB4 HXT Filter Select Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |HXTFSEL |HXT Filter Select\r
+ * | | |0 = HXT frequency is > 12MHz.\r
+ * | | |1 = HXT frequency is <= 12MHz.\r
+ * | | |Note: This bit is auto cleared by hardware.\r
+ */\r
+\r
+\r
+ __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */\r
+ __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */\r
+ __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */\r
+ __IO uint32_t APBCLK1; /*!< [0x000C] APB Devices Clock Enable Control Register 1 */\r
+ __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */\r
+ __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */\r
+ __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */\r
+ __IO uint32_t CLKSEL3; /*!< [0x001C] Clock Source Select Control Register 3 */\r
+ __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */\r
+ __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */\r
+ __I uint32_t RESERVE0[2];\r
+ __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */\r
+ __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */\r
+ __I uint32_t RESERVE1[2];\r
+ __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */\r
+ __I uint32_t RESERVE2[3];\r
+ __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */\r
+ __I uint32_t RESERVE3[3];\r
+ __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */\r
+ __I uint32_t RESERVE4[3];\r
+ __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */\r
+ __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */\r
+ __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Detector Upper Boundary Register */\r
+ __IO uint32_t CDLOWB; /*!< [0x007C] Clock Frequency Detector Low Boundary Register */\r
+ __I uint32_t RESERVE5[4];\r
+ __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */\r
+ __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */\r
+ __I uint32_t RESERVE6[1];\r
+ __IO uint32_t SWKDBCTL; /*!< [0x009C] Standby Power-down Wake-up De-bounce Control Register */\r
+ __IO uint32_t PASWKCTL; /*!< [0x00A0] GPA Standby Power-down Wake-up Control Register */\r
+ __IO uint32_t PBSWKCTL; /*!< [0x00A4] GPB Standby Power-down Wake-up Control Register */\r
+ __IO uint32_t PCSWKCTL; /*!< [0x00A8] GPC Standby Power-down Wake-up Control Register */\r
+ __IO uint32_t PDSWKCTL; /*!< [0x00AC] GPD Standby Power-down Wake-up Control Register */\r
+ __IO uint32_t IOPDCTL; /*!< [0x00B0] GPIO Standby Power-down Control Register */\r
+ __IO uint32_t HXTFSEL; /*!< [0x00B4] HXT Filter Select Control Register */\r
+\r
+} CLK_T;\r
+\r
+/**\r
+ @addtogroup CLK_CONST CLK Bit Field Definition\r
+ Constant Definitions for CLK Controller\r
+@{ */\r
+\r
+#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */\r
+#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */\r
+\r
+#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */\r
+#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */\r
+\r
+#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */\r
+#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */\r
+\r
+#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */\r
+#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */\r
+\r
+#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */\r
+#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */\r
+\r
+#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */\r
+#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */\r
+\r
+#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */\r
+#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */\r
+\r
+#define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */\r
+#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */\r
+\r
+#define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */\r
+#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */\r
+\r
+#define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */\r
+#define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */\r
+\r
+#define CLK_PWRCTL_HIRC48EN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48EN Position */\r
+#define CLK_PWRCTL_HIRC48EN_Msk (0x1ul << CLK_PWRCTL_HIRC48EN_Pos) /*!< CLK_T::PWRCTL: HIRC48EN Mask */\r
+\r
+#define CLK_AHBCLK_PDMA0CKEN_Pos (0) /*!< CLK_T::AHBCLK: PDMA0CKEN Position */\r
+#define CLK_AHBCLK_PDMA0CKEN_Msk (0x1ul << CLK_AHBCLK_PDMA0CKEN_Pos) /*!< CLK_T::AHBCLK: PDMA0CKEN Mask */\r
+\r
+#define CLK_AHBCLK_PDMA1CKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMA1CKEN Position */\r
+#define CLK_AHBCLK_PDMA1CKEN_Msk (0x1ul << CLK_AHBCLK_PDMA1CKEN_Pos) /*!< CLK_T::AHBCLK: PDMA1CKEN Mask */\r
+\r
+#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */\r
+#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */\r
+\r
+#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */\r
+#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */\r
+\r
+#define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */\r
+#define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */\r
+\r
+#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */\r
+#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */\r
+\r
+#define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */\r
+#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */\r
+\r
+#define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */\r
+#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */\r
+\r
+#define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */\r
+#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */\r
+\r
+#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */\r
+#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */\r
+\r
+#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */\r
+#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */\r
+\r
+#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */\r
+#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */\r
+\r
+#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */\r
+#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */\r
+\r
+#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */\r
+#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */\r
+\r
+#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */\r
+#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */\r
+\r
+#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */\r
+#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */\r
+\r
+#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */\r
+#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */\r
+\r
+#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */\r
+#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */\r
+\r
+#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */\r
+#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */\r
+\r
+#define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */\r
+#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */\r
+\r
+#define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */\r
+#define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */\r
+\r
+#define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */\r
+#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */\r
+\r
+#define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */\r
+#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */\r
+\r
+#define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */\r
+#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */\r
+\r
+#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */\r
+#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */\r
+\r
+#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */\r
+#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */\r
+\r
+#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */\r
+#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */\r
+\r
+#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */\r
+#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */\r
+\r
+#define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */\r
+#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */\r
+\r
+#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */\r
+#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */\r
+\r
+#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */\r
+#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */\r
+\r
+#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */\r
+#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */\r
+\r
+#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */\r
+#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */\r
+\r
+#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */\r
+#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */\r
+\r
+#define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */\r
+#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */\r
+\r
+#define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */\r
+#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */\r
+\r
+#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */\r
+#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */\r
+\r
+#define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */\r
+#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */\r
+\r
+#define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */\r
+#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */\r
+\r
+#define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */\r
+#define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */\r
+\r
+#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */\r
+#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */\r
+\r
+#define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */\r
+#define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */\r
+\r
+#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */\r
+#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */\r
+\r
+#define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */\r
+#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */\r
+\r
+#define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */\r
+#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */\r
+\r
+#define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */\r
+#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */\r
+\r
+#define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */\r
+#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */\r
+\r
+#define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */\r
+#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */\r
+\r
+#define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */\r
+#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */\r
+\r
+#define CLK_APBCLK1_TRNGCKEN_Pos (25) /*!< CLK_T::APBCLK1: TRNGCKEN Position */\r
+#define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) /*!< CLK_T::APBCLK1: TRNGCKEN Mask */\r
+\r
+#define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */\r
+#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */\r
+\r
+#define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */\r
+#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */\r
+\r
+#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */\r
+#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */\r
+\r
+#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */\r
+#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */\r
+\r
+#define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: USBSEL Position */\r
+#define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: USBSEL Mask */\r
+\r
+#define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */\r
+#define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */\r
+\r
+#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */\r
+#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */\r
+\r
+#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */\r
+#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */\r
+\r
+#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */\r
+#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */\r
+\r
+#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */\r
+#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */\r
+\r
+#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */\r
+#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */\r
+\r
+#define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */\r
+#define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */\r
+\r
+#define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */\r
+#define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */\r
+\r
+#define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */\r
+#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */\r
+\r
+#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */\r
+#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */\r
+\r
+#define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */\r
+#define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */\r
+\r
+#define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */\r
+#define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */\r
+\r
+#define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */\r
+#define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */\r
+\r
+#define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */\r
+#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */\r
+\r
+#define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */\r
+#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */\r
+\r
+#define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */\r
+#define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */\r
+\r
+#define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */\r
+#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */\r
+\r
+#define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */\r
+#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */\r
+\r
+#define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */\r
+#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */\r
+\r
+#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */\r
+#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */\r
+\r
+#define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */\r
+#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */\r
+\r
+#define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */\r
+#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */\r
+\r
+#define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */\r
+#define CLK_CLKSEL3_RTCSEL_Msk (0x3ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */\r
+\r
+#define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */\r
+#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */\r
+\r
+#define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */\r
+#define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */\r
+\r
+#define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */\r
+#define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */\r
+\r
+#define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */\r
+#define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */\r
+\r
+#define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */\r
+#define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */\r
+\r
+#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */\r
+#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */\r
+\r
+#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */\r
+#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */\r
+\r
+#define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */\r
+#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */\r
+\r
+#define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */\r
+#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */\r
+\r
+#define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */\r
+#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */\r
+\r
+#define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */\r
+#define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */\r
+\r
+#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */\r
+#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */\r
+\r
+#define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */\r
+#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */\r
+\r
+#define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */\r
+#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */\r
+\r
+#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */\r
+#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */\r
+\r
+#define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */\r
+#define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */\r
+\r
+#define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */\r
+#define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */\r
+\r
+#define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */\r
+#define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */\r
+\r
+#define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */\r
+#define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */\r
+\r
+#define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */\r
+#define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */\r
+\r
+#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */\r
+#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */\r
+\r
+#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */\r
+#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */\r
+\r
+#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */\r
+#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */\r
+\r
+#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */\r
+#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */\r
+\r
+#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */\r
+#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */\r
+\r
+#define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */\r
+#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */\r
+\r
+#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */\r
+#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */\r
+\r
+#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */\r
+#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */\r
+\r
+#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */\r
+#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */\r
+\r
+#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */\r
+#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */\r
+\r
+#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */\r
+#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */\r
+\r
+#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */\r
+#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */\r
+\r
+#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */\r
+#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */\r
+\r
+#define CLK_STATUS_HIRC48STB_Pos (6) /*!< CLK_T::STATUS: HIRC48STB Position */\r
+#define CLK_STATUS_HIRC48STB_Msk (0x1ul << CLK_STATUS_HIRC48STB_Pos) /*!< CLK_T::STATUS: HIRC48STB Mask */\r
+\r
+#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */\r
+#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */\r
+\r
+#define CLK_STATUS_EXTLXTSTB_Pos (8) /*!< CLK_T::STATUS: EXTLXTSTB Position */\r
+#define CLK_STATUS_EXTLXTSTB_Msk (0x1ul << CLK_STATUS_EXTLXTSTB_Pos) /*!< CLK_T::STATUS: EXTLXTSTB Mask */\r
+\r
+#define CLK_STATUS_LIRC32STB_Pos (9) /*!< CLK_T::STATUS: LIRC32STB Position */\r
+#define CLK_STATUS_LIRC32STB_Msk (0x1ul << CLK_STATUS_LIRC32STB_Pos) /*!< CLK_T::STATUS: LIRC32STB Mask */\r
+\r
+#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */\r
+#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */\r
+\r
+#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */\r
+#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */\r
+\r
+#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */\r
+#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */\r
+\r
+#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */\r
+#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */\r
+\r
+#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */\r
+#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */\r
+\r
+#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */\r
+#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */\r
+\r
+#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */\r
+#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */\r
+\r
+#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */\r
+#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */\r
+\r
+#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */\r
+#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */\r
+\r
+#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */\r
+#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */\r
+\r
+#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */\r
+#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */\r
+\r
+#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */\r
+#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */\r
+\r
+#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */\r
+#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */\r
+\r
+#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */\r
+#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */\r
+\r
+#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */\r
+#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */\r
+\r
+#define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */\r
+#define CLK_PMUCTL_PDMSEL_Msk (0x7ul<< CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */\r
+\r
+#define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */\r
+#define CLK_PMUCTL_WKTMREN_Msk (0x1ul<< CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */\r
+\r
+#define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */\r
+#define CLK_PMUCTL_WKTMRIS_Msk (0x7ul<< CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */\r
+\r
+#define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */\r
+#define CLK_PMUCTL_WKPINEN_Msk (0x3ul<< CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */\r
+\r
+#define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */\r
+#define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul<< CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */\r
+\r
+#define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */\r
+#define CLK_PMUCTL_RTCWKEN_Msk (0x1ul<< CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */\r
+\r
+#define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */\r
+#define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */\r
+\r
+#define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */\r
+#define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */\r
+\r
+#define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */\r
+#define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */\r
+\r
+#define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */\r
+#define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */\r
+\r
+#define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */\r
+#define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */\r
+\r
+#define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */\r
+#define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */\r
+\r
+#define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */\r
+#define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */\r
+\r
+#define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */\r
+#define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */\r
+\r
+#define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */\r
+#define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */\r
+\r
+#define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */\r
+#define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */\r
+\r
+#define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */\r
+#define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */\r
+\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xFul<< CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */\r
+\r
+#define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */\r
+#define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */\r
+\r
+#define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */\r
+#define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */\r
+\r
+#define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */\r
+#define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */\r
+\r
+#define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */\r
+#define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */\r
+\r
+#define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */\r
+#define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */\r
+\r
+#define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */\r
+#define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */\r
+\r
+#define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */\r
+#define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */\r
+\r
+#define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */\r
+#define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */\r
+\r
+#define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */\r
+#define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */\r
+\r
+#define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */\r
+#define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */\r
+\r
+#define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */\r
+#define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */\r
+\r
+#define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */\r
+#define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */\r
+\r
+#define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */\r
+#define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */\r
+\r
+#define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */\r
+#define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */\r
+\r
+#define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */\r
+#define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */\r
+\r
+#define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */\r
+#define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */\r
+\r
+#define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */\r
+#define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */\r
+\r
+#define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */\r
+#define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */\r
+\r
+#define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */\r
+#define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */\r
+\r
+#define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */\r
+#define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */\r
+\r
+#define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */\r
+#define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */\r
+\r
+#define CLK_HXTFSEL_HXTFSEL_Pos (0) /*!< CLK_T::HXTFSEL: HXTFSEL Position */\r
+#define CLK_HXTFSEL_HXTFSEL_Msk (0x1ul << CLK_HXTFSEL_HXTFSEL_Pos) /*!< CLK_T::HXTFSEL: HXTFSEL Mask */\r
+\r
+\r
+/**@}*/ /* CLK_CONST */\r
+/**@}*/ /* end of CLK register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __CLK_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file crc_reg.h\r
+ * @version V1.00\r
+ * @brief CRC register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __CRC_REG_H__\r
+#define __CRC_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- Cyclic Redundancy Check Controller -------------------------*/\r
+/**\r
+ @addtogroup CRC Cyclic Redundancy Check Controller(CRC)\r
+ Memory Mapped Structure for CRC Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var CRC_T::CTL\r
+ * Offset: 0x00 CRC Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CRCEN |CRC Channel Generator Enable Bit\r
+ * | | |Set this bit 1 to enable CRC generator for CRC operation.\r
+ * | | |0 = No effect.\r
+ * | | |1 = CRC operation generator is active.\r
+ * |[1] |CHKSINIT |Checksum Initialization\r
+ * | | |Set this bit will auto reload SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reload SEED value to CHECKSUM register as CRC operation initial checksum value.\r
+ * | | |The others contents of CRC_CTL register will not be cleared.\r
+ * | | |Note1: This bit will be cleared automatically\r
+ * | | |Note2: Setting this bit will reload the seed value from CRC_SEED register as checksum initial value.\r
+ * |[24] |DATREV |Write Data Bit Order Reverse Enable Bit\r
+ * | | |This bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]) in CRC_DAT register.\r
+ * | | |0 = Bit order reversed for CRC_DATA write data in Disabled.\r
+ * | | |1 = Bit order reversed for CRC_DATA write data in Enabled (per byte).\r
+ * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.\r
+ * |[25] |CHKSREV |Checksum Bit Order Reverse Enable Bit\r
+ * | | |This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).\r
+ * | | |0 = Bit order reverse for CRC CHECKSUMCRC checksum Disabled.\r
+ * | | |1 = Bit order reverse for CRC CHECKSUMCRC checksum Enabled.\r
+ * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB.\r
+ * |[26] |DATFMT |Write Data 1's Complement Enable Bit\r
+ * | | |This bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0]).\r
+ * | | |0 = 1's complement for CRC_DATA writes data in Disabled.\r
+ * | | |1 = 1's complement for CRC_DATA writes data in Enabled.\r
+ * |[27] |CHKSFMT |Checksum 1's Complement Enable Bit\r
+ * | | |This bit is used to enable the 1's complement function for checksum result in CHECKSUM (CRC_CHECKSUM[31:0]) register.\r
+ * | | |0 = 1's complement for CRC CHECKSUM Disabled.\r
+ * | | |1 = 1's complement for CRC CHECKSUMCRC Enabled.\r
+ * |[29:28] |DATLEN |CPU Write Data Length\r
+ * | | |This field indicates the valid write data length of DATA (CRC_DAT[31:0]).\r
+ * | | |00 = Data length is 8-bit mode.\r
+ * | | |01 = Data length is 16-bit mode.\r
+ * | | |1x = Data length is 32-bit mode.\r
+ * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]\r
+ * |[31:30] |CRCMODE |CRC Polynomial Mode\r
+ * | | |This field indicates the CRC operation polynomial mode.\r
+ * | | |00 = CRC-CCITT Polynomial mode.\r
+ * | | |01 = CRC-8 Polynomial mode.\r
+ * | | |10 = CRC-16 Polynomial mode.\r
+ * | | |11 = CRC-32 Polynomial mode.\r
+ * @var CRC_T::DAT\r
+ * Offset: 0x04 CRC Write Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DATA |CRC Write Data Bits\r
+ * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\r
+ * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].\r
+ * @var CRC_T::SEED\r
+ * Offset: 0x08 CRC Seed Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SEED |CRC Seed Value\r
+ * | | |This field indicates the CRC seed value.\r
+ * | | |Note1: This field SEED value will be reloaded to as checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) register) after perform CRC engine reset, CHKSINIT (CRC_CTL[1]) to 1.\r
+ * | | |Note2: The valid bits of CRC_SEED[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).\r
+ * @var CRC_T::CHECKSUM\r
+ * Offset: 0x0C CRC Checksum Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CHECKSUM |CRC Checksum Results\r
+ * | | |This field indicates the CRC checksum result.\r
+ * | | |Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).\r
+ */\r
+ __IO uint32_t CTL; /*!< [0x0000] CRC Control Register */\r
+ __IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */\r
+ __IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */\r
+ __I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */\r
+\r
+} CRC_T;\r
+\r
+/**\r
+ @addtogroup CRC_CONST CRC Bit Field Definition\r
+ Constant Definitions for CRC Controller\r
+@{ */\r
+\r
+#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */\r
+#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */\r
+\r
+#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */\r
+#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */\r
+\r
+#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */\r
+#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */\r
+\r
+#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */\r
+#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */\r
+\r
+#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */\r
+#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */\r
+\r
+#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */\r
+#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */\r
+\r
+#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */\r
+#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */\r
+\r
+#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */\r
+#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */\r
+\r
+#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */\r
+#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */\r
+\r
+#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */\r
+#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */\r
+\r
+#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */\r
+#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */\r
+\r
+/**@}*/ /* CRC_CONST */\r
+/**@}*/ /* end of CRC register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __CLK_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file crpt_reg.h\r
+ * @version V1.00\r
+ * @brief CRPT register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __CRPT_REG_H__\r
+#define __CRPT_REG_H__\r
+\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- Cryptographic Accelerator -------------------------*/\r
+/**\r
+ @addtogroup CRPT Cryptographic Accelerator(CRPT)\r
+ Memory Mapped Structure for CRPT Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var CRPT_T::INTEN\r
+ * Offset: 0x00 Crypto Interrupt Enable Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |AESIEN |AES Interrupt Enable Control\r
+ * | | |0 = AES interrupt Disabled.\r
+ * | | |1 = AES interrupt Enabled.\r
+ * | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.\r
+ * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.\r
+ * |[1] |AESEIEN |AES Error Flag Enable Control\r
+ * | | |0 = AES error interrupt flag Disabled.\r
+ * | | |1 = AES error interrupt flag Enabled.\r
+ * |[8] |TDESIEN |TDES/DES Interrupt Enable Control\r
+ * | | |0 = TDES/DES interrupt Disabled.\r
+ * | | |1 = TDES/DES interrupt Enabled.\r
+ * | | |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine.\r
+ * | | |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.\r
+ * |[9] |TDESEIEN |TDES/DES Error Flag Enable Control\r
+ * | | |0 = TDES/DES error interrupt flag Disabled.\r
+ * | | |1 = TDES/DES error interrupt flag Enabled.\r
+ * |[16] |PRNGIEN |PRNG Interrupt Enable Control\r
+ * | | |0 = PRNG interrupt Disabled.\r
+ * | | |1 = PRNG interrupt Enabled.\r
+ * |[22] |ECCIEN |ECC Interrupt Enable Control\r
+ * | | |0 = ECC interrupt Disabled.\r
+ * | | |1 = ECC interrupt Enabled.\r
+ * | | |In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine.\r
+ * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation.\r
+ * |[23] |ECCEIEN |ECC Error Interrupt Enable Control\r
+ * | | |0 = ECC error interrupt flag Disabled.\r
+ * | | |1 = ECC error interrupt flag Enabled.\r
+ * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Control\r
+ * | | |0 = SHA/HMAC interrupt Disabled.\r
+ * | | |1 = SHA/HMAC interrupt Enabled.\r
+ * | | |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA/HMAC engine\r
+ * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation.\r
+ * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Control\r
+ * | | |0 = SHA/HMAC error interrupt flag Disabled.\r
+ * | | |1 = SHA/HMAC error interrupt flag Enabled.\r
+ * @var CRPT_T::INTSTS\r
+ * Offset: 0x04 Crypto Interrupt Flag\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |AESIF |AES Finish Interrupt Flag\r
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.\r
+ * | | |0 = No AES interrupt.\r
+ * | | |1 = AES encryption/decryption done interrupt.\r
+ * |[1] |AESEIF |AES Error Flag\r
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.\r
+ * | | |0 = No AES error.\r
+ * | | |1 = AES encryption/decryption done interrupt.\r
+ * |[8] |TDESIF |TDES/DES Finish Interrupt Flag\r
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.\r
+ * | | |0 = No TDES/DES interrupt.\r
+ * | | |1 = TDES/DES encryption/decryption done interrupt.\r
+ * |[9] |TDESEIF |TDES/DES Error Flag\r
+ * | | |This bit includes the operating and setting error\r
+ * | | |The detailed flag is shown in the TDES _FLAG register\r
+ * | | |This includes operating and setting error.\r
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.\r
+ * | | |0 = No TDES/DES error.\r
+ * | | |1 = TDES/DES encryption/decryption error interrupt.\r
+ * |[16] |PRNGIF |PRNG Finish Interrupt Flag\r
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.\r
+ * | | |0 = No PRNG interrupt.\r
+ * | | |1 = PRNG key generation done interrupt.\r
+ * |[22] |ECCIF |ECC Finish Interrupt Flag\r
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.\r
+ * | | |0 = No ECC interrupt.\r
+ * | | |1 = ECC operation done interrupt.\r
+ * |[23] |ECCEIF |ECC Error Flag\r
+ * | | |This register includes operating and setting error. The detail flag is shown in ECC _FLAG register.\r
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.\r
+ * | | |0 = No ECC error.\r
+ * | | |1 = ECC error interrupt.\r
+ * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag\r
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.\r
+ * | | |0 = No SHA/HMAC interrupt.\r
+ * | | |1 = SHA/HMAC operation done interrupt.\r
+ * |[25] |HMACEIF |SHA/HMAC Error Flag\r
+ * | | |This register includes operating and setting error. The detail flag is shown in SHA _FLAG register.\r
+ * | | |This bit is cleared by writing 1, and it has no effect by writing 0.\r
+ * | | |0 = No SHA/HMAC error.\r
+ * | | |1 = SHA/HMAC error interrupt.\r
+ * @var CRPT_T::PRNG_CTL\r
+ * Offset: 0x08 PRNG Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |START |Start PRNG Engine\r
+ * | | |0 = Stop PRNG engine.\r
+ * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated.\r
+ * |[1] |SEEDRLD |Reload New Seed for PRNG Engine\r
+ * | | |0 = Generating key based on the current seed.\r
+ * | | |1 = Reload new seed.\r
+ * |[3:2] |KEYSZ |PRNG Generate Key Size\r
+ * | | |00 = 64 bits.\r
+ * | | |01 = 128 bits.\r
+ * | | |10 = 192 bits.\r
+ * | | |11 = 256 bits.\r
+ * |[8] |BUSY |PRNG Busy (Read Only)\r
+ * | | |0 = PRNG engine is idle.\r
+ * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.\r
+ * @var CRPT_T::PRNG_SEED\r
+ * Offset: 0x0C Seed for PRNG\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SEED |Seed for PRNG (Write Only)\r
+ * | | |The bits store the seed for PRNG engine.\r
+ * @var CRPT_T::PRNG_KEY[8]\r
+ * Offset: 0x10 PRNG Generated Key0~Key7\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |Store PRNG Generated Key (Read Only)\r
+ * | | |The bits store the key that is generated by PRNG.\r
+ * @var CRPT_T::AES_FDBCK[4]\r
+ * Offset: 0x50 AES Engine Output Feedback Data after Cryptographic Operation\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |FDBCK |AES Feedback Information\r
+ * | | |The feedback value is 128 bits in size.\r
+ * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode.\r
+ * | | |The AES engine outputs feedback information for IV in the next block's operation\r
+ * | | |Software can use this feedback information to implement more than four DMA channels\r
+ * | | |Software can store that feedback value temporarily\r
+ * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.\r
+ * @var CRPT_T::TDES_FDBCKH\r
+ * Offset: 0x60 TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |FDBCK |TDES/DES Feedback\r
+ * | | |The feedback value is 64 bits in size.\r
+ * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode\r
+ * | | |The feedback register is for CBC, CFB, and OFB mode.\r
+ * | | |TDES/DES engine outputs feedback information for IV in the next block's operation\r
+ * | | |Software can use this feedback information to implement more than four DMA channels\r
+ * | | |Software can store that feedback value temporarily\r
+ * | | |After switching back, fill the stored feedback value to this register in the same channel operation\r
+ * | | |Then can continue the operation with the original setting.\r
+ * @var CRPT_T::TDES_FDBCKL\r
+ * Offset: 0x64 TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |FDBCK |TDES/DES Feedback\r
+ * | | |The feedback value is 64 bits in size.\r
+ * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode\r
+ * | | |The feedback register is for CBC, CFB, and OFB mode.\r
+ * | | |TDES/DES engine outputs feedback information for IV in the next block's operation\r
+ * | | |Software can use this feedback information to implement more than four DMA channels\r
+ * | | |Software can store that feedback value temporarily\r
+ * | | |After switching back, fill the stored feedback value to this register in the same channel operation\r
+ * | | |Then can continue the operation with the original setting.\r
+ * @var CRPT_T::AES_CTL\r
+ * Offset: 0x100 AES Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |START |AES Engine Start\r
+ * | | |0 = No effect.\r
+ * | | |1 = Start AES engine. BUSY flag will be set.\r
+ * | | |Note: This bit is always 0 when it's read back.\r
+ * |[1] |STOP |AES Engine Stop\r
+ * | | |0 = No effect.\r
+ * | | |1 = Stop AES engine.\r
+ * | | |Note: This bit is always 0 when it's read back.\r
+ * |[3:2] |KEYSZ |AES Key Size\r
+ * | | |This bit defines three different key size for AES operation.\r
+ * | | |2'b00 = 128 bits key.\r
+ * | | |2'b01 = 192 bits key.\r
+ * | | |2'b10 = 256 bits key.\r
+ * | | |2'b11 = Reserved.\r
+ * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.\r
+ * |[5] |DMALAST |AES Last Block\r
+ * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.\r
+ * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.\r
+ * | | |This bit is always 0 when it's read back. Must be written again once START is triggered.\r
+ * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode\r
+ * | | |0 = DMA cascade function Disabled.\r
+ * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.\r
+ * |[7] |DMAEN |AES Engine DMA Enable Control\r
+ * | | |0 = AES DMA engine Disabled.\r
+ * | | |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN.\r
+ * | | |1 = AES_DMA engine Enabled.\r
+ * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.\r
+ * |[15:8] |OPMODE |AES Engine Operation Modes\r
+ * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode).\r
+ * | | |0x02 = CFB (Cipher Feedback Mode).\r
+ * | | |0x03 = OFB (Output Feedback Mode).\r
+ * | | |0x04 = CTR (Counter Mode).\r
+ * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode).\r
+ * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode).\r
+ * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode).\r
+ * |[16] |ENCRPT |AES Encryption/Decryption\r
+ * | | |0 = AES engine executes decryption operation.\r
+ * | | |1 = AES engine executes encryption operation.\r
+ * |[22] |OUTSWAP |AES Engine Output Data Swap\r
+ * | | |0 = Keep the original order.\r
+ * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.\r
+ * |[23] |INSWAP |AES Engine Input Data Swap\r
+ * | | |0 = Keep the original order.\r
+ * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.\r
+ * |[25:24] |CHANNEL |AES Engine Working Channel\r
+ * | | |00 = Current control register setting is for channel 0.\r
+ * | | |01 = Current control register setting is for channel 1.\r
+ * | | |10 = Current control register setting is for channel 2.\r
+ * | | |11 = Current control register setting is for channel 3.\r
+ * |[30:26] |KEYUNPRT |Unprotect Key\r
+ * | | |Writing 0 to CRPT_AES_CTL[31] and ...10110 to CRPT_AES_CTL[30:26] is to unprotect the AES key.\r
+ * | | |The KEYUNPRT can be read and written\r
+ * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.\r
+ * |[31] |KEYPRT |Protect Key\r
+ * | | |Read as a flag to reflect KEYPRT.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Protect the content of the AES key from reading\r
+ * | | |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx\r
+ * | | |Once it is set, it can be cleared by asserting KEYUNPRT\r
+ * | | |And the key content would be cleared as well.\r
+ * @var CRPT_T::AES_STS\r
+ * Offset: 0x104 AES Engine Flag\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BUSY |AES Engine Busy\r
+ * | | |0 = The AES engine is idle or finished.\r
+ * | | |1 = The AES engine is under processing.\r
+ * |[8] |INBUFEMPTY|AES Input Buffer Empty\r
+ * | | |0 = There are some data in input buffer waiting for the AES engine to process.\r
+ * | | |1 = AES input buffer is empty\r
+ * | | |Software needs to feed data to the AES engine\r
+ * | | |Otherwise, the AES engine will be pending to wait for input data.\r
+ * |[9] |INBUFFULL |AES Input Buffer Full Flag\r
+ * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine.\r
+ * | | |1 = AES input buffer is full\r
+ * | | |Software cannot feed data to the AES engine\r
+ * | | |Otherwise, the flag INBUFERR will be set to 1.\r
+ * |[10] |INBUFERR |AES Input Buffer Error Flag\r
+ * | | |0 = No error.\r
+ * | | |1 = Error happens during feeding data to the AES engine.\r
+ * |[12] |CNTERR |CRPT_AESn_CNT Setting Error\r
+ * | | |0 = No error in CRPT_AESn_CNT setting.\r
+ * | | |1 = CRPT_AESn_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode.\r
+ * |[16] |OUTBUFEMPTY|AES Out Buffer Empty\r
+ * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer.\r
+ * | | |1 = AES output buffer is empty\r
+ * | | |Software cannot get data from CRPT_AES_DATOUT\r
+ * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty.\r
+ * |[17] |OUTBUFFULL|AES Out Buffer Full Flag\r
+ * | | |0 = AES output buffer is not full.\r
+ * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT\r
+ * | | |Otherwise, the AES engine will be pending since the output buffer is full.\r
+ * |[18] |OUTBUFERR |AES Out Buffer Error Flag\r
+ * | | |0 = No error.\r
+ * | | |1 = Error happens during getting the result from AES engine.\r
+ * |[20] |BUSERR |AES DMA Access Bus Error Flag\r
+ * | | |0 = No error.\r
+ * | | |1 = Bus error will stop DMA operation and AES engine.\r
+ * @var CRPT_T::AES_DATIN\r
+ * Offset: 0x108 AES Engine Data Input Port Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DATIN |AES Engine Input Port\r
+ * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.\r
+ * @var CRPT_T::AES_DATOUT\r
+ * Offset: 0x10C AES Engine Data Output Port Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DATOUT |AES Engine Output Port\r
+ * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS\r
+ * | | |Get data as OUTBUFEMPTY is 0.\r
+ * @var CRPT_T::AES0_KEY[8]\r
+ * Offset: 0x110~0x12C AES Key Word 0~7 Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |CRPT_AESn_KEYx\r
+ * | | |The KEY keeps the security key for AES operation.\r
+ * | | |n = 0, 1..3.\r
+ * | | |x = 0, 1..7.\r
+ * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key\r
+ * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation\r
+ * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation\r
+ * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.\r
+ * @var CRPT_T::AES0_IV[4]\r
+ * Offset: 0x130~0x13C AES Initial Vector Word 0~3 Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |IV |AES Initial Vectors\r
+ * | | |n = 0, 1..3.\r
+ * | | |x = 0, 1..3.\r
+ * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode\r
+ * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.\r
+ * @var CRPT_T::AES0_SADDR\r
+ * Offset: 0x140 AES DMA Source Address Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SADDR |AES DMA Source Address\r
+ * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO\r
+ * | | |The SADDR keeps the source address of the data buffer where the source text is stored\r
+ * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation\r
+ * | | |The start of source address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of SADDR are ignored.\r
+ * | | |SADDR can be read and written\r
+ * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation\r
+ * | | |But the value of SADDR will be updated later on\r
+ * | | |Consequently, software can prepare the DMA source address for the next AES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.\r
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.\r
+ * @var CRPT_T::AES0_DADDR\r
+ * Offset: 0x144 AES DMA Destination Address Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DADDR |AES DMA Destination Address\r
+ * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO\r
+ * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored\r
+ * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished\r
+ * | | |The start of destination address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of DADDR are ignored.\r
+ * | | |DADDR can be read and written\r
+ * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation\r
+ * | | |But the value of DADDR will be updated later on\r
+ * | | |Consequently, software can prepare the destination address for the next AES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.\r
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.\r
+ * @var CRPT_T::AES0_CNT\r
+ * Offset: 0x148 AES Byte Count Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNT |AES Byte Count\r
+ * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode\r
+ * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\r
+ * | | |CRPT_AESn_CNT can be read and written\r
+ * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation\r
+ * | | |But the value of CRPT_AESn_CNT will be updated later on\r
+ * | | |Consequently, software can prepare the byte count of data for the next AES operation.\r
+ * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block\r
+ * | | |Operations that are less than one block will output unexpected result.\r
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data\r
+ * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.\r
+ * @var CRPT_T::AES1_KEY[8]\r
+ * Offset: 0x14C~0x168 AES Key Word 0~7 Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |CRPT_AESn_KEYx\r
+ * | | |The KEY keeps the security key for AES operation.\r
+ * | | |n = 0, 1..3.\r
+ * | | |x = 0, 1..7.\r
+ * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key\r
+ * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation\r
+ * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation\r
+ * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.\r
+ * @var CRPT_T::AES1_IV[4]\r
+ * Offset: 0x16C~0x178 AES Initial Vector Word 0~3 Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |IV |AES Initial Vectors\r
+ * | | |n = 0, 1..3.\r
+ * | | |x = 0, 1..3.\r
+ * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode\r
+ * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.\r
+ * @var CRPT_T::AES1_SADDR\r
+ * Offset: 0x17C AES DMA Source Address Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SADDR |AES DMA Source Address\r
+ * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO\r
+ * | | |The SADDR keeps the source address of the data buffer where the source text is stored\r
+ * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation\r
+ * | | |The start of source address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of SADDR are ignored.\r
+ * | | |SADDR can be read and written\r
+ * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation\r
+ * | | |But the value of SADDR will be updated later on\r
+ * | | |Consequently, software can prepare the DMA source address for the next AES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.\r
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.\r
+ * @var CRPT_T::AES1_DADDR\r
+ * Offset: 0x180 AES DMA Destination Address Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DADDR |AES DMA Destination Address\r
+ * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO\r
+ * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored\r
+ * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished\r
+ * | | |The start of destination address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of DADDR are ignored.\r
+ * | | |DADDR can be read and written\r
+ * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation\r
+ * | | |But the value of DADDR will be updated later on\r
+ * | | |Consequently, software can prepare the destination address for the next AES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.\r
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.\r
+ * @var CRPT_T::AES1_CNT\r
+ * Offset: 0x184 AES Byte Count Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNT |AES Byte Count\r
+ * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode\r
+ * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\r
+ * | | |CRPT_AESn_CNT can be read and written\r
+ * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation\r
+ * | | |But the value of CRPT_AESn_CNT will be updated later on\r
+ * | | |Consequently, software can prepare the byte count of data for the next AES operation.\r
+ * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block\r
+ * | | |Operations that are less than one block will output unexpected result.\r
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data\r
+ * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.\r
+ * @var CRPT_T::AES2_KEY[8]\r
+ * Offset: 0x188~0x1A4 AES Key Word 0~7 Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |CRPT_AESn_KEYx\r
+ * | | |The KEY keeps the security key for AES operation.\r
+ * | | |n = 0, 1..3.\r
+ * | | |x = 0, 1..7.\r
+ * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key\r
+ * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation\r
+ * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation\r
+ * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.\r
+ * @var CRPT_T::AES2_IV[4]\r
+ * Offset: 0x1A8~0x1B4 AES Initial Vector Word 0~3 Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |IV |AES Initial Vectors\r
+ * | | |n = 0, 1..3.\r
+ * | | |x = 0, 1..3.\r
+ * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode\r
+ * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.\r
+ * @var CRPT_T::AES2_SADDR\r
+ * Offset: 0x1B8 AES DMA Source Address Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SADDR |AES DMA Source Address\r
+ * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO\r
+ * | | |The SADDR keeps the source address of the data buffer where the source text is stored\r
+ * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation\r
+ * | | |The start of source address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of SADDR are ignored.\r
+ * | | |SADDR can be read and written\r
+ * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation\r
+ * | | |But the value of SADDR will be updated later on\r
+ * | | |Consequently, software can prepare the DMA source address for the next AES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.\r
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.\r
+ * @var CRPT_T::AES2_DADDR\r
+ * Offset: 0x1BC AES DMA Destination Address Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DADDR |AES DMA Destination Address\r
+ * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO\r
+ * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored\r
+ * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished\r
+ * | | |The start of destination address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of DADDR are ignored.\r
+ * | | |DADDR can be read and written\r
+ * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation\r
+ * | | |But the value of DADDR will be updated later on\r
+ * | | |Consequently, software can prepare the destination address for the next AES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.\r
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.\r
+ * @var CRPT_T::AES2_CNT\r
+ * Offset: 0x1C0 AES Byte Count Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNT |AES Byte Count\r
+ * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode\r
+ * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\r
+ * | | |CRPT_AESn_CNT can be read and written\r
+ * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation\r
+ * | | |But the value of CRPT_AESn_CNT will be updated later on\r
+ * | | |Consequently, software can prepare the byte count of data for the next AES operation.\r
+ * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block\r
+ * | | |Operations that are less than one block will output unexpected result.\r
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data\r
+ * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.\r
+ * @var CRPT_T::AES3_KEY[8]\r
+ * Offset: 0x1C4~0x1E0 AES Key Word 0~7 Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |CRPT_AESn_KEYx\r
+ * | | |The KEY keeps the security key for AES operation.\r
+ * | | |n = 0, 1..3.\r
+ * | | |x = 0, 1..7.\r
+ * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key\r
+ * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation\r
+ * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation\r
+ * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.\r
+ * @var CRPT_T::AES3_IV[4]\r
+ * Offset: 0x1E4~0x1F0 AES Initial Vector Word 0~3 Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |IV |AES Initial Vectors\r
+ * | | |n = 0, 1..3.\r
+ * | | |x = 0, 1..3.\r
+ * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode\r
+ * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.\r
+ * @var CRPT_T::AES3_SADDR\r
+ * Offset: 0x1F4 AES DMA Source Address Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SADDR |AES DMA Source Address\r
+ * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO\r
+ * | | |The SADDR keeps the source address of the data buffer where the source text is stored\r
+ * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation\r
+ * | | |The start of source address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of SADDR are ignored.\r
+ * | | |SADDR can be read and written\r
+ * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation\r
+ * | | |But the value of SADDR will be updated later on\r
+ * | | |Consequently, software can prepare the DMA source address for the next AES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.\r
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.\r
+ * @var CRPT_T::AES3_DADDR\r
+ * Offset: 0x1F8 AES DMA Destination Address Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DADDR |AES DMA Destination Address\r
+ * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO\r
+ * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored\r
+ * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished\r
+ * | | |The start of destination address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of DADDR are ignored.\r
+ * | | |DADDR can be read and written\r
+ * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation\r
+ * | | |But the value of DADDR will be updated later on\r
+ * | | |Consequently, software can prepare the destination address for the next AES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.\r
+ * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.\r
+ * @var CRPT_T::AES3_CNT\r
+ * Offset: 0x1FC AES Byte Count Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNT |AES Byte Count\r
+ * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode\r
+ * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\r
+ * | | |CRPT_AESn_CNT can be read and written\r
+ * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation\r
+ * | | |But the value of CRPT_AESn_CNT will be updated later on\r
+ * | | |Consequently, software can prepare the byte count of data for the next AES operation.\r
+ * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block\r
+ * | | |Operations that are less than one block will output unexpected result.\r
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data\r
+ * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.\r
+ * @var CRPT_T::TDES_CTL\r
+ * Offset: 0x200 TDES/DES Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |START |TDES/DES Engine Start\r
+ * | | |0 = No effect.\r
+ * | | |1 = Start TDES/DES engine. The flag BUSY would be set.\r
+ * | | |Note: The bit is always 0 when it's read back.\r
+ * |[1] |STOP |TDES/DES Engine Stop\r
+ * | | |0 = No effect.\r
+ * | | |1 = Stop TDES/DES engine.\r
+ * | | |Note: The bit is always 0 when it's read back.\r
+ * |[2] |TMODE |TDES/DES Engine Operating Mode\r
+ * | | |0 = Set DES mode for TDES/DES engine.\r
+ * | | |1 = Set Triple DES mode for TDES/DES engine.\r
+ * |[3] |3KEYS |TDES/DES Key Number\r
+ * | | |0 = Select KEY1 and KEY2 in TDES/DES engine.\r
+ * | | |1 = Triple keys in TDES/DES engine Enabled.\r
+ * |[5] |DMALAST |TDES/DES Engine Start for the Last Block\r
+ * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.\r
+ * | | |In Non-DMA mode, this bit must be set as feeding in last block of data.\r
+ * |[6] |DMACSCAD |TDES/DES Engine DMA with Cascade Mode\r
+ * | | |0 = DMA cascade function Disabled.\r
+ * | | |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.\r
+ * |[7] |DMAEN |TDES/DES Engine DMA Enable Control\r
+ * | | |0 = TDES_DMA engine Disabled.\r
+ * | | |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN.\r
+ * | | |1 = TDES_DMA engine Enabled.\r
+ * | | |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.\r
+ * |[10:8] |OPMODE |TDES/DES Engine Operation Mode\r
+ * | | |0x00 = ECB (Electronic Codebook Mode).\r
+ * | | |0x01 = CBC (Cipher Block Chaining Mode).\r
+ * | | |0x02 = CFB (Cipher Feedback Mode).\r
+ * | | |0x03 = OFB (Output Feedback Mode).\r
+ * | | |0x04 = CTR (Counter Mode).\r
+ * | | |Others = CTR (Counter Mode).\r
+ * |[16] |ENCRPT |TDES/DES Encryption/Decryption\r
+ * | | |0 = TDES engine executes decryption operation.\r
+ * | | |1 = TDES engine executes encryption operation.\r
+ * |[21] |BLKSWAP |TDES/DES Engine Block Double Word Endian Swap\r
+ * | | |0 = Keep the original order, e.g. {WORD_H, WORD_L}.\r
+ * | | |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}.\r
+ * |[22] |OUTSWAP |TDES/DES Engine Output Data Swap\r
+ * | | |0 = Keep the original order.\r
+ * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.\r
+ * |[23] |INSWAP |TDES/DES Engine Input Data Swap\r
+ * | | |0 = Keep the original order.\r
+ * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.\r
+ * |[25:24] |CHANNEL |TDES/DES Engine Working Channel\r
+ * | | |00 = Current control register setting is for channel 0.\r
+ * | | |01 = Current control register setting is for channel 1.\r
+ * | | |10 = Current control register setting is for channel 2.\r
+ * | | |11 = Current control register setting is for channel 3.\r
+ * |[30:26] |KEYUNPRT |Unprotect Key\r
+ * | | |Writing 0 to CRPT_TDES_CTL [31] and ...10110 to CRPT_TDES_CTL [30:26] is to unprotect TDES key.\r
+ * | | |The KEYUNPRT can be read and written\r
+ * | | |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.\r
+ * |[31] |KEYPRT |Protect Key\r
+ * | | |Read as a flag to reflect KEYPRT.\r
+ * | | |0 = No effect.\r
+ * | | |1 = This bit is to protect the content of TDES key from reading\r
+ * | | |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L\r
+ * | | |Once it is set, it can be cleared by asserting KEYUNPRT\r
+ * | | |The key content would be cleared as well.\r
+ * @var CRPT_T::TDES_STS\r
+ * Offset: 0x204 TDES/DES Engine Flag\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BUSY |TDES/DES Engine Busy\r
+ * | | |0 = TDES/DES engine is idle or finished.\r
+ * | | |1 = TDES/DES engine is under processing.\r
+ * |[8] |INBUFEMPTY|TDES/DES in Buffer Empty\r
+ * | | |0 = There are some data in input buffer waiting for the TDES/DES engine to process.\r
+ * | | |1 = TDES/DES input buffer is empty\r
+ * | | |Software needs to feed data to the TDES/DES engine\r
+ * | | |Otherwise, the TDES/DES engine will be pending to wait for input data.\r
+ * |[9] |INBUFFULL |TDES/DES in Buffer Full Flag\r
+ * | | |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine.\r
+ * | | |1 = TDES input buffer is full\r
+ * | | |Software cannot feed data to the TDES/DES engine\r
+ * | | |Otherwise, the flag INBUFERR will be set to 1.\r
+ * |[10] |INBUFERR |TDES/DES in Buffer Error Flag\r
+ * | | |0 = No error.\r
+ * | | |1 = Error happens during feeding data to the TDES/DES engine.\r
+ * |[16] |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag\r
+ * | | |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer.\r
+ * | | |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT\r
+ * | | |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty.\r
+ * |[17] |OUTBUFFULL|TDES/DES Output Buffer Full Flag\r
+ * | | |0 = TDES/DES output buffer is not full.\r
+ * | | |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT\r
+ * | | |Otherwise, the TDES/DES engine will be pending since output buffer is full.\r
+ * |[18] |OUTBUFERR |TDES/DES Out Buffer Error Flag\r
+ * | | |0 = No error.\r
+ * | | |1 = Error happens during getting test result from TDES/DES engine.\r
+ * |[20] |BUSERR |TDES/DES DMA Access Bus Error Flag\r
+ * | | |0 = No error.\r
+ * | | |1 = Bus error will stop DMA operation and TDES/DES engine.\r
+ * @var CRPT_T::TDES0_KEY1H\r
+ * Offset: 0x208 TDES/DES Key 1 High Word Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES0_KEY1L\r
+ * Offset: 0x20C TDES/DES Key 1 Low Word Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES0_KEY2H\r
+ * Offset: 0x210 TDES Key 2 High Word Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES0_KEY2L\r
+ * Offset: 0x214 TDES Key 2 Low Word Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES0_KEY3H\r
+ * Offset: 0x218 TDES Key 3 High Word Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES0_KEY3L\r
+ * Offset: 0x21C TDES Key 3 Low Word Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES0_IVH\r
+ * Offset: 0x220 TDES/DES Initial Vector High Word Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |IV |TDES/DES Initial Vector High/Low Word\r
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode\r
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.\r
+ * @var CRPT_T::TDES0_IVL\r
+ * Offset: 0x224 TDES/DES Initial Vector Low Word Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |IV |TDES/DES Initial Vector High/Low Word\r
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode\r
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.\r
+ * @var CRPT_T::TDES0_SADDR\r
+ * Offset: 0x228 TDES/DES DMA Source Address Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SA |TDES/DES DMA Source Address\r
+ * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO\r
+ * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored\r
+ * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation\r
+ * | | |The start of source address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.\r
+ * | | |CRPT_TDESn_SA can be read and written\r
+ * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation\r
+ * | | |But the value of CRPT_TDESn_SA will be updated later on\r
+ * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.\r
+ * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.\r
+ * @var CRPT_T::TDES0_DADDR\r
+ * Offset: 0x22C TDES/DES DMA Destination Address Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DA |TDES/DES DMA Destination Address\r
+ * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO\r
+ * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored\r
+ * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished\r
+ * | | |The start of destination address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.\r
+ * | | |CRPT_TDESn_DA can be read and written\r
+ * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation\r
+ * | | |But the value of CRPT_TDESn_DA will be updated later on\r
+ * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.\r
+ * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.\r
+ * @var CRPT_T::TDES0_CNT\r
+ * Offset: 0x230 TDES/DES Byte Count Register for Channel 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNT |TDES/DES Byte Count\r
+ * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode\r
+ * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\r
+ * | | |CRPT_TDESn_CNT can be read and written\r
+ * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation\r
+ * | | |But the value of CRPT_TDESn_CNT will be updated later on\r
+ * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.\r
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.\r
+ * @var CRPT_T::TDES_DATIN\r
+ * Offset: 0x234 TDES/DES Engine Input data Word Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DATIN |TDES/DES Engine Input Port\r
+ * | | |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS\r
+ * | | |Feed data as INBUFFULL is 0.\r
+ * @var CRPT_T::TDES_DATOUT\r
+ * Offset: 0x238 TDES/DES Engine Output data Word Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DATOUT |TDES/DES Engine Output Port\r
+ * | | |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS\r
+ * | | |Get data as OUTBUFEMPTY is 0.\r
+ * @var CRPT_T::TDES1_KEY1H\r
+ * Offset: 0x248 TDES/DES Key 1 High Word Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES1_KEY1L\r
+ * Offset: 0x24C TDES/DES Key 1 Low Word Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES1_KEY2H\r
+ * Offset: 0x250 TDES Key 2 High Word Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES1_KEY2L\r
+ * Offset: 0x254 TDES Key 2 Low Word Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES1_KEY3H\r
+ * Offset: 0x258 TDES Key 3 High Word Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES1_KEY3L\r
+ * Offset: 0x25C TDES Key 3 Low Word Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES1_IVH\r
+ * Offset: 0x260 TDES/DES Initial Vector High Word Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |IV |TDES/DES Initial Vector High/Low Word\r
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode\r
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.\r
+ * @var CRPT_T::TDES1_IVL\r
+ * Offset: 0x264 TDES/DES Initial Vector Low Word Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |IV |TDES/DES Initial Vector High/Low Word\r
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode\r
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.\r
+ * @var CRPT_T::TDES1_SADDR\r
+ * Offset: 0x268 TDES/DES DMA Source Address Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SA |TDES/DES DMA Source Address\r
+ * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO\r
+ * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored\r
+ * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation\r
+ * | | |The start of source address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.\r
+ * | | |CRPT_TDESn_SA can be read and written\r
+ * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation\r
+ * | | |But the value of CRPT_TDESn_SA will be updated later on\r
+ * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.\r
+ * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.\r
+ * @var CRPT_T::TDES1_DADDR\r
+ * Offset: 0x26C TDES/DES DMA Destination Address Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DA |TDES/DES DMA Destination Address\r
+ * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO\r
+ * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored\r
+ * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished\r
+ * | | |The start of destination address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.\r
+ * | | |CRPT_TDESn_DA can be read and written\r
+ * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation\r
+ * | | |But the value of CRPT_TDESn_DA will be updated later on\r
+ * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.\r
+ * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.\r
+ * @var CRPT_T::TDES1_CNT\r
+ * Offset: 0x270 TDES/DES Byte Count Register for Channel 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNT |TDES/DES Byte Count\r
+ * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode\r
+ * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\r
+ * | | |CRPT_TDESn_CNT can be read and written\r
+ * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation\r
+ * | | |But the value of CRPT_TDESn_CNT will be updated later on\r
+ * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.\r
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.\r
+ * @var CRPT_T::TDES2_KEY1H\r
+ * Offset: 0x288 TDES/DES Key 1 High Word Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES2_KEY1L\r
+ * Offset: 0x28C TDES/DES Key 1 Low Word Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES2_KEY2H\r
+ * Offset: 0x290 TDES Key 2 High Word Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES2_KEY2L\r
+ * Offset: 0x294 TDES Key 2 Low Word Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES2_KEY3H\r
+ * Offset: 0x298 TDES Key 3 High Word Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES2_KEY3L\r
+ * Offset: 0x29C TDES Key 3 Low Word Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES2_IVH\r
+ * Offset: 0x2A0 TDES/DES Initial Vector High Word Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |IV |TDES/DES Initial Vector High/Low Word\r
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode\r
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.\r
+ * @var CRPT_T::TDES2_IVL\r
+ * Offset: 0x2A4 TDES/DES Initial Vector Low Word Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |IV |TDES/DES Initial Vector High/Low Word\r
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode\r
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.\r
+ * @var CRPT_T::TDES2_SADDR\r
+ * Offset: 0x2A8 TDES/DES DMA Source Address Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SA |TDES/DES DMA Source Address\r
+ * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO\r
+ * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored\r
+ * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation\r
+ * | | |The start of source address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.\r
+ * | | |CRPT_TDESn_SA can be read and written\r
+ * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation\r
+ * | | |But the value of CRPT_TDESn_SA will be updated later on\r
+ * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.\r
+ * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.\r
+ * @var CRPT_T::TDES2_DADDR\r
+ * Offset: 0x2AC TDES/DES DMA Destination Address Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DA |TDES/DES DMA Destination Address\r
+ * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO\r
+ * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored\r
+ * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished\r
+ * | | |The start of destination address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.\r
+ * | | |CRPT_TDESn_DA can be read and written\r
+ * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation\r
+ * | | |But the value of CRPT_TDESn_DA will be updated later on\r
+ * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.\r
+ * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.\r
+ * @var CRPT_T::TDES2_CNT\r
+ * Offset: 0x2B0 TDES/DES Byte Count Register for Channel 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNT |TDES/DES Byte Count\r
+ * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode\r
+ * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\r
+ * | | |CRPT_TDESn_CNT can be read and written\r
+ * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation\r
+ * | | |But the value of CRPT_TDESn_CNT will be updated later on\r
+ * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.\r
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.\r
+ * @var CRPT_T::TDES3_KEY1H\r
+ * Offset: 0x2C8 TDES/DES Key 1 High Word Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES3_KEY1L\r
+ * Offset: 0x2CC TDES/DES Key 1 Low Word Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES3_KEY2H\r
+ * Offset: 0x2D0 TDES Key 2 High Word Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES3_KEY2L\r
+ * Offset: 0x2D4 TDES Key 2 Low Word Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES3_KEY3H\r
+ * Offset: 0x2D8 TDES Key 3 High Word Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES3_KEY3L\r
+ * Offset: 0x2DC TDES Key 3 Low Word Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEY |TDES/DES Key High/Low Word\r
+ * | | |The key registers for TDES/DES algorithm calculation\r
+ * | | |The security key for the TDES/DES accelerator is 64 bits\r
+ * | | |Thus, it needs two 32-bit registers to store a security key\r
+ * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].\r
+ * @var CRPT_T::TDES3_IVH\r
+ * Offset: 0x2E0 TDES/DES Initial Vector High Word Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |IV |TDES/DES Initial Vector High/Low Word\r
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode\r
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.\r
+ * @var CRPT_T::TDES3_IVL\r
+ * Offset: 0x2E4 TDES/DES Initial Vector Low Word Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |IV |TDES/DES Initial Vector High/Low Word\r
+ * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode\r
+ * | | |IV is Nonce counter for TDES/DES engine in CTR mode.\r
+ * @var CRPT_T::TDES3_SADDR\r
+ * Offset: 0x2E8 TDES/DES DMA Source Address Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SA |TDES/DES DMA Source Address\r
+ * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO\r
+ * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored\r
+ * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation\r
+ * | | |The start of source address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.\r
+ * | | |CRPT_TDESn_SA can be read and written\r
+ * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation\r
+ * | | |But the value of CRPT_TDESn_SA will be updated later on\r
+ * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.\r
+ * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.\r
+ * @var CRPT_T::TDES3_DADDR\r
+ * Offset: 0x2EC TDES/DES DMA Destination Address Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DA |TDES/DES DMA Destination Address\r
+ * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO\r
+ * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored\r
+ * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished\r
+ * | | |The start of destination address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.\r
+ * | | |CRPT_TDESn_DA can be read and written\r
+ * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation\r
+ * | | |But the value of CRPT_TDESn_DA will be updated later on\r
+ * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.\r
+ * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.\r
+ * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.\r
+ * @var CRPT_T::TDES3_CNT\r
+ * Offset: 0x2F0 TDES/DES Byte Count Register for Channel 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNT |TDES/DES Byte Count\r
+ * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode\r
+ * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\r
+ * | | |CRPT_TDESn_CNT can be read and written\r
+ * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation\r
+ * | | |But the value of CRPT_TDESn_CNT will be updated later on\r
+ * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.\r
+ * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.\r
+ * @var CRPT_T::HMAC_CTL\r
+ * Offset: 0x300 SHA/HMAC Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |START |SHA/HMAC Engine Start\r
+ * | | |0 = No effect.\r
+ * | | |1 = Start SHA/HMAC engine. BUSY flag will be set.\r
+ * | | |This bit is always 0 when it's read back.\r
+ * |[1] |STOP |SHA/HMAC Engine Stop\r
+ * | | |0 = No effect.\r
+ * | | |1 = Stop SHA/HMAC engine.\r
+ * | | |This bit is always 0 when it's read back.\r
+ * |[5] |DMALAST |SHA/HMAC Last Block\r
+ * | | |This bit must be set as feeding in last byte of data.\r
+ * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Control\r
+ * | | |0 = SHA/HMAC DMA engine Disabled.\r
+ * | | |SHA/HMAC engine operates in Non-DMA mode, and gets data from the port CRPT_HMAC_DATIN.\r
+ * | | |1 = SHA/HMAC DMA engine Enabled.\r
+ * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.\r
+ * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes\r
+ * | | |0x0xx: SHA160\r
+ * | | |0x100: SHA256\r
+ * | | |0x101: SHA224\r
+ * | | |0x110: SHA512\r
+ * | | |0x111: SHA384\r
+ * | | |These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1.\r
+ * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap\r
+ * | | |0 = Keep the original order.\r
+ * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.\r
+ * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap\r
+ * | | |0 = Keep the original order.\r
+ * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.\r
+ * @var CRPT_T::HMAC_STS\r
+ * Offset: 0x304 SHA/HMAC Status Flag\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BUSY |SHA/HMAC Engine Busy\r
+ * | | |0 = SHA/HMAC engine is idle or finished.\r
+ * | | |1 = SHA/HMAC engine is busy.\r
+ * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag\r
+ * | | |0 = SHA/HMAC DMA engine is idle or finished.\r
+ * | | |1 = SHA/HMAC DMA engine is busy.\r
+ * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag\r
+ * | | |0 = Show the SHA/HMAC engine access normal.\r
+ * | | |1 = Show the SHA/HMAC engine access error.\r
+ * |[16] |DATINREQ |SHA/HMAC Non-DMA Mode Data Input Request\r
+ * | | |0 = No effect.\r
+ * | | |1 = Request SHA/HMAC Non-DMA mode data input.\r
+ * @var CRPT_T::HMAC_DGST[16]\r
+ * Offset: 0x308~0x344 SHA/HMAC Digest Message 0~15\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DGST |SHA/HMAC Digest Message Output Register\r
+ * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4.\r
+ * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6.\r
+ * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7.\r
+ * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11.\r
+ * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15.\r
+ * @var CRPT_T::HMAC_KEYCNT\r
+ * Offset: 0x348 SHA/HMAC Key Byte Count Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count\r
+ * | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates\r
+ * | | |The register is 32-bit and the maximum byte count is 4G bytes\r
+ * | | |It can be read and written.\r
+ * | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation\r
+ * | | |But the value of CRPT_SHA _KEYCNT will be updated later on\r
+ * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation.\r
+ * @var CRPT_T::HMAC_SADDR\r
+ * Offset: 0x34C SHA/HMAC DMA Source Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SADDR |SHA/HMAC DMA Source Address\r
+ * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO\r
+ * | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored\r
+ * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from system memory and do SHA/HMAC operation\r
+ * | | |The start of source address should be located at word boundary\r
+ * | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored.\r
+ * | | |CRPT_HMAC_SADDR can be read and written\r
+ * | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation\r
+ * | | |But the value of CRPT_HMAC_SADDR will be updated later on\r
+ * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation.\r
+ * | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START.\r
+ * | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value.\r
+ * @var CRPT_T::HMAC_DMACNT\r
+ * Offset: 0x350 SHA/HMAC Byte Count Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count\r
+ * | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode\r
+ * | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes.\r
+ * | | |CRPT_HMAC_DMACNT can be read and written\r
+ * | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation\r
+ * | | |But the value of CRPT_HMAC_DMACNT will be updated later on\r
+ * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation.\r
+ * | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data.\r
+ * @var CRPT_T::HMAC_DATIN\r
+ * Offset: 0x354 SHA/HMAC Engine Non-DMA Mode Data Input Port Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DATIN |SHA/HMAC Engine Input Port\r
+ * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS\r
+ * | | |Feed data as DATINREQ is 1.\r
+ * @var CRPT_T::ECC_CTL\r
+ * Offset: 0x800 ECC Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |START |ECC Accelerator Start\r
+ * | | |0 = No effect.\r
+ * | | |1 = Start ECC accelerator. BUSY flag will be set.\r
+ * | | |This bit is always 0 when it's read back.\r
+ * | | |ECC accelerator will ignore this START signal when BUSY flag is 1.\r
+ * |[1] |STOP |ECC Accelerator Stop\r
+ * | | |0 = No effect.\r
+ * | | |1 = Abort ECC accelerator and make it into idle state.\r
+ * | | |This bit is always 0 when it's read back.\r
+ * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator.\r
+ * |[7] |DMAEN |ECC Accelerator DMA Enable Control\r
+ * | | |0 = ECC DMA engine Disabled.\r
+ * | | |1 = ECC DMA engine Enabled.\r
+ * | | |Only when START and DMAEN are 1, ECC DMA engine will be active\r
+ * |[8] |FSEL |Field Selection\r
+ * | | |0 = Binary Field (GF(2m )).\r
+ * | | |1 = Prime Field (GF(p)).\r
+ * |[10:9] |ECCOP |Point Operation for BF and PF\r
+ * | | |00 = Point multiplication :\r
+ * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1).\r
+ * | | |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]).\r
+ * | | |10 = Point addition :\r
+ * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +.\r
+ * | | |(POINTX2, POINTY2)\r
+ * | | |11 = Point doubling :\r
+ * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1).\r
+ * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11\r
+ * |[12:11] |MODOP |Modulus Operation for PF\r
+ * | | |00 = Division :\r
+ * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN.\r
+ * | | |01 = Multiplication :\r
+ * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN.\r
+ * | | |10 = Addition :\r
+ * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN.\r
+ * | | |11 = Subtraction :\r
+ * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN.\r
+ * | | |MODOP is active only when ECCOP = 01.\r
+ * |[16] |LDP1 |The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1)\r
+ * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user.\r
+ * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user.\r
+ * |[17] |LDP2 |The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2)\r
+ * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user.\r
+ * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user.\r
+ * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve\r
+ * | | |0 = The register for CURVEA is not modified by DMA or user.\r
+ * | | |1 = The register for CURVEA is modified by DMA or user.\r
+ * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve\r
+ * | | |0 = The register for CURVEB is not modified by DMA or user.\r
+ * | | |1 = The register for CURVEB is modified by DMA or user.\r
+ * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve\r
+ * | | |0 = The register for CURVEN is not modified by DMA or user.\r
+ * | | |1 = The register for CURVEN is modified by DMA or user.\r
+ * |[21] |LDK |The Control Signal of Register for SCALARK\r
+ * | | |0 = The register for SCALARK is not modified by DMA or user.\r
+ * | | |1 = The register for SCALARK is modified by DMA or user.\r
+ * |[31:22] |CURVEM |The key length of elliptic curve.\r
+ * @var CRPT_T::ECC_STS\r
+ * Offset: 0x804 ECC Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BUSY |ECC Accelerator Busy Flag\r
+ * | | |0 = The ECC accelerator is idle or finished.\r
+ * | | |1 = The ECC accelerator is under processing and protects all registers.\r
+ * | | |Remember to clear ECC interrupt flag after ECC accelerator finished\r
+ * |[1] |DMABUSY |ECC DMA Busy Flag\r
+ * | | |0 = ECC DMA is idle or finished.\r
+ * | | |1 = ECC DMA is busy.\r
+ * |[16] |BUSERR |ECC DMA Access Bus Error Flag\r
+ * | | |0 = No error.\r
+ * | | |1 = Bus error will stop DMA operation and ECC accelerator.\r
+ * @var CRPT_T::ECC_X1[18]\r
+ * Offset: 0x808~0x84C ECC The X-coordinate word 0~17 of the first point\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |POINTX1 |ECC the x-coordinate Value of the First Point (POINTX1)\r
+ * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05\r
+ * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07\r
+ * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08\r
+ * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12\r
+ * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17\r
+ * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05\r
+ * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06\r
+ * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07\r
+ * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11\r
+ * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16\r
+ * @var CRPT_T::ECC_Y1[18]\r
+ * Offset: 0x850~0x894 ECC The Y-coordinate word 0~17 of the first point\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point (POINTY1)\r
+ * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05\r
+ * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07\r
+ * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08\r
+ * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12\r
+ * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17\r
+ * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05\r
+ * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06\r
+ * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07\r
+ * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11\r
+ * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16\r
+ * @var CRPT_T::ECC_X2[18]\r
+ * Offset: 0x898~0x8DC ECC The X-coordinate word 0~17 of the second point\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |POINTX2 |ECC the x-coordinate Value of the Second Point (POINTX2)\r
+ * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05\r
+ * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07\r
+ * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08\r
+ * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12\r
+ * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17\r
+ * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05\r
+ * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06\r
+ * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07\r
+ * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11\r
+ * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16\r
+ * @var CRPT_T::ECC_Y2[18]\r
+ * Offset: 0x8E0~0x924 ECC The Y-coordinate word 0~17 of the second point\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point (POINTY2)\r
+ * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05\r
+ * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07\r
+ * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08\r
+ * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12\r
+ * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17\r
+ * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05\r
+ * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06\r
+ * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07\r
+ * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11\r
+ * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16\r
+ * @var CRPT_T::ECC_A[18]\r
+ * Offset: 0x928~0x96C ECC The parameter CURVEA word 0~17 of elliptic curve\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\r
+ * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m).\r
+ * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05\r
+ * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07\r
+ * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08\r
+ * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12\r
+ * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17\r
+ * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05\r
+ * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06\r
+ * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07\r
+ * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11\r
+ * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16\r
+ * @var CRPT_T::ECC_B[18]\r
+ * Offset: 0x970~0x9B4 ECC The parameter CURVEB word 0~17 of elliptic curve\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\r
+ * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m).\r
+ * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05\r
+ * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07\r
+ * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08\r
+ * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12\r
+ * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17\r
+ * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05\r
+ * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06\r
+ * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07\r
+ * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11\r
+ * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16\r
+ * @var CRPT_T::ECC_N[18]\r
+ * Offset: 0x9B8~0x9FC ECC The parameter CURVEN word 0~17 of elliptic curve\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\r
+ * | | |In GF(p), CURVEN is the prime p.\r
+ * | | |In GF(2m), CURVEN is the irreducible polynomial.\r
+ * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05\r
+ * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07\r
+ * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08\r
+ * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12\r
+ * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17\r
+ * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05\r
+ * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06\r
+ * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07\r
+ * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11\r
+ * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16\r
+ * @var CRPT_T::ECC_K[18]\r
+ * Offset: 0xA00~0xA44 ECC The scalar SCALARK word 0~17 of point multiplication\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\r
+ * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK.\r
+ * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05\r
+ * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07\r
+ * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08\r
+ * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12\r
+ * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17\r
+ * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05\r
+ * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06\r
+ * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07\r
+ * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11\r
+ * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16\r
+ * @var CRPT_T::ECC_SADDR\r
+ * Offset: 0xA48 ECC DMA Source Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * @var CRPT_T::ECC_DADDR\r
+ * Offset: 0xA4C ECC DMA Destination Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DADDR |ECC DMA Destination Address\r
+ * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between system memory and ECC accelerator\r
+ * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored\r
+ * | | |Based on the destination address, the ECC accelerator can write the result data back to system memory after the ECC operation is finished\r
+ * | | |The start of destination address should be located at word boundary\r
+ * | | |That is, bit 1 and 0 of DADDR are ignored\r
+ * | | |DADDR can be read and written\r
+ * | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START\r
+ * @var CRPT_T::ECC_STARTREG\r
+ * Offset: 0xA50 ECC Starting Address of Updated Registers\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |STARTREG |ECC Starting Address of Updated Registers\r
+ * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine\r
+ * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG\r
+ * | | |For example, we want to updated input data from register CRPT_ECC POINTX1\r
+ * | | |Thus, the value of STARTREG is 0x808.\r
+ * @var CRPT_T::ECC_WORDCNT\r
+ * Offset: 0xA54 ECC DMA Word Count\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |WORDCNT |ECC DMA Word Count\r
+ * | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode\r
+ * | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words\r
+ * | | |CRPT_ECC_WORDCNT can be read and written\r
+ */\r
+ __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */\r
+ __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */\r
+ __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */\r
+ __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */\r
+ __I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */\r
+ __I uint32_t RESERVE0[8];\r
+ __I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */\r
+ __I uint32_t TDES_FDBCKH; /*!< [0x0060] TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */\r
+ __I uint32_t TDES_FDBCKL; /*!< [0x0064] TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation */\r
+ __I uint32_t RESERVE1[38];\r
+ __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */\r
+ __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */\r
+ __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */\r
+ __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */\r
+ __IO uint32_t AES0_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */\r
+ __IO uint32_t AES0_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */\r
+ __IO uint32_t AES0_SADDR; /*!< [0x0140] AES DMA Source Address Register for Channel 0 */\r
+ __IO uint32_t AES0_DADDR; /*!< [0x0144] AES DMA Destination Address Register for Channel 0 */\r
+ __IO uint32_t AES0_CNT; /*!< [0x0148] AES Byte Count Register for Channel 0 */\r
+ __IO uint32_t AES1_KEY[8]; /*!< [0x014c] ~ [0x0168] AES Key Word 0~7 Register for Channel 1 */\r
+ __IO uint32_t AES1_IV[4]; /*!< [0x016c] ~ [0x0178] AES Initial Vector Word 0~3 Register for Channel 1 */\r
+ __IO uint32_t AES1_SADDR; /*!< [0x017c] AES DMA Source Address Register for Channel 1 */\r
+ __IO uint32_t AES1_DADDR; /*!< [0x0180] AES DMA Destination Address Register for Channel 1 */\r
+ __IO uint32_t AES1_CNT; /*!< [0x0184] AES Byte Count Register for Channel 1 */\r
+ __IO uint32_t AES2_KEY[8]; /*!< [0x0188] ~ [0x01a4] AES Key Word 0~7 Register for Channel 2 */\r
+ __IO uint32_t AES2_IV[4]; /*!< [0x01a8] ~ [0x01b4] AES Initial Vector Word 0~3 Register for Channel 2 */\r
+ __IO uint32_t AES2_SADDR; /*!< [0x01b8] AES DMA Source Address Register for Channel 2 */\r
+ __IO uint32_t AES2_DADDR; /*!< [0x01bc] AES DMA Destination Address Register for Channel 2 */\r
+ __IO uint32_t AES2_CNT; /*!< [0x01c0] AES Byte Count Register for Channel 2 */\r
+ __IO uint32_t AES3_KEY[8]; /*!< [0x01c4] ~ [0x01e0] AES Key Word 0~7 Register for Channel 3 */\r
+ __IO uint32_t AES3_IV[4]; /*!< [0x01e4] ~ [0x01f0] AES Initial Vector Word 0~3 Register for Channel 3 */\r
+ __IO uint32_t AES3_SADDR; /*!< [0x01f4] AES DMA Source Address Register for Channel 3 */\r
+ __IO uint32_t AES3_DADDR; /*!< [0x01f8] AES DMA Destination Address Register for Channel 3 */\r
+ __IO uint32_t AES3_CNT; /*!< [0x01fc] AES Byte Count Register for Channel 3 */\r
+ __IO uint32_t TDES_CTL; /*!< [0x0200] TDES/DES Control Register */\r
+ __I uint32_t TDES_STS; /*!< [0x0204] TDES/DES Engine Flag */\r
+ __IO uint32_t TDES0_KEY1H; /*!< [0x0208] TDES/DES Key 1 High Word Register for Channel 0 */\r
+ __IO uint32_t TDES0_KEY1L; /*!< [0x020c] TDES/DES Key 1 Low Word Register for Channel 0 */\r
+ __IO uint32_t TDES0_KEY2H; /*!< [0x0210] TDES Key 2 High Word Register for Channel 0 */\r
+ __IO uint32_t TDES0_KEY2L; /*!< [0x0214] TDES Key 2 Low Word Register for Channel 0 */\r
+ __IO uint32_t TDES0_KEY3H; /*!< [0x0218] TDES Key 3 High Word Register for Channel 0 */\r
+ __IO uint32_t TDES0_KEY3L; /*!< [0x021c] TDES Key 3 Low Word Register for Channel 0 */\r
+ __IO uint32_t TDES0_IVH; /*!< [0x0220] TDES/DES Initial Vector High Word Register for Channel 0 */\r
+ __IO uint32_t TDES0_IVL; /*!< [0x0224] TDES/DES Initial Vector Low Word Register for Channel 0 */\r
+ __IO uint32_t TDES0_SADDR; /*!< [0x0228] TDES/DES DMA Source Address Register for Channel 0 */\r
+ __IO uint32_t TDES0_DADDR; /*!< [0x022c] TDES/DES DMA Destination Address Register for Channel 0 */\r
+ __IO uint32_t TDES0_CNT; /*!< [0x0230] TDES/DES Byte Count Register for Channel 0 */\r
+ __IO uint32_t TDES_DATIN; /*!< [0x0234] TDES/DES Engine Input data Word Register */\r
+ __I uint32_t TDES_DATOUT; /*!< [0x0238] TDES/DES Engine Output data Word Register */\r
+ __I uint32_t RESERVE2[3];\r
+ __IO uint32_t TDES1_KEY1H; /*!< [0x0248] TDES/DES Key 1 High Word Register for Channel 1 */\r
+ __IO uint32_t TDES1_KEY1L; /*!< [0x024c] TDES/DES Key 1 Low Word Register for Channel 1 */\r
+ __IO uint32_t TDES1_KEY2H; /*!< [0x0250] TDES Key 2 High Word Register for Channel 1 */\r
+ __IO uint32_t TDES1_KEY2L; /*!< [0x0254] TDES Key 2 Low Word Register for Channel 1 */\r
+ __IO uint32_t TDES1_KEY3H; /*!< [0x0258] TDES Key 3 High Word Register for Channel 1 */\r
+ __IO uint32_t TDES1_KEY3L; /*!< [0x025c] TDES Key 3 Low Word Register for Channel 1 */\r
+ __IO uint32_t TDES1_IVH; /*!< [0x0260] TDES/DES Initial Vector High Word Register for Channel 1 */\r
+ __IO uint32_t TDES1_IVL; /*!< [0x0264] TDES/DES Initial Vector Low Word Register for Channel 1 */\r
+ __IO uint32_t TDES1_SADDR; /*!< [0x0268] TDES/DES DMA Source Address Register for Channel 1 */\r
+ __IO uint32_t TDES1_DADDR; /*!< [0x026c] TDES/DES DMA Destination Address Register for Channel 1 */\r
+ __IO uint32_t TDES1_CNT; /*!< [0x0270] TDES/DES Byte Count Register for Channel 1 */\r
+ __I uint32_t RESERVE3[5];\r
+ __IO uint32_t TDES2_KEY1H; /*!< [0x0288] TDES/DES Key 1 High Word Register for Channel 2 */\r
+ __IO uint32_t TDES2_KEY1L; /*!< [0x028c] TDES/DES Key 1 Low Word Register for Channel 2 */\r
+ __IO uint32_t TDES2_KEY2H; /*!< [0x0290] TDES Key 2 High Word Register for Channel 2 */\r
+ __IO uint32_t TDES2_KEY2L; /*!< [0x0294] TDES Key 2 Low Word Register for Channel 2 */\r
+ __IO uint32_t TDES2_KEY3H; /*!< [0x0298] TDES Key 3 High Word Register for Channel 2 */\r
+ __IO uint32_t TDES2_KEY3L; /*!< [0x029c] TDES Key 3 Low Word Register for Channel 2 */\r
+ __IO uint32_t TDES2_IVH; /*!< [0x02a0] TDES/DES Initial Vector High Word Register for Channel 2 */\r
+ __IO uint32_t TDES2_IVL; /*!< [0x02a4] TDES/DES Initial Vector Low Word Register for Channel 2 */\r
+ __IO uint32_t TDES2_SADDR; /*!< [0x02a8] TDES/DES DMA Source Address Register for Channel 2 */\r
+ __IO uint32_t TDES2_DADDR; /*!< [0x02ac] TDES/DES DMA Destination Address Register for Channel 2 */\r
+ __IO uint32_t TDES2_CNT; /*!< [0x02b0] TDES/DES Byte Count Register for Channel 2 */\r
+ __I uint32_t RESERVE4[5];\r
+ __IO uint32_t TDES3_KEY1H; /*!< [0x02c8] TDES/DES Key 1 High Word Register for Channel 3 */\r
+ __IO uint32_t TDES3_KEY1L; /*!< [0x02cc] TDES/DES Key 1 Low Word Register for Channel 3 */\r
+ __IO uint32_t TDES3_KEY2H; /*!< [0x02d0] TDES Key 2 High Word Register for Channel 3 */\r
+ __IO uint32_t TDES3_KEY2L; /*!< [0x02d4] TDES Key 2 Low Word Register for Channel 3 */\r
+ __IO uint32_t TDES3_KEY3H; /*!< [0x02d8] TDES Key 3 High Word Register for Channel 3 */\r
+ __IO uint32_t TDES3_KEY3L; /*!< [0x02dc] TDES Key 3 Low Word Register for Channel 3 */\r
+ __IO uint32_t TDES3_IVH; /*!< [0x02e0] TDES/DES Initial Vector High Word Register for Channel 3 */\r
+ __IO uint32_t TDES3_IVL; /*!< [0x02e4] TDES/DES Initial Vector Low Word Register for Channel 3 */\r
+ __IO uint32_t TDES3_SADDR; /*!< [0x02e8] TDES/DES DMA Source Address Register for Channel 3 */\r
+ __IO uint32_t TDES3_DADDR; /*!< [0x02ec] TDES/DES DMA Destination Address Register for Channel 3 */\r
+ __IO uint32_t TDES3_CNT; /*!< [0x02f0] TDES/DES Byte Count Register for Channel 3 */\r
+ __I uint32_t RESERVE5[3];\r
+ __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */\r
+ __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */\r
+ __I uint32_t HMAC_DGST[16]; /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15 */\r
+ __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */\r
+ __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */\r
+ __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */\r
+ __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register */\r
+ __I uint32_t RESERVE6[298];\r
+ __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */\r
+ __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */\r
+ __IO uint32_t ECC_X1[18]; /*!< [0x0808] ~ [0x084c] ECC The X-coordinate word 0~17 of the first point */\r
+ __IO uint32_t ECC_Y1[18]; /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point */\r
+ __IO uint32_t ECC_X2[18]; /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point */\r
+ __IO uint32_t ECC_Y2[18]; /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point */\r
+ __IO uint32_t ECC_A[18]; /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve */\r
+ __IO uint32_t ECC_B[18]; /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve */\r
+ __IO uint32_t ECC_N[18]; /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve */\r
+ __O uint32_t ECC_K[18]; /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */\r
+ __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */\r
+ __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */\r
+ __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */\r
+ __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */\r
+\r
+} CRPT_T;\r
+\r
+/**\r
+ @addtogroup CRPT_CONST CRPT Bit Field Definition\r
+ Constant Definitions for CRPT Controller\r
+@{ */\r
+\r
+#define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */\r
+#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */\r
+\r
+#define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */\r
+#define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */\r
+\r
+#define CRPT_INTEN_TDESIEN_Pos (8) /*!< CRPT_T::INTEN: TDESIEN Position */\r
+#define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) /*!< CRPT_T::INTEN: TDESIEN Mask */\r
+\r
+#define CRPT_INTEN_TDESEIEN_Pos (9) /*!< CRPT_T::INTEN: TDESEIEN Position */\r
+#define CRPT_INTEN_TDESEIEN_Msk (0x1ul << CRPT_INTEN_TDESEIEN_Pos) /*!< CRPT_T::INTEN: TDESEIEN Mask */\r
+\r
+#define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */\r
+#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */\r
+\r
+#define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */\r
+#define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */\r
+\r
+#define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */\r
+#define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */\r
+\r
+#define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */\r
+#define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */\r
+\r
+#define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */\r
+#define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */\r
+\r
+#define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */\r
+#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */\r
+\r
+#define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */\r
+#define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */\r
+\r
+#define CRPT_INTSTS_TDESIF_Pos (8) /*!< CRPT_T::INTSTS: TDESIF Position */\r
+#define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) /*!< CRPT_T::INTSTS: TDESIF Mask */\r
+\r
+#define CRPT_INTSTS_TDESEIF_Pos (9) /*!< CRPT_T::INTSTS: TDESEIF Position */\r
+#define CRPT_INTSTS_TDESEIF_Msk (0x1ul << CRPT_INTSTS_TDESEIF_Pos) /*!< CRPT_T::INTSTS: TDESEIF Mask */\r
+\r
+#define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */\r
+#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */\r
+\r
+#define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */\r
+#define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */\r
+\r
+#define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */\r
+#define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */\r
+\r
+#define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */\r
+#define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */\r
+\r
+#define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */\r
+#define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */\r
+\r
+#define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */\r
+#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */\r
+\r
+#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */\r
+#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */\r
+\r
+#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */\r
+#define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */\r
+\r
+#define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */\r
+#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */\r
+\r
+#define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */\r
+#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */\r
+\r
+#define CRPT_PRNG_KEYx_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY[8]: KEY Position */\r
+#define CRPT_PRNG_KEYx_KEY_Msk (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos) /*!< CRPT_T::PRNG_KEY[8]: KEY Mask */\r
+\r
+#define CRPT_AES_FDBCKx_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position */\r
+#define CRPT_AES_FDBCKx_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask */\r
+\r
+#define CRPT_TDES_FDBCKH_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKH: FDBCK Position */\r
+#define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKH: FDBCK Mask */\r
+\r
+#define CRPT_TDES_FDBCKL_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKL: FDBCK Position */\r
+#define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKL: FDBCK Mask */\r
+\r
+#define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */\r
+#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */\r
+\r
+#define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */\r
+#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */\r
+\r
+#define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */\r
+#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */\r
+\r
+#define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */\r
+#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */\r
+\r
+#define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */\r
+#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */\r
+\r
+#define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */\r
+#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */\r
+\r
+#define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */\r
+#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */\r
+\r
+#define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRPT Position */\r
+#define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRPT Mask */\r
+\r
+#define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */\r
+#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */\r
+\r
+#define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */\r
+#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */\r
+\r
+#define CRPT_AES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::AES_CTL: CHANNEL Position */\r
+#define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) /*!< CRPT_T::AES_CTL: CHANNEL Mask */\r
+\r
+#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */\r
+#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */\r
+\r
+#define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */\r
+#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */\r
+\r
+#define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */\r
+#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */\r
+\r
+#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */\r
+#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */\r
+\r
+#define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */\r
+#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */\r
+\r
+#define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */\r
+#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */\r
+\r
+#define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */\r
+#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */\r
+\r
+#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position */\r
+#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */\r
+\r
+#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */\r
+#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */\r
+\r
+#define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */\r
+#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */\r
+\r
+#define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */\r
+#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */\r
+\r
+#define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */\r
+#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */\r
+\r
+#define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */\r
+#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */\r
+\r
+#define CRPT_AES0_KEYx_KEY_Pos (0) /*!< CRPT_T::AES0_KEY[8]: KEY Position */\r
+#define CRPT_AES0_KEYx_KEY_Msk (0xfffffffful << CRPT_AES0_KEYx_KEY_Pos) /*!< CRPT_T::AES0_KEY[8]: KEY Mask */\r
+\r
+#define CRPT_AES0_IVx_IV_Pos (0) /*!< CRPT_T::AES0_IV[4]: IV Position */\r
+#define CRPT_AES0_IVx_IV_Msk (0xfffffffful << CRPT_AES0_IVx_IV_Pos) /*!< CRPT_T::AES0_IV[4]: IV Mask */\r
+\r
+#define CRPT_AES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES0_SADDR: SADDR Position */\r
+#define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) /*!< CRPT_T::AES0_SADDR: SADDR Mask */\r
+\r
+#define CRPT_AES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES0_DADDR: DADDR Position */\r
+#define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) /*!< CRPT_T::AES0_DADDR: DADDR Mask */\r
+\r
+#define CRPT_AES0_CNT_CNT_Pos (0) /*!< CRPT_T::AES0_CNT: CNT Position */\r
+#define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) /*!< CRPT_T::AES0_CNT: CNT Mask */\r
+\r
+#define CRPT_AES1_KEYx_KEY_Pos (0) /*!< CRPT_T::AES1_KEY[8]: KEY Position */\r
+#define CRPT_AES1_KEYx_KEY_Msk (0xfffffffful << CRPT_AES1_KEYx_KEY_Pos) /*!< CRPT_T::AES1_KEY[8]: KEY Mask */\r
+\r
+#define CRPT_AES1_IVx_IV_Pos (0) /*!< CRPT_T::AES1_IV[4]: IV Position */\r
+#define CRPT_AES1_IVx_IV_Msk (0xfffffffful << CRPT_AES1_IVx_IV_Pos) /*!< CRPT_T::AES1_IV[4]: IV Mask */\r
+\r
+#define CRPT_AES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES1_SADDR: SADDR Position */\r
+#define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) /*!< CRPT_T::AES1_SADDR: SADDR Mask */\r
+\r
+#define CRPT_AES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES1_DADDR: DADDR Position */\r
+#define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) /*!< CRPT_T::AES1_DADDR: DADDR Mask */\r
+\r
+#define CRPT_AES1_CNT_CNT_Pos (0) /*!< CRPT_T::AES1_CNT: CNT Position */\r
+#define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) /*!< CRPT_T::AES1_CNT: CNT Mask */\r
+\r
+#define CRPT_AES2_KEYx_KEY_Pos (0) /*!< CRPT_T::AES2_KEYx: KEY Position */\r
+#define CRPT_AES2_KEYx_KEY_Msk (0xfffffffful << CRPT_AES2_KEYx_KEY_Pos) /*!< CRPT_T::AES2_KEYx: KEY Mask */\r
+\r
+#define CRPT_AES2_IVx_IV_Pos (0) /*!< CRPT_T::AES2_IVx: IV Position */\r
+#define CRPT_AES2_IVx_IV_Msk (0xfffffffful << CRPT_AES2_IVx_IV_Pos) /*!< CRPT_T::AES2_IVx: IV Mask */\r
+\r
+#define CRPT_AES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES2_SADDR: SADDR Position */\r
+#define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) /*!< CRPT_T::AES2_SADDR: SADDR Mask */\r
+\r
+#define CRPT_AES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES2_DADDR: DADDR Position */\r
+#define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) /*!< CRPT_T::AES2_DADDR: DADDR Mask */\r
+\r
+#define CRPT_AES2_CNT_CNT_Pos (0) /*!< CRPT_T::AES2_CNT: CNT Position */\r
+#define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) /*!< CRPT_T::AES2_CNT: CNT Mask */\r
+\r
+#define CRPT_AES3_KEYx_KEY_Pos (0) /*!< CRPT_T::AES3_KEY[8]: KEY Position */\r
+#define CRPT_AES3_KEYx_KEY_Msk (0xfffffffful << CRPT_AES3_KEYx_KEY_Pos) /*!< CRPT_T::AES3_KEY[8]: KEY Mask */\r
+\r
+#define CRPT_AES3_IVx_IV_Pos (0) /*!< CRPT_T::AES3_IV[4]: IV Position */\r
+#define CRPT_AES3_IVx_IV_Msk (0xfffffffful << CRPT_AES3_IVx_IV_Pos) /*!< CRPT_T::AES3_IV[4]: IV Mask */\r
+\r
+#define CRPT_AES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES3_SADDR: SADDR Position */\r
+#define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) /*!< CRPT_T::AES3_SADDR: SADDR Mask */\r
+\r
+#define CRPT_AES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES3_DADDR: DADDR Position */\r
+#define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) /*!< CRPT_T::AES3_DADDR: DADDR Mask */\r
+\r
+#define CRPT_AES3_CNT_CNT_Pos (0) /*!< CRPT_T::AES3_CNT: CNT Position */\r
+#define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) /*!< CRPT_T::AES3_CNT: CNT Mask */\r
+\r
+#define CRPT_TDES_CTL_START_Pos (0) /*!< CRPT_T::TDES_CTL: START Position */\r
+#define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) /*!< CRPT_T::TDES_CTL: START Mask */\r
+\r
+#define CRPT_TDES_CTL_STOP_Pos (1) /*!< CRPT_T::TDES_CTL: STOP Position */\r
+#define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) /*!< CRPT_T::TDES_CTL: STOP Mask */\r
+\r
+#define CRPT_TDES_CTL_TMODE_Pos (2) /*!< CRPT_T::TDES_CTL: TMODE Position */\r
+#define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) /*!< CRPT_T::TDES_CTL: TMODE Mask */\r
+\r
+#define CRPT_TDES_CTL_3KEYS_Pos (3) /*!< CRPT_T::TDES_CTL: 3KEYS Position */\r
+#define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) /*!< CRPT_T::TDES_CTL: 3KEYS Mask */\r
+\r
+#define CRPT_TDES_CTL_DMALAST_Pos (5) /*!< CRPT_T::TDES_CTL: DMALAST Position */\r
+#define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) /*!< CRPT_T::TDES_CTL: DMALAST Mask */\r
+\r
+#define CRPT_TDES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::TDES_CTL: DMACSCAD Position */\r
+#define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) /*!< CRPT_T::TDES_CTL: DMACSCAD Mask */\r
+\r
+#define CRPT_TDES_CTL_DMAEN_Pos (7) /*!< CRPT_T::TDES_CTL: DMAEN Position */\r
+#define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) /*!< CRPT_T::TDES_CTL: DMAEN Mask */\r
+\r
+#define CRPT_TDES_CTL_OPMODE_Pos (8) /*!< CRPT_T::TDES_CTL: OPMODE Position */\r
+#define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) /*!< CRPT_T::TDES_CTL: OPMODE Mask */\r
+\r
+#define CRPT_TDES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::TDES_CTL: ENCRPT Position */\r
+#define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) /*!< CRPT_T::TDES_CTL: ENCRPT Mask */\r
+\r
+#define CRPT_TDES_CTL_BLKSWAP_Pos (21) /*!< CRPT_T::TDES_CTL: BLKSWAP Position */\r
+#define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) /*!< CRPT_T::TDES_CTL: BLKSWAP Mask */\r
+\r
+#define CRPT_TDES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::TDES_CTL: OUTSWAP Position */\r
+#define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) /*!< CRPT_T::TDES_CTL: OUTSWAP Mask */\r
+\r
+#define CRPT_TDES_CTL_INSWAP_Pos (23) /*!< CRPT_T::TDES_CTL: INSWAP Position */\r
+#define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) /*!< CRPT_T::TDES_CTL: INSWAP Mask */\r
+\r
+#define CRPT_TDES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::TDES_CTL: CHANNEL Position */\r
+#define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) /*!< CRPT_T::TDES_CTL: CHANNEL Mask */\r
+\r
+#define CRPT_TDES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::TDES_CTL: KEYUNPRT Position */\r
+#define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYUNPRT Mask */\r
+\r
+#define CRPT_TDES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::TDES_CTL: KEYPRT Position */\r
+#define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYPRT Mask */\r
+\r
+#define CRPT_TDES_STS_BUSY_Pos (0) /*!< CRPT_T::TDES_STS: BUSY Position */\r
+#define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) /*!< CRPT_T::TDES_STS: BUSY Mask */\r
+\r
+#define CRPT_TDES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::TDES_STS: INBUFEMPTY Position */\r
+#define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: INBUFEMPTY Mask */\r
+\r
+#define CRPT_TDES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::TDES_STS: INBUFFULL Position */\r
+#define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) /*!< CRPT_T::TDES_STS: INBUFFULL Mask */\r
+\r
+#define CRPT_TDES_STS_INBUFERR_Pos (10) /*!< CRPT_T::TDES_STS: INBUFERR Position */\r
+#define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) /*!< CRPT_T::TDES_STS: INBUFERR Mask */\r
+\r
+#define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Position */\r
+#define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Mask */\r
+\r
+#define CRPT_TDES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::TDES_STS: OUTBUFFULL Position */\r
+#define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::TDES_STS: OUTBUFFULL Mask */\r
+\r
+#define CRPT_TDES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::TDES_STS: OUTBUFERR Position */\r
+#define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) /*!< CRPT_T::TDES_STS: OUTBUFERR Mask */\r
+\r
+#define CRPT_TDES_STS_BUSERR_Pos (20) /*!< CRPT_T::TDES_STS: BUSERR Position */\r
+#define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) /*!< CRPT_T::TDES_STS: BUSERR Mask */\r
+\r
+#define CRPT_TDES0_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxH: KEY Position */\r
+#define CRPT_TDES0_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxH_KEY_Pos) /*!< CRPT_T::TDES0_KEYxH: KEY Mask */\r
+\r
+#define CRPT_TDES0_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxL: KEY Position */\r
+#define CRPT_TDES0_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxL_KEY_Pos) /*!< CRPT_T::TDES0_KEYxL: KEY Mask */\r
+\r
+#define CRPT_TDES0_IVH_IV_Pos (0) /*!< CRPT_T::TDES0_IVH: IV Position */\r
+#define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) /*!< CRPT_T::TDES0_IVH: IV Mask */\r
+\r
+#define CRPT_TDES0_IVL_IV_Pos (0) /*!< CRPT_T::TDES0_IVL: IV Position */\r
+#define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) /*!< CRPT_T::TDES0_IVL: IV Mask */\r
+\r
+#define CRPT_TDES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES0_SADDR: SADDR Position */\r
+#define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) /*!< CRPT_T::TDES0_SADDR: SADDR Mask */\r
+\r
+#define CRPT_TDES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES0_DADDR: DADDR Position */\r
+#define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) /*!< CRPT_T::TDES0_DADDR: DADDR Mask */\r
+\r
+#define CRPT_TDES0_CNT_CNT_Pos (0) /*!< CRPT_T::TDES0_CNT: CNT Position */\r
+#define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) /*!< CRPT_T::TDES0_CNT: CNT Mask */\r
+\r
+#define CRPT_TDES_DATIN_DATIN_Pos (0) /*!< CRPT_T::TDES_DATIN: DATIN Position */\r
+#define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) /*!< CRPT_T::TDES_DATIN: DATIN Mask */\r
+\r
+#define CRPT_TDES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::TDES_DATOUT: DATOUT Position */\r
+#define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) /*!< CRPT_T::TDES_DATOUT: DATOUT Mask */\r
+\r
+#define CRPT_TDES1_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxH: KEY Position */\r
+#define CRPT_TDES1_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES1_KEYxH_KEY_Pos) /*!< CRPT_T::TDES1_KEYxH: KEY Mask */\r
+\r
+#define CRPT_TDES1_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxL: KEY Position */\r
+#define CRPT_TDES1_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) /*!< CRPT_T::TDES1_KEYxL: KEY Mask */\r
+\r
+#define CRPT_TDES1_IVH_IV_Pos (0) /*!< CRPT_T::TDES1_IVH: IV Position */\r
+#define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) /*!< CRPT_T::TDES1_IVH: IV Mask */\r
+\r
+#define CRPT_TDES1_IVL_IV_Pos (0) /*!< CRPT_T::TDES1_IVL: IV Position */\r
+#define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) /*!< CRPT_T::TDES1_IVL: IV Mask */\r
+\r
+#define CRPT_TDES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES1_SADDR: SADDR Position */\r
+#define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) /*!< CRPT_T::TDES1_SADDR: SADDR Mask */\r
+\r
+#define CRPT_TDES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES1_DADDR: DADDR Position */\r
+#define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) /*!< CRPT_T::TDES1_DADDR: DADDR Mask */\r
+\r
+#define CRPT_TDES1_CNT_CNT_Pos (0) /*!< CRPT_T::TDES1_CNT: CNT Position */\r
+#define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) /*!< CRPT_T::TDES1_CNT: CNT Mask */\r
+\r
+#define CRPT_TDES2_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxH: KEY Position */\r
+#define CRPT_TDES2_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxH_KEY_Pos) /*!< CRPT_T::TDES2_KEYxH: KEY Mask */\r
+\r
+#define CRPT_TDES2_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxL: KEY Position */\r
+#define CRPT_TDES2_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxL_KEY_Pos) /*!< CRPT_T::TDES2_KEYxL: KEY Mask */\r
+\r
+#define CRPT_TDES2_IVH_IV_Pos (0) /*!< CRPT_T::TDES2_IVH: IV Position */\r
+#define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) /*!< CRPT_T::TDES2_IVH: IV Mask */\r
+\r
+#define CRPT_TDES2_IVL_IV_Pos (0) /*!< CRPT_T::TDES2_IVL: IV Position */\r
+#define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) /*!< CRPT_T::TDES2_IVL: IV Mask */\r
+\r
+#define CRPT_TDES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES2_SADDR: SADDR Position */\r
+#define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) /*!< CRPT_T::TDES2_SADDR: SADDR Mask */\r
+\r
+#define CRPT_TDES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES2_DADDR: DADDR Position */\r
+#define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) /*!< CRPT_T::TDES2_DADDR: DADDR Mask */\r
+\r
+#define CRPT_TDES2_CNT_CNT_Pos (0) /*!< CRPT_T::TDES2_CNT: CNT Position */\r
+#define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) /*!< CRPT_T::TDES2_CNT: CNT Mask */\r
+\r
+#define CRPT_TDES3_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxH: KEY Position */\r
+#define CRPT_TDES3_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxH_KEY_Pos) /*!< CRPT_T::TDES3_KEYxH: KEY Mask */\r
+\r
+#define CRPT_TDES3_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxL: KEY Position */\r
+#define CRPT_TDES3_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxL_KEY_Pos) /*!< CRPT_T::TDES3_KEYxL: KEY Mask */\r
+\r
+#define CRPT_TDES3_IVH_IV_Pos (0) /*!< CRPT_T::TDES3_IVH: IV Position */\r
+#define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) /*!< CRPT_T::TDES3_IVH: IV Mask */\r
+\r
+#define CRPT_TDES3_IVL_IV_Pos (0) /*!< CRPT_T::TDES3_IVL: IV Position */\r
+#define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) /*!< CRPT_T::TDES3_IVL: IV Mask */\r
+\r
+#define CRPT_TDES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES3_SADDR: SADDR Position */\r
+#define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) /*!< CRPT_T::TDES3_SADDR: SADDR Mask */\r
+\r
+#define CRPT_TDES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES3_DADDR: DADDR Position */\r
+#define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) /*!< CRPT_T::TDES3_DADDR: DADDR Mask */\r
+\r
+#define CRPT_TDES3_CNT_CNT_Pos (0) /*!< CRPT_T::TDES3_CNT: CNT Position */\r
+#define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) /*!< CRPT_T::TDES3_CNT: CNT Mask */\r
+\r
+#define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */\r
+#define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */\r
+\r
+#define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */\r
+#define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */\r
+\r
+#define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */\r
+#define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */\r
+\r
+#define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */\r
+#define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */\r
+\r
+#define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */\r
+#define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */\r
+\r
+#define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */\r
+#define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */\r
+\r
+#define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */\r
+#define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */\r
+\r
+#define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */\r
+#define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */\r
+\r
+#define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */\r
+#define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */\r
+\r
+#define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */\r
+#define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */\r
+\r
+#define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */\r
+#define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */\r
+\r
+#define CRPT_HMAC_DGSTx_DGST_Pos (0) /*!< CRPT_T::HMAC_DGSTx: DGST Position */\r
+#define CRPT_HMAC_DGSTx_DGST_Msk (0xfffffffful << CRPT_HMAC_DGSTx_DGST_Pos) /*!< CRPT_T::HMAC_DGSTx: DGST Mask */\r
+\r
+#define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */\r
+#define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */\r
+\r
+#define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */\r
+#define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */\r
+\r
+#define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */\r
+#define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */\r
+\r
+#define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */\r
+#define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */\r
+\r
+#define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */\r
+#define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */\r
+\r
+#define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */\r
+#define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */\r
+\r
+#define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */\r
+#define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */\r
+\r
+#define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */\r
+#define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */\r
+\r
+#define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */\r
+#define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */\r
+\r
+#define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */\r
+#define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */\r
+\r
+#define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */\r
+#define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */\r
+\r
+#define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */\r
+#define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */\r
+\r
+#define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */\r
+#define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */\r
+\r
+#define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */\r
+#define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */\r
+\r
+#define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */\r
+#define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */\r
+\r
+#define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */\r
+#define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */\r
+\r
+#define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */\r
+#define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */\r
+\r
+#define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */\r
+#define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */\r
+\r
+#define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */\r
+#define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */\r
+\r
+#define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */\r
+#define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */\r
+\r
+#define CRPT_ECC_X1_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1: POINTX1 Position */\r
+#define CRPT_ECC_X1_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_POINTX1_Pos) /*!< CRPT_T::ECC_X1: POINTX1 Mask */\r
+\r
+#define CRPT_ECC_Y1_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1: POINTY1 Position */\r
+#define CRPT_ECC_Y1_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_POINTY1_Pos) /*!< CRPT_T::ECC_Y1: POINTY1 Mask */\r
+\r
+#define CRPT_ECC_X2_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2: POINTX2 Position */\r
+#define CRPT_ECC_X2_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_POINTX2_Pos) /*!< CRPT_T::ECC_X2: POINTX2 Mask */\r
+\r
+#define CRPT_ECC_Y2_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2: POINTY2 Position */\r
+#define CRPT_ECC_Y2_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_POINTY2_Pos) /*!< CRPT_T::ECC_Y2: POINTY2 Mask */\r
+\r
+#define CRPT_ECC_A_CURVEA_Pos (0) /*!< CRPT_T::ECC_A: CURVEA Position */\r
+#define CRPT_ECC_A_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_CURVEA_Pos) /*!< CRPT_T::ECC_A: CURVEA Mask */\r
+\r
+#define CRPT_ECC_B_CURVEB_Pos (0) /*!< CRPT_T::ECC_B: CURVEB Position */\r
+#define CRPT_ECC_B_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_CURVEB_Pos) /*!< CRPT_T::ECC_B: CURVEB Mask */\r
+\r
+#define CRPT_ECC_N_CURVEN_Pos (0) /*!< CRPT_T::ECC_N: CURVEN Position */\r
+#define CRPT_ECC_N_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_CURVEN_Pos) /*!< CRPT_T::ECC_N: CURVEN Mask */\r
+\r
+#define CRPT_ECC_K_SCALARK_Pos (0) /*!< CRPT_T::ECC_K: SCALARK Position */\r
+#define CRPT_ECC_K_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_SCALARK_Pos) /*!< CRPT_T::ECC_K: SCALARK Mask */\r
+\r
+#define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */\r
+#define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */\r
+\r
+#define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/\r
+#define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */\r
+\r
+#define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position */\r
+#define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */\r
+\r
+/**@}*/ /* CRPT_CONST */\r
+/**@}*/ /* end of CRPT register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __CRPT_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file dac_reg.h\r
+ * @version V1.00\r
+ * @brief DAC register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __DAC_REG_H__\r
+#define __DAC_REG_H__\r
+\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Digital to Analog Converter -------------------------*/\r
+/**\r
+ @addtogroup DAC Digital to Analog Converter(DAC)\r
+ Memory Mapped Structure for DAC Controller\r
+@{ */\r
+\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+\r
+ /**\r
+ * @var DAC_T::CTL\r
+ * Offset: 0x00 DAC Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |DACEN |DAC Enable Bit\r
+ * | | |0 = DAC is Disabled.\r
+ * | | |1 = DAC is Enabled.\r
+ * |[1] |DACIEN |DAC Interrupt Enable Bit\r
+ * | | |0 = Interrupt is Disabled.\r
+ * | | |1 = Interrupt is Enabled.\r
+ * |[2] |DMAEN |DMA Mode Enable Bit\r
+ * | | |0 = DMA mode Disabled.\r
+ * | | |1 = DMA mode Enabled.\r
+ * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit\r
+ * | | |0 = DMA under-run interrupt Disabled.\r
+ * | | |1 = DMA under-run interrupt Enabled.\r
+ * |[4] |TRGEN |Trigger Mode Enable Bit\r
+ * | | |0 = DAC event trigger mode Disabled.\r
+ * | | |1 = DAC event trigger mode Enabled.\r
+ * |[7:5] |TRGSEL |Trigger Source Selection\r
+ * | | |000 = Software trigger.\r
+ * | | |001 = External pin DAC0_ST trigger.\r
+ * | | |010 = Timer 0 trigger.\r
+ * | | |011 = Timer 1 trigger.\r
+ * | | |100 = Timer 2 trigger.\r
+ * | | |101 = Timer 3 trigger.\r
+ * | | |110 = EPWM0 trigger.\r
+ * | | |111 = EPWM1 trigger.\r
+ * |[8] |BYPASS |Bypass Buffer Mode\r
+ * | | |0 = Output voltage buffer Enabled.\r
+ * | | |1 = Output voltage buffer Disabled.\r
+ * |[10] |LALIGN |DAC Data Left-aligned Enabled Control\r
+ * | | |0 = Right alignment.\r
+ * | | |1 = Left alignment.\r
+ * |[13:12] |ETRGSEL |External Pin Trigger Selection\r
+ * | | |00 = Low level trigger.\r
+ * | | |01 = High level trigger.\r
+ * | | |10 = Falling edge trigger.\r
+ * | | |11 = Rising edge trigger.\r
+ * |[15:14] |BWSEL |DAC Data Bit-width Selection\r
+ * | | |00 = data is 12 bits.\r
+ * | | |01 = data is 8 bits.\r
+ * | | |Others = reserved.\r
+ * |[16] |GRPEN |DAC Group Mode Enable Bit\r
+ * | | |0 = DAC0 and DAC1 are not grouped.\r
+ * | | |1 = DAC0 and DAC1 are grouped.\r
+ * @var DAC_T::SWTRG\r
+ * Offset: 0x04 DAC Software Trigger Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SWTRG |Software Trigger\r
+ * | | |0 = Software trigger Disabled.\r
+ * | | |1 = Software trigger Enabled.\r
+ * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.\r
+ * @var DAC_T::DAT\r
+ * Offset: 0x08 DAC Data Holding Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |DACDAT |DAC 12-bit Holding Data\r
+ * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output.\r
+ * | | |The unused bits (DACDAT[3:0] in left-alignment mode and DACDAT[15:12] in right alignment mode) are ignored by DAC controller hardware.\r
+ * | | |12 bit left alignment: user has to load data into DACDAT[15:4] bits.\r
+ * | | |12 bit right alignment: user has to load data into DACDAT[11:0] bits.\r
+ * @var DAC_T::DATOUT\r
+ * Offset: 0x0C DAC Data Output Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[11:0] |DATOUT |DAC 12-bit Output Data\r
+ * | | |These bits are current digital data for DAC output conversion.\r
+ * | | |It is loaded from DAC_DAT register and user cannot write it directly.\r
+ * @var DAC_T::STATUS\r
+ * Offset: 0x10 DAC Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |FINISH |DAC Conversion Complete Finish Flag\r
+ * | | |0 = DAC is in conversion state.\r
+ * | | |1 = DAC conversion finish.\r
+ * | | |This bit set to 1 when conversion time counter counts to SETTLET.\r
+ * | | |It is cleared to 0 when DAC starts a new conversion.\r
+ * | | |User writes 1 to clear this bit to 0.\r
+ * |[1] |DMAUDR |DMA Under-run Interrupt Flag\r
+ * | | |0 = No DMA under-run error condition occurred.\r
+ * | | |1 = DMA under-run error condition occurred.\r
+ * | | |User writes 1 to clear this bit.\r
+ * |[8] |BUSY |DAC Busy Flag (Read Only)\r
+ * | | |0 = DAC is ready for next conversion.\r
+ * | | |1 = DAC is busy in conversion.\r
+ * | | |This is read only bit.\r
+ * @var DAC_T::TCTL\r
+ * Offset: 0x14 DAC Timing Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[9:0] |SETTLET |DAC Output Settling Time\r
+ * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\r
+ * | | |For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x40.\r
+ */\r
+ __IO uint32_t CTL; /*!< [0x0000] DAC Control Register */\r
+ __IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */\r
+ __IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */\r
+ __I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */\r
+ __IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */\r
+ __IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */\r
+\r
+} DAC_T;\r
+\r
+/**\r
+ @addtogroup DAC_CONST DAC Bit Field Definition\r
+ Constant Definitions for DAC Controller\r
+@{ */\r
+\r
+#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */\r
+#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */\r
+\r
+#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */\r
+#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */\r
+\r
+#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */\r
+#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */\r
+\r
+#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */\r
+#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */\r
+\r
+#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */\r
+#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */\r
+\r
+#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */\r
+#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */\r
+\r
+#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */\r
+#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */\r
+\r
+#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */\r
+#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */\r
+\r
+#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */\r
+#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */\r
+\r
+#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */\r
+#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */\r
+\r
+#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */\r
+#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */\r
+\r
+#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */\r
+#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */\r
+\r
+#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */\r
+#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */\r
+\r
+#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */\r
+#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */\r
+\r
+#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */\r
+#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */\r
+\r
+#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */\r
+#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */\r
+\r
+#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */\r
+#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */\r
+\r
+#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */\r
+#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */\r
+\r
+/**@}*/ /* DAC_CONST */\r
+/**@}*/ /* end of DAC register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __DAC_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file eadc_reg.h\r
+ * @version V1.00\r
+ * @brief EADC register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __EADC_REG_H__\r
+#define __EADC_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Enhanced Analog to Digital Converter -------------------------*/\r
+/**\r
+ @addtogroup EADC Enhanced Analog to Digital Converter(EADC)\r
+ Memory Mapped Structure for EADC Controller\r
+@{ */\r
+\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var EADC_T::DAT[19]\r
+ * Offset: 0x00 ADC Data Register 0~18 for Sample Module 0~18\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |RESULT |ADC Conversion Result\r
+ * | | |This field contains 12 bits conversion result.\r
+ * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\r
+ * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].\r
+ * |[16] |OV |Overrun Flag\r
+ * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.\r
+ * | | |0 = Data in RESULT[11:0] is recent conversion result.\r
+ * | | |1 = Data in RESULT[11:0] is overwrite.\r
+ * | | |Note: It is cleared by hardware after EADC_DAT register is read.\r
+ * |[17] |VALID |Valid Flag\r
+ * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.\r
+ * | | |0 = Data in RESULT[11:0] bits is not valid.\r
+ * | | |1 = Data in RESULT[11:0] bits is valid.\r
+ * @var EADC_T::CURDAT\r
+ * Offset: 0x4C ADC PDMA Current Transfer Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register\r
+ * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.\r
+ * | | |This is a read only register.\r
+ * @var EADC_T::CTL\r
+ * Offset: 0x50 ADC Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ADCEN |ADC Converter Enable Bit\r
+ * | | |0 = Disabled EADC.\r
+ * | | |1 = Enabled EADC.\r
+ * | | |Note: Before starting ADC conversion function, this bit should be set to 1\r
+ * | | |Clear it to 0 to disable ADC converter analog circuit power consumption.\r
+ * |[1] |ADCRST |ADC Converter Control Circuits Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.\r
+ * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.\r
+ * |[2] |ADCIEN0 |Specific Sample Module ADC ADINT0 Interrupt Enable Bit\r
+ * | | |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion\r
+ * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.\r
+ * | | |0 = Specific sample module ADC ADINT0 interrupt function Disabled.\r
+ * | | |1 = Specific sample module ADC ADINT0 interrupt function Enabled.\r
+ * |[3] |ADCIEN1 |Specific Sample Module ADC ADINT1 Interrupt Enable Bit\r
+ * | | |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion\r
+ * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.\r
+ * | | |0 = Specific sample module ADC ADINT1 interrupt function Disabled.\r
+ * | | |1 = Specific sample module ADC ADINT1 interrupt function Enabled.\r
+ * |[4] |ADCIEN2 |Specific Sample Module ADC ADINT2 Interrupt Enable Bit\r
+ * | | |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion\r
+ * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.\r
+ * | | |0 = Specific sample module ADC ADINT2 interrupt function Disabled.\r
+ * | | |1 = Specific sample module ADC ADINT2 interrupt function Enabled.\r
+ * |[5] |ADCIEN3 |Specific Sample Module ADC ADINT3 Interrupt Enable Bit\r
+ * | | |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion\r
+ * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.\r
+ * | | |0 = Specific sample module ADC ADINT3 interrupt function Disabled.\r
+ * | | |1 = Specific sample module ADC ADINT3 interrupt function Enabled.\r
+ * |[7:6] |RESSEL |Resolution Selection\r
+ * | | |00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]).\r
+ * | | |01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]).\r
+ * | | |10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]).\r
+ * | | |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]).\r
+ * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit\r
+ * | | |0 = Single-end analog input mode.\r
+ * | | |1 = Differential analog input mode.\r
+ * |[9] |DMOF |ADC Differential Input Mode Output Format\r
+ * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.\r
+ * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.\r
+ * |[11] |PDMAEN |PDMA Transfer Enable Bit\r
+ * | | |When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.\r
+ * | | |0 = PDMA data transfer Disabled.\r
+ * | | |1 = PDMA data transfer Enabled.\r
+ * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.\r
+ * @var EADC_T::SWTRG\r
+ * Offset: 0x54 ADC Sample Module Software Start Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[18:0] |SWTRG |ADC Sample Module 0~18 Software Force to Start ADC Conversion\r
+ * | | |0 = No effect.\r
+ * | | |1 = Cause an ADC conversion when the priority is given to sample module.\r
+ * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion\r
+ * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.\r
+ * @var EADC_T::PENDSTS\r
+ * Offset: 0x58 ADC Start of Conversion Pending Flag Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[18:0] |STPF |ADC Sample Module 0~18 Start of Conversion Pending Flag\r
+ * | | |Read:\r
+ * | | |0 = There is no pending conversion for sample module.\r
+ * | | |1 = Sample module ADC start of conversion is pending.\r
+ * | | |Write:\r
+ * | | |1 = clear pending flag and cancel the conversion for sample module.\r
+ * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0\r
+ * @var EADC_T::OVSTS\r
+ * Offset: 0x5C ADC Sample Module Start of Conversion Overrun Flag Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[18:0] |SPOVF |ADC SAMPLE0~18 Overrun Flag\r
+ * | | |0 = No sample module event overrun.\r
+ * | | |1 = Indicates a new sample module event is generated while an old one event is pending.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * @var EADC_T::SCTL[19]\r
+ * Offset: 0x80 ADC Sample Module 0~18 Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |CHSEL |ADC Sample Module Channel Selection\r
+ * | | |00H = EADC_CH0 (slow channel).\r
+ * | | |01H = EADC_CH1 (slow channel).\r
+ * | | |02H = EADC_CH2 (slow channel).\r
+ * | | |03H = EADC_CH3 (slow channel).\r
+ * | | |04H = EADC_CH4 (slow channel).\r
+ * | | |05H = EADC_CH5 (slow channel).\r
+ * | | |06H = EADC_CH6 (slow channel).\r
+ * | | |07H = EADC_CH7 (slow channel).\r
+ * | | |08H = EADC_CH8 (slow channel).\r
+ * | | |09H = EADC_CH9 (slow channel).\r
+ * | | |0AH = EADC_CH10 (fast channel).\r
+ * | | |0BH = EADC_CH11 (fast channel).\r
+ * | | |0CH = EADC_CH12 (fast channel).\r
+ * | | |0DH = EADC_CH13 (fast channel).\r
+ * | | |0EH = EADC_CH14 (fast channel).\r
+ * | | |0FH = EADC_CH15 (fast channel).\r
+ * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit\r
+ * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source.\r
+ * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source.\r
+ * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit\r
+ * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source.\r
+ * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source.\r
+ * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\r
+ * | | |Trigger delay clock frequency:\r
+ * | | |00 = ADC_CLK/1.\r
+ * | | |01 = ADC_CLK/2.\r
+ * | | |10 = ADC_CLK/4.\r
+ * | | |11 = ADC_CLK/16.\r
+ * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time\r
+ * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).\r
+ * |[20:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection\r
+ * | | |0H = Disable trigger.\r
+ * | | |1H = External trigger from EADC0_ST pin input.\r
+ * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.\r
+ * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.\r
+ * | | |4H = Timer0 overflow pulse trigger.\r
+ * | | |5H = Timer1 overflow pulse trigger.\r
+ * | | |6H = Timer2 overflow pulse trigger.\r
+ * | | |7H = Timer3 overflow pulse trigger.\r
+ * | | |8H = EPWM0TG0.\r
+ * | | |9H = EPWM0TG1.\r
+ * | | |AH = EPWM0TG2.\r
+ * | | |BH = EPWM0TG3.\r
+ * | | |CH = EPWM0TG4.\r
+ * | | |DH = EPWM0TG5.\r
+ * | | |EH = EPWM1TG0.\r
+ * | | |FH = EPWM1TG1.\r
+ * | | |10H = EPWM1TG2.\r
+ * | | |11H = EPWM1TG3.\r
+ * | | |12H = EPWM1TG4.\r
+ * | | |13H = EPWM1TG5.\r
+ * | | |14H = BPWM0TG.\r
+ * | | |15H = BPWM1TG.\r
+ * | | |other = Reserved.\r
+ * |[22] |INTPOS |Interrupt Flag Position Select\r
+ * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion.\r
+ * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion.\r
+ * |[23] |DBMEN |Double Buffer Mode Enable Bit\r
+ * | | |0 = Sample has one sample result register. (default).\r
+ * | | |1 = Sample has two sample result registers.\r
+ * |[31:24] |EXTSMPT |ADC Sampling Time Extend\r
+ * | | |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.\r
+ * | | |The range of start delay time is from 0~255 ADC clock.\r
+ * @var EADC_T::INTSRC[4]\r
+ * Offset: 0xD0 ADC interrupt 0~3 Source Enable Control Register.\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 0 interrupt Disabled.\r
+ * | | |1 = Sample Module 0 interrupt Enabled.\r
+ * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 1 interrupt Disabled.\r
+ * | | |1 = Sample Module 1 interrupt Enabled.\r
+ * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 2 interrupt Disabled.\r
+ * | | |1 = Sample Module 2 interrupt Enabled.\r
+ * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 3 interrupt Disabled.\r
+ * | | |1 = Sample Module 3 interrupt Enabled.\r
+ * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 4 interrupt Disabled.\r
+ * | | |1 = Sample Module 4 interrupt Enabled.\r
+ * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 5 interrupt Disabled.\r
+ * | | |1 = Sample Module 5 interrupt Enabled.\r
+ * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 6 interrupt Disabled.\r
+ * | | |1 = Sample Module 6 interrupt Enabled.\r
+ * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 7 interrupt Disabled.\r
+ * | | |1 = Sample Module 7 interrupt Enabled.\r
+ * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 8 interrupt Disabled.\r
+ * | | |1 = Sample Module 8 interrupt Enabled.\r
+ * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 9 interrupt Disabled.\r
+ * | | |1 = Sample Module 9 interrupt Enabled.\r
+ * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 10 interrupt Disabled.\r
+ * | | |1 = Sample Module 10 interrupt Enabled.\r
+ * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 11 interrupt Disabled.\r
+ * | | |1 = Sample Module 11 interrupt Enabled.\r
+ * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 12 interrupt Disabled.\r
+ * | | |1 = Sample Module 12 interrupt Enabled.\r
+ * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 13 interrupt Disabled.\r
+ * | | |1 = Sample Module 13 interrupt Enabled.\r
+ * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 14 interrupt Disabled.\r
+ * | | |1 = Sample Module 14 interrupt Enabled.\r
+ * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 15 interrupt Disabled.\r
+ * | | |1 = Sample Module 15 interrupt Enabled.\r
+ * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 16 interrupt Disabled.\r
+ * | | |1 = Sample Module 16 interrupt Enabled.\r
+ * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 17 interrupt Disabled.\r
+ * | | |1 = Sample Module 17 interrupt Enabled.\r
+ * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit\r
+ * | | |0 = Sample Module 18 interrupt Disabled.\r
+ * | | |1 = Sample Module 18 interrupt Enabled.\r
+ * @var EADC_T::CMP[4]\r
+ * Offset: 0xE0 ADC Result Compare Register 0~3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ADCMPEN |ADC Result Compare Enable Bit\r
+ * | | |0 = Compare Disabled.\r
+ * | | |1 = Compare Enabled.\r
+ * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.\r
+ * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit\r
+ * | | |0 = Compare function interrupt Disabled.\r
+ * | | |1 = Compare function interrupt Enabled.\r
+ * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.\r
+ * |[2] |CMPCOND |Compare Condition\r
+ * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.\r
+ * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.\r
+ * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.\r
+ * |[7:3] |CMPSPL |Compare Sample Module Selection\r
+ * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.\r
+ * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.\r
+ * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.\r
+ * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.\r
+ * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.\r
+ * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.\r
+ * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.\r
+ * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.\r
+ * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.\r
+ * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.\r
+ * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.\r
+ * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.\r
+ * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.\r
+ * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.\r
+ * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.\r
+ * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.\r
+ * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.\r
+ * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.\r
+ * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.\r
+ * |[11:8] |CMPMCNT |Compare Match Count\r
+ * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1\r
+ * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0\r
+ * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.\r
+ * |[15] |CMPWEN |Compare Window Mode Enable Bit\r
+ * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched\r
+ * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched\r
+ * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched\r
+ * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.\r
+ * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.\r
+ * |[27:16] |CMPDAT |Comparison Data\r
+ * | | |The 12 bits data is used to compare with conversion result of specified sample module\r
+ * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software.\r
+ * @var EADC_T::STATUS0\r
+ * Offset: 0xF0 ADC Status Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag\r
+ * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18).\r
+ * |[31:16] |OV |EADC_DAT0~15 Overrun Flag\r
+ * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18).\r
+ * @var EADC_T::STATUS1\r
+ * Offset: 0xF4 ADC Status Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag\r
+ * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18).\r
+ * |[18:16] |OV |EADC_DAT16~18 Overrun Flag\r
+ * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18).\r
+ * @var EADC_T::STATUS2\r
+ * Offset: 0xF8 ADC Status Register 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ADIF0 |ADC ADINT0 Interrupt Flag\r
+ * | | |0 = No ADINT0 interrupt pulse received.\r
+ * | | |1 = ADINT0 interrupt pulse has been received.\r
+ * | | |Note1: This bit is cleared by writing 1 to it.\r
+ * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed\r
+ * |[1] |ADIF1 |ADC ADINT1 Interrupt Flag\r
+ * | | |0 = No ADINT1 interrupt pulse received.\r
+ * | | |1 = ADINT1 interrupt pulse has been received.\r
+ * | | |Note1: This bit is cleared by writing 1 to it.\r
+ * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed\r
+ * |[2] |ADIF2 |ADC ADINT2 Interrupt Flag\r
+ * | | |0 = No ADINT2 interrupt pulse received.\r
+ * | | |1 = ADINT2 interrupt pulse has been received.\r
+ * | | |Note1: This bit is cleared by writing 1 to it.\r
+ * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed\r
+ * |[3] |ADIF3 |ADC ADINT3 Interrupt Flag\r
+ * | | |0 = No ADINT3 interrupt pulse received.\r
+ * | | |1 = ADINT3 interrupt pulse has been received.\r
+ * | | |Note1: This bit is cleared by writing 1 to it.\r
+ * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed\r
+ * |[4] |ADCMPF0 |ADC Compare 0 Flag\r
+ * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\r
+ * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.\r
+ * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[5] |ADCMPF1 |ADC Compare 1 Flag\r
+ * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\r
+ * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.\r
+ * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[6] |ADCMPF2 |ADC Compare 2 Flag\r
+ * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\r
+ * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.\r
+ * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[7] |ADCMPF3 |ADC Compare 3 Flag\r
+ * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\r
+ * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.\r
+ * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[8] |ADOVIF0 |ADC ADINT0 Interrupt Flag Overrun\r
+ * | | |0 = ADINT0 interrupt flag is not overwritten to 1.\r
+ * | | |1 = ADINT0 interrupt flag is overwritten to 1.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[9] |ADOVIF1 |ADC ADINT1 Interrupt Flag Overrun\r
+ * | | |0 = ADINT1 interrupt flag is not overwritten to 1.\r
+ * | | |1 = ADINT1 interrupt flag is overwritten to 1.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[10] |ADOVIF2 |ADC ADINT2 Interrupt Flag Overrun\r
+ * | | |0 = ADINT2 interrupt flag is not overwritten to 1.\r
+ * | | |1 = ADINT2 interrupt flag is s overwritten to 1.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[11] |ADOVIF3 |ADC ADINT3 Interrupt Flag Overrun\r
+ * | | |0 = ADINT3 interrupt flag is not overwritten to 1.\r
+ * | | |1 = ADINT3 interrupt flag is overwritten to 1.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[12] |ADCMPO0 |ADC Compare 0 Output Status (Read Only)\r
+ * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module.\r
+ * | | |User can use it to monitor the external analog input pin voltage status.\r
+ * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting.\r
+ * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting.\r
+ * |[13] |ADCMPO1 |ADC Compare 1 Output Status (Read Only)\r
+ * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module.\r
+ * | | |User can use it to monitor the external analog input pin voltage status.\r
+ * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting.\r
+ * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting.\r
+ * |[14] |ADCMPO2 |ADC Compare 2 Output Status (Read Only)\r
+ * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module.\r
+ * | | |User can use it to monitor the external analog input pin voltage status.\r
+ * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting.\r
+ * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting.\r
+ * |[15] |ADCMPO3 |ADC Compare 3 Output Status (Read Only)\r
+ * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module.\r
+ * | | |User can use it to monitor the external analog input pin voltage status.\r
+ * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting.\r
+ * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting.\r
+ * |[20:16] |CHANNEL |Current Conversion Channel (Read Only)\r
+ * | | |This filed reflects ADC current conversion channel when BUSY=1.\r
+ * | | |It is read only.\r
+ * | | |00H = EADC_CH0.\r
+ * | | |01H = EADC_CH1.\r
+ * | | |02H = EADC_CH2.\r
+ * | | |03H = EADC_CH3.\r
+ * | | |04H = EADC_CH4.\r
+ * | | |05H = EADC_CH5.\r
+ * | | |06H = EADC_CH6.\r
+ * | | |07H = EADC_CH7.\r
+ * | | |08H = EADC_CH8.\r
+ * | | |09H = EADC_CH9.\r
+ * | | |0AH = EADC_CH10.\r
+ * | | |0BH = EADC_CH11.\r
+ * | | |0CH = EADC_CH12.\r
+ * | | |0DH = EADC_CH13.\r
+ * | | |0EH = EADC_CH14.\r
+ * | | |0FH = EADC_CH15.\r
+ * | | |10H = VBG.\r
+ * | | |11H = VTEMP.\r
+ * | | |12H = VBAT/4.\r
+ * |[23] |BUSY |Busy/Idle (Read Only)\r
+ * | | |0 = EADC is in idle state.\r
+ * | | |1 = EADC is busy at conversion.\r
+ * |[24] |ADOVIF |All ADC Interrupt Flag Overrun Bits Check (Read Only)\r
+ * | | |n=0~3.\r
+ * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.\r
+ * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.\r
+ * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.\r
+ * |[25] |STOVF |for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only)\r
+ * | | |n=0~18.\r
+ * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.\r
+ * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.\r
+ * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.\r
+ * |[26] |AVALID |for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)\r
+ * | | |n=0~18.\r
+ * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.\r
+ * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.\r
+ * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1.\r
+ * |[27] |AOV |for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only)\r
+ * | | |n=0~18.\r
+ * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.\r
+ * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.\r
+ * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1.\r
+ * @var EADC_T::STATUS3\r
+ * Offset: 0xFC ADC Status Register 3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[4:0] |CURSPL |ADC Current Sample Module\r
+ * | | |This register show the current ADC is controlled by which sample module control logic modules.\r
+ * | | |If the ADC is Idle, this bit filed will set to 0x1F.\r
+ * | | |This is a read only register.\r
+ * @var EADC_T::DDAT\r
+ * Offset: 0x100-0x10C ADC Double Data Register n for Sample Module n, n=0~3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |RESULT |ADC Conversion Results\r
+ * | | |This field contains 12 bits conversion results.\r
+ * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].\r
+ * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].\r
+ * |[16] |OV |Overrun Flag\r
+ * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.\r
+ * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.\r
+ * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1.\r
+ * | | |It is cleared by hardware after EADC_DDAT register is read.\r
+ * |[17] |VALID |Valid Flag\r
+ * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.\r
+ * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.\r
+ * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read.\r
+ * | | |(n=0~3).\r
+ * @var EADC_T::PWRM\r
+ * Offset: 0x110 ADC Power Management Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PWUPRDY |ADC Power-up Sequence Completed and Ready for Conversion (Read Only)\r
+ * | | |0 = ADC is not ready for conversion may be in power down state or in the progress of power up.\r
+ * | | |1 = ADC is ready for conversion.\r
+ * |[1] |PWUCALEN |Power Up Calibration Function Enable Control\r
+ * | | |0 = Disable the function of calibration at power up.\r
+ * | | |1 = Enable the function of calibration at power up.\r
+ * | | |Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following\r
+ * | | |{PWUCALEN, CALSEL } Description:\r
+ * | | |PWUCALEN is 0 and CALSEL is 0: No need to calibrate.\r
+ * | | |PWUCALEN is 0 and CALSEL is 1: No need to calibrate.\r
+ * | | |PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up.\r
+ * | | |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up.\r
+ * |[3:2] |PWDMOD |ADC Power-down Mode\r
+ * | | |Set this bit fields to select ADC power down mode when system power-down.\r
+ * | | |00 = ADC Deep power down mode.\r
+ * | | |01 = ADC Power down.\r
+ * | | |10 = ADC Standby mode.\r
+ * | | |11 = ADC Deep power down mode.\r
+ * | | |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up\r
+ * |[19:8] |LDOSUT |ADC Internal LDO Start-up Time\r
+ * | | |Set this bit fields to control LDO start-up time\r
+ * | | |The minimum required LDO start-up time is 20us\r
+ * | | |LDO start-up time = (1/ADC_CLK) x LDOSUT.\r
+ * @var EADC_T::CALCTL\r
+ * Offset: 0x114 ADC Calibration Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |CALSTART |Calibration Functional Block Start\r
+ * | | |0 = Stops calibration functional block.\r
+ * | | |1 = Starts calibration functional block.\r
+ * | | |Note: This bit is set by SW and clear by HW after re-calibration finish\r
+ * |[2] |CALDONE |Calibration Functional Block Complete (Read Only)\r
+ * | | |0 = During a calibration.\r
+ * | | |1 = Calibration is completed.\r
+ * |[3] |CALSEL |Select Calibration Functional Block\r
+ * | | |0 = Load calibration word when calibration functional block is active.\r
+ * | | |1 = Execute calibration when calibration functional block is active.\r
+ * @var EADC_T::CALDWRD\r
+ * Offset: 0x118 ADC Calibration Load Word Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[6:0] |CALWORD |Calibration Word Bits\r
+ * | | |Write to this register with the previous calibration word before load calibration action.\r
+ * | | |Read this register after calibration done.\r
+ * | | |Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.\r
+ */\r
+\r
+ __I uint32_t DAT[19]; /*!< [0x0000~0x0048] ADC Data Register n for Sample Module n, n=0~18 */\r
+ __I uint32_t CURDAT; /*!< [0x004c] ADC PDMA Current Transfer Data Register */\r
+ __IO uint32_t CTL; /*!< [0x0050] ADC Control Register */\r
+ __O uint32_t SWTRG; /*!< [0x0054] ADC Sample Module Software Start Register */\r
+ __IO uint32_t PENDSTS; /*!< [0x0058] ADC Start of Conversion Pending Flag Register */\r
+ __IO uint32_t OVSTS; /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register */\r
+ __I uint32_t RESERVE0[8];\r
+ __IO uint32_t SCTL[19]; /*!< [0x0080~0x00c8] ADC Sample Module n Control Register, n=0~18 */\r
+ __I uint32_t RESERVE1[1];\r
+ __IO uint32_t INTSRC[4]; /*!< [0x00d0~0x00dc] ADC interrupt n Source Enable Control Register, n=0~3 */\r
+ __IO uint32_t CMP[4]; /*!< [0x00e0~0x00ec] ADC Result Compare Register n, n=0~3 */\r
+ __I uint32_t STATUS0; /*!< [0x00f0] ADC Status Register 0 */\r
+ __I uint32_t STATUS1; /*!< [0x00f4] ADC Status Register 1 */\r
+ __IO uint32_t STATUS2; /*!< [0x00f8] ADC Status Register 2 */\r
+ __I uint32_t STATUS3; /*!< [0x00fc] ADC Status Register 3 */\r
+ __I uint32_t DDAT[4]; /*!< [0x0100~0x010c] ADC Double Data Register n for Sample Module n, n=0~3 */\r
+ __IO uint32_t PWRM; /*!< [0x0110] ADC Power Management Register */\r
+ __IO uint32_t CALCTL; /*!< [0x0114] ADC Calibration Control Register */\r
+ __IO uint32_t CALDWRD; /*!< [0x0118] ADC Calibration Load Word Register */\r
+\r
+} EADC_T;\r
+\r
+/**\r
+ @addtogroup EADC_CONST EADC Bit Field Definition\r
+ Constant Definitions for EADC Controller\r
+@{ */\r
+\r
+#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */\r
+#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */\r
+\r
+#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */\r
+#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */\r
+\r
+#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */\r
+#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */\r
+\r
+#define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */\r
+#define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */\r
+\r
+#define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */\r
+#define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */\r
+\r
+#define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */\r
+#define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */\r
+\r
+#define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */\r
+#define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */\r
+\r
+#define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */\r
+#define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */\r
+\r
+#define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */\r
+#define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */\r
+\r
+#define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */\r
+#define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */\r
+\r
+#define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */\r
+#define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */\r
+\r
+#define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */\r
+#define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */\r
+\r
+#define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */\r
+#define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */\r
+\r
+#define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */\r
+#define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */\r
+\r
+#define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */\r
+#define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */\r
+\r
+#define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */\r
+#define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */\r
+\r
+#define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */\r
+#define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */\r
+\r
+#define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */\r
+#define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */\r
+\r
+#define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */\r
+#define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */\r
+\r
+#define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */\r
+#define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */\r
+\r
+#define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */\r
+#define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */\r
+\r
+#define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */\r
+#define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */\r
+\r
+#define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */\r
+#define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */\r
+\r
+#define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */\r
+#define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */\r
+\r
+#define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */\r
+#define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */\r
+\r
+#define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */\r
+#define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */\r
+\r
+#define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */\r
+#define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */\r
+\r
+#define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */\r
+#define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */\r
+\r
+#define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */\r
+#define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */\r
+\r
+#define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */\r
+#define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */\r
+\r
+#define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */\r
+#define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */\r
+\r
+#define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */\r
+#define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */\r
+\r
+#define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */\r
+#define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */\r
+\r
+#define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */\r
+#define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */\r
+\r
+#define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */\r
+#define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */\r
+\r
+#define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */\r
+#define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */\r
+\r
+#define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */\r
+#define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */\r
+\r
+#define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */\r
+#define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */\r
+\r
+#define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */\r
+#define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */\r
+\r
+#define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */\r
+#define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */\r
+\r
+#define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */\r
+#define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */\r
+\r
+#define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */\r
+#define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */\r
+\r
+#define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */\r
+#define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */\r
+\r
+#define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */\r
+#define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */\r
+\r
+#define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */\r
+#define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */\r
+\r
+#define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */\r
+#define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */\r
+\r
+#define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */\r
+#define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */\r
+\r
+#define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */\r
+#define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */\r
+\r
+#define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */\r
+#define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */\r
+\r
+#define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */\r
+#define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */\r
+\r
+#define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */\r
+#define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */\r
+\r
+#define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */\r
+#define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */\r
+\r
+#define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */\r
+#define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */\r
+\r
+#define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */\r
+#define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */\r
+\r
+#define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */\r
+#define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */\r
+\r
+#define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */\r
+#define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */\r
+\r
+#define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */\r
+#define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */\r
+\r
+#define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */\r
+#define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */\r
+\r
+#define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */\r
+#define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */\r
+\r
+#define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */\r
+#define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */\r
+\r
+#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */\r
+#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */\r
+\r
+#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */\r
+#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */\r
+\r
+#define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */\r
+#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */\r
+\r
+#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */\r
+#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */\r
+\r
+#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */\r
+#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */\r
+\r
+#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */\r
+#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */\r
+\r
+#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */\r
+#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */\r
+\r
+#define EADC_CTL_RESSEL_Pos (6) /*!< EADC_T::CTL: RESSEL Position */\r
+#define EADC_CTL_RESSEL_Msk (0x3ul << EADC_CTL_RESSEL_Pos) /*!< EADC_T::CTL: RESSEL Mask */\r
+\r
+#define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */\r
+#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */\r
+\r
+#define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */\r
+#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */\r
+\r
+#define EADC_CTL_PDMAEN_Pos (11) /*!< EADC_T::CTL: PDMAEN Position */\r
+#define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /*!< EADC_T::CTL: PDMAEN Mask */\r
+\r
+#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */\r
+#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */\r
+\r
+#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */\r
+#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */\r
+\r
+#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */\r
+#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */\r
+\r
+#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */\r
+#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */\r
+\r
+#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */\r
+#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */\r
+\r
+#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */\r
+#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */\r
+\r
+#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */\r
+#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */\r
+#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */\r
+#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */\r
+\r
+#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */\r
+#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */\r
+\r
+#define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */\r
+#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */\r
+\r
+#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */\r
+#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */\r
+#define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */\r
+\r
+#define EADC_SCTL0_EXTREN_Pos (4) /*!< EADC_T::SCTL0: EXTREN Position */\r
+#define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */\r
+\r
+#define EADC_SCTL0_EXTFEN_Pos (5) /*!< EADC_T::SCTL0: EXTFEN Position */\r
+#define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */\r
+\r
+#define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */\r
+#define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */\r
+#define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */\r
+#define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */\r
+\r
+#define EADC_SCTL0_INTPOS_Pos (22) /*!< EADC_T::SCTL0: INTPOS Position */\r
+#define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */\r
+\r
+#define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */\r
+#define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */\r
+\r
+#define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */\r
+#define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */\r
+#define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */\r
+\r
+#define EADC_SCTL1_EXTREN_Pos (4) /*!< EADC_T::SCTL1: EXTREN Position */\r
+#define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */\r
+\r
+#define EADC_SCTL1_EXTFEN_Pos (5) /*!< EADC_T::SCTL1: EXTFEN Position */\r
+#define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */\r
+\r
+#define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */\r
+#define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */\r
+#define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */\r
+#define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */\r
+\r
+#define EADC_SCTL1_INTPOS_Pos (22) /*!< EADC_T::SCTL1: INTPOS Position */\r
+#define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */\r
+\r
+#define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */\r
+#define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */\r
+\r
+#define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */\r
+#define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */\r
+#define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */\r
+\r
+#define EADC_SCTL2_EXTREN_Pos (4) /*!< EADC_T::SCTL2: EXTREN Position */\r
+#define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */\r
+\r
+#define EADC_SCTL2_EXTFEN_Pos (5) /*!< EADC_T::SCTL2: EXTFEN Position */\r
+#define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */\r
+\r
+#define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */\r
+#define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */\r
+#define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */\r
+#define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */\r
+\r
+#define EADC_SCTL2_INTPOS_Pos (22) /*!< EADC_T::SCTL2: INTPOS Position */\r
+#define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */\r
+\r
+#define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */\r
+#define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */\r
+\r
+#define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */\r
+#define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */\r
+#define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */\r
+\r
+#define EADC_SCTL3_EXTREN_Pos (4) /*!< EADC_T::SCTL3: EXTREN Position */\r
+#define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */\r
+\r
+#define EADC_SCTL3_EXTFEN_Pos (5) /*!< EADC_T::SCTL3: EXTFEN Position */\r
+#define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */\r
+\r
+#define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */\r
+#define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */\r
+#define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */\r
+#define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */\r
+\r
+#define EADC_SCTL3_INTPOS_Pos (22) /*!< EADC_T::SCTL3: INTPOS Position */\r
+#define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */\r
+\r
+#define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */\r
+#define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */\r
+\r
+#define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */\r
+#define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */\r
+#define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */\r
+\r
+#define EADC_SCTL4_EXTREN_Pos (4) /*!< EADC_T::SCTL4: EXTREN Position */\r
+#define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */\r
+\r
+#define EADC_SCTL4_EXTFEN_Pos (5) /*!< EADC_T::SCTL4: EXTFEN Position */\r
+#define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */\r
+\r
+#define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */\r
+#define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */\r
+#define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */\r
+#define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */\r
+\r
+#define EADC_SCTL4_INTPOS_Pos (22) /*!< EADC_T::SCTL4: INTPOS Position */\r
+#define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */\r
+\r
+#define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */\r
+#define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */\r
+#define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */\r
+\r
+#define EADC_SCTL5_EXTREN_Pos (4) /*!< EADC_T::SCTL5: EXTREN Position */\r
+#define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */\r
+\r
+#define EADC_SCTL5_EXTFEN_Pos (5) /*!< EADC_T::SCTL5: EXTFEN Position */\r
+#define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */\r
+\r
+#define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */\r
+#define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */\r
+#define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */\r
+#define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */\r
+\r
+#define EADC_SCTL5_INTPOS_Pos (22) /*!< EADC_T::SCTL5: INTPOS Position */\r
+#define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */\r
+\r
+#define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */\r
+#define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */\r
+#define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */\r
+\r
+#define EADC_SCTL6_EXTREN_Pos (4) /*!< EADC_T::SCTL6: EXTREN Position */\r
+#define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */\r
+\r
+#define EADC_SCTL6_EXTFEN_Pos (5) /*!< EADC_T::SCTL6: EXTFEN Position */\r
+#define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */\r
+\r
+#define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */\r
+#define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */\r
+#define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */\r
+#define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */\r
+\r
+#define EADC_SCTL6_INTPOS_Pos (22) /*!< EADC_T::SCTL6: INTPOS Position */\r
+#define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */\r
+\r
+#define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */\r
+#define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */\r
+#define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */\r
+\r
+#define EADC_SCTL7_EXTREN_Pos (4) /*!< EADC_T::SCTL7: EXTREN Position */\r
+#define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */\r
+\r
+#define EADC_SCTL7_EXTFEN_Pos (5) /*!< EADC_T::SCTL7: EXTFEN Position */\r
+#define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */\r
+\r
+#define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */\r
+#define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */\r
+#define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */\r
+#define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */\r
+\r
+#define EADC_SCTL7_INTPOS_Pos (22) /*!< EADC_T::SCTL7: INTPOS Position */\r
+#define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */\r
+\r
+#define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */\r
+#define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */\r
+#define EADC_SCTL8_CHSEL_Msk (0xful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */\r
+\r
+#define EADC_SCTL8_EXTREN_Pos (4) /*!< EADC_T::SCTL8: EXTREN Position */\r
+#define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */\r
+\r
+#define EADC_SCTL8_EXTFEN_Pos (5) /*!< EADC_T::SCTL8: EXTFEN Position */\r
+#define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */\r
+\r
+#define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */\r
+#define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */\r
+#define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */\r
+#define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */\r
+\r
+#define EADC_SCTL8_INTPOS_Pos (22) /*!< EADC_T::SCTL8: INTPOS Position */\r
+#define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */\r
+\r
+#define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */\r
+#define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */\r
+#define EADC_SCTL9_CHSEL_Msk (0xful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */\r
+\r
+#define EADC_SCTL9_EXTREN_Pos (4) /*!< EADC_T::SCTL9: EXTREN Position */\r
+#define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */\r
+\r
+#define EADC_SCTL9_EXTFEN_Pos (5) /*!< EADC_T::SCTL9: EXTFEN Position */\r
+#define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */\r
+\r
+#define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */\r
+#define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */\r
+#define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */\r
+#define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */\r
+\r
+#define EADC_SCTL9_INTPOS_Pos (22) /*!< EADC_T::SCTL9: INTPOS Position */\r
+#define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */\r
+\r
+#define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */\r
+#define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */\r
+#define EADC_SCTL10_CHSEL_Msk (0xful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */\r
+\r
+#define EADC_SCTL10_EXTREN_Pos (4) /*!< EADC_T::SCTL10: EXTREN Position */\r
+#define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */\r
+\r
+#define EADC_SCTL10_EXTFEN_Pos (5) /*!< EADC_T::SCTL10: EXTFEN Position */\r
+#define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */\r
+\r
+#define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */\r
+#define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */\r
+#define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */\r
+#define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */\r
+\r
+#define EADC_SCTL10_INTPOS_Pos (22) /*!< EADC_T::SCTL10: INTPOS Position */\r
+#define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */\r
+\r
+#define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */\r
+#define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */\r
+#define EADC_SCTL11_CHSEL_Msk (0xful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */\r
+\r
+#define EADC_SCTL11_EXTREN_Pos (4) /*!< EADC_T::SCTL11: EXTREN Position */\r
+#define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */\r
+\r
+#define EADC_SCTL11_EXTFEN_Pos (5) /*!< EADC_T::SCTL11: EXTFEN Position */\r
+#define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */\r
+\r
+#define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */\r
+#define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */\r
+#define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */\r
+#define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */\r
+\r
+#define EADC_SCTL11_INTPOS_Pos (22) /*!< EADC_T::SCTL11: INTPOS Position */\r
+#define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */\r
+\r
+#define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */\r
+#define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */\r
+#define EADC_SCTL12_CHSEL_Msk (0xful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */\r
+\r
+#define EADC_SCTL12_EXTREN_Pos (4) /*!< EADC_T::SCTL12: EXTREN Position */\r
+#define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */\r
+\r
+#define EADC_SCTL12_EXTFEN_Pos (5) /*!< EADC_T::SCTL12: EXTFEN Position */\r
+#define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */\r
+\r
+#define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */\r
+#define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */\r
+#define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */\r
+#define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */\r
+\r
+#define EADC_SCTL12_INTPOS_Pos (22) /*!< EADC_T::SCTL12: INTPOS Position */\r
+#define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */\r
+\r
+#define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */\r
+#define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */\r
+#define EADC_SCTL13_CHSEL_Msk (0xful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */\r
+\r
+#define EADC_SCTL13_EXTREN_Pos (4) /*!< EADC_T::SCTL13: EXTREN Position */\r
+#define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */\r
+\r
+#define EADC_SCTL13_EXTFEN_Pos (5) /*!< EADC_T::SCTL13: EXTFEN Position */\r
+#define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */\r
+\r
+#define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */\r
+#define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */\r
+#define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */\r
+#define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */\r
+\r
+#define EADC_SCTL13_INTPOS_Pos (22) /*!< EADC_T::SCTL13: INTPOS Position */\r
+#define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */\r
+\r
+#define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */\r
+#define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */\r
+#define EADC_SCTL14_CHSEL_Msk (0xful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */\r
+\r
+#define EADC_SCTL14_EXTREN_Pos (4) /*!< EADC_T::SCTL14: EXTREN Position */\r
+#define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */\r
+\r
+#define EADC_SCTL14_EXTFEN_Pos (5) /*!< EADC_T::SCTL14: EXTFEN Position */\r
+#define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */\r
+\r
+#define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */\r
+#define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */\r
+#define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */\r
+#define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */\r
+\r
+#define EADC_SCTL14_INTPOS_Pos (22) /*!< EADC_T::SCTL14: INTPOS Position */\r
+#define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */\r
+\r
+#define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */\r
+#define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */\r
+#define EADC_SCTL15_CHSEL_Msk (0xful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */\r
+\r
+#define EADC_SCTL15_EXTREN_Pos (4) /*!< EADC_T::SCTL15: EXTREN Position */\r
+#define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */\r
+\r
+#define EADC_SCTL15_EXTFEN_Pos (5) /*!< EADC_T::SCTL15: EXTFEN Position */\r
+#define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */\r
+\r
+#define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */\r
+#define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */\r
+\r
+#define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */\r
+#define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */\r
+\r
+#define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */\r
+#define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */\r
+\r
+#define EADC_SCTL15_INTPOS_Pos (22) /*!< EADC_T::SCTL15: INTPOS Position */\r
+#define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */\r
+\r
+#define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */\r
+#define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */\r
+#define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */\r
+#define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */\r
+\r
+#define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */\r
+#define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */\r
+#define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */\r
+#define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */\r
+#define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */\r
+#define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */\r
+#define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */\r
+#define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */\r
+#define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */\r
+#define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */\r
+#define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */\r
+#define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */\r
+#define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */\r
+#define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */\r
+#define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */\r
+#define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */\r
+#define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */\r
+#define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */\r
+#define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */\r
+#define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */\r
+\r
+#define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */\r
+#define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */\r
+#define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */\r
+#define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */\r
+#define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */\r
+#define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */\r
+#define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */\r
+#define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */\r
+#define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */\r
+#define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */\r
+#define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */\r
+#define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */\r
+#define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */\r
+#define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */\r
+#define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */\r
+#define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */\r
+#define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */\r
+#define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */\r
+#define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */\r
+#define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */\r
+\r
+#define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */\r
+#define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */\r
+#define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */\r
+#define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */\r
+#define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */\r
+#define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */\r
+#define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */\r
+#define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */\r
+#define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */\r
+#define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */\r
+#define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */\r
+#define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */\r
+#define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */\r
+#define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */\r
+#define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */\r
+#define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */\r
+#define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */\r
+#define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */\r
+#define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */\r
+#define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */\r
+\r
+#define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */\r
+#define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */\r
+#define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */\r
+#define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */\r
+#define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */\r
+#define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */\r
+#define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */\r
+#define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */\r
+#define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */\r
+#define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */\r
+#define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */\r
+#define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */\r
+#define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */\r
+#define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */\r
+#define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */\r
+#define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */\r
+#define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */\r
+#define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */\r
+#define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */\r
+#define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */\r
+\r
+#define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */\r
+#define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */\r
+\r
+#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */\r
+#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */\r
+\r
+#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */\r
+#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */\r
+\r
+#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */\r
+#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */\r
+\r
+#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */\r
+#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */\r
+\r
+#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */\r
+#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */\r
+\r
+#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */\r
+#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */\r
+\r
+#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */\r
+#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */\r
+\r
+#define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */\r
+#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */\r
+\r
+#define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */\r
+#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */\r
+\r
+#define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */\r
+#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */\r
+\r
+#define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */\r
+#define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */\r
+\r
+#define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */\r
+#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */\r
+\r
+#define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */\r
+#define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */\r
+\r
+#define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */\r
+#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */\r
+\r
+#define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */\r
+#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */\r
+\r
+#define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */\r
+#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */\r
+\r
+#define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */\r
+#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */\r
+\r
+#define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */\r
+#define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */\r
+\r
+#define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */\r
+#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */\r
+\r
+#define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */\r
+#define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */\r
+\r
+#define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */\r
+#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */\r
+\r
+#define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */\r
+#define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */\r
+\r
+#define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */\r
+#define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */\r
+\r
+#define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */\r
+#define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */\r
+\r
+#define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */\r
+#define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */\r
+\r
+#define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */\r
+#define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */\r
+\r
+#define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */\r
+#define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */\r
+\r
+#define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */\r
+#define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */\r
+\r
+#define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */\r
+#define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */\r
+\r
+#define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */\r
+#define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */\r
+\r
+#define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */\r
+#define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */\r
+\r
+#define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */\r
+#define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */\r
+\r
+#define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */\r
+#define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */\r
+\r
+#define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */\r
+#define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */\r
+\r
+#define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */\r
+#define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */\r
+\r
+#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */\r
+#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */\r
+\r
+#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */\r
+#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */\r
+\r
+#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */\r
+#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */\r
+\r
+#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */\r
+#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */\r
+\r
+#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */\r
+#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */\r
+\r
+#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */\r
+#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */\r
+\r
+#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */\r
+#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */\r
+\r
+#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */\r
+#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */\r
+\r
+#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */\r
+#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */\r
+\r
+#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */\r
+#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */\r
+\r
+#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */\r
+#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */\r
+\r
+#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */\r
+#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */\r
+\r
+#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */\r
+#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */\r
+\r
+#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */\r
+#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */\r
+\r
+#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */\r
+#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */\r
+\r
+#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */\r
+#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */\r
+\r
+#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */\r
+#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */\r
+\r
+#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */\r
+#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */\r
+\r
+#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */\r
+#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */\r
+\r
+#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */\r
+#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */\r
+\r
+#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */\r
+#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */\r
+\r
+#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */\r
+#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */\r
+\r
+#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */\r
+#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */\r
+\r
+#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */\r
+#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */\r
+\r
+#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */\r
+#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */\r
+\r
+#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */\r
+#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */\r
+\r
+#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */\r
+#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */\r
+\r
+#define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */\r
+#define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */\r
+\r
+#define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */\r
+#define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */\r
+\r
+#define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */\r
+#define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */\r
+\r
+#define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */\r
+#define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */\r
+\r
+#define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */\r
+#define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */\r
+\r
+#define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */\r
+#define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */\r
+\r
+#define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */\r
+#define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */\r
+\r
+#define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */\r
+#define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */\r
+\r
+#define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */\r
+#define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */\r
+\r
+#define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */\r
+#define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */\r
+\r
+#define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */\r
+#define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */\r
+\r
+#define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */\r
+#define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */\r
+\r
+#define EADC_PWRM_PWUPRDY_Pos (0) /*!< EADC_T::PWRM: PWUPRDY Position */\r
+#define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) /*!< EADC_T::PWRM: PWUPRDY Mask */\r
+\r
+#define EADC_PWRM_PWUCALEN_Pos (1) /*!< EADC_T::PWRM: PWUCALEN Position */\r
+#define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) /*!< EADC_T::PWRM: PWUCALEN Mask */\r
+\r
+#define EADC_PWRM_PWDMOD_Pos (2) /*!< EADC_T::PWRM: PWDMOD Position */\r
+#define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) /*!< EADC_T::PWRM: PWDMOD Mask */\r
+\r
+#define EADC_PWRM_LDOSUT_Pos (8) /*!< EADC_T::PWRM: LDOSUT Position */\r
+#define EADC_PWRM_LDOSUT_Msk (0xffful << EADC_PWRM_LDOSUT_Pos) /*!< EADC_T::PWRM: LDOSUT Mask */\r
+\r
+#define EADC_CALCTL_CALSTART_Pos (1) /*!< EADC_T::CALCTL: CALSTART Position */\r
+#define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) /*!< EADC_T::CALCTL: CALSTART Mask */\r
+\r
+#define EADC_CALCTL_CALDONE_Pos (2) /*!< EADC_T::CALCTL: CALDONE Position */\r
+#define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) /*!< EADC_T::CALCTL: CALDONE Mask */\r
+\r
+#define EADC_CALCTL_CALSEL_Pos (3) /*!< EADC_T::CALCTL: CALSEL Position */\r
+#define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) /*!< EADC_T::CALCTL: CALSEL Mask */\r
+\r
+#define EADC_CALDWRD_CALWORD_Pos (0) /*!< EADC_T::CALDWRD: CALWORD Position */\r
+#define EADC_CALDWRD_CALWORD_Msk (0x7ful << EADC_CALDWRD_CALWORD_Pos) /*!< EADC_T::CALDWRD: CALWORD Mask */\r
+\r
+/**@}*/ /* EADC_CONST */\r
+/**@}*/ /* end of EADC register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+\r
+#endif /* __EADC_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file ebi_reg.h\r
+ * @version V1.00\r
+ * @brief EBI register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __EBI_REG_H__\r
+#define __EBI_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- External Bus Interface Controller -------------------------*/\r
+/**\r
+ @addtogroup EBI External Bus Interface Controller(EBI)\r
+ Memory Mapped Structure for EBI Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var EBI_T::CTL0\r
+ * Offset: 0x00 External Bus Interface Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |EN |EBI Enable Bit\r
+ * | | |This bit is the functional enable bit for EBI.\r
+ * | | |0 = EBI function Disabled.\r
+ * | | |1 = EBI function Enabled.\r
+ * |[1] |DW16 |EBI Data Width 16-bit Select\r
+ * | | |This bit defines if the EBI data width is 8-bit or 16-bit.\r
+ * | | |0 = EBI data width is 8-bit.\r
+ * | | |1 = EBI data width is 16-bit.\r
+ * |[2] |CSPOLINV |Chip Select Pin Polar Inverse\r
+ * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).\r
+ * | | |0 = Chip select pin (EBI_nCS) is active low.\r
+ * | | |1 = Chip select pin (EBI_nCS) is active high.\r
+ * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit\r
+ * | | |0 = Address/Data Bus Separating Mode Disabled.\r
+ * | | |1 = Address/Data Bus Separating Mode Enabled.\r
+ * |[4] |CACCESS |Continuous Data Access Mode\r
+ * | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.\r
+ * | | |0 = Continuous data access mode Disabled.\r
+ * | | |1 = Continuous data access mode Enabled.\r
+ * |[10:8] |MCLKDIV |External Output Clock Divider\r
+ * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:\r
+ * | | |000 = HCLK/1.\r
+ * | | |001 = HCLK/2.\r
+ * | | |010 = HCLK/4.\r
+ * | | |011 = HCLK/8.\r
+ * | | |100 = HCLK/16.\r
+ * | | |101 = HCLK/32.\r
+ * | | |110 = HCLK/64.\r
+ * | | |111 = HCLK/128.\r
+ * |[18:16] |TALE |Extend Time of ALE\r
+ * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\r
+ * | | |tALE = (TALE+1)*EBI_MCLK.\r
+ * | | |Note: This field only available in EBI_CTL0 register\r
+ * @var EBI_T::TCTL0\r
+ * Offset: 0x04 External Bus Interface Timing Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:3] |TACC |EBI Data Access Time\r
+ * | | |TACC define data access time (tACC).\r
+ * | | |tACC = (TACC+1) * EBI_MCLK.\r
+ * |[10:8] |TAHD |EBI Data Access Hold Time\r
+ * | | |TAHD define data access hold time (tAHD).\r
+ * | | |tAHD = (TAHD+1) * EBI_MCLK.\r
+ * |[15:12] |W2X |Idle Cycle After Write\r
+ * | | |This field defines the number of W2X idle cycle.\r
+ * | | |W2X idle cycle = (W2X * EBI_MCLK).\r
+ * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.\r
+ * |[22] |RAHDOFF |Access Hold Time Disable Control When Read\r
+ * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.\r
+ * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.\r
+ * |[23] |WAHDOFF |Access Hold Time Disable Control When Write\r
+ * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.\r
+ * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.\r
+ * |[27:24] |R2R |Idle Cycle Between Read-to-read\r
+ * | | |This field defines the number of R2R idle cycle.\r
+ * | | |R2R idle cycle = (R2R * EBI_MCLK).\r
+ * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.\r
+ */\r
+ __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */\r
+ __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */\r
+ __I uint32_t RESERVE0[2];\r
+ __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */\r
+ __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */\r
+ __I uint32_t RESERVE1[2];\r
+ __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */\r
+ __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */\r
+\r
+} EBI_T;\r
+\r
+/**\r
+ @addtogroup EBI_CONST EBI Bit Field Definition\r
+ Constant Definitions for EBI Controller\r
+@{ */\r
+\r
+#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */\r
+#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL0: EN Mask */\r
+\r
+#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */\r
+#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */\r
+\r
+#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */\r
+#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */\r
+\r
+#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */\r
+#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */\r
+\r
+#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */\r
+#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */\r
+\r
+#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */\r
+#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */\r
+\r
+#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */\r
+#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */\r
+\r
+#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */\r
+#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */\r
+\r
+#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */\r
+#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */\r
+\r
+#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */\r
+#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */\r
+\r
+#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */\r
+#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */\r
+\r
+#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */\r
+#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */\r
+\r
+#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */\r
+#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */\r
+\r
+/**@}*/ /* EBI_CONST */\r
+/**@}*/ /* end of EBI register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __EBI_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file ecap_reg.h\r
+ * @version V1.00\r
+ * @brief ECAP register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __ECAP_REG_H__\r
+#define __ECAP_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Enhanced Input Capture Timer -------------------------*/\r
+/**\r
+ @addtogroup ECAP Enhanced Input Capture Timer(ECAP)\r
+ Memory Mapped Structure for ECAP Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+ /**\r
+ * @var ECAP_T::CNT\r
+ * Offset: 0x00 Input Capture Counter (24-bit up counter)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[23:0] |CNT |Input Capture Timer/Counter\r
+ * | | |The input Capture Timer/Counter is a 24-bit up-counting counter\r
+ * | | |The clock source for the counter is from the clock divider\r
+ * @var ECAP_T::HLD0\r
+ * Offset: 0x04 Input Capture Hold Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[23:0] |HOLD |Input Capture Counter Hold Register\r
+ * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register\r
+ * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.\r
+ * @var ECAP_T::HLD1\r
+ * Offset: 0x08 Input Capture Hold Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[23:0] |HOLD |Input Capture Counter Hold Register\r
+ * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register\r
+ * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.\r
+ * @var ECAP_T::HLD2\r
+ * Offset: 0x0C Input Capture Hold Register 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[23:0] |HOLD |Input Capture Counter Hold Register\r
+ * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register\r
+ * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.\r
+ * @var ECAP_T::CNTCMP\r
+ * Offset: 0x10 Input Capture Compare Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[23:0] |CNTCMP |Input Capture Counter Compare Register\r
+ * | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).\r
+ * | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.\r
+ * @var ECAP_T::CTL0\r
+ * Offset: 0x14 Input Capture Control Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection\r
+ * | | |To determine the sampling frequency of the Noise Filter clock\r
+ * | | |000 = CAP_CLK.\r
+ * | | |001 = CAP_CLK/2.\r
+ * | | |010 = CAP_CLK/4.\r
+ * | | |011 = CAP_CLK/16.\r
+ * | | |100 = CAP_CLK/32.\r
+ * | | |101 = CAP_CLK/64.\r
+ * |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control\r
+ * | | |0 = Noise filter of Input Capture Enabled.\r
+ * | | |1 = Noise filter of Input Capture Disabled (Bypass).\r
+ * |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control\r
+ * | | |0 = IC0 input to Input Capture Unit Disabled.\r
+ * | | |1 = IC0 input to Input Capture Unit Enabled.\r
+ * |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control\r
+ * | | |0 = IC1 input to Input Capture Unit Disabled.\r
+ * | | |1 = IC1 input to Input Capture Unit Enabled.\r
+ * |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control\r
+ * | | |0 = IC2 input to Input Capture Unit Disabled.\r
+ * | | |1 = IC2 input to Input Capture Unit Enabled.\r
+ * |[9:8] |CAPSEL0 |CAP0 Input Source Selection\r
+ * | | |00 = CAP0 input is from port pin ICAP0.\r
+ * | | |01 = Reserved.\r
+ * | | |10 = CAP0 input is from signal CHA of QEI controller unit n.\r
+ * | | |11 = Reserved.\r
+ * | | |Note: Input capture unit n matches QEIn, where n = 0~1.\r
+ * |[11:10] |CAPSEL1 |CAP1 Input Source Selection\r
+ * | | |00 = CAP1 input is from port pin ICAP1.\r
+ * | | |01 = Reserved.\r
+ * | | |10 = CAP1 input is from signal CHB of QEI controller unit n.\r
+ * | | |11 = Reserved.\r
+ * | | |Note: Input capture unit n matches QEIn, where n = 0~1.\r
+ * |[13:12] |CAPSEL2 |CAP2 Input Source Selection\r
+ * | | |00 = CAP2 input is from port pin ICAP2.\r
+ * | | |01 = Reserved.\r
+ * | | |10 = CAP2 input is from signal CHX of QEI controller unit n.\r
+ * | | |11 = Reserved.\r
+ * | | |Note: Input capture unit n matches QEIn, where n = 0~1.\r
+ * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control\r
+ * | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.\r
+ * | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.\r
+ * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control\r
+ * | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.\r
+ * | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.\r
+ * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control\r
+ * | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.\r
+ * | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.\r
+ * |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control\r
+ * | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.\r
+ * | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.\r
+ * |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control\r
+ * | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.\r
+ * | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.\r
+ * |[24] |CNTEN |Input Capture Counter Start Counting Control\r
+ * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .\r
+ * | | |0 = ECAP_CNT stop counting.\r
+ * | | |1 = ECAP_CNT starts up-counting.\r
+ * |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control\r
+ * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.\r
+ * | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.\r
+ * | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.\r
+ * |[28] |CMPEN |Compare Function Enable Control\r
+ * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.\r
+ * | | |0 = The compare function Disabled.\r
+ * | | |1 = The compare function Enabled.\r
+ * |[29] |CAPEN |Input Capture Timer/Counter Enable Control\r
+ * | | |0 = Input Capture function Disabled.\r
+ * | | |1 = Input Capture function Enabled.\r
+ * @var ECAP_T::CTL1\r
+ * Offset: 0x18 Input Capture Control Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection\r
+ * | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change\r
+ * | | |00 = Detect rising edge only.\r
+ * | | |01 = Detect falling edge only.\r
+ * | | |1x = Detect both rising and falling edge.\r
+ * |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection\r
+ * | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change\r
+ * | | |00 = Detect rising edge only.\r
+ * | | |01 = Detect falling edge only.\r
+ * | | |1x = Detect both rising and falling edge.\r
+ * |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection\r
+ * | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes\r
+ * | | |00 = Detect rising edge only.\r
+ * | | |01 = Detect falling edge only.\r
+ * | | |1x = Detect both rising and falling edge.\r
+ * |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit\r
+ * | | |0 = The reload triggered by Event CAPTE0 Disabled.\r
+ * | | |1 = The reload triggered by Event CAPTE0 Enabled.\r
+ * |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit\r
+ * | | |0 = The reload triggered by Event CAPTE1 Disabled.\r
+ * | | |1 = The reload triggered by Event CAPTE1 Enabled.\r
+ * |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit\r
+ * | | |0 = The reload triggered by Event CAPTE2 Disabled.\r
+ * | | |1 = The reload triggered by Event CAPTE2 Enabled.\r
+ * |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit\r
+ * | | |0 = The reload triggered by CAPOV Disabled.\r
+ * | | |1 = The reload triggered by CAPOV Enabled.\r
+ * |[14:12] |CLKSEL |Capture Timer Clock Divide Selection\r
+ * | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].\r
+ * | | |000 = CAP_CLK/1.\r
+ * | | |001 = CAP_CLK/4.\r
+ * | | |010 = CAP_CLK/16.\r
+ * | | |011 = CAP_CLK/32.\r
+ * | | |100 = CAP_CLK/64.\r
+ * | | |101 = CAP_CLK/96.\r
+ * | | |110 = CAP_CLK/112.\r
+ * | | |111 = CAP_CLK/128.\r
+ * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection\r
+ * | | |Select the capture timer/counter clock source.\r
+ * | | |00 = CAP_CLK (default).\r
+ * | | |01 = CAP0.\r
+ * | | |10 = CAP1.\r
+ * | | |11 = CAP2.\r
+ * |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control\r
+ * | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.\r
+ * | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.\r
+ * |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control\r
+ * | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.\r
+ * | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.\r
+ * |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control\r
+ * | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.\r
+ * | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.\r
+ * @var ECAP_T::STATUS\r
+ * Offset: 0x1C Input Capture Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag\r
+ * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.\r
+ * | | |0 = No valid edge change has been detected at CAP0 input since last clear.\r
+ * | | |1 = At least a valid edge change has been detected at CAP0 input since last clear.\r
+ * | | |Note: This bit is only cleared by writing 1 to it.\r
+ * |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag\r
+ * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.\r
+ * | | |0 = No valid edge change has been detected at CAP1 input since last clear.\r
+ * | | |1 = At least a valid edge change has been detected at CAP1 input since last clear.\r
+ * | | |Note: This bit is only cleared by writing 1 to it.\r
+ * |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag\r
+ * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.\r
+ * | | |0 = No valid edge change has been detected at CAP2 input since last clear.\r
+ * | | |1 = At least a valid edge change has been detected at CAP2 input since last clear.\r
+ * | | |Note: This bit is only cleared by writing 1 to it.\r
+ * |[4] |CAPCMPF |Input Capture Compare-match Flag\r
+ * | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\r
+ * | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.\r
+ * | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.\r
+ * | | |Note: This bit is only cleared by writing 1 to it.\r
+ * |[5] |CAPOVF |Input Capture Counter Overflow Flag\r
+ * | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\r
+ * | | |0 = No overflow event has occurred since last clear.\r
+ * | | |1 = Overflow event(s) has/have occurred since last clear.\r
+ * | | |Note: This bit is only cleared by writing 1 to it.\r
+ * |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only)\r
+ * | | |Reflecting the value of input channel 0, CAP0\r
+ * | | |(The bit is read only and write is ignored)\r
+ * |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only)\r
+ * | | |Reflecting the value of input channel 1, CAP1\r
+ * | | |(The bit is read only and write is ignored)\r
+ * |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only)\r
+ * | | |Reflecting the value of input channel 2, CAP2.\r
+ * | | |(The bit is read only and write is ignored)\r
+ */\r
+ __IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */\r
+ __IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */\r
+ __IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */\r
+ __IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */\r
+ __IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */\r
+ __IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */\r
+ __IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */\r
+ __IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */\r
+\r
+} ECAP_T;\r
+\r
+/**\r
+ @addtogroup ECAP_CONST ECAP Bit Field Definition\r
+ Constant Definitions for ECAP Controller\r
+@{ */\r
+\r
+#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */\r
+#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */\r
+\r
+#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */\r
+#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */\r
+\r
+#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */\r
+#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */\r
+\r
+#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */\r
+#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */\r
+\r
+#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */\r
+#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */\r
+\r
+#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */\r
+#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */\r
+\r
+#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */\r
+#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */\r
+\r
+#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */\r
+#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */\r
+\r
+#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */\r
+#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */\r
+\r
+#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */\r
+#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */\r
+\r
+#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */\r
+#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */\r
+\r
+#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */\r
+#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */\r
+\r
+#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */\r
+#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */\r
+\r
+#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */\r
+#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */\r
+\r
+#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */\r
+#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */\r
+\r
+#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */\r
+#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */\r
+\r
+#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */\r
+#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */\r
+\r
+#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */\r
+#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */\r
+\r
+#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */\r
+#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */\r
+\r
+#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */\r
+#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */\r
+\r
+#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */\r
+#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */\r
+\r
+#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */\r
+#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */\r
+\r
+#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */\r
+#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */\r
+\r
+#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */\r
+#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */\r
+\r
+#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */\r
+#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */\r
+\r
+#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */\r
+#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */\r
+\r
+#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */\r
+#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */\r
+\r
+#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */\r
+#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */\r
+\r
+#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */\r
+#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */\r
+\r
+#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */\r
+#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */\r
+\r
+#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */\r
+#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */\r
+\r
+#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */\r
+#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */\r
+\r
+#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */\r
+#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */\r
+\r
+#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */\r
+#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */\r
+\r
+#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */\r
+#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */\r
+\r
+#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */\r
+#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */\r
+\r
+#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */\r
+#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */\r
+\r
+#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */\r
+#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */\r
+\r
+#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */\r
+#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */\r
+\r
+#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */\r
+#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */\r
+\r
+#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */\r
+#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */\r
+\r
+#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */\r
+#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */\r
+\r
+/**@}*/ /* ECAP_CONST */\r
+/**@}*/ /* end of ECAP register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __ECAP_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file epwm_reg.h\r
+ * @version V1.00\r
+ * @brief EPWM register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __EPWM_REG_H__\r
+#define __EPWM_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- Enhanced Pulse Width Modulation Controller -------------------------*/\r
+/**\r
+ @addtogroup EPWM Enhanced Pulse Width Modulation Controller(EPWM)\r
+ Memory Mapped Structure for EPWM Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+ /**\r
+ * @var ECAPDAT_T::RCAPDAT\r
+ * Offset: 0x20C EPWM Rising Capture Data Register 0~5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only)\r
+ * | | |When rising capture condition happened, the EPWM counter value will be saved in this register.\r
+ * @var ECAPDAT_T::FCAPDAT\r
+ * Offset: 0x210 EPWM Falling Capture Data Register 0~5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only)\r
+ * | | |When falling capture condition happened, the EPWM counter value will be saved in this register.\r
+ */\r
+ __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */\r
+ __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */\r
+} ECAPDAT_T;\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var EPWM_T::CTL0\r
+ * Offset: 0x00 EPWM Control Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CTRLD0 |Center Re-load\r
+ * | | |In up-down counter type, PERIOD0 register will load to PBUF0 register at the end point of each period.\r
+ * | | |CMPDAT0 register will load to CMPBUF0 register at the center point of a period.\r
+ * |[1] |CTRLD1 |Center Re-load\r
+ * | | |In up-down counter type, PERIOD1 register will load to PBUF1 register at the end point of each period.\r
+ * | | |CMPDAT1 register will load to CMPBUF1 register at the center point of a period.\r
+ * |[2] |CTRLD2 |Center Re-load\r
+ * | | |In up-down counter type, PERIOD2 register will load to PBUF2 register at the end point of each period.\r
+ * | | |CMPDAT2 register will load to CMPBUF2 register at the center point of a period.\r
+ * |[3] |CTRLD3 |Center Re-load\r
+ * | | |In up-down counter type, PERIOD3 register will load to PBUF3 register at the end point of each period.\r
+ * | | |CMPDAT3 register will load to CMPBUF3 register at the center point of a period.\r
+ * |[4] |CTRLD4 |Center Re-load\r
+ * | | |In up-down counter type, PERIOD4 register will load to PBUF4 register at the end point of each period.\r
+ * | | |CMPDAT4 register will load to CMPBUF4 register at the center point of a period.\r
+ * |[5] |CTRLD5 |Center Re-load\r
+ * | | |In up-down counter type, PERIOD5 register will load to PBUF5 register at the end point of each period.\r
+ * | | |CMPDAT5 register will load to CMPBUF5 register at the center point of a period.\r
+ * |[8] |WINLDEN0 |Window Load Enable Bits\r
+ * | | |0 = PERIOD0 register will load to PBUF0 register at the end point of each period.\r
+ * | | |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit.\r
+ * | | |1 = PERIOD0 register will load to PBUF0 and CMPDAT0 registers will load to CMPBUF0 register at the end point of each period when valid reload window is set.\r
+ * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.\r
+ * |[9] |WINLDEN1 |Window Load Enable Bits\r
+ * | | |0 = PERIOD1 register will load to PBUF1 register at the end point of each period.\r
+ * | | |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit.\r
+ * | | |1 = PERIOD1 register will load to PBUF1 and CMPDAT1 registers will load to CMPBUF1 register at the end point of each period when valid reload window is set.\r
+ * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.\r
+ * |[10] |WINLDEN2 |Window Load Enable Bits\r
+ * | | |0 = PERIOD2 register will load to PBUF2 register at the end point of each period.\r
+ * | | |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit.\r
+ * | | |1 = PERIOD2 register will load to PBUF2 and CMPDAT2 registers will load to CMPBUF2 register at the end point of each period when valid reload window is set.\r
+ * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.\r
+ * |[11] |WINLDEN3 |Window Load Enable Bits\r
+ * | | |0 = PERIOD3 register will load to PBUF3 register at the end point of each period.\r
+ * | | |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit.\r
+ * | | |1 = PERIOD3 register will load to PBUF3 and CMPDAT3 registers will load to CMPBUF3 register at the end point of each period when valid reload window is set.\r
+ * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.\r
+ * |[12] |WINLDEN4 |Window Load Enable Bits\r
+ * | | |0 = PERIOD4 register will load to PBUF4 register at the end point of each period.\r
+ * | | |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit.\r
+ * | | |1 = PERIOD4 register will load to PBUF4 and CMPDAT4 registers will load to CMPBUF4 register at the end point of each period when valid reload window is set.\r
+ * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.\r
+ * |[13] |WINLDEN5 |Window Load Enable Bits\r
+ * | | |0 = PERIOD5 register will load to PBUF5 register at the end point of each period.\r
+ * | | |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit.\r
+ * | | |1 = PERIOD5 register will load to PBUF5 and CMPDAT5 registers will load to CMPBUF5 register at the end point of each period when valid reload window is set.\r
+ * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.\r
+ * |[16] |IMMLDEN0 |Immediately Load Enable Bits\r
+ * | | |0 = PERIOD0 register will load to PBUF0 register at the end point of each period.\r
+ * | | |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit.\r
+ * | | |1 = PERIOD0/CMPDAT0 registers will load to PBUF0 and CMPBUF0 register immediately when software update PERIOD0/CMPDAT0 register.\r
+ * | | |Note: If IMMLDEN0 bit is enabled, WINLDEN0 bit and CTRLD0 bits will be invalid.\r
+ * |[17] |IMMLDEN1 |Immediately Load Enable Bits\r
+ * | | |0 = PERIOD1 register will load to PBUF1 register at the end point of each period.\r
+ * | | |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit.\r
+ * | | |1 = PERIOD1/CMPDAT1 registers will load to PBUF1 and CMPBUF1 register immediately when software update PERIOD1/CMPDAT1 register.\r
+ * | | |Note: If IMMLDEN1 bit is enabled, WINLDEN1 bit and CTRLD1 bits will be invalid.\r
+ * |[18] |IMMLDEN2 |Immediately Load Enable Bits\r
+ * | | |0 = PERIOD2 register will load to PBUF2 register at the end point of each period.\r
+ * | | |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit.\r
+ * | | |1 = PERIOD2/CMPDAT2 registers will load to PBUF2 and CMPBUF2 register immediately when software update PERIOD2/CMPDAT2 register.\r
+ * | | |Note: If IMMLDEN2 bit is enabled, WINLDEN2 bit and CTRLD2 bits will be invalid.\r
+ * |[19] |IMMLDEN3 |Immediately Load Enable Bits\r
+ * | | |0 = PERIOD3 register will load to PBUF3 register at the end point of each period.\r
+ * | | |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit.\r
+ * | | |1 = PERIOD3/CMPDAT3 registers will load to PBUF3 and CMPBUF3 register immediately when software update PERIOD3/CMPDAT3 register.\r
+ * | | |Note: If IMMLDEN3 bit is enabled, WINLDEN3 bit and CTRLD3 bits will be invalid.\r
+ * |[20] |IMMLDEN4 |Immediately Load Enable Bits\r
+ * | | |0 = PERIOD4 register will load to PBUF4 register at the end point of each period.\r
+ * | | |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit.\r
+ * | | |1 = PERIOD4/CMPDAT4 registers will load to PBUF4 and CMPBUF4 register immediately when software update PERIOD4/CMPDAT4 register.\r
+ * | | |Note: If IMMLDEN4 bit is enabled, WINLDEN4 bit and CTRLD4 bits will be invalid.\r
+ * |[21] |IMMLDEN5 |Immediately Load Enable Bits\r
+ * | | |0 = PERIOD5 register will load to PBUF5 register at the end point of each period.\r
+ * | | |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit.\r
+ * | | |1 = PERIOD5/CMPDAT5 registers will load to PBUF5 and CMPBUF5 register immediately when software update PERIOD5/CMPDAT5 register.\r
+ * | | |Note: If IMMLDEN5 bit is enabled, WINLDEN5 bit and CTRLD5 bits will be invalid.\r
+ * |[24] |GROUPEN |Group Function Enable Bit\r
+ * | | |0 = The output waveform of each EPWM channel are independent.\r
+ * | | |1 = Unify the EPWMx_CH2 and EPWMx_CH4 to output the same waveform as EPWMx_CH0 and unify the EPWMx_CH3 and EPWMx_CH5 to output the same waveform as EPWMx_CH1.\r
+ * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)\r
+ * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode.\r
+ * | | |0 = ICE debug mode counter halt disable.\r
+ * | | |1 = ICE debug mode counter halt enable.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)\r
+ * | | |0 = ICE debug mode acknowledgement effects EPWM output.\r
+ * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged.\r
+ * | | |1 = ICE debug mode acknowledgement disabled.\r
+ * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * @var EPWM_T::CTL1\r
+ * Offset: 0x04 EPWM Control Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type\r
+ * | | |00 = Up counter type (supports in capture mode).\r
+ * | | |01 = Down count type (supports in capture mode).\r
+ * | | |10 = Up-down counter type.\r
+ * | | |11 = Reserved.\r
+ * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type\r
+ * | | |00 = Up counter type (supports in capture mode).\r
+ * | | |01 = Down count type (supports in capture mode).\r
+ * | | |10 = Up-down counter type.\r
+ * | | |11 = Reserved.\r
+ * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type\r
+ * | | |00 = Up counter type (supports in capture mode).\r
+ * | | |01 = Down count type (supports in capture mode).\r
+ * | | |10 = Up-down counter type.\r
+ * | | |11 = Reserved.\r
+ * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type\r
+ * | | |00 = Up counter type (supports in capture mode).\r
+ * | | |01 = Down count type (supports in capture mode).\r
+ * | | |10 = Up-down counter type.\r
+ * | | |11 = Reserved.\r
+ * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type\r
+ * | | |00 = Up counter type (supports in capture mode).\r
+ * | | |01 = Down count type (supports in capture mode).\r
+ * | | |10 = Up-down counter type.\r
+ * | | |11 = Reserved.\r
+ * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type\r
+ * | | |00 = Up counter type (supports in capture mode).\r
+ * | | |01 = Down count type (supports in capture mode).\r
+ * | | |10 = Up-down counter type.\r
+ * | | |11 = Reserved.\r
+ * |[16] |CNTMODE0 |EPWM Counter Mode\r
+ * | | |0 = Auto-reload mode.\r
+ * | | |1 = One-shot mode.\r
+ * |[17] |CNTMODE1 |EPWM Counter Mode\r
+ * | | |0 = Auto-reload mode.\r
+ * | | |1 = One-shot mode.\r
+ * |[18] |CNTMODE2 |EPWM Counter Mode\r
+ * | | |0 = Auto-reload mode.\r
+ * | | |1 = One-shot mode.\r
+ * |[19] |CNTMODE3 |EPWM Counter Mode\r
+ * | | |0 = Auto-reload mode.\r
+ * | | |1 = One-shot mode.\r
+ * |[20] |CNTMODE4 |EPWM Counter Mode\r
+ * | | |0 = Auto-reload mode.\r
+ * | | |1 = One-shot mode.\r
+ * |[21] |CNTMODE5 |EPWM Counter Mode\r
+ * | | |0 = Auto-reload mode.\r
+ * | | |1 = One-shot mode.\r
+ * |[24] |OUTMODE0 |EPWM Output Mode\r
+ * | | |Each bit n controls the output mode of corresponding EPWM channel n.\r
+ * | | |0 = EPWM independent mode.\r
+ * | | |1 = EPWM complementary mode.\r
+ * | | |Note: When operating in group function, these bits must all set to the same mode.\r
+ * |[25] |OUTMODE2 |EPWM Output Mode\r
+ * | | |Each bit n controls the output mode of corresponding EPWM channel n.\r
+ * | | |0 = EPWM independent mode.\r
+ * | | |1 = EPWM complementary mode.\r
+ * | | |Note: When operating in group function, these bits must all set to the same mode.\r
+ * |[26] |OUTMODE4 |EPWM Output Mode\r
+ * | | |Each bit n controls the output mode of corresponding EPWM channel n.\r
+ * | | |0 = EPWM independent mode.\r
+ * | | |1 = EPWM complementary mode.\r
+ * | | |Note: When operating in group function, these bits must all set to the same mode.\r
+ * @var EPWM_T::SYNC\r
+ * Offset: 0x08 EPWM Synchronization Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PHSEN0 |SYNC Phase Enable Bits\r
+ * | | |0 = EPWM counter disable to load PHS value.\r
+ * | | |1 = EPWM counter enable to load PHS value.\r
+ * |[1] |PHSEN2 |SYNC Phase Enable Bits\r
+ * | | |0 = EPWM counter disable to load PHS value.\r
+ * | | |1 = EPWM counter enable to load PHS value.\r
+ * |[2] |PHSEN4 |SYNC Phase Enable Bits\r
+ * | | |0 = EPWM counter disable to load PHS value.\r
+ * | | |1 = EPWM counter enable to load PHS value.\r
+ * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection\r
+ * | | |00 = Synchronize source from SYNC_IN or SWSYNC.\r
+ * | | |01 = Counter equal to 0.\r
+ * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.\r
+ * | | |11 = SYNC_OUT will not be generated.\r
+ * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection\r
+ * | | |00 = Synchronize source from SYNC_IN or SWSYNC.\r
+ * | | |01 = Counter equal to 0.\r
+ * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.\r
+ * | | |11 = SYNC_OUT will not be generated.\r
+ * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection\r
+ * | | |00 = Synchronize source from SYNC_IN or SWSYNC.\r
+ * | | |01 = Counter equal to 0.\r
+ * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.\r
+ * | | |11 = SYNC_OUT will not be generated.\r
+ * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits\r
+ * | | |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled.\r
+ * | | |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled.\r
+ * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection\r
+ * | | |000 = Filter clock = HCLK.\r
+ * | | |001 = Filter clock = HCLK/2.\r
+ * | | |010 = Filter clock = HCLK/4.\r
+ * | | |011 = Filter clock = HCLK/8.\r
+ * | | |100 = Filter clock = HCLK/16.\r
+ * | | |101 = Filter clock = HCLK/32.\r
+ * | | |110 = Filter clock = HCLK/64.\r
+ * | | |111 = Filter clock = HCLK/128.\r
+ * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count\r
+ * | | |The register bits control the counter number of edge detector.\r
+ * |[23] |SINPINV |SYNC Input Pin Inverse\r
+ * | | |0 = The state of pin EPWM0_SYNC_IN is passed to the negative edge detector.\r
+ * | | |1 = The inverse state of pin EPWM0_SYNC_IN is passed to the negative edge detector.\r
+ * |[24] |PHSDIR0 |EPWM Phase Direction Control\r
+ * | | |0 = Control EPWM counter count decrement after synchronizing.\r
+ * | | |1 = Control EPWM counter count increment after synchronizing.\r
+ * |[25] |PHSDIR2 |EPWM Phase Direction Control\r
+ * | | |0 = Control EPWM counter count decrement after synchronizing.\r
+ * | | |1 = Control EPWM counter count increment after synchronizing.\r
+ * |[26] |PHSDIR4 |EPWM Phase Direction Control\r
+ * | | |0 = Control EPWM counter count decrement after synchronizing.\r
+ * | | |1 = Control EPWM counter count increment after synchronizing.\r
+ * @var EPWM_T::SWSYNC\r
+ * Offset: 0x0C EPWM Software Control Synchronization Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SWSYNC0 |Software SYNC Function\r
+ * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.\r
+ * |[1] |SWSYNC2 |Software SYNC Function\r
+ * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.\r
+ * |[2] |SWSYNC4 |Software SYNC Function\r
+ * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.\r
+ * @var EPWM_T::CLKSRC\r
+ * Offset: 0x10 EPWM Clock Source Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select\r
+ * | | |000 = EPWMx_CLK, x denotes 0 or 1.\r
+ * | | |001 = TIMER0 overflow.\r
+ * | | |010 = TIMER1 overflow.\r
+ * | | |011 = TIMER2 overflow.\r
+ * | | |100 = TIMER3 overflow.\r
+ * | | |Others = Reserved.\r
+ * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select\r
+ * | | |000 = EPWMx_CLK, x denotes 0 or 1.\r
+ * | | |001 = TIMER0 overflow.\r
+ * | | |010 = TIMER1 overflow.\r
+ * | | |011 = TIMER2 overflow.\r
+ * | | |100 = TIMER3 overflow.\r
+ * | | |Others = Reserved.\r
+ * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select\r
+ * | | |000 = EPWMx_CLK, x denotes 0 or 1.\r
+ * | | |001 = TIMER0 overflow.\r
+ * | | |010 = TIMER1 overflow.\r
+ * | | |011 = TIMER2 overflow.\r
+ * | | |100 = TIMER3 overflow.\r
+ * | | |Others = Reserved.\r
+ * @var EPWM_T::CLKPSC[3]\r
+ * Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[11:0] |CLKPSC |EPWM Counter Clock Prescale\r
+ * | | |The clock of EPWM counter is decided by clock prescaler\r
+ * | | |Each EPWM pair share one EPWM counter clock prescaler\r
+ * | | |The clock of EPWM counter is divided by (CLKPSC+ 1)\r
+ * @var EPWM_T::CNTEN\r
+ * Offset: 0x20 EPWM Counter Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CNTEN0 |EPWM Counter Enable Bits\r
+ * | | |0 = EPWM Counter and clock prescaler Stop Running.\r
+ * | | |1 = EPWM Counter and clock prescaler Start Running.\r
+ * |[1] |CNTEN1 |EPWM Counter Enable Bits\r
+ * | | |0 = EPWM Counter and clock prescaler Stop Running.\r
+ * | | |1 = EPWM Counter and clock prescaler Start Running.\r
+ * |[2] |CNTEN2 |EPWM Counter Enable Bits\r
+ * | | |0 = EPWM Counter and clock prescaler Stop Running.\r
+ * | | |1 = EPWM Counter and clock prescaler Start Running.\r
+ * |[3] |CNTEN3 |EPWM Counter Enable Bits\r
+ * | | |0 = EPWM Counter and clock prescaler Stop Running.\r
+ * | | |1 = EPWM Counter and clock prescaler Start Running.\r
+ * |[4] |CNTEN4 |EPWM Counter Enable Bits\r
+ * | | |0 = EPWM Counter and clock prescaler Stop Running.\r
+ * | | |1 = EPWM Counter and clock prescaler Start Running.\r
+ * |[5] |CNTEN5 |EPWM Counter Enable Bits\r
+ * | | |0 = EPWM Counter and clock prescaler Stop Running.\r
+ * | | |1 = EPWM Counter and clock prescaler Start Running.\r
+ * @var EPWM_T::CNTCLR\r
+ * Offset: 0x24 EPWM Clear Counter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit\r
+ * | | |It is automatically cleared by hardware.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear 16-bit EPWM counter to 0000H.\r
+ * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit\r
+ * | | |It is automatically cleared by hardware.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear 16-bit EPWM counter to 0000H.\r
+ * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit\r
+ * | | |It is automatically cleared by hardware.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear 16-bit EPWM counter to 0000H.\r
+ * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit\r
+ * | | |It is automatically cleared by hardware.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear 16-bit EPWM counter to 0000H.\r
+ * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit\r
+ * | | |It is automatically cleared by hardware.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear 16-bit EPWM counter to 0000H.\r
+ * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit\r
+ * | | |It is automatically cleared by hardware.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear 16-bit EPWM counter to 0000H.\r
+ * @var EPWM_T::LOAD\r
+ * Offset: 0x28 EPWM Load Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |LOAD0 |Re-load EPWM Comparator Register (CMPDAT) Control Bit\r
+ * | | |This bit is software write, hardware clear when current EPWM period end.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Set load window of window loading mode.\r
+ * | | |Read Operation:\r
+ * | | |0 = No load window is set.\r
+ * | | |1 = Load window is set.\r
+ * | | |Note: This bit only use in window loading mode, WINLDEN0(EPWM_CTL0[13:8]) = 1.\r
+ * |[1] |LOAD1 |Re-load EPWM Comparator Register (CMPDAT) Control Bit\r
+ * | | |This bit is software write, hardware clear when current EPWM period end.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Set load window of window loading mode.\r
+ * | | |Read Operation:\r
+ * | | |0 = No load window is set.\r
+ * | | |1 = Load window is set.\r
+ * | | |Note: This bit only use in window loading mode, WINLDEN1(EPWM_CTL0[13:8]) = 1.\r
+ * |[2] |LOAD2 |Re-load EPWM Comparator Register (CMPDAT) Control Bit\r
+ * | | |This bit is software write, hardware clear when current EPWM period end.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Set load window of window loading mode.\r
+ * | | |Read Operation:\r
+ * | | |0 = No load window is set.\r
+ * | | |1 = Load window is set.\r
+ * | | |Note: This bit only use in window loading mode, WINLDEN2(EPWM_CTL0[13:8]) = 1.\r
+ * |[3] |LOAD3 |Re-load EPWM Comparator Register (CMPDAT) Control Bit\r
+ * | | |This bit is software write, hardware clear when current EPWM period end.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Set load window of window loading mode.\r
+ * | | |Read Operation:\r
+ * | | |0 = No load window is set.\r
+ * | | |1 = Load window is set.\r
+ * | | |Note: This bit only use in window loading mode, WINLDEN3(EPWM_CTL0[13:8]) = 1.\r
+ * |[4] |LOAD4 |Re-load EPWM Comparator Register (CMPDAT) Control Bit\r
+ * | | |This bit is software write, hardware clear when current EPWM period end.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Set load window of window loading mode.\r
+ * | | |Read Operation:\r
+ * | | |0 = No load window is set.\r
+ * | | |1 = Load window is set.\r
+ * | | |Note: This bit only use in window loading mode, WINLDEN4(EPWM_CTL0[13:8]) = 1.\r
+ * |[5] |LOAD5 |Re-load EPWM Comparator Register (CMPDAT) Control Bit\r
+ * | | |This bit is software write, hardware clear when current EPWM period end.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Set load window of window loading mode.\r
+ * | | |Read Operation:\r
+ * | | |0 = No load window is set.\r
+ * | | |1 = Load window is set.\r
+ * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.\r
+ * @var EPWM_T::PERIOD[6]\r
+ * Offset: 0x30 EPWM Period Register 0~5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |PERIOD |EPWM Period Register\r
+ * | | |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0.\r
+ * | | |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD.\r
+ * | | |EPWM period time = (PERIOD+1) * EPWM_CLK period.\r
+ * | | |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.\r
+ * | | |EPWM period time = 2 * PERIOD * EPWM_CLK period.\r
+ * @var EPWM_T::CMPDAT[6]\r
+ * Offset: 0x50 EPWM Comparator Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |CMP |EPWM Comparator Register\r
+ * | | |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC.\r
+ * | | |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\r
+ * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.\r
+ * @var EPWM_T::DTCTL[3]\r
+ * Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[11:0] |DTCNT |Dead-time Counter (Write Protect)\r
+ * | | |The dead-time can be calculated from the following formula:\r
+ * | | |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect)\r
+ * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled\r
+ * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\r
+ * | | |0 = Dead-time insertion Disabled on the pin pair.\r
+ * | | |1 = Dead-time insertion Enabled on the pin pair.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect)\r
+ * | | |0 = Dead-time clock source from EPWM_CLK.\r
+ * | | |1 = Dead-time clock source from prescaler output.\r
+ * | | |Note: This register is write protected. Refer toREGWRPROT register.\r
+ * @var EPWM_T::PHS[3]\r
+ * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |PHS |EPWM Synchronous Start Phase Bits\r
+ * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function.\r
+ * @var EPWM_T::CNT[6]\r
+ * Offset: 0x90 EPWM Counter Register 0~5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |CNT |EPWM Data Register (Read Only)\r
+ * | | |User can monitor CNTR to know the current value in 16-bit period counter.\r
+ * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only)\r
+ * | | |0 = Counter is Down count.\r
+ * | | |1 = Counter is UP count.\r
+ * @var EPWM_T::WGCTL0\r
+ * Offset: 0xB0 EPWM Generation Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |ZPCTL0 |EPWM Zero Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM zero point output Low.\r
+ * | | |10 = EPWM zero point output High.\r
+ * | | |11 = EPWM zero point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter count to zero.\r
+ * |[3:2] |ZPCTL1 |EPWM Zero Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM zero point output Low.\r
+ * | | |10 = EPWM zero point output High.\r
+ * | | |11 = EPWM zero point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter count to zero.\r
+ * |[5:4] |ZPCTL2 |EPWM Zero Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM zero point output Low.\r
+ * | | |10 = EPWM zero point output High.\r
+ * | | |11 = EPWM zero point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter count to zero.\r
+ * |[7:6] |ZPCTL3 |EPWM Zero Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM zero point output Low.\r
+ * | | |10 = EPWM zero point output High.\r
+ * | | |11 = EPWM zero point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter count to zero.\r
+ * |[9:8] |ZPCTL4 |EPWM Zero Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM zero point output Low.\r
+ * | | |10 = EPWM zero point output High.\r
+ * | | |11 = EPWM zero point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter count to zero.\r
+ * |[11:10] |ZPCTL5 |EPWM Zero Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM zero point output Low.\r
+ * | | |10 = EPWM zero point output High.\r
+ * | | |11 = EPWM zero point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter count to zero.\r
+ * |[17:16] |PRDPCTL0 |EPWM Period (Center) Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM period (center) point output Low.\r
+ * | | |10 = EPWM period (center) point output High.\r
+ * | | |11 = EPWM period (center) point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter count to (PERIOD0+1).\r
+ * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.\r
+ * |[19:18] |PRDPCTL1 |EPWM Period (Center) Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM period (center) point output Low.\r
+ * | | |10 = EPWM period (center) point output High.\r
+ * | | |11 = EPWM period (center) point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter count to (PERIOD1+1).\r
+ * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.\r
+ * |[21:20] |PRDPCTL2 |EPWM Period (Center) Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM period (center) point output Low.\r
+ * | | |10 = EPWM period (center) point output High.\r
+ * | | |11 = EPWM period (center) point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter count to (PERIOD2+1).\r
+ * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.\r
+ * |[23:22] |PRDPCTL3 |EPWM Period (Center) Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM period (center) point output Low.\r
+ * | | |10 = EPWM period (center) point output High.\r
+ * | | |11 = EPWM period (center) point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter count to (PERIOD3+1).\r
+ * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.\r
+ * |[25:24] |PRDPCTL4 |EPWM Period (Center) Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM period (center) point output Low.\r
+ * | | |10 = EPWM period (center) point output High.\r
+ * | | |11 = EPWM period (center) point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter count to (PERIOD4+1).\r
+ * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.\r
+ * |[27:26] |PRDPCTL5 |EPWM Period (Center) Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM period (center) point output Low.\r
+ * | | |10 = EPWM period (center) point output High.\r
+ * | | |11 = EPWM period (center) point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter count to (PERIOD5+1).\r
+ * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.\r
+ * @var EPWM_T::WGCTL1\r
+ * Offset: 0xB4 EPWM Generation Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM compare up point output Low.\r
+ * | | |10 = EPWM compare up point output High.\r
+ * | | |11 = EPWM compare up point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter up count to CMPDAT.\r
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.\r
+ * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM compare up point output Low.\r
+ * | | |10 = EPWM compare up point output High.\r
+ * | | |11 = EPWM compare up point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter up count to CMPDAT.\r
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.\r
+ * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM compare up point output Low.\r
+ * | | |10 = EPWM compare up point output High.\r
+ * | | |11 = EPWM compare up point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter up count to CMPDAT.\r
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.\r
+ * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM compare up point output Low.\r
+ * | | |10 = EPWM compare up point output High.\r
+ * | | |11 = EPWM compare up point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter up count to CMPDAT.\r
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.\r
+ * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM compare up point output Low.\r
+ * | | |10 = EPWM compare up point output High.\r
+ * | | |11 = EPWM compare up point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter up count to CMPDAT.\r
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.\r
+ * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM compare up point output Low.\r
+ * | | |10 = EPWM compare up point output High.\r
+ * | | |11 = EPWM compare up point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter up count to CMPDAT.\r
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.\r
+ * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM compare down point output Low.\r
+ * | | |10 = EPWM compare down point output High.\r
+ * | | |11 = EPWM compare down point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter down count to CMPDAT.\r
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.\r
+ * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM compare down point output Low.\r
+ * | | |10 = EPWM compare down point output High.\r
+ * | | |11 = EPWM compare down point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter down count to CMPDAT.\r
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.\r
+ * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM compare down point output Low.\r
+ * | | |10 = EPWM compare down point output High.\r
+ * | | |11 = EPWM compare down point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter down count to CMPDAT.\r
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.\r
+ * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM compare down point output Low.\r
+ * | | |10 = EPWM compare down point output High.\r
+ * | | |11 = EPWM compare down point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter down count to CMPDAT.\r
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.\r
+ * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM compare down point output Low.\r
+ * | | |10 = EPWM compare down point output High.\r
+ * | | |11 = EPWM compare down point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter down count to CMPDAT.\r
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.\r
+ * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control\r
+ * | | |00 = Do nothing.\r
+ * | | |01 = EPWM compare down point output Low.\r
+ * | | |10 = EPWM compare down point output High.\r
+ * | | |11 = EPWM compare down point output Toggle.\r
+ * | | |EPWM can control output level when EPWM counter down count to CMPDAT.\r
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.\r
+ * @var EPWM_T::MSKEN\r
+ * Offset: 0xB8 EPWM Mask Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |MSKEN0 |EPWM Mask Enable Bits\r
+ * | | |The EPWM output signal will be masked when this bit is enabled.\r
+ * | | |The corresponding EPWM channel 0 will output MSKDAT0 (EPWM_MSK[5:0]) data.\r
+ * | | |0 = EPWM output signal is non-masked.\r
+ * | | |1 = EPWM output signal is masked and output MSKDAT0 data.\r
+ * |[1] |MSKEN1 |EPWM Mask Enable Bits\r
+ * | | |The EPWM output signal will be masked when this bit is enabled.\r
+ * | | |The corresponding EPWM channel 1 will output MSKDAT1 (EPWM_MSK[5:0]) data.\r
+ * | | |0 = EPWM output signal is non-masked.\r
+ * | | |1 = EPWM output signal is masked and output MSKDAT1 data.\r
+ * |[2] |MSKEN2 |EPWM Mask Enable Bits\r
+ * | | |The EPWM output signal will be masked when this bit is enabled.\r
+ * | | |The corresponding EPWM channel 2 will output MSKDAT2 (EPWM_MSK[5:0]) data.\r
+ * | | |0 = EPWM output signal is non-masked.\r
+ * | | |1 = EPWM output signal is masked and output MSKDAT2 data.\r
+ * |[3] |MSKEN3 |EPWM Mask Enable Bits\r
+ * | | |The EPWM output signal will be masked when this bit is enabled.\r
+ * | | |The corresponding EPWM channel 3 will output MSKDAT3 (EPWM_MSK[5:0]) data.\r
+ * | | |0 = EPWM output signal is non-masked.\r
+ * | | |1 = EPWM output signal is masked and output MSKDAT3 data.\r
+ * |[4] |MSKEN4 |EPWM Mask Enable Bits\r
+ * | | |The EPWM output signal will be masked when this bit is enabled.\r
+ * | | |The corresponding EPWM channel 4 will output MSKDAT4 (EPWM_MSK[5:0]) data.\r
+ * | | |0 = EPWM output signal is non-masked.\r
+ * | | |1 = EPWM output signal is masked and output MSKDAT4 data.\r
+ * |[5] |MSKEN5 |EPWM Mask Enable Bits\r
+ * | | |The EPWM output signal will be masked when this bit is enabled.\r
+ * | | |The corresponding EPWM channel 5 will output MSKDAT5 (EPWM_MSK[5:0]) data.\r
+ * | | |0 = EPWM output signal is non-masked.\r
+ * | | |1 = EPWM output signal is masked and output MSKDAT5 data.\r
+ * @var EPWM_T::MSK\r
+ * Offset: 0xBC EPWM Mask Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |MSKDAT0 |EPWM Mask Data Bit\r
+ * | | |This data bit control the state of EPWM_CH0 output pin, if corresponding mask function is enabled.\r
+ * | | |0 = Output logic low to EPWM_CH0.\r
+ * | | |1 = Output logic high to EPWM_CH0.\r
+ * |[1] |MSKDAT1 |EPWM Mask Data Bit\r
+ * | | |This data bit control the state of EPWM_CH1 output pin, if corresponding mask function is enabled.\r
+ * | | |0 = Output logic low to EPWM_CH1.\r
+ * | | |1 = Output logic high to EPWM_CH1.\r
+ * |[2] |MSKDAT2 |EPWM Mask Data Bit\r
+ * | | |This data bit control the state of EPWM_CH2 output pin, if corresponding mask function is enabled.\r
+ * | | |0 = Output logic low to EPWM_CH2.\r
+ * | | |1 = Output logic high to EPWM_CH2.\r
+ * |[3] |MSKDAT3 |EPWM Mask Data Bit\r
+ * | | |This data bit control the state of EPWM_CH3 output pin, if corresponding mask function is enabled.\r
+ * | | |0 = Output logic low to EPWM_CH3.\r
+ * | | |1 = Output logic high to EPWM_CH3.\r
+ * |[4] |MSKDAT4 |EPWM Mask Data Bit\r
+ * | | |This data bit control the state of EPWM_CH4 output pin, if corresponding mask function is enabled.\r
+ * | | |0 = Output logic low to EPWM_CH4.\r
+ * | | |1 = Output logic high to EPWM_CH4.\r
+ * |[5] |MSKDAT5 |EPWM Mask Data Bit\r
+ * | | |This data bit control the state of EPWM_CH5 output pin, if corresponding mask function is enabled.\r
+ * | | |0 = Output logic low to EPWM_CH5.\r
+ * | | |1 = Output logic high to EPWM_CH5.\r
+ * @var EPWM_T::BNF\r
+ * Offset: 0xC0 EPWM Brake Noise Filter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit\r
+ * | | |0 = Noise filter of EPWM Brake 0 Disabled.\r
+ * | | |1 = Noise filter of EPWM Brake 0 Enabled.\r
+ * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection\r
+ * | | |000 = Filter clock = HCLK.\r
+ * | | |001 = Filter clock = HCLK/2.\r
+ * | | |010 = Filter clock = HCLK/4.\r
+ * | | |011 = Filter clock = HCLK/8.\r
+ * | | |100 = Filter clock = HCLK/16.\r
+ * | | |101 = Filter clock = HCLK/32.\r
+ * | | |110 = Filter clock = HCLK/64.\r
+ * | | |111 = Filter clock = HCLK/128.\r
+ * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count\r
+ * | | |The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT.\r
+ * |[7] |BRK0PINV |Brake 0 Pin Inverse\r
+ * | | |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector.\r
+ * | | |1 = The inversed state of pin EPWMx_BRAKE0 is passed to the negative edge detector.\r
+ * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit\r
+ * | | |0 = Noise filter of EPWM Brake 1 Disabled.\r
+ * | | |1 = Noise filter of EPWM Brake 1 Enabled.\r
+ * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection\r
+ * | | |000 = Filter clock = HCLK.\r
+ * | | |001 = Filter clock = HCLK/2.\r
+ * | | |010 = Filter clock = HCLK/4.\r
+ * | | |011 = Filter clock = HCLK/8.\r
+ * | | |100 = Filter clock = HCLK/16.\r
+ * | | |101 = Filter clock = HCLK/32.\r
+ * | | |110 = Filter clock = HCLK/64.\r
+ * | | |111 = Filter clock = HCLK/128.\r
+ * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count\r
+ * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.\r
+ * |[15] |BRK1PINV |Brake 1 Pin Inverse\r
+ * | | |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector.\r
+ * | | |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector.\r
+ * |[16] |BK0SRC |Brake 0 Pin Source Select\r
+ * | | |For EPWM0 setting:\r
+ * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0.\r
+ * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0.\r
+ * | | |For EPWM1 setting:\r
+ * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0.\r
+ * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0.\r
+ * |[24] |BK1SRC |Brake 1 Pin Source Select\r
+ * | | |For EPWM0 setting:\r
+ * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1.\r
+ * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1.\r
+ * | | |For EPWM1 setting:\r
+ * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1.\r
+ * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1.\r
+ * @var EPWM_T::FAILBRK\r
+ * Offset: 0xC4 EPWM System Fail Brake Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit\r
+ * | | |0 = Brake Function triggered by CSS detection Disabled.\r
+ * | | |1 = Brake Function triggered by CSS detection Enabled.\r
+ * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit\r
+ * | | |0 = Brake Function triggered by BOD Disabled.\r
+ * | | |1 = Brake Function triggered by BOD Enabled.\r
+ * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit\r
+ * | | |0 = Brake Function triggered by SRAM parity error detection Disabled.\r
+ * | | |1 = Brake Function triggered by SRAM parity error detection Enabled.\r
+ * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit\r
+ * | | |0 = Brake Function triggered by Core lockup detection Disabled.\r
+ * | | |1 = Brake Function triggered by Core lockup detection Enabled.\r
+ * @var EPWM_T::BRKCTL[3]\r
+ * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\r
+ * | | |0 = ACMP0_O as edge-detect brake source Disabled.\r
+ * | | |1 = ACMP0_O as edge-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\r
+ * | | |0 = ACMP1_O as edge-detect brake source Disabled.\r
+ * | | |1 = ACMP1_O as edge-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\r
+ * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled.\r
+ * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\r
+ * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled.\r
+ * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect)\r
+ * | | |0 = System Fail condition as edge-detect brake source Disabled.\r
+ * | | |1 = System Fail condition as edge-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\r
+ * | | |0 = ACMP0_O as level-detect brake source Disabled.\r
+ * | | |1 = ACMP0_O as level-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\r
+ * | | |0 = ACMP1_O as level-detect brake source Disabled.\r
+ * | | |1 = ACMP1_O as level-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\r
+ * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled.\r
+ * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\r
+ * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled.\r
+ * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect)\r
+ * | | |0 = System Fail condition as level-detect brake source Disabled.\r
+ * | | |1 = System Fail condition as level-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect)\r
+ * | | |00 = EPWMx brake event will not affect even channels output.\r
+ * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened.\r
+ * | | |10 = EPWM even channel output low level when EPWMx brake event happened.\r
+ * | | |11 = EPWM even channel output high level when EPWMx brake event happened.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect)\r
+ * | | |00 = EPWMx brake event will not affect odd channels output.\r
+ * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened.\r
+ * | | |10 = EPWM odd channel output low level when EPWMx brake event happened.\r
+ * | | |11 = EPWM odd channel output high level when EPWMx brake event happened.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[20] |EADCEBEN |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\r
+ * | | |0 = EADCRM as edge-detect brake source Disabled.\r
+ * | | |1 = EADCRM as edge-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[28] |EADCLBEN |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\r
+ * | | |0 = EADCRM as level-detect brake source Disabled.\r
+ * | | |1 = EADCRM as level-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * @var EPWM_T::POLCTL\r
+ * Offset: 0xD4 EPWM Pin Polar Inverse Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PINV0 |EPWM_CH0 PIN Polar Inverse Control\r
+ * | | |The register controls polarity state of EPWM_CH0 output.\r
+ * | | |0 = EPWM_CH0 output polar inverse Disabled.\r
+ * | | |1 = EPWM_CH0 output polar inverse Enabled.\r
+ * |[1] |PINV1 |EPWM_CH1 PIN Polar Inverse Control\r
+ * | | |The register controls polarity state of EPWM_CH1 output.\r
+ * | | |0 = EPWM_CH1 output polar inverse Disabled.\r
+ * | | |1 = EPWM_CH1 output polar inverse Enabled.\r
+ * |[2] |PINV2 |EPWM_CH2 PIN Polar Inverse Control\r
+ * | | |The register controls polarity state of EPWM_CH2 output.\r
+ * | | |0 = EPWM_CH2 output polar inverse Disabled.\r
+ * | | |1 = EPWM_CH2 output polar inverse Enabled.\r
+ * |[3] |PINV3 |EPWM_CH3 PIN Polar Inverse Control\r
+ * | | |The register controls polarity state of EPWM_CH3 output.\r
+ * | | |0 = EPWM_CH3 output polar inverse Disabled.\r
+ * | | |1 = EPWM_CH3 output polar inverse Enabled.\r
+ * |[4] |PINV4 |EPWM_CH4 PIN Polar Inverse Control\r
+ * | | |The register controls polarity state of EPWM_CH4 output.\r
+ * | | |0 = EPWM_CH4 output polar inverse Disabled.\r
+ * | | |1 = EPWM_CH4 output polar inverse Enabled.\r
+ * |[5] |PINV5 |EPWM_CH5 PIN Polar Inverse Control\r
+ * | | |The register controls polarity state of EPWM_CH5 output.\r
+ * | | |0 = EPWM_CH5 output polar inverse Disabled.\r
+ * | | |1 = EPWM_CH5 output polar inverse Enabled.\r
+ * @var EPWM_T::POEN\r
+ * Offset: 0xD8 EPWM Output Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |POEN0 |EPWM_CH0 Pin Output Enable Bits\r
+ * | | |0 = EPWM_CH0 pin at tri-state.\r
+ * | | |1 = EPWM_CH0 pin in output mode.\r
+ * |[1] |POEN1 |EPWM_CH1 Pin Output Enable Bits\r
+ * | | |0 = EPWM_CH1 pin at tri-state.\r
+ * | | |1 = EPWM_CH1 pin in output mode.\r
+ * |[2] |POEN2 |EPWM_CH2 Pin Output Enable Bits\r
+ * | | |0 = EPWM_CH2 pin at tri-state.\r
+ * | | |1 = EPWM_CH2 pin in output mode.\r
+ * |[3] |POEN3 |EPWM_CH3 Pin Output Enable Bits\r
+ * | | |0 = EPWM_CH3 pin at tri-state.\r
+ * | | |1 = EPWM_CH3 pin in output mode.\r
+ * |[4] |POEN4 |EPWM_CH4 Pin Output Enable Bits\r
+ * | | |0 = EPWM_CH4 pin at tri-state.\r
+ * | | |1 = EPWM_CH4 pin in output mode.\r
+ * |[5] |POEN5 |EPWM_CH5 Pin Output Enable Bits\r
+ * | | |0 = EPWM_CH5 pin at tri-state.\r
+ * | | |1 = EPWM_CH5 pin in output mode.\r
+ * @var EPWM_T::SWBRK\r
+ * Offset: 0xDC EPWM Software Brake Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\r
+ * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF0 to 1 in EPWM_INTSTS1 register.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\r
+ * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF2 to 1 in EPWM_INTSTS1 register.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\r
+ * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF4 to 1 in EPWM_INTSTS1 register.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect)\r
+ * | | |Write 1 to this bit will trigger level brake, and set BRKLIF0 to 1 in EPWM_INTSTS1 register.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect)\r
+ * | | |Write 1 to this bit will trigger level brake, and set BRKLIF2 to 1 in EPWM_INTSTS1 register.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect)\r
+ * | | |Write 1 to this bit will trigger level brake, and set BRKLIF4 to 1 in EPWM_INTSTS1 register.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * @var EPWM_T::INTEN0\r
+ * Offset: 0xE0 EPWM Interrupt Enable Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits\r
+ * | | |0 = Zero point interrupt Disabled.\r
+ * | | |1 = Zero point interrupt Enabled.\r
+ * | | |Note: Odd channels will read always 0 at complementary mode.\r
+ * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits\r
+ * | | |0 = Zero point interrupt Disabled.\r
+ * | | |1 = Zero point interrupt Enabled.\r
+ * | | |Note: Odd channels will read always 0 at complementary mode.\r
+ * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits\r
+ * | | |0 = Zero point interrupt Disabled.\r
+ * | | |1 = Zero point interrupt Enabled.\r
+ * | | |Note: Odd channels will read always 0 at complementary mode.\r
+ * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits\r
+ * | | |0 = Zero point interrupt Disabled.\r
+ * | | |1 = Zero point interrupt Enabled.\r
+ * | | |Note: Odd channels will read always 0 at complementary mode.\r
+ * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits\r
+ * | | |0 = Zero point interrupt Disabled.\r
+ * | | |1 = Zero point interrupt Enabled.\r
+ * | | |Note: Odd channels will read always 0 at complementary mode.\r
+ * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits\r
+ * | | |0 = Zero point interrupt Disabled.\r
+ * | | |1 = Zero point interrupt Enabled.\r
+ * | | |Note: Odd channels will read always 0 at complementary mode.\r
+ * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits\r
+ * | | |0 = Period point interrupt Disabled.\r
+ * | | |1 = Period point interrupt Enabled.\r
+ * | | |Note1: When up-down counter type period point means center point.\r
+ * | | |Note2: Odd channels will read always 0 at complementary mode.\r
+ * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits\r
+ * | | |0 = Period point interrupt Disabled.\r
+ * | | |1 = Period point interrupt Enabled.\r
+ * | | |Note1: When up-down counter type period point means center point.\r
+ * | | |Note2: Odd channels will read always 0 at complementary mode.\r
+ * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits\r
+ * | | |0 = Period point interrupt Disabled.\r
+ * | | |1 = Period point interrupt Enabled.\r
+ * | | |Note1: When up-down counter type period point means center point.\r
+ * | | |Note2: Odd channels will read always 0 at complementary mode.\r
+ * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits\r
+ * | | |0 = Period point interrupt Disabled.\r
+ * | | |1 = Period point interrupt Enabled.\r
+ * | | |Note1: When up-down counter type period point means center point.\r
+ * | | |Note2: Odd channels will read always 0 at complementary mode.\r
+ * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits\r
+ * | | |0 = Period point interrupt Disabled.\r
+ * | | |1 = Period point interrupt Enabled.\r
+ * | | |Note1: When up-down counter type period point means center point.\r
+ * | | |Note2: Odd channels will read always 0 at complementary mode.\r
+ * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits\r
+ * | | |0 = Period point interrupt Disabled.\r
+ * | | |1 = Period point interrupt Enabled.\r
+ * | | |Note1: When up-down counter type period point means center point.\r
+ * | | |Note2: Odd channels will read always 0 at complementary mode.\r
+ * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.\r
+ * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.\r
+ * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.\r
+ * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.\r
+ * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.\r
+ * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.\r
+ * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.\r
+ * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.\r
+ * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.\r
+ * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.\r
+ * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.\r
+ * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.\r
+ * @var EPWM_T::INTEN1\r
+ * Offset: 0xE4 EPWM Interrupt Enable Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\r
+ * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled.\r
+ * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\r
+ * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled.\r
+ * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\r
+ * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled.\r
+ * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\r
+ * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled.\r
+ * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\r
+ * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled.\r
+ * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\r
+ * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled.\r
+ * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * @var EPWM_T::INTSTS0\r
+ * Offset: 0xE8 EPWM Interrupt Flag Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag\r
+ * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.\r
+ * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag\r
+ * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.\r
+ * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag\r
+ * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.\r
+ * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag\r
+ * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.\r
+ * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag\r
+ * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.\r
+ * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag\r
+ * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.\r
+ * |[8] |PIF0 |EPWM Period Point Interrupt Flag\r
+ * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD0, software can write 1 to clear this bit to zero\r
+ * |[9] |PIF1 |EPWM Period Point Interrupt Flag\r
+ * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD1, software can write 1 to clear this bit to zero\r
+ * |[10] |PIF2 |EPWM Period Point Interrupt Flag\r
+ * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD2, software can write 1 to clear this bit to zero\r
+ * |[11] |PIF3 |EPWM Period Point Interrupt Flag\r
+ * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD4, software can write 1 to clear this bit to zero\r
+ * |[12] |PIF4 |EPWM Period Point Interrupt Flag\r
+ * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD5, software can write 1 to clear this bit to zero\r
+ * |[13] |PIF5 |EPWM Period Point Interrupt Flag\r
+ * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.\r
+ * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag\r
+ * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it.\r
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\r
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.\r
+ * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag\r
+ * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it.\r
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\r
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.\r
+ * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag\r
+ * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it.\r
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\r
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.\r
+ * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag\r
+ * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it.\r
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\r
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.\r
+ * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag\r
+ * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it.\r
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\r
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.\r
+ * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag\r
+ * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it.\r
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\r
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.\r
+ * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag\r
+ * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it.\r
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\r
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.\r
+ * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag\r
+ * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it.\r
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\r
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.\r
+ * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag\r
+ * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it.\r
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\r
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.\r
+ * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag\r
+ * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it.\r
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\r
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.\r
+ * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag\r
+ * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it.\r
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\r
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.\r
+ * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag\r
+ * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it.\r
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\r
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.\r
+ * @var EPWM_T::INTSTS1\r
+ * Offset: 0xEC EPWM Interrupt Flag Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect)\r
+ * | | |0 = EPWM channel0 edge-detect brake event do not happened.\r
+ * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect)\r
+ * | | |0 = EPWM channel1 edge-detect brake event do not happened.\r
+ * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect)\r
+ * | | |0 = EPWM channel2 edge-detect brake event do not happened.\r
+ * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect)\r
+ * | | |0 = EPWM channel3 edge-detect brake event do not happened.\r
+ * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect)\r
+ * | | |0 = EPWM channel4 edge-detect brake event do not happened.\r
+ * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect)\r
+ * | | |0 = EPWM channel5 edge-detect brake event do not happened.\r
+ * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect)\r
+ * | | |0 = EPWM channel0 level-detect brake event do not happened.\r
+ * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect)\r
+ * | | |0 = EPWM channel1 level-detect brake event do not happened.\r
+ * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect)\r
+ * | | |0 = EPWM channel2 level-detect brake event do not happened.\r
+ * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect)\r
+ * | | |0 = EPWM channel3 level-detect brake event do not happened.\r
+ * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect)\r
+ * | | |0 = EPWM channel4 level-detect brake event do not happened.\r
+ * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect)\r
+ * | | |0 = EPWM channel5 level-detect brake event do not happened.\r
+ * | | |1 = When EPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.\r
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.\r
+ * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only)\r
+ * | | |0 = EPWM channel0 edge-detect brake state is released.\r
+ * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear.\r
+ * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only)\r
+ * | | |0 = EPWM channel1 edge-detect brake state is released.\r
+ * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear.\r
+ * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only)\r
+ * | | |0 = EPWM channel2 edge-detect brake state is released.\r
+ * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear.\r
+ * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only)\r
+ * | | |0 = EPWM channel3 edge-detect brake state is released.\r
+ * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear.\r
+ * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only)\r
+ * | | |0 = EPWM channel4 edge-detect brake state is released.\r
+ * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear.\r
+ * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only)\r
+ * | | |0 = EPWM channel5 edge-detect brake state is released.\r
+ * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear.\r
+ * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only)\r
+ * | | |0 = EPWM channel0 level-detect brake state is released.\r
+ * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state.\r
+ * | | |Note: This bit is read only and auto cleared by hardware\r
+ * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished\r
+ * | | |The EPWM waveform will start output from next full EPWM period.\r
+ * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only)\r
+ * | | |0 = EPWM channel1 level-detect brake state is released.\r
+ * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state.\r
+ * | | |Note: This bit is read only and auto cleared by hardware\r
+ * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished\r
+ * | | |The EPWM waveform will start output from next full EPWM period.\r
+ * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only)\r
+ * | | |0 = EPWM channel2 level-detect brake state is released.\r
+ * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state.\r
+ * | | |Note: This bit is read only and auto cleared by hardware\r
+ * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished\r
+ * | | |The EPWM waveform will start output from next full EPWM period.\r
+ * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only)\r
+ * | | |0 = EPWM channel3 level-detect brake state is released.\r
+ * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state.\r
+ * | | |Note: This bit is read only and auto cleared by hardware\r
+ * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished\r
+ * | | |The EPWM waveform will start output from next full EPWM period.\r
+ * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only)\r
+ * | | |0 = EPWM channel4 level-detect brake state is released.\r
+ * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state.\r
+ * | | |Note: This bit is read only and auto cleared by hardware\r
+ * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished\r
+ * | | |The EPWM waveform will start output from next full EPWM period.\r
+ * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only)\r
+ * | | |0 = EPWM channel5 level-detect brake state is released.\r
+ * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state.\r
+ * | | |Note: This bit is read only and auto cleared by hardware\r
+ * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished\r
+ * | | |The EPWM waveform will start output from next full EPWM period.\r
+ * @var EPWM_T::DACTRGEN\r
+ * Offset: 0xF4 EPWM Trigger DAC Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.\r
+ * | | |0 = EPWM period point trigger DAC function Disabled.\r
+ * | | |1 = EPWM period point trigger DAC function Enabled.\r
+ * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.\r
+ * | | |0 = EPWM period point trigger DAC function Disabled.\r
+ * | | |1 = EPWM period point trigger DAC function Enabled.\r
+ * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.\r
+ * | | |0 = EPWM period point trigger DAC function Disabled.\r
+ * | | |1 = EPWM period point trigger DAC function Enabled.\r
+ * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.\r
+ * | | |0 = EPWM period point trigger DAC function Disabled.\r
+ * | | |1 = EPWM period point trigger DAC function Enabled.\r
+ * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.\r
+ * | | |0 = EPWM period point trigger DAC function Disabled.\r
+ * | | |1 = EPWM period point trigger DAC function Enabled.\r
+ * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.\r
+ * | | |0 = EPWM period point trigger DAC function Disabled.\r
+ * | | |1 = EPWM period point trigger DAC function Enabled.\r
+ * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.\r
+ * | | |0 = EPWM period point trigger DAC function Disabled.\r
+ * | | |1 = EPWM period point trigger DAC function Enabled.\r
+ * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.\r
+ * | | |0 = EPWM period point trigger DAC function Disabled.\r
+ * | | |1 = EPWM period point trigger DAC function Enabled.\r
+ * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.\r
+ * | | |0 = EPWM period point trigger DAC function Disabled.\r
+ * | | |1 = EPWM period point trigger DAC function Enabled.\r
+ * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.\r
+ * | | |0 = EPWM period point trigger DAC function Disabled.\r
+ * | | |1 = EPWM period point trigger DAC function Enabled.\r
+ * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.\r
+ * | | |0 = EPWM period point trigger DAC function Disabled.\r
+ * | | |1 = EPWM period point trigger DAC function Enabled.\r
+ * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.\r
+ * | | |0 = EPWM period point trigger DAC function Disabled.\r
+ * | | |1 = EPWM period point trigger DAC function Enabled.\r
+ * |[16] |CUTRGE0 |EPWM Compare Up Count Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.\r
+ * | | |0 = EPWM Compare Up point trigger DAC function Disabled.\r
+ * | | |1 = EPWM Compare Up point trigger DAC function Enabled.\r
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.\r
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.\r
+ * |[17] |CUTRGE1 |EPWM Compare Up Count Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.\r
+ * | | |0 = EPWM Compare Up point trigger DAC function Disabled.\r
+ * | | |1 = EPWM Compare Up point trigger DAC function Enabled.\r
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.\r
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.\r
+ * |[18] |CUTRGE2 |EPWM Compare Up Count Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.\r
+ * | | |0 = EPWM Compare Up point trigger DAC function Disabled.\r
+ * | | |1 = EPWM Compare Up point trigger DAC function Enabled.\r
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.\r
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.\r
+ * |[19] |CUTRGE3 |EPWM Compare Up Count Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.\r
+ * | | |0 = EPWM Compare Up point trigger DAC function Disabled.\r
+ * | | |1 = EPWM Compare Up point trigger DAC function Enabled.\r
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.\r
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.\r
+ * |[20] |CUTRGE4 |EPWM Compare Up Count Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.\r
+ * | | |0 = EPWM Compare Up point trigger DAC function Disabled.\r
+ * | | |1 = EPWM Compare Up point trigger DAC function Enabled.\r
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.\r
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.\r
+ * |[21] |CUTRGE5 |EPWM Compare Up Count Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.\r
+ * | | |0 = EPWM Compare Up point trigger DAC function Disabled.\r
+ * | | |1 = EPWM Compare Up point trigger DAC function Enabled.\r
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.\r
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.\r
+ * |[24] |CDTRGE0 |EPWM Compare Down Count Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\r
+ * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.\r
+ * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.\r
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.\r
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.\r
+ * |[25] |CDTRGE1 |EPWM Compare Down Count Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\r
+ * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.\r
+ * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.\r
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.\r
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.\r
+ * |[26] |CDTRGE2 |EPWM Compare Down Count Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\r
+ * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.\r
+ * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.\r
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.\r
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.\r
+ * |[27] |CDTRGE3 |EPWM Compare Down Count Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\r
+ * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.\r
+ * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.\r
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.\r
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.\r
+ * |[28] |CDTRGE4 |EPWM Compare Down Count Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\r
+ * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.\r
+ * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.\r
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.\r
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.\r
+ * |[29] |CDTRGE5 |EPWM Compare Down Count Point Trigger DAC Enable Bits\r
+ * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\r
+ * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.\r
+ * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.\r
+ * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.\r
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.\r
+ * @var EPWM_T::EADCTS0\r
+ * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select\r
+ * | | |0000 = EPWM_CH0 zero point.\r
+ * | | |0001 = EPWM_CH0 period point.\r
+ * | | |0010 = EPWM_CH0 zero or period point.\r
+ * | | |0011 = EPWM_CH0 up-count CMPDAT point.\r
+ * | | |0100 = EPWM_CH0 down-count CMPDAT point.\r
+ * | | |0101 = EPWM_CH1 zero point.\r
+ * | | |0110 = EPWM_CH1 period point.\r
+ * | | |0111 = EPWM_CH1 zero or period point.\r
+ * | | |1000 = EPWM_CH1 up-count CMPDAT point.\r
+ * | | |1001 = EPWM_CH1 down-count CMPDAT point.\r
+ * | | |1010 = EPWM_CH0 up-count free CMPDAT point.\r
+ * | | |1011 = EPWM_CH0 down-count free CMPDAT point.\r
+ * | | |1100 = EPWM_CH2 up-count free CMPDAT point.\r
+ * | | |1101 = EPWM_CH2 down-count free CMPDAT point.\r
+ * | | |1110 = EPWM_CH4 up-count free CMPDAT point.\r
+ * | | |1111 = EPWM_CH4 down-count free CMPDAT point.\r
+ * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC enable bit\r
+ * |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select\r
+ * | | |0000 = EPWM_CH0 zero point.\r
+ * | | |0001 = EPWM_CH0 period point.\r
+ * | | |0010 = EPWM_CH0 zero or period point.\r
+ * | | |0011 = EPWM_CH0 up-count CMPDAT point.\r
+ * | | |0100 = EPWM_CH0 down-count CMPDAT point.\r
+ * | | |0101 = EPWM_CH1 zero point.\r
+ * | | |0110 = EPWM_CH1 period point.\r
+ * | | |0111 = EPWM_CH1 zero or period point.\r
+ * | | |1000 = EPWM_CH1 up-count CMPDAT point.\r
+ * | | |1001 = EPWM_CH1 down-count CMPDAT point.\r
+ * | | |1010 = EPWM_CH0 up-count free CMPDAT point.\r
+ * | | |1011 = EPWM_CH0 down-count free CMPDAT point.\r
+ * | | |1100 = EPWM_CH2 up-count free CMPDAT point.\r
+ * | | |1101 = EPWM_CH2 down-count free CMPDAT point.\r
+ * | | |1110 = EPWM_CH4 up-count free CMPDAT point.\r
+ * | | |1111 = EPWM_CH4 down-count free CMPDAT point.\r
+ * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC enable bit\r
+ * |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select\r
+ * | | |0000 = EPWM_CH2 zero point.\r
+ * | | |0001 = EPWM_CH2 period point.\r
+ * | | |0010 = EPWM_CH2 zero or period point.\r
+ * | | |0011 = EPWM_CH2 up-count CMPDAT point.\r
+ * | | |0100 = EPWM_CH2 down-count CMPDAT point.\r
+ * | | |0101 = EPWM_CH3 zero point.\r
+ * | | |0110 = EPWM_CH3 period point.\r
+ * | | |0111 = EPWM_CH3 zero or period point.\r
+ * | | |1000 = EPWM_CH3 up-count CMPDAT point.\r
+ * | | |1001 = EPWM_CH3 down-count CMPDAT point.\r
+ * | | |1010 = EPWM_CH0 up-count free CMPDAT point.\r
+ * | | |1011 = EPWM_CH0 down-count free CMPDAT point.\r
+ * | | |1100 = EPWM_CH2 up-count free CMPDAT point.\r
+ * | | |1101 = EPWM_CH2 down-count free CMPDAT point.\r
+ * | | |1110 = EPWM_CH4 up-count free CMPDAT point.\r
+ * | | |1111 = EPWM_CH4 down-count free CMPDAT point.\r
+ * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC enable bit\r
+ * |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select\r
+ * | | |0000 = EPWM_CH2 zero point.\r
+ * | | |0001 = EPWM_CH2 period point.\r
+ * | | |0010 = EPWM_CH2 zero or period point.\r
+ * | | |0011 = EPWM_CH2 up-count CMPDAT point.\r
+ * | | |0100 = EPWM_CH2 down-count CMPDAT point.\r
+ * | | |0101 = EPWM_CH3 zero point.\r
+ * | | |0110 = EPWM_CH3 period point.\r
+ * | | |0111 = EPWM_CH3 zero or period point.\r
+ * | | |1000 = EPWM_CH3 up-count CMPDAT point.\r
+ * | | |1001 = EPWM_CH3 down-count CMPDAT point.\r
+ * | | |1010 = EPWM_CH0 up-count free CMPDAT point.\r
+ * | | |1011 = EPWM_CH0 down-count free CMPDAT point.\r
+ * | | |1100 = EPWM_CH2 up-count free CMPDAT point.\r
+ * | | |1101 = EPWM_CH2 down-count free CMPDAT point.\r
+ * | | |1110 = EPWM_CH4 up-count free CMPDAT point.\r
+ * | | |1111 = EPWM_CH4 down-count free CMPDAT point.\r
+ * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC enable bit\r
+ * @var EPWM_T::EADCTS1\r
+ * Offset: 0xFC EPWM Trigger EADC Source Select Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select\r
+ * | | |0000 = EPWM_CH4 zero point.\r
+ * | | |0001 = EPWM_CH4 period point.\r
+ * | | |0010 = EPWM_CH4 zero or period point.\r
+ * | | |0011 = EPWM_CH4 up-count CMPDAT point.\r
+ * | | |0100 = EPWM_CH4 down-count CMPDAT point.\r
+ * | | |0101 = EPWM_CH5 zero point.\r
+ * | | |0110 = EPWM_CH5 period point.\r
+ * | | |0111 = EPWM_CH5 zero or period point.\r
+ * | | |1000 = EPWM_CH5 up-count CMPDAT point.\r
+ * | | |1001 = EPWM_CH5 down-count CMPDAT point.\r
+ * | | |1010 = EPWM_CH0 up-count free CMPDAT point.\r
+ * | | |1011 = EPWM_CH0 down-count free CMPDAT point.\r
+ * | | |1100 = EPWM_CH2 up-count free CMPDAT point.\r
+ * | | |1101 = EPWM_CH2 down-count free CMPDAT point.\r
+ * | | |1110 = EPWM_CH4 up-count free CMPDAT point.\r
+ * | | |1111 = EPWM_CH4 down-count free CMPDAT point.\r
+ * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC enable bit\r
+ * |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select\r
+ * | | |0000 = EPWM_CH4 zero point.\r
+ * | | |0001 = EPWM_CH4 period point.\r
+ * | | |0010 = EPWM_CH4 zero or period point.\r
+ * | | |0011 = EPWM_CH4 up-count CMPDAT point.\r
+ * | | |0100 = EPWM_CH4 down-count CMPDAT point.\r
+ * | | |0101 = EPWM_CH5 zero point.\r
+ * | | |0110 = EPWM_CH5 period point.\r
+ * | | |0111 = EPWM_CH5 zero or period point.\r
+ * | | |1000 = EPWM_CH5 up-count CMPDAT point.\r
+ * | | |1001 = EPWM_CH5 down-count CMPDAT point.\r
+ * | | |1010 = EPWM_CH0 up-count free CMPDAT point.\r
+ * | | |1011 = EPWM_CH0 down-count free CMPDAT point.\r
+ * | | |1100 = EPWM_CH2 up-count free CMPDAT point.\r
+ * | | |1101 = EPWM_CH2 down-count free CMPDAT point.\r
+ * | | |1110 = EPWM_CH4 up-count free CMPDAT point.\r
+ * | | |1111 = EPWM_CH4 down-count free CMPDAT point.\r
+ * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC enable bit\r
+ * @var EPWM_T::FTCMPDAT[3]\r
+ * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |FTCMP |EPWM Free Trigger Compare Register\r
+ * | | |FTCMP use to compare with even CNTR to trigger EADC\r
+ * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.\r
+ * @var EPWM_T::SSCTL\r
+ * Offset: 0x110 EPWM Synchronous Start Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits\r
+ * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).\r
+ * | | |0 = EPWM synchronous start function Disabled.\r
+ * | | |1 = EPWM synchronous start function Enabled.\r
+ * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits\r
+ * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).\r
+ * | | |0 = EPWM synchronous start function Disabled.\r
+ * | | |1 = EPWM synchronous start function Enabled.\r
+ * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits\r
+ * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).\r
+ * | | |0 = EPWM synchronous start function Disabled.\r
+ * | | |1 = EPWM synchronous start function Enabled.\r
+ * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits\r
+ * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).\r
+ * | | |0 = EPWM synchronous start function Disabled.\r
+ * | | |1 = EPWM synchronous start function Enabled.\r
+ * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits\r
+ * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).\r
+ * | | |0 = EPWM synchronous start function Disabled.\r
+ * | | |1 = EPWM synchronous start function Enabled.\r
+ * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits\r
+ * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).\r
+ * | | |0 = EPWM synchronous start function Disabled.\r
+ * | | |1 = EPWM synchronous start function Enabled.\r
+ * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits\r
+ * | | |00 = Synchronous start source come from EPWM0.\r
+ * | | |01 = Synchronous start source come from EPWM1.\r
+ * | | |10 = Synchronous start source come from BPWM0.\r
+ * | | |11 = Synchronous start source come from BPWM1.\r
+ * @var EPWM_T::SSTRG\r
+ * Offset: 0x114 EPWM Synchronous Start Trigger Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only)\r
+ * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\r
+ * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled.\r
+ * @var EPWM_T::LEBCTL\r
+ * Offset: 0x118 EPWM Leading Edge Blanking Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit\r
+ * | | |0 = EPWM Leading Edge Blanking Disabled.\r
+ * | | |1 = EPWM Leading Edge Blanking Enabled.\r
+ * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit\r
+ * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled.\r
+ * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled.\r
+ * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit\r
+ * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled.\r
+ * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled.\r
+ * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit\r
+ * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled.\r
+ * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled.\r
+ * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type\r
+ * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting.\r
+ * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting.\r
+ * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting.\r
+ * | | |3 = Reserved.\r
+ * @var EPWM_T::LEBCNT\r
+ * Offset: 0x11C EPWM Leading Edge Blanking Counter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter\r
+ * | | |This counter value decides leading edge blanking window size.\r
+ * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK.\r
+ * @var EPWM_T::STATUS\r
+ * Offset: 0x120 EPWM Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag\r
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.\r
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.\r
+ * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag\r
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.\r
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.\r
+ * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag\r
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.\r
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.\r
+ * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag\r
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.\r
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.\r
+ * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag\r
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.\r
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.\r
+ * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag\r
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.\r
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.\r
+ * |[8] |SYNCINF0 |Input Synchronization Latched Flag\r
+ * | | |0 = Indicates no SYNC_IN event has occurred.\r
+ * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.\r
+ * |[9] |SYNCINF2 |Input Synchronization Latched Flag\r
+ * | | |0 = Indicates no SYNC_IN event has occurred.\r
+ * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.\r
+ * |[10] |SYNCINF4 |Input Synchronization Latched Flag\r
+ * | | |0 = Indicates no SYNC_IN event has occurred.\r
+ * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.\r
+ * |[16] |EADCTRGF0 |EADC Start of Conversion Flag\r
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.\r
+ * |[17] |EADCTRGF1 |EADC Start of Conversion Flag\r
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.\r
+ * |[18] |EADCTRGF2 |EADC Start of Conversion Flag\r
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.\r
+ * |[19] |EADCTRGF3 |EADC Start of Conversion Flag\r
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.\r
+ * |[20] |EADCTRGF4 |EADC Start of Conversion Flag\r
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.\r
+ * |[21] |EADCTRGF5 |EADC Start of Conversion Flag\r
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.\r
+ * |[24] |DACTRGF |DAC Start of Conversion Flag\r
+ * | | |0 = Indicates no DAC start of conversion trigger event has occurred.\r
+ * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit\r
+ * @var EPWM_T::IFA[6]\r
+ * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter\r
+ * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\r
+ * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period.\r
+ * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select\r
+ * | | |00 = CNT equal to Zero in channel n.\r
+ * | | |01 = CNT equal to PERIOD in channel n.\r
+ * | | |10 = CNT equal to CMPU in channel n.\r
+ * | | |11 = CNT equal to CMPD in channel n.\r
+ * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits\r
+ * | | |0 = EPWM_CHn interrupt flag accumulator disable.\r
+ * | | |1 = EPWM_CHn interrupt flag accumulator enable.\r
+ * @var EPWM_T::AINTSTS\r
+ * Offset: 0x150 EPWM Accumulator Interrupt Flag Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\r
+ * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.\r
+ * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\r
+ * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.\r
+ * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\r
+ * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.\r
+ * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\r
+ * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.\r
+ * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\r
+ * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.\r
+ * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\r
+ * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.\r
+ * @var EPWM_T::AINTEN\r
+ * Offset: 0x154 EPWM Accumulator Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits\r
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.\r
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.\r
+ * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits\r
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.\r
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.\r
+ * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits\r
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.\r
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.\r
+ * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits\r
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.\r
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.\r
+ * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits\r
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.\r
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.\r
+ * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits\r
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.\r
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.\r
+ * @var EPWM_T::APDMACTL\r
+ * Offset: 0x158 EPWM Accumulator PDMA Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |APDMAEN0 |Channel N Accumulator PDMA Enable Bits\r
+ * | | |0 = Channel n PDMA function Disabled.\r
+ * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.\r
+ * |[1] |APDMAEN1 |Channel N Accumulator PDMA Enable Bits\r
+ * | | |0 = Channel n PDMA function Disabled.\r
+ * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.\r
+ * |[2] |APDMAEN2 |Channel N Accumulator PDMA Enable Bits\r
+ * | | |0 = Channel n PDMA function Disabled.\r
+ * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.\r
+ * |[3] |APDMAEN3 |Channel N Accumulator PDMA Enable Bits\r
+ * | | |0 = Channel n PDMA function Disabled.\r
+ * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.\r
+ * |[4] |APDMAEN4 |Channel N Accumulator PDMA Enable Bits\r
+ * | | |0 = Channel n PDMA function Disabled.\r
+ * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.\r
+ * |[5] |APDMAEN5 |Channel N Accumulator PDMA Enable Bits\r
+ * | | |0 = Channel n PDMA function Disabled.\r
+ * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.\r
+ * @var EPWM_T::CAPINEN\r
+ * Offset: 0x200 EPWM Capture Input Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CAPINEN0 |Capture Input Enable Bits\r
+ * | | |0 = EPWM Channel capture input path Disabled\r
+ * | | |The input of EPWM channel capture function is always regarded as 0.\r
+ * | | |1 = EPWM Channel capture input path Enabled\r
+ * | | |The input of EPWM channel capture function comes from correlative multifunction pin.\r
+ * |[1] |CAPINEN1 |Capture Input Enable Bits\r
+ * | | |0 = EPWM Channel capture input path Disabled\r
+ * | | |The input of EPWM channel capture function is always regarded as 0.\r
+ * | | |1 = EPWM Channel capture input path Enabled\r
+ * | | |The input of EPWM channel capture function comes from correlative multifunction pin.\r
+ * |[2] |CAPINEN2 |Capture Input Enable Bits\r
+ * | | |0 = EPWM Channel capture input path Disabled\r
+ * | | |The input of EPWM channel capture function is always regarded as 0.\r
+ * | | |1 = EPWM Channel capture input path Enabled\r
+ * | | |The input of EPWM channel capture function comes from correlative multifunction pin.\r
+ * |[3] |CAPINEN3 |Capture Input Enable Bits\r
+ * | | |0 = EPWM Channel capture input path Disabled\r
+ * | | |The input of EPWM channel capture function is always regarded as 0.\r
+ * | | |1 = EPWM Channel capture input path Enabled\r
+ * | | |The input of EPWM channel capture function comes from correlative multifunction pin.\r
+ * |[4] |CAPINEN4 |Capture Input Enable Bits\r
+ * | | |0 = EPWM Channel capture input path Disabled\r
+ * | | |The input of EPWM channel capture function is always regarded as 0.\r
+ * | | |1 = EPWM Channel capture input path Enabled\r
+ * | | |The input of EPWM channel capture function comes from correlative multifunction pin.\r
+ * |[5] |CAPINEN5 |Capture Input Enable Bits\r
+ * | | |0 = EPWM Channel capture input path Disabled\r
+ * | | |The input of EPWM channel capture function is always regarded as 0.\r
+ * | | |1 = EPWM Channel capture input path Enabled\r
+ * | | |The input of EPWM channel capture function comes from correlative multifunction pin.\r
+ * @var EPWM_T::CAPCTL\r
+ * Offset: 0x204 EPWM Capture Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CAPEN0 |Capture Function Enable Bits\r
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.\r
+ * | | |1 = Capture function Enabled\r
+ * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).\r
+ * |[1] |CAPEN1 |Capture Function Enable Bits\r
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.\r
+ * | | |1 = Capture function Enabled\r
+ * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).\r
+ * |[2] |CAPEN2 |Capture Function Enable Bits\r
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.\r
+ * | | |1 = Capture function Enabled\r
+ * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).\r
+ * |[3] |CAPEN3 |Capture Function Enable Bits\r
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.\r
+ * | | |1 = Capture function Enabled\r
+ * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).\r
+ * |[4] |CAPEN4 |Capture Function Enable Bits\r
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.\r
+ * | | |1 = Capture function Enabled\r
+ * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).\r
+ * |[5] |CAPEN5 |Capture Function Enable Bits\r
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.\r
+ * | | |1 = Capture function Enabled\r
+ * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).\r
+ * |[8] |CAPINV0 |Capture Inverter Enable Bits\r
+ * | | |0 = Capture source inverter Disabled.\r
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.\r
+ * |[9] |CAPINV1 |Capture Inverter Enable Bits\r
+ * | | |0 = Capture source inverter Disabled.\r
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.\r
+ * |[10] |CAPINV2 |Capture Inverter Enable Bits\r
+ * | | |0 = Capture source inverter Disabled.\r
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.\r
+ * |[11] |CAPINV3 |Capture Inverter Enable Bits\r
+ * | | |0 = Capture source inverter Disabled.\r
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.\r
+ * |[12] |CAPINV4 |Capture Inverter Enable Bits\r
+ * | | |0 = Capture source inverter Disabled.\r
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.\r
+ * |[13] |CAPINV5 |Capture Inverter Enable Bits\r
+ * | | |0 = Capture source inverter Disabled.\r
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.\r
+ * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits\r
+ * | | |0 = Rising capture reload counter Disabled.\r
+ * | | |1 = Rising capture reload counter Enabled.\r
+ * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits\r
+ * | | |0 = Rising capture reload counter Disabled.\r
+ * | | |1 = Rising capture reload counter Enabled.\r
+ * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits\r
+ * | | |0 = Rising capture reload counter Disabled.\r
+ * | | |1 = Rising capture reload counter Enabled.\r
+ * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits\r
+ * | | |0 = Rising capture reload counter Disabled.\r
+ * | | |1 = Rising capture reload counter Enabled.\r
+ * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits\r
+ * | | |0 = Rising capture reload counter Disabled.\r
+ * | | |1 = Rising capture reload counter Enabled.\r
+ * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits\r
+ * | | |0 = Rising capture reload counter Disabled.\r
+ * | | |1 = Rising capture reload counter Enabled.\r
+ * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits\r
+ * | | |0 = Falling capture reload counter Disabled.\r
+ * | | |1 = Falling capture reload counter Enabled.\r
+ * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits\r
+ * | | |0 = Falling capture reload counter Disabled.\r
+ * | | |1 = Falling capture reload counter Enabled.\r
+ * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits\r
+ * | | |0 = Falling capture reload counter Disabled.\r
+ * | | |1 = Falling capture reload counter Enabled.\r
+ * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits\r
+ * | | |0 = Falling capture reload counter Disabled.\r
+ * | | |1 = Falling capture reload counter Enabled.\r
+ * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits\r
+ * | | |0 = Falling capture reload counter Disabled.\r
+ * | | |1 = Falling capture reload counter Enabled.\r
+ * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits\r
+ * | | |0 = Falling capture reload counter Disabled.\r
+ * | | |1 = Falling capture reload counter Enabled.\r
+ * @var EPWM_T::CAPSTS\r
+ * Offset: 0x208 EPWM Capture Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.\r
+ * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.\r
+ * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.\r
+ * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.\r
+ * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.\r
+ * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.\r
+ * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.\r
+ * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.\r
+ * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.\r
+ * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.\r
+ * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.\r
+ * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\r
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.\r
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.\r
+ * @var EPWM_T::PDMACTL\r
+ * Offset: 0x23C EPWM PDMA Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable\r
+ * | | |0 = Channel 0/1 PDMA function Disabled.\r
+ * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.\r
+ * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer\r
+ * | | |00 = Reserved.\r
+ * | | |01 = EPWM_RCAPDAT0/1 register.\r
+ * | | |10 = EPWM_FCAPDAT0/1 register.\r
+ * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1 registers.\r
+ * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order\r
+ * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to = 0x3.\r
+ * | | |0 = EPWM_FCAPDAT0/1 register is the first captured data to memory.\r
+ * | | |1 = EPWM_RCAPDAT0/1 register is the first captured data to memory.\r
+ * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer\r
+ * | | |0 = Channel0.\r
+ * | | |1 = Channel1.\r
+ * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable\r
+ * | | |0 = Channel 2/3 PDMA function Disabled.\r
+ * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.\r
+ * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer\r
+ * | | |00 = Reserved.\r
+ * | | |01 = EPWM_RCAPDAT2/3 register.\r
+ * | | |10 = EPWM_FCAPDAT2/3 register.\r
+ * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3 registers.\r
+ * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order\r
+ * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to =0x3.\r
+ * | | |0 = EPWM_FCAPDAT2/3 register is the first captured data to memory.\r
+ * | | |1 = EPWM_RCAPDAT2/3 register is the first captured data to memory.\r
+ * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer\r
+ * | | |0 = Channel2.\r
+ * | | |1 = Channel3.\r
+ * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable\r
+ * | | |0 = Channel 4/5 PDMA function Disabled.\r
+ * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.\r
+ * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer\r
+ * | | |00 = Reserved.\r
+ * | | |01 = EPWM_RCAPDAT4/5 register.\r
+ * | | |10 = EPWM_FCAPDAT4/5 register.\r
+ * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5 registers.\r
+ * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order\r
+ * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits =are set to 0x3.\r
+ * | | |0 = EPWM_FCAPDAT4/5 register is the first captured data to memory.\r
+ * | | |1 = EPWM_RCAPDAT4/5 register is the first captured data to memory.\r
+ * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer\r
+ * | | |0 = Channel4.\r
+ * | | |1 = Channel5.\r
+ * @var EPWM_T::PDMACAP[3]\r
+ * Offset: 0x240 EPWM Capture Channel 01 PDMA Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only)\r
+ * | | |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA.\r
+ * @var EPWM_T::CAPIEN\r
+ * Offset: 0x250 EPWM Capture Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits\r
+ * | | |0 = Capture rising edge latch interrupt Disabled.\r
+ * | | |1 = Capture rising edge latch interrupt Enabled.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN0 bit must be disabled.\r
+ * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits\r
+ * | | |0 = Capture rising edge latch interrupt Disabled.\r
+ * | | |1 = Capture rising edge latch interrupt Enabled.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN1 bit must be disabled.\r
+ * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits\r
+ * | | |0 = Capture rising edge latch interrupt Disabled.\r
+ * | | |1 = Capture rising edge latch interrupt Enabled.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN2 bit must be disabled.\r
+ * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits\r
+ * | | |0 = Capture rising edge latch interrupt Disabled.\r
+ * | | |1 = Capture rising edge latch interrupt Enabled.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN3 bit must be disabled.\r
+ * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits\r
+ * | | |0 = Capture rising edge latch interrupt Disabled.\r
+ * | | |1 = Capture rising edge latch interrupt Enabled.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN4 bit must be disabled.\r
+ * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits\r
+ * | | |0 = Capture rising edge latch interrupt Disabled.\r
+ * | | |1 = Capture rising edge latch interrupt Enabled.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN5 bit must be disabled.\r
+ * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits\r
+ * | | |0 = Capture falling edge latch interrupt Disabled.\r
+ * | | |1 = Capture falling edge latch interrupt Enabled.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN0 bit must be disabled.\r
+ * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits\r
+ * | | |0 = Capture falling edge latch interrupt Disabled.\r
+ * | | |1 = Capture falling edge latch interrupt Enabled.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN1 bit must be disabled.\r
+ * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits\r
+ * | | |0 = Capture falling edge latch interrupt Disabled.\r
+ * | | |1 = Capture falling edge latch interrupt Enabled.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN2 bit must be disabled.\r
+ * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits\r
+ * | | |0 = Capture falling edge latch interrupt Disabled.\r
+ * | | |1 = Capture falling edge latch interrupt Enabled.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN3 bit must be disabled.\r
+ * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits\r
+ * | | |0 = Capture falling edge latch interrupt Disabled.\r
+ * | | |1 = Capture falling edge latch interrupt Enabled.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN4 bit must be disabled.\r
+ * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits\r
+ * | | |0 = Capture falling edge latch interrupt Disabled.\r
+ * | | |1 = Capture falling edge latch interrupt Enabled.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN5 bit must be disabled.\r
+ * @var EPWM_T::CAPIF\r
+ * Offset: 0x254 EPWM Capture Interrupt Flag Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear.\r
+ * | | |0 = No capture rising latch condition happened.\r
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF0 bit will cleared by hardware after PDMA transfer data.\r
+ * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear.\r
+ * | | |0 = No capture rising latch condition happened.\r
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF1 bit will cleared by hardware after PDMA transfer data.\r
+ * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear.\r
+ * | | |0 = No capture rising latch condition happened.\r
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF2 bit will cleared by hardware after PDMA transfer data.\r
+ * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear.\r
+ * | | |0 = No capture rising latch condition happened.\r
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF3 bit will cleared by hardware after PDMA transfer data.\r
+ * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear.\r
+ * | | |0 = No capture rising latch condition happened.\r
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF4 bit will cleared by hardware after PDMA transfer data.\r
+ * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear.\r
+ * | | |0 = No capture rising latch condition happened.\r
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF5 bit will cleared by hardware after PDMA transfer data.\r
+ * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear.\r
+ * | | |0 = No capture falling latch condition happened.\r
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF0 bit will cleared by hardware after PDMA transfer data.\r
+ * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear.\r
+ * | | |0 = No capture falling latch condition happened.\r
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF1 bit will cleared by hardware after PDMA transfer data.\r
+ * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear.\r
+ * | | |0 = No capture falling latch condition happened.\r
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF2 bit will cleared by hardware after PDMA transfer data.\r
+ * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear.\r
+ * | | |0 = No capture falling latch condition happened.\r
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF3 bit will cleared by hardware after PDMA transfer data.\r
+ * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear.\r
+ * | | |0 = No capture falling latch condition happened.\r
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.\r
+ * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF4 bit will cleared by hardware after PDMA transfer data.\r
+ * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag\r
+ * | | |This bit is writing 1 to clear.\r
+ * | | |0 = No capture falling latch condition happened.\r
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.\r
+ * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.\r
+ * @var EPWM_T::PBUF[6]\r
+ * Offset: 0x304 EPWM PERIOD0~5 Buffer\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only)\r
+ * | | |Used as PERIOD active register.\r
+ * @var EPWM_T::CMPBUF[6]\r
+ * Offset: 0x31C EPWM CMPDAT0~5 Buffer\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only)\r
+ * | | |Used as CMP active register.\r
+ * @var EPWM_T::CPSCBUF[3]\r
+ * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer\r
+ * | | |Use as EPWM counter clock prescale active register.\r
+ * @var EPWM_T::FTCBUF[3]\r
+ * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only)\r
+ * | | |Used as FTCMPDAT active register.\r
+ * @var EPWM_T::FTCI\r
+ * Offset: 0x34C EPWM FTCMPDAT Indicator Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator\r
+ * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.\r
+ * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator\r
+ * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.\r
+ * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator\r
+ * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.\r
+ * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator\r
+ * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.\r
+ * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator\r
+ * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.\r
+ * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator\r
+ * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.\r
+ */\r
+ __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */\r
+ __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */\r
+ __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */\r
+ __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */\r
+ __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */\r
+ __IO uint32_t CLKPSC[3]; /*!< [0x0014~0x001c] EPWM Clock Prescale Register 0_1,2_3,4_5 */\r
+ __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */\r
+ __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */\r
+ __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */\r
+ __I uint32_t RESERVE0[1];\r
+ __IO uint32_t PERIOD[6]; /*!< [0x0030~0x0044] EPWM Period Register 0~5 */\r
+ __I uint32_t RESERVE1[2];\r
+ __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] EPWM Comparator Register 0~5 */\r
+ __I uint32_t RESERVE2[2];\r
+ __IO uint32_t DTCTL[3]; /*!< [0x0070~0x0078] EPWM Dead-Time Control Register 0_1,2_3,4_5 */\r
+ __I uint32_t RESERVE3[1];\r
+ __IO uint32_t PHS[3]; /*!< [0x0080~0x0088] EPWM Counter Phase Register 0_1,2_3,4_5 */\r
+ __I uint32_t RESERVE4[1];\r
+ __I uint32_t CNT[6]; /*!< [0x0090~0x00A4 EPWM Counter Register 0~5 */\r
+ __I uint32_t RESERVE5[2];\r
+ __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */\r
+ __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */\r
+ __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */\r
+ __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */\r
+ __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */\r
+ __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */\r
+ __IO uint32_t BRKCTL[3]; /*!< [0x00c8~0x00d0] EPWM Brake Edge Detect Control Register 0_1,2_3,4_5 */\r
+ __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */\r
+ __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */\r
+ __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */\r
+ __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */\r
+ __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */\r
+ __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */\r
+ __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */\r
+ __I uint32_t RESERVE6[1];\r
+ __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */\r
+ __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */\r
+ __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */\r
+ __IO uint32_t FTCMPDAT[3]; /*!< [0x0100~0x108] EPWM Free Trigger Compare Register 0_1,2_3,4_5 */\r
+ __I uint32_t RESERVE7[1];\r
+ __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */\r
+ __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */\r
+ __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */\r
+ __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */\r
+ __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */\r
+ __I uint32_t RESERVE8[3];\r
+ __IO uint32_t IFA[6]; /*!< [0x0130~0x144] EPWM Interrupt Flag Accumulator Register 0~5 */\r
+ __I uint32_t RESERVE9[2];\r
+ __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */\r
+ __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */\r
+ __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */\r
+ __I uint32_t RESERVE10[41];\r
+ __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */\r
+ __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */\r
+ __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */\r
+ ECAPDAT_T CAPDAT[6]; /*!< [0x020c~0x0238] EPWM Rising and Falling Capture Data Register 0~5 */\r
+ __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */\r
+ __I uint32_t PDMACAP[3]; /*!< [0x0240~0x248] EPWM Capture Channel 0_1,2_3,4_5 PDMA Register */\r
+ __I uint32_t RESERVE11[1];\r
+ __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */\r
+ __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */\r
+ __I uint32_t RESERVE12[43];\r
+ __I uint32_t PBUF[6]; /*!< [0x0304~0x0318 EPWM PERIOD0~5 Buffer */\r
+ __I uint32_t CMPBUF[6]; /*!< [0x031C~0x0330 EPWM CMPDAT0~5 Buffer */\r
+ __I uint32_t CPSCBUF[3]; /*!< [0x0334~0x33c] EPWM CLKPSC0_1,2_3,4_5 Buffer */\r
+ __I uint32_t FTCBUF[3]; /*!< [0x0340~0x348] EPWM FTCMPDAT0_1,2_3,4_5 Buffer */\r
+ __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */\r
+\r
+} EPWM_T;\r
+\r
+/**\r
+ @addtogroup EPWM_CONST EPWM Bit Field Definition\r
+ Constant Definitions for EPWM Controller\r
+@{ */\r
+\r
+#define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */\r
+#define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */\r
+\r
+#define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */\r
+#define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */\r
+\r
+#define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */\r
+#define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */\r
+\r
+#define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */\r
+#define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */\r
+\r
+#define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */\r
+#define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */\r
+\r
+#define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */\r
+#define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */\r
+\r
+#define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */\r
+#define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */\r
+\r
+#define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */\r
+#define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */\r
+\r
+#define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */\r
+#define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */\r
+\r
+#define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */\r
+#define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */\r
+\r
+#define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */\r
+#define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */\r
+\r
+#define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */\r
+#define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */\r
+\r
+#define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */\r
+#define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */\r
+\r
+#define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */\r
+#define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */\r
+\r
+#define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */\r
+#define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */\r
+\r
+#define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */\r
+#define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */\r
+\r
+#define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */\r
+#define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */\r
+\r
+#define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */\r
+#define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */\r
+\r
+#define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */\r
+#define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */\r
+\r
+#define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */\r
+#define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */\r
+\r
+#define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */\r
+#define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */\r
+\r
+#define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */\r
+#define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */\r
+\r
+#define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */\r
+#define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */\r
+\r
+#define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */\r
+#define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */\r
+\r
+#define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */\r
+#define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */\r
+\r
+#define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */\r
+#define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */\r
+\r
+#define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */\r
+#define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */\r
+\r
+#define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */\r
+#define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */\r
+\r
+#define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */\r
+#define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */\r
+\r
+#define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */\r
+#define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */\r
+\r
+#define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */\r
+#define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */\r
+\r
+#define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */\r
+#define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */\r
+\r
+#define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */\r
+#define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */\r
+\r
+#define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */\r
+#define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */\r
+\r
+#define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */\r
+#define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */\r
+\r
+#define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */\r
+#define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */\r
+\r
+#define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */\r
+#define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */\r
+\r
+#define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */\r
+#define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */\r
+\r
+#define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */\r
+#define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */\r
+\r
+#define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */\r
+#define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */\r
+\r
+#define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */\r
+#define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */\r
+\r
+#define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */\r
+#define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */\r
+\r
+#define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */\r
+#define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */\r
+\r
+#define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */\r
+#define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */\r
+\r
+#define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */\r
+#define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */\r
+\r
+#define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */\r
+#define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */\r
+\r
+#define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */\r
+#define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */\r
+\r
+#define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */\r
+#define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */\r
+\r
+#define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */\r
+#define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */\r
+\r
+#define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */\r
+#define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */\r
+\r
+#define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */\r
+#define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */\r
+\r
+#define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */\r
+#define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */\r
+\r
+#define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */\r
+#define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */\r
+\r
+#define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */\r
+#define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */\r
+\r
+#define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */\r
+#define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */\r
+\r
+#define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */\r
+#define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */\r
+\r
+#define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */\r
+#define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */\r
+\r
+#define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */\r
+#define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */\r
+\r
+#define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */\r
+#define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */\r
+\r
+#define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */\r
+#define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */\r
+\r
+#define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */\r
+#define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */\r
+\r
+#define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */\r
+#define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */\r
+\r
+#define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */\r
+#define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */\r
+\r
+#define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */\r
+#define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */\r
+\r
+#define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */\r
+#define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */\r
+\r
+#define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */\r
+#define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */\r
+\r
+#define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */\r
+#define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */\r
+\r
+#define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */\r
+#define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */\r
+\r
+#define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */\r
+#define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */\r
+\r
+#define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */\r
+#define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */\r
+\r
+#define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */\r
+#define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */\r
+\r
+#define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */\r
+#define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */\r
+\r
+#define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */\r
+#define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */\r
+\r
+#define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */\r
+#define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */\r
+\r
+#define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */\r
+#define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */\r
+\r
+#define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */\r
+#define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */\r
+\r
+#define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */\r
+#define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */\r
+\r
+#define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */\r
+#define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */\r
+\r
+#define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */\r
+#define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */\r
+\r
+#define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */\r
+#define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */\r
+\r
+#define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */\r
+#define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */\r
+\r
+#define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */\r
+#define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */\r
+\r
+#define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */\r
+#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */\r
+\r
+#define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */\r
+#define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */\r
+\r
+#define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */\r
+#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */\r
+\r
+#define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */\r
+#define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */\r
+\r
+#define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */\r
+#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */\r
+\r
+#define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */\r
+#define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */\r
+\r
+#define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */\r
+#define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */\r
+\r
+#define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */\r
+#define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */\r
+\r
+#define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */\r
+#define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */\r
+\r
+#define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */\r
+#define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */\r
+\r
+#define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */\r
+#define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */\r
+\r
+#define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */\r
+#define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */\r
+\r
+#define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */\r
+#define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */\r
+\r
+#define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */\r
+#define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */\r
+\r
+#define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */\r
+#define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */\r
+\r
+#define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */\r
+#define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */\r
+\r
+#define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */\r
+#define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */\r
+\r
+#define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */\r
+#define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */\r
+\r
+#define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */\r
+#define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */\r
+\r
+#define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */\r
+#define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */\r
+\r
+#define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */\r
+#define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */\r
+\r
+#define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */\r
+#define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */\r
+\r
+#define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */\r
+#define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */\r
+\r
+#define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */\r
+#define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */\r
+\r
+#define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */\r
+#define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */\r
+\r
+#define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */\r
+#define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */\r
+\r
+#define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */\r
+#define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */\r
+\r
+#define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */\r
+#define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */\r
+\r
+#define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */\r
+#define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */\r
+\r
+#define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */\r
+#define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */\r
+\r
+#define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */\r
+#define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */\r
+\r
+#define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */\r
+#define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */\r
+\r
+#define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */\r
+#define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */\r
+\r
+#define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */\r
+#define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */\r
+\r
+#define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */\r
+#define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */\r
+\r
+#define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */\r
+#define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */\r
+\r
+#define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */\r
+#define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */\r
+\r
+#define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */\r
+#define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */\r
+\r
+#define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */\r
+#define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */\r
+\r
+#define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */\r
+#define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */\r
+\r
+#define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */\r
+#define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */\r
+\r
+#define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */\r
+#define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */\r
+\r
+#define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */\r
+#define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */\r
+\r
+#define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */\r
+#define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */\r
+\r
+#define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */\r
+#define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */\r
+\r
+#define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */\r
+#define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */\r
+\r
+#define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */\r
+#define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */\r
+\r
+#define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */\r
+#define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */\r
+\r
+#define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */\r
+#define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */\r
+\r
+#define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */\r
+#define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */\r
+\r
+#define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */\r
+#define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */\r
+\r
+#define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */\r
+#define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */\r
+\r
+#define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */\r
+#define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */\r
+\r
+#define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */\r
+#define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */\r
+\r
+#define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */\r
+#define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */\r
+\r
+#define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */\r
+#define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */\r
+\r
+#define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */\r
+#define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */\r
+\r
+#define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */\r
+#define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */\r
+\r
+#define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */\r
+#define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */\r
+\r
+#define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */\r
+#define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */\r
+\r
+#define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */\r
+#define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */\r
+\r
+#define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */\r
+#define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */\r
+\r
+#define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */\r
+#define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */\r
+\r
+#define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */\r
+#define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */\r
+\r
+#define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */\r
+#define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */\r
+\r
+#define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */\r
+#define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */\r
+\r
+#define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */\r
+#define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */\r
+\r
+#define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */\r
+#define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */\r
+\r
+#define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */\r
+#define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */\r
+\r
+#define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */\r
+#define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */\r
+\r
+#define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */\r
+#define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */\r
+\r
+#define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */\r
+#define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */\r
+\r
+#define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */\r
+#define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */\r
+\r
+#define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */\r
+#define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */\r
+\r
+#define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */\r
+#define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */\r
+\r
+#define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */\r
+#define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */\r
+\r
+#define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */\r
+#define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */\r
+\r
+#define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */\r
+#define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */\r
+\r
+#define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */\r
+#define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */\r
+\r
+#define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */\r
+#define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */\r
+#define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */\r
+#define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */\r
+#define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */\r
+#define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */\r
+#define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */\r
+#define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */\r
+#define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */\r
+#define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */\r
+#define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */\r
+#define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */\r
+#define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */\r
+#define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */\r
+\r
+#define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */\r
+#define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */\r
+\r
+#define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */\r
+#define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */\r
+#define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */\r
+#define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */\r
+#define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */\r
+#define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */\r
+#define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */\r
+#define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */\r
+#define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */\r
+#define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */\r
+#define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */\r
+#define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */\r
+#define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */\r
+#define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */\r
+\r
+#define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */\r
+#define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */\r
+\r
+#define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */\r
+#define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */\r
+#define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */\r
+#define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */\r
+#define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */\r
+#define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */\r
+#define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */\r
+#define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */\r
+#define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */\r
+#define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */\r
+#define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */\r
+#define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */\r
+#define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */\r
+#define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */\r
+\r
+#define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */\r
+#define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */\r
+\r
+#define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */\r
+#define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */\r
+\r
+#define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */\r
+#define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */\r
+\r
+#define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */\r
+#define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */\r
+\r
+#define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */\r
+#define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */\r
+\r
+#define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */\r
+#define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */\r
+\r
+#define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */\r
+#define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */\r
+\r
+#define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */\r
+#define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */\r
+\r
+#define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */\r
+#define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */\r
+\r
+#define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */\r
+#define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */\r
+\r
+#define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */\r
+#define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */\r
+\r
+#define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */\r
+#define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */\r
+\r
+#define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */\r
+#define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */\r
+\r
+#define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */\r
+#define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */\r
+\r
+#define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */\r
+#define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */\r
+\r
+#define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */\r
+#define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */\r
+\r
+#define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */\r
+#define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */\r
+\r
+#define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */\r
+#define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */\r
+\r
+#define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */\r
+#define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */\r
+\r
+#define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */\r
+#define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */\r
+\r
+#define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */\r
+#define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */\r
+\r
+#define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */\r
+#define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */\r
+\r
+#define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */\r
+#define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */\r
+\r
+#define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */\r
+#define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */\r
+\r
+#define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */\r
+#define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */\r
+\r
+#define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */\r
+#define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */\r
+\r
+#define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */\r
+#define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */\r
+\r
+#define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */\r
+#define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */\r
+\r
+#define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */\r
+#define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */\r
+\r
+#define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */\r
+#define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */\r
+\r
+#define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */\r
+#define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */\r
+\r
+#define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */\r
+#define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */\r
+\r
+#define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */\r
+#define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */\r
+\r
+#define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */\r
+#define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */\r
+\r
+#define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */\r
+#define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */\r
+\r
+#define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */\r
+#define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */\r
+\r
+#define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */\r
+#define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */\r
+\r
+#define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */\r
+#define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */\r
+\r
+#define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */\r
+#define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */\r
+\r
+#define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */\r
+#define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */\r
+\r
+#define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */\r
+#define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */\r
+\r
+#define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */\r
+#define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */\r
+\r
+#define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */\r
+#define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */\r
+\r
+#define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */\r
+#define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */\r
+\r
+#define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */\r
+#define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */\r
+\r
+#define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */\r
+#define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */\r
+\r
+#define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */\r
+#define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */\r
+\r
+#define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */\r
+#define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */\r
+\r
+#define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */\r
+#define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */\r
+\r
+#define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */\r
+#define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */\r
+\r
+#define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */\r
+#define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */\r
+\r
+#define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */\r
+#define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */\r
+\r
+#define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */\r
+#define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */\r
+\r
+#define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */\r
+#define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */\r
+\r
+#define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */\r
+#define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */\r
+\r
+#define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */\r
+#define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */\r
+\r
+#define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */\r
+#define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */\r
+\r
+#define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */\r
+#define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */\r
+\r
+#define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */\r
+#define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */\r
+\r
+#define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */\r
+#define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */\r
+\r
+#define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */\r
+#define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */\r
+\r
+#define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */\r
+#define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */\r
+\r
+#define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */\r
+#define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */\r
+\r
+#define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */\r
+#define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */\r
+\r
+#define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */\r
+#define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */\r
+\r
+#define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */\r
+#define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */\r
+\r
+#define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */\r
+#define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */\r
+\r
+#define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */\r
+#define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */\r
+\r
+#define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */\r
+#define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */\r
+\r
+#define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */\r
+#define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */\r
+\r
+#define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */\r
+#define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */\r
+\r
+#define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */\r
+#define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */\r
+\r
+#define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */\r
+#define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */\r
+\r
+#define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */\r
+#define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */\r
+#define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */\r
+#define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */\r
+#define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */\r
+#define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */\r
+#define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */\r
+#define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */\r
+#define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */\r
+#define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */\r
+#define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */\r
+#define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */\r
+#define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */\r
+#define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */\r
+#define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */\r
+#define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */\r
+#define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */\r
+#define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */\r
+#define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */\r
+#define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */\r
+#define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */\r
+#define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */\r
+#define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */\r
+#define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */\r
+#define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */\r
+\r
+#define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */\r
+#define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */\r
+\r
+#define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */\r
+#define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */\r
+\r
+#define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */\r
+#define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */\r
+\r
+#define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */\r
+#define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */\r
+\r
+#define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */\r
+#define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */\r
+\r
+#define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */\r
+#define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */\r
+\r
+#define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */\r
+#define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */\r
+\r
+#define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */\r
+#define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */\r
+\r
+#define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */\r
+#define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */\r
+\r
+#define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */\r
+#define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */\r
+\r
+#define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */\r
+#define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */\r
+\r
+#define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */\r
+#define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */\r
+\r
+#define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */\r
+#define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */\r
+\r
+#define EPWM_DACTRGEN_CUTRGE0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGE0 Position */\r
+#define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask */\r
+\r
+#define EPWM_DACTRGEN_CUTRGE1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGE1 Position */\r
+#define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask */\r
+\r
+#define EPWM_DACTRGEN_CUTRGE2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGE2 Position */\r
+#define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask */\r
+\r
+#define EPWM_DACTRGEN_CUTRGE3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGE3 Position */\r
+#define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask */\r
+\r
+#define EPWM_DACTRGEN_CUTRGE4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGE4 Position */\r
+#define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask */\r
+\r
+#define EPWM_DACTRGEN_CUTRGE5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGE5 Position */\r
+#define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask */\r
+\r
+#define EPWM_DACTRGEN_CDTRGE0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGE0 Position */\r
+#define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask */\r
+\r
+#define EPWM_DACTRGEN_CDTRGE1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGE1 Position */\r
+#define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask */\r
+\r
+#define EPWM_DACTRGEN_CDTRGE2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGE2 Position */\r
+#define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask */\r
+\r
+#define EPWM_DACTRGEN_CDTRGE3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGE3 Position */\r
+#define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask */\r
+\r
+#define EPWM_DACTRGEN_CDTRGE4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGE4 Position */\r
+#define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask */\r
+\r
+#define EPWM_DACTRGEN_CDTRGE5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGE5 Position */\r
+#define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask */\r
+\r
+#define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */\r
+#define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */\r
+\r
+#define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */\r
+#define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */\r
+\r
+#define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */\r
+#define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */\r
+\r
+#define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */\r
+#define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */\r
+\r
+#define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */\r
+#define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */\r
+\r
+#define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */\r
+#define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */\r
+\r
+#define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */\r
+#define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */\r
+\r
+#define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */\r
+#define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */\r
+\r
+#define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */\r
+#define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */\r
+\r
+#define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */\r
+#define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */\r
+\r
+#define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */\r
+#define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */\r
+\r
+#define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */\r
+#define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */\r
+\r
+#define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */\r
+#define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */\r
+\r
+#define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */\r
+#define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */\r
+\r
+#define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */\r
+#define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */\r
+\r
+#define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */\r
+#define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */\r
+\r
+#define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */\r
+#define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */\r
+\r
+#define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */\r
+#define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */\r
+\r
+#define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */\r
+#define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */\r
+\r
+#define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */\r
+#define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */\r
+\r
+#define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */\r
+#define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */\r
+\r
+#define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */\r
+#define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */\r
+\r
+#define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */\r
+#define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */\r
+\r
+#define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */\r
+#define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */\r
+\r
+#define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */\r
+#define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */\r
+\r
+#define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */\r
+#define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */\r
+\r
+#define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */\r
+#define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */\r
+\r
+#define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */\r
+#define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */\r
+\r
+#define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */\r
+#define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */\r
+\r
+#define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */\r
+#define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */\r
+\r
+#define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */\r
+#define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */\r
+\r
+#define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */\r
+#define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */\r
+\r
+#define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */\r
+#define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */\r
+\r
+#define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */\r
+#define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */\r
+\r
+#define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */\r
+#define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */\r
+\r
+#define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */\r
+#define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */\r
+\r
+#define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */\r
+#define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */\r
+\r
+#define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */\r
+#define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */\r
+\r
+#define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */\r
+#define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */\r
+\r
+#define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */\r
+#define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */\r
+\r
+#define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */\r
+#define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */\r
+\r
+#define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */\r
+#define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */\r
+\r
+#define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */\r
+#define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */\r
+\r
+#define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */\r
+#define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */\r
+\r
+#define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */\r
+#define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */\r
+\r
+#define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */\r
+#define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */\r
+\r
+#define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */\r
+#define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */\r
+\r
+#define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */\r
+#define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */\r
+\r
+#define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */\r
+#define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */\r
+\r
+#define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */\r
+#define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */\r
+\r
+#define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */\r
+#define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */\r
+\r
+#define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */\r
+#define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */\r
+\r
+#define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */\r
+#define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */\r
+\r
+#define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */\r
+#define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */\r
+\r
+#define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */\r
+#define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */\r
+\r
+#define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */\r
+#define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */\r
+\r
+#define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */\r
+#define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */\r
+\r
+#define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */\r
+#define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */\r
+\r
+#define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */\r
+#define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */\r
+\r
+#define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */\r
+#define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */\r
+\r
+#define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */\r
+#define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */\r
+\r
+#define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */\r
+#define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */\r
+\r
+#define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */\r
+#define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */\r
+\r
+#define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */\r
+#define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */\r
+\r
+#define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */\r
+#define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */\r
+\r
+#define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */\r
+#define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */\r
+\r
+#define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */\r
+#define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */\r
+\r
+#define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */\r
+#define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */\r
+\r
+#define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */\r
+#define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */\r
+\r
+#define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */\r
+#define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */\r
+\r
+#define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */\r
+#define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */\r
+\r
+#define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */\r
+#define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */\r
+\r
+#define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */\r
+#define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */\r
+\r
+#define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */\r
+#define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */\r
+\r
+#define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */\r
+#define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */\r
+\r
+#define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */\r
+#define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */\r
+\r
+#define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */\r
+#define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */\r
+\r
+#define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */\r
+#define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */\r
+\r
+#define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */\r
+#define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */\r
+\r
+#define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */\r
+#define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */\r
+\r
+#define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */\r
+#define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */\r
+\r
+#define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */\r
+#define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */\r
+\r
+#define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */\r
+#define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */\r
+\r
+#define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */\r
+#define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */\r
+\r
+#define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */\r
+#define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */\r
+\r
+#define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */\r
+#define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */\r
+\r
+#define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */\r
+#define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */\r
+\r
+#define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */\r
+#define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */\r
+\r
+#define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */\r
+#define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */\r
+\r
+#define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */\r
+#define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */\r
+\r
+#define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */\r
+#define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */\r
+\r
+#define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */\r
+#define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */\r
+\r
+#define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */\r
+#define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */\r
+\r
+#define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */\r
+#define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */\r
+\r
+#define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */\r
+#define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */\r
+\r
+#define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */\r
+#define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */\r
+\r
+#define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */\r
+#define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */\r
+\r
+#define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */\r
+#define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */\r
+\r
+#define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */\r
+#define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */\r
+\r
+#define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */\r
+#define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */\r
+\r
+#define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */\r
+#define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */\r
+\r
+#define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */\r
+#define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */\r
+\r
+#define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */\r
+#define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */\r
+\r
+#define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */\r
+#define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */\r
+\r
+#define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */\r
+#define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */\r
+\r
+#define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */\r
+#define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */\r
+\r
+#define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */\r
+#define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */\r
+\r
+#define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */\r
+#define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */\r
+\r
+#define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */\r
+#define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */\r
+\r
+#define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */\r
+#define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */\r
+\r
+#define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */\r
+#define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */\r
+\r
+#define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */\r
+#define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */\r
+\r
+#define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */\r
+#define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */\r
+\r
+#define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */\r
+#define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */\r
+\r
+#define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */\r
+#define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */\r
+\r
+#define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */\r
+#define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */\r
+\r
+#define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */\r
+#define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */\r
+\r
+#define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */\r
+#define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */\r
+\r
+#define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */\r
+#define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */\r
+\r
+#define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */\r
+#define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */\r
+\r
+#define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */\r
+#define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */\r
+\r
+#define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */\r
+#define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */\r
+\r
+#define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */\r
+#define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */\r
+\r
+#define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */\r
+#define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */\r
+\r
+#define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */\r
+#define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */\r
+\r
+#define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */\r
+#define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */\r
+\r
+#define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */\r
+#define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */\r
+\r
+#define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */\r
+#define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */\r
+\r
+#define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */\r
+#define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */\r
+\r
+#define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */\r
+#define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */\r
+\r
+#define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */\r
+#define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */\r
+\r
+#define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */\r
+#define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */\r
+\r
+#define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */\r
+#define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */\r
+\r
+#define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */\r
+#define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */\r
+\r
+#define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */\r
+#define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */\r
+\r
+#define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */\r
+#define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */\r
+\r
+#define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */\r
+#define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */\r
+\r
+#define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */\r
+#define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */\r
+\r
+#define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */\r
+#define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */\r
+\r
+#define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */\r
+#define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */\r
+\r
+#define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */\r
+#define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */\r
+\r
+#define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */\r
+#define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */\r
+\r
+#define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */\r
+#define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */\r
+\r
+#define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */\r
+#define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */\r
+\r
+#define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */\r
+#define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */\r
+\r
+#define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */\r
+#define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */\r
+\r
+#define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */\r
+#define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */\r
+\r
+#define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */\r
+#define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */\r
+\r
+#define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */\r
+#define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */\r
+\r
+#define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */\r
+#define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */\r
+\r
+#define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */\r
+#define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */\r
+\r
+#define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */\r
+#define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */\r
+\r
+#define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */\r
+#define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */\r
+\r
+#define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */\r
+#define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */\r
+\r
+#define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */\r
+#define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */\r
+\r
+#define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */\r
+#define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */\r
+\r
+#define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */\r
+#define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */\r
+\r
+#define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */\r
+#define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */\r
+\r
+#define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */\r
+#define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */\r
+\r
+#define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */\r
+#define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */\r
+\r
+#define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */\r
+#define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */\r
+\r
+#define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */\r
+#define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */\r
+\r
+#define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */\r
+#define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */\r
+\r
+#define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */\r
+#define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */\r
+\r
+#define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */\r
+#define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */\r
+\r
+#define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */\r
+#define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */\r
+\r
+#define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */\r
+#define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */\r
+\r
+#define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */\r
+#define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */\r
+\r
+#define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */\r
+#define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */\r
+\r
+#define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */\r
+#define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */\r
+\r
+#define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */\r
+#define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */\r
+\r
+#define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */\r
+#define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */\r
+\r
+#define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */\r
+#define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */\r
+\r
+#define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */\r
+#define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */\r
+\r
+#define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */\r
+#define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */\r
+\r
+#define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */\r
+#define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */\r
+\r
+#define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */\r
+#define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */\r
+\r
+#define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */\r
+#define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */\r
+\r
+#define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */\r
+#define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */\r
+\r
+#define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */\r
+#define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */\r
+\r
+#define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */\r
+#define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */\r
+\r
+#define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */\r
+#define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */\r
+\r
+#define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */\r
+#define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */\r
+\r
+#define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */\r
+#define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */\r
+\r
+#define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */\r
+#define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */\r
+\r
+#define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */\r
+#define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */\r
+\r
+#define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */\r
+#define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */\r
+\r
+#define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */\r
+#define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */\r
+\r
+#define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */\r
+#define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */\r
+\r
+#define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */\r
+#define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */\r
+\r
+#define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */\r
+#define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */\r
+\r
+#define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */\r
+#define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */\r
+\r
+#define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */\r
+#define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */\r
+\r
+#define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */\r
+#define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */\r
+\r
+#define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */\r
+#define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */\r
+\r
+#define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */\r
+#define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */\r
+\r
+#define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */\r
+#define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */\r
+\r
+#define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */\r
+#define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */\r
+\r
+/**@}*/ /* EPWM_CONST */\r
+/**@}*/ /* end of EPWM register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+\r
+#endif /* __EPWM_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file fmc_reg.h\r
+ * @version V1.00\r
+ * @brief FMC register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __FMC_REG_H__\r
+#define __FMC_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- Flash Memory Controller -------------------------*/\r
+/**\r
+ @addtogroup FMC Flash Memory Controller(FMC)\r
+ Memory Mapped Structure for FMC Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var FMC_T::ISPCTL\r
+ * Offset: 0x00 ISP Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ISPEN |ISP Enable Bit (Write Protect)\r
+ * | | |ISP function enable bit. Set this bit to enable ISP function.\r
+ * | | |0 = ISP function Disabled.\r
+ * | | |1 = ISP function Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[1] |BS |Boot Select (Write Protect)\r
+ * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively\r
+ * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from\r
+ * | | |This bit is initiated with the inverse value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened\r
+ * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.\r
+ * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[3] |APUEN |APROM Update Enable Bit (Write Protect)\r
+ * | | |0 = APROM cannot be updated when the chip runs in APROM.\r
+ * | | |1 = APROM can be updated when the chip runs in APROM.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)\r
+ * | | |0 = CONFIG cannot be updated.\r
+ * | | |1 = CONFIG can be updated.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)\r
+ * | | |LDROM update enable bit.\r
+ * | | |0 = LDROM cannot be updated.\r
+ * | | |1 = LDROM can be updated.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[6] |ISPFF |ISP Fail Flag (Write Protect)\r
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:\r
+ * | | |This bit needs to be cleared by writing 1 to it.\r
+ * | | |(1) APROM writes to itself if APUEN is set to 0.\r
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.\r
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.\r
+ * | | |(4) Page Erase command at LOCK mode with ICE connection\r
+ * | | |(5) Erase or Program command at brown-out detected\r
+ * | | |(6) Destination address is illegal, such as over an available range.\r
+ * | | |(7) Invalid ISP commands\r
+ * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1\r
+ * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1\r
+ * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1\r
+ * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0\r
+ * | | |(12) Read any content of boot loader with ICE connection\r
+ * | | |(13) The address of block erase and bank erase is not in APROM\r
+ * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command\r
+ * | | |(15) The wrong setting of page erase ISP CMD in XOM\r
+ * | | |(16) Violate XOM setting one time protection\r
+ * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page\r
+ * | | |(18) Mass erase when MERASE (CFG0[13]) is disable\r
+ * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[16] |BL |Boot Loader Booting (Write Protect)\r
+ * | | |This bit is initiated with the inverses value of MBS (CONFIG0[5])\r
+ * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded\r
+ * | | |This bit is used to check chip boot from Boot Loader or not\r
+ * | | |User should keep original value of this bit when updating FMC_ISPCTL register.\r
+ * | | |0 = Booting from APROM or LDROM.\r
+ * | | |1 = Booting from Boot Loader.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[24] |INTEN |Interrupt Enable (Write Protect)\r
+ * | | |0 = ISP INT Disabled.\r
+ * | | |1 = ISP INT Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. Before use INT, user need to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time.\r
+ * @var FMC_T::ISPADDR\r
+ * Offset: 0x04 ISP Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ISPADDR |ISP Address\r
+ * | | |The NuMicro M2351 series is equipped with embedded flash\r
+ * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation\r
+ * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.\r
+ * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 KBytes alignment is necessary for CRC32 checksum calculation.\r
+ * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte)\r
+ * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte).\r
+ * @var FMC_T::ISPDAT\r
+ * Offset: 0x08 ISP Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ISPDAT |ISP Data\r
+ * | | |Write data to this register before ISP program operation.\r
+ * | | |Read data from this register after ISP read operation.\r
+ * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff\r
+ * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 2 KBytes alignment\r
+ * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result\r
+ * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect\r
+ * | | |For XOM page erase function, , ISPDAT = 0x0055_aa03.\r
+ * @var FMC_T::ISPCMD\r
+ * Offset: 0x0C ISP Command Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[6:0] |CMD |ISP Command\r
+ * | | |ISP command table is shown below:\r
+ * | | |0x00= FLASH Read.\r
+ * | | |0x04= Read Unique ID.\r
+ * | | |0x08= Read Flash All-One Result.\r
+ * | | |0x0B= Read Company ID.\r
+ * | | |0x0C= Read Device ID.\r
+ * | | |0x0D= Read Checksum.\r
+ * | | |0x21= FLASH 32-bit Program.\r
+ * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP.\r
+ * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1.\r
+ * | | |0x25= FLASH Block Erase Erase four pages alignment of APROM in BANK0 or BANK1..\r
+ * | | |0x27= FLASH Multi-Word Program.\r
+ * | | |0x28= Run Flash All-One Verification.\r
+ * | | |0x2D= Run Checksum Calculation.\r
+ * | | |0x2E= Vector Remap.\r
+ * | | |0x40= FLASH 64-bit Read.\r
+ * | | |0x61= FLASH 64-bit Program.\r
+ * | | |The other commands are invalid.\r
+ * @var FMC_T::ISPTRG\r
+ * Offset: 0x10 ISP Trigger Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ISPGO |ISP Start Trigger (Write Protect)\r
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished\r
+ * | | |When ISPGO=1, the operation of accessing value from address FMC_BA+0x00 to FMC_BA+0x68 would halt CPU still ISPGO =0\r
+ * | | |If user want to monitor whether ISP finish or not,user can access FMC_MPSTS[0] MPBUSY.\r
+ * | | |0 = ISP operation is finished.\r
+ * | | |1 = ISP is progressed.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * @var FMC_T::ISPSTS\r
+ * Offset: 0x40 ISP Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ISPBUSY |ISP Busy Flag (Read Only)\r
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\r
+ * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).\r
+ * | | |0 = ISP operation is finished.\r
+ * | | |1 = ISP is progressed.\r
+ * |[2] |CBS |Boot Selection of CONFIG (Read Only)\r
+ * | | |This bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.\r
+ * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.\r
+ * | | |0 = LDROM with IAP mode.\r
+ * | | |1 = APROM with IAP mode.\r
+ * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)\r
+ * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened\r
+ * | | |0 = Booting from Boot Loader.\r
+ * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting)\r
+ * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only)\r
+ * | | |This bit is set if flash access cycle auto-tuning function is disabled\r
+ * | | |The auto-tuning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.\r
+ * | | |0 = Flash access cycle auto-tuning is Enabled.\r
+ * | | |1 = Flash access cycle auto-tuning is Disabled.\r
+ * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only)\r
+ * | | |This bit is set if data is mismatched at ISP programming verification\r
+ * | | |This bit is clear by performing ISP flash erase or ISP read CID operation\r
+ * | | |0 = Flash Program is success.\r
+ * | | |1 = Flash Program is fail. Program data is different with data in the flash memory\r
+ * |[6] |ISPFF |ISP Fail Flag (Write Protect)\r
+ * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] if this bit is set.\r
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:\r
+ * | | |(1) APROM writes to itself if APUEN is set to 0.\r
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.\r
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.\r
+ * | | |(4) Page Erase command at LOCK mode with ICE connection\r
+ * | | |(5) Erase or Program command at brown-out detected\r
+ * | | |(6) Destination address is illegal, such as over an available range.\r
+ * | | |(7) Invalid ISP commands\r
+ * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1\r
+ * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1\r
+ * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1\r
+ * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0.\r
+ * | | |(12) Read any content of boot loader with ICE connection\r
+ * | | |(13) The address of block erase and bank erase is not in APROM\r
+ * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command\r
+ * | | |(15) The wrong setting of page erase ISP CMD in XOM\r
+ * | | |(16) Violate XOM setting one time protection\r
+ * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page\r
+ * | | |(18) Mass erase when MERASE (CFG0[13]) is disable\r
+ * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[7] |ALLONE |Flash All-one Verification Flag\r
+ * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete; this bit also can be clear by writing 1\r
+ * | | |0 = All of flash bits are 1 after Run Flash All-One Verification complete.\r
+ * | | |1 = Flash bits are not all 1 after Run Flash All-One Verification complete.\r
+ * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)\r
+ * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}\r
+ * |[24] |INTFLAG |Interrupt Flag\r
+ * | | |0 = ISP is not finish.\r
+ * | | |1 = ISP done or ISPFF set.\r
+ * @var FMC_T::CYCCTL\r
+ * Offset: 0x4C Flash Access Cycle Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect)\r
+ * | | |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1).\r
+ * | | |When auto-tuning function disabled, user needs to check the speed of HCLK and set the cycle >0.\r
+ * | | |0000 = CPU access with zero wait cycle ; Flash access cycle is 1. The HCLK working frequency range is <27MHz; Cache is disabled by hardware.\r
+ * | | |0001 = CPU access with one wait cycle if cache miss; Flash access cycle is 1. The HCLK working frequency range range is<27MHz.\r
+ * | | |0010 = CPU access with two wait cycles if cache miss; Flash access cycle is 2. The optimized HCLK working frequency range is 25~52 MHz.\r
+ * | | |0011 = CPU access with three wait cycles if cache miss; Flash access cycle is 3. The optimized HCLK working frequency range is 49~79MHz.\r
+ * | | |Others = Reserved.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[8] |FADIS |Flash Access Cycle Auto-tuning Disabled Control (Write Protect)\r
+ * | | |Set this bit to disable flash access cycle auto-tuning function\r
+ * | | |0 = Flash access cycle auto-tuning is enabled.\r
+ * | | |1 = Flash access cycle auto-tuning is disabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * @var FMC_T::KPKEY0\r
+ * Offset: 0x50 KPROM KEY0 Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only)\r
+ * | | |Write KPKEY0 data to this register before KEY Comparison operation.\r
+ * @var FMC_T::KPKEY1\r
+ * Offset: 0x54 KPROM KEY1 Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only)\r
+ * | | |Write KPKEY1 data to this register before KEY Comparison operation.\r
+ * @var FMC_T::KPKEY2\r
+ * Offset: 0x58 KPROM KEY2 Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only)\r
+ * | | |Write KPKEY2 data to this register before KEY Comparison operation.\r
+ * @var FMC_T::KPKEYTRG\r
+ * Offset: 0x5C KPROM KEY Comparison Trigger Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection)\r
+ * | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished\r
+ * | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0.\r
+ * | | |0 = KEY comparison operation is finished.\r
+ * | | |1 = KEY comparison is progressed.\r
+ * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.\r
+ * |[1] |TCEN |Timeout Counting Enable (Write Protection)\r
+ * | | |0 = Timeout counting is disabled.\r
+ * | | |1 = Timeout counting is enabled if input key is matched after key comparison finish.\r
+ * | | |10 minutes is at least for timeout, and average is about 20 minutes.\r
+ * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.\r
+ * @var FMC_T::KPKEYSTS\r
+ * Offset: 0x60 KPROM KEY Comparison Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |KEYBUSY |KEY Comparison Busy (Read Only)\r
+ * | | |0 = KEY comparison is finished.\r
+ * | | |1 = KEY comparison is busy.\r
+ * |[1] |KEYLOCK |KEY LOCK Flag\r
+ * | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection\r
+ * | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0\r
+ * | | |This bit also can be set to 1 while\r
+ * | | |l CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or\r
+ * | | |l KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or\r
+ * | | |l KEYENROM is programmed a non-0x5a value or\r
+ * | | |l Timeout event or\r
+ * | | |l FORBID(FMC_KPKEYSTS[3]) is 1\r
+ * | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection.\r
+ * | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection.\r
+ * | | |CONFIG write protect is depended on CFGFLAG\r
+ * |[2] |KEYMATCH |KEY Match Flag (Read Only)\r
+ * | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched\r
+ * | | |This bit is also cleared to 0 while\r
+ * | | |l CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or\r
+ * | | |l Timeout event or\r
+ * | | |l KPROM is erased or\r
+ * | | |l KEYENROM is programmed to a non-0x5a value.\r
+ * | | |l Chip is in power down mode.\r
+ * | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting.\r
+ * | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting.\r
+ * |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only)\r
+ * | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]).\r
+ * | | |0 = KEY comparison is not forbidden.\r
+ * | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger.\r
+ * |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only)\r
+ * | | |This bit is set while the KEYENROM [7:0] is not 0x5a at power-on or reset\r
+ * | | |This bit is cleared to 0 by hardware while KPROM is erased\r
+ * | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0x5a value.\r
+ * | | |0 = Security Key protection is disabled.\r
+ * | | |1 = Security Key protection is enabled.\r
+ * |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only)\r
+ * | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset\r
+ * | | |This bit is cleared to 0 by hardware while KPROM is erased\r
+ * | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0.\r
+ * | | |0 = CONFIG write-protection is disabled.\r
+ * | | |1 = CONFIG write-protection is enabled.\r
+ * |[8] |SBKPBUSY |Secure Boot Key Programming BUSY (Read Only)\r
+ * | | |This bit is set to 1 while secure boot key program function is running\r
+ * | | |This bit is cleared to 0 while secure boot key key program function had been done.\r
+ * | | |0 = Secure boot key program function is done.\r
+ * | | |1 = Secure boot key program function is busy.\r
+ * |[9] |SBKPFLAG |Secure Boot Key Programming Flag (Read Only)\r
+ * | | |This bit is set to 1 while secure boot key program function fails\r
+ * | | |This bit is cleared to 0 while secure boot key had been programmed into flash memory.\r
+ * | | |0 = Secure boot key program function is successful.\r
+ * | | |1 = Secure boot key program function fails.\r
+ * @var FMC_T::KPKEYCNT\r
+ * Offset: 0x64 KPROM KEY-Unmatched Counting Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only)\r
+ * | | |KPKECNT is increased when entry keys is wrong in Security Key protection\r
+ * | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on.\r
+ * |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only)\r
+ * | | |KPKEMAX is the maximum error key entry number at each power-on\r
+ * | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated\r
+ * | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting\r
+ * | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX.\r
+ * @var FMC_T::KPCNT\r
+ * Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only)\r
+ * | | |KPCNT is the power-on counting for error key entry in Security Key protection\r
+ * | | |KPCNT is cleared to 0 if key comparison is matched.\r
+ * |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only)\r
+ * | | |KPMAX is the power-on maximum number for error key entry\r
+ * | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated\r
+ * | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting\r
+ * | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX\r
+ * @var FMC_T::MPDAT0\r
+ * Offset: 0x80 ISP Data0 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ISPDAT0 |ISP Data 0\r
+ * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data\r
+ * @var FMC_T::MPDAT1\r
+ * Offset: 0x84 ISP Data1 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ISPDAT1 |ISP Data 1\r
+ * | | |This register is the second 32-bit data for 64-bit/multi-word programming.\r
+ * @var FMC_T::MPDAT2\r
+ * Offset: 0x88 ISP Data2 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ISPDAT2 |ISP Data 2\r
+ * | | |This register is the third 32-bit data for multi-word programming.\r
+ * @var FMC_T::MPDAT3\r
+ * Offset: 0x8C ISP Data3 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ISPDAT3 |ISP Data 3\r
+ * | | |This register is the fourth 32-bit data for multi-word programming.\r
+ * @var FMC_T::MPSTS\r
+ * Offset: 0xC0 ISP Multi-Program Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only)\r
+ * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\r
+ * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).\r
+ * | | |0 = ISP Multi-Word program operation is finished.\r
+ * | | |1 = ISP Multi-Word program operation is progressed.\r
+ * |[1] |PPGO |ISP Multi-program Status (Read Only)\r
+ * | | |0 = ISP multi-word program operation is not active.\r
+ * | | |1 = ISP multi-word program operation is in progress.\r
+ * |[2] |ISPFF |ISP Fail Flag (Read Only)\r
+ * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]\r
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:\r
+ * | | |(1) APROM writes to itself if APUEN is set to 0.\r
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.\r
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.\r
+ * | | |(4) Page Erase command at LOCK mode with ICE connection\r
+ * | | |(5) Erase or Program command at brown-out detected\r
+ * | | |(6) Destination address is illegal, such as over an available range.\r
+ * | | |(7) Invalid ISP commands\r
+ * |[4] |D0 |ISP DATA 0 Flag (Read Only)\r
+ * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.\r
+ * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.\r
+ * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.\r
+ * |[5] |D1 |ISP DATA 1 Flag (Read Only)\r
+ * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.\r
+ * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.\r
+ * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.\r
+ * |[6] |D2 |ISP DATA 2 Flag (Read Only)\r
+ * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.\r
+ * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.\r
+ * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.\r
+ * |[7] |D3 |ISP DATA 3 Flag (Read Only)\r
+ * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.\r
+ * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.\r
+ * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.\r
+ * @var FMC_T::MPADDR\r
+ * Offset: 0xC4 ISP Multi-Program Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |MPADDR |ISP Multi-word Program Address\r
+ * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\r
+ * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.\r
+ * @var FMC_T::XOMR0STS\r
+ * Offset: 0xD0 XOM Region 0 Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |SIZE |XOM Region 0 Size (Page-aligned)\r
+ * | | |SIZE is the page number of XOM Region 0.\r
+ * |[31:8] |BASE |XOM Region 0 Base Address (Page-aligned)\r
+ * | | |BASE is the base address of XOM Region 0.\r
+ * @var FMC_T::XOMR1STS\r
+ * Offset: 0xD4 XOM Region 1 Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |SIZE |XOM Region 1 Size (Page-aligned)\r
+ * | | |SIZE is the page number of XOM Region 1.\r
+ * |[31:8] |BASE |XOM Region 1 Base Address (Page-aligned)\r
+ * | | |BASE is the base address of XOM Region 1.\r
+ * @var FMC_T::XOMR2STS\r
+ * Offset: 0xD8 XOM Region 2 Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |SIZE |XOM Region 2 Size (Page-aligned)\r
+ * | | |SIZE is the page number of XOM Region 2.\r
+ * |[31:8] |BASE |XOM Region 2 Base Address (Page-aligned)\r
+ * | | |BASE is the base address of XOM Region 2.\r
+ * @var FMC_T::XOMR3STS\r
+ * Offset: 0xDC XOM Region 3 Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |SIZE |XOM Region 3 Size (Page-aligned)\r
+ * | | |SIZE is the page number of XOM Region 3.\r
+ * |[31:8] |BASE |XOM Region 3 Base Address (Page-aligned)\r
+ * | | |BASE is the base address of XOM Region 3.\r
+ * @var FMC_T::XOMSTS\r
+ * Offset: 0xE0 XOM Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |XOMR0ON |XOM Region 0 On\r
+ * | | |XOM Region 0 active status.\r
+ * | | |0 = No active.\r
+ * | | |1 = XOM region 0 is active.\r
+ * |[1] |XOMR1ON |XOM Region 1 On\r
+ * | | |XOM Region 1 active status.\r
+ * | | |0 = No active.\r
+ * | | |1 = XOM region 1 is active.\r
+ * |[2] |XOMR2ON |XOM Region 2 On\r
+ * | | |XOM Region 2 active status.\r
+ * | | |0 = No active.\r
+ * | | |1 = XOM region 2 is active.\r
+ * |[3] |XOMR3ON |XOM Region 3 On\r
+ * | | |XOM Region 3 active status.\r
+ * | | |0 = No active.\r
+ * | | |1 = XOM region 3 is active.\r
+ * |[4] |XOMPEF |XOM Page Erase Function Fail\r
+ * | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.\r
+ * | | |0 = Success.\r
+ * | | |1 = Fail.\r
+ */\r
+ __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */\r
+ __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */\r
+ __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */\r
+ __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */\r
+ __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */\r
+ __I uint32_t RESERVE0[11];\r
+ __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */\r
+ __I uint32_t RESERVE1[2];\r
+ __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */\r
+ __O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */\r
+ __O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */\r
+ __O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */\r
+ __IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */\r
+ __IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */\r
+ __I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */\r
+ __I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */\r
+ __I uint32_t RESERVE2[5];\r
+ __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */\r
+ __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */\r
+ __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */\r
+ __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */\r
+ __I uint32_t RESERVE3[12];\r
+ __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */\r
+ __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */\r
+ __I uint32_t RESERVE4[2];\r
+ __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */\r
+ __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */\r
+ __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */\r
+ __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */\r
+ __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */\r
+\r
+} FMC_T;\r
+\r
+/**\r
+ @addtogroup FMC_CONST FMC Bit Field Definition\r
+ Constant Definitions for FMC Controller\r
+@{ */\r
+\r
+#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */\r
+#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */\r
+\r
+#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */\r
+#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */\r
+\r
+#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */\r
+#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */\r
+\r
+#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */\r
+#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */\r
+\r
+#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */\r
+#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */\r
+\r
+#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */\r
+#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */\r
+\r
+#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */\r
+#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */\r
+\r
+#define FMC_ISPCTL_INTEN_Pos (24) /*!< FMC_T::ISPCTL: INTEN Position */\r
+#define FMC_ISPCTL_INTEN_Msk (0x1ul << FMC_ISPCTL_INTEN_Pos) /*!< FMC_T::ISPCTL: INTEN Mask */\r
+\r
+#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */\r
+#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */\r
+\r
+#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */\r
+#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */\r
+\r
+#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */\r
+#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */\r
+\r
+#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */\r
+#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */\r
+\r
+#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */\r
+#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */\r
+\r
+#define FMC_ISPSTS_CBS_Pos (2) /*!< FMC_T::ISPSTS: CBS Position */\r
+#define FMC_ISPSTS_CBS_Msk (0x1ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */\r
+\r
+#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */\r
+#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */\r
+\r
+#define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */\r
+#define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */\r
+\r
+#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */\r
+#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */\r
+\r
+#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */\r
+#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */\r
+\r
+#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */\r
+#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */\r
+\r
+#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */\r
+#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */\r
+\r
+#define FMC_ISPSTS_INTFLAG_Pos (24) /*!< FMC_T::ISPSTS: INTFLAG Position */\r
+#define FMC_ISPSTS_INTFLAG_Msk (0x1ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Mask */\r
+\r
+#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */\r
+#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */\r
+\r
+#define FMC_CYCCTL_FADIS_Pos (8) /*!< FMC_T::CYCCTL: FADIS Position */\r
+#define FMC_CYCCTL_FADIS_Msk (0x1ul << FMC_CYCCTL_FADIS_Pos) /*!< FMC_T::CYCCTL: FADIS Mask */\r
+\r
+#define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */\r
+#define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */\r
+\r
+#define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */\r
+#define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */\r
+\r
+#define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */\r
+#define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */\r
+\r
+#define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */\r
+#define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */\r
+\r
+#define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */\r
+#define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */\r
+\r
+#define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */\r
+#define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */\r
+\r
+#define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */\r
+#define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */\r
+\r
+#define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */\r
+#define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */\r
+\r
+#define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */\r
+#define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */\r
+\r
+#define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */\r
+#define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */\r
+\r
+#define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */\r
+#define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */\r
+\r
+#define FMC_KPKEYSTS_SBKPBUSY_Pos (8) /*!< FMC_T::KPKEYSTS: SBKPBUSY Position */\r
+#define FMC_KPKEYSTS_SBKPBUSY_Msk (0x1ul << FMC_KPKEYSTS_SBKPBUSY_Pos) /*!< FMC_T::KPKEYSTS: SBKPBUSY Mask */\r
+\r
+#define FMC_KPKEYSTS_SBKPFLAG_Pos (9) /*!< FMC_T::KPKEYSTS: SBKPFLAG Position */\r
+#define FMC_KPKEYSTS_SBKPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SBKPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SBKPFLAG Mask */\r
+\r
+#define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */\r
+#define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */\r
+\r
+#define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */\r
+#define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */\r
+\r
+#define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */\r
+#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */\r
+\r
+#define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */\r
+#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */\r
+\r
+#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */\r
+#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */\r
+\r
+#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */\r
+#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */\r
+\r
+#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */\r
+#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */\r
+\r
+#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */\r
+#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */\r
+\r
+#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */\r
+#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */\r
+\r
+#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */\r
+#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */\r
+\r
+#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */\r
+#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */\r
+\r
+#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */\r
+#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */\r
+\r
+#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */\r
+#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */\r
+\r
+#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */\r
+#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */\r
+\r
+#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */\r
+#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */\r
+\r
+#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */\r
+#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */\r
+\r
+#define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */\r
+#define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */\r
+\r
+#define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */\r
+#define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */\r
+\r
+#define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */\r
+#define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */\r
+\r
+#define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */\r
+#define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */\r
+\r
+#define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */\r
+#define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */\r
+\r
+#define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */\r
+#define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOMR2STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */\r
+\r
+#define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */\r
+#define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */\r
+\r
+#define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */\r
+#define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */\r
+\r
+#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */\r
+#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */\r
+\r
+#define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */\r
+#define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */\r
+\r
+#define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */\r
+#define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */\r
+\r
+#define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */\r
+#define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */\r
+\r
+#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */\r
+#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */\r
+\r
+/**@}*/ /* FMC_CONST */\r
+/**@}*/ /* end of FMC register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __FMC_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file gpio_reg.h\r
+ * @version V1.00\r
+ * @brief GPIO register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __GPIO_REG_H__\r
+#define __GPIO_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- General Purpose Input/Output Controller -------------------------*/\r
+/**\r
+ @addtogroup GPIO General Purpose Input/Output Controller(GPIO)\r
+ Memory Mapped Structure for GPIO Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var GPIO_T::MODE\r
+ * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 PA-H I/O Mode Control\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2n+1:2n]|MODEn |Port A-H I/O Pin[n] Mode Control\r
+ * | | |Determine each I/O mode of Px.n pins.\r
+ * | | |00 = Px.n is in Input mode.\r
+ * | | |01 = Px.n is in Push-pull Output mode.\r
+ * | | |10 = Px.n is in Open-drain Output mode.\r
+ * | | |11 = Px.n is in Quasi-bidirectional mode.\r
+ * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).\r
+ * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.\r
+ * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\r
+ * | | |Note2:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var GPIO_T::DINOFF\r
+ * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 PA-H Digital Input Path Disable Control\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[n+16] |DINOFFn |Port A-H Pin[n] Digital Input Path Disable Control\r
+ * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.\r
+ * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\r
+ * | | |0 = Px.n digital input path Enabled.\r
+ * | | |1 = Px.n digital input path Disabled (digital input tied to low).\r
+ * | | |Note:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var GPIO_T::DOUT\r
+ * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 PA-H Data Output Value\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[n] |DOUTn |Port A-H Pin[n] Output Value\r
+ * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\r
+ * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\r
+ * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.\r
+ * | | |Note:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var GPIO_T::DATMSK\r
+ * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC PA-H Data Output Write Mask\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask\r
+ * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.\r
+ * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.\r
+ * | | |If the write signal is masked, writing data to the protect bit is ignored.\r
+ * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.\r
+ * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.\r
+ * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\r
+ * | | |Note2:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var GPIO_T::PIN\r
+ * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 PA-H Pin Value\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[n] |PINn |Port A-H Pin[n] Pin Value\r
+ * | | |Each bit of the register reflects the actual status of the respective Px.n pin.\r
+ * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\r
+ * | | |Note:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var GPIO_T::DBEN\r
+ * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 PA-H De-Bounce Enable Control\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[n] |DBENn |Port A-H Pin[n] Input Signal De-bounce Enable Bit\r
+ * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.\r
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.\r
+ * | | |The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).\r
+ * | | |0 = Px.n de-bounce function Disabled.\r
+ * | | |1 = Px.n de-bounce function Enabled.\r
+ * | | |The de-bounce function is valid only for edge triggered interrupt.\r
+ * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\r
+ * | | |Note:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var GPIO_T::INTTYPE\r
+ * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 PA-H Interrupt Trigger Type Control\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\r
+ * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.\r
+ * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.\r
+ * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\r
+ * | | |0 = Edge trigger interrupt.\r
+ * | | |1 = Level trigger interrupt.\r
+ * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).\r
+ * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\r
+ * | | |The de-bounce function is valid only for edge triggered interrupt.\r
+ * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\r
+ * | | |Note:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var GPIO_T::INTEN\r
+ * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC PA-H Interrupt Enable Control\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\r
+ * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.\r
+ * | | |Set bit to 1 also enable the pin wake-up function.\r
+ * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :\r
+ * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\r
+ * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\r
+ * | | |0 = Px.n level low or high to low interrupt Disabled.\r
+ * | | |1 = Px.n level low or high to low interrupt Enabled.\r
+ * | | |Note:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * |[n+16] |RHIENn |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\r
+ * | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.\r
+ * | | |Set bit to 1 also enable the pin wake-up function.\r
+ * | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\r
+ * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\r
+ * | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\r
+ * | | |0 = Px.n level high or low to high interrupt Disabled.\r
+ * | | |1 = Px.n level high or low to high interrupt Enabled.\r
+ * | | |Note:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var GPIO_T::INTSRC\r
+ * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 PA-H Interrupt Source Flag\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[n] |INTSRCn |Port A-H Pin[n] Interrupt Source Flag\r
+ * | | |Write Operation :\r
+ * | | |0 = No action.\r
+ * | | |1 = Clear the corresponding pending interrupt.\r
+ * | | |Read Operation :\r
+ * | | |0 = No interrupt at Px.n.\r
+ * | | |1 = Px.n generates an interrupt.\r
+ * | | |Note:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var GPIO_T::SMTEN\r
+ * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 PA-H Input Schmitt Trigger Enable\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[n] |SMTENn |Port A-H Pin[n] Input Schmitt Trigger Enable Bit\r
+ * | | |0 = Px.n input Schmitt trigger function Disabled.\r
+ * | | |1 = Px.n input Schmitt trigger function Enabled.\r
+ * | | |Note:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var GPIO_T::SLEWCTL\r
+ * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 PA-H High Slew Rate Control\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2n+1:2n]|HSRENn |Port A-H Pin[n] High Slew Rate Control\r
+ * | | |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V).\r
+ * | | |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V).\r
+ * | | |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V.\r
+ * | | |11 = Reserved.\r
+ * | | |Note:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var GPIO_T::PUSEL\r
+ * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 PA-H Pull-up and Pull-down Selection Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2n+1:2n]|PUSELn |Port A-H Pin[n] Pull-up and Pull-down Enable Register\r
+ * | | |Determine each I/O Pull-up/pull-down of Px.n pins.\r
+ * | | |00 = Px.n pull-up and pull-down disable.\r
+ * | | |01 = Px.n pull-up enable.\r
+ * | | |10 = Px.n pull-down enable.\r
+ * | | |11 = Px.n pull-up and pull-down disable.\r
+ * | | |Note1:\r
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.\r
+ * | | |The independent pull-up control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state and open-drain mode.\r
+ * | | |The independent pull-down control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state mode.\r
+ * | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode.\r
+ * | | |Note:2\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var GPIO_T::DBCTL\r
+ * Offset: 0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4 PA-H Interrupt De-bounce Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |DBCLKSEL |De-bounce Sampling Cycle Selection\r
+ * | | |0000 = Sample interrupt input once per 1 clocks.\r
+ * | | |0001 = Sample interrupt input once per 2 clocks.\r
+ * | | |0010 = Sample interrupt input once per 4 clocks.\r
+ * | | |0011 = Sample interrupt input once per 8 clocks.\r
+ * | | |0100 = Sample interrupt input once per 16 clocks.\r
+ * | | |0101 = Sample interrupt input once per 32 clocks.\r
+ * | | |0110 = Sample interrupt input once per 64 clocks.\r
+ * | | |0111 = Sample interrupt input once per 128 clocks.\r
+ * | | |1000 = Sample interrupt input once per 256 clocks.\r
+ * | | |1001 = Sample interrupt input once per 2*256 clocks.\r
+ * | | |1010 = Sample interrupt input once per 4*256 clocks.\r
+ * | | |1011 = Sample interrupt input once per 8*256 clocks.\r
+ * | | |1100 = Sample interrupt input once per 16*256 clocks.\r
+ * | | |1101 = Sample interrupt input once per 32*256 clocks.\r
+ * | | |1110 = Sample interrupt input once per 64*256 clocks.\r
+ * | | |1111 = Sample interrupt input once per 128*256 clocks.\r
+ * |[4] |DBCLKSRC |De-bounce Counter Clock Source Selection\r
+ * | | |0 = De-bounce counter clock source is the HCLK.\r
+ * | | |1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).\r
+ * |[5] |ICLKON |Interrupt Clock on Mode\r
+ * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.\r
+ * | | |1 = All I/O pins edge detection circuit is always active after reset.\r
+ * | | |Note: It is recommended to disable this bit to save system power if no special application concern.\r
+ */\r
+\r
+\r
+ __IO uint32_t MODE; /*!< [0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0] Port A-H I/O Mode Control */\r
+ __IO uint32_t DINOFF; /*!< [0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4] Port A-H Digital Input Path Disable Control */\r
+ __IO uint32_t DOUT; /*!< [0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8] Port A-H Data Output Value */\r
+ __IO uint32_t DATMSK; /*!< [0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC] Port A-H Data Output Write Mask */\r
+ __I uint32_t PIN; /*!< [0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0] Port A-H Pin Value */\r
+ __IO uint32_t DBEN; /*!< [0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4] Port A-H De-Bounce Enable Control */\r
+ __IO uint32_t INTTYPE; /*!< [0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8] Port A-H Interrupt Trigger Type Control */\r
+ __IO uint32_t INTEN; /*!< [0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC] Port A-H Interrupt Enable Control */\r
+ __IO uint32_t INTSRC; /*!< [0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0] Port A-H Interrupt Source Flag */\r
+ __IO uint32_t SMTEN; /*!< [0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4] Port A-H Input Schmitt Trigger Enable */\r
+ __IO uint32_t SLEWCTL; /*!< [0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8] Port A-H High Slew Rate Control */\r
+ __I uint32_t RESERVE0[1];\r
+ __IO uint32_t PUSEL; /*!< [0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0] Port A-H Pull-up and Pull-down Selection Register */\r
+ __IO uint32_t DBCTL; /*!< [0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4] Port A-H Interrupt De-bounce Control */\r
+\r
+} GPIO_T;\r
+\r
+\r
+\r
+/**\r
+ @addtogroup GPIO_CONST GPIO Bit Field Definition\r
+ Constant Definitions for GPIO Controller\r
+@{ */\r
+\r
+#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */\r
+#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */\r
+\r
+#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */\r
+#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */\r
+\r
+#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */\r
+#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */\r
+\r
+#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */\r
+#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */\r
+\r
+#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */\r
+#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */\r
+\r
+#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */\r
+#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */\r
+\r
+#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */\r
+#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */\r
+\r
+#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */\r
+#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */\r
+\r
+#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */\r
+#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */\r
+\r
+#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */\r
+#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */\r
+\r
+#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */\r
+#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */\r
+\r
+#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */\r
+#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */\r
+\r
+#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */\r
+#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */\r
+\r
+#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */\r
+#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */\r
+\r
+#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */\r
+#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */\r
+\r
+#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */\r
+#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */\r
+#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */\r
+#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */\r
+#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */\r
+#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */\r
+#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */\r
+#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */\r
+#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */\r
+#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */\r
+#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */\r
+#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */\r
+#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */\r
+#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */\r
+#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */\r
+#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */\r
+#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */\r
+\r
+#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */\r
+#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */\r
+\r
+#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */\r
+#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */\r
+\r
+#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */\r
+#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */\r
+\r
+#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */\r
+#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */\r
+\r
+#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */\r
+#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */\r
+\r
+#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */\r
+#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */\r
+\r
+#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */\r
+#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */\r
+\r
+#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */\r
+#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */\r
+\r
+#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */\r
+#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */\r
+\r
+#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */\r
+#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */\r
+\r
+#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */\r
+#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */\r
+\r
+#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */\r
+#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */\r
+\r
+#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */\r
+#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */\r
+\r
+#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */\r
+#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */\r
+\r
+#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */\r
+#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */\r
+\r
+#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */\r
+#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */\r
+\r
+#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */\r
+#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */\r
+#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */\r
+#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */\r
+#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */\r
+#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */\r
+#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */\r
+#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */\r
+#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */\r
+#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */\r
+#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */\r
+#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */\r
+#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */\r
+#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */\r
+#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */\r
+#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */\r
+#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */\r
+\r
+#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */\r
+#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */\r
+\r
+#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */\r
+#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */\r
+\r
+#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */\r
+#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */\r
+\r
+#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */\r
+#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */\r
+\r
+#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */\r
+#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */\r
+\r
+#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */\r
+#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */\r
+\r
+#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */\r
+#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */\r
+\r
+#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */\r
+#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */\r
+\r
+#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */\r
+#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */\r
+\r
+#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */\r
+#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */\r
+\r
+#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */\r
+#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */\r
+\r
+#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */\r
+#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */\r
+\r
+#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */\r
+#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */\r
+\r
+#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */\r
+#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */\r
+\r
+#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */\r
+#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */\r
+\r
+#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */\r
+#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */\r
+\r
+#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */\r
+#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */\r
+\r
+#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */\r
+#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */\r
+\r
+#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */\r
+#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */\r
+\r
+#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */\r
+#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */\r
+\r
+#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */\r
+#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */\r
+\r
+#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */\r
+#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */\r
+\r
+#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */\r
+#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */\r
+\r
+#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */\r
+#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */\r
+\r
+#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */\r
+#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */\r
+\r
+#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */\r
+#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */\r
+\r
+#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */\r
+#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */\r
+\r
+#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */\r
+#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */\r
+\r
+#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */\r
+#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */\r
+\r
+#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */\r
+#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */\r
+\r
+#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */\r
+#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */\r
+\r
+#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */\r
+#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */\r
+\r
+#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */\r
+#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */\r
+#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */\r
+#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */\r
+#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */\r
+#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */\r
+#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */\r
+#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */\r
+#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */\r
+#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */\r
+#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */\r
+#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */\r
+#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */\r
+#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */\r
+#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */\r
+#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */\r
+#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */\r
+\r
+#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */\r
+#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */\r
+#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */\r
+#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */\r
+#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */\r
+#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */\r
+#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */\r
+#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */\r
+#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */\r
+#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */\r
+#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */\r
+#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */\r
+#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */\r
+#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */\r
+#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */\r
+#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */\r
+#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */\r
+\r
+#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */\r
+#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */\r
+#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */\r
+#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */\r
+#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */\r
+#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */\r
+#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */\r
+#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */\r
+#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */\r
+#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */\r
+#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */\r
+#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */\r
+#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */\r
+#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */\r
+#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */\r
+#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */\r
+#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */\r
+\r
+#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */\r
+#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */\r
+#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */\r
+#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */\r
+#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */\r
+#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */\r
+#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */\r
+#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */\r
+#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */\r
+#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */\r
+#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */\r
+#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */\r
+#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */\r
+#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */\r
+#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */\r
+#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */\r
+#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */\r
+\r
+#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */\r
+#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */\r
+#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */\r
+#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */\r
+#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */\r
+#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */\r
+#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */\r
+#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */\r
+#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */\r
+#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */\r
+#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */\r
+#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */\r
+#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */\r
+#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */\r
+#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */\r
+#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */\r
+#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */\r
+\r
+#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */\r
+#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */\r
+#define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO_T::SLEWCTL: HSREN1 Position */\r
+#define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN2 Position */\r
+#define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO_T::SLEWCTL: HSREN3 Position */\r
+#define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN4 Position */\r
+#define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO_T::SLEWCTL: HSREN5 Position */\r
+#define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN6 Position */\r
+#define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO_T::SLEWCTL: HSREN7 Position */\r
+#define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN8 Position */\r
+#define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO_T::SLEWCTL: HSREN9 Position */\r
+#define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN10 Position */\r
+#define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO_T::SLEWCTL: HSREN11 Position */\r
+#define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN12 Position */\r
+#define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO_T::SLEWCTL: HSREN13 Position */\r
+#define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN14 Position */\r
+#define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */\r
+\r
+#define GPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO_T::SLEWCTL: HSREN15 Position */\r
+#define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */\r
+#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */\r
+#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */\r
+#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */\r
+#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */\r
+#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */\r
+#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */\r
+#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */\r
+#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */\r
+#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */\r
+#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */\r
+#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */\r
+#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */\r
+#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */\r
+#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */\r
+#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */\r
+\r
+#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */\r
+#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */\r
+\r
+#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */\r
+#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */\r
+\r
+#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */\r
+#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */\r
+\r
+#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */\r
+#define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */\r
+\r
+\r
+/**@}*/ /* GPIO_CONST */\r
+/**@}*/ /* end of GPIO register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __GPIO_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file hdiv_reg.h\r
+ * @version V1.00\r
+ * @brief HDIV register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __HDIV_REG_H__\r
+#define __HDIV_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Hardware Divider --------------------------------*/\r
+/**\r
+ @addtogroup HDIV Hardware Divider(HDIV)\r
+ Memory Mapped Structure for HDIV Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var HDIV_T::DIVIDEND\r
+ * Offset: 0x00 Dividend Source Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DIVIDEND |Dividend Source\r
+ * | | |This register is given the dividend of divider before calculation starting.\r
+ * @var HDIV_T::DIVISOR\r
+ * Offset: 0x04 Divisor Source Resister\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |DIVISOR |Divisor Source\r
+ * | | |This register is given the divisor of divider before calculation starts.\r
+ * | | |Note: When this register is written, hardware divider will start calculate.\r
+ * @var HDIV_T::DIVQUO\r
+ * Offset: 0x08 Quotient Result Resister\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |QUOTIENT |Quotient Result\r
+ * | | |This register holds the quotient result of divider after calculation complete.\r
+ * @var HDIV_T::DIVREM\r
+ * Offset: 0x0C Remainder Result Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |REMAINDER |Remainder Result\r
+ * | | |The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete.\r
+ * | | |The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer.\r
+ * | | |This register holds the remainder result of divider after calculation complete.\r
+ * @var HDIV_T::DIVSTS\r
+ * Offset: 0x10 Divider Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |FINISH |Division Finish Flag\r
+ * | | |0 = Under Calculation.\r
+ * | | |1 = Calculation finished.\r
+ * | | |The flag will become low when the divider is in calculation.\r
+ * | | |The flag will go back to high once the calculation finished.\r
+ * |[1] |DIV0 |Divisor Zero Warning\r
+ * | | |0 = The divisor is not 0.\r
+ * | | |1 = The divisor is 0.\r
+ * | | |Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written\r
+ * | | |This register is read only.\r
+ */\r
+ __IO uint32_t DIVIDEND; /*!< [0x0000] Dividend Source Register */\r
+ __IO uint32_t DIVISOR; /*!< [0x0004] Divisor Source Resister */\r
+ __IO uint32_t DIVQUO; /*!< [0x0008] Quotient Result Resister */\r
+ __IO uint32_t DIVREM; /*!< [0x000c] Remainder Result Register */\r
+ __I uint32_t DIVSTS; /*!< [0x0010] Divider Status Register */\r
+\r
+} HDIV_T;\r
+\r
+/**\r
+ @addtogroup HDIV_CONST HDIV Bit Field Definition\r
+ Constant Definitions for HDIV Controller\r
+@{ */\r
+\r
+#define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */\r
+#define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */\r
+\r
+#define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */\r
+#define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */\r
+\r
+#define HDIV_DIVQUO_QUOTIENT_Pos (0) /*!< HDIV_T::DIVQUO: QUOTIENT Position */\r
+#define HDIV_DIVQUO_QUOTIENT_Msk (0xfffffffful << HDIV_DIVQUO_QUOTIENT_Pos) /*!< HDIV_T::DIVQUO: QUOTIENT Mask */\r
+\r
+#define HDIV_DIVREM_REMAINDER_Pos (0) /*!< HDIV_T::DIVREM: REMAINDER Position */\r
+#define HDIV_DIVREM_REMAINDER_Msk (0xfffffffful << HDIV_DIVREM_REMAINDER_Pos) /*!< HDIV_T::DIVREM: REMAINDER Mask */\r
+\r
+#define HDIV_DIVSTS_FINISH_Pos (0) /*!< HDIV_T::DIVSTS: FINISH Position */\r
+#define HDIV_DIVSTS_FINISH_Msk (0x1ul << HDIV_DIVSTS_FINISH_Pos) /*!< HDIV_T::DIVSTS: FINISH Mask */\r
+\r
+#define HDIV_DIVSTS_DIV0_Pos (1) /*!< HDIV_T::DIVSTS: DIV0 Position */\r
+#define HDIV_DIVSTS_DIV0_Msk (0x1ul << HDIV_DIVSTS_DIV0_Pos) /*!< HDIV_T::DIVSTS: DIV0 Mask */\r
+\r
+/**@}*/ /* HDIV_CONST */\r
+/**@}*/ /* end of HDIV register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __HDIV_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file i2c_reg.h\r
+ * @version V1.00\r
+ * @brief I2C register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __I2C_REG_H__\r
+#define __I2C_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Inter-IC Bus Controller -------------------------*/\r
+/**\r
+ @addtogroup I2C Inter-IC Bus Controller(I2C)\r
+ Memory Mapped Structure for I2C Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var I2C_T::CTL0\r
+ * Offset: 0x00 I2C Control Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2] |AA |Assert Acknowledge Control\r
+ * | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter\r
+ * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line\r
+ * |[3] |SI |I2C Interrupt Flag\r
+ * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware\r
+ * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested\r
+ * | | |SI must be cleared by software\r
+ * | | |Clear SI by writing 1 to this bit.\r
+ * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.\r
+ * |[4] |STO |I2C STOP Control\r
+ * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected\r
+ * | | |This bit will be cleared by hardware automatically.\r
+ * |[5] |STA |I2C START Control\r
+ * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.\r
+ * |[6] |I2CEN |I2C Controller Enable Bit\r
+ * | | |Set to enable I2C serial function controller\r
+ * | | |When I2CEN=1 the I2C serial function enable\r
+ * | | |The multi-function pin function must set to SDA, and SCL of I2C function first.\r
+ * | | |0 = I2C controller Disabled.\r
+ * | | |1 = I2C controller Enabled.\r
+ * |[7] |INTEN |Enable Interrupt\r
+ * | | |0 = I2C interrupt Disabled.\r
+ * | | |1 = I2C interrupt Enabled.\r
+ * @var I2C_T::ADDR0\r
+ * Offset: 0x04 I2C Slave Address Register0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |GC |General Call Function\r
+ * | | |0 = General Call Function Disabled.\r
+ * | | |1 = General Call Function Enabled.\r
+ * |[10:1] |ADDR |I2C Address\r
+ * | | |The content of this register is irrelevant when I2C is in Master mode\r
+ * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address\r
+ * | | |The I2C hardware will react if either of the address is matched.\r
+ * @var I2C_T::DAT\r
+ * Offset: 0x08 I2C Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |DAT |I2C Data\r
+ * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.\r
+ * @var I2C_T::STATUS0\r
+ * Offset: 0x0C I2C Status Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |STATUS |I2C Status\r
+ * | | |The three least significant bits are always 0\r
+ * | | |The five most significant bits contain the status code\r
+ * | | |There are 28 possible status codes\r
+ * | | |When the content of I2C_STATUS0 is F8H, no serial interrupt is requested\r
+ * | | |Others I2C_STATUS0 values correspond to defined I2C states\r
+ * | | |When each of these states is entered, a status interrupt is requested (SI = 1)\r
+ * | | |A valid status code is present in I2C_STATUS0 one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software\r
+ * | | |In addition, states 00H stands for a Bus Error\r
+ * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame\r
+ * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.\r
+ * @var I2C_T::CLKDIV\r
+ * Offset: 0x10 I2C Clock Divided Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[9:0] |DIVIDER |I2C Clock Divided\r
+ * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).\r
+ * | | |Note: The minimum value of I2C_CLKDIV is 4.\r
+ * @var I2C_T::TOCTL\r
+ * Offset: 0x14 I2C Time-out Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |TOIF |Time-out Flag\r
+ * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\r
+ * | | |Note: Software can write 1 to clear this bit.\r
+ * |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4\r
+ * | | |When Enabled, The time-out period is extend 4 times.\r
+ * | | |0 = Time-out period is extend 4 times Disabled.\r
+ * | | |1 = Time-out period is extend 4 times Enabled.\r
+ * |[2] |TOCEN |Time-out Counter Enable Bit\r
+ * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear\r
+ * | | |Setting flag SI to u20181' will reset counter and re-start up counting after SI is cleared.\r
+ * | | |0 = Time-out counter Disabled.\r
+ * | | |1 = Time-out counter Enabled.\r
+ * @var I2C_T::ADDR1\r
+ * Offset: 0x18 I2C Slave Address Register1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |GC |General Call Function\r
+ * | | |0 = General Call Function Disabled.\r
+ * | | |1 = General Call Function Enabled.\r
+ * |[10:1] |ADDR |I2C Address\r
+ * | | |The content of this register is irrelevant when I2C is in Master mode\r
+ * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address\r
+ * | | |The I2C hardware will react if either of the address is matched.\r
+ * @var I2C_T::ADDR2\r
+ * Offset: 0x1C I2C Slave Address Register2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |GC |General Call Function\r
+ * | | |0 = General Call Function Disabled.\r
+ * | | |1 = General Call Function Enabled.\r
+ * |[10:1] |ADDR |I2C Address\r
+ * | | |The content of this register is irrelevant when I2C is in Master mode\r
+ * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address\r
+ * | | |The I2C hardware will react if either of the address is matched.\r
+ * @var I2C_T::ADDR3\r
+ * Offset: 0x20 I2C Slave Address Register3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |GC |General Call Function\r
+ * | | |0 = General Call Function Disabled.\r
+ * | | |1 = General Call Function Enabled.\r
+ * |[10:1] |ADDR |I2C Address\r
+ * | | |The content of this register is irrelevant when I2C is in Master mode\r
+ * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address\r
+ * | | |The I2C hardware will react if either of the address is matched.\r
+ * @var I2C_T::ADDRMSK0\r
+ * Offset: 0x24 I2C Slave Address Mask Register0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[10:1] |ADDRMSK |I2C Address Mask\r
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).\r
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).\r
+ * | | |I2C bus controllers support multiple address recognition with four address mask register\r
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care\r
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\r
+ * | | |Note: The wake-up function can not use address mask.\r
+ * @var I2C_T::ADDRMSK1\r
+ * Offset: 0x28 I2C Slave Address Mask Register1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[10:1] |ADDRMSK |I2C Address Mask\r
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).\r
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).\r
+ * | | |I2C bus controllers support multiple address recognition with four address mask register\r
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care\r
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\r
+ * | | |Note: The wake-up function can not use address mask.\r
+ * @var I2C_T::ADDRMSK2\r
+ * Offset: 0x2C I2C Slave Address Mask Register2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[10:1] |ADDRMSK |I2C Address Mask\r
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).\r
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).\r
+ * | | |I2C bus controllers support multiple address recognition with four address mask register\r
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care\r
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\r
+ * | | |Note: The wake-up function can not use address mask.\r
+ * @var I2C_T::ADDRMSK3\r
+ * Offset: 0x30 I2C Slave Address Mask Register3\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[10:1] |ADDRMSK |I2C Address Mask\r
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).\r
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).\r
+ * | | |I2C bus controllers support multiple address recognition with four address mask register\r
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care\r
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\r
+ * | | |Note: The wake-up function can not use address mask.\r
+ * @var I2C_T::WKCTL\r
+ * Offset: 0x3C I2C Wake-up Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKEN |I2C Wake-up Enable Bit\r
+ * | | |0 = I2C wake-up function Disabled.\r
+ * | | |1= I2C wake-up function Enabled.\r
+ * |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit\r
+ * | | |0 = I2C don't hold bus after wake-up disable.\r
+ * | | |1= I2C don't hold bus after wake-up enable.\r
+ * | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received\r
+ * | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.\r
+ * @var I2C_T::WKSTS\r
+ * Offset: 0x40 I2C Wake-up Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKIF |I2C Wake-up Flag\r
+ * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1\r
+ * | | |Software can write 1 to clear this bit.\r
+ * |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done\r
+ * | | |0 = The ACK bit cycle of address match frame isn't done.\r
+ * | | |1 = The ACK bit cycle of address match frame is done in power-down.\r
+ * | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit.\r
+ * |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame\r
+ * | | |0 = Write command be record on the address match wakeup frame.\r
+ * | | |1 = Read command be record on the address match wakeup frame.\r
+ * | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit.\r
+ * @var I2C_T::CTL1\r
+ * Offset: 0x44 I2C Control Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |TXPDMAEN |PDMA Transmit Channel Available\r
+ * | | |0 = Transmit PDMA function disable.\r
+ * | | |1 = Transmit PDMA function enable.\r
+ * |[1] |RXPDMAEN |PDMA Receive Channel Available\r
+ * | | |0 = Receive PDMA function disable.\r
+ * | | |1 = Receive PDMA function enable.\r
+ * |[2] |PDMARST |PDMA Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the I2C request to PDMA. This bit will be cleared to 0 automatically.\r
+ * |[8] |PDMASTR |PDMA Stretch Bit\r
+ * | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX)\r
+ * | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared\r
+ * | | |(only master TX)\r
+ * |[9] |ADDR10EN |Address 10-bit Function Enable\r
+ * | | |0 = Address match 10-bit function is disabled.\r
+ * | | |1 = Address match 10-bit function is enabled.\r
+ * @var I2C_T::STATUS1\r
+ * Offset: 0x48 I2C Status Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ADMAT0 |I2C Address 0 Match Status Register\r
+ * | | |When address 0 is matched, hardware will inform which address used\r
+ * | | |This bit will set to 1, and software can write 1 to clear this bit.\r
+ * |[1] |ADMAT1 |I2C Address 1 Match Status Register\r
+ * | | |When address 1 is matched, hardware will inform which address used\r
+ * | | |This bit will set to 1, and software can write 1 to clear this bit.\r
+ * |[2] |ADMAT2 |I2C Address 2 Match Status Register\r
+ * | | |When address 2 is matched, hardware will inform which address used\r
+ * | | |This bit will set to 1, and software can write 1 to clear this bit.\r
+ * |[3] |ADMAT3 |I2C Address 3 Match Status Register\r
+ * | | |When address 3 is matched, hardware will inform which address used\r
+ * | | |This bit will set to 1, and software can write 1 to clear this bit.\r
+ * |[8] |ONBUSY |On Bus Busy\r
+ * | | |Indicates that a communication is in progress on the bus\r
+ * | | |It is set by hardware when a START condition is detected\r
+ * | | |It is cleared by hardware when a STOP condition is detected.\r
+ * | | |0 = The bus is IDLE (both SCLK and SDA High).\r
+ * | | |1 = The bus is busy.\r
+ * | | |Note:This bit is read only.\r
+ * @var I2C_T::TMCTL\r
+ * Offset: 0x4C I2C Timing Configure Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[8:0] |STCTL |Setup Time Configure Control Register\r
+ * | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\r
+ * | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK.\r
+ * | | |Note: Setup time setting should not make SCL output less than three PCLKs.\r
+ * |[24:16] |HTCTL |Hold Time Configure Control Register\r
+ * | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.\r
+ * | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK.\r
+ * @var I2C_T::BUSCTL\r
+ * Offset: 0x50 I2C Bus Management Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ACKMEN |Acknowledge Control by Manual\r
+ * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.\r
+ * | | |0 = Slave byte control Disabled.\r
+ * | | |1 = Slave byte control Enabled\r
+ * | | |The 9th bit can response the ACK or NACK according the received data by user\r
+ * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.\r
+ * | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.\r
+ * |[1] |PECEN |Packet Error Checking Calculation Enable Bit\r
+ * | | |0 = Packet Error Checking Calculation Disabled.\r
+ * | | |1 = Packet Error Checking Calculation Enabled.\r
+ * | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation.\r
+ * |[2] |BMDEN |Bus Management Device Default Address Enable Bit\r
+ * | | |0 = Device default address Disable\r
+ * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed\r
+ * | | |1 = Device default address Enabled\r
+ * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.\r
+ * |[3] |BMHEN |Bus Management Host Enable Bit\r
+ * | | |0 = Host function Disabled.\r
+ * | | |1 = Host function Enabled.\r
+ * |[4] |ALERTEN |Bus Management Alert Enable Bit\r
+ * | | |Device Mode (BMHEN =0).\r
+ * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.\r
+ * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.\r
+ * | | |Host Mode (BMHEN =1).\r
+ * | | |0 = BM_ALERT pin not supported.\r
+ * | | |1 = BM_ALERT pin supported.\r
+ * |[5] |SCTLOSTS |Suspend/Control Data Output Status\r
+ * | | |0 = The output of SUSCON pin is low.\r
+ * | | |1 = The output of SUSCON pin is high.\r
+ * |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit\r
+ * | | |0 = The SUSCON pin in input.\r
+ * | | |1 = The output enable is active on the SUSCON pin.\r
+ * |[7] |BUSEN |BUS Enable Bit\r
+ * | | |0 = The system management function is Disabled.\r
+ * | | |1 = The system management function is Enable.\r
+ * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.\r
+ * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception\r
+ * | | |0 = No PEC transfer.\r
+ * | | |1 = PEC transmission is requested.\r
+ * | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0.\r
+ * |[9] |TIDLE |Timer Check in Idle State\r
+ * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle\r
+ * | | |This bit is used to define which condition is enabled.\r
+ * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active.\r
+ * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.\r
+ * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.\r
+ * |[10] |PECCLR |PEC Clear at Repeat Start\r
+ * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected\r
+ * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.\r
+ * | | |0 = The PEC calculation is cleared by Repeat Start function is Disabled.\r
+ * | | |1 = The PEC calculation is cleared by Repeat Start function is Enabled.\r
+ * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt\r
+ * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.\r
+ * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.\r
+ * |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit\r
+ * | | |0 = Indicates the byte count done interrupt is Disabled.\r
+ * | | |1 = Indicates the byte count done interrupt is Enabled.\r
+ * | | |Note: This bit is used in PECEN =1.\r
+ * |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit\r
+ * | | |0 = Indicates the PEC transfer done interrupt is Disabled.\r
+ * | | |1 = Indicates the PEC transfer done interrupt is Enabled.\r
+ * | | |Note: This bit is used in PECEN =1.\r
+ * @var I2C_T::BUSTCTL\r
+ * Offset: 0x54 I2C Bus Management Timer Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BUSTOEN |Bus Time Out Enable Bit\r
+ * | | |0 = Indicates the bus clock low time-out detection is Disabled.\r
+ * | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1)\r
+ * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit\r
+ * | | |0 = Indicates the cumulative clock low time-out detection is Disabled.\r
+ * | | |1 = Indicates the cumulative clock low time-out detection is Enabled.\r
+ * | | |For Master, it calculates the period from START to ACK\r
+ * | | |For Slave, it calculates the period from START to STOP\r
+ * |[2] |BUSTOIEN |Time-out Interrupt Enable Bit\r
+ * | | |BUSY =1.\r
+ * | | |0 = Indicates the SCLK low time-out interrupt is Disabled.\r
+ * | | |1 = Indicates the SCLK low time-out interrupt is Enabled.\r
+ * | | |BUSY =0.\r
+ * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled.\r
+ * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled.\r
+ * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit\r
+ * | | |0 = Indicates the clock time out interrupt is Disabled.\r
+ * | | |1 = Indicates the clock time out interrupt is Enabled.\r
+ * |[4] |TORSTEN |Time Out Reset Enable Bit\r
+ * | | |0 = Indicates the I2C state machine reset is Disable.\r
+ * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)\r
+ * @var I2C_T::BUSSTS\r
+ * Offset: 0x58 I2C Bus Management Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BUSY |Bus Busy\r
+ * | | |Indicates that a communication is in progress on the bus\r
+ * | | |It is set by hardware when a START condition is detected\r
+ * | | |It is cleared by hardware when a STOP condition is detected\r
+ * | | |0 = The bus is IDLE (both SCLK and SDA High).\r
+ * | | |1 = The bus is busy.\r
+ * |[1] |BCDONE |Byte Count Transmission/Receive Done\r
+ * | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set.\r
+ * | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set.\r
+ * | | |Note: Software can write 1 to clear this bit.\r
+ * |[2] |PECERR |PEC Error in Reception\r
+ * | | |0 = Indicates the PEC value equal the received PEC data packet.\r
+ * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet.\r
+ * | | |Note: Software can write 1 to clear this bit.\r
+ * |[3] |ALERT |SMBus Alert Status\r
+ * | | |Device Mode (BMHEN =0).\r
+ * | | |0 = Indicates SMBALERT pin state is low.\r
+ * | | |1 = Indicates SMBALERT pin state is high.\r
+ * | | |Host Mode (BMHEN =1).\r
+ * | | |0 = No SMBALERT event.\r
+ * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.\r
+ * | | |Note: 1\r
+ * | | |The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system\r
+ * | | |2\r
+ * | | |Software can write 1 to clear this bit.\r
+ * |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status\r
+ * | | |0 = The input status of SUSCON pin is 0.\r
+ * | | |1 = The input status of SUSCON pin is 1.\r
+ * |[5] |BUSTO |Bus Time-out Status\r
+ * | | |0 = Indicates that there is no any time-out or external clock time-out.\r
+ * | | |1 = Indicates that a time-out or external clock time-out occurred.\r
+ * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.\r
+ * | | |Note: Software can write 1 to clear this bit.\r
+ * |[6] |CLKTO |Clock Low Accumulate Time-out Status\r
+ * | | |0 = Indicates that the cumulative clock low is no any time-out.\r
+ * | | |1 = Indicates that the cumulative clock low time-out occurred.\r
+ * | | |Note: Software can write 1 to clear this bit.\r
+ * |[7] |PECDONE |PEC Byte Transmission/Receive Done\r
+ * | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set.\r
+ * | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set.\r
+ * | | |Note: Software can write 1 to clear this bit.\r
+ * @var I2C_T::PKTSIZE\r
+ * Offset: 0x5C I2C Packet Error Checking Byte Number Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[8:0] |PLDSIZE |Transfer Byte Number\r
+ * | | |The transmission or receive byte number in one transaction when the PECEN is set\r
+ * | | |The maximum transaction or receive byte is 256 Bytes.\r
+ * | | |Notice: The byte number counting includes address, command code, and data frame.\r
+ * @var I2C_T::PKTCRC\r
+ * Offset: 0x60 I2C Packet Error Checking Byte Value Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |PECCRC |Packet Error Checking Byte Value\r
+ * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1\r
+ * | | |It is read only.\r
+ * @var I2C_T::BUSTOUT\r
+ * Offset: 0x64 I2C Bus Management Timer Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |BUSTO |Bus Management Time-out Value\r
+ * | | |Indicate the bus time-out value in bus is IDLE or SCLK low.\r
+ * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.\r
+ * @var I2C_T::CLKTOUT\r
+ * Offset: 0x68 I2C Bus Management Clock Low Timer Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |CLKTO |Bus Clock Low Timer\r
+ * | | |The field is used to configure the cumulative clock extension time-out.\r
+ * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.\r
+ */\r
+ __IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */\r
+ __IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */\r
+ __IO uint32_t DAT; /*!< [0x0008] I2C Data Register */\r
+ __I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */\r
+ __IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */\r
+ __IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */\r
+ __IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */\r
+ __IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */\r
+ __IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */\r
+ __IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */\r
+ __IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */\r
+ __IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */\r
+ __IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */\r
+ __I uint32_t RESERVE0[2];\r
+ __IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */\r
+ __IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */\r
+ __IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */\r
+ __IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */\r
+ __IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */\r
+ __IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */\r
+ __IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */\r
+ __IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */\r
+ __IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */\r
+ __I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */\r
+ __IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */\r
+ __IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */\r
+\r
+} I2C_T;\r
+\r
+/**\r
+ @addtogroup I2C_CONST I2C Bit Field Definition\r
+ Constant Definitions for I2C Controller\r
+@{ */\r
+\r
+#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL0: AA Position */\r
+#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL0: AA Mask */\r
+\r
+#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL0: SI Position */\r
+#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL0: SI Mask */\r
+\r
+#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL0: STO Position */\r
+#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL0: STO Mask */\r
+\r
+#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL0: STA Position */\r
+#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL0: STA Mask */\r
+\r
+#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL0: I2CEN Position */\r
+#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL0: I2CEN Mask */\r
+\r
+#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL0: INTEN Position */\r
+#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL0: INTEN Mask */\r
+\r
+#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */\r
+#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */\r
+\r
+#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */\r
+#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */\r
+\r
+#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */\r
+#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */\r
+\r
+#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS0: STATUS Position */\r
+#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS0_STATUS_Pos) /*!< I2C_T::STATUS0: STATUS Mask */\r
+\r
+#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */\r
+#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */\r
+\r
+#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */\r
+#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */\r
+\r
+#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */\r
+#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */\r
+\r
+#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */\r
+#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */\r
+\r
+#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */\r
+#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */\r
+\r
+#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */\r
+#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */\r
+\r
+#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */\r
+#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */\r
+\r
+#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */\r
+#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */\r
+\r
+#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */\r
+#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */\r
+\r
+#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */\r
+#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */\r
+\r
+#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */\r
+#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */\r
+\r
+#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */\r
+#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */\r
+\r
+#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */\r
+#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */\r
+\r
+#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */\r
+#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */\r
+\r
+#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */\r
+#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */\r
+\r
+#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */\r
+#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */\r
+\r
+#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */\r
+#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */\r
+\r
+#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */\r
+#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */\r
+\r
+#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */\r
+#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */\r
+\r
+#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */\r
+#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */\r
+\r
+#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */\r
+#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */\r
+\r
+#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */\r
+#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */\r
+\r
+#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */\r
+#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */\r
+\r
+#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */\r
+#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */\r
+\r
+#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */\r
+#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */\r
+\r
+#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */\r
+#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */\r
+\r
+#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */\r
+#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */\r
+\r
+#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */\r
+#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */\r
+\r
+#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */\r
+#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */\r
+\r
+#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */\r
+#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */\r
+\r
+#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */\r
+#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */\r
+\r
+#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */\r
+#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */\r
+\r
+#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */\r
+#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */\r
+\r
+#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */\r
+#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */\r
+\r
+#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */\r
+#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */\r
+\r
+#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */\r
+#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */\r
+\r
+#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */\r
+#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */\r
+\r
+#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */\r
+#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */\r
+\r
+#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */\r
+#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */\r
+\r
+#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */\r
+#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */\r
+\r
+#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */\r
+#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */\r
+\r
+#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */\r
+#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */\r
+\r
+#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */\r
+#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */\r
+\r
+#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */\r
+#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */\r
+\r
+#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */\r
+#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */\r
+\r
+#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */\r
+#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */\r
+\r
+#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */\r
+#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */\r
+\r
+#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */\r
+#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */\r
+\r
+#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */\r
+#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */\r
+\r
+#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */\r
+#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */\r
+\r
+#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */\r
+#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */\r
+\r
+#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */\r
+#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */\r
+\r
+#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */\r
+#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */\r
+\r
+#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */\r
+#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */\r
+\r
+#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */\r
+#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */\r
+\r
+#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */\r
+#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */\r
+\r
+#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */\r
+#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */\r
+\r
+#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */\r
+#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */\r
+\r
+#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */\r
+#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */\r
+\r
+#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */\r
+#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */\r
+\r
+#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */\r
+#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */\r
+\r
+#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */\r
+#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */\r
+\r
+/**@}*/ /* I2C_CONST */\r
+/**@}*/ /* end of I2C register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __I2C_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file i2s_reg.h\r
+ * @version V1.00\r
+ * @brief I2S register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __I2S_REG_H__\r
+#define __I2S_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- I2S Interface Controller -------------------------*/\r
+/**\r
+ @addtogroup I2S I2S Interface Controller(I2S)\r
+ Memory Mapped Structure for I2S Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var I2S_T::CTL0\r
+ * Offset: 0x00 I2S Control Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |I2SEN |I2S Controller Enable Control\r
+ * | | |0 = I2S controller Disabled.\r
+ * | | |1 = I2S controller Enabled.\r
+ * |[1] |TXEN |Transmit Enable Control\r
+ * | | |0 = Data transmission Disabled.\r
+ * | | |1 = Data transmission Enabled.\r
+ * |[2] |RXEN |Receive Enable Control\r
+ * | | |0 = Data receiving Disabled.\r
+ * | | |1 = Data receiving Enabled.\r
+ * |[3] |MUTE |Transmit Mute Enable Control\r
+ * | | |0 = Transmit data is shifted from buffer.\r
+ * | | |1 = Send zero on transmit channel.\r
+ * |[5:4] |DATWIDTH |Data Width\r
+ * | | |This bit field is used to define the bit-width of data word in each audio channel\r
+ * | | |00 = The bit-width of data word is 8-bit.\r
+ * | | |01 = The bit-width of data word is 16-bit.\r
+ * | | |10 = The bit-width of data word is 24-bit.\r
+ * | | |11 = The bit-width of data word is 32-bit.\r
+ * |[6] |MONO |Monaural Data Control\r
+ * | | |0 = Data is stereo format.\r
+ * | | |1 = Data is monaural format.\r
+ * | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected.\r
+ * |[7] |ORDER |Stereo Data Order in FIFO\r
+ * | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte\r
+ * | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.\r
+ * | | |0 = Even channel data at high byte in 8-bit/16-bit data width.\r
+ * | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries.\r
+ * | | |1 = Even channel data at low byte.\r
+ * | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries.\r
+ * |[8] |SLAVE |Slave Mode Enable Control\r
+ * | | |0 = Master mode.\r
+ * | | |1 = Slave mode.\r
+ * | | |Note: I2S can operate as master or slave\r
+ * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip\r
+ * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.\r
+ * |[15] |MCLKEN |Master Clock Enable Control\r
+ * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.\r
+ * | | |0 = Master clock Disabled.\r
+ * | | |1 = Master clock Enabled.\r
+ * |[18] |TXFBCLR |Transmit FIFO Buffer Clear\r
+ * | | |0 = No Effect.\r
+ * | | |1 = Clear TX FIFO.\r
+ * | | |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.\r
+ * | | |Note2: This bit is clear by hardware automatically, read it return zero.\r
+ * |[19] |RXFBCLR |Receive FIFO Buffer Clear\r
+ * | | |0 = No Effect.\r
+ * | | |1 = Clear RX FIFO.\r
+ * | | |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.\r
+ * | | |Note2: This bit is cleared by hardware automatically, read it return zero.\r
+ * |[20] |TXPDMAEN |Transmit PDMA Enable Control\r
+ * | | |0 = Transmit PDMA function Disabled.\r
+ * | | |1 = Transmit PDMA function Enabled.\r
+ * |[21] |RXPDMAEN |Receive PDMA Enable Control\r
+ * | | |0 = Receiver PDMA function Disabled.\r
+ * | | |1 = Receiver PDMA function Enabled.\r
+ * |[23] |RXLCH |Receive Left Channel Enable Control\r
+ * | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1.\r
+ * | | |0 = Receives channel1 data in MONO mode.\r
+ * | | |1 = Receives channel0 data in MONO mode.\r
+ * |[26:24] |FORMAT |Data Format Selection\r
+ * | | |000 = I2S standard data format.\r
+ * | | |001 = I2S with MSB justified.\r
+ * | | |010 = I2S with LSB justified.\r
+ * | | |011 = Reserved.\r
+ * | | |100 = PCM standard data format.\r
+ * | | |101 = PCM with MSB justified.\r
+ * | | |110 = PCM with LSB justified.\r
+ * | | |111 = Reserved.\r
+ * |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection\r
+ * | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol\r
+ * | | |0 = One BCLK period.\r
+ * | | |1 = One channel period.\r
+ * | | |Note: This bit is only available in master mode\r
+ * |[29:28] |CHWIDTH |Channel Width\r
+ * | | |This bit fields are used to define the length of audio channel\r
+ * | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH.\r
+ * | | |00 = The bit-width of each audio channel is 8-bit.\r
+ * | | |01 = The bit-width of each audio channel is 16-bit.\r
+ * | | |10 = The bit-width of each audio channel is 24-bit.\r
+ * | | |11 = The bit-width of each audio channel is 32-bit.\r
+ * |[31:30] |TDMCHNUM |TDM Channel Number\r
+ * | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1).\r
+ * | | |00 = 2 channels in audio frame.\r
+ * | | |01 = 4 channels in audio frame.\r
+ * | | |10 = 6 channels in audio frame.\r
+ * | | |11 = 8 channels in audio frame.\r
+ * @var I2S_T::CLKDIV\r
+ * Offset: 0x04 I2S Clock Divider Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[5:0] |MCLKDIV |Master Clock Divider\r
+ * | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip\r
+ * | | |If MCLKDIV is set to 0, MCLK is the same as external clock input.\r
+ * | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1.\r
+ * | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ).\r
+ * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ).\r
+ * | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK\r
+ * |[16:8] |BCLKDIV |Bit Clock Divider\r
+ * | | |The I2S controller will generate bit clock in Master mode\r
+ * | | |Software can program these bit fields to generate sampling rate clock frequency.\r
+ * | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)).\r
+ * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK\r
+ * @var I2S_T::IEN\r
+ * Offset: 0x08 I2S Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1.\r
+ * |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1\r
+ * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1\r
+ * | | |If RXTHIEN bit is enabled, interrupt occur.\r
+ * |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1.\r
+ * |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1\r
+ * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]).\r
+ * |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross\r
+ * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.\r
+ * |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross\r
+ * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.\r
+ * |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross\r
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross\r
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross\r
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross\r
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross\r
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross\r
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * @var I2S_T::STATUS0\r
+ * Offset: 0x0C I2S Status Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |I2SINT |I2S Interrupt Flag (Read Only)\r
+ * | | |0 = No I2S interrupt.\r
+ * | | |1 = I2S interrupt.\r
+ * | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits.\r
+ * |[1] |I2SRXINT |I2S Receive Interrupt (Read Only)\r
+ * | | |0 = No receive interrupt.\r
+ * | | |1 = Receive interrupt.\r
+ * |[2] |I2STXINT |I2S Transmit Interrupt (Read Only)\r
+ * | | |0 = No transmit interrupt.\r
+ * | | |1 = Transmit interrupt.\r
+ * |[5:3] |DATACH |Transmission Data Channel (Read Only)\r
+ * | | |This bit fields are used to indicate which audio channel is current transmit data belong.\r
+ * | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode).\r
+ * | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode).\r
+ * | | |010 = channel2 (available while 4-channel TDM PCM mode).\r
+ * | | |011 = channel3 (available while 4-channel TDM PCM mode).\r
+ * | | |100 = channel4 (available while 6-channel TDM PCM mode).\r
+ * | | |101 = channel5 (available while 6-channel TDM PCM mode).\r
+ * | | |110 = channel6 (available while 8-channel TDM PCM mode).\r
+ * | | |111 = channel7 (available while 8-channel TDM PCM mode).\r
+ * |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag\r
+ * | | |0 = No underflow occur.\r
+ * | | |1 = Underflow occur.\r
+ * | | |Note1: When receive FIFO is empty, and software reads the receive FIFO again\r
+ * | | |This bit will be set to 1, and it indicates underflow situation occurs.\r
+ * | | |Note2: Write 1 to clear this bit to zero\r
+ * |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag\r
+ * | | |0 = No overflow occur.\r
+ * | | |1 = Overflow occur.\r
+ * | | |Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.\r
+ * | | |Note2: Write 1 to clear this bit to 0.\r
+ * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)\r
+ * | | |0 = Data word(s) in FIFO is not higher than threshold level.\r
+ * | | |1 = Data word(s) in FIFO is higher than threshold level.\r
+ * | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1\r
+ * | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register.\r
+ * |[11] |RXFULL |Receive FIFO Full (Read Only)\r
+ * | | |0 = Not full.\r
+ * | | |1 = Full.\r
+ * | | |Note: This bit reflects data words number in receive FIFO is 16.\r
+ * |[12] |RXEMPTY |Receive FIFO Empty (Read Only)\r
+ * | | |0 = Not empty.\r
+ * | | |1 = Empty.\r
+ * | | |Note: This bit reflects data words number in receive FIFO is zero\r
+ * |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag\r
+ * | | |0 = No underflow.\r
+ * | | |1 = Underflow.\r
+ * | | |Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.\r
+ * | | |Note2: Write 1 to clear this bit to 0.\r
+ * |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag\r
+ * | | |0 = No overflow.\r
+ * | | |1 = Overflow.\r
+ * | | |Note1: Write data to transmit FIFO when it is full and this bit set to 1\r
+ * | | |Note2: Write 1 to clear this bit to 0.\r
+ * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)\r
+ * | | |0 = Data word(s) in FIFO is higher than threshold level.\r
+ * | | |1 = Data word(s) in FIFO is equal or lower than threshold level.\r
+ * | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1\r
+ * | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register.\r
+ * |[19] |TXFULL |Transmit FIFO Full (Read Only)\r
+ * | | |This bit reflect data word number in transmit FIFO is 16\r
+ * | | |0 = Not full.\r
+ * | | |1 = Full.\r
+ * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only)\r
+ * | | |This bit reflect data word number in transmit FIFO is zero\r
+ * | | |0 = Not empty.\r
+ * | | |1 = Empty.\r
+ * |[21] |TXBUSY |Transmit Busy (Read Only)\r
+ * | | |0 = Transmit shift buffer is empty.\r
+ * | | |1 = Transmit shift buffer is busy.\r
+ * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out\r
+ * | | |And set to 1 when 1st data is load to shift buffer\r
+ * @var I2S_T::TXFIFO\r
+ * Offset: 0x10 I2S Transmit FIFO Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |TXFIFO |Transmit FIFO Bits\r
+ * | | |I2S contains 16 words (16x32 bit) data buffer for data transmit\r
+ * | | |Write data to this register to prepare data for transmit\r
+ * | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]).\r
+ * @var I2S_T::RXFIFO\r
+ * Offset: 0x14 I2S Receive FIFO Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |RXFIFO |Receive FIFO Bits\r
+ * | | |I2S contains 16 words (16x32 bit) data buffer for data receive\r
+ * | | |Read this register to get data in FIFO\r
+ * | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]).\r
+ * @var I2S_T::CTL1\r
+ * Offset: 0x20 I2S Control Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control\r
+ * | | |0 = channel0 zero-cross detect Disabled.\r
+ * | | |1 = channel0 zero-cross detect Enabled.\r
+ * | | |Note1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.\r
+ * | | |Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.\r
+ * | | |Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute.\r
+ * |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control\r
+ * | | |0 = channel1 zero-cross detect Disabled.\r
+ * | | |1 = channel1 zero-cross detect Enabled.\r
+ * | | |Note1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.\r
+ * | | |Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.\r
+ * | | |Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute.\r
+ * |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control\r
+ * | | |0 = channel2 zero-cross detect Disabled.\r
+ * | | |1 = channel2 zero-cross detect Enabled.\r
+ * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * | | |Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.\r
+ * | | |Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute.\r
+ * |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control\r
+ * | | |0 = channel3 zero-cross detect Disabled.\r
+ * | | |1 = channel3 zero-cross detect Enabled.\r
+ * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * | | |Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.\r
+ * | | |Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute.\r
+ * |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control\r
+ * | | |0 = channel4 zero-cross detect Disabled.\r
+ * | | |1 = channel4 zero-cross detect Enabled.\r
+ * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * | | |Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.\r
+ * | | |Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute.\r
+ * |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control\r
+ * | | |0 = channel5 zero-cross detect Disabled.\r
+ * | | |1 = channel5 zero-cross detect Enabled.\r
+ * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * | | |Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.\r
+ * | | |Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute.\r
+ * |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control\r
+ * | | |0 = channel6 zero-cross detect Disabled.\r
+ * | | |1 = channel6 zero-cross detect Enabled.\r
+ * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * | | |Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.\r
+ * | | |Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute.\r
+ * |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control\r
+ * | | |0 = channel7 zero-cross detect Disabled.\r
+ * | | |1 = channel7 zero-cross detect Enabled.\r
+ * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * | | |Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.\r
+ * | | |Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute.\r
+ * |[11:8] |TXTH |Transmit FIFO Threshold Level\r
+ * | | |0000 = 0 data word in transmit FIFO.\r
+ * | | |0001 = 1 data word in transmit FIFO.\r
+ * | | |0010 = 2 data words in transmit FIFO.\r
+ * | | |...\r
+ * | | |1110 = 14 data words in transmit FIFO.\r
+ * | | |1111 = 15 data words in transmit FIFO.\r
+ * | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set.\r
+ * |[19:16] |RXTH |Receive FIFO Threshold Level\r
+ * | | |0000 = 1 data word in receive FIFO.\r
+ * | | |0001 = 2 data words in receive FIFO.\r
+ * | | |0010 = 3 data words in receive FIFO.\r
+ * | | |...\r
+ * | | |1110 = 15 data words in receive FIFO.\r
+ * | | |1111 = 16 data words in receive FIFO.\r
+ * | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set.\r
+ * |[24] |PBWIDTH |Peripheral Bus Data Width Selection\r
+ * | | |This bit is used to choice the available data width of APB bus\r
+ * | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode\r
+ * | | |0 = 32 bits data width.\r
+ * | | |1 = 16 bits data width.\r
+ * | | |Note1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available.\r
+ * | | |Note2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations.\r
+ * | | |Note3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations.\r
+ * |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus\r
+ * | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access\r
+ * | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries.\r
+ * | | |0 = Low 16-bit read/write access first.\r
+ * | | |1 = High 16-bit read/write access first.\r
+ * | | |Note: This bit is available while PBWIDTH = 1.\r
+ * @var I2S_T::STATUS1\r
+ * Offset: 0x24 I2S Status Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag\r
+ * | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero.\r
+ * | | |0 = No zero-cross in channel0.\r
+ * | | |1 = Channel0 zero-cross is detected.\r
+ * | | |Note1: Write 1 to clear this bit to 0.\r
+ * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.\r
+ * |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag\r
+ * | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero.\r
+ * | | |0 = No zero-cross in channel1.\r
+ * | | |1 = Channel1 zero-cross is detected.\r
+ * | | |Note1: Write 1 to clear this bit to 0.\r
+ * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.\r
+ * |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag\r
+ * | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero.\r
+ * | | |0 = No zero-cross in channel2.\r
+ * | | |1 = Channel2 zero-cross is detected.\r
+ * | | |Note1: Write 1 to clear this bit to 0.\r
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag\r
+ * | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero.\r
+ * | | |0 = No zero-cross in channel3.\r
+ * | | |1 = Channel3 zero-cross is detected.\r
+ * | | |Note1: Write 1 to clear this bit to 0.\r
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag\r
+ * | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero.\r
+ * | | |0 = No zero-cross in channel4.\r
+ * | | |1 = Channel4 zero-cross is detected.\r
+ * | | |Note1: Write 1 to clear this bit to 0.\r
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag\r
+ * | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero.\r
+ * | | |0 = No zero-cross in channel5.\r
+ * | | |1 = Channel5 zero-cross is detected.\r
+ * | | |Note1: Write 1 to clear this bit to 0.\r
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag\r
+ * | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero.\r
+ * | | |0 = No zero-cross in channel6.\r
+ * | | |1 = Channel6 zero-cross is detected.\r
+ * | | |Note1: Write 1 to clear this bit to 0.\r
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag\r
+ * | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero.\r
+ * | | |0 = No zero-cross in channel7.\r
+ * | | |1 = Channel7 zero-cross is detected.\r
+ * | | |Note1: Write 1 to clear this bit to 0.\r
+ * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.\r
+ * |[12:8] |TXCNT |Transmit FIFO Level (Read Only)\r
+ * | | |These bits indicate the number of available entries in transmit FIFO\r
+ * | | |00000 = No data.\r
+ * | | |00001 = 1 word in transmit FIFO.\r
+ * | | |00010 = 2 words in transmit FIFO.\r
+ * | | |...\r
+ * | | |01110 = 14 words in transmit FIFO.\r
+ * | | |01111 = 15 words in transmit FIFO.\r
+ * | | |10000 = 16 words in transmit FIFO.\r
+ * | | |Others are reserved.\r
+ * |[20:16] |RXCNT |Receive FIFO Level (Read Only)\r
+ * | | |These bits indicate the number of available entries in receive FIFO\r
+ * | | |00000 = No data.\r
+ * | | |00001 = 1 word in receive FIFO.\r
+ * | | |00010 = 2 words in receive FIFO.\r
+ * | | |...\r
+ * | | |01110 = 14 words in receive FIFO.\r
+ * | | |01111 = 15 words in receive FIFO.\r
+ * | | |10000 = 16 words in receive FIFO.\r
+ * | | |Others are reserved.\r
+ */\r
+ __IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */\r
+ __IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */\r
+ __IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */\r
+ __IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */\r
+ __O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */\r
+ __I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */\r
+ __I uint32_t RESERVE0[2];\r
+ __IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */\r
+ __IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */\r
+\r
+} I2S_T;\r
+\r
+/**\r
+ @addtogroup I2S_CONST I2S Bit Field Definition\r
+ Constant Definitions for I2S Controller\r
+@{ */\r
+\r
+#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */\r
+#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */\r
+\r
+#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */\r
+#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */\r
+\r
+#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */\r
+#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */\r
+\r
+#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */\r
+#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */\r
+\r
+#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */\r
+#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */\r
+\r
+#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */\r
+#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */\r
+\r
+#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */\r
+#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */\r
+\r
+#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */\r
+#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */\r
+\r
+#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */\r
+#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */\r
+\r
+#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */\r
+#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */\r
+\r
+#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */\r
+#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */\r
+\r
+#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */\r
+#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */\r
+\r
+#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */\r
+#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */\r
+\r
+#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */\r
+#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */\r
+\r
+#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */\r
+#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */\r
+\r
+#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */\r
+#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */\r
+\r
+#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */\r
+#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */\r
+\r
+#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */\r
+#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */\r
+\r
+#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */\r
+#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */\r
+\r
+#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */\r
+#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */\r
+\r
+#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */\r
+#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */\r
+\r
+#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */\r
+#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */\r
+\r
+#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */\r
+#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */\r
+\r
+#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */\r
+#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */\r
+\r
+#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */\r
+#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */\r
+\r
+#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */\r
+#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */\r
+\r
+#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */\r
+#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */\r
+\r
+#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */\r
+#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */\r
+\r
+#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */\r
+#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */\r
+\r
+#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */\r
+#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */\r
+\r
+#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */\r
+#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */\r
+\r
+#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */\r
+#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */\r
+\r
+#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */\r
+#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */\r
+\r
+#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */\r
+#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */\r
+\r
+#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */\r
+#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */\r
+\r
+#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */\r
+#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */\r
+\r
+#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */\r
+#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */\r
+\r
+#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */\r
+#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */\r
+\r
+#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */\r
+#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */\r
+\r
+#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */\r
+#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */\r
+\r
+#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */\r
+#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */\r
+\r
+#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */\r
+#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */\r
+\r
+#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */\r
+#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */\r
+\r
+#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */\r
+#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */\r
+\r
+#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */\r
+#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */\r
+\r
+#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */\r
+#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */\r
+\r
+#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */\r
+#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */\r
+\r
+#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */\r
+#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */\r
+\r
+#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */\r
+#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */\r
+\r
+#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */\r
+#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */\r
+\r
+#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */\r
+#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */\r
+\r
+#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */\r
+#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */\r
+\r
+#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */\r
+#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */\r
+\r
+#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */\r
+#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */\r
+\r
+#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */\r
+#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */\r
+\r
+#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */\r
+#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */\r
+\r
+#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */\r
+#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */\r
+\r
+#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */\r
+#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */\r
+\r
+#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */\r
+#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */\r
+\r
+#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */\r
+#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */\r
+\r
+#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */\r
+#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */\r
+\r
+#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */\r
+#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */\r
+\r
+#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */\r
+#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */\r
+\r
+#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */\r
+#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */\r
+\r
+#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */\r
+#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */\r
+\r
+#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */\r
+#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */\r
+\r
+#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */\r
+#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */\r
+\r
+#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */\r
+#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */\r
+\r
+#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */\r
+#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */\r
+\r
+#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */\r
+#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */\r
+\r
+#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */\r
+#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */\r
+\r
+#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */\r
+#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */\r
+\r
+#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */\r
+#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */\r
+\r
+/**@}*/ /* I2S_CONST */\r
+/**@}*/ /* end of I2S register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+\r
+#endif /* __I2S_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file otg_reg.h\r
+ * @version V1.00\r
+ * @brief OTG register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __OTG_REG_H__\r
+#define __OTG_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- USB On-The-Go Controller -------------------------*/\r
+/**\r
+ @addtogroup OTG USB On-The-Go Controller(OTG)\r
+ Memory Mapped Structure for OTG Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var OTG_T::CTL\r
+ * Offset: 0x00 OTG Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |VBUSDROP |Drop VBUS Control\r
+ * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS\r
+ * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.\r
+ * | | |0 = Not drop the VBUS.\r
+ * | | |1 = Drop the VBUS.\r
+ * |[1] |BUSREQ |OTG Bus Request\r
+ * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection\r
+ * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power\r
+ * | | |This bit will be cleared when A-device goes to A_wait_vfall state\r
+ * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.\r
+ * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol\r
+ * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues SRP in specified interval, defined in OTG specification)\r
+ * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.\r
+ * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.\r
+ * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.\r
+ * |[2] |HNPREQEN |OTG HNP Request Enable Bit\r
+ * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral\r
+ * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state\r
+ * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host\r
+ * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.\r
+ * | | |0 = HNP request Disabled.\r
+ * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).\r
+ * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.\r
+ * |[4] |OTGEN |OTG Function Enable Bit\r
+ * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device\r
+ * | | |When USB frame not configured as OTG device, this bit is must be low.\r
+ * | | |0= OTG function Disabled.\r
+ * | | |1 = OTG function Enabled.\r
+ * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit\r
+ * | | |0 = OTG ID pin status change wake-up function Disabled.\r
+ * | | |1 = OTG ID pin status change wake-up function Enabled.\r
+ * @var OTG_T::PHYCTL\r
+ * Offset: 0x04 OTG PHY Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |OTGPHYEN |OTG PHY Enable Bit\r
+ * | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function\r
+ * | | |If device is not configured as OTG-device nor ID-dependent , this bit is "don't care".\r
+ * | | |0 = OTG PHY Disabled.\r
+ * | | |1 = OTG PHY Enabled.\r
+ * |[1] |IDDETEN |ID Detection Enable Bit\r
+ * | | |0 = Detect ID pin status Disabled.\r
+ * | | |1 = Detect ID pin status Enabled.\r
+ * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity\r
+ * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need\r
+ * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.\r
+ * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component\r
+ * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.\r
+ * | | |0 = The off-chip USB VBUS power switch enable is active high.\r
+ * | | |1 = The off-chip USB VBUS power switch enable is active low.\r
+ * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity\r
+ * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component\r
+ * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch\r
+ * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.\r
+ * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.\r
+ * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.\r
+ * @var OTG_T::INTEN\r
+ * Offset: 0x08 OTG Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG specification.\r
+ * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * | | |Note: Going to idle state means going to a_idle or b_idle state\r
+ * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.\r
+ * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit\r
+ * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, an interrupt will be asserted.\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit\r
+ * | | |If this bit is set to 1 and the device is changed as a peripheral, an interrupt will be asserted.\r
+ * | | |0 = This device as a peripheral interrupt Disabled.\r
+ * | | |1 = This device as a peripheral interrupt Enabled.\r
+ * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit\r
+ * | | |If this bit is set to 1 and the device is changed as a host, an interrupt will be asserted.\r
+ * | | |0 = This device as a host interrupt Disabled.\r
+ * | | |1 = This device as a host interrupt Enabled.\r
+ * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit\r
+ * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, an interrupt will be asserted.\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit\r
+ * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, an interrupt will be asserted.\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit\r
+ * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, an interrupt will be asserted.\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit\r
+ * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, an interrupt will be asserted.\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * @var OTG_T::INTSTS\r
+ * Offset: 0x0C OTG Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ROLECHGIF |OTG Role Change Interrupt Status\r
+ * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.\r
+ * | | |0 = OTG device role not changed.\r
+ * | | |1 = OTG device role changed.\r
+ * | | |Note: Write 1 to clear this flag.\r
+ * |[1] |VBEIF |VBUS Error Interrupt Status\r
+ * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.\r
+ * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.\r
+ * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.\r
+ * | | |Note: Write 1 to clear this flag and recover from the VBUS error state.\r
+ * |[2] |SRPFIF |SRP Fail Interrupt Status\r
+ * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification\r
+ * | | |This flag is set when the OTG B-device does not get VBUS high after this interval.\r
+ * | | |0 = OTG B-device gets VBUS high before this interval.\r
+ * | | |1 = OTG B-device does not get VBUS high before this interval.\r
+ * | | |Note: Write 1 to clear this flag.\r
+ * |[3] |HNPFIF |HNP Fail Interrupt Status\r
+ * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.\r
+ * | | |0 = A-device connects to B-device before specified interval expires.\r
+ * | | |1 = A-device does not connect to B-device before specified interval expires.\r
+ * | | |Note: Write 1 to clear this flag.\r
+ * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status\r
+ * | | |Flag is set if the OTG device transfers from non-idle state to idle state\r
+ * | | |The OTG device will be neither a host nor a peripheral.\r
+ * | | |0 = OTG device does not go back to idle state (a_idle or b_idle).\r
+ * | | |1 = OTG device goes back to idle state(a_idle or b_idle).\r
+ * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.\r
+ * | | |Note 2: Write 1 to clear this flag.\r
+ * |[5] |IDCHGIF |ID State Change Interrupt Status\r
+ * | | |0 = IDSTS (OTG_STATUS[1]) not toggled.\r
+ * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.\r
+ * | | |Note: Write 1 to clear this flag.\r
+ * |[6] |PDEVIF |Act As Peripheral Interrupt Status\r
+ * | | |0= This device does not act as a peripheral.\r
+ * | | |1 = This device acts as a peripheral.\r
+ * | | |Note: Write 1 to clear this flag.\r
+ * |[7] |HOSTIF |Act As Host Interrupt Status\r
+ * | | |0= This device does not act as a host.\r
+ * | | |1 = This device acts as a host.\r
+ * | | |Note: Write 1 to clear this flag.\r
+ * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status\r
+ * | | |0 = BVLD (OTG_STATUS[3]) is not toggled.\r
+ * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.\r
+ * | | |Note: Write 1 to clear this status.\r
+ * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status\r
+ * | | |0 = AVLD (OTG_STATUS[4]) not toggled.\r
+ * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.\r
+ * | | |Note: Write 1 to clear this status.\r
+ * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status\r
+ * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.\r
+ * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.\r
+ * | | |Note: Write 1 to clear this status.\r
+ * |[11] |SECHGIF |SESSEND State Change Interrupt Status\r
+ * | | |0 = SESSEND (OTG_STATUS[2]) not toggled.\r
+ * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.\r
+ * | | |Note: Write 1 to clear this flag.\r
+ * |[13] |SRPDETIF |SRP Detected Interrupt Status\r
+ * | | |0 = SRP not detected.\r
+ * | | |1 = SRP detected.\r
+ * | | |Note: Write 1 to clear this status.\r
+ * @var OTG_T::STATUS\r
+ * Offset: 0x10 OTG Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |OVERCUR |Over Current Condition\r
+ * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.\r
+ * | | |0 = OTG A-device drives VBUS successfully.\r
+ * | | |1 = OTG A-device cannot drives VBUS high in this interval.\r
+ * |[1] |IDSTS |USB_ID Pin State of Mini-/Micro- Plug\r
+ * | | |0 = Mini-A/Micro-A plug is attached.\r
+ * | | |1 = Mini-B/Micro-B plug is attached.\r
+ * |[2] |SESSEND |Session End Status\r
+ * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1\r
+ * | | |Session end means no meaningful power on VBUS.\r
+ * | | |0 = Session is not end.\r
+ * | | |1 = Session is end.\r
+ * |[3] |BVLD |B-device Session Valid Status\r
+ * | | |0 = B-device session is not valid.\r
+ * | | |1 = B-device session is valid.\r
+ * |[4] |AVLD |A-device Session Valid Status\r
+ * | | |0 = A-device session is not valid.\r
+ * | | |1 = A-device session is valid.\r
+ * |[5] |VBUSVLD |VBUS Valid Status\r
+ * | | |When VBUS is larger than 4.7V, this bit will be set to 1.\r
+ * | | |0 = VBUS is not valid.\r
+ * | | |1 = VBUS is valid.\r
+ * |[6] |ASPERI |As Peripheral Status\r
+ * | | |When OTG as peripheral, this bit is set.\r
+ * | | |0: OTG not as peripheral\r
+ * | | |1: OTG as peripheral\r
+ * |[7] |ASHOST |As Host Status\r
+ * | | |When OTG as Host, this bit is set.\r
+ * | | |0: OTG not as Host\r
+ * | | |1: OTG as Host\r
+ */\r
+ __IO uint32_t CTL; /*!< [0x0000] OTG Control Register */\r
+ __IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */\r
+ __IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */\r
+ __IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */\r
+ __I uint32_t STATUS; /*!< [0x0010] OTG Status Register */\r
+\r
+} OTG_T;\r
+\r
+/**\r
+ @addtogroup OTG_CONST OTG Bit Field Definition\r
+ Constant Definitions for OTG Controller\r
+@{ */\r
+\r
+#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */\r
+#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */\r
+\r
+#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */\r
+#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */\r
+\r
+#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */\r
+#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */\r
+\r
+#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */\r
+#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */\r
+\r
+#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */\r
+#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */\r
+\r
+#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */\r
+#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */\r
+\r
+#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */\r
+#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */\r
+\r
+#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */\r
+#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */\r
+\r
+#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */\r
+#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */\r
+\r
+#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */\r
+#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */\r
+\r
+#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */\r
+#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */\r
+\r
+#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */\r
+#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */\r
+\r
+#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */\r
+#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */\r
+\r
+#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */\r
+#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */\r
+\r
+#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */\r
+#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */\r
+\r
+#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */\r
+#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */\r
+\r
+#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */\r
+#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */\r
+\r
+#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */\r
+#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */\r
+\r
+#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */\r
+#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */\r
+\r
+#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */\r
+#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */\r
+\r
+#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */\r
+#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */\r
+\r
+#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */\r
+#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */\r
+\r
+#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */\r
+#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */\r
+\r
+#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */\r
+#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */\r
+\r
+#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */\r
+#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */\r
+\r
+#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */\r
+#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */\r
+\r
+#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */\r
+#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */\r
+\r
+#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */\r
+#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */\r
+\r
+#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */\r
+#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */\r
+\r
+#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */\r
+#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */\r
+\r
+#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */\r
+#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */\r
+\r
+#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */\r
+#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */\r
+\r
+#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */\r
+#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */\r
+\r
+#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */\r
+#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */\r
+\r
+#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */\r
+#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */\r
+\r
+#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */\r
+#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */\r
+\r
+#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */\r
+#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */\r
+\r
+#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */\r
+#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */\r
+\r
+#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */\r
+#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */\r
+\r
+#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */\r
+#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */\r
+\r
+#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */\r
+#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */\r
+\r
+#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */\r
+#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */\r
+\r
+#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */\r
+#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */\r
+\r
+/**@}*/ /* OTG_CONST */\r
+/**@}*/ /* end of OTG register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+\r
+#endif /* __OTG_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file pdma_reg.h\r
+ * @version V1.00\r
+ * @brief PDMA register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __PDMA_REG_H__\r
+#define __PDMA_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/\r
+/**\r
+ @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)\r
+ Memory Mapped Structure for PDMA Controller\r
+@{ */\r
+\r
+\r
+\r
+typedef struct\r
+{\r
+ /**\r
+ * @var DSCT_T::CTL\r
+ * Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70 Descriptor Table Control Register of PDMA Channel 0~7\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |OPMODE |PDMA Operation Mode Selection\r
+ * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.\r
+ * | | |01 = Basic mode: The descriptor table only has one task\r
+ * | | |When this task is finished, the TDIF(PDMA_INTSTS[1]) will be asserted.\r
+ * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register; PDMA controller will ignore this task, then load the next task to execute.\r
+ * | | |11 = Reserved.\r
+ * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.\r
+ * |[2] |TXTYPE |Transfer Type\r
+ * | | |0 = Burst transfer type.\r
+ * | | |1 = Single transfer type.\r
+ * |[6:4] |BURSIZE |Burst Size\r
+ * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\r
+ * | | |000 = 128 Transfers.\r
+ * | | |001 = 64 Transfers.\r
+ * | | |010 = 32 Transfers.\r
+ * | | |011 = 16 Transfers.\r
+ * | | |100 = 8 Transfers.\r
+ * | | |101 = 4 Transfers.\r
+ * | | |110 = 2 Transfers.\r
+ * | | |111 = 1 Transfers.\r
+ * | | |Note: This field is only useful in burst transfer type.\r
+ * |[7] |TBINTDIS |Table Interrupt Disable Bit\r
+ * | | |This field can be used to decide whether to enable table interrupt or not\r
+ * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.\r
+ * | | |0 = Table interrupt Enabled.\r
+ * | | |1 = Table interrupt Disabled.\r
+ * | | |Note: If this bit set to 1, the TEMPTYF will not be set.\r
+ * |[9:8] |SAINC |Source Address Increment\r
+ * | | |This field is used to set the source address increment size.\r
+ * | | |11 = No increment (fixed address).\r
+ * | | |Others = Increment and size is depended on TXWIDTH selection.\r
+ * |[11:10] |DAINC |Destination Address Increment\r
+ * | | |This field is used to set the destination address increment size.\r
+ * | | |11 = No increment (fixed address).\r
+ * | | |Others = Increment and size is depended on TXWIDTH selection.\r
+ * |[13:12] |TXWIDTH |Transfer Width Selection\r
+ * | | |This field is used for transfer width.\r
+ * | | |00 = One byte (8 bit) is transferred for every operation.\r
+ * | | |01 = One half-word (16 bit) is transferred for every operation.\r
+ * | | |10 = One word (32-bit) is transferred for every operation.\r
+ * | | |11 = Reserved.\r
+ * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection\r
+ * | | |For example, if source address is 0x2000_0202, but TXWIDTH is word transfer, the source address is not word alignment\r
+ * | | |The source address is aligned when TXWIDTH is byte or half-word transfer.\r
+ * |[14] |TXACK |Transfer Acknowledge Selection\r
+ * | | |0 = transfer ack when transfer done.\r
+ * | | |1 = transfer ack when PDMA get transfer data.\r
+ * |[15] |STRIDEEN |Stride Mode Enable Bit\r
+ * | | |0 = Stride transfer mode Disabled.\r
+ * | | |1 = Stride transfer mode Enabled.\r
+ * |[31:16] |TXCNT |Transfer Count\r
+ * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.\r
+ * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.\r
+ * @var DSCT_T::SA\r
+ * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74 Source Address Register of PDMA Channel 0~7\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SA |PDMA Transfer Source Address Register\r
+ * | | |This field indicates a 32-bit source address of PDMA controller.\r
+ * | | |Note: The PDMA transfer source address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection.\r
+ * @var DSCT_T::DA\r
+ * Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78 Destination Address Register of PDMA Channel 0~7\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |DA |PDMA Transfer Destination Address Register\r
+ * | | |This field indicates a 32-bit destination address of PDMA controller.\r
+ * | | |Note: The PDMA transfer destination address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection.\r
+ * @var DSCT_T::NEXT\r
+ * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C First Scatter-Gather Descriptor Table Offset of PDMA Channel 0~7\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |FIRST |PDMA First Descriptor Table Offset\r
+ * | | |This field indicates the offset of the first descriptor table address in system memory.\r
+ * | | |Write Operation:\r
+ * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.\r
+ * | | |Read Operation:\r
+ * | | |When operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved.\r
+ * | | |Note1: The first descriptor table address must be word boundary.\r
+ * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.\r
+ * |[31:16] |NEXT |PDMA Next Descriptor Table Offset\r
+ * | | |This field indicates the offset of next descriptor table address in system memory.\r
+ * | | |Note: write operation is useless in this field.\r
+ */\r
+\r
+ __IO uint32_t CTL; /*!< [0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70] Descriptor Table Control Register of PDMA Channel 0~7 */\r
+ __IO uint32_t SA; /*!< [0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74] Source Address Register of PDMA Channel 0~7 */\r
+ __IO uint32_t DA; /*!< [0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78] Destination Address Register of PDMA Channel 0~7 */\r
+ __IO uint32_t NEXT; /*!< [0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C]Next Scatter-Gather Descriptor Table Offset */\r
+\r
+} DSCT_T;\r
+\r
+typedef struct\r
+{\r
+ /**\r
+ * @var STRIDE_T::STCR\r
+ * Offset: 0x500/0x508/0x510/0x518/0x520/0x528 Stride Transfer Count Register of PDMA Channel 0~5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |STC |PDMA Stride Transfer Count\r
+ * | | |The 16-bit register defines the stride transfer count of each row.\r
+ * @var STRIDE_T::ASOCR\r
+ * Offset: 0x504/0x50C/0x514/0x51C/0x524/0x52C Address Stride Offset Register of PDMA Channel 0~5\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |SASOL |VDMA Source Address Stride Offset Length\r
+ * | | |The 16-bit register defines the source address stride transfer offset count of each row.\r
+ * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length\r
+ * | | |The 16-bit register defines the destination address stride transfer offset count of each row.\r
+ */\r
+ __IO uint32_t STCR; /*!< [0x0500/0x508/0x510/0x518/0x520/0x528] Stride Transfer Count Register of PDMA Channel 0~7 */\r
+ __IO uint32_t ASOCR; /*!< [0x0504/0x50C/0x514/0x51C/0x524/0x52C] Address Stride Offset Register of PDMA Channel 0 */\r
+} STRIDE_T;\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var PDMA_T::CURSCAT\r
+ * Offset: 0x80/0x84/0x88/0x8C/0x90/0x94/0x98/0x9C Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only)\r
+ * | | |This field indicates a 32-bit current external description address of PDMA controller.\r
+ * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.\r
+ * @var PDMA_T::CHCTL\r
+ * Offset: 0x400 PDMA Channel Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |CHENn |PDMA Channel Enable Bit\r
+ * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\r
+ * | | |0 = PDMA channel [n] Disabled.\r
+ * | | |1 = PDMA channel [n] Enabled.\r
+ * | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.\r
+ * @var PDMA_T::PAUSE\r
+ * Offset: 0x404 PDMA Transfer Pause Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only)\r
+ * | | |User can set PAUSEn bit field to pause the PDMA transfer\r
+ * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag\r
+ * | | |If re-enable the paused channel again, the remaining transfers will be processed.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Pause PDMA channel n transfer.\r
+ * @var PDMA_T::SWREQ\r
+ * Offset: 0x408 PDMA Software Request Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |SWREQn |PDMA Software Request Register (Write Only)\r
+ * | | |Set this bit to 1 to generate a software request to PDMA [n].\r
+ * | | |0 = No effect.\r
+ * | | |1 = Generate a software request.\r
+ * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active\r
+ * | | |Active flag may be triggered by software request or peripheral request.\r
+ * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.\r
+ * @var PDMA_T::TRGSTS\r
+ * Offset: 0x40C PDMA Channel Request Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only)\r
+ * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral\r
+ * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.\r
+ * | | |0 = PDMA Channel n has no request.\r
+ * | | |1 = PDMA Channel n has a request.\r
+ * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.\r
+ * @var PDMA_T::PRISET\r
+ * Offset: 0x410 PDMA Fixed Priority Setting Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register\r
+ * | | |Set this bit to 1 to enable fixed priority level.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Set PDMA channel [n] to fixed priority channel.\r
+ * | | |Read Operation:\r
+ * | | |0 = Corresponding PDMA channel is round-robin priority.\r
+ * | | |1 = Corresponding PDMA channel is fixed priority.\r
+ * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.\r
+ * @var PDMA_T::PRICLR\r
+ * Offset: 0x414 PDMA Fixed Priority Clear Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only)\r
+ * | | |Set this bit to 1 to clear fixed priority level.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear PDMA channel [n] fixed priority setting.\r
+ * | | |Note: User can read PDMA_PRISET register to know the channel priority.\r
+ * @var PDMA_T::INTEN\r
+ * Offset: 0x418 PDMA Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |INTENn |PDMA Interrupt Enable Register\r
+ * | | |This field is used for enabling PDMA channel[n] interrupt.\r
+ * | | |0 = PDMA channel n interrupt Disabled.\r
+ * | | |1 = PDMA channel n interrupt Enabled.\r
+ * @var PDMA_T::INTSTS\r
+ * Offset: 0x41C PDMA Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read Only)\r
+ * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.\r
+ * | | |0 = No AHB bus ERROR response received.\r
+ * | | |1 = AHB bus ERROR response received.\r
+ * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)\r
+ * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.\r
+ * | | |0 = Not finished yet.\r
+ * | | |1 = PDMA channel has finished transmission.\r
+ * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only)\r
+ * | | |0 = PDMA channel source address and destination address both follow transfer width setting.\r
+ * | | |1 = PDMA channel source address or destination address is not follow transfer width setting.\r
+ * |[8] |REQTOF0 |Request Time-out Flag for Channel 0\r
+ * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.\r
+ * | | |0 = No request time-out.\r
+ * | | |1 = Peripheral request time-out.\r
+ * |[9] |REQTOF1 |Request Time-out Flag for Channel 1\r
+ * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.\r
+ * | | |0 = No request time-out.\r
+ * | | |1 = Peripheral request time-out.\r
+ * @var PDMA_T::ABTSTS\r
+ * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag\r
+ * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.\r
+ * | | |0 = No AHB bus ERROR response received when channel n transfer.\r
+ * | | |1 = AHB bus ERROR response received when channel n transfer.\r
+ * @var PDMA_T::TDSTS\r
+ * Offset: 0x424 PDMA Channel Transfer Done Flag Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |TDIFn |Transfer Done Flag Register\r
+ * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.\r
+ * | | |0 = PDMA channel transfer has not finished.\r
+ * | | |1 = PDMA channel has finished transmission.\r
+ * @var PDMA_T::ALIGN\r
+ * Offset: 0x428 PDMA Transfer Alignment Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |ALIGNn |Transfer Alignment Flag Register\r
+ * | | |0 = PDMA channel source address and destination address both follow transfer width setting.\r
+ * | | |1 = PDMA channel source address or destination address is not follow transfer width setting.\r
+ * @var PDMA_T::TACTSTS\r
+ * Offset: 0x42C PDMA Transfer Active Flag Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only)\r
+ * | | |This bit indicates which PDMA channel is in active.\r
+ * | | |0 = PDMA channel is not finished.\r
+ * | | |1 = PDMA channel is active.\r
+ * @var PDMA_T::TOUTPSC\r
+ * Offset: 0x430 PDMA Time-out Prescaler Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits\r
+ * | | |000 = PDMA channel 0 time-out clock source is HCLK/2^8.\r
+ * | | |001 = PDMA channel 0 time-out clock source is HCLK/2^9.\r
+ * | | |010 = PDMA channel 0 time-out clock source is HCLK/2^10.\r
+ * | | |011 = PDMA channel 0 time-out clock source is HCLK/2^11.\r
+ * | | |100 = PDMA channel 0 time-out clock source is HCLK/2^12.\r
+ * | | |101 = PDMA channel 0 time-out clock source is HCLK/2^13.\r
+ * | | |110 = PDMA channel 0 time-out clock source is HCLK/2^14.\r
+ * | | |111 = PDMA channel 0 time-out clock source is HCLK/2^15.\r
+ * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits\r
+ * | | |000 = PDMA channel 1 time-out clock source is HCLK/2^8.\r
+ * | | |001 = PDMA channel 1 time-out clock source is HCLK/2^9.\r
+ * | | |010 = PDMA channel 1 time-out clock source is HCLK/2^10.\r
+ * | | |011 = PDMA channel 1 time-out clock source is HCLK/2^11.\r
+ * | | |100 = PDMA channel 1 time-out clock source is HCLK/2^12.\r
+ * | | |101 = PDMA channel 1 time-out clock source is HCLK/2^13.\r
+ * | | |110 = PDMA channel 1 time-out clock source is HCLK/2^14.\r
+ * | | |111 = PDMA channel 1 time-out clock source is HCLK/2^15.\r
+ * @var PDMA_T::TOUTEN\r
+ * Offset: 0x434 PDMA Time-out Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |TOUTEN0 |PDMA Channel 0 Time-out Enable Bit\r
+ * | | |0 = PDMA Channel 0 time-out function Disable.\r
+ * | | |1 = PDMA Channel 0 time-out function Enable.\r
+ * |[1] |TOUTEN1 |PDMA Channel 1 Time-out Enable Bit\r
+ * | | |0 = PDMA Channel 1 time-out function Disable.\r
+ * | | |1 = PDMA Channel 1 time-out function Enable.\r
+ * @var PDMA_T::TOUTIEN\r
+ * Offset: 0x438 PDMA Time-out Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |TOUTIEN0 |PDMA Channel 0 Time-out Interrupt Enable Bit\r
+ * | | |0 = PDMA Channel 0 time-out interrupt Disable.\r
+ * | | |1 = PDMA Channel 0 time-out interrupt Enable.\r
+ * |[1] |TOUTIEN1 |PDMA Channel 1 Time-out Interrupt Enable Bit\r
+ * | | |0 = PDMA Channel 1 time-out interrupt Disable.\r
+ * | | |1 = PDMA Channel 1 time-out interrupt Enable.\r
+ * @var PDMA_T::SCATBA\r
+ * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register\r
+ * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address\r
+ * | | |The next link address equation is\r
+ * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.\r
+ * | | |Note: Only useful in Scatter-Gather mode.\r
+ * @var PDMA_T::TOC0_1\r
+ * Offset: 0x440 PDMA Channel 0 and Channel 1 Time-out Counter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |TOC0 |Time-out Counter for Channel 0\r
+ * | | |This controls the period of time-out function for channel 0\r
+ * | | |The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock.\r
+ * | | |Time-out period = (Period of time-out clock) * (16-bit TOCn),n = 0,1.\r
+ * |[31:16] |TOC1 |Time-out Counter for Channel 1\r
+ * | | |This controls the period of time-out function for channel 1\r
+ * | | |The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock\r
+ * | | |The example of time-out period can refer TOC0 bit description.\r
+ * @var PDMA_T::CHRST\r
+ * Offset: 0x460 PDMA Channel Reset Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |CHnRST |Channel N Reset\r
+ * | | |0 = corresponding channel n not reset.\r
+ * | | |1 = corresponding channel n is reset.\r
+ * @var PDMA_T::REQSEL0_3\r
+ * Offset: 0x480 PDMA Channel 0 to Channel 3 Request Source Select Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[6:0] |REQSRC0 |Channel 0 Request Source Selection\r
+ * | | |This filed defines which peripheral is connected to PDMA channel 0\r
+ * | | |User can configure the peripheral by setting REQSRC0.\r
+ * | | |0 = Disable PDMA.\r
+ * | | |1 = Reserved.\r
+ * | | |2 = Channel connects to USB_TX.\r
+ * | | |3 = Channel connects to USB_RX.\r
+ * | | |4 = Channel connects to UART0_TX.\r
+ * | | |5 = Channel connects to UART0_RX.\r
+ * | | |6 = Channel connects to UART1_TX.\r
+ * | | |7 = Channel connects to UART1_RX.\r
+ * | | |8 = Channel connects to UART2_TX.\r
+ * | | |9 = Channel connects to UART2_RX.\r
+ * | | |10 = Channel connects to UART3_TX.\r
+ * | | |11 = Channel connects to UART3_RX.\r
+ * | | |12 = Channel connects to UART4_TX.\r
+ * | | |13 = Channel connects to UART4_RX.\r
+ * | | |14 = Channel connects to UART5_TX.\r
+ * | | |15 = Channel connects to UART5_RX.\r
+ * | | |16 = Channel connects to USCI0_TX.\r
+ * | | |17 = Channel connects to USCI0_RX.\r
+ * | | |18 = Channel connects to USCI1_TX.\r
+ * | | |19 = Channel connects to USCI1_RX.\r
+ * | | |20 = Channel connects to QSPI0_TX.\r
+ * | | |21 = Channel connects to QSPI0_RX.\r
+ * | | |22 = Channel connects to SPI0_TX.\r
+ * | | |23 = Channel connects to SPI0_RX.\r
+ * | | |24 = Channel connects to SPI1_TX.\r
+ * | | |25 = Channel connects to SPI1_RX.\r
+ * | | |26 = Channel connects to SPI2_TX.\r
+ * | | |27 = Channel connects to SPI2_RX.\r
+ * | | |28 = Channel connects to SPI3_TX.\r
+ * | | |29 = Channel connects to SPI3_RX.\r
+ * | | |32 = Channel connects to EPWM0_P1_RX.\r
+ * | | |33 = Channel connects to EPWM0_P2_RX.\r
+ * | | |34 = Channel connects to EPWM0_P3_RX.\r
+ * | | |35 = Channel connects to EPWM1_P1_RX.\r
+ * | | |36 = Channel connects to EPWM1_P2_RX.\r
+ * | | |37 = Channel connects to EPWM1_P3_RX.\r
+ * | | |38 = Channel connects to I2C0_TX.\r
+ * | | |39 = Channel connects to I2C0_RX.\r
+ * | | |40 = Channel connects to I2C1_TX.\r
+ * | | |41 = Channel connects to I2C1_RX.\r
+ * | | |42 = Channel connects to I2C2_TX.\r
+ * | | |43 = Channel connects to I2C2_RX.\r
+ * | | |44 = Channel connects to I2S0_TX.\r
+ * | | |45 = Channel connects to I2S0_RX.\r
+ * | | |46 = Channel connects to TMR0.\r
+ * | | |47 = Channel connects to TMR1.\r
+ * | | |48 = Channel connects to TMR2.\r
+ * | | |49 = Channel connects to TMR3.\r
+ * | | |50 = Channel connects to ADC_RX.\r
+ * | | |51 = Channel connects to DAC0_TX.\r
+ * | | |52 = Channel connects to DAC1_TX.\r
+ * | | |53 = Channel connects to EPWM0_CH0_TX.\r
+ * | | |54 = Channel connects to EPWM0_CH1_TX.\r
+ * | | |55 = Channel connects to EPWM0_CH2_TX.\r
+ * | | |56 = Channel connects to EPWM0_CH3_TX.\r
+ * | | |57 = Channel connects to EPWM0_CH4_TX.\r
+ * | | |58 = Channel connects to EPWM0_CH5_TX.\r
+ * | | |59 = Channel connects to EPWM1_CH0_TX.\r
+ * | | |60 = Channel connects to EPWM1_CH1_TX.\r
+ * | | |61 = Channel connects to EPWM1_CH2_TX.\r
+ * | | |62 = Channel connects to EPWM1_CH3_TX.\r
+ * | | |63 = Channel connects to EPWM1_CH4_TX.\r
+ * | | |64 = Channel connects to EPWM1_CH5_TX.\r
+ * | | |Others = Reserved.\r
+ * | | |Note 1: A request source cannot assign to two channels at the same time.\r
+ * | | |Note 2: This field is useless when transfer between memory and memory.\r
+ * |[14:8] |REQSRC1 |Channel 1 Request Source Selection\r
+ * | | |This filed defines which peripheral is connected to PDMA channel 1\r
+ * | | |User can configure the peripheral setting by REQSRC1.\r
+ * | | |Note: The channel configuration is the same as REQSRC0 field\r
+ * | | |Please refer to the explanation of REQSRC0.\r
+ * |[22:16] |REQSRC2 |Channel 2 Request Source Selection\r
+ * | | |This filed defines which peripheral is connected to PDMA channel 2\r
+ * | | |User can configure the peripheral setting by REQSRC2.\r
+ * | | |Note: The channel configuration is the same as REQSRC0 field\r
+ * | | |Please refer to the explanation of REQSRC0.\r
+ * |[30:24] |REQSRC3 |Channel 3 Request Source Selection\r
+ * | | |This filed defines which peripheral is connected to PDMA channel 3\r
+ * | | |User can configure the peripheral setting by REQSRC3.\r
+ * | | |Note: The channel configuration is the same as REQSRC0 field\r
+ * | | |Please refer to the explanation of REQSRC0.\r
+ * @var PDMA_T::REQSEL4_7\r
+ * Offset: 0x484 PDMA Request Source Select Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[6:0] |REQSRC4 |Channel 4 Request Source Selection\r
+ * | | |This filed defines which peripheral is connected to PDMA channel 4\r
+ * | | |User can configure the peripheral setting by REQSRC4.\r
+ * | | |Note: The channel configuration is the same as REQSRC0 field\r
+ * | | |Please refer to the explanation of REQSRC0.\r
+ * |[14:8] |REQSRC5 |Channel 5 Request Source Selection\r
+ * | | |This filed defines which peripheral is connected to PDMA channel 5\r
+ * | | |User can configure the peripheral setting by REQSRC5.\r
+ * | | |Note: The channel configuration is the same as REQSRC0 field\r
+ * | | |Please refer to the explanation of REQSRC0.\r
+ * |[22:16] |REQSRC6 |Channel 6 Request Source Selection\r
+ * | | |This filed defines which peripheral is connected to PDMA channel 6\r
+ * | | |User can configure the peripheral setting by REQSRC6.\r
+ * | | |Note: The channel configuration is the same as REQSRC0 field\r
+ * | | |Please refer to the explanation of REQSRC0.\r
+ * |[30:24] |REQSRC7 |Channel 7 Request Source Selection\r
+ * | | |This filed defines which peripheral is connected to PDMA channel 7\r
+ * | | |User can configure the peripheral setting by REQSRC7.\r
+ * | | |Note: The channel configuration is the same as REQSRC0 field\r
+ * | | |Please refer to the explanation of REQSRC0.\r
+ */\r
+\r
+ DSCT_T DSCT[8]; /*!< [0x0000 ~ 0x007C] DMA Embedded Description Table 0~7 */\r
+ __I uint32_t CURSCAT[8]; /*!< [0x0080~0x009C] Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7 */\r
+ __I uint32_t RESERVE0[216];\r
+ __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */\r
+ __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */\r
+ __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */\r
+ __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */\r
+ __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */\r
+ __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */\r
+ __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */\r
+ __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */\r
+ __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */\r
+ __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */\r
+ __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */\r
+ __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */\r
+ __IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */\r
+ __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */\r
+ __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */\r
+ __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */\r
+ __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Channel 0 and Channel 1 Time-out Counter Register */\r
+ __I uint32_t RESERVE1[7];\r
+ __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */\r
+ __I uint32_t RESERVE2[7];\r
+ __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Channel 0 to Channel 3 Request Source Select Register */\r
+ __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Channel 4 to Channel 7 Request Source Select Register */\r
+ __I uint32_t RESERVE4[30];\r
+ STRIDE_T STRIDE[6]; /*!< [0x0500 ~ 0x052C] Stride function control register of PDMA Channel 0 ~ 5 */\r
+\r
+} PDMA_T;\r
+\r
+\r
+\r
+\r
+/**\r
+ @addtogroup PDMA_CONST PDMA Bit Field Definition\r
+ Constant Definitions for PDMA Controller\r
+@{ */\r
+\r
+#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */\r
+#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */\r
+\r
+#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */\r
+#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */\r
+\r
+#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */\r
+#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */\r
+\r
+#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */\r
+#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */\r
+\r
+#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */\r
+#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */\r
+\r
+#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */\r
+#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */\r
+\r
+#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */\r
+#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */\r
+\r
+#define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */\r
+#define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */\r
+\r
+#define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */\r
+#define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */\r
+\r
+#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */\r
+#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */\r
+\r
+#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */\r
+#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */\r
+\r
+#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */\r
+#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */\r
+\r
+#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */\r
+#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */\r
+\r
+#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */\r
+#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */\r
+\r
+#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */\r
+#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */\r
+\r
+#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */\r
+#define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */\r
+\r
+#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */\r
+#define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */\r
+\r
+#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */\r
+#define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */\r
+\r
+#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */\r
+#define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */\r
+\r
+#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */\r
+#define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */\r
+\r
+#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */\r
+#define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */\r
+\r
+#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */\r
+#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */\r
+\r
+#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */\r
+#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */\r
+\r
+#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */\r
+#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */\r
+\r
+#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */\r
+#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */\r
+\r
+#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */\r
+#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */\r
+\r
+#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */\r
+#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */\r
+#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */\r
+#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */\r
+#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */\r
+#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */\r
+#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */\r
+#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */\r
+#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */\r
+#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */\r
+#define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */\r
+#define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */\r
+#define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */\r
+#define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */\r
+#define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */\r
+#define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */\r
+#define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */\r
+\r
+#define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */\r
+#define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */\r
+#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */\r
+#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */\r
+#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */\r
+#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */\r
+#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */\r
+#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */\r
+#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */\r
+#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */\r
+#define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */\r
+#define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */\r
+#define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */\r
+#define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */\r
+#define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */\r
+#define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */\r
+#define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */\r
+\r
+#define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */\r
+#define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */\r
+\r
+#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */\r
+#define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */\r
+\r
+#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */\r
+#define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */\r
+\r
+#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */\r
+#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */\r
+\r
+#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */\r
+#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */\r
+\r
+#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */\r
+#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */\r
+\r
+#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */\r
+#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */\r
+\r
+#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */\r
+#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */\r
+\r
+#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */\r
+#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */\r
+\r
+#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */\r
+#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */\r
+\r
+#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */\r
+#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */\r
+\r
+#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */\r
+#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */\r
+\r
+#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */\r
+#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */\r
+\r
+#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */\r
+#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */\r
+\r
+#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */\r
+#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */\r
+\r
+#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */\r
+#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */\r
+\r
+#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */\r
+#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */\r
+\r
+#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */\r
+#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */\r
+\r
+#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */\r
+#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */\r
+\r
+#define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */\r
+#define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */\r
+\r
+#define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */\r
+#define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */\r
+\r
+#define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */\r
+#define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */\r
+\r
+/**@}*/ /* PDMA_CONST */\r
+/**@}*/ /* end of PDMA register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __PDMA_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file qei_reg.h\r
+ * @version V1.00\r
+ * @brief QEI register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __QEI_REG_H__\r
+#define __QEI_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Quadrature Encoder Interface -------------------------*/\r
+/**\r
+ @addtogroup QEI Quadrature Encoder Interface(QEI)\r
+ Memory Mapped Structure for QEI Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var QEI_T::CNT\r
+ * Offset: 0x00 QEI Counter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNT |Quadrature Encoder Interface Counter\r
+ * | | |A 32-bit up/down counter\r
+ * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF is zero\r
+ * | | |This register performs an integrator which count value is proportional to the encoder position\r
+ * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs:\r
+ * | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0.\r
+ * | | |2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode.\r
+ * | | |3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTL[27])=1.\r
+ * @var QEI_T::CNTHOLD\r
+ * Offset: 0x04 QEI Counter Hold Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold\r
+ * | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register.\r
+ * @var QEI_T::CNTLATCH\r
+ * Offset: 0x08 QEI Counter Index Latch Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch\r
+ * | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register.\r
+ * @var QEI_T::CNTCMP\r
+ * Offset: 0x0C QEI Counter Compare Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare\r
+ * | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set\r
+ * | | |This register is software writable.\r
+ * @var QEI_T::CNTMAX\r
+ * Offset: 0x14 QEI Pre-set Maximum Count Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count\r
+ * | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode\r
+ * @var QEI_T::CTL\r
+ * Offset: 0x18 QEI Controller Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection\r
+ * | | |To determine the sampling frequency of the Noise Filter clock .\r
+ * | | |000 = QEI_CLK.\r
+ * | | |001 = QEI_CLK/2.\r
+ * | | |010 = QEI_CLK/4.\r
+ * | | |011 = QEI_CLK/16.\r
+ * | | |100 = QEI_CLK/32.\r
+ * | | |101 = QEI_CLK/64.\r
+ * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit\r
+ * | | |0 = The noise filter of QEI controller Enabled.\r
+ * | | |1 = The noise filter of QEI controller Disabled.\r
+ * |[4] |CHAEN |QEA Input to QEI Controller Enable Bit\r
+ * | | |0 = QEA input to QEI Controller Disabled.\r
+ * | | |1 = QEA input to QEI Controller Enabled.\r
+ * |[5] |CHBEN |QEB Input to QEI Controller Enable Bit\r
+ * | | |0 = QEB input to QEI Controller Disabled.\r
+ * | | |1 = QEB input to QEI Controller Enabled.\r
+ * |[6] |IDXEN |IDX Input to QEI Controller Enable Bit\r
+ * | | |0 = IDX input to QEI Controller Disabled.\r
+ * | | |1 = IDX input to QEI Controller Enabled.\r
+ * |[9:8] |MODE |QEI Counting Mode Selection\r
+ * | | |There are four quadrature encoder pulse counter operation modes.\r
+ * | | |00 = X4 Free-counting Mode.\r
+ * | | |01 = X2 Free-counting Mode.\r
+ * | | |10 = X4 Compare-counting Mode.\r
+ * | | |11 = X2 Compare-counting Mode.\r
+ * |[12] |CHAINV |Inverse QEA Input Polarity\r
+ * | | |0 = Not inverse QEA input polarity.\r
+ * | | |1 = QEA input polarity is inverse to QEI controller.\r
+ * |[13] |CHBINV |Inverse QEB Input Polarity\r
+ * | | |0 = Not inverse QEB input polarity.\r
+ * | | |1 = QEB input polarity is inverse to QEI controller.\r
+ * |[14] |IDXINV |Inverse IDX Input Polarity\r
+ * | | |0 = Not inverse IDX input polarity.\r
+ * | | |1 = IDX input polarity is inverse to QEI controller.\r
+ * |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit\r
+ * | | |0 = OVUNF can trigger QEI controller interrupt Disabled.\r
+ * | | |1 = OVUNF can trigger QEI controller interrupt Enabled.\r
+ * |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit\r
+ * | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled.\r
+ * | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled.\r
+ * |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit\r
+ * | | |0 = CMPF can trigger QEI controller interrupt Disabled.\r
+ * | | |1 = CMPF can trigger QEI controller interrupt Enabled.\r
+ * |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit\r
+ * | | |0 = The IDXF can trigger QEI interrupt Disabled.\r
+ * | | |1 = The IDXF can trigger QEI interrupt Enabled.\r
+ * |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0\r
+ * | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT.\r
+ * | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1.\r
+ * |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1\r
+ * | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT.\r
+ * | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1.\r
+ * |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2\r
+ * | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT.\r
+ * | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1.\r
+ * |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3\r
+ * | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT.\r
+ * | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1.\r
+ * |[24] |HOLDCNT |Hold QEI_CNT Control\r
+ * | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into QEI_CNTHOLD\r
+ * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).\r
+ * | | |0 = No operation.\r
+ * | | |1 = QEI_CNT content is captured and stored in QEI_CNTHOLD.\r
+ * | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.\r
+ * |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit\r
+ * | | |If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX.\r
+ * | | |0 = The index signal latch QEI counter function Disabled.\r
+ * | | |1 = The index signal latch QEI counter function Enabled.\r
+ * |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit\r
+ * | | |When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF = 0).\r
+ * | | |0 = Reload function Disabled.\r
+ * | | |1 = QEI_CNT re-initialized by Index signal Enabled.\r
+ * |[28] |CMPEN |the Compare Function Enable Bit\r
+ * | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set.\r
+ * | | |0 = Compare function Disabled.\r
+ * | | |1 = Compare function Enabled.\r
+ * |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit\r
+ * | | |0 = QEI controller function Disabled.\r
+ * | | |1 = QEI controller function Enabled.\r
+ * @var QEI_T::STATUS\r
+ * Offset: 0x2C QEI Controller Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |IDXF |IDX Detected Flag\r
+ * | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\r
+ * | | |0 = No rising edge detected on signal CHX.\r
+ * | | |1 = A rising edge occurs on signal CHX.\r
+ * | | |Note: This bit is only cleared by writing 1 to it.\r
+ * |[1] |CMPF |Compare-match Flag\r
+ * | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).\r
+ * | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]).\r
+ * | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]).\r
+ * | | |Note: This bit is only cleared by writing 1 to it.\r
+ * |[2] |OVUNF |QEI Counter Overflow or Underflow Flag\r
+ * | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode\r
+ * | | |Similarly, the flag is set wile QEI counter underflow from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).\r
+ * | | |0 = No overflow or underflow occurs in QEI counter.\r
+ * | | |1 = QEI counter occurs counting overflow or underflow.\r
+ * | | |Note: This bit is only cleared by writing 1 to it.\r
+ * |[3] |DIRCHGF |Direction Change Flag\r
+ * | | |Flag is set by hardware while QEI counter counting direction is changed\r
+ * | | |Software can clear this bit by writing 1 to it.\r
+ * | | |0 = No change in QEI counter counting direction.\r
+ * | | |1 = QEI counter counting direction is changed.\r
+ * | | |Note: This bit is only cleared by writing 1 to it.\r
+ * |[8] |DIRF |QEI Counter Counting Direction Indication\r
+ * | | |0 = QEI Counter is in down-counting.\r
+ * | | |1 = QEI Counter is in up-counting.\r
+ * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.\r
+ */\r
+ __IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */\r
+ __IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */\r
+ __IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */\r
+ __IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */\r
+ __I uint32_t RESERVE0[1];\r
+ __IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */\r
+ __IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */\r
+ __I uint32_t RESERVE1[4];\r
+ __IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */\r
+\r
+} QEI_T;\r
+\r
+/**\r
+ @addtogroup QEI_CONST QEI Bit Field Definition\r
+ Constant Definitions for QEI Controller\r
+@{ */\r
+\r
+#define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */\r
+#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */\r
+\r
+#define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */\r
+#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */\r
+\r
+#define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */\r
+#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */\r
+\r
+#define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */\r
+#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */\r
+\r
+#define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */\r
+#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */\r
+\r
+#define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */\r
+#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */\r
+\r
+#define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */\r
+#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */\r
+\r
+#define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */\r
+#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */\r
+\r
+#define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */\r
+#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */\r
+\r
+#define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */\r
+#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */\r
+\r
+#define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */\r
+#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */\r
+\r
+#define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */\r
+#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */\r
+\r
+#define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */\r
+#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */\r
+\r
+#define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */\r
+#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */\r
+\r
+#define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */\r
+#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */\r
+\r
+#define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */\r
+#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */\r
+\r
+#define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */\r
+#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */\r
+\r
+#define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */\r
+#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */\r
+\r
+#define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */\r
+#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */\r
+\r
+#define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */\r
+#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */\r
+\r
+#define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */\r
+#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */\r
+\r
+#define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */\r
+#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */\r
+\r
+#define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */\r
+#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */\r
+\r
+#define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */\r
+#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */\r
+\r
+#define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */\r
+#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */\r
+\r
+#define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */\r
+#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */\r
+\r
+#define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */\r
+#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */\r
+\r
+#define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */\r
+#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */\r
+\r
+#define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */\r
+#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */\r
+\r
+#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */\r
+#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */\r
+\r
+#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */\r
+#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */\r
+\r
+#define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */\r
+#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */\r
+\r
+/**@}*/ /* QEI_CONST */\r
+/**@}*/ /* end of QEI register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __QEI_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file qspi_reg.h\r
+ * @version V1.00\r
+ * @brief QSPI register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __QSPI_REG_H__\r
+#define __QSPI_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Quad Serial Peripheral Interface Controller -------------------------*/\r
+/**\r
+ @addtogroup QSPI Quad Serial Peripheral Interface Controller(QSPI)\r
+ Memory Mapped Structure for QSPI Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var QSPI_T::CTL\r
+ * Offset: 0x00 QSPI Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SPIEN |QSPI Transfer Control Enable Bit\r
+ * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1\r
+ * | | |In Slave mode, this device is ready to receive data when this bit is set to 1.\r
+ * | | |0 = Transfer control Disabled.\r
+ * | | |1 = Transfer control Enabled.\r
+ * | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0.\r
+ * |[1] |RXNEG |Receive on Negative Edge\r
+ * | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock.\r
+ * | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock.\r
+ * |[2] |TXNEG |Transmit on Negative Edge\r
+ * | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock.\r
+ * | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock.\r
+ * |[3] |CLKPOL |Clock Polarity\r
+ * | | |0 = QSPI bus clock is idle low.\r
+ * | | |1 = QSPI bus clock is idle high.\r
+ * |[7:4] |SUSPITV |Suspend Interval (Master Only)\r
+ * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer\r
+ * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word\r
+ * | | |The default value is 0x3\r
+ * | | |The period of the suspend interval is obtained according to the following equation.\r
+ * | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle\r
+ * | | |Example:\r
+ * | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle.\r
+ * | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle.\r
+ * | | |.....\r
+ * | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle.\r
+ * | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle.\r
+ * |[12:8] |DWIDTH |Data Width\r
+ * | | |This field specifies how many bits can be transmitted / received in one transaction\r
+ * | | |The minimum bit length is 8 bits and can up to 32 bits.\r
+ * | | |DWIDTH = 0x08 .... 8 bits.\r
+ * | | |DWIDTH = 0x09 .... 9 bits.\r
+ * | | |.....\r
+ * | | |DWIDTH = 0x1F .... 31 bits.\r
+ * | | |DWIDTH = 0x00 .... 32 bits.\r
+ * | | |Note: For QSPI0~QSPI3, this bit field will decide the depth of TX/RX FIFO configuration in QSPI mode\r
+ * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in QSPI0~QSPI3.\r
+ * |[13] |LSB |Send LSB First\r
+ * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.\r
+ * | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX).\r
+ * |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit\r
+ * | | |This bit is used to select full-duplex or half-duplex for QSPI transfer\r
+ * | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.\r
+ * | | |0 = QSPI operates in full-duplex transfer.\r
+ * | | |1 = QSPI operates in half-duplex transfer.\r
+ * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)\r
+ * | | |This bit field is only available in Master mode\r
+ * | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status.\r
+ * | | |0 = Receive-only mode Disabled.\r
+ * | | |1 = Receive-only mode Enabled.\r
+ * |[16] |TWOBIT |2-bit Transfer Mode Enable Bit (Only Supported in QSPI0)\r
+ * | | |0 = 2-Bit Transfer mode Disabled.\r
+ * | | |1 = 2-Bit Transfer mode Enabled.\r
+ * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data\r
+ * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.\r
+ * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit\r
+ * | | |0 = QSPI unit transfer interrupt Disabled.\r
+ * | | |1 = QSPI unit transfer interrupt Enabled.\r
+ * |[18] |SLAVE |Slave Mode Control\r
+ * | | |0 = Master mode.\r
+ * | | |1 = Slave mode.\r
+ * |[19] |REORDER |Byte Reorder Function Enable Bit\r
+ * | | |0 = Byte Reorder function Disabled.\r
+ * | | |1 = Byte Reorder function Enabled\r
+ * | | |A byte suspend interval will be inserted among each byte\r
+ * | | |The period of the byte suspend interval depends on the setting of SUSPITV.\r
+ * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.\r
+ * |[20] |DATDIR |Data Port Direction Control\r
+ * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer\r
+ * | | |0 = QSPI data is input direction.\r
+ * | | |1 = QSPI data is output direction.\r
+ * |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in QSPI0)\r
+ * | | |0 = Dual I/O mode Disabled.\r
+ * | | |1 = Dual I/O mode Enabled.\r
+ * |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in QSPI0)\r
+ * | | |0 = Quad I/O mode Disabled.\r
+ * | | |1 = Quad I/O mode Enabled.\r
+ * @var QSPI_T::CLKDIV\r
+ * Offset: 0x04 QSPI Clock Divider Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[8:0] |DIVIDER |Clock Divider\r
+ * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master\r
+ * | | |The frequency is obtained according to the following equation.\r
+ * | | |where\r
+ * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\r
+ * @var QSPI_T::SSCTL\r
+ * Offset: 0x08 QSPI Slave Select Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SS |Slave Selection Control (Master Only)\r
+ * | | |If AUTOSS bit is cleared to 0,\r
+ * | | |0 = set the QSPIx_SS line to inactive state.\r
+ * | | |1 = set the QSPIx_SS line to active state.\r
+ * | | |If the AUTOSS bit is set to 1,\r
+ * | | |0 = Keep the QSPIx_SS line at inactive state.\r
+ * | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time\r
+ * | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]).\r
+ * |[2] |SSACTPOL |Slave Selection Active Polarity\r
+ * | | |This bit defines the active polarity of slave selection signal (QSPIx_SS).\r
+ * | | |0 = The slave selection signal QSPIx_SS is active low.\r
+ * | | |1 = The slave selection signal QSPIx_SS is active high.\r
+ * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)\r
+ * | | |0 = Automatic slave selection function Disabled\r
+ * | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]).\r
+ * | | |1 = Automatic slave selection function Enabled.\r
+ * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit (Only Supported in QSPI0)\r
+ * | | |Slave 3-wire mode is only available in QSPI0\r
+ * | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins.\r
+ * | | |0 = 4-wire bi-direction interface.\r
+ * | | |1 = 3-wire bi-direction interface.\r
+ * |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit (Only Supported in QSPI0)\r
+ * | | |0 = Slave mode time-out interrupt Disabled.\r
+ * | | |1 = Slave mode time-out interrupt Enabled.\r
+ * |[6] |SLVTORST |Slave Mode Time-out Reset Control (Only Supported in QSPI0)\r
+ * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.\r
+ * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.\r
+ * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit\r
+ * | | |0 = Slave mode bit count error interrupt Disabled.\r
+ * | | |1 = Slave mode bit count error interrupt Enabled.\r
+ * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit\r
+ * | | |0 = Slave mode TX under run interrupt Disabled.\r
+ * | | |1 = Slave mode TX under run interrupt Enabled.\r
+ * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit\r
+ * | | |0 = Slave select active interrupt Disabled.\r
+ * | | |1 = Slave select active interrupt Enabled.\r
+ * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit\r
+ * | | |0 = Slave select inactive interrupt Disabled.\r
+ * | | |1 = Slave select inactive interrupt Enabled.\r
+ * |[31:16] |SLVTOCNT |Slave Mode Time-out Period (Only Supported in QSPI0)\r
+ * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active\r
+ * | | |The clock source of the time-out counter is Slave peripheral clock\r
+ * | | |If the value is 0, it indicates the slave mode time-out function is disabled.\r
+ * @var QSPI_T::PDMACTL\r
+ * Offset: 0x0C QSPI PDMA Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |TXPDMAEN |Transmit PDMA Enable Bit\r
+ * | | |0 = Transmit PDMA function Disabled.\r
+ * | | |1 = Transmit PDMA function Enabled.\r
+ * | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function\r
+ * | | |User can enable TX PDMA function firstly or enable both functions simultaneously.\r
+ * |[1] |RXPDMAEN |Receive PDMA Enable Bit\r
+ * | | |0 = Receive PDMA function Disabled.\r
+ * | | |1 = Receive PDMA function Enabled.\r
+ * |[2] |PDMARST |PDMA Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0.\r
+ * @var QSPI_T::FIFOCTL\r
+ * Offset: 0x10 QSPI FIFO Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RXRST |Receive Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset receive FIFO pointer and receive circuit\r
+ * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1\r
+ * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1\r
+ * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.\r
+ * |[1] |TXRST |Transmit Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset transmit FIFO pointer and transmit circuit\r
+ * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1\r
+ * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1\r
+ * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.\r
+ * | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.\r
+ * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit\r
+ * | | |0 = RX FIFO threshold interrupt Disabled.\r
+ * | | |1 = RX FIFO threshold interrupt Enabled.\r
+ * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit\r
+ * | | |0 = TX FIFO threshold interrupt Disabled.\r
+ * | | |1 = TX FIFO threshold interrupt Enabled.\r
+ * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit\r
+ * | | |0 = Receive time-out interrupt Disabled.\r
+ * | | |1 = Receive time-out interrupt Enabled.\r
+ * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit\r
+ * | | |0 = Receive FIFO overrun interrupt Disabled.\r
+ * | | |1 = Receive FIFO overrun interrupt Enabled.\r
+ * |[6] |TXUFPOL |TX Underflow Data Polarity\r
+ * | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode.\r
+ * | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode.\r
+ * | | |Note:\r
+ * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\r
+ * | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward\r
+ * | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.\r
+ * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit\r
+ * | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1\r
+ * | | |This bit is used to enable the TX underflow interrupt.\r
+ * | | |0 = Slave TX underflow interrupt Disabled.\r
+ * | | |1 = Slave TX underflow interrupt Enabled.\r
+ * |[8] |RXFBCLR |Receive FIFO Buffer Clear\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear receive FIFO pointer\r
+ * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1\r
+ * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.\r
+ * | | |Note: The RX shift register will not be cleared.\r
+ * |[9] |TXFBCLR |Transmit FIFO Buffer Clear\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear transmit FIFO pointer\r
+ * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1\r
+ * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.\r
+ * | | |Note: The TX shift register will not be cleared.\r
+ * |[26:24] |RXTH |Receive FIFO Threshold\r
+ * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0\r
+ * | | |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length.\r
+ * |[30:28] |TXTH |Transmit FIFO Threshold\r
+ * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0\r
+ * | | |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length.\r
+ * @var QSPI_T::STATUS\r
+ * Offset: 0x14 QSPI Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BUSY |Busy Status (Read Only)\r
+ * | | |0 = QSPI controller is in idle state.\r
+ * | | |1 = QSPI controller is in busy state.\r
+ * | | |The following listing are the bus busy conditions:\r
+ * | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0.\r
+ * | | |b\r
+ * | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.\r
+ * | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1.\r
+ * | | |d.\r
+ * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active.\r
+ * | | |e.\r
+ * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.\r
+ * |[1] |UNITIF |Unit Transfer Interrupt Flag\r
+ * | | |0 = No transaction has been finished since this bit was cleared to 0.\r
+ * | | |1 = QSPI controller has finished one unit transfer.\r
+ * | | |Note: This bit will be cleared by writing 1 to it.\r
+ * |[2] |SSACTIF |Slave Select Active Interrupt Flag\r
+ * | | |0 = Slave select active interrupt was cleared or not occurred.\r
+ * | | |1 = Slave select active interrupt event occurred.\r
+ * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.\r
+ * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag\r
+ * | | |0 = Slave select inactive interrupt was cleared or not occurred.\r
+ * | | |1 = Slave select inactive interrupt event occurred.\r
+ * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.\r
+ * |[4] |SSLINE |Slave Select Line Bus Status (Read Only)\r
+ * | | |0 = The slave select line status is 0.\r
+ * | | |1 = The slave select line status is 1.\r
+ * | | |Note: This bit is only available in Slave mode\r
+ * | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.\r
+ * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Only Supported in QSPI0)\r
+ * | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started\r
+ * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.\r
+ * | | |0 = Slave time-out is not active.\r
+ * | | |1 = Slave time-out is active.\r
+ * | | |Note: This bit will be cleared by writing 1 to it.\r
+ * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag\r
+ * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\r
+ * | | |0 = No Slave mode bit count error event.\r
+ * | | |1 = Slave mode bit count error event occurs.\r
+ * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state\r
+ * | | |This bit will be cleared by writing 1 to it.\r
+ * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag\r
+ * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\r
+ * | | |0 = No Slave TX under run event.\r
+ * | | |1 = Slave TX under run event occurs.\r
+ * | | |Note: This bit will be cleared by writing 1 to it.\r
+ * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)\r
+ * | | |0 = Receive FIFO buffer is not empty.\r
+ * | | |1 = Receive FIFO buffer is empty.\r
+ * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)\r
+ * | | |0 = Receive FIFO buffer is not full.\r
+ * | | |1 = Receive FIFO buffer is full.\r
+ * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)\r
+ * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.\r
+ * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.\r
+ * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag\r
+ * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\r
+ * | | |0 = No FIFO is overrun.\r
+ * | | |1 = Receive FIFO is overrun.\r
+ * | | |Note: This bit will be cleared by writing 1 to it.\r
+ * |[12] |RXTOIF |Receive Time-out Interrupt Flag\r
+ * | | |0 = No receive FIFO time-out event.\r
+ * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode\r
+ * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.\r
+ * | | |Note: This bit will be cleared by writing 1 to it.\r
+ * |[15] |SPIENSTS |QSPI Enable Status (Read Only)\r
+ * | | |0 = The QSPI controller is disabled.\r
+ * | | |1 = The QSPI controller is enabled.\r
+ * | | |Note: The QSPI peripheral clock is asynchronous with the system clock\r
+ * | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.\r
+ * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)\r
+ * | | |0 = Transmit FIFO buffer is not empty.\r
+ * | | |1 = Transmit FIFO buffer is empty.\r
+ * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)\r
+ * | | |0 = Transmit FIFO buffer is not full.\r
+ * | | |1 = Transmit FIFO buffer is full.\r
+ * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)\r
+ * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.\r
+ * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.\r
+ * |[19] |TXUFIF |TX Underflow Interrupt Flag\r
+ * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\r
+ * | | |0 = No effect.\r
+ * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.\r
+ * | | |Note 1: This bit will be cleared by writing 1 to it.\r
+ * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.\r
+ * |[23] |TXRXRST |TX or RX Reset Status (Read Only)\r
+ * | | |0 = The reset function of TXRST or RXRST is done.\r
+ * | | |1 = Doing the reset function of TXRST or RXRST.\r
+ * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles\r
+ * | | |User can check the status of this bit to monitor the reset function is doing or done.\r
+ * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)\r
+ * | | |This bit field indicates the valid data count of receive FIFO buffer.\r
+ * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)\r
+ * | | |This bit field indicates the valid data count of transmit FIFO buffer.\r
+ * @var QSPI_T::TX\r
+ * Offset: 0x20 QSPI Data Transmit Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |TX |Data Transmit Register\r
+ * | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers\r
+ * | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode.\r
+ * | | |In QSPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.\r
+ * | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer.\r
+ * | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.\r
+ * @var QSPI_T::RX\r
+ * Offset: 0x30 QSPI Data Receive Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |RX |Data Receive Register (Read Only)\r
+ * | | |There are 8-level FIFO buffers in this controller.\r
+ * | | |The data receive register holds the data received from QSPI data input pin.\r
+ * | | |If the RXEMPTY (QSPIx_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.\r
+ */\r
+\r
+ __IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */\r
+ __IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */\r
+ __IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */\r
+ __IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */\r
+ __IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */\r
+ __IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */\r
+ __I uint32_t RESERVE0[2];\r
+ __O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */\r
+ __I uint32_t RESERVE1[3];\r
+ __I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */\r
+\r
+} QSPI_T;\r
+\r
+/**\r
+ @addtogroup QSPI_CONST QSPI Bit Field Definition\r
+ Constant Definitions for QSPI Controller\r
+@{ */\r
+\r
+#define QSPI_CTL_SPIEN_Pos (0) /*!< QSPI_T::CTL: SPIEN Position */\r
+#define QSPI_CTL_SPIEN_Msk (0x1ul << QSPI_CTL_SPIEN_Pos) /*!< QSPI_T::CTL: SPIEN Mask */\r
+\r
+#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */\r
+#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */\r
+\r
+#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */\r
+#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */\r
+\r
+#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */\r
+#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */\r
+\r
+#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */\r
+#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */\r
+\r
+#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */\r
+#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */\r
+\r
+#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */\r
+#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */\r
+\r
+#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */\r
+#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */\r
+\r
+#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */\r
+#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */\r
+\r
+#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */\r
+#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */\r
+\r
+#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */\r
+#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */\r
+\r
+#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */\r
+#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */\r
+\r
+#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */\r
+#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */\r
+\r
+#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */\r
+#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */\r
+\r
+#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */\r
+#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */\r
+\r
+#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */\r
+#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */\r
+\r
+#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */\r
+#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */\r
+\r
+#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */\r
+#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */\r
+\r
+#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */\r
+#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */\r
+\r
+#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */\r
+#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */\r
+\r
+#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */\r
+#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */\r
+\r
+#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */\r
+#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */\r
+\r
+#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */\r
+#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */\r
+\r
+#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */\r
+#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */\r
+\r
+#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */\r
+#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */\r
+\r
+#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */\r
+#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */\r
+\r
+#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */\r
+#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */\r
+\r
+#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */\r
+#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */\r
+\r
+#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */\r
+#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */\r
+\r
+#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */\r
+#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */\r
+\r
+#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */\r
+#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */\r
+\r
+#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */\r
+#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */\r
+\r
+#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */\r
+#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */\r
+\r
+#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */\r
+#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */\r
+\r
+#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */\r
+#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */\r
+\r
+#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */\r
+#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */\r
+\r
+#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */\r
+#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */\r
+\r
+#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */\r
+#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */\r
+\r
+#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */\r
+#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */\r
+\r
+#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */\r
+#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */\r
+\r
+#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */\r
+#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */\r
+\r
+#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */\r
+#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */\r
+\r
+#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */\r
+#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */\r
+\r
+#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */\r
+#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */\r
+\r
+#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */\r
+#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */\r
+\r
+#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */\r
+#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */\r
+\r
+#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */\r
+#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */\r
+\r
+#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */\r
+#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */\r
+\r
+#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */\r
+#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */\r
+\r
+#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */\r
+#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */\r
+\r
+#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */\r
+#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */\r
+\r
+#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */\r
+#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */\r
+\r
+#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */\r
+#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */\r
+\r
+#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */\r
+#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */\r
+\r
+#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */\r
+#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */\r
+\r
+#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */\r
+#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */\r
+\r
+#define QSPI_STATUS_SPIENSTS_Pos (15) /*!< QSPI_T::STATUS: SPIENSTS Position */\r
+#define QSPI_STATUS_SPIENSTS_Msk (0x1ul << QSPI_STATUS_SPIENSTS_Pos) /*!< QSPI_T::STATUS: SPIENSTS Mask */\r
+\r
+#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */\r
+#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */\r
+\r
+#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */\r
+#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */\r
+\r
+#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */\r
+#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */\r
+\r
+#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */\r
+#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */\r
+\r
+#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */\r
+#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */\r
+\r
+#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */\r
+#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */\r
+\r
+#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */\r
+#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */\r
+\r
+#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */\r
+#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */\r
+\r
+#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */\r
+#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */\r
+\r
+/**@}*/ /* QSPI_CONST */\r
+/**@}*/ /* end of QSPI register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __QSPI_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file rtc_reg.h\r
+ * @version V1.00\r
+ * @brief RTC register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __RTC_REG_H__\r
+#define __RTC_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Real Time Clock Controller -------------------------*/\r
+/**\r
+ @addtogroup RTC Real Time Clock Controller(RTC)\r
+ Memory Mapped Structure for RTC Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var RTC_T::INIT\r
+ * Offset: 0x00 RTC Initiation Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |INIT_ACTIVE|RTC Active Status (Read Only)\r
+ * | | |0 = RTC is at reset state.\r
+ * | | |1 = RTC is at normal active state.\r
+ * |[31:1] |INIT |RTC Initiation\r
+ * | | |When RTC block is powered on, RTC is at reset state\r
+ * | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state\r
+ * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\r
+ * | | |The INIT is a write-only field and read value will be always 0.\r
+ * @var RTC_T::RWEN\r
+ * Offset: 0x04 RTC Access Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |RWEN |RTC Register Access Enable Password (Write Only)\r
+ * | | |Writing 0xA965 to this field will enable RTC accessible period keeps 1024 RTC clocks.\r
+ * | | |Note: Writing other value will clear RWENF and disable RTC register access function immediately.\r
+ * |[16] |RWENF |RTC Register Access Enable Flag (Read Only)\r
+ * | | |0 = RTC register read/write Disabled.\r
+ * | | |1 = RTC register read/write Enabled.\r
+ * | | |This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clocks expired.\r
+ * | | |Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also.\r
+ * |[24] |RTCBUSY |RTC Write Busy Flag\r
+ * | | |This bit indicates RTC registers are busy or not. RTC register R/W is invalid during RTCBUSY.\r
+ * | | |0: RTC registers are readable and writable.\r
+ * | | |1: RTC registers can't R/W, RTC under Busy Status.\r
+ * | | |Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles or PCLKRTC switch on first few cycles.\r
+ * | | |Note: The bit reflect RWENF (RWENF = 0 when RTCBUSY).\r
+ * @var RTC_T::FREQADJ\r
+ * Offset: 0x08 RTC Frequency Compensation Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[21:0] |FREQADJ |Frequency Compensation Register\r
+ * | | |User must to get actual LXT frequency for RTC application.\r
+ * | | |FCR = 0x200000 * (32768 / LXT frequency).\r
+ * | | |Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0.\r
+ * | | |If set RTCSEL (CLK_CLKSEL3[8]) to 1, RTC clock source is from LIRC.\r
+ * | | |User can set FREQADJ to execute LIRC compensation for RTC counter more accurate and the formula as below,\r
+ * | | |FCR = 0x80000 * (32768 / LIRC frequency).\r
+ * @var RTC_T::TIME\r
+ * Offset: 0x0C RTC Time Loading Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |SEC |1-Sec Time Digit (0~9)\r
+ * |[6:4] |TENSEC |10-Sec Time Digit (0~5)\r
+ * |[11:8] |MIN |1-Min Time Digit (0~9)\r
+ * |[14:12] |TENMIN |10-Min Time Digit (0~5)\r
+ * |[19:16] |HR |1-Hour Time Digit (0~9)\r
+ * |[21:20] |TENHR |10-Hour Time Digit (0~2)\r
+ * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)\r
+ * |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F)\r
+ * @var RTC_T::CAL\r
+ * Offset: 0x10 RTC Calendar Loading Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |DAY |1-Day Calendar Digit (0~9)\r
+ * |[5:4] |TENDAY |10-Day Calendar Digit (0~3)\r
+ * |[11:8] |MON |1-Month Calendar Digit (0~9)\r
+ * |[12] |TENMON |10-Month Calendar Digit (0~1)\r
+ * |[19:16] |YEAR |1-Year Calendar Digit (0~9)\r
+ * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)\r
+ * @var RTC_T::CLKFMT\r
+ * Offset: 0x14 RTC Time Scale Selection Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |24HEN |24-hour / 12-hour Time Scale Selection\r
+ * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale\r
+ * | | |0 = 12-hour time scale with AM and PM indication selected.\r
+ * | | |1 = 24-hour time scale selected.\r
+ * |[8] |HZCNTEN |Sub-second Counter Enable Bit\r
+ * | | |0 = HZCNT disabled in RTC_TIME and RTC_TALM.\r
+ * | | |1 = HZCNT enabled in RTC_TIME and RTC_TALM .\r
+ * @var RTC_T::WEEKDAY\r
+ * Offset: 0x18 RTC Day of the Week Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |WEEKDAY |Day of the Week Register\r
+ * | | |000 = Sunday.\r
+ * | | |001 = Monday.\r
+ * | | |010 = Tuesday.\r
+ * | | |011 = Wednesday.\r
+ * | | |100 = Thursday.\r
+ * | | |101 = Friday.\r
+ * | | |110 = Saturday.\r
+ * | | |111 = Reserved.\r
+ * @var RTC_T::TALM\r
+ * Offset: 0x1C RTC Time Alarm Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)\r
+ * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)\r
+ * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)\r
+ * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)\r
+ * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)\r
+ * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)\r
+ * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)\r
+ * |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F)\r
+ * @var RTC_T::CALM\r
+ * Offset: 0x20 RTC Calendar Alarm Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)\r
+ * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)\r
+ * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)\r
+ * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)\r
+ * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)\r
+ * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)\r
+ * @var RTC_T::LEAPYEAR\r
+ * Offset: 0x24 RTC Leap Year Indicator Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)\r
+ * | | |0 = This year is not a leap year.\r
+ * | | |1 = This year is leap year.\r
+ * @var RTC_T::INTEN\r
+ * Offset: 0x28 RTC Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ALMIEN |Alarm Interrupt Enable Bit\r
+ * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.\r
+ * | | |0 = RTC Alarm interrupt Disabled.\r
+ * | | |1 = RTC Alarm interrupt Enabled.\r
+ * |[1] |TICKIEN |Time Tick Interrupt Enable Bit\r
+ * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.\r
+ * | | |0 = RTC Time Tick interrupt Disabled.\r
+ * | | |1 = RTC Time Tick interrupt Enabled.\r
+ * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit\r
+ * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.\r
+ * | | |0 = Tamper 0 interrupt Disabled.\r
+ * | | |1 = Tamper 0 interrupt Enabled.\r
+ * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit\r
+ * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated.\r
+ * | | |0 = Tamper 1 or Pair 0 interrupt Disabled.\r
+ * | | |1 = Tamper 1 or Pair 0 interrupt Enabled.\r
+ * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit\r
+ * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated.\r
+ * | | |0 = Tamper 2 interrupt Disabled.\r
+ * | | |1 = Tamper 2 interrupt Enabled.\r
+ * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit\r
+ * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated.\r
+ * | | |0 = Tamper 3 or Pair 1 interrupt Disabled.\r
+ * | | |1 = Tamper 3 or Pair 1 interrupt Enabled.\r
+ * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit\r
+ * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated.\r
+ * | | |0 = Tamper 4 interrupt Disabled.\r
+ * | | |1 = Tamper 4 interrupt Enabled.\r
+ * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit\r
+ * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated.\r
+ * | | |0 = Tamper 5 or Pair 2 interrupt Disabled.\r
+ * | | |1 = Tamper 5 or Pair 2 interrupt Enabled.\r
+ * |[24] |CLKFIEN |LXT Clock Frequency Monitor Fail Interrupt Enable Bit\r
+ * | | |0 = LXT Frequency Fail interrupt Disabled.\r
+ * | | |1 = LXT Frequency Fail interrupt Enabled.\r
+ * |[25] |CLKSPIEN |LXT Clock Frequency Monitor Stop Interrupt Enable Bit\r
+ * | | |0 = LXT Frequency Stop interrupt Disabled.\r
+ * | | |1 = LXT Frequency Stop interrupt Enabled.\r
+ * @var RTC_T::INTSTS\r
+ * Offset: 0x2C RTC Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ALMIF |RTC Alarm Interrupt Flag\r
+ * | | |0 = Alarm condition is not matched.\r
+ * | | |1 = Alarm condition is matched.\r
+ * | | |Note: Write 1 to clear this bit.\r
+ * |[1] |TICKIF |RTC Time Tick Interrupt Flag\r
+ * | | |0 = Tick condition does not occur.\r
+ * | | |1 = Tick condition occur.\r
+ * | | |Note: Write 1 to clear this bit.\r
+ * |[8] |TAMP0IF |Tamper 0 Interrupt Flag\r
+ * | | |0 = No Tamper 0 interrupt flag is generated.\r
+ * | | |1 = Tamper 0 interrupt flag is generated.\r
+ * | | |Note1: Write 1 to clear this bit.\r
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.\r
+ * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag\r
+ * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated.\r
+ * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated.\r
+ * | | |Note1: Write 1 to clear this bit.\r
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.\r
+ * |[10] |TAMP2IF |Tamper 2 Interrupt Flag\r
+ * | | |0 = No Tamper 2 interrupt flag is generated.\r
+ * | | |1 = Tamper 2 interrupt flag is generated.\r
+ * | | |Note1: Write 1 to clear this bit.\r
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.\r
+ * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag\r
+ * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated.\r
+ * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated.\r
+ * | | |Note1: Write 1 to clear this bit.\r
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.\r
+ * |[12] |TAMP4IF |Tamper 4 Interrupt Flag\r
+ * | | |0 = No Tamper 4 interrupt flag is generated.\r
+ * | | |1 = Tamper 4 interrupt flag is generated.\r
+ * | | |Note1: Write 1 to clear this bit.\r
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.\r
+ * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag\r
+ * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated.\r
+ * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated.\r
+ * | | |Note1: Write 1 to clear this bit.\r
+ * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.\r
+ * |[24] |CLKFIF |LXT Clock Frequency Monitor Fail Interrupt Flag\r
+ * | | |0 = LXT frequency is normal.\r
+ * | | |1 = LXT frequency is abnormal.\r
+ * | | |Note1: Write 1 to clear the bit to 0.\r
+ * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear.\r
+ * |[25] |CLKSPIF |LXT Clock Frequency Monitor Stop Interrupt Flag\r
+ * | | |0 = LXT frequency is normal.\r
+ * | | |1 = LXT frequency is almost stop ..\r
+ * | | |Note1: Write 1 to clear the bit to 0.\r
+ * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear.\r
+ * @var RTC_T::TICK\r
+ * Offset: 0x30 RTC Time Tick Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |TICK |Time Tick Register\r
+ * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.\r
+ * | | |000 = Time tick is 1 second.\r
+ * | | |001 = Time tick is 1/2 second.\r
+ * | | |010 = Time tick is 1/4 second.\r
+ * | | |011 = Time tick is 1/8 second.\r
+ * | | |100 = Time tick is 1/16 second.\r
+ * | | |101 = Time tick is 1/32 second.\r
+ * | | |110 = Time tick is 1/64 second.\r
+ * | | |111 = Time tick is 1/128 second.\r
+ * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.\r
+ * @var RTC_T::TAMSK\r
+ * Offset: 0x34 RTC Time Alarm Mask Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)\r
+ * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)\r
+ * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)\r
+ * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)\r
+ * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)\r
+ * | | |Note: MHR function is only for 24-hour time scale mode.\r
+ * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)\r
+ * | | |Note: MTENHR function is only for 24-hour time scale mode.\r
+ * @var RTC_T::CAMSK\r
+ * Offset: 0x38 RTC Calendar Alarm Mask Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)\r
+ * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)\r
+ * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)\r
+ * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)\r
+ * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)\r
+ * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)\r
+ * @var RTC_T::SPRCTL\r
+ * Offset: 0x3C RTC Spare Functional Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2] |SPRRWEN |Spare Register Enable Bit\r
+ * | | |0 = Spare register is Disabled.\r
+ * | | |1 = Spare register is Enabled.\r
+ * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.\r
+ * |[5] |SPRCSTS |SPR Clear Flag\r
+ * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected.\r
+ * | | |0 = Spare register content is not cleared.\r
+ * | | |1 = Spare register content is cleared.\r
+ * | | |Writes 1 to clear this bit.\r
+ * | | |Note: This bit keep 1 when RTC_INTSTS[13:8] or RTC_INTSTS[25:24] are not equal zero.\r
+ * |[16] |LXTFCLR |LXT Clock Monitor Fail/Stop to Clear Spare Enable Bit\r
+ * | | |0 = LXT monitor Fail/Stop to clear Spare register content is Disabled..\r
+ * | | |1 = LXT monitor Fail/Stop to clear Spare register content is Enabled.\r
+ * @var RTC_T::SPR[20]\r
+ * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SPARE |Spare Register\r
+ * | | |This field is used to store back-up information defined by user.\r
+ * | | |This field will be cleared by hardware automatically once a tamper pin event is detected.\r
+ * | | |Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.\r
+ * @var RTC_T::LXTCTL\r
+ * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |LIRC32KEN |LIRC 32K Source Enable Bit\r
+ * | | |0 = LIRC32K Disabled.\r
+ * | | |1 = LIRC32K.Enabled.\r
+ * |[3:1] |GAIN |Oscillator Gain Option\r
+ * | | |User can select oscillator gain according to crystal external loading and operating temperature range\r
+ * | | |The larger gain value corresponding to stronger driving capability and higher power consumption.\r
+ * | | |000 = L0 mode.\r
+ * | | |001 = L1 mode.\r
+ * | | |010 = L2 mode.\r
+ * | | |011 = L3 mode.\r
+ * | | |100 = L4 mode.\r
+ * | | |101 = L5 mode.\r
+ * | | |110 = L6 mode.\r
+ * | | |111 = L7 mode (Default).\r
+ * |[7] |C32KS |Clock 32K Source Selection:\r
+ * | | |0 = Internal 32K clock is from 32K crystal .\r
+ * | | |1 = Internal 32K clock is from LIRC32K.\r
+ * @var RTC_T::GPIOCTL0\r
+ * Offset: 0x104 RTC GPIO Control 0 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |OPMODE0 |IO Operation Mode\r
+ * | | |00 = PF.0 is input only mode, without pull-up resistor.\r
+ * | | |01 = PF.0 is output push pull mode.\r
+ * | | |10 = PF.0 is open drain mode.\r
+ * | | |11 = PF.0 is quasi-bidirectional mode with internal pull up.\r
+ * |[2] |DOUT0 |IO Output Data\r
+ * | | |0 = PF.0 output low.\r
+ * | | |1 = PF.0 output high.\r
+ * |[3] |CTLSEL0 |IO Pin State Backup Selection\r
+ * | | |When low speed 32 kHz oscillator is disabled, PF.0 pin (X32KO pin) can be used as GPIO function\r
+ * | | |User can program CTLSEL0 to decide PF.0 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\r
+ * | | |0 = PF.0 pin I/O function is controlled by GPIO module.\r
+ * | | |Hardware auto becomes CTLSEL0 = 1 when system power is turned off.\r
+ * | | |1 = PF.0 pin I/O function is controlled by VBAT power domain.\r
+ * | | |PF.0 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1.\r
+ * | | |Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.\r
+ * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable Bit\r
+ * | | |Determine PF.0 I/O pull-up or pull-down.\r
+ * | | |00 = PF.0 pull-up and pull-up disable.\r
+ * | | |01 = PF.0 pull-down enable.\r
+ * | | |10 = PF.0 pull-up enable.\r
+ * | | |11 = PF.0 pull-up and pull-up disable.\r
+ * | | |Note:\r
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.\r
+ * | | |The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode.\r
+ * | | |The independent pull-down control register only valid when OPMODE0 set as input tri-state mode.\r
+ * |[9:8] |OPMODE1 |IO Operation Mode\r
+ * | | |00 = PF.1 is input only mode, without pull-up resistor.\r
+ * | | |01 = PF.1 is output push pull mode.\r
+ * | | |10 = PF.1 is open drain mode.\r
+ * | | |11 = PF.1 is quasi-bidirectional mode with internal pull up.\r
+ * |[10] |DOUT1 |IO Output Data\r
+ * | | |0 = PF.1 output low.\r
+ * | | |1 = PF.1 output high.\r
+ * |[11] |CTLSEL1 |IO Pin State Backup Selection\r
+ * | | |When low speed 32 kHz oscillator is disabled, PF.1 pin (X32KI pin) can be used as GPIO function\r
+ * | | |User can program CTLSEL1 to decide PF.1 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\r
+ * | | |0 = PF.1 pin I/O function is controlled by GPIO module.\r
+ * | | |Hardware auto becomes CTLSEL1 = 1 when system power is turned off.\r
+ * | | |1 = PF.1 pin I/O function is controlled by VBAT power domain.\r
+ * | | |PF.1 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1.\r
+ * | | |Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.\r
+ * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable Bit\r
+ * | | |Determine PF.1 I/O pull-up or pull-down.\r
+ * | | |00 = PF.1 pull-up and pull-up disable.\r
+ * | | |01 = PF.1 pull-down enable.\r
+ * | | |10 = PF.1 pull-up enable.\r
+ * | | |11 = PF.1 pull-up and pull-up disable.\r
+ * | | |Note:\r
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.\r
+ * | | |The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode.\r
+ * | | |The independent pull-down control register only valid when OPMODE1 set as input tri-state mode.\r
+ * |[17:16] |OPMODE2 |IO Operation Mode\r
+ * | | |00 = PF.2 is input only mode, without pull-up resistor.\r
+ * | | |01 = PF.2 is output push pull mode.\r
+ * | | |10 = PF.2 is open drain mode.\r
+ * | | |11 = PF.2 is quasi-bidirectional mode with internal pull up.\r
+ * |[18] |DOUT2 |IO Output Data\r
+ * | | |0 = PF.2 output low.\r
+ * | | |1 = PF.2 output high.\r
+ * |[19] |CTLSEL2 |IO Pin State Backup Selection\r
+ * | | |When TAMP0EN is disabled, PF.2 pin (TAMPER0 pin) can be used as GPIO function\r
+ * | | |User can program CTLSEL2 to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\r
+ * | | |0 = PF.2 pin I/O function is controlled by GPIO module.\r
+ * | | |Hardware auto becomes CTLSEL2 = 1 when system power is turned off.\r
+ * | | |1 = PF.2 pin I/O function is controlled by VBAT power domain.\r
+ * | | |PF.2 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1.\r
+ * | | |Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.\r
+ * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable Bit\r
+ * | | |Determine PF.2 I/O pull-up or pull-down.\r
+ * | | |00 = PF.2 pull-up and pull-up disable.\r
+ * | | |01 = PF.2 pull-down enable.\r
+ * | | |10 = PF.2 pull-up enable.\r
+ * | | |11 = PF.2 pull-up and pull-up disable.\r
+ * | | |Note1:\r
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.\r
+ * | | |The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode.\r
+ * | | |The independent pull-down control register only valid when OPMODE2 set as input tri-state mode.\r
+ * |[25:24] |OPMODE3 |IO Operation Mode\r
+ * | | |00 = PF.7 is input only mode, without pull-up resistor.\r
+ * | | |01 = PF.7 is output push pull mode.\r
+ * | | |10 = PF.7 is open drain mode.\r
+ * | | |11 = PF.7 is quasi-bidirectional mode with with internal pull up.\r
+ * |[26] |DOUT3 |IO Output Data\r
+ * | | |0 = PF.7 output low.\r
+ * | | |1 = PF.7 output high.\r
+ * |[27] |CTLSEL3 |IO Pin State Backup Selection\r
+ * | | |When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function\r
+ * | | |User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\r
+ * | | |0 = PF.7 pin I/O function is controlled by GPIO module.\r
+ * | | |Hardware auto becomes CTLSEL3 = 1 when system power is turned off.\r
+ * | | |1 = PF.7 pin I/O function is controlled by VBAT power domain.\r
+ * | | |PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1.\r
+ * | | |Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.\r
+ * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable Bit\r
+ * | | |Determine PF.7 I/O pull-up or pull-down.\r
+ * | | |00 = PF.7 pull-up and pull-down disable.\r
+ * | | |01 = PF.7 pull-down enable.\r
+ * | | |10 = PF.7 pull-up enable.\r
+ * | | |11 = PF.7 pull-up and pull-down disable.\r
+ * | | |Note:\r
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.\r
+ * | | |The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode.\r
+ * | | |The independent pull-down control register only valid when OPMODE3 set as input tri-state mode.\r
+ * @var RTC_T::GPIOCTL1\r
+ * Offset: 0x108 RTC GPIO Control 1 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |OPMODE4 |IO Operation Mode\r
+ * | | |00 = PF.8 is input only mode, without pull-up resistor.\r
+ * | | |01 = PF.8 is output push pull mode.\r
+ * | | |10 = PF.8 is open drain mode.\r
+ * | | |11 = PF.8 is quasi-bidirectional mode with with internal pull up.\r
+ * |[2] |DOUT4 |IO Output Data\r
+ * | | |0 = PF.8 output low.\r
+ * | | |1 = PF.8 output high.\r
+ * |[3] |CTLSEL4 |IO Pin State Backup Selection\r
+ * | | |When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function\r
+ * | | |User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.\r
+ * | | |0 = PF.8 pin I/O function is controlled by GPIO module.\r
+ * | | |Hardware auto becomes CTLSEL4 = 1 when system power is turned off.\r
+ * | | |1 = PF.8 pin I/O function is controlled by VBAT power domain.\r
+ * | | |PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1.\r
+ * | | |Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.\r
+ * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable Bit\r
+ * | | |Determine PF.8 I/O pull-up or pull-down.\r
+ * | | |00 = PF.8 pull-up and pull-down disable.\r
+ * | | |01 = PF.8 pull-down enable.\r
+ * | | |10 = PF.8 pull-up enable.\r
+ * | | |11 = PF.8 pull-up and pull-down disable.\r
+ * | | |Note:\r
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.\r
+ * | | |The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode.\r
+ * | | |The independent pull-down control register only valid when OPMODE4 set as input tri-state mode.\r
+ * |[9:8] |OPMODE5 |IO Operation Mode\r
+ * | | |00 = PF.9 is input only mode, without pull-up resistor.\r
+ * | | |01 = PF.9 is output push pull mode.\r
+ * | | |10 = PF.9 is open drain mode.\r
+ * | | |11 = PF.9 is quasi-bidirectional mode with with internal pull up.\r
+ * |[10] |DOUT5 |IO Output Data\r
+ * | | |0 = PF.9 output low.\r
+ * | | |1 = PF.9 output high.\r
+ * |[11] |CTLSEL5 |IO Pin State Backup Selection\r
+ * | | |When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function\r
+ * | | |User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.\r
+ * | | |0 = PF.9 pin I/O function is controlled by GPIO module.\r
+ * | | |Hardware auto becomes CTLSEL5 = 1 when system power is turned off.\r
+ * | | |1 = PF.9 pin I/O function is controlled by VBAT power domain.\r
+ * | | |PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1.\r
+ * | | |Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.\r
+ * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable Bit\r
+ * | | |Determine PF.9 I/O pull-up or pull-down.\r
+ * | | |00 = PF.9 pull-up and pull-down disable.\r
+ * | | |01 = PF.9 pull-down enable.\r
+ * | | |10 = PF.9 pull-up enable.\r
+ * | | |11 = PF.9 pull-up and pull-down disable.\r
+ * | | |.Note:\r
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.\r
+ * | | |The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode.\r
+ * | | |The independent pull-down control register only valid when OPMODE5 set as input tri-state mode.\r
+ * |[17:16] |OPMODE6 |IO Operation Mode\r
+ * | | |00 = PF.10 is input only mode, without pull-up resistor.\r
+ * | | |01 = PF.10 is output push pull mode.\r
+ * | | |10 = PF.10 is open drain mode.\r
+ * | | |11 = PF.10 is quasi-bidirectional mode with with internal pull up.\r
+ * |[18] |DOUT6 |IO Output Data\r
+ * | | |0 = PF.10 output low.\r
+ * | | |1 = PF.10 output high.\r
+ * |[19] |CTLSEL6 |IO Pin State Backup Selection\r
+ * | | |When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function\r
+ * | | |User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.\r
+ * | | |0 = PF.10 pin I/O function is controlled by GPIO module.\r
+ * | | |Hardware auto becomes CTLSEL6 = 1 when system power is turned off.\r
+ * | | |1 = PF.10 pin I/O function is controlled by VBAT power domain.\r
+ * | | |PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1.\r
+ * | | |Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.\r
+ * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable Bit\r
+ * | | |Determine PF.10 I/O pull-up or pull-down.\r
+ * | | |00 = PF.10 pull-up and pull-down disable.\r
+ * | | |01 = PF.10 pull-down enable.\r
+ * | | |10 = PF.10 pull-up enable.\r
+ * | | |11 = PF.10 pull-up and pull-down disable.\r
+ * | | |Note:\r
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.\r
+ * | | |The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode.\r
+ * | | |The independent pull-down control register only valid when OPMODE6 set as input tri-state mode.\r
+ * |[25:24] |OPMODE7 |IO Operation Mode\r
+ * | | |00 = PF.11 is input only mode, without pull-up resistor.\r
+ * | | |01 = PF.11 is output push pull mode.\r
+ * | | |10 = PF.11 is open drain mode.\r
+ * | | |11 = PF.11 is quasi-bidirectional mode with with internal pull up.\r
+ * |[26] |DOUT7 |IO Output Data\r
+ * | | |0 = PF.11 output low.\r
+ * | | |1 = PF.11 output high.\r
+ * |[27] |CTLSEL7 |IO Pin State Backup Selection\r
+ * | | |When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function\r
+ * | | |User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.\r
+ * | | |0 = PF.11 pin I/O function is controlled by GPIO module.\r
+ * | | |Hardware auto becomes CTLSEL7 = 1 when system power is turned off.\r
+ * | | |1 = PF.11 pin I/O function is controlled by VBAT power domain.\r
+ * | | |PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1.\r
+ * | | |Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.\r
+ * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable Bit\r
+ * | | |Determine PF.11 I/O pull-up or pull-down.\r
+ * | | |00 = PF.11 pull-up and pull-down disable.\r
+ * | | |01 = PF.11 pull-down enable.\r
+ * | | |10 = PF.11 pull-up enable.\r
+ * | | |11 = PF.11 pull-up and pull-down disable.\r
+ * | | |Note:\r
+ * | | |Basically, the pull-up control and pull-down control has following behavior limitation.\r
+ * | | |The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode.\r
+ * | | |The independent pull-down control register only valid when OPMODE7 set as input tri-state mode.\r
+ * @var RTC_T::DSTCTL\r
+ * Offset: 0x110 RTC Daylight Saving Time Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ADDHR |Add 1 Hour\r
+ * | | |0 = No effect.\r
+ * | | |1 = Indicates RTC hour digit has been added one hour for summer time change.\r
+ * |[1] |SUBHR |Subtract 1 Hour\r
+ * | | |0 = No effect.\r
+ * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change.\r
+ * |[2] |DSBAK |Daylight Saving Back\r
+ * | | |0= Daylight Saving Change is not performed.\r
+ * | | |1= Daylight Saving Change is performed.\r
+ * @var RTC_T::TAMPCTL\r
+ * Offset: 0x120 RTC Tamper Pin Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select\r
+ * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.\r
+ * | | |0 = Tamper input is from Tamper 2.\r
+ * | | |1 = Tamper input is from Tamper 0.\r
+ * | | |Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set\r
+ * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select\r
+ * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.\r
+ * | | |0 = Tamper input is from Tamper 4.\r
+ * | | |1 = Tamper input is from Tamper 0.\r
+ * | | |Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set\r
+ * |[3:2] |DYNSRC |Dynamic Reference Pattern\r
+ * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode.\r
+ * | | |00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out.\r
+ * | | |01 = The new reference pattern is repeated previous random value when the reference pattern run out.\r
+ * | | |11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out.\r
+ * | | |Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set.\r
+ * |[4] |SEEDRLD |Reload New Seed for PRNG Engine\r
+ * | | |Setting this bit, the tamper configuration will be reload.\r
+ * | | |0 = Generating key based on the current seed.\r
+ * | | |1 = Reload new seed.\r
+ * | | |Note: Before set this bit, the tamper configuration should be set to complete.\r
+ * |[7:5] |DYNRATE |Dynamic Change Rate\r
+ * | | |This item is choice the dynamic tamper output change rate.\r
+ * | | |000 = 2^10 * RTC_CLK.\r
+ * | | |001 = 2^11 * RTC_CLK.\r
+ * | | |010 = 2^12 * RTC_CLK.\r
+ * | | |011 = 2^13 * RTC_CLK.\r
+ * | | |100 = 2^14 * RTC_CLK.\r
+ * | | |101 = 2^15 * RTC_CLK.\r
+ * | | |110 = 2^16 * RTC_CLK.\r
+ * | | |111 = 2^17 * RTC_CLK.\r
+ * | | |Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload chage rate immediately.\r
+ * |[8] |TAMP0EN |Tamper0 Detect Enable Bit\r
+ * | | |0 = Tamper 0 detect Disabled.\r
+ * | | |1 = Tamper 0 detect Enabled.\r
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.\r
+ * |[9] |TAMP0LV |Tamper 0 Level\r
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.\r
+ * | | |0 = Detect voltage level is low.\r
+ * | | |1 = Detect voltage level is high.\r
+ * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit\r
+ * | | |0 = Tamper 0 de-bounce Disabled.\r
+ * | | |1 = Tamper 0 de-bounce Enabled.\r
+ * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit\r
+ * | | |0 = Tamper 1 detect Disabled.\r
+ * | | |1 = Tamper 1 detect Enabled.\r
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.\r
+ * |[13] |TAMP1LV |Tamper 1 Level\r
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.\r
+ * | | |0 = Detect voltage level is low.\r
+ * | | |1 = Detect voltage level is high.\r
+ * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit\r
+ * | | |0 = Tamper 1 de-bounce Disabled.\r
+ * | | |1 = Tamper 1 de-bounce Enabled.\r
+ * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit\r
+ * | | |0 = Static detect.\r
+ * | | |1 = Dynamic detect.\r
+ * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit\r
+ * | | |0 = Tamper 2 detect Disabled.\r
+ * | | |1 = Tamper 2 detect Enabled.\r
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.\r
+ * |[17] |TAMP2LV |Tamper 2 Level\r
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.\r
+ * | | |0 = Detect voltage level is low.\r
+ * | | |1 = Detect voltage level is high.\r
+ * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit\r
+ * | | |0 = Tamper 2 de-bounce Disabled.\r
+ * | | |1 = Tamper 2 de-bounce Enabled.\r
+ * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit\r
+ * | | |0 = Tamper 3 detect Disabled.\r
+ * | | |1 = Tamper 3 detect Enabled.\r
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.\r
+ * |[21] |TAMP3LV |Tamper 3 Level\r
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.\r
+ * | | |0 = Detect voltage level is low.\r
+ * | | |1 = Detect voltage level is high.\r
+ * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit\r
+ * | | |0 = Tamper 3 de-bounce Disabled.\r
+ * | | |1 = Tamper 3 de-bounce Enabled.\r
+ * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit\r
+ * | | |0 = Static detect.\r
+ * | | |1 = Dynamic detect.\r
+ * |[24] |TAMP4EN |Tamper4 Detect Enable Bit\r
+ * | | |0 = Tamper 4 detect Disabled.\r
+ * | | |1 = Tamper 4 detect Enabled.\r
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.\r
+ * |[25] |TAMP4LV |Tamper 4 Level\r
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.\r
+ * | | |0 = Detect voltage level is low.\r
+ * | | |1 = Detect voltage level is high.\r
+ * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit\r
+ * | | |0 = Tamper 4 de-bounce Disabled.\r
+ * | | |1 = Tamper 4 de-bounce Enabled.\r
+ * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit\r
+ * | | |0 = Tamper 5 detect Disabled.\r
+ * | | |1 = Tamper 5 detect Enabled.\r
+ * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.\r
+ * |[29] |TAMP5LV |Tamper 5 Level\r
+ * | | |This bit depend on level attribute of tamper pin for static tamper detection.\r
+ * | | |0 = Detect voltage level is low.\r
+ * | | |1 = Detect voltage level is high.\r
+ * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit\r
+ * | | |0 = Tamper 5 de-bounce Disabled.\r
+ * | | |1 = Tamper 5 de-bounce Enabled.\r
+ * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit\r
+ * | | |0 = Static detect.\r
+ * | | |1 = Dynamic detect.\r
+ * @var RTC_T::TAMPSEED\r
+ * Offset: 0x128 RTC Tamper Dynamic Seed Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |SEED |Seed Value\r
+ * @var RTC_T::TAMPTIME\r
+ * Offset: 0x130 RTC Tamper Time Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9)\r
+ * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5)\r
+ * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9)\r
+ * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5)\r
+ * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9)\r
+ * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) Note: 24-hour time scale only .\r
+ * |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F)\r
+ * @var RTC_T::TAMPCAL\r
+ * Offset: 0x134 RTC Tamper Calendar Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9)\r
+ * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3)\r
+ * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9)\r
+ * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1)\r
+ * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9)\r
+ * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9)\r
+ * @var RTC_T::CLKDCTL\r
+ * Offset: 0x140 Clock Fail Detector Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |LXTFDEN |LXT Clock Fail/Stop Detector Enable Bit\r
+ * | | |0 = LXT clock fail/stop detector Disabled.\r
+ * | | |1 = LXT clock fail/stop detector Enabled.\r
+ * | | |Note:\r
+ * |[1] |LXTFSW |LXT Clock Fail Detector Switch LIRC32K Enable Bit\r
+ * | | |0 = LXT Clock Fail Detector Switch LIRC32K Disabled.\r
+ * | | |1 = Enabled\r
+ * | | |If LXT clock fail detector flag CLKFIF (RTC_INTSTS[24]) is generated, RTC clock source will switch to LIRC32K automatically.\r
+ * |[2] |LXTSPSW |LXT Clock Stop Detector Switch LIRC32K Enable Bit\r
+ * | | |0 = LXT Clock Stop Detector Switch LIRC32K Disabled.\r
+ * | | |1 = Enabled\r
+ * | | |If LXT clock stop detector flag CLKSPIF (RTC_INTSTS[25]) is generated, RTC clock source will switch to LIRC32K automatically\r
+ * |[16] |CLKSWLIRCF|LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only)\r
+ * | | |0 = RTC clock source from LXT.\r
+ * | | |1 = RTC clock source from LIRC32K .\r
+ * |[17] |LXTFASTF |LXT Faster Than LIRX32K Flag (Read Only)\r
+ * | | |0 = LXT frequency is slowly.\r
+ * | | |1 = LXT frequency faster than LIRC32K.\r
+ * @var RTC_T::CDBR\r
+ * Offset: 0x144 Clock Frequency Detector Boundary Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |STOPBD |LXT Clock Frequency Detector Stop Boundary\r
+ * | | |The bits define the stop value of frequency monitor window.\r
+ * | | |When LXT frequency monitor counter lower than Clock Frequency Detector Stop Boundary , the LXT frequency detect Stop interrupt flag will set to 1.\r
+ * | | |Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time.\r
+ * |[23:16] |FAILBD |LXT Clock Frequency Detector Fail Boundary\r
+ * | | |The bits define the fail value of frequency monitor window.\r
+ * | | |When LXT frequency monitor counter lower than Clock Frequency Detector fail Boundary , the LXT frequency detect fail interrupt flag will set to 1.\r
+ * | | |Note: The boundary is defined as the minimum value of LXT among 256 LIRC32K clock time.\r
+ */\r
+ __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */\r
+ __IO uint32_t RWEN; /*!< [0x0004] RTC Access Enable Register */\r
+ __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */\r
+ __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */\r
+ __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */\r
+ __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */\r
+ __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */\r
+ __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */\r
+ __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */\r
+ __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */\r
+ __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */\r
+ __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */\r
+ __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */\r
+ __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */\r
+ __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */\r
+ __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */\r
+ __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008C] RTC Spare Register 0 ~ 19 */\r
+ __I uint32_t RESERVE0[28]; /* 0x90 ~ 0xFC */\r
+ __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */\r
+ __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */\r
+ __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */\r
+ __I uint32_t RESERVE1[1];\r
+ __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */\r
+ __I uint32_t RESERVE2[3];\r
+ __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */\r
+ __I uint32_t RESERVE3[1];\r
+ __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */\r
+ __I uint32_t RESERVE4[1];\r
+ __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */\r
+ __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */\r
+ __I uint32_t RESERVE5[2];\r
+ __IO uint32_t CLKDCTL; /*!< [0x0140] Clock Fail Detector Control Register */\r
+ __IO uint32_t CDBR; /*!< [0x0144] Clock Frequency Detector Boundary Register */\r
+\r
+} RTC_T;\r
+\r
+/**\r
+ @addtogroup RTC_CONST RTC Bit Field Definition\r
+ Constant Definitions for RTC Controller\r
+@{ */\r
+\r
+#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */\r
+#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */\r
+\r
+#define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */\r
+#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */\r
+\r
+#define RTC_RWEN_RWEN_Pos (0) /*!< RTC_T::RWEN: RWEN Position */\r
+#define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) /*!< RTC_T::RWEN: RWEN Mask */\r
+\r
+#define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */\r
+#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */\r
+\r
+#define RTC_RWEN_RTCBUSY_Pos (24) /*!< RTC_T::RWEN: RTCBUSY Position */\r
+#define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) /*!< RTC_T::RWEN: RTCBUSY Mask */\r
+\r
+#define RTC_FREQADJ_FREQADJ_Pos (0) /*!< RTC_T::FREQADJ: FREQADJ Position */\r
+#define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos) /*!< RTC_T::FREQADJ: FREQADJ Mask */\r
+\r
+#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */\r
+#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */\r
+\r
+#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */\r
+#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */\r
+\r
+#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */\r
+#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */\r
+\r
+#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */\r
+#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */\r
+\r
+#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */\r
+#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */\r
+\r
+#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */\r
+#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */\r
+\r
+#define RTC_TIME_HZCNT_Pos (24) /*!< RTC_T::TIME: HZCNT Position */\r
+#define RTC_TIME_HZCNT_Msk (0x7ful << RTC_TIME_HZCNT_Pos) /*!< RTC_T::TIME: HZCNT Mask */\r
+\r
+#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */\r
+#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */\r
+\r
+#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */\r
+#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */\r
+\r
+#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */\r
+#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */\r
+\r
+#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */\r
+#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */\r
+\r
+#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */\r
+#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */\r
+\r
+#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */\r
+#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */\r
+\r
+#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */\r
+#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */\r
+\r
+#define RTC_CLKFMT_HZCNTEN_Pos (8) /*!< RTC_T::CLKFMT: HZCNTEN Position */\r
+#define RTC_CLKFMT_HZCNTEN_Msk (0x1ul << RTC_CLKFMT_HZCNTEN_Pos) /*!< RTC_T::CLKFMT: HZCNTEN Mask */\r
+\r
+#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */\r
+#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */\r
+\r
+#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */\r
+#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */\r
+\r
+#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */\r
+#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */\r
+\r
+#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */\r
+#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */\r
+\r
+#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */\r
+#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */\r
+\r
+#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */\r
+#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */\r
+\r
+#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */\r
+#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */\r
+\r
+#define RTC_TALM_HZCNT_Pos (24) /*!< RTC_T::TALM: HZCNT Position */\r
+#define RTC_TALM_HZCNT_Msk (0x7ful << RTC_TALM_HZCNT_Pos) /*!< RTC_T::TALM: HZCNT Mask */\r
+\r
+#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */\r
+#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */\r
+\r
+#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */\r
+#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */\r
+\r
+#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */\r
+#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */\r
+\r
+#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */\r
+#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */\r
+\r
+#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */\r
+#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */\r
+\r
+#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */\r
+#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */\r
+\r
+#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */\r
+#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */\r
+\r
+#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */\r
+#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */\r
+\r
+#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */\r
+#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */\r
+\r
+#define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */\r
+#define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */\r
+\r
+#define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */\r
+#define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */\r
+\r
+#define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */\r
+#define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */\r
+\r
+#define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */\r
+#define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */\r
+\r
+#define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */\r
+#define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */\r
+\r
+#define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */\r
+#define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */\r
+\r
+#define RTC_INTEN_CLKFIEN_Pos (24) /*!< RTC_T::INTEN: CLKFIEN Position */\r
+#define RTC_INTEN_CLKFIEN_Msk (0x1ul << RTC_INTEN_CLKFIEN_Pos) /*!< RTC_T::INTEN: CLKFIEN Mask */\r
+\r
+#define RTC_INTEN_CLKSPIEN_Pos (25) /*!< RTC_T::INTEN: CLKSPIEN Position */\r
+#define RTC_INTEN_CLKSPIEN_Msk (0x1ul << RTC_INTEN_CLKSPIEN_Pos) /*!< RTC_T::INTEN: CLKSPIEN Mask */\r
+\r
+#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */\r
+#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */\r
+\r
+#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */\r
+#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */\r
+\r
+#define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */\r
+#define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */\r
+\r
+#define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */\r
+#define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */\r
+\r
+#define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */\r
+#define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */\r
+\r
+#define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */\r
+#define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */\r
+\r
+#define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */\r
+#define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */\r
+\r
+#define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */\r
+#define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */\r
+\r
+#define RTC_INTSTS_CLKFIF_Pos (24) /*!< RTC_T::INTSTS: CLKFIF Position */\r
+#define RTC_INTSTS_CLKFIF_Msk (0x1ul << RTC_INTSTS_CLKFIF_Pos) /*!< RTC_T::INTSTS: CLKFIF Mask */\r
+\r
+#define RTC_INTSTS_CLKSPIF_Pos (25) /*!< RTC_T::INTSTS: CLKSPIF Position */\r
+#define RTC_INTSTS_CLKSPIF_Msk (0x1ul << RTC_INTSTS_CLKSPIF_Pos) /*!< RTC_T::INTSTS: CLKSPIF Mask */\r
+\r
+#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */\r
+#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */\r
+\r
+#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */\r
+#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */\r
+\r
+#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */\r
+#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */\r
+\r
+#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */\r
+#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */\r
+\r
+#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */\r
+#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */\r
+\r
+#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */\r
+#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */\r
+\r
+#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */\r
+#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */\r
+\r
+#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */\r
+#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */\r
+\r
+#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */\r
+#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */\r
+\r
+#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */\r
+#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */\r
+\r
+#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */\r
+#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */\r
+\r
+#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */\r
+#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */\r
+\r
+#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */\r
+#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */\r
+\r
+#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */\r
+#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */\r
+\r
+#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */\r
+#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */\r
+\r
+#define RTC_SPRCTL_LXTFCLR_Pos (16) /*!< RTC_T::SPRCTL: LXTFCLR Position */\r
+#define RTC_SPRCTL_LXTFCLR_Msk (0x1ul << RTC_SPRCTL_LXTFCLR_Pos) /*!< RTC_T::SPRCTL: LXTFCLR Mask */\r
+\r
+#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */\r
+#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */\r
+\r
+#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */\r
+#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */\r
+\r
+#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */\r
+#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */\r
+\r
+#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */\r
+#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */\r
+\r
+#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */\r
+#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */\r
+\r
+#define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */\r
+#define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */\r
+\r
+#define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */\r
+#define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */\r
+\r
+#define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */\r
+#define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */\r
+\r
+#define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */\r
+#define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */\r
+\r
+#define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */\r
+#define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */\r
+\r
+#define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */\r
+#define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */\r
+\r
+#define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */\r
+#define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */\r
+\r
+#define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */\r
+#define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */\r
+\r
+#define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */\r
+#define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */\r
+\r
+#define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */\r
+#define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */\r
+\r
+#define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */\r
+#define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */\r
+\r
+#define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */\r
+#define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */\r
+\r
+#define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */\r
+#define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */\r
+\r
+#define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */\r
+#define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */\r
+\r
+#define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */\r
+#define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */\r
+\r
+#define RTC_LXTCTL_LIRC32KEN_Pos (0) /*!< RTC_T::LXTCTL: LIRC32KEN Position */\r
+#define RTC_LXTCTL_LIRC32KEN_Msk (0x1ul << RTC_LXTCTL_LIRC32KEN_Pos) /*!< RTC_T::LXTCTL: LIRC32KEN Mask */\r
+\r
+#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */\r
+#define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */\r
+\r
+#define RTC_LXTCTL_C32KS_Pos (7) /*!< RTC_T::LXTCTL: C32KS Position */\r
+#define RTC_LXTCTL_C32KS_Msk (0x1ul << RTC_LXTCTL_C32KS_Pos) /*!< RTC_T::LXTCTL: C32KS Mask */\r
+\r
+#define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */\r
+#define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */\r
+\r
+#define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */\r
+#define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */\r
+\r
+#define RTC_GPIOCTL0_CTLSEL0_Pos (3) /*!< RTC_T::GPIOCTL0: CTLSEL0 Position */\r
+#define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask */\r
+\r
+#define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */\r
+#define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */\r
+\r
+#define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */\r
+#define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */\r
+\r
+#define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */\r
+#define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */\r
+\r
+#define RTC_GPIOCTL0_CTLSEL1_Pos (11) /*!< RTC_T::GPIOCTL0: CTLSEL1 Position */\r
+#define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask */\r
+\r
+#define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */\r
+#define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */\r
+\r
+#define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */\r
+#define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */\r
+\r
+#define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */\r
+#define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */\r
+\r
+#define RTC_GPIOCTL0_CTLSEL2_Pos (19) /*!< RTC_T::GPIOCTL0: CTLSEL2 Position */\r
+#define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask */\r
+\r
+#define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */\r
+#define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */\r
+\r
+#define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */\r
+#define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */\r
+\r
+#define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */\r
+#define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */\r
+\r
+#define RTC_GPIOCTL0_CTLSEL3_Pos (27) /*!< RTC_T::GPIOCTL0: CTLSEL3 Position */\r
+#define RTC_GPIOCTL0_CTLSEL3_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL3 Mask */\r
+\r
+#define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */\r
+#define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */\r
+\r
+#define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */\r
+#define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */\r
+\r
+#define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */\r
+#define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */\r
+\r
+#define RTC_GPIOCTL1_CTLSEL4_Pos (3) /*!< RTC_T::GPIOCTL1: CTLSEL4 Position */\r
+#define RTC_GPIOCTL1_CTLSEL4_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL4 Mask */\r
+\r
+#define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */\r
+#define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */\r
+\r
+#define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */\r
+#define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */\r
+\r
+#define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */\r
+#define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */\r
+\r
+#define RTC_GPIOCTL1_CTLSEL5_Pos (11) /*!< RTC_T::GPIOCTL1: CTLSEL5 Position */\r
+#define RTC_GPIOCTL1_CTLSEL5_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL5 Mask */\r
+\r
+#define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */\r
+#define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */\r
+\r
+#define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */\r
+#define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */\r
+\r
+#define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */\r
+#define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */\r
+\r
+#define RTC_GPIOCTL1_CTLSEL6_Pos (19) /*!< RTC_T::GPIOCTL1: CTLSEL6 Position */\r
+#define RTC_GPIOCTL1_CTLSEL6_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL6 Mask */\r
+\r
+#define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */\r
+#define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */\r
+\r
+#define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */\r
+#define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */\r
+\r
+#define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */\r
+#define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */\r
+\r
+#define RTC_GPIOCTL1_CTLSEL7_Pos (27) /*!< RTC_T::GPIOCTL1: CTLSEL7 Position */\r
+#define RTC_GPIOCTL1_CTLSEL7_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL7 Mask */\r
+\r
+#define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */\r
+#define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */\r
+\r
+#define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */\r
+#define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */\r
+\r
+#define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */\r
+#define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */\r
+\r
+#define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */\r
+#define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */\r
+\r
+#define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */\r
+#define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */\r
+\r
+#define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */\r
+#define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */\r
+\r
+#define RTC_TAMPCTL_DYNSRC_Pos (2) /*!< RTC_T::TAMPCTL: DYNSRC Position */\r
+#define RTC_TAMPCTL_DYNSRC_Msk (0x3ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */\r
+\r
+#define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */\r
+#define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */\r
+\r
+#define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */\r
+#define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */\r
+#define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */\r
+#define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */\r
+#define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */\r
+#define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */\r
+#define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */\r
+#define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */\r
+\r
+#define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */\r
+#define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */\r
+#define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */\r
+#define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */\r
+#define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */\r
+#define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */\r
+#define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */\r
+#define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */\r
+\r
+#define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */\r
+#define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */\r
+#define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */\r
+#define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */\r
+#define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */\r
+#define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */\r
+#define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */\r
+\r
+#define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */\r
+#define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */\r
+\r
+#define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */\r
+#define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */\r
+\r
+#define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */\r
+#define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */\r
+\r
+#define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */\r
+#define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */\r
+\r
+#define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */\r
+#define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */\r
+\r
+#define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */\r
+#define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */\r
+\r
+#define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */\r
+#define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */\r
+\r
+#define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */\r
+#define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */\r
+\r
+#define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */\r
+#define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */\r
+\r
+#define RTC_TAMPTIME_HZCNT_Pos (24) /*!< RTC_T::TAMPTIME: HZCNT Position */\r
+#define RTC_TAMPTIME_HZCNT_Msk (0x7ful << RTC_TAMPTIME_HZCNT_Pos) /*!< RTC_T::TAMPTIME: HZCNT Mask */\r
+\r
+#define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */\r
+#define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */\r
+\r
+#define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */\r
+#define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */\r
+\r
+#define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */\r
+#define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */\r
+\r
+#define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */\r
+#define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */\r
+\r
+#define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */\r
+#define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */\r
+\r
+#define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */\r
+#define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */\r
+\r
+#define RTC_CLKDCTL_LXTFDEN_Pos (0) /*!< RTC_T::CLKDCTL: LXTFDEN Position */\r
+#define RTC_CLKDCTL_LXTFDEN_Msk (0x1ul << RTC_CLKDCTL_LXTFDEN_Pos) /*!< RTC_T::CLKDCTL: LXTFDEN Mask */\r
+\r
+#define RTC_CLKDCTL_LXTFSW_Pos (1) /*!< RTC_T::CLKDCTL: LXTFSW Position */\r
+#define RTC_CLKDCTL_LXTFSW_Msk (0x1ul << RTC_CLKDCTL_LXTFSW_Pos) /*!< RTC_T::CLKDCTL: LXTFSW Mask */\r
+\r
+#define RTC_CLKDCTL_LXTSPSW_Pos (2) /*!< RTC_T::CLKDCTL: LXTSPSW Position */\r
+#define RTC_CLKDCTL_LXTSPSW_Msk (0x1ul << RTC_CLKDCTL_LXTSPSW_Pos) /*!< RTC_T::CLKDCTL: LXTSPSW Mask */\r
+\r
+#define RTC_CLKDCTL_CLKSWLIRCF_Pos (16) /*!< RTC_T::CLKDCTL: CLKSWLIRCF Position */\r
+#define RTC_CLKDCTL_CLKSWLIRCF_Msk (0x1ul << RTC_CLKDCTL_CLKSWLIRCF_Pos) /*!< RTC_T::CLKDCTL: CLKSWLIRCF Mask */\r
+\r
+#define RTC_CLKDCTL_LXTFASTF_Pos (17) /*!< RTC_T::CLKDCTL: LXTFASTF Position */\r
+#define RTC_CLKDCTL_LXTFASTF_Msk (0x1ul << RTC_CLKDCTL_LXTFASTF_Pos) /*!< RTC_T::CLKDCTL: LXTFASTF Mask */\r
+\r
+#define RTC_CDBR_STOPBD_Pos (0) /*!< RTC_T::CDBR: STOPBD Position */\r
+#define RTC_CDBR_STOPBD_Msk (0xfful << RTC_CDBR_STOPBD_Pos) /*!< RTC_T::CDBR: STOPBD Mask */\r
+\r
+#define RTC_CDBR_FAILBD_Pos (16) /*!< RTC_T::CDBR: FAILBD Position */\r
+#define RTC_CDBR_FAILBD_Msk (0xfful << RTC_CDBR_FAILBD_Pos) /*!< RTC_T::CDBR: FAILBD Mask */\r
+\r
+/**@}*/ /* RTC_CONST */\r
+/**@}*/ /* end of RTC register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __RTC_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file sc_reg.h\r
+ * @version V1.00\r
+ * @brief SC register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __SC_REG_H__\r
+#define __SC_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Smart Card Host Interface Controller -------------------------*/\r
+/**\r
+ @addtogroup SC Smart Card Host Interface Controller(SC)\r
+ Memory Mapped Structure for SC Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var SC_T::DAT\r
+ * Offset: 0x00 SC Receive/Transmit Holding Buffer Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |DAT |Receive/Transmit Holding Buffer\r
+ * | | |Write Operation:\r
+ * | | |By writing data to DAT, the SC will send out an 8-bit data.\r
+ * | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.\r
+ * | | |Read Operation:\r
+ * | | |By reading DAT, the SC will return an 8-bit received data.\r
+ * @var SC_T::CTL\r
+ * Offset: 0x04 SC Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SCEN |SC Controller Enable Bit\r
+ * | | |Set this bit to 1 to enable SC operation.\r
+ * | | |0 = SC will force all transition to IDLE state.\r
+ * | | |1 = SC controller is enabled and all function can work correctly.\r
+ * | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly.\r
+ * |[1] |RXOFF |RX Transition Disable Control Bit\r
+ * | | |This bit is used for disable Rx transition function.\r
+ * | | |0 = The receiver Enabled.\r
+ * | | |1 = The receiver Disabled.\r
+ * | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.\r
+ * |[2] |TXOFF |TX Transition Disable Control Bit\r
+ * | | |This bit is used for disable Tx transition function.\r
+ * | | |0 = The transceiver Enabled.\r
+ * | | |1 = The transceiver Disabled.\r
+ * |[3] |AUTOCEN |Auto Convention Enable Bit\r
+ * | | |This bit is used for enable auto convention function.\r
+ * | | |0 = Auto-convention Disabled.\r
+ * | | |1 = Auto-convention Enabled.\r
+ * | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F\r
+ * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F\r
+ * | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.\r
+ * | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled.\r
+ * |[5:4] |CONSEL |Convention Selection\r
+ * | | |00 = Direct convention.\r
+ * | | |01 = Reserved.\r
+ * | | |10 = Reserved.\r
+ * | | |11 = Inverse convention.\r
+ * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.\r
+ * |[7:6] |RXTRGLV |Rx Buffer Trigger Level\r
+ * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set\r
+ * | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU.\r
+ * | | |00 = Rx Buffer Trigger Level with 01 bytes.\r
+ * | | |01 = Rx Buffer Trigger Level with 02 bytes.\r
+ * | | |10 = Rx Buffer Trigger Level with 03 bytes.\r
+ * | | |11 = Reserved.\r
+ * |[12:8] |BGT |Block Guard Time (BGT)\r
+ * | | |Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions\r
+ * | | |This field indicates the counter for the bit length of block guard time\r
+ * | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it.\r
+ * | | |Note: The real block guard time is BGT + 1.\r
+ * |[14:13] |TMRSEL |Timer Channel Selection\r
+ * | | |00 = All internal timer function Disabled.\r
+ * | | |.\r
+ * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled\r
+ * | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0].\r
+ * | | |Other configurations are reserve\r
+ * |[15] |NSB |Stop Bit Length\r
+ * | | |This field indicates the length of stop bit.\r
+ * | | |0 = The stop bit length is 2 ETU.(for ISO 7816-3 T=0 mode).\r
+ * | | |1= The stop bit length is 1 ETU.(for ISO 7816-3 T=1 mode).\r
+ * | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length.\r
+ * | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0.\r
+ * |[18:16] |RXRTY |RX Error Retry Count Number\r
+ * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred\r
+ * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\r
+ * | | |Note2: This field cannot be changed when RXRTYEN enabled\r
+ * | | |The change flow is to disable RXRTYEN first and then fill in new retry value.\r
+ * |[19] |RXRTYEN |RX Error Retry Enable Bit\r
+ * | | |This bit enables receiver retry function when parity error has occurred.\r
+ * | | |0 = RX error retry function Disabled.\r
+ * | | |1 = RX error retry function Enabled.\r
+ * | | |Note: User must fill in the RXRTY value before enabling this bit.\r
+ * |[22:20] |TXRTY |TX Error Retry Count Number\r
+ * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\r
+ * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\r
+ * | | |Note2: This field cannot be changed when TXRTYEN enabled\r
+ * | | |The change flow is to disable TXRTYEN first and then fill in new retry value.\r
+ * |[23] |TXRTYEN |TX Error Retry Enable Bit\r
+ * | | |This bit enables transmitter retry function when parity error has occurred.\r
+ * | | |0 = TX error retry function Disabled.\r
+ * | | |1 = TX error retry function Enabled.\r
+ * |[25:24] |CDDBSEL |Card Detect De-bounce Selection\r
+ * | | |This field indicates the card detect de-bounce selection.\r
+ * | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks.\r
+ * | | |Other configurations are reserved.\r
+ * |[26] |CDLV |Card Detect Level Selection\r
+ * | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected.\r
+ * | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected.\r
+ * | | |Note: User must select card detect level before Smart Card controller enabled.\r
+ * |[30] |SYNC |SYNC Flag Indicator (Read Only)\r
+ * | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields.\r
+ * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.\r
+ * | | |1 = Last value is synchronizing.\r
+ * @var SC_T::ALTCTL\r
+ * Offset: 0x08 SC Alternate Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |TXRST |TX Software Reset\r
+ * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the TX internal state machine and pointers.\r
+ * | | |Note: This bit will be auto cleared after reset is complete.\r
+ * |[1] |RXRST |Rx Software Reset\r
+ * | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the Rx internal state machine and pointers.\r
+ * | | |Note: This bit will be auto cleared after reset is complete.\r
+ * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit\r
+ * | | |This bit enables SC controller to initiate the card by deactivation sequence.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Deactivation sequence generator Enabled.\r
+ * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\r
+ * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])\r
+ * | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.\r
+ * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\r
+ * |[3] |ACTEN |Activation Sequence Generator Enable Bit\r
+ * | | |This bit enables SC controller to initiate the card by activation sequence.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Activation sequence generator Enabled.\r
+ * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\r
+ * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])\r
+ * | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.\r
+ * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\r
+ * | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data\r
+ * | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation.\r
+ * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit\r
+ * | | |This bit enables SC controller to initiate the card by warm reset sequence.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Warm reset sequence generator Enabled.\r
+ * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\r
+ * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])\r
+ * | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.\r
+ * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\r
+ * | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data\r
+ * | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence.\r
+ * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit\r
+ * | | |This bit enables Timer 0 to start counting\r
+ * | | |User can fill 0 to stop it and set 1 to reload and count\r
+ * | | |The counter unit is ETU base.\r
+ * | | |0 = Stops counting.\r
+ * | | |1 = Start counting.\r
+ * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only.\r
+ * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.\r
+ * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed\r
+ * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit\r
+ * | | |This bit enables Timer 1 to start counting\r
+ * | | |User can fill 0 to stop it and set 1 to reload and count\r
+ * | | |The counter unit is ETU base.\r
+ * | | |0 = Stops counting.\r
+ * | | |1 = Start counting.\r
+ * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only\r
+ * | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.\r
+ * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.\r
+ * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\r
+ * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit\r
+ * | | |This bit enables Timer 2 to start counting\r
+ * | | |User can fill 0 to stop it and set 1 to reload and count\r
+ * | | |The counter unit is ETU base.\r
+ * | | |0 = Stops counting.\r
+ * | | |1 = Start counting.\r
+ * | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only\r
+ * | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.\r
+ * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.\r
+ * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\r
+ * |[9:8] |INITSEL |Initial Timing Selection\r
+ * | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation.\r
+ * | | |The unit of initial timing is SC module clock.\r
+ * | | |Activation: refer to SC Activation Sequence in Figure 6.17-4 SC Activation Sequence.\r
+ * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5 SC Warm Reset Sequence.\r
+ * | | |Deactivation: refer to Deactivation Sequence in Figure 6.17-6 SC Deactivation Sequence.\r
+ * | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles.\r
+ * |[11] |ADACEN |Auto Deactivation When Card Removal\r
+ * | | |This bit is used for enable hardware auto deactivation when smart card is removed.\r
+ * | | |0 = Auto deactivation Disabled.\r
+ * | | |1 = Auto deactivation Enabled.\r
+ * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set\r
+ * | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also.\r
+ * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit\r
+ * | | |This bit enables the receiver block guard time function.\r
+ * | | |0 = Receiver block guard time function Disabled.\r
+ * | | |1 = Receiver block guard time function Enabled.\r
+ * |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only)\r
+ * | | |This bit indicates the timer counter status of timer0.\r
+ * | | |0 = Timer0 is not active.\r
+ * | | |1 = Timer0 is active.\r
+ * | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]).\r
+ * |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only)\r
+ * | | |This bit indicates the timer counter status of timer1.\r
+ * | | |0 = Timer1 is not active.\r
+ * | | |1 = Timer1 is active.\r
+ * | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]).\r
+ * |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only)\r
+ * | | |This bit indicates the timer counter status of timer2.\r
+ * | | |0 = Timer2 is not active.\r
+ * | | |1 = Timer2 is active.\r
+ * | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]).\r
+ * |[31] |SYNC |SYNC Flag Indicator (Read Only)\r
+ * | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register.\r
+ * | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register.\r
+ * | | |1 = Last value is synchronizing.\r
+ * @var SC_T::EGT\r
+ * Offset: 0x0C SC Extra Guard Time Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |EGT |Extra Guard Time\r
+ * | | |This field indicates the extra guard time value.\r
+ * | | |Note: The extra guard time unit is ETU base.\r
+ * @var SC_T::RXTOUT\r
+ * Offset: 0x10 SC Receive Buffer Time-out Counter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[8:0] |RFTM |SC Receiver FIFO Time-out Counter\r
+ * | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data\r
+ * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled.\r
+ * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.\r
+ * | | |Note2: Filling in all 0 to this field indicates to disable this function.\r
+ * @var SC_T::ETUCTL\r
+ * Offset: 0x14 SC Element Time Unit Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[11:0] |ETURDIV |ETU Rate Divider\r
+ * | | |The field is used for ETU clock rate divider.\r
+ * | | |The real ETU is ETURDIV + 1.\r
+ * | | |Note: User can configure this field, but this field must be greater than 0x04.\r
+ * @var SC_T::INTEN\r
+ * Offset: 0x18 SC Interrupt Enable Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit\r
+ * | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt.\r
+ * | | |0 = Receive data reach trigger level interrupt Disabled.\r
+ * | | |1 = Receive data reach trigger level interrupt Enabled.\r
+ * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit\r
+ * | | |This field is used to enable transmit buffer empty interrupt.\r
+ * | | |0 = Transmit buffer empty interrupt Disabled.\r
+ * | | |1 = Transmit buffer empty interrupt Enabled.\r
+ * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit\r
+ * | | |This field is used to enable transfer error interrupt\r
+ * | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]).\r
+ * | | |0 = Transfer error interrupt Disabled.\r
+ * | | |1 = Transfer error interrupt Enabled.\r
+ * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit\r
+ * | | |This field is used to enable Timer0 interrupt function.\r
+ * | | |0 = Timer0 interrupt Disabled.\r
+ * | | |1 = Timer0 interrupt Enabled.\r
+ * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit\r
+ * | | |This field is used to enable the Timer1 interrupt function.\r
+ * | | |0 = Timer1 interrupt Disabled.\r
+ * | | |1 = Timer1 interrupt Enabled.\r
+ * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit\r
+ * | | |This field is used to enable Timer2 interrupt function.\r
+ * | | |0 = Timer2 interrupt Disabled.\r
+ * | | |1 = Timer2 interrupt Enabled.\r
+ * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit\r
+ * | | |This field is used to enable block guard time interrupt in receive direction.\r
+ * | | |0 = Block guard time interrupt Disabled.\r
+ * | | |1 = Block guard time interrupt Enabled.\r
+ * | | |Note: This bit is valid only for receive receive direction block guard time.\r
+ * |[7] |CDIEN |Card Detect Interrupt Enable Bit\r
+ * | | |This field is used to enable card detect interrupt\r
+ * | | |The card detect status is CDPINSTS (SCn_STATUS[13]).\r
+ * | | |0 = Card detect interrupt Disabled.\r
+ * | | |1 = Card detect interrupt Enabled.\r
+ * |[8] |INITIEN |Initial End Interrupt Enable Bit\r
+ * | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation (DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt.\r
+ * | | |0 = Initial end interrupt Disabled.\r
+ * | | |1 = Initial end interrupt Enabled.\r
+ * |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit\r
+ * | | |This field is used to enable receiver buffer time-out interrupt.\r
+ * | | |0 = Receiver buffer time-out interrupt Disabled.\r
+ * | | |1 = Receiver buffer time-out interrupt Enabled.\r
+ * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit\r
+ * | | |This field is used to enable auto-convention error interrupt.\r
+ * | | |0 = Auto-convention error interrupt Disabled.\r
+ * | | |1 = Auto-convention error interrupt Enabled.\r
+ * @var SC_T::INTSTS\r
+ * Offset: 0x1C SC Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)\r
+ * | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\r
+ * | | |0 = Number of receive buffer is less than RXTRGLV setting.\r
+ * | | |1 = Number of receive buffer data equals the RXTRGLV setting.\r
+ * | | |Note: This bit is read only\r
+ * | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically.\r
+ * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)\r
+ * | | |This field is used for transmit buffer empty interrupt status flag.\r
+ * | | |0 = Transmit buffer is not empty.\r
+ * | | |1 = Transmit buffer is empty.\r
+ * | | |Note: This bit is read only\r
+ * | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically.\r
+ * |[2] |TERRIF |Transfer Error Interrupt Status Flag\r
+ * | | |This field is used for transfer error interrupt status flag\r
+ * | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]).\r
+ * | | |0 = Transfer error interrupt did not occur.\r
+ * | | |1 = Transfer error interrupt occurred.\r
+ * | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.\r
+ * | | |Note2: This bit can be cleared by writing 1 to it.\r
+ * |[3] |TMR0IF |Timer0 Interrupt Status Flag\r
+ * | | |This field is used for Timer0 interrupt status flag.\r
+ * | | |0 = Timer0 interrupt did not occur.\r
+ * | | |1 = Timer0 interrupt occurred.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[4] |TMR1IF |Timer1 Interrupt Status Flag\r
+ * | | |This field is used for Timer1 interrupt status flag.\r
+ * | | |0 = Timer1 interrupt did not occur.\r
+ * | | |1 = Timer1 interrupt occurred.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[5] |TMR2IF |Timer2 Interrupt Status Flag\r
+ * | | |This field is used for Timer2 interrupt status flag.\r
+ * | | |0 = Timer2 interrupt did not occur.\r
+ * | | |1 = Timer2 interrupt occurred.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[6] |BGTIF |Block Guard Time Interrupt Status Flag\r
+ * | | |This field is used for indicate block guard time interrupt status flag in receive direction.\r
+ * | | |0 = Block guard time interrupt did not occur.\r
+ * | | |1 = Block guard time interrupt occurred.\r
+ * | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\r
+ * | | |Note2: This bit can be cleared by writing 1 to it.\r
+ * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)\r
+ * | | |This field is used for card detect interrupt status flag\r
+ * | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).\r
+ * | | |0 = Card detect event did not occur.\r
+ * | | |1 = Card detect event occurred.\r
+ * | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it.\r
+ * |[8] |INITIF |Initial End Interrupt Status Flag\r
+ * | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\r
+ * | | |0 = Initial sequence is not complete.\r
+ * | | |1 = Initial sequence is completed.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only)\r
+ * | | |This field is used for indicate receive buffer time-out interrupt status flag.\r
+ * | | |0 = Receive buffer time-out interrupt did not occur.\r
+ * | | |1 = Receive buffer time-out interrupt occurred.\r
+ * | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it.\r
+ * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag\r
+ * | | |This field indicates auto convention sequence error.\r
+ * | | |0 = Received TS at ATR state is 0x3B or 0x3F.\r
+ * | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * @var SC_T::STATUS\r
+ * Offset: 0x20 SC Transfer Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RXOV |Receive Overflow Error Status Flag\r
+ * | | |This bit is set when Rx buffer overflow.\r
+ * | | |0 = Rx buffer is not overflow.\r
+ * | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes).\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only)\r
+ * | | |This bit indicates Rx buffer empty or not.\r
+ * | | |0 = Rx buffer is not empty.\r
+ * | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU.\r
+ * |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only)\r
+ * | | |This bit indicates Rx buffer full or not.\r
+ * | | |0 = Rx buffer count is less than 4.\r
+ * | | |1 = Rx buffer count equals to 4.\r
+ * |[4] |PEF |Receiver Parity Error Status Flag\r
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit.\r
+ * | | |0 = Receiver parity error flag did not occur.\r
+ * | | |1 = Receiver parity error flag occurred.\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.\r
+ * |[5] |FEF |Receiver Frame Error Status Flag\r
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\r
+ * | | |0 = Receiver frame error flag did not occur.\r
+ * | | |1 = Receiver frame error flag occurred.\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.\r
+ * |[6] |BEF |Receiver Break Error Status Flag\r
+ * | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity bit + stop bits).\r
+ * | | |0 = Receiver break error flag did not occur.\r
+ * | | |1 = Receiver break error flag occurred.\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.\r
+ * |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag\r
+ * | | |This bit is set when Tx buffer overflow.\r
+ * | | |0 = Tx buffer is not overflow.\r
+ * | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]).\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)\r
+ * | | |This bit indicates TX buffer empty or not.\r
+ * | | |0 = Tx buffer is not empty.\r
+ * | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register.\r
+ * | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]).\r
+ * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)\r
+ * | | |This bit indicates Tx buffer full or not.\r
+ * | | |0 = Tx buffer count is less than 4.\r
+ * | | |1 = Tx buffer count equals to 4.\r
+ * |[11] |CREMOVE |Card Removal Status of SCn_CD Pin\r
+ * | | |This bit is set whenever card has been removal.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Card removed.\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set.\r
+ * |[12] |CINSERT |Card Insert Status of SCn_CD Pin\r
+ * | | |This bit is set whenever card has been inserted.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Card insert.\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set.\r
+ * |[13] |CDPINSTS |Card Detect Pin Status (Read Only)\r
+ * | | |This bit is the pin status of SCn_CD.\r
+ * | | |0 = The SCn_CD pin state at low.\r
+ * | | |1 = The SCn_CD pin state at high.\r
+ * |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only)\r
+ * | | |This field indicates the Rx buffer pointer status\r
+ * | | |When SC controller receives one byte from external device, RXPOINT increases one\r
+ * | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one.\r
+ * |[21] |RXRERR |Receiver Retry Error\r
+ * | | |This bit is used for receiver error retry and set by hardware.\r
+ * | | |0 = No Rx retry transfer.\r
+ * | | |1 = Rx has any error and retries transfer.\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.\r
+ * | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.\r
+ * |[22] |RXOVERR |Receiver over Retry Error\r
+ * | | |This bit is used for receiver retry counts over than retry number limitation.\r
+ * | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1.\r
+ * | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1.\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.\r
+ * |[23] |RXACT |Receiver in Active Status Flag (Read Only)\r
+ * | | |This bit indicates Rx transfer status.\r
+ * | | |0 = This bit is cleared automatically when Rx transfer is finished.\r
+ * | | |1 = This bit is set by hardware when Rx transfer is in active.\r
+ * | | |Note: This bit is read only.\r
+ * | | |Note2:\r
+ * |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only)\r
+ * | | |This field indicates the Tx buffer pointer status\r
+ * | | |When CPU writes data into SCn_DAT, TXPOINT increases one\r
+ * | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one.\r
+ * |[29] |TXRERR |Transmitter Retry Error\r
+ * | | |This bit is used for indicate transmitter error retry and set by hardware..\r
+ * | | |0 = No Tx retry transfer.\r
+ * | | |1 = Tx has any error and retries transfer.\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2: This bit is a flag and cannot generate any interrupt to CPU.\r
+ * |[30] |TXOVERR |Transmitter over Retry Error\r
+ * | | |This bit is used for transmitter retry counts over than retry number limitation.\r
+ * | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1.\r
+ * | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[31] |TXACT |Transmit in Active Status Flag (Read Only)\r
+ * | | |This bit indicates Tx transmit status.\r
+ * | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed.\r
+ * | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted.\r
+ * | | |Note: This bit is read only.\r
+ * @var SC_T::PINCTL\r
+ * Offset: 0x24 SC Pin Control State Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PWREN |SCn_PWR Pin Signal\r
+ * | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\r
+ * | | |Write this field to drive SCn_PWR pin\r
+ * | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level.\r
+ * | | |Read this field to get SCn_PWR signal status.\r
+ * | | |0 = SCn_PWR signal status is low.\r
+ * | | |1 = SCn_PWR signal status is high.\r
+ * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically\r
+ * | | |Thus, do not fill in this field when operating in these modes.\r
+ * |[1] |RSTEN |SCn_RST Pin Signal\r
+ * | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\r
+ * | | |Write this field to drive SCn_RST pin.\r
+ * | | |0 = Drive SCn_RST pin to low.\r
+ * | | |1 = Drive SCn_RST pin to high.\r
+ * | | |Read this field to get SCn_RST signal status.\r
+ * | | |0 = SCn_RST signal status is low.\r
+ * | | |1 = SCn_RST signal status is high.\r
+ * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically\r
+ * | | |Thus, do not fill in this field when operating in these modes.\r
+ * |[5] |CSTOPLV |SCn_CLK Pin Stop Level\r
+ * | | |This field indicates the SCn_CLK pin status when SC clock in clock stop mode.\r
+ * | | |0 = SCn_CLK pin keeps at low when SC clock stopped.\r
+ * | | |1 = SCn_CLK pin keeps at high when SC clock stopped.\r
+ * |[6] |CLKKEEP |SC Clock Enable Bit\r
+ * | | |0 = SC clock generation Disabled.\r
+ * | | |1 = SC clock always keeps free running.\r
+ * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically\r
+ * | | |Thus, do not fill in this field when operating in these modes.\r
+ * |[9] |SCDATA |SCn_DATA Pin Signal\r
+ * | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\r
+ * | | |0 = Drive SCn_DATA pin to low.\r
+ * | | |1 = Drive SCn_DATA pin to high.\r
+ * | | |Read this field to get SCn_DATA signal status.\r
+ * | | |0 = SCn_DATA signal status is low.\r
+ * | | |1 = SCn_DATA signal status is high.\r
+ * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically\r
+ * | | |Thus, do not fill in this field when SC is in these modes.\r
+ * |[11] |PWRINV |SCn_PWR Pin Inverse\r
+ * | | |This bit is used for inverse the SCn_PWR pin.\r
+ * | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]).\r
+ * | | |0 = SCn_PWR pin inverse Disabled\r
+ * | | |If PWREN is 1, SCn_PWR pin status is 1; if PWREN is 0, SCn_PWR pin status is 0.\r
+ * | | |1 = SCn_PWR pin inverse Enabled\r
+ * | | |If PWREN is 1, SCn_PWR pin status is 0; if PWREN is 0, SCn_PWR pin status is 1.\r
+ * | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]).\r
+ * |[16] |DATASTS |SCn_DATA Pin Status (Read Only)\r
+ * | | |This bit is the pin status of SCn_DATA.\r
+ * | | |0 = The SCn_DATA pin status is low.\r
+ * | | |1 = The SCn_DATA pin status is high.\r
+ * | | |Note:\r
+ * |[17] |PWRSTS |SCn_PWR Pin Status (Read Only)\r
+ * | | |This bit is the pin status of SCn_PWR.\r
+ * | | |0 = SCn_PWR pin to low.\r
+ * | | |1 = SCn_PWR pin to high.\r
+ * |[18] |RSTSTS |SCn_RST Pin Status (Read Only)\r
+ * | | |This bit is the pin status of SCn_RST.\r
+ * | | |0 = SCn_RST pin is low.\r
+ * | | |1 = SCn_RST pin is high.\r
+ * |[30] |SYNC |SYNC Flag Indicator (Read Only)\r
+ * | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register.\r
+ * | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register.\r
+ * | | |1 = Last value is synchronizing.\r
+ * @var SC_T::TMRCTL0\r
+ * Offset: 0x28 SC Internal Timer0 Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[23:0] |CNT |Timer0 Counter Value\r
+ * | | |This field indicates the internal Timer0 counter values.\r
+ * | | |Note: Unit of Timer0 counter is ETU base.\r
+ * |[27:24] |OPMODE |Timer0 Operation Mode Selection\r
+ * | | |This field indicates the internal 24-bit Timer0 operation selection.\r
+ * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer0.\r
+ * |[31] |SYNC |SYNC Flag Indicator (Read Only)\r
+ * | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register.\r
+ * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register.\r
+ * | | |1 = Last value is synchronizing.\r
+ * @var SC_T::TMRCTL1\r
+ * Offset: 0x2C SC Internal Timer1 Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |CNT |Timer 1 Counter Value\r
+ * | | |This field indicates the internal Timer1 counter values.\r
+ * | | |Note: Unit of Timer1 counter is ETU base.\r
+ * |[27:24] |OPMODE |Timer 1 Operation Mode Selection\r
+ * | | |This field indicates the internal 8-bit Timer1 operation selection.\r
+ * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer1.\r
+ * |[31] |SYNC |SYNC Flag Indicator (Read Only)\r
+ * | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register.\r
+ * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register.\r
+ * | | |1 = Last value is synchronizing.\r
+ * @var SC_T::TMRCTL2\r
+ * Offset: 0x30 SC Internal Timer2 Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |CNT |Timer 2 Counter Value\r
+ * | | |This field indicates the internal Timer2 counter values.\r
+ * | | |Note: Unit of Timer2 counter is ETU base.\r
+ * |[27:24] |OPMODE |Timer 2 Operation Mode Selection\r
+ * | | |This field indicates the internal 8-bit Timer2 operation selection\r
+ * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer2.\r
+ * |[31] |SYNC |SYNC Flag Indicator (Read Only)\r
+ * | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register.\r
+ * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register.\r
+ * | | |1 = Last value is synchronizing.\r
+ * @var SC_T::UARTCTL\r
+ * Offset: 0x34 SC UART Mode Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |UARTEN |UART Mode Enable Bit\r
+ * | | |Sets this bit to enable UART mode function.\r
+ * | | |0 = Smart Card mode.\r
+ * | | |1 = UART mode.\r
+ * | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0.\r
+ * | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0.\r
+ * | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine.\r
+ * |[5:4] |WLS |Word Length Selection\r
+ * | | |This field is used for select UART data length.\r
+ * | | |00 = Word length is 8 bits.\r
+ * | | |01 = Word length is 7 bits.\r
+ * | | |10 = Word length is 6 bits.\r
+ * | | |11 = Word length is 5 bits.\r
+ * | | |Note: In smart card mode, this WLS must be u201800'.\r
+ * |[6] |PBOFF |Parity Bit Disable Control\r
+ * | | |Sets this bit is used for disable parity check function.\r
+ * | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data.\r
+ * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.\r
+ * | | |Note: In smart card mode, this field must be u20180' (default setting is with parity bit).\r
+ * |[7] |OPE |Odd Parity Enable Bit\r
+ * | | |This is used for odd/even parity selection.\r
+ * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.\r
+ * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.\r
+ * | | |Note: This bit has effect only when PBOFF bit is u20180'.\r
+ * @var SC_T::ACTCTL\r
+ * Offset: 0x4C SC Activation Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[4:0] |T1EXT |T1 Extend Time of Hardware Activation\r
+ * | | |This field provide the configurable cycles to extend the activation time T1 period.\r
+ * | | |The cycle scaling factor is 2048.\r
+ * | | |Extend cycles = (filled value * 2048) cycles.\r
+ * | | |Refer to SC activation sequence in Figure 6.17-4 SC Activation Sequence.\r
+ * | | |For example,\r
+ * | | |SCLK = 4MHz, each cycle = 0.25us,.\r
+ * | | |Filled 20 to this field\r
+ * | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms.\r
+ * | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3\r
+ */\r
+ __IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */\r
+ __IO uint32_t CTL; /*!< [0x0004] SC Control Register */\r
+ __IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */\r
+ __IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */\r
+ __IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */\r
+ __IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */\r
+ __IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */\r
+ __IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */\r
+ __IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */\r
+ __IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */\r
+ __IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */\r
+ __IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */\r
+ __IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */\r
+ __IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */\r
+ __I uint32_t RESERVE0[5];\r
+ __IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */\r
+\r
+} SC_T;\r
+\r
+/**\r
+ @addtogroup SC_CONST SC Bit Field Definition\r
+ Constant Definitions for SC Controller\r
+@{ */\r
+\r
+#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */\r
+#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */\r
+\r
+#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */\r
+#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */\r
+\r
+#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */\r
+#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */\r
+\r
+#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */\r
+#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */\r
+\r
+#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */\r
+#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */\r
+\r
+#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */\r
+#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */\r
+\r
+#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */\r
+#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */\r
+\r
+#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */\r
+#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */\r
+\r
+#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */\r
+#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */\r
+\r
+#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */\r
+#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */\r
+\r
+#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */\r
+#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */\r
+\r
+#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */\r
+#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */\r
+\r
+#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */\r
+#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */\r
+\r
+#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */\r
+#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */\r
+\r
+#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */\r
+#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */\r
+\r
+#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */\r
+#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */\r
+\r
+#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */\r
+#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */\r
+\r
+#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */\r
+#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */\r
+\r
+#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */\r
+#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */\r
+\r
+#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */\r
+#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */\r
+\r
+#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */\r
+#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */\r
+\r
+#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */\r
+#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */\r
+\r
+#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */\r
+#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */\r
+\r
+#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */\r
+#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */\r
+\r
+#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */\r
+#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */\r
+\r
+#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */\r
+#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */\r
+\r
+#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */\r
+#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */\r
+\r
+#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */\r
+#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */\r
+\r
+#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */\r
+#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */\r
+\r
+#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */\r
+#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */\r
+\r
+#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */\r
+#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */\r
+\r
+#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */\r
+#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */\r
+\r
+#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */\r
+#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */\r
+\r
+#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */\r
+#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */\r
+\r
+#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */\r
+#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */\r
+\r
+#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */\r
+#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */\r
+\r
+#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */\r
+#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */\r
+\r
+#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */\r
+#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */\r
+\r
+#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */\r
+#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */\r
+\r
+#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */\r
+#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */\r
+\r
+#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */\r
+#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */\r
+\r
+#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */\r
+#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */\r
+\r
+#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */\r
+#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */\r
+\r
+#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */\r
+#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */\r
+\r
+#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */\r
+#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */\r
+\r
+#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */\r
+#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */\r
+\r
+#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */\r
+#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */\r
+\r
+#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */\r
+#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */\r
+\r
+#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */\r
+#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */\r
+\r
+#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */\r
+#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */\r
+\r
+#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */\r
+#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */\r
+\r
+#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */\r
+#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */\r
+\r
+#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */\r
+#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */\r
+\r
+#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */\r
+#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */\r
+\r
+#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */\r
+#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */\r
+\r
+#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */\r
+#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */\r
+\r
+#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */\r
+#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */\r
+\r
+#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */\r
+#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */\r
+\r
+#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */\r
+#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */\r
+\r
+#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */\r
+#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */\r
+\r
+#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */\r
+#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */\r
+\r
+#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */\r
+#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */\r
+\r
+#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */\r
+#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */\r
+\r
+#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */\r
+#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */\r
+\r
+#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */\r
+#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */\r
+\r
+#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */\r
+#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */\r
+\r
+#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */\r
+#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */\r
+\r
+#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */\r
+#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */\r
+\r
+#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */\r
+#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */\r
+\r
+#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */\r
+#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */\r
+\r
+#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */\r
+#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */\r
+\r
+#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */\r
+#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */\r
+\r
+#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */\r
+#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */\r
+\r
+#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */\r
+#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */\r
+\r
+#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */\r
+#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */\r
+\r
+#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */\r
+#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */\r
+\r
+#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */\r
+#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */\r
+\r
+#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */\r
+#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */\r
+\r
+#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */\r
+#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */\r
+\r
+#define SC_PINCTL_CSTOPLV_Pos (5) /*!< SC_T::PINCTL: CSTOPLV Position */\r
+#define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) /*!< SC_T::PINCTL: CSTOPLV Mask */\r
+\r
+#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */\r
+#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */\r
+\r
+#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */\r
+#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */\r
+\r
+#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */\r
+#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */\r
+\r
+#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */\r
+#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */\r
+\r
+#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */\r
+#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */\r
+\r
+#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */\r
+#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */\r
+\r
+#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */\r
+#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */\r
+\r
+#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */\r
+#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */\r
+\r
+#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */\r
+#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */\r
+\r
+#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */\r
+#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */\r
+\r
+#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */\r
+#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */\r
+\r
+#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */\r
+#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */\r
+\r
+#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */\r
+#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */\r
+\r
+#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */\r
+#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */\r
+\r
+#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */\r
+#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */\r
+\r
+#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */\r
+#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */\r
+\r
+#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */\r
+#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */\r
+\r
+#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */\r
+#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */\r
+\r
+#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */\r
+#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */\r
+\r
+#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */\r
+#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */\r
+\r
+#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */\r
+#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */\r
+\r
+/**@}*/ /* SC_CONST */\r
+/**@}*/ /* end of SC register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __SC_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file scu_reg.h\r
+ * @version V1.00\r
+ * @brief SCU register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __SCU_REG_H__\r
+#define __SCU_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- Secure configuration Unit -------------------------*/\r
+/**\r
+ @addtogroup SCU Secure configuration Unit(SCU)\r
+ Memory Mapped Structure for SCU Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var SCU_T::PNSSET[0]\r
+ * Offset: 0x00 Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x4001_FFFF)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[9] |USBH |Set USBH to Non-secure State\r
+ * | | |Write 1 to set USBH to non-secure state. Write 0 has no effect.\r
+ * | | |0 = USBH is a secure module (default).\r
+ * | | |1 = USBH is a non-secure module.\r
+ * |[13] |SDH0 |Set SDH0 to Non-secure State\r
+ * | | |Write 1 to set SDH0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = SDH0 is a secure module (default).\r
+ * | | |1 = SDH0 is a non-secure module.\r
+ * |[16] |EBI |Set EBI to Non-secure State\r
+ * | | |Write 1 to set EBI to non-secure state. Write 0 has no effect.\r
+ * | | |0 = EBI is a secure module (default).\r
+ * | | |1 = EBI is a non-secure module.\r
+ * |[24] |PDMA1 |Set PDMA1 to Non-secure State\r
+ * | | |Write 1 to set PDMA1 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = PDMA1 is a secure module (default).\r
+ * | | |1 = PDMA1 is a non-secure module.\r
+ * @var SCU_T::PNSSET[1]\r
+ * Offset: 0x04 Peripheral Non-secure Attribution Set Register1 (0x4002_0000~0x4003_FFFF)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[17] |CRC |Set CRC to Non-secure State\r
+ * | | |Write 1 to set CRC to non-secure state. Write 0 has no effect.\r
+ * | | |0 = CRC is a secure module (default).\r
+ * | | |1 = CRC is a non-secure module.\r
+ * |[18] |CRPT |Set CRPT to Non-secure State\r
+ * | | |Write 1 to set CRPT to non-secure state. Write 0 has no effect.\r
+ * | | |0 = CRPT is a secure module (default).\r
+ * | | |1 = CRPT is a non-secure module.\r
+ * @var SCU_T::PNSSET[2]\r
+ * Offset: 0x08 Peripheral Non-secure Attribution Set Register2 (0x4004_0000~0x4005_FFFF)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |RTC |Set RTC to Non-secure State\r
+ * | | |Write 1 to set RTC to non-secure state. Write 0 has no effect.\r
+ * | | |0 = RTC is a secure module (default).\r
+ * | | |1 = RTC is a non-secure module.\r
+ * |[3] |EADC |Set EADC to Non-secure State\r
+ * | | |Write 1 to set EADC to non-secure state. Write 0 has no effect.\r
+ * | | |0 = EADC is a secure module (default).\r
+ * | | |1 = EADC is a non-secure module.\r
+ * |[5] |ACMP01 |Set ACMP01 to Non-secure State\r
+ * | | |Write 1 to set ACMP0, ACMP1 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = ACMP0, ACMP1 are secure modules (default).\r
+ * | | |1 = ACMP0, ACMP1 are non-secure modules.\r
+ * |[7] |DAC |Set DAC to Non-secure State\r
+ * | | |Write 1 to set DAC to non-secure state. Write 0 has no effect.\r
+ * | | |0 = DAC is a secure module (default).\r
+ * | | |1 = DAC is a non-secure module.\r
+ * |[8] |I2S0 |Set I2S0 to Non-secure State\r
+ * | | |Write 1 to set I2S0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = I2S0 is a secure module (default).\r
+ * | | |1 = I2S0 is a non-secure module.\r
+ * |[13] |OTG |Set OTG to Non-secure State\r
+ * | | |Write 1 to set OTG to non-secure state. Write 0 has no effect.\r
+ * | | |0 = OTG is a secure module (default).\r
+ * | | |1 = OTG is a non-secure module.\r
+ * |[17] |TMR23 |Set TMR23 to Non-secure State\r
+ * | | |Write 1 to set TMR23 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = TMR23 is a secure module (default).\r
+ * | | |1 = TMR23 is a non-secure module.\r
+ * |[24] |EPWM0 |Set EPWM0 to Non-secure State\r
+ * | | |Write 1 to set EPWM0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = EPWM0 is a secure module (default).\r
+ * | | |1 = EPWM0 is a non-secure module.\r
+ * |[25] |EPWM1 |Set EPWM1 to Non-secure State\r
+ * | | |Write 1 to set EPWM1 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = EPWM1 is a secure module (default).\r
+ * | | |1 = EPWM1 is a non-secure module.\r
+ * |[26] |BPWM0 |Set BPWM0 to Non-secure State\r
+ * | | |Write 1 to set BPWM0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = BPWM0 is a secure module (default).\r
+ * | | |1 = BPWM0 is a non-secure module.\r
+ * |[27] |BPWM1 |Set BPWM1 to Non-secure State\r
+ * | | |Write 1 to set BPWM1 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = BPWM1 is a secure module (default).\r
+ * | | |1 = BPWM1 is a non-secure module.\r
+ * @var SCU_T::PNSSET[3]\r
+ * Offset: 0x0C Peripheral Non-secure Attribution Set Register3 (0x4006_0000~0x4007_FFFF)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |QSPI0 |Set QSPI0 to Non-secure State\r
+ * | | |Write 1 to set QSPI0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = QSPI0 is a secure module (default).\r
+ * | | |1 = QSPI0 is a non-secure module.\r
+ * |[1] |SPI0 |Set SPI0 to Non-secure State\r
+ * | | |Write 1 to set SPI0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = SPI0 is a secure module (default).\r
+ * | | |1 = SPI0 is a non-secure module.\r
+ * |[2] |SPI1 |Set SPI1 to Non-secure State\r
+ * | | |Write 1 to set SPI1 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = SPI1 is a secure module (default).\r
+ * | | |1 = SPI1 is a non-secure module.\r
+ * |[3] |SPI2 |Set SPI2 to Non-secure State\r
+ * | | |Write 1 to set SPI2 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = SPI2 is a secure module (default).\r
+ * | | |1 = SPI2 is a non-secure module.\r
+ * |[4] |SPI3 |Set SPI3 to Non-secure State\r
+ * | | |Write 1 to set SPI3 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = SPI3 is a secure module (default).\r
+ * | | |1 = SPI3 is a non-secure module.\r
+ * |[16] |UART0 |Set UART0 to Non-secure State\r
+ * | | |Write 1 to set UART0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = UART0 is a secure module (default).\r
+ * | | |1 = UART0 is a non-secure module.\r
+ * |[17] |UART1 |Set UART1 to Non-secure State\r
+ * | | |Write 1 to set UART1 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = UART1 is a secure module (default).\r
+ * | | |1 = UART1 is a non-secure module.\r
+ * |[18] |UART2 |Set UART2 to Non-secure State\r
+ * | | |Write 1 to set UART2 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = UART2 is a secure module (default).\r
+ * | | |1 = UART2 is a non-secure module.\r
+ * |[19] |UART3 |Set UART3 to Non-secure State\r
+ * | | |Write 1 to set UART3 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = UART3 is a secure module (default).\r
+ * | | |1 = UART3 is a non-secure module.\r
+ * |[20] |UART4 |Set UART4 to Non-secure State\r
+ * | | |Write 1 to set UART4 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = UART4 is a secure module (default).\r
+ * | | |1 = UART4 is a non-secure module.\r
+ * |[21] |UART5 |Set UART5 to Non-secure State\r
+ * | | |Write 1 to set UART5 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = UART5 is a secure module (default).\r
+ * | | |1 = UART5 is a non-secure module.\r
+ * @var SCU_T::PNSSET[4]\r
+ * Offset: 0x10 Peripheral Non-secure Attribution Set Register4 (0x4008_0000~0x4009_FFFF)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |I2C0 |Set I2C0 to Non-secure State\r
+ * | | |Write 1 to set I2C0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = I2C0 is a secure module (default).\r
+ * | | |1 = I2C0 is a non-secure module.\r
+ * |[1] |I2C1 |Set I2C1 to Non-secure State\r
+ * | | |Write 1 to set I2C1 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = I2C1 is a secure module (default).\r
+ * | | |1 = I2C1 is a non-secure module.\r
+ * |[2] |I2C2 |Set I2C2 to Non-secure State\r
+ * | | |Write 1 to set I2C2 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = I2C2 is a secure module (default).\r
+ * | | |1 = I2C2 is a non-secure module.\r
+ * |[16] |SC0 |Set SC0 to Non-secure State\r
+ * | | |Write 1 to set SC0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = SC0 is a secure module (default).\r
+ * | | |1 = SC0 is a non-secure module.\r
+ * |[17] |SC1 |Set SC1 to Non-secure State\r
+ * | | |Write 1 to set SC1 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = SC1 is a secure module (default).\r
+ * | | |1 = SC1 is a non-secure module.\r
+ * |[18] |SC2 |Set SC2 to Non-secure State\r
+ * | | |Write 1 to set SC2 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = SC2 is a secure module (default).\r
+ * | | |1 = SC2 is a non-secure module.\r
+ * @var SCU_T::PNSSET[5]\r
+ * Offset: 0x14 Peripheral Non-secure Attribution Set Register5 (0x400A_0000~0x400B_FFFF)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CAN0 |Set CAN0 to Non-secure State\r
+ * | | |Write 1 to set CAN0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = CAN0 is a secure module (default).\r
+ * | | |1 = CAN0 is a non-secure module.\r
+ * |[16] |QEI0 |Set QEI0 to Non-secure State\r
+ * | | |Write 1 to set QEI0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = QEI0 is a secure module (default).\r
+ * | | |1 = QEI0 is a non-secure module.\r
+ * |[17] |QEI1 |Set QEI1 to Non-secure State\r
+ * | | |Write 1 to set QEI1 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = QEI1 is a secure module (default).\r
+ * | | |1 = QEI1 is a non-secure module.\r
+ * |[20] |ECAP0 |Set ECAP0 to Non-secure State\r
+ * | | |Write 1 to set ECAP0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = ECAP0 is a secure module (default).\r
+ * | | |1 = ECAP0 is a non-secure module.\r
+ * |[21] |ECAP1 |Set ECAP1 to Non-secure State\r
+ * | | |Write 1 to set ECAP1 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = ECAP1 is a secure module (default).\r
+ * | | |1 = ECAP1 is a non-secure module.\r
+ * |[25] |TRNG |Set TRNG to Non-secure State\r
+ * | | |Write 1 to set TRNG to non-secure state. Write 0 has no effect.\r
+ * | | |0 = TRNG is a secure module (default).\r
+ * | | |1 = TRNG is a non-secure module.\r
+ * @var SCU_T::PNSSET[6]\r
+ * Offset: 0x18 Peripheral Non-secure Attribution Set Register6 (0x400C_0000~0x400D_FFFF)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |USBD |Set USBD to Non-secure State\r
+ * | | |Write 1 to set USBD to non-secure state. Write 0 has no effect.\r
+ * | | |0 = USBD is a secure module (default).\r
+ * | | |1 = USBD is a non-secure module.\r
+ * |[16] |USCI0 |Set USCI0 to Non-secure State\r
+ * | | |Write 1 to set USCI0 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = USCI0 is a secure module (default).\r
+ * | | |1 = USCI0 is a non-secure module.\r
+ * |[17] |USCI1 |Set USCI1 to Non-secure State\r
+ * | | |Write 1 to set USCI1 to non-secure state. Write 0 has no effect.\r
+ * | | |0 = USCI1 is a secure module (default).\r
+ * | | |1 = USCI1 is a non-secure module.\r
+ * @var SCU_T::IONSSET\r
+ * Offset: 0x20 IO Non-secure Attribution Set Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PA |Set GPIO Port a to Non-scecure State\r
+ * | | |Write 1 to set PA to non-secure state. Write 0 has no effect.\r
+ * | | |0 = GPIO port A is secure (default).\r
+ * | | |1 = GPIO port A is non-secure.\r
+ * |[1] |PB |Set GPIO Port B to Non-scecure State\r
+ * | | |Write 1 to set PB to non-secure state. Write 0 has no effect.\r
+ * | | |0 = GPIO port B is secure (default).\r
+ * | | |1 = GPIO port B is non-secure.\r
+ * |[2] |PC |Set GPIO Port C to Non-scecure State\r
+ * | | |Write 1 to set PC to non-secure state. Write 0 has no effect.\r
+ * | | |0 = GPIO port C is secure (default).\r
+ * | | |1 = GPIO port C is non-secure.\r
+ * |[3] |PD |Set GPIO Port D to Non-scecure State\r
+ * | | |Write 1 to set PD to non-secure state. Write 0 has no effect.\r
+ * | | |0 = GPIO port D is secure (default).\r
+ * | | |1 = GPIO port D is non-secure.\r
+ * |[4] |PE |Set GPIO Port E to Non-scecure State\r
+ * | | |Write 1 to set PE to non-secure state. Write 0 has no effect.\r
+ * | | |0 = GPIO port E is secure (default).\r
+ * | | |1 = GPIO port E is non-secure.\r
+ * |[5] |PF |Set GPIO Port F to Non-scecure State\r
+ * | | |Write 1 to set PF to non-secure state. Write 0 has no effect.\r
+ * | | |0 = GPIO port F is secure (default).\r
+ * | | |1 = GPIO port F is non-secure.\r
+ * |[6] |PG |Set GPIO Port G to Non-scecure State\r
+ * | | |Write 1 to set PG to non-secure state. Write 0 has no effect.\r
+ * | | |0 = GPIO port G is secure (default).\r
+ * | | |1 = GPIO port G is non-secure.\r
+ * |[7] |PH |Set GPIO Port H to Non-scecure State\r
+ * | | |Write 1 to set PH to non-secure state. Write 0 has no effect.\r
+ * | | |0 = GPIO port H is secure (default).\r
+ * | | |1 = GPIO port H is non-secure.\r
+ * @var SCU_T::SRAMNSSET\r
+ * Offset: 0x24 SRAM Non-secure Attribution Set Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[11:0] |SECn |Set SRAM Section N to Non-scecure State\r
+ * | | |Write 1 to set SRAM section n to non-secure state. Write 0 is ignored.\r
+ * | | |0 = SRAM Section n is secure (default).\r
+ * | | |1 = SRAM Section n is non-secure.\r
+ * | | |Secure SRAM section n is 0x2000_0000+0x2000*n to 0x2000_0000+0x2000*(n+1)-0x1\r
+ * | | |Non-secure SRAM section n is 0x3000_0000+0x2000*n to 0x3000_0000+0x2000*(n+1)-0x1\r
+ * @var SCU_T::FNSADDR\r
+ * Offset: 0x28 Flash Non-secure Boundary Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |FNSADDR |Flash Non-secure Boundary Address\r
+ * | | |Indicate the base address of Non-secure region set in user configuration\r
+ * | | |Refer to FMC section for more details.\r
+ * @var SCU_T::SVIOIEN\r
+ * Offset: 0x2C Security Violation Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |APB0IEN |APB0 Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of APB0 Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of APB0 Enabled.\r
+ * |[1] |APB1IEN |APB1 Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of APB1 Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of APB1 Enabled.\r
+ * |[4] |GPIOIEN |GPIO Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of GPIO Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of GPIO Enabled.\r
+ * |[5] |EBIIEN |EBI Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of EBI Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of EBI Enabled.\r
+ * |[6] |USBHIEN |USBH Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of USB host Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of USB host Enabled.\r
+ * |[7] |CRCIEN |CRC Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of CRC Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of CRC Enabled.\r
+ * |[8] |SDH0IEN |SDH0 Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of SD host 0 Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of SD host 0 Enabled.\r
+ * |[10] |PDMA0IEN |PDMA0 Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of PDMA0 Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of PDMA0 Enabled.\r
+ * |[11] |PDMA1IEN |PDMA1 Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of PDMA1 Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of PDMA1 Enabled.\r
+ * |[12] |SRAM0IEN |SRAM Bank 0 Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of SRAM bank0 Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of SRAM bank0 Enabled.\r
+ * |[13] |SRAM1IEN |SRAM Bank 1 Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of SRAM bank1 Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of SRAM bank1 Enabled.\r
+ * |[14] |FMCIEN |FMC Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of FMC Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of FMC Enabled.\r
+ * |[15] |FLASHIEN |FLASH Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of Flash data Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of Flash data Enabled.\r
+ * |[16] |SCUIEN |SCU Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of SCU Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of SCU Enabled.\r
+ * |[17] |SYSIEN |SYS Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of system manager Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of system manager Enabled.\r
+ * |[18] |CRPTIEN |CRPT Security Violation Interrupt Enable Bit\r
+ * | | |0 = Interrupt triggered from security violation of crypto Disabled.\r
+ * | | |1 = Interrupt triggered from security violation of crypto Enabled.\r
+ * @var SCU_T::SVINTSTS\r
+ * Offset: 0x30 Security Violation Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |APB0IF |APB0 Security Violation Interrupt Status\r
+ * | | |0 = No APB0 violation interrupt event.\r
+ * | | |1 = There is APB0 violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[1] |APB1IF |APB1 Security Violation Interrupt Status\r
+ * | | |0 = No APB1 violation interrupt event.\r
+ * | | |1 = There is APB1 violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[4] |GPIOIF |GPIO Security Violation Interrupt Status\r
+ * | | |0 = No GPIO violation interrupt event.\r
+ * | | |1 = There is GPIO violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[5] |EBIIF |EBI Security Violation Interrupt Status\r
+ * | | |0 = No EBI violation interrupt event.\r
+ * | | |1 = There is EBI violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[6] |USBHIF |USBH Security Violation Interrupt Status\r
+ * | | |0 = No USBH violation interrupt event.\r
+ * | | |1 = There is USBH violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[7] |CRCIF |CRC Security Violation Interrupt Status\r
+ * | | |0 = No CRC violation interrupt event.\r
+ * | | |1 = There is CRC violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[8] |SDH0IF |SDH0 Security Violation Interrupt Status\r
+ * | | |0 = No SDH0 violation interrupt event.\r
+ * | | |1 = There is SDH0 violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[10] |PDMA0IF |PDMA0 Security Violation Interrupt Status\r
+ * | | |0 = No PDMA0 violation interrupt event.\r
+ * | | |1 = There is PDMA0 violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[11] |PDMA1IF |PDMA1 Security Violation Interrupt Status\r
+ * | | |0 = No PDMA1 violation interrupt event.\r
+ * | | |1 = There is PDMA1 violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[12] |SRAM0IF |SRAM0 Security Violation Interrupt Status\r
+ * | | |0 = No SRAM0 violation interrupt event.\r
+ * | | |1 = There is SRAM0 violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[13] |SRAM1IF |SRAM Bank 1 Security Violation Interrupt Status\r
+ * | | |0 = No SRAM1 violation interrupt event.\r
+ * | | |1 = There is SRAM1 violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[14] |FMCIF |FMC Security Violation Interrupt Status\r
+ * | | |0 = No FMC violation interrupt event.\r
+ * | | |1 = There is FMC violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[15] |FLASHIF |FLASH Security Violation Interrupt Status\r
+ * | | |0 = No FLASH violation interrupt event.\r
+ * | | |1 = There is FLASH violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[16] |SCUIF |SCU Security Violation Interrupt Status\r
+ * | | |0 = No SCU violation interrupt event.\r
+ * | | |1 = There is SCU violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[17] |SYSIF |SYS Security Violation Interrupt Status\r
+ * | | |0 = No SYS violation interrupt event.\r
+ * | | |1 = There is SYS violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * |[18] |CRPTIF |CRPT Security Violation Interrupt Status\r
+ * | | |0 = No CRPT violation interrupt event.\r
+ * | | |1 = There is CRPT violation interrupt event.\r
+ * | | |Note: Write 1 to clear the interrupt flag.\r
+ * @var SCU_T::APB0VSRC\r
+ * Offset: 0x34 APB0 Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::APB0VA\r
+ * Offset: 0x38 APB0 Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::APB1VSRC\r
+ * Offset: 0x3C APB1 Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::APB1VA\r
+ * Offset: 0x40 APB1 Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::GPIOVSRC\r
+ * Offset: 0x44 GPIO Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::GPIOVA\r
+ * Offset: 0x48 GPIO Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::EBIVSRC\r
+ * Offset: 0x4C EBI Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::EBIVA\r
+ * Offset: 0x50 EBI Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::USBHVSRC\r
+ * Offset: 0x54 USBH Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::USBHVA\r
+ * Offset: 0x58 USBH Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::CRCVSRC\r
+ * Offset: 0x5C CRC Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::CRCVA\r
+ * Offset: 0x60 CRC Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::SD0VSRC\r
+ * Offset: 0x64 SDH0 Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::SD0VA\r
+ * Offset: 0x68 SDH0 Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::PDMA0VSRC\r
+ * Offset: 0x74 PDMA0 Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::PDMA0VA\r
+ * Offset: 0x78 PDMA0 Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::PDMA1VSRC\r
+ * Offset: 0x7C PDMA1 Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::PDMA1VA\r
+ * Offset: 0x80 PDMA1 Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::SRAM0VSRC\r
+ * Offset: 0x84 SRAM0 Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::SRAM0VA\r
+ * Offset: 0x88 SRAM0 Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::SRAM1VSRC\r
+ * Offset: 0x8C SRAM1 Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::SRAM1VA\r
+ * Offset: 0x90 SRAM1 Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::FMCVSRC\r
+ * Offset: 0x94 FMC Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::FMCVA\r
+ * Offset: 0x98 FMC Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::FLASHVSRC\r
+ * Offset: 0x9C Flash Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::FLASHVA\r
+ * Offset: 0xA0 Flash Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::SCUVSRC\r
+ * Offset: 0xA4 SCU Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::SCUVA\r
+ * Offset: 0xA8 SCU Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::SYSVSRC\r
+ * Offset: 0xAC System Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::SYSVA\r
+ * Offset: 0xB0 System Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::CRPTVSRC\r
+ * Offset: 0xB4 Crypto Security Policy Violation Source\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |MASTER |Master Violating Security Policy\r
+ * | | |Indicate which master invokes the security violation.\r
+ * | | |0x0 = core processor.\r
+ * | | |0x3 = PDMA0.\r
+ * | | |0x4 = SDH0.\r
+ * | | |0x5 = CRYPTO.\r
+ * | | |0x6 = USH.\r
+ * | | |0xB = PDMA1.\r
+ * | | |Others is undefined.\r
+ * @var SCU_T::CRPTVA\r
+ * Offset: 0xB8 Crypto Violation Address\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |VIOADDR |Violation Address\r
+ * | | |Indicate the target address of the access, which invokes the security violation.\r
+ * @var SCU_T::NSMCTL\r
+ * Offset: 0x200 Non-secure State Monitor Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |PRESCALE |Pre-scale Value of Non-secure State Monitor Counter\r
+ * | | |0 = Counter Disabled.\r
+ * | | |Others = Counter Enabled and the counter clock source = HCLK/PRESCALE.\r
+ * |[8] |NSMIEN |Non-secure State Monitor Interrupt Enable Bit\r
+ * | | |0 = Non-secure state monitor interrupt Disabled.\r
+ * | | |1 = Non-secure state monitor interrupt Enabled.\r
+ * |[9] |AUTORLD |Auto Reload Non-secure State Monitor Counter When CURRNS Changing to 1\r
+ * | | |0 = Disable clearing non-secure state monitor counter automtically. (default)\r
+ * | | |1 = Enable clearing non-secure state monitor counter automatically when the core processor changes from secure state to non-secure state\r
+ * |[10] |TMRMOD |Non-secure Monitor Mode Enable Bit\r
+ * | | |0 = Monitor mode. The counter will count down when the core processor is in non-secure state. (default)\r
+ * | | |1 = Free-counting mode\r
+ * | | |The counter will keep counting no mater the core processor is in secure or non-secure state.\r
+ * |[12] |IDLEON |Monitor Counter Keep Counting When the Chip is in Idle Mode Enable Bit\r
+ * | | |0 = The counter will be halted when the chip is in idle mode.\r
+ * | | |1 = The counter will keep counting when the chip is in idle mode. (default)\r
+ * | | |Note: In monitor mode, the counter is always halted when the core processor is in secure state.\r
+ * |[13] |DBGON |Monitor Counter Keep Counting When the Chip is in Debug Mode Enable Bit\r
+ * | | |0 = The counter will be halted when the core processor is halted by ICE. (default)\r
+ * | | |1 = The counter will keep counting when the core processor is halted by ICE.\r
+ * @var SCU_T::NSMLOAD\r
+ * Offset: 0x204 Non-secure State Monitor Reload Value Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[23:0] |RELOAD |Reload Value for Non-secure State Monitor Counter\r
+ * | | |The RELOAD value will be reloaded to the counter whenever the counter counts down to 0.\r
+ * @var SCU_T::NSMVAL\r
+ * Offset: 0x208 Non-secure State Monitor Counter Value Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[23:0] |VALUE |Counter Value of Non-secure State Monitor Counter\r
+ * | | |Current value of non-secure state monitor counter\r
+ * | | |This is down counter and counts down only when CURRNS = 1\r
+ * | | |When counting down to 0, VALUE will automatically be reloaded from NSMLOAD register.\r
+ * | | |A write of any value clears the VALUE to 0 and also clears NSMIF.\r
+ * @var SCU_T::NSMSTS\r
+ * Offset: 0x20C Non-secure State Monitor Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CURRNS |Current Core Processor Secure/Non-secure State\r
+ * | | |0 = Core processor is in secure state.\r
+ * | | |1 = Core processor is in non-secure state.\r
+ * | | |Note: This bit can be used to monitor the current secure/non-secure state of the core processor, even if the non-secure state monitor counter is disabled.\r
+ * |[1] |NSMIF |Non-secure State Monitor Interrupt Flag\r
+ * | | |0 = Counter doesnu2019t count down to 0 since the last NSMIF has been cleared.\r
+ * | | |1 = Counter counts down to 0.\r
+ * | | |Note: This bit is cleared by writing 1.\r
+ */\r
+ __IO uint32_t PNSSET[7]; /*!< [0x0000~0X0018] Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x4001_FFFF) */\r
+ __I uint32_t RESERVE0[1];\r
+ __IO uint32_t IONSSET; /*!< [0x0020] IO Non-secure Attribution Set Register */\r
+ __IO uint32_t SRAMNSSET; /*!< [0x0024] SRAM Non-secure Attribution Set Register */\r
+ __I uint32_t FNSADDR; /*!< [0x0028] Flash Non-secure Boundary Address Register */\r
+ __IO uint32_t SVIOIEN; /*!< [0x002c] Security Violation Interrupt Enable Register */\r
+ __IO uint32_t SVINTSTS; /*!< [0x0030] Security Violation Interrupt Status Register */\r
+ __I uint32_t APB0VSRC; /*!< [0x0034] APB0 Security Policy Violation Source */\r
+ __I uint32_t APB0VA; /*!< [0x0038] APB0 Violation Address */\r
+ __I uint32_t APB1VSRC; /*!< [0x003c] APB1 Security Policy Violation Source */\r
+ __I uint32_t APB1VA; /*!< [0x0040] APB1 Violation Address */\r
+ __I uint32_t GPIOVSRC; /*!< [0x0044] GPIO Security Policy Violation Source */\r
+ __I uint32_t GPIOVA; /*!< [0x0048] GPIO Violation Address */\r
+ __I uint32_t EBIVSRC; /*!< [0x004c] EBI Security Policy Violation Source */\r
+ __I uint32_t EBIVA; /*!< [0x0050] EBI Violation Address */\r
+ __I uint32_t USBHVSRC; /*!< [0x0054] USBH Security Policy Violation Source */\r
+ __I uint32_t USBHVA; /*!< [0x0058] USBH Violation Address */\r
+ __I uint32_t CRCVSRC; /*!< [0x005c] CRC Security Policy Violation Source */\r
+ __I uint32_t CRCVA; /*!< [0x0060] CRC Violation Address */\r
+ __I uint32_t SD0VSRC; /*!< [0x0064] SDH0 Security Policy Violation Source */\r
+ __I uint32_t SD0VA; /*!< [0x0068] SDH0 Violation Address */\r
+ __I uint32_t RESERVE1[2];\r
+ __I uint32_t PDMA0VSRC; /*!< [0x0074] PDMA0 Security Policy Violation Source */\r
+ __I uint32_t PDMA0VA; /*!< [0x0078] PDMA0 Violation Address */\r
+ __I uint32_t PDMA1VSRC; /*!< [0x007c] PDMA1 Security Policy Violation Source */\r
+ __I uint32_t PDMA1VA; /*!< [0x0080] PDMA1 Violation Address */\r
+ __I uint32_t SRAM0VSRC; /*!< [0x0084] SRAM0 Security Policy Violation Source */\r
+ __I uint32_t SRAM0VA; /*!< [0x0088] SRAM0 Violation Address */\r
+ __I uint32_t SRAM1VSRC; /*!< [0x008c] SRAM1 Security Policy Violation Source */\r
+ __I uint32_t SRAM1VA; /*!< [0x0090] SRAM1 Violation Address */\r
+ __I uint32_t FMCVSRC; /*!< [0x0094] FMC Security Policy Violation Source */\r
+ __I uint32_t FMCVA; /*!< [0x0098] FMC Violation Address */\r
+ __I uint32_t FLASHVSRC; /*!< [0x009c] Flash Security Policy Violation Source */\r
+ __I uint32_t FLASHVA; /*!< [0x00a0] Flash Violation Address */\r
+ __I uint32_t SCUVSRC; /*!< [0x00a4] SCU Security Policy Violation Source */\r
+ __I uint32_t SCUVA; /*!< [0x00a8] SCU Violation Address */\r
+ __I uint32_t SYSVSRC; /*!< [0x00ac] System Security Policy Violation Source */\r
+ __I uint32_t SYSVA; /*!< [0x00b0] System Violation Address */\r
+ __I uint32_t CRPTVSRC; /*!< [0x00b4] Crypto Security Policy Violation Source */\r
+ __I uint32_t CRPTVA; /*!< [0x00b8] Crypto Violation Address */\r
+ __I uint32_t RESERVE2[81];\r
+ __IO uint32_t NSMCTL; /*!< [0x0200] Non-secure State Monitor Control Register */\r
+ __IO uint32_t NSMLOAD; /*!< [0x0204] Non-secure State Monitor Reload Value Register */\r
+ __IO uint32_t NSMVAL; /*!< [0x0208] Non-secure State Monitor Counter Value Register */\r
+ __IO uint32_t NSMSTS; /*!< [0x020c] Non-secure State Monitor Status Register */\r
+\r
+} SCU_T;\r
+\r
+/**\r
+ @addtogroup SCU_CONST SCU Bit Field Definition\r
+ Constant Definitions for SCU Controller\r
+@{ */\r
+\r
+#define SCU_PNSSET0_USBH_Pos (9) /*!< SCU_T::PNSSET0: USBH Position */\r
+#define SCU_PNSSET0_USBH_Msk (0x1ul << SCU_PNSSET0_USBH_Pos) /*!< SCU_T::PNSSET0: USBH Mask */\r
+\r
+#define SCU_PNSSET0_SDH0_Pos (13) /*!< SCU_T::PNSSET0: SDH0 Position */\r
+#define SCU_PNSSET0_SDH0_Msk (0x1ul << SCU_PNSSET0_SDH0_Pos) /*!< SCU_T::PNSSET0: SDH0 Mask */\r
+\r
+#define SCU_PNSSET0_EBI_Pos (16) /*!< SCU_T::PNSSET0: EBI Position */\r
+#define SCU_PNSSET0_EBI_Msk (0x1ul << SCU_PNSSET0_EBI_Pos) /*!< SCU_T::PNSSET0: EBI Mask */\r
+\r
+#define SCU_PNSSET0_PDMA1_Pos (24) /*!< SCU_T::PNSSET0: PDMA1 Position */\r
+#define SCU_PNSSET0_PDMA1_Msk (0x1ul << SCU_PNSSET0_PDMA1_Pos) /*!< SCU_T::PNSSET0: PDMA1 Mask */\r
+\r
+#define SCU_PNSSET1_CRC_Pos (17) /*!< SCU_T::PNSSET1: CRC Position */\r
+#define SCU_PNSSET1_CRC_Msk (0x1ul << SCU_PNSSET1_CRC_Pos) /*!< SCU_T::PNSSET1: CRC Mask */\r
+\r
+#define SCU_PNSSET1_CRPT_Pos (18) /*!< SCU_T::PNSSET1: CRPT Position */\r
+#define SCU_PNSSET1_CRPT_Msk (0x1ul << SCU_PNSSET1_CRPT_Pos) /*!< SCU_T::PNSSET1: CRPT Mask */\r
+\r
+#define SCU_PNSSET2_RTC_Pos (1) /*!< SCU_T::PNSSET2: RTC Position */\r
+#define SCU_PNSSET2_RTC_Msk (0x1ul << SCU_PNSSET2_RTC_Pos) /*!< SCU_T::PNSSET2: RTC Mask */\r
+\r
+#define SCU_PNSSET2_EADC_Pos (3) /*!< SCU_T::PNSSET2: EADC Position */\r
+#define SCU_PNSSET2_EADC_Msk (0x1ul << SCU_PNSSET2_EADC_Pos) /*!< SCU_T::PNSSET2: EADC Mask */\r
+\r
+#define SCU_PNSSET2_ACMP01_Pos (5) /*!< SCU_T::PNSSET2: ACMP01 Position */\r
+#define SCU_PNSSET2_ACMP01_Msk (0x1ul << SCU_PNSSET2_ACMP01_Pos) /*!< SCU_T::PNSSET2: ACMP01 Mask */\r
+\r
+#define SCU_PNSSET2_DAC_Pos (7) /*!< SCU_T::PNSSET2: DAC Position */\r
+#define SCU_PNSSET2_DAC_Msk (0x1ul << SCU_PNSSET2_DAC_Pos) /*!< SCU_T::PNSSET2: DAC Mask */\r
+\r
+#define SCU_PNSSET2_I2S0_Pos (8) /*!< SCU_T::PNSSET2: I2S0 Position */\r
+#define SCU_PNSSET2_I2S0_Msk (0x1ul << SCU_PNSSET2_I2S0_Pos) /*!< SCU_T::PNSSET2: I2S0 Mask */\r
+\r
+#define SCU_PNSSET2_OTG_Pos (13) /*!< SCU_T::PNSSET2: OTG Position */\r
+#define SCU_PNSSET2_OTG_Msk (0x1ul << SCU_PNSSET2_OTG_Pos) /*!< SCU_T::PNSSET2: OTG Mask */\r
+\r
+#define SCU_PNSSET2_TMR23_Pos (17) /*!< SCU_T::PNSSET2: TMR23 Position */\r
+#define SCU_PNSSET2_TMR23_Msk (0x1ul << SCU_PNSSET2_TMR23_Pos) /*!< SCU_T::PNSSET2: TMR23 Mask */\r
+\r
+#define SCU_PNSSET2_EPWM0_Pos (24) /*!< SCU_T::PNSSET2: EPWM0 Position */\r
+#define SCU_PNSSET2_EPWM0_Msk (0x1ul << SCU_PNSSET2_EPWM0_Pos) /*!< SCU_T::PNSSET2: EPWM0 Mask */\r
+\r
+#define SCU_PNSSET2_EPWM1_Pos (25) /*!< SCU_T::PNSSET2: EPWM1 Position */\r
+#define SCU_PNSSET2_EPWM1_Msk (0x1ul << SCU_PNSSET2_EPWM1_Pos) /*!< SCU_T::PNSSET2: EPWM1 Mask */\r
+\r
+#define SCU_PNSSET2_BPWM0_Pos (26) /*!< SCU_T::PNSSET2: BPWM0 Position */\r
+#define SCU_PNSSET2_BPWM0_Msk (0x1ul << SCU_PNSSET2_BPWM0_Pos) /*!< SCU_T::PNSSET2: BPWM0 Mask */\r
+\r
+#define SCU_PNSSET2_BPWM1_Pos (27) /*!< SCU_T::PNSSET2: BPWM1 Position */\r
+#define SCU_PNSSET2_BPWM1_Msk (0x1ul << SCU_PNSSET2_BPWM1_Pos) /*!< SCU_T::PNSSET2: BPWM1 Mask */\r
+\r
+#define SCU_PNSSET3_QSPI0_Pos (0) /*!< SCU_T::PNSSET3: QSPI0 Position */\r
+#define SCU_PNSSET3_QSPI0_Msk (0x1ul << SCU_PNSSET3_QSPI0_Pos) /*!< SCU_T::PNSSET3: QSPI0 Mask */\r
+\r
+#define SCU_PNSSET3_SPI0_Pos (1) /*!< SCU_T::PNSSET3: SPI0 Position */\r
+#define SCU_PNSSET3_SPI0_Msk (0x1ul << SCU_PNSSET3_SPI0_Pos) /*!< SCU_T::PNSSET3: SPI0 Mask */\r
+\r
+#define SCU_PNSSET3_SPI1_Pos (2) /*!< SCU_T::PNSSET3: SPI1 Position */\r
+#define SCU_PNSSET3_SPI1_Msk (0x1ul << SCU_PNSSET3_SPI1_Pos) /*!< SCU_T::PNSSET3: SPI1 Mask */\r
+\r
+#define SCU_PNSSET3_SPI2_Pos (3) /*!< SCU_T::PNSSET3: SPI2 Position */\r
+#define SCU_PNSSET3_SPI2_Msk (0x1ul << SCU_PNSSET3_SPI2_Pos) /*!< SCU_T::PNSSET3: SPI2 Mask */\r
+\r
+#define SCU_PNSSET3_SPI3_Pos (4) /*!< SCU_T::PNSSET3: SPI3 Position */\r
+#define SCU_PNSSET3_SPI3_Msk (0x1ul << SCU_PNSSET3_SPI3_Pos) /*!< SCU_T::PNSSET3: SPI3 Mask */\r
+\r
+#define SCU_PNSSET3_UART0_Pos (16) /*!< SCU_T::PNSSET3: UART0 Position */\r
+#define SCU_PNSSET3_UART0_Msk (0x1ul << SCU_PNSSET3_UART0_Pos) /*!< SCU_T::PNSSET3: UART0 Mask */\r
+\r
+#define SCU_PNSSET3_UART1_Pos (17) /*!< SCU_T::PNSSET3: UART1 Position */\r
+#define SCU_PNSSET3_UART1_Msk (0x1ul << SCU_PNSSET3_UART1_Pos) /*!< SCU_T::PNSSET3: UART1 Mask */\r
+\r
+#define SCU_PNSSET3_UART2_Pos (18) /*!< SCU_T::PNSSET3: UART2 Position */\r
+#define SCU_PNSSET3_UART2_Msk (0x1ul << SCU_PNSSET3_UART2_Pos) /*!< SCU_T::PNSSET3: UART2 Mask */\r
+\r
+#define SCU_PNSSET3_UART3_Pos (19) /*!< SCU_T::PNSSET3: UART3 Position */\r
+#define SCU_PNSSET3_UART3_Msk (0x1ul << SCU_PNSSET3_UART3_Pos) /*!< SCU_T::PNSSET3: UART3 Mask */\r
+\r
+#define SCU_PNSSET3_UART4_Pos (20) /*!< SCU_T::PNSSET3: UART4 Position */\r
+#define SCU_PNSSET3_UART4_Msk (0x1ul << SCU_PNSSET3_UART4_Pos) /*!< SCU_T::PNSSET3: UART4 Mask */\r
+\r
+#define SCU_PNSSET3_UART5_Pos (21) /*!< SCU_T::PNSSET3: UART5 Position */\r
+#define SCU_PNSSET3_UART5_Msk (0x1ul << SCU_PNSSET3_UART5_Pos) /*!< SCU_T::PNSSET3: UART5 Mask */\r
+\r
+#define SCU_PNSSET4_I2C0_Pos (0) /*!< SCU_T::PNSSET4: I2C0 Position */\r
+#define SCU_PNSSET4_I2C0_Msk (0x1ul << SCU_PNSSET4_I2C0_Pos) /*!< SCU_T::PNSSET4: I2C0 Mask */\r
+\r
+#define SCU_PNSSET4_I2C1_Pos (1) /*!< SCU_T::PNSSET4: I2C1 Position */\r
+#define SCU_PNSSET4_I2C1_Msk (0x1ul << SCU_PNSSET4_I2C1_Pos) /*!< SCU_T::PNSSET4: I2C1 Mask */\r
+\r
+#define SCU_PNSSET4_I2C2_Pos (2) /*!< SCU_T::PNSSET4: I2C2 Position */\r
+#define SCU_PNSSET4_I2C2_Msk (0x1ul << SCU_PNSSET4_I2C2_Pos) /*!< SCU_T::PNSSET4: I2C2 Mask */\r
+\r
+#define SCU_PNSSET4_SC0_Pos (16) /*!< SCU_T::PNSSET4: SC0 Position */\r
+#define SCU_PNSSET4_SC0_Msk (0x1ul << SCU_PNSSET4_SC0_Pos) /*!< SCU_T::PNSSET4: SC0 Mask */\r
+\r
+#define SCU_PNSSET4_SC1_Pos (17) /*!< SCU_T::PNSSET4: SC1 Position */\r
+#define SCU_PNSSET4_SC1_Msk (0x1ul << SCU_PNSSET4_SC1_Pos) /*!< SCU_T::PNSSET4: SC1 Mask */\r
+\r
+#define SCU_PNSSET4_SC2_Pos (18) /*!< SCU_T::PNSSET4: SC2 Position */\r
+#define SCU_PNSSET4_SC2_Msk (0x1ul << SCU_PNSSET4_SC2_Pos) /*!< SCU_T::PNSSET4: SC2 Mask */\r
+\r
+#define SCU_PNSSET5_CAN0_Pos (0) /*!< SCU_T::PNSSET5: CAN0 Position */\r
+#define SCU_PNSSET5_CAN0_Msk (0x1ul << SCU_PNSSET5_CAN0_Pos) /*!< SCU_T::PNSSET5: CAN0 Mask */\r
+\r
+#define SCU_PNSSET5_QEI0_Pos (16) /*!< SCU_T::PNSSET5: QEI0 Position */\r
+#define SCU_PNSSET5_QEI0_Msk (0x1ul << SCU_PNSSET5_QEI0_Pos) /*!< SCU_T::PNSSET5: QEI0 Mask */\r
+\r
+#define SCU_PNSSET5_QEI1_Pos (17) /*!< SCU_T::PNSSET5: QEI1 Position */\r
+#define SCU_PNSSET5_QEI1_Msk (0x1ul << SCU_PNSSET5_QEI1_Pos) /*!< SCU_T::PNSSET5: QEI1 Mask */\r
+\r
+#define SCU_PNSSET5_ECAP0_Pos (20) /*!< SCU_T::PNSSET5: ECAP0 Position */\r
+#define SCU_PNSSET5_ECAP0_Msk (0x1ul << SCU_PNSSET5_ECAP0_Pos) /*!< SCU_T::PNSSET5: ECAP0 Mask */\r
+\r
+#define SCU_PNSSET5_ECAP1_Pos (21) /*!< SCU_T::PNSSET5: ECAP1 Position */\r
+#define SCU_PNSSET5_ECAP1_Msk (0x1ul << SCU_PNSSET5_ECAP1_Pos) /*!< SCU_T::PNSSET5: ECAP1 Mask */\r
+\r
+#define SCU_PNSSET5_TRNG_Pos (25) /*!< SCU_T::PNSSET5: TRNG Position */\r
+#define SCU_PNSSET5_TRNG_Msk (0x1ul << SCU_PNSSET5_TRNG_Pos) /*!< SCU_T::PNSSET5: TRNG Mask */\r
+\r
+#define SCU_PNSSET6_USBD_Pos (0) /*!< SCU_T::PNSSET6: USBD Position */\r
+#define SCU_PNSSET6_USBD_Msk (0x1ul << SCU_PNSSET6_USBD_Pos) /*!< SCU_T::PNSSET6: USBD Mask */\r
+\r
+#define SCU_PNSSET6_USCI0_Pos (16) /*!< SCU_T::PNSSET6: USCI0 Position */\r
+#define SCU_PNSSET6_USCI0_Msk (0x1ul << SCU_PNSSET6_USCI0_Pos) /*!< SCU_T::PNSSET6: USCI0 Mask */\r
+\r
+#define SCU_PNSSET6_USCI1_Pos (17) /*!< SCU_T::PNSSET6: USCI1 Position */\r
+#define SCU_PNSSET6_USCI1_Msk (0x1ul << SCU_PNSSET6_USCI1_Pos) /*!< SCU_T::PNSSET6: USCI1 Mask */\r
+\r
+#define SCU_IONSSET_PA_Pos (0) /*!< SCU_T::IONSSET: PA Position */\r
+#define SCU_IONSSET_PA_Msk (0x1ul << SCU_IONSSET_PA_Pos) /*!< SCU_T::IONSSET: PA Mask */\r
+\r
+#define SCU_IONSSET_PB_Pos (1) /*!< SCU_T::IONSSET: PB Position */\r
+#define SCU_IONSSET_PB_Msk (0x1ul << SCU_IONSSET_PB_Pos) /*!< SCU_T::IONSSET: PB Mask */\r
+\r
+#define SCU_IONSSET_PC_Pos (2) /*!< SCU_T::IONSSET: PC Position */\r
+#define SCU_IONSSET_PC_Msk (0x1ul << SCU_IONSSET_PC_Pos) /*!< SCU_T::IONSSET: PC Mask */\r
+\r
+#define SCU_IONSSET_PD_Pos (3) /*!< SCU_T::IONSSET: PD Position */\r
+#define SCU_IONSSET_PD_Msk (0x1ul << SCU_IONSSET_PD_Pos) /*!< SCU_T::IONSSET: PD Mask */\r
+\r
+#define SCU_IONSSET_PE_Pos (4) /*!< SCU_T::IONSSET: PE Position */\r
+#define SCU_IONSSET_PE_Msk (0x1ul << SCU_IONSSET_PE_Pos) /*!< SCU_T::IONSSET: PE Mask */\r
+\r
+#define SCU_IONSSET_PF_Pos (5) /*!< SCU_T::IONSSET: PF Position */\r
+#define SCU_IONSSET_PF_Msk (0x1ul << SCU_IONSSET_PF_Pos) /*!< SCU_T::IONSSET: PF Mask */\r
+\r
+#define SCU_IONSSET_PG_Pos (6) /*!< SCU_T::IONSSET: PG Position */\r
+#define SCU_IONSSET_PG_Msk (0x1ul << SCU_IONSSET_PG_Pos) /*!< SCU_T::IONSSET: PG Mask */\r
+\r
+#define SCU_IONSSET_PH_Pos (7) /*!< SCU_T::IONSSET: PH Position */\r
+#define SCU_IONSSET_PH_Msk (0x1ul << SCU_IONSSET_PH_Pos) /*!< SCU_T::IONSSET: PH Mask */\r
+\r
+#define SCU_SRAMNSSET_SECn_Pos (0) /*!< SCU_T::SRAMNSSET: SECn Position */\r
+#define SCU_SRAMNSSET_SECn_Msk (0xffful << SCU_SRAMNSSET_SECn_Pos) /*!< SCU_T::SRAMNSSET: SECn Mask */\r
+\r
+#define SCU_FNSADDR_FNSADDR_Pos (0) /*!< SCU_T::FNSADDR: FNSADDR Position */\r
+#define SCU_FNSADDR_FNSADDR_Msk (0xfffffffful << SCU_FNSADDR_FNSADDR_Pos) /*!< SCU_T::FNSADDR: FNSADDR Mask */\r
+\r
+#define SCU_SVIOIEN_APB0IEN_Pos (0) /*!< SCU_T::SVIOIEN: APB0IEN Position */\r
+#define SCU_SVIOIEN_APB0IEN_Msk (0x1ul << SCU_SVIOIEN_APB0IEN_Pos) /*!< SCU_T::SVIOIEN: APB0IEN Mask */\r
+\r
+#define SCU_SVIOIEN_APB1IEN_Pos (1) /*!< SCU_T::SVIOIEN: APB1IEN Position */\r
+#define SCU_SVIOIEN_APB1IEN_Msk (0x1ul << SCU_SVIOIEN_APB1IEN_Pos) /*!< SCU_T::SVIOIEN: APB1IEN Mask */\r
+\r
+#define SCU_SVIOIEN_GPIOIEN_Pos (4) /*!< SCU_T::SVIOIEN: GPIOIEN Position */\r
+#define SCU_SVIOIEN_GPIOIEN_Msk (0x1ul << SCU_SVIOIEN_GPIOIEN_Pos) /*!< SCU_T::SVIOIEN: GPIOIEN Mask */\r
+\r
+#define SCU_SVIOIEN_EBIIEN_Pos (5) /*!< SCU_T::SVIOIEN: EBIIEN Position */\r
+#define SCU_SVIOIEN_EBIIEN_Msk (0x1ul << SCU_SVIOIEN_EBIIEN_Pos) /*!< SCU_T::SVIOIEN: EBIIEN Mask */\r
+\r
+#define SCU_SVIOIEN_USBHIEN_Pos (6) /*!< SCU_T::SVIOIEN: USBHIEN Position */\r
+#define SCU_SVIOIEN_USBHIEN_Msk (0x1ul << SCU_SVIOIEN_USBHIEN_Pos) /*!< SCU_T::SVIOIEN: USBHIEN Mask */\r
+\r
+#define SCU_SVIOIEN_CRCIEN_Pos (7) /*!< SCU_T::SVIOIEN: CRCIEN Position */\r
+#define SCU_SVIOIEN_CRCIEN_Msk (0x1ul << SCU_SVIOIEN_CRCIEN_Pos) /*!< SCU_T::SVIOIEN: CRCIEN Mask */\r
+\r
+#define SCU_SVIOIEN_SDH0IEN_Pos (8) /*!< SCU_T::SVIOIEN: SDH0IEN Position */\r
+#define SCU_SVIOIEN_SDH0IEN_Msk (0x1ul << SCU_SVIOIEN_SDH0IEN_Pos) /*!< SCU_T::SVIOIEN: SDH0IEN Mask */\r
+\r
+#define SCU_SVIOIEN_PDMA0IEN_Pos (10) /*!< SCU_T::SVIOIEN: PDMA0IEN Position */\r
+#define SCU_SVIOIEN_PDMA0IEN_Msk (0x1ul << SCU_SVIOIEN_PDMA0IEN_Pos) /*!< SCU_T::SVIOIEN: PDMA0IEN Mask */\r
+\r
+#define SCU_SVIOIEN_PDMA1IEN_Pos (11) /*!< SCU_T::SVIOIEN: PDMA1IEN Position */\r
+#define SCU_SVIOIEN_PDMA1IEN_Msk (0x1ul << SCU_SVIOIEN_PDMA1IEN_Pos) /*!< SCU_T::SVIOIEN: PDMA1IEN Mask */\r
+\r
+#define SCU_SVIOIEN_SRAM0IEN_Pos (12) /*!< SCU_T::SVIOIEN: SRAM0IEN Position */\r
+#define SCU_SVIOIEN_SRAM0IEN_Msk (0x1ul << SCU_SVIOIEN_SRAM0IEN_Pos) /*!< SCU_T::SVIOIEN: SRAM0IEN Mask */\r
+\r
+#define SCU_SVIOIEN_SRAM1IEN_Pos (13) /*!< SCU_T::SVIOIEN: SRAM1IEN Position */\r
+#define SCU_SVIOIEN_SRAM1IEN_Msk (0x1ul << SCU_SVIOIEN_SRAM1IEN_Pos) /*!< SCU_T::SVIOIEN: SRAM1IEN Mask */\r
+\r
+#define SCU_SVIOIEN_FMCIEN_Pos (14) /*!< SCU_T::SVIOIEN: FMCIEN Position */\r
+#define SCU_SVIOIEN_FMCIEN_Msk (0x1ul << SCU_SVIOIEN_FMCIEN_Pos) /*!< SCU_T::SVIOIEN: FMCIEN Mask */\r
+\r
+#define SCU_SVIOIEN_FLASHIEN_Pos (15) /*!< SCU_T::SVIOIEN: FLASHIEN Position */\r
+#define SCU_SVIOIEN_FLASHIEN_Msk (0x1ul << SCU_SVIOIEN_FLASHIEN_Pos) /*!< SCU_T::SVIOIEN: FLASHIEN Mask */\r
+\r
+#define SCU_SVIOIEN_SCUIEN_Pos (16) /*!< SCU_T::SVIOIEN: SCUIEN Position */\r
+#define SCU_SVIOIEN_SCUIEN_Msk (0x1ul << SCU_SVIOIEN_SCUIEN_Pos) /*!< SCU_T::SVIOIEN: SCUIEN Mask */\r
+\r
+#define SCU_SVIOIEN_SYSIEN_Pos (17) /*!< SCU_T::SVIOIEN: SYSIEN Position */\r
+#define SCU_SVIOIEN_SYSIEN_Msk (0x1ul << SCU_SVIOIEN_SYSIEN_Pos) /*!< SCU_T::SVIOIEN: SYSIEN Mask */\r
+\r
+#define SCU_SVIOIEN_CRPTIEN_Pos (18) /*!< SCU_T::SVIOIEN: CRPTIEN Position */\r
+#define SCU_SVIOIEN_CRPTIEN_Msk (0x1ul << SCU_SVIOIEN_CRPTIEN_Pos) /*!< SCU_T::SVIOIEN: CRPTIEN Mask */\r
+\r
+#define SCU_SVINTSTS_APB0IF_Pos (0) /*!< SCU_T::SVINTSTS: APB0IF Position */\r
+#define SCU_SVINTSTS_APB0IF_Msk (0x1ul << SCU_SVINTSTS_APB0IF_Pos) /*!< SCU_T::SVINTSTS: APB0IF Mask */\r
+\r
+#define SCU_SVINTSTS_APB1IF_Pos (1) /*!< SCU_T::SVINTSTS: APB1IF Position */\r
+#define SCU_SVINTSTS_APB1IF_Msk (0x1ul << SCU_SVINTSTS_APB1IF_Pos) /*!< SCU_T::SVINTSTS: APB1IF Mask */\r
+\r
+#define SCU_SVINTSTS_GPIOIF_Pos (4) /*!< SCU_T::SVINTSTS: GPIOIF Position */\r
+#define SCU_SVINTSTS_GPIOIF_Msk (0x1ul << SCU_SVINTSTS_GPIOIF_Pos) /*!< SCU_T::SVINTSTS: GPIOIF Mask */\r
+\r
+#define SCU_SVINTSTS_EBIIF_Pos (5) /*!< SCU_T::SVINTSTS: EBIIF Position */\r
+#define SCU_SVINTSTS_EBIIF_Msk (0x1ul << SCU_SVINTSTS_EBIIF_Pos) /*!< SCU_T::SVINTSTS: EBIIF Mask */\r
+\r
+#define SCU_SVINTSTS_USBHIF_Pos (6) /*!< SCU_T::SVINTSTS: USBHIF Position */\r
+#define SCU_SVINTSTS_USBHIF_Msk (0x1ul << SCU_SVINTSTS_USBHIF_Pos) /*!< SCU_T::SVINTSTS: USBHIF Mask */\r
+\r
+#define SCU_SVINTSTS_CRCIF_Pos (7) /*!< SCU_T::SVINTSTS: CRCIF Position */\r
+#define SCU_SVINTSTS_CRCIF_Msk (0x1ul << SCU_SVINTSTS_CRCIF_Pos) /*!< SCU_T::SVINTSTS: CRCIF Mask */\r
+\r
+#define SCU_SVINTSTS_SDH0IF_Pos (8) /*!< SCU_T::SVINTSTS: SDH0IF Position */\r
+#define SCU_SVINTSTS_SDH0IF_Msk (0x1ul << SCU_SVINTSTS_SDH0IF_Pos) /*!< SCU_T::SVINTSTS: SDH0IF Mask */\r
+\r
+#define SCU_SVINTSTS_PDMA0IF_Pos (10) /*!< SCU_T::SVINTSTS: PDMA0IF Position */\r
+#define SCU_SVINTSTS_PDMA0IF_Msk (0x1ul << SCU_SVINTSTS_PDMA0IF_Pos) /*!< SCU_T::SVINTSTS: PDMA0IF Mask */\r
+\r
+#define SCU_SVINTSTS_PDMA1IF_Pos (11) /*!< SCU_T::SVINTSTS: PDMA1IF Position */\r
+#define SCU_SVINTSTS_PDMA1IF_Msk (0x1ul << SCU_SVINTSTS_PDMA1IF_Pos) /*!< SCU_T::SVINTSTS: PDMA1IF Mask */\r
+\r
+#define SCU_SVINTSTS_SRAM0IF_Pos (12) /*!< SCU_T::SVINTSTS: SRAM0IF Position */\r
+#define SCU_SVINTSTS_SRAM0IF_Msk (0x1ul << SCU_SVINTSTS_SRAM0IF_Pos) /*!< SCU_T::SVINTSTS: SRAM0IF Mask */\r
+\r
+#define SCU_SVINTSTS_SRAM1IF_Pos (13) /*!< SCU_T::SVINTSTS: SRAM1IF Position */\r
+#define SCU_SVINTSTS_SRAM1IF_Msk (0x1ul << SCU_SVINTSTS_SRAM1IF_Pos) /*!< SCU_T::SVINTSTS: SRAM1IF Mask */\r
+\r
+#define SCU_SVINTSTS_FMCIF_Pos (14) /*!< SCU_T::SVINTSTS: FMCIF Position */\r
+#define SCU_SVINTSTS_FMCIF_Msk (0x1ul << SCU_SVINTSTS_FMCIF_Pos) /*!< SCU_T::SVINTSTS: FMCIF Mask */\r
+\r
+#define SCU_SVINTSTS_FLASHIF_Pos (15) /*!< SCU_T::SVINTSTS: FLASHIF Position */\r
+#define SCU_SVINTSTS_FLASHIF_Msk (0x1ul << SCU_SVINTSTS_FLASHIF_Pos) /*!< SCU_T::SVINTSTS: FLASHIF Mask */\r
+\r
+#define SCU_SVINTSTS_SCUIF_Pos (16) /*!< SCU_T::SVINTSTS: SCUIF Position */\r
+#define SCU_SVINTSTS_SCUIF_Msk (0x1ul << SCU_SVINTSTS_SCUIF_Pos) /*!< SCU_T::SVINTSTS: SCUIF Mask */\r
+\r
+#define SCU_SVINTSTS_SYSIF_Pos (17) /*!< SCU_T::SVINTSTS: SYSIF Position */\r
+#define SCU_SVINTSTS_SYSIF_Msk (0x1ul << SCU_SVINTSTS_SYSIF_Pos) /*!< SCU_T::SVINTSTS: SYSIF Mask */\r
+\r
+#define SCU_SVINTSTS_CRPTIF_Pos (18) /*!< SCU_T::SVINTSTS: CRPTIF Position */\r
+#define SCU_SVINTSTS_CRPTIF_Msk (0x1ul << SCU_SVINTSTS_CRPTIF_Pos) /*!< SCU_T::SVINTSTS: CRPTIF Mask */\r
+\r
+#define SCU_APB0VSRC_MASTER_Pos (0) /*!< SCU_T::APB0VSRC: MASTER Position */\r
+#define SCU_APB0VSRC_MASTER_Msk (0xful << SCU_APB0VSRC_MASTER_Pos) /*!< SCU_T::APB0VSRC: MASTER Mask */\r
+\r
+#define SCU_APB0VA_VIOADDR_Pos (0) /*!< SCU_T::APB0VA: VIOADDR Position */\r
+#define SCU_APB0VA_VIOADDR_Msk (0xfffffffful << SCU_APB0VA_VIOADDR_Pos) /*!< SCU_T::APB0VA: VIOADDR Mask */\r
+\r
+#define SCU_APB1VSRC_MASTER_Pos (0) /*!< SCU_T::APB1VSRC: MASTER Position */\r
+#define SCU_APB1VSRC_MASTER_Msk (0xful << SCU_APB1VSRC_MASTER_Pos) /*!< SCU_T::APB1VSRC: MASTER Mask */\r
+\r
+#define SCU_APB1VA_VIOADDR_Pos (0) /*!< SCU_T::APB1VA: VIOADDR Position */\r
+#define SCU_APB1VA_VIOADDR_Msk (0xfffffffful << SCU_APB1VA_VIOADDR_Pos) /*!< SCU_T::APB1VA: VIOADDR Mask */\r
+\r
+#define SCU_GPIOVSRC_MASTER_Pos (0) /*!< SCU_T::GPIOVSRC: MASTER Position */\r
+#define SCU_GPIOVSRC_MASTER_Msk (0xful << SCU_GPIOVSRC_MASTER_Pos) /*!< SCU_T::GPIOVSRC: MASTER Mask */\r
+\r
+#define SCU_GPIOVA_VIOADDR_Pos (0) /*!< SCU_T::GPIOVA: VIOADDR Position */\r
+#define SCU_GPIOVA_VIOADDR_Msk (0xfffffffful << SCU_GPIOVA_VIOADDR_Pos) /*!< SCU_T::GPIOVA: VIOADDR Mask */\r
+\r
+#define SCU_EBIVSRC_MASTER_Pos (0) /*!< SCU_T::EBIVSRC: MASTER Position */\r
+#define SCU_EBIVSRC_MASTER_Msk (0xful << SCU_EBIVSRC_MASTER_Pos) /*!< SCU_T::EBIVSRC: MASTER Mask */\r
+\r
+#define SCU_EBIVA_VIOADDR_Pos (0) /*!< SCU_T::EBIVA: VIOADDR Position */\r
+#define SCU_EBIVA_VIOADDR_Msk (0xfffffffful << SCU_EBIVA_VIOADDR_Pos) /*!< SCU_T::EBIVA: VIOADDR Mask */\r
+\r
+#define SCU_USBHVSRC_MASTER_Pos (0) /*!< SCU_T::USBHVSRC: MASTER Position */\r
+#define SCU_USBHVSRC_MASTER_Msk (0xful << SCU_USBHVSRC_MASTER_Pos) /*!< SCU_T::USBHVSRC: MASTER Mask */\r
+\r
+#define SCU_USBHVA_VIOADDR_Pos (0) /*!< SCU_T::USBHVA: VIOADDR Position */\r
+#define SCU_USBHVA_VIOADDR_Msk (0xfffffffful << SCU_USBHVA_VIOADDR_Pos) /*!< SCU_T::USBHVA: VIOADDR Mask */\r
+\r
+#define SCU_CRCVSRC_MASTER_Pos (0) /*!< SCU_T::CRCVSRC: MASTER Position */\r
+#define SCU_CRCVSRC_MASTER_Msk (0xful << SCU_CRCVSRC_MASTER_Pos) /*!< SCU_T::CRCVSRC: MASTER Mask */\r
+\r
+#define SCU_CRCVA_VIOADDR_Pos (0) /*!< SCU_T::CRCVA: VIOADDR Position */\r
+#define SCU_CRCVA_VIOADDR_Msk (0xfffffffful << SCU_CRCVA_VIOADDR_Pos) /*!< SCU_T::CRCVA: VIOADDR Mask */\r
+\r
+#define SCU_SD0VSRC_MASTER_Pos (0) /*!< SCU_T::SD0VSRC: MASTER Position */\r
+#define SCU_SD0VSRC_MASTER_Msk (0xful << SCU_SD0VSRC_MASTER_Pos) /*!< SCU_T::SD0VSRC: MASTER Mask */\r
+\r
+#define SCU_SD0VA_VIOADDR_Pos (0) /*!< SCU_T::SD0VA: VIOADDR Position */\r
+#define SCU_SD0VA_VIOADDR_Msk (0xfffffffful << SCU_SD0VA_VIOADDR_Pos) /*!< SCU_T::SD0VA: VIOADDR Mask */\r
+\r
+#define SCU_PDMA0VSRC_MASTER_Pos (0) /*!< SCU_T::PDMA0VSRC: MASTER Position */\r
+#define SCU_PDMA0VSRC_MASTER_Msk (0xful << SCU_PDMA0VSRC_MASTER_Pos) /*!< SCU_T::PDMA0VSRC: MASTER Mask */\r
+\r
+#define SCU_PDMA0VA_VIOADDR_Pos (0) /*!< SCU_T::PDMA0VA: VIOADDR Position */\r
+#define SCU_PDMA0VA_VIOADDR_Msk (0xfffffffful << SCU_PDMA0VA_VIOADDR_Pos) /*!< SCU_T::PDMA0VA: VIOADDR Mask */\r
+\r
+#define SCU_PDMA1VSRC_MASTER_Pos (0) /*!< SCU_T::PDMA1VSRC: MASTER Position */\r
+#define SCU_PDMA1VSRC_MASTER_Msk (0xful << SCU_PDMA1VSRC_MASTER_Pos) /*!< SCU_T::PDMA1VSRC: MASTER Mask */\r
+\r
+#define SCU_PDMA1VA_VIOADDR_Pos (0) /*!< SCU_T::PDMA1VA: VIOADDR Position */\r
+#define SCU_PDMA1VA_VIOADDR_Msk (0xfffffffful << SCU_PDMA1VA_VIOADDR_Pos) /*!< SCU_T::PDMA1VA: VIOADDR Mask */\r
+\r
+#define SCU_SRAM0VSRC_MASTER_Pos (0) /*!< SCU_T::SRAM0VSRC: MASTER Position */\r
+#define SCU_SRAM0VSRC_MASTER_Msk (0xful << SCU_SRAM0VSRC_MASTER_Pos) /*!< SCU_T::SRAM0VSRC: MASTER Mask */\r
+\r
+#define SCU_SRAM0VA_VIOADDR_Pos (0) /*!< SCU_T::SRAM0VA: VIOADDR Position */\r
+#define SCU_SRAM0VA_VIOADDR_Msk (0xfffffffful << SCU_SRAM0VA_VIOADDR_Pos) /*!< SCU_T::SRAM0VA: VIOADDR Mask */\r
+\r
+#define SCU_SRAM1VSRC_MASTER_Pos (0) /*!< SCU_T::SRAM1VSRC: MASTER Position */\r
+#define SCU_SRAM1VSRC_MASTER_Msk (0xful << SCU_SRAM1VSRC_MASTER_Pos) /*!< SCU_T::SRAM1VSRC: MASTER Mask */\r
+\r
+#define SCU_SRAM1VA_VIOADDR_Pos (0) /*!< SCU_T::SRAM1VA: VIOADDR Position */\r
+#define SCU_SRAM1VA_VIOADDR_Msk (0xfffffffful << SCU_SRAM1VA_VIOADDR_Pos) /*!< SCU_T::SRAM1VA: VIOADDR Mask */\r
+\r
+#define SCU_FMCVSRC_MASTER_Pos (0) /*!< SCU_T::FMCVSRC: MASTER Position */\r
+#define SCU_FMCVSRC_MASTER_Msk (0xful << SCU_FMCVSRC_MASTER_Pos) /*!< SCU_T::FMCVSRC: MASTER Mask */\r
+\r
+#define SCU_FMCVA_VIOADDR_Pos (0) /*!< SCU_T::FMCVA: VIOADDR Position */\r
+#define SCU_FMCVA_VIOADDR_Msk (0xfffffffful << SCU_FMCVA_VIOADDR_Pos) /*!< SCU_T::FMCVA: VIOADDR Mask */\r
+\r
+#define SCU_FLASHVSRC_MASTER_Pos (0) /*!< SCU_T::FLASHVSRC: MASTER Position */\r
+#define SCU_FLASHVSRC_MASTER_Msk (0xful << SCU_FLASHVSRC_MASTER_Pos) /*!< SCU_T::FLASHVSRC: MASTER Mask */\r
+\r
+#define SCU_FLASHVA_VIOADDR_Pos (0) /*!< SCU_T::FLASHVA: VIOADDR Position */\r
+#define SCU_FLASHVA_VIOADDR_Msk (0xfffffffful << SCU_FLASHVA_VIOADDR_Pos) /*!< SCU_T::FLASHVA: VIOADDR Mask */\r
+\r
+#define SCU_SCUVSRC_MASTER_Pos (0) /*!< SCU_T::SCUVSRC: MASTER Position */\r
+#define SCU_SCUVSRC_MASTER_Msk (0xful << SCU_SCUVSRC_MASTER_Pos) /*!< SCU_T::SCUVSRC: MASTER Mask */\r
+\r
+#define SCU_SCUVA_VIOADDR_Pos (0) /*!< SCU_T::SCUVA: VIOADDR Position */\r
+#define SCU_SCUVA_VIOADDR_Msk (0xfffffffful << SCU_SCUVA_VIOADDR_Pos) /*!< SCU_T::SCUVA: VIOADDR Mask */\r
+\r
+#define SCU_SYSVSRC_MASTER_Pos (0) /*!< SCU_T::SYSVSRC: MASTER Position */\r
+#define SCU_SYSVSRC_MASTER_Msk (0xful << SCU_SYSVSRC_MASTER_Pos) /*!< SCU_T::SYSVSRC: MASTER Mask */\r
+\r
+#define SCU_SYSVA_VIOADDR_Pos (0) /*!< SCU_T::SYSVA: VIOADDR Position */\r
+#define SCU_SYSVA_VIOADDR_Msk (0xfffffffful << SCU_SYSVA_VIOADDR_Pos) /*!< SCU_T::SYSVA: VIOADDR Mask */\r
+\r
+#define SCU_CRPTVSRC_MASTER_Pos (0) /*!< SCU_T::CRPTVSRC: MASTER Position */\r
+#define SCU_CRPTVSRC_MASTER_Msk (0xful << SCU_CRPTVSRC_MASTER_Pos) /*!< SCU_T::CRPTVSRC: MASTER Mask */\r
+\r
+#define SCU_CRPTVA_VIOADDR_Pos (0) /*!< SCU_T::CRPTVA: VIOADDR Position */\r
+#define SCU_CRPTVA_VIOADDR_Msk (0xfffffffful << SCU_CRPTVA_VIOADDR_Pos) /*!< SCU_T::CRPTVA: VIOADDR Mask */\r
+\r
+#define SCU_NSMCTL_PRESCALE_Pos (0) /*!< SCU_T::NSMCTL: PRESCALE Position */\r
+#define SCU_NSMCTL_PRESCALE_Msk (0xfful << SCU_NSMCTL_PRESCALE_Pos) /*!< SCU_T::NSMCTL: PRESCALE Mask */\r
+\r
+#define SCU_NSMCTL_NSMIEN_Pos (8) /*!< SCU_T::NSMCTL: NSMIEN Position */\r
+#define SCU_NSMCTL_NSMIEN_Msk (0x1ul << SCU_NSMCTL_NSMIEN_Pos) /*!< SCU_T::NSMCTL: NSMIEN Mask */\r
+\r
+#define SCU_NSMCTL_AUTORLD_Pos (9) /*!< SCU_T::NSMCTL: AUTORLD Position */\r
+#define SCU_NSMCTL_AUTORLD_Msk (0x1ul << SCU_NSMCTL_AUTORLD_Pos) /*!< SCU_T::NSMCTL: AUTORLD Mask */\r
+\r
+#define SCU_NSMCTL_TMRMOD_Pos (10) /*!< SCU_T::NSMCTL: TMRMOD Position */\r
+#define SCU_NSMCTL_TMRMOD_Msk (0x1ul << SCU_NSMCTL_TMRMOD_Pos) /*!< SCU_T::NSMCTL: TMRMOD Mask */\r
+\r
+#define SCU_NSMCTL_IDLEON_Pos (12) /*!< SCU_T::NSMCTL: IDLEON Position */\r
+#define SCU_NSMCTL_IDLEON_Msk (0x1ul << SCU_NSMCTL_IDLEON_Pos) /*!< SCU_T::NSMCTL: IDLEON Mask */\r
+\r
+#define SCU_NSMCTL_DBGON_Pos (13) /*!< SCU_T::NSMCTL: DBGON Position */\r
+#define SCU_NSMCTL_DBGON_Msk (0x1ul << SCU_NSMCTL_DBGON_Pos) /*!< SCU_T::NSMCTL: DBGON Mask */\r
+\r
+#define SCU_NSMLOAD_RELOAD_Pos (0) /*!< SCU_T::NSMLOAD: RELOAD Position */\r
+#define SCU_NSMLOAD_RELOAD_Msk (0xfffffful << SCU_NSMLOAD_RELOAD_Pos) /*!< SCU_T::NSMLOAD: RELOAD Mask */\r
+\r
+#define SCU_NSMVAL_VALUE_Pos (0) /*!< SCU_T::NSMVAL: VALUE Position */\r
+#define SCU_NSMVAL_VALUE_Msk (0xfffffful << SCU_NSMVAL_VALUE_Pos) /*!< SCU_T::NSMVAL: VALUE Mask */\r
+\r
+#define SCU_NSMSTS_CURRNS_Pos (0) /*!< SCU_T::NSMSTS: CURRNS Position */\r
+#define SCU_NSMSTS_CURRNS_Msk (0x1ul << SCU_NSMSTS_CURRNS_Pos) /*!< SCU_T::NSMSTS: CURRNS Mask */\r
+\r
+#define SCU_NSMSTS_NSMIF_Pos (1) /*!< SCU_T::NSMSTS: NSMIF Position */\r
+#define SCU_NSMSTS_NSMIF_Msk (0x1ul << SCU_NSMSTS_NSMIF_Pos) /*!< SCU_T::NSMSTS: NSMIF Mask */\r
+\r
+/**@}*/ /* SCU_CONST */\r
+/**@}*/ /* end of SCU register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __SCU_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file sdh_reg.h\r
+ * @version V1.00\r
+ * @brief SDH register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __SDH_REG_H__\r
+#define __SDH_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- SD Card Host Interface -------------------------*/\r
+/**\r
+ @addtogroup SDH SD Card Host Interface(SDH)\r
+ Memory Mapped Structure for SDH Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+ /**\r
+ * @var SDH_T::FB\r
+ * Offset: 0x00~0x7C Shared Buffer (FIFO)\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |BUFFER |Shared Buffer\r
+ * | | |Buffer for DMA transfer\r
+ * @var SDH_T::DMACTL\r
+ * Offset: 0x400 DMA Control and Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |DMAEN |DMA Engine Enable Bit\r
+ * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.\r
+ * | | |0 = DMA Disabled.\r
+ * | | |1 = DMA Enabled.\r
+ * | | |Note: If target abort is occurred, DMAEN will be cleared.\r
+ * |[1] |DMARST |Software Engine Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset internal state machine and pointers\r
+ * | | |The contents of control register will not be cleared\r
+ * | | |This bit will auto be cleared after few clock cycles.\r
+ * | | |Note: The software reset DMA related registers.\r
+ * |[3] |SGEN |Scatter-gather Function Enable Bit\r
+ * | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory).\r
+ * | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table\r
+ * | | |The format of these Pads' will be described later).\r
+ * |[9] |DMABUSY |DMA Transfer Is in Progress\r
+ * | | |This bit indicates if SD Host is granted and doing DMA transfer or not.\r
+ * | | |0 = DMA transfer is not in progress.\r
+ * | | |1 = DMA transfer is in progress.\r
+ * @var SDH_T::DMASA\r
+ * Offset: 0x408 DMA Transfer Starting Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order\r
+ * | | |0 = PAD table is fetched in order.\r
+ * | | |1 = PAD table is fetched out of order.\r
+ * | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1.\r
+ * |[31:1] |DMASA |DMA Transfer Starting Address\r
+ * | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.\r
+ * | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.\r
+ * | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004.\r
+ * @var SDH_T::DMABCNT\r
+ * Offset: 0x40C DMA Transfer Byte Count Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[25:0] |BCNT |DMA Transfer Byte Count (Read Only)\r
+ * | | |This field indicates the remained byte count of DMA transfer\r
+ * | | |The value of this field is valid only when DMA is busy; otherwise, it is 0.\r
+ * @var SDH_T::DMAINTEN\r
+ * Offset: 0x410 DMA Interrupt Enable Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit\r
+ * | | |0 = Target abort interrupt generation Disabled during DMA transfer.\r
+ * | | |1 = Target abort interrupt generation Enabled during DMA transfer.\r
+ * |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit\r
+ * | | |0 = Interrupt generation Disabled when wrong EOT is encountered.\r
+ * | | |1 = Interrupt generation Enabled when wrong EOT is encountered.\r
+ * @var SDH_T::DMAINTSTS\r
+ * Offset: 0x414 DMA Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag\r
+ * | | |0 = No bus ERROR response received.\r
+ * | | |1 = Bus ERROR response received.\r
+ * | | |Note1: This bit is read only, but can be cleared by writing '1' to it.\r
+ * | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened\r
+ * | | |DMA will stop transfer and respond this event and then go to IDLE state\r
+ * | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again.\r
+ * |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag\r
+ * | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.\r
+ * | | |0 = No EOT encountered before DMA transfer finished.\r
+ * | | |1 = EOT encountered before DMA transfer finished.\r
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.\r
+ * @var SDH_T::GCTL\r
+ * Offset: 0x800 Global Control and Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |GCTLRST |Software Engine Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset SD host\r
+ * | | |The contents of control register will not be cleared\r
+ * | | |This bit will auto cleared after reset complete.\r
+ * |[1] |SDEN |Secure Digital Functionality Enable Bit\r
+ * | | |0 = SD functionality disabled.\r
+ * | | |1 = SD functionality enabled.\r
+ * @var SDH_T::GINTEN\r
+ * Offset: 0x804 Global Interrupt Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit\r
+ * | | |0 = DMA READ/WRITE target abort interrupt generation disabled.\r
+ * | | |1 = DMA READ/WRITE target abort interrupt generation enabled.\r
+ * @var SDH_T::GINTSTS\r
+ * Offset: 0x808 Global Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)\r
+ * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation\r
+ * | | |When Target Abort is occurred, please reset all engine.\r
+ * | | |0 = No bus ERROR response received.\r
+ * | | |1 = Bus ERROR response received.\r
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.\r
+ * @var SDH_T::CTL\r
+ * Offset: 0x820 SD Control and Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |COEN |Command Output Enable Bit\r
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)\r
+ * | | |1 = Enabled, SD host will output a command to SD card.\r
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).\r
+ * |[1] |RIEN |Response Input Enable Bit\r
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)\r
+ * | | |1 = Enabled, SD host will wait to receive a response from SD card.\r
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).\r
+ * |[2] |DIEN |Data Input Enable Bit\r
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)\r
+ * | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card.\r
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).\r
+ * |[3] |DOEN |Data Output Enable Bit\r
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)\r
+ * | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card.\r
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).\r
+ * |[4] |R2EN |Response R2 Input Enable Bit\r
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)\r
+ * | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7).\r
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).\r
+ * |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit\r
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)\r
+ * | | |1 = Enabled, SD host will output 74 clock cycles to SD card.\r
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).\r
+ * |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit\r
+ * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)\r
+ * | | |1 = Enabled, SD host will output 8 clock cycles.\r
+ * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).\r
+ * |[7] |CLKKEEP0 |SD Clock Enable Control for Port 0\r
+ * | | |0 = SD host decided when to output clock and when to disable clock output automatically.\r
+ * | | |1 = SD clock always keeps free running.\r
+ * |[13:8] |CMDCODE |SD Command Code\r
+ * | | |This register contains the SD command code (0x00 ~ 0x3F).\r
+ * |[14] |CTLRST |Software Engine Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the internal state machine and counters\r
+ * | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2EN will be cleared)\r
+ * | | |This bit will be auto cleared after few clock cycles.\r
+ * |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection)\r
+ * | | |0 = Data bus width is 1-bit.\r
+ * | | |1 = Data bus width is 4-bit.\r
+ * |[23:16] |BLKCNT |Block Counts to Be Transferred or Received\r
+ * | | |This field contains the block counts for data-in and data-out transfer\r
+ * | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance\r
+ * | | |Don't fill 0x0 to this field.\r
+ * | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).\r
+ * |[27:24] |SDNWR |NWR Parameter for Block Write Operation\r
+ * | | |This value indicates the NWR parameter for data block write operation in SD clock counts\r
+ * | | |The actual clock cycle will be SDNWR+1.\r
+ * @var SDH_T::CMDARG\r
+ * Offset: 0x824 SD Command Argument Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ARGUMENT |SD Command Argument\r
+ * | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card\r
+ * | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.\r
+ * @var SDH_T::INTEN\r
+ * Offset: 0x828 SD Interrupt Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit\r
+ * | | |0 = SD host will not generate interrupt when data-in (out) transfer done.\r
+ * | | |1 = SD host will generate interrupt when data-in (out) transfer done.\r
+ * |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit\r
+ * | | |0 = SD host will not generate interrupt when CRC7, CRC16 and CRC status is error.\r
+ * | | |1 = SD host will generate interrupt when CRC7, CRC16 and CRC status is error.\r
+ * |[8] |CDIEN0 |SD0 Card Detection Interrupt Enable Bit\r
+ * | | |Enable/Disable interrupts generation of SD controller when card 0 is inserted or removed.\r
+ * | | |0 = SD card detection interrupt Disabled.\r
+ * | | |1 = SD card detection interrupt Enabled.\r
+ * |[12] |RTOIEN |Response Time-out Interrupt Enable Bit\r
+ * | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out\r
+ * | | |Time-out value is specified at TOUT register.\r
+ * | | |0 = Response time-out interrupt Disabled.\r
+ * | | |1 = Response time-out interrupt Enabled.\r
+ * |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit\r
+ * | | |Enable/Disable interrupts generation of SD controller when data input time-out\r
+ * | | |Time-out value is specified at TOUT register.\r
+ * | | |0 = Data input time-out interrupt Disabled.\r
+ * | | |1 = Data input time-out interrupt Enabled.\r
+ * |[14] |WKIEN |Wake-up Signal Generating Enable Bit\r
+ * | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.\r
+ * | | |0 = Wake-up signal generating Disabled.\r
+ * | | |1 = Wake-up signal generating Enabled.\r
+ * |[30] |CDSRC0 |SD0 Card Detect Source Selection\r
+ * | | |0 = From SD0 card's DAT3 pin.\r
+ * | | |Host need clock to got data on pin DAT3\r
+ * | | |Please make sure CLKKEEP0 (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin.\r
+ * | | |1 = From GPIO pin.\r
+ * @var SDH_T::INTSTS\r
+ * Offset: 0x82C SD Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only)\r
+ * | | |This bit indicates that SD host has finished all data-in or data-out block transfer\r
+ * | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.\r
+ * | | |0 = Not finished yet.\r
+ * | | |1 = Done.\r
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.\r
+ * |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)\r
+ * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer\r
+ * | | |When CRC error is occurred, software should reset SD engine\r
+ * | | |Some response (ex\r
+ * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag\r
+ * | | |In this condition, software should ignore CRC error and clears this bit manually.\r
+ * | | |0 = No CRC error is occurred.\r
+ * | | |1 = CRC error is occurred.\r
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.\r
+ * |[2] |CRC7 |CRC7 Check Status (Read Only)\r
+ * | | |SD host will check CRC7 correctness during each response in\r
+ * | | |If that response does not contain CRC7 information (ex\r
+ * | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.\r
+ * | | |0 = Fault.\r
+ * | | |1 = OK.\r
+ * |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only)\r
+ * | | |SD host will check CRC16 correctness after data-in transfer.\r
+ * | | |0 = Fault.\r
+ * | | |1 = OK.\r
+ * |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only)\r
+ * | | |SD host will record CRC status of data-out transfer\r
+ * | | |Software could use this value to identify what type of error is during data-out transfer.\r
+ * | | |010 = Positive CRC status.\r
+ * | | |101 = Negative CRC status.\r
+ * | | |111 = SD card programming error occurs.\r
+ * |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only)\r
+ * | | |This bit is the DAT0 pin status of current selected SD port.\r
+ * |[8] |CDIF0 |SD0 Card Detection Interrupt Flag (Read Only)\r
+ * | | |This bit indicates that SD card 0 is inserted or removed\r
+ * | | |Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active.\r
+ * | | |0 = No card is inserted or removed.\r
+ * | | |1 = There is a card inserted in or removed from SD0.\r
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.\r
+ * |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only)\r
+ * | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).\r
+ * | | |0 = Not time-out.\r
+ * | | |1 = Response time-out.\r
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.\r
+ * |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only)\r
+ * | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit).\r
+ * | | |0 = Not time-out.\r
+ * | | |1 = Data input time-out.\r
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.\r
+ * |[16] |CDSTS0 |Card Detect Status of SD0 (Read Only)\r
+ * | | |This bit indicates the card detect pin status of SD0, and is used for card detection\r
+ * | | |When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal.\r
+ * | | |If CDSRC0 (SDH_INTEN[30]) = 0, to select DAT3 for card detection:.\r
+ * | | |0 = Card removed.\r
+ * | | |1 = Card inserted.\r
+ * | | |If CDSRC0 (SDH_INTEN[30]) = 1, to select GPIO for card detection:.\r
+ * | | |0 = Card inserted.\r
+ * | | |1 = Card removed.\r
+ * |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only)\r
+ * | | |This bit indicates the DAT1 pin status of SD port.\r
+ * @var SDH_T::RESP0\r
+ * Offset: 0x830 SD Receiving Response Token Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |RESPTK0 |SD Receiving Response Token 0\r
+ * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set\r
+ * | | |This field contains response bit 47-16 of the response token.\r
+ * @var SDH_T::RESP1\r
+ * Offset: 0x834 SD Receiving Response Token Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |RESPTK1 |SD Receiving Response Token 1\r
+ * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set\r
+ * | | |This register contains the bit 15-8 of the response token.\r
+ * @var SDH_T::BLEN\r
+ * Offset: 0x838 SD Block Length Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit\r
+ * | | |An 11-bit value specifies the SD transfer byte count of a block\r
+ * | | |The actual byte count is equal to BLKLEN+1.\r
+ * | | |Note: The default SD block length is 512 bytes\r
+ * @var SDH_T::TOUT\r
+ * Offset: 0x83C SD Response/Data-in Time-out Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[23:0] |TOUT |SD Response/Data-in Time-out Value\r
+ * | | |A 24-bit value specifies the time-out counts of response and data input\r
+ * | | |SD host controller will wait start bit of response or data-in until this value reached\r
+ * | | |The time period depends on SD engine clock frequency\r
+ * | | |Do not write a small number into this field, or you may never get response or data due to time-out.\r
+ * | | |Note: Filling 0x0 into this field will disable hardware time-out function.\r
+ */\r
+\r
+ __IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */\r
+ __I uint32_t RESERVE0[224];\r
+ __IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */\r
+ __I uint32_t RESERVE1[1];\r
+ __IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */\r
+ __I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */\r
+ __IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */\r
+ __IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */\r
+ __I uint32_t RESERVE2[250];\r
+ __IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */\r
+ __IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */\r
+ __IO uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */\r
+ __I uint32_t RESERVE3[5];\r
+ __IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */\r
+ __IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */\r
+ __IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */\r
+ __IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */\r
+ __I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */\r
+ __I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */\r
+ __IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */\r
+ __IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */\r
+\r
+} SDH_T;\r
+\r
+/**\r
+ @addtogroup SDH_CONST SDH Bit Field Definition\r
+ Constant Definitions for SDH Controller\r
+@{ */\r
+\r
+#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */\r
+#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */\r
+\r
+#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */\r
+#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */\r
+\r
+#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */\r
+#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */\r
+\r
+#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */\r
+#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */\r
+\r
+#define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */\r
+#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */\r
+\r
+#define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */\r
+#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */\r
+\r
+#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */\r
+#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */\r
+\r
+#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */\r
+#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */\r
+\r
+#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */\r
+#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */\r
+\r
+#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */\r
+#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */\r
+\r
+#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */\r
+#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */\r
+\r
+#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */\r
+#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */\r
+\r
+#define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */\r
+#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */\r
+\r
+#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */\r
+#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */\r
+\r
+#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */\r
+#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */\r
+\r
+#define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */\r
+#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */\r
+\r
+#define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */\r
+#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */\r
+\r
+#define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */\r
+#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */\r
+\r
+#define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */\r
+#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */\r
+\r
+#define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */\r
+#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */\r
+\r
+#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */\r
+#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */\r
+\r
+#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */\r
+#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */\r
+\r
+#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */\r
+#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */\r
+\r
+#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */\r
+#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */\r
+\r
+#define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */\r
+#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */\r
+\r
+#define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */\r
+#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */\r
+\r
+#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */\r
+#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */\r
+\r
+#define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */\r
+#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */\r
+\r
+#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */\r
+#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */\r
+\r
+#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */\r
+#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */\r
+\r
+#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */\r
+#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */\r
+\r
+#define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */\r
+#define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */\r
+\r
+#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */\r
+#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */\r
+\r
+#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */\r
+#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */\r
+\r
+#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */\r
+#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */\r
+\r
+#define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */\r
+#define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */\r
+\r
+#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */\r
+#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */\r
+\r
+#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */\r
+#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */\r
+\r
+#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */\r
+#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */\r
+\r
+#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */\r
+#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */\r
+\r
+#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */\r
+#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */\r
+\r
+#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */\r
+#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */\r
+\r
+#define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */\r
+#define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */\r
+\r
+#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */\r
+#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */\r
+\r
+#define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */\r
+#define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */\r
+\r
+#define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */\r
+#define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */\r
+\r
+#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */\r
+#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */\r
+\r
+#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */\r
+#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */\r
+\r
+#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */\r
+#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */\r
+\r
+#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */\r
+#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */\r
+\r
+#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */\r
+#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */\r
+\r
+/**@}*/ /* SDH_CONST */\r
+/**@}*/ /* end of SDH register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __SDH_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file spi_reg.h\r
+ * @version V1.00\r
+ * @brief SPI register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __SPI_REG_H__\r
+#define __SPI_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Serial Peripheral Interface Controller -------------------------*/\r
+/**\r
+ @addtogroup SPI Serial Peripheral Interface Controller(SPI)\r
+ Memory Mapped Structure for SPI Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var SPI_T::CTL\r
+ * Offset: 0x00 SPI Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SPIEN |SPI Transfer Control Enable Bit\r
+ * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1\r
+ * | | |In Slave mode, this device is ready to receive data when this bit is set to 1.\r
+ * | | |0 = Transfer control Disabled.\r
+ * | | |1 = Transfer control Enabled.\r
+ * | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.\r
+ * |[1] |RXNEG |Receive on Negative Edge\r
+ * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.\r
+ * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.\r
+ * |[2] |TXNEG |Transmit on Negative Edge\r
+ * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.\r
+ * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock.\r
+ * |[3] |CLKPOL |Clock Polarity\r
+ * | | |0 = SPI bus clock is idle low.\r
+ * | | |1 = SPI bus clock is idle high.\r
+ * |[7:4] |SUSPITV |Suspend Interval (Master Only)\r
+ * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer\r
+ * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word\r
+ * | | |The default value is 0x3\r
+ * | | |The period of the suspend interval is obtained according to the following equation.\r
+ * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\r
+ * | | |Example:\r
+ * | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle.\r
+ * | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle.\r
+ * | | |.....\r
+ * | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle.\r
+ * | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle.\r
+ * |[12:8] |DWIDTH |Data Width\r
+ * | | |This field specifies how many bits can be transmitted / received in one transaction\r
+ * | | |The minimum bit length is 8 bits and can up to 32 bits.\r
+ * | | |DWIDTH = 0x08 .... 8 bits.\r
+ * | | |DWIDTH = 0x09 .... 9 bits.\r
+ * | | |.....\r
+ * | | |DWIDTH = 0x1F .... 31 bits.\r
+ * | | |DWIDTH = 0x00 .... 32 bits.\r
+ * | | |Note: For SPI0~SPI3, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode\r
+ * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI0~SPI3.\r
+ * |[13] |LSB |Send LSB First\r
+ * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.\r
+ * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).\r
+ * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit\r
+ * | | |This bit is used to select full-duplex or half-duplex for SPI transfer\r
+ * | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.\r
+ * | | |0 = SPI operates in full-duplex transfer.\r
+ * | | |1 = SPI operates in half-duplex transfer.\r
+ * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)\r
+ * | | |This bit field is only available in Master mode\r
+ * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.\r
+ * | | |0 = Receive-only mode Disabled.\r
+ * | | |1 = Receive-only mode Enabled.\r
+ * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit\r
+ * | | |0 = SPI unit transfer interrupt Disabled.\r
+ * | | |1 = SPI unit transfer interrupt Enabled.\r
+ * |[18] |SLAVE |Slave Mode Control\r
+ * | | |0 = Master mode.\r
+ * | | |1 = Slave mode.\r
+ * |[19] |REORDER |Byte Reorder Function Enable Bit\r
+ * | | |0 = Byte Reorder function Disabled.\r
+ * | | |1 = Byte Reorder function Enabled\r
+ * | | |A byte suspend interval will be inserted among each byte\r
+ * | | |The period of the byte suspend interval depends on the setting of SUSPITV.\r
+ * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.\r
+ * |[20] |DATDIR |Data Port Direction Control\r
+ * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer\r
+ * | | |0 = SPI data is input direction.\r
+ * | | |1 = SPI data is output direction.\r
+ * @var SPI_T::CLKDIV\r
+ * Offset: 0x04 SPI Clock Divider Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[8:0] |DIVIDER |Clock Divider\r
+ * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master\r
+ * | | |The frequency is obtained according to the following equation.\r
+ * | | |where\r
+ * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\r
+ * | | |Note: Not supported in I2S mode.\r
+ * @var SPI_T::SSCTL\r
+ * Offset: 0x08 SPI Slave Select Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SS |Slave Selection Control (Master Only)\r
+ * | | |If AUTOSS bit is cleared to 0,\r
+ * | | |0 = set the SPIx_SS line to inactive state.\r
+ * | | |1 = set the SPIx_SS line to active state.\r
+ * | | |If the AUTOSS bit is set to 1,\r
+ * | | |0 = Keep the SPIx_SS line at inactive state.\r
+ * | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time\r
+ * | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]).\r
+ * |[2] |SSACTPOL |Slave Selection Active Polarity\r
+ * | | |This bit defines the active polarity of slave selection signal (SPIx_SS).\r
+ * | | |0 = The slave selection signal SPIx_SS is active low.\r
+ * | | |1 = The slave selection signal SPIx_SS is active high.\r
+ * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)\r
+ * | | |0 = Automatic slave selection function Disabled\r
+ * | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]).\r
+ * | | |1 = Automatic slave selection function Enabled.\r
+ * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit\r
+ * | | |0 = Slave mode bit count error interrupt Disabled.\r
+ * | | |1 = Slave mode bit count error interrupt Enabled.\r
+ * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit\r
+ * | | |0 = Slave mode TX under run interrupt Disabled.\r
+ * | | |1 = Slave mode TX under run interrupt Enabled.\r
+ * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit\r
+ * | | |0 = Slave select active interrupt Disabled.\r
+ * | | |1 = Slave select active interrupt Enabled.\r
+ * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit\r
+ * | | |0 = Slave select inactive interrupt Disabled.\r
+ * | | |1 = Slave select inactive interrupt Enabled.\r
+ * @var SPI_T::PDMACTL\r
+ * Offset: 0x0C SPI PDMA Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |TXPDMAEN |Transmit PDMA Enable Bit\r
+ * | | |0 = Transmit PDMA function Disabled.\r
+ * | | |1 = Transmit PDMA function Enabled.\r
+ * | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function\r
+ * | | |User can enable TX PDMA function firstly or enable both functions simultaneously.\r
+ * |[1] |RXPDMAEN |Receive PDMA Enable Bit\r
+ * | | |0 = Receive PDMA function Disabled.\r
+ * | | |1 = Receive PDMA function Enabled.\r
+ * |[2] |PDMARST |PDMA Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.\r
+ * @var SPI_T::FIFOCTL\r
+ * Offset: 0x10 SPI FIFO Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RXRST |Receive Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset receive FIFO pointer and receive circuit\r
+ * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1\r
+ * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1\r
+ * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.\r
+ * |[1] |TXRST |Transmit Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset transmit FIFO pointer and transmit circuit\r
+ * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1\r
+ * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1\r
+ * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.\r
+ * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.\r
+ * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit\r
+ * | | |0 = RX FIFO threshold interrupt Disabled.\r
+ * | | |1 = RX FIFO threshold interrupt Enabled.\r
+ * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit\r
+ * | | |0 = TX FIFO threshold interrupt Disabled.\r
+ * | | |1 = TX FIFO threshold interrupt Enabled.\r
+ * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit\r
+ * | | |0 = Receive time-out interrupt Disabled.\r
+ * | | |1 = Receive time-out interrupt Enabled.\r
+ * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit\r
+ * | | |0 = Receive FIFO overrun interrupt Disabled.\r
+ * | | |1 = Receive FIFO overrun interrupt Enabled.\r
+ * |[6] |TXUFPOL |TX Underflow Data Polarity\r
+ * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.\r
+ * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.\r
+ * | | |Note:\r
+ * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\r
+ * | | |2. This bit should be set as 0 in I2S mode.\r
+ * | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward\r
+ * | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.\r
+ * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit\r
+ * | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1\r
+ * | | |This bit is used to enable the TX underflow interrupt.\r
+ * | | |0 = Slave TX underflow interrupt Disabled.\r
+ * | | |1 = Slave TX underflow interrupt Enabled.\r
+ * |[8] |RXFBCLR |Receive FIFO Buffer Clear\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear receive FIFO pointer\r
+ * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1\r
+ * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.\r
+ * | | |Note: The RX shift register will not be cleared.\r
+ * |[9] |TXFBCLR |Transmit FIFO Buffer Clear\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear transmit FIFO pointer\r
+ * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1\r
+ * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.\r
+ * | | |Note: The TX shift register will not be cleared.\r
+ * |[26:24] |RXTH |Receive FIFO Threshold\r
+ * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0\r
+ * | | |For SPI0~SPI3, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.\r
+ * |[30:28] |TXTH |Transmit FIFO Threshold\r
+ * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0\r
+ * | | |For SPI0~SPI3, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.\r
+ * @var SPI_T::STATUS\r
+ * Offset: 0x14 SPI Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BUSY |Busy Status (Read Only)\r
+ * | | |0 = SPI controller is in idle state.\r
+ * | | |1 = SPI controller is in busy state.\r
+ * | | |The following listing are the bus busy conditions:\r
+ * | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0.\r
+ * | | |b\r
+ * | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.\r
+ * | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1.\r
+ * | | |d.\r
+ * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.\r
+ * | | |e.\r
+ * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.\r
+ * |[1] |UNITIF |Unit Transfer Interrupt Flag\r
+ * | | |0 = No transaction has been finished since this bit was cleared to 0.\r
+ * | | |1 = SPI controller has finished one unit transfer.\r
+ * | | |Note: This bit will be cleared by writing 1 to it.\r
+ * |[2] |SSACTIF |Slave Select Active Interrupt Flag\r
+ * | | |0 = Slave select active interrupt was cleared or not occurred.\r
+ * | | |1 = Slave select active interrupt event occurred.\r
+ * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.\r
+ * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag\r
+ * | | |0 = Slave select inactive interrupt was cleared or not occurred.\r
+ * | | |1 = Slave select inactive interrupt event occurred.\r
+ * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.\r
+ * |[4] |SSLINE |Slave Select Line Bus Status (Read Only)\r
+ * | | |0 = The slave select line status is 0.\r
+ * | | |1 = The slave select line status is 1.\r
+ * | | |Note: This bit is only available in Slave mode\r
+ * | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.\r
+ * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag\r
+ * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\r
+ * | | |0 = No Slave mode bit count error event.\r
+ * | | |1 = Slave mode bit count error event occurs.\r
+ * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state\r
+ * | | |This bit will be cleared by writing 1 to it.\r
+ * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag\r
+ * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\r
+ * | | |0 = No Slave TX under run event.\r
+ * | | |1 = Slave TX under run event occurs.\r
+ * | | |Note: This bit will be cleared by writing 1 to it.\r
+ * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)\r
+ * | | |0 = Receive FIFO buffer is not empty.\r
+ * | | |1 = Receive FIFO buffer is empty.\r
+ * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)\r
+ * | | |0 = Receive FIFO buffer is not full.\r
+ * | | |1 = Receive FIFO buffer is full.\r
+ * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)\r
+ * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.\r
+ * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.\r
+ * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag\r
+ * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\r
+ * | | |0 = No FIFO is overrun.\r
+ * | | |1 = Receive FIFO is overrun.\r
+ * | | |Note: This bit will be cleared by writing 1 to it.\r
+ * |[12] |RXTOIF |Receive Time-out Interrupt Flag\r
+ * | | |0 = No receive FIFO time-out event.\r
+ * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode\r
+ * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.\r
+ * | | |Note: This bit will be cleared by writing 1 to it.\r
+ * |[15] |SPIENSTS |SPI Enable Status (Read Only)\r
+ * | | |0 = The SPI controller is disabled.\r
+ * | | |1 = The SPI controller is enabled.\r
+ * | | |Note: The SPI peripheral clock is asynchronous with the system clock\r
+ * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.\r
+ * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)\r
+ * | | |0 = Transmit FIFO buffer is not empty.\r
+ * | | |1 = Transmit FIFO buffer is empty.\r
+ * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)\r
+ * | | |0 = Transmit FIFO buffer is not full.\r
+ * | | |1 = Transmit FIFO buffer is full.\r
+ * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)\r
+ * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.\r
+ * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.\r
+ * |[19] |TXUFIF |TX Underflow Interrupt Flag\r
+ * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\r
+ * | | |0 = No effect.\r
+ * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.\r
+ * | | |Note 1: This bit will be cleared by writing 1 to it.\r
+ * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.\r
+ * |[23] |TXRXRST |TX or RX Reset Status (Read Only)\r
+ * | | |0 = The reset function of TXRST or RXRST is done.\r
+ * | | |1 = Doing the reset function of TXRST or RXRST.\r
+ * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles\r
+ * | | |User can check the status of this bit to monitor the reset function is doing or done.\r
+ * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)\r
+ * | | |This bit field indicates the valid data count of receive FIFO buffer.\r
+ * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)\r
+ * | | |This bit field indicates the valid data count of transmit FIFO buffer.\r
+ * @var SPI_T::TX\r
+ * Offset: 0x20 SPI Data Transmit Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |TX |Data Transmit Register\r
+ * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers\r
+ * | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.\r
+ * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted\r
+ * | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer.\r
+ * | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]\r
+ * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section\r
+ * | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.\r
+ * @var SPI_T::RX\r
+ * Offset: 0x30 SPI Data Receive Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |RX |Data Receive Register (Read Only)\r
+ * | | |There are 4-level FIFO buffers in this controller.\r
+ * | | |The data receive register holds the data received from SPI data input pin.\r
+ * | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.\r
+ * @var SPI_T::I2SCTL\r
+ * Offset: 0x60 I2S Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |I2SEN |I2S Controller Enable Bit\r
+ * | | |0 = Disabled I2S mode.\r
+ * | | |1 = Enabled I2S mode.\r
+ * | | |Note:\r
+ * | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode.\r
+ * | | |2\r
+ * | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.\r
+ * |[1] |TXEN |Transmit Enable Bit\r
+ * | | |0 = Data transmit Disabled.\r
+ * | | |1 = Data transmit Enabled.\r
+ * |[2] |RXEN |Receive Enable Bit\r
+ * | | |0 = Data receive Disabled.\r
+ * | | |1 = Data receive Enabled.\r
+ * |[3] |MUTE |Transmit Mute Enable Bit\r
+ * | | |0 = Transmit data is shifted from buffer.\r
+ * | | |1 = Transmit channel zero.\r
+ * |[5:4] |WDWIDTH |Word Width\r
+ * | | |00 = data size is 8-bit.\r
+ * | | |01 = data size is 16-bit.\r
+ * | | |10 = data size is 24-bit.\r
+ * | | |11 = data size is 32-bit.\r
+ * |[6] |MONO |Monaural Data\r
+ * | | |0 = Data is stereo format.\r
+ * | | |1 = Data is monaural format.\r
+ * |[7] |ORDER |Stereo Data Order in FIFO\r
+ * | | |0 = Left channel data at high byte.\r
+ * | | |1 = Left channel data at low byte.\r
+ * |[8] |SLAVE |Slave Mode\r
+ * | | |I2S can operate as master or slave\r
+ * | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M2351 series to audio CODEC chip\r
+ * | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.\r
+ * | | |0 = Master mode.\r
+ * | | |1 = Slave mode.\r
+ * |[15] |MCLKEN |Master Clock Enable Bit\r
+ * | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.\r
+ * | | |0 = Master clock Disabled.\r
+ * | | |1 = Master clock Enabled.\r
+ * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit\r
+ * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1\r
+ * | | |This function is only available in transmit operation.\r
+ * | | |0 = Right channel zero cross detection Disabled.\r
+ * | | |1 = Right channel zero cross detection Enabled.\r
+ * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit\r
+ * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1\r
+ * | | |This function is only available in transmit operation.\r
+ * | | |0 = Left channel zero cross detection Disabled.\r
+ * | | |1 = Left channel zero cross detection Enabled.\r
+ * |[23] |RXLCH |Receive Left Channel Enable Bit\r
+ * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.\r
+ * | | |0 = Receive right channel data in Mono mode.\r
+ * | | |1 = Receive left channel data in Mono mode.\r
+ * |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit\r
+ * | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit\r
+ * | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.\r
+ * | | |0 = Interrupt Disabled.\r
+ * | | |1 = Interrupt Enabled.\r
+ * |[29:28] |FORMAT |Data Format Selection\r
+ * | | |00 = I2S data format.\r
+ * | | |01 = MSB justified data format.\r
+ * | | |10 = PCM mode A.\r
+ * | | |11 = PCM mode B.\r
+ * @var SPI_T::I2SCLK\r
+ * Offset: 0x64 I2S Clock Divider Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[6:0] |MCLKDIV |Master Clock Divider\r
+ * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices.\r
+ * | | |The frequency of master clock, F_MCLK, is determined by the following expressions:\r
+ * | | |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)).\r
+ * | | |If MCLKDIV = 0, F_MCLK = F_I2SCLK.\r
+ * | | |where\r
+ * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.\r
+ * | | |F_I2SCLK is the frequency of I2S peripheral clock.\r
+ * | | |In general, the master clock rate is 256 times sampling clock rate.\r
+ * |[17:8] |BCLKDIV |Bit Clock Divider\r
+ * | | |The I2S controller will generate bit clock in Master mode.\r
+ * | | |The clock frequency of bit clock, F_BCLK, is determined by the following expression:\r
+ * | | |F_BCLK = F_I2SCLK/(2x(BCLKDIV + 1)),\r
+ * | | |where\r
+ * | | |F_I2SCLK is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.\r
+ * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by F_I2SCLK/(BCLKDIV/2 + 1).\r
+ * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.\r
+ * @var SPI_T::I2SSTS\r
+ * Offset: 0x68 I2S Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[4] |RIGHT |Right Channel (Read Only)\r
+ * | | |This bit indicates the current transmit data is belong to which channel.\r
+ * | | |0 = Left channel.\r
+ * | | |1 = Right channel.\r
+ * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)\r
+ * | | |0 = Receive FIFO buffer is not empty.\r
+ * | | |1 = Receive FIFO buffer is empty.\r
+ * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)\r
+ * | | |0 = Receive FIFO buffer is not full.\r
+ * | | |1 = Receive FIFO buffer is full.\r
+ * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)\r
+ * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.\r
+ * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.\r
+ * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.\r
+ * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag\r
+ * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\r
+ * | | |Note: This bit will be cleared by writing 1 to it.\r
+ * |[12] |RXTOIF |Receive Time-out Interrupt Flag\r
+ * | | |0 = No receive FIFO time-out event.\r
+ * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode\r
+ * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.\r
+ * | | |Note: This bit will be cleared by writing 1 to it.\r
+ * |[15] |I2SENSTS |I2S Enable Status (Read Only)\r
+ * | | |0 = The SPI/I2S control logic is disabled.\r
+ * | | |1 = The SPI/I2S control logic is enabled.\r
+ * | | |Note: The SPI peripheral clock is asynchronous with the system clock\r
+ * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.\r
+ * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)\r
+ * | | |0 = Transmit FIFO buffer is not empty.\r
+ * | | |1 = Transmit FIFO buffer is empty.\r
+ * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)\r
+ * | | |0 = Transmit FIFO buffer is not full.\r
+ * | | |1 = Transmit FIFO buffer is full.\r
+ * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)\r
+ * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.\r
+ * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.\r
+ * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.\r
+ * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag\r
+ * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.\r
+ * | | |Note: This bit will be cleared by writing 1 to it.\r
+ * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag\r
+ * | | |0 = No zero cross event occurred on right channel.\r
+ * | | |1 = Zero cross event occurred on right channel.\r
+ * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag\r
+ * | | |0 = No zero cross event occurred on left channel.\r
+ * | | |1 = Zero cross event occurred on left channel.\r
+ * |[23] |TXRXRST |TX or RX Reset Status (Read Only)\r
+ * | | |0 = The reset function of TXRST or RXRST is done.\r
+ * | | |1 = Doing the reset function of TXRST or RXRST.\r
+ * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles\r
+ * | | |User can check the status of this bit to monitor the reset function is doing or done.\r
+ * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)\r
+ * | | |This bit field indicates the valid data count of receive FIFO buffer.\r
+ * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)\r
+ * | | |This bit field indicates the valid data count of transmit FIFO buffer.\r
+ */\r
+\r
+ __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */\r
+ __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */\r
+ __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */\r
+ __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */\r
+ __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */\r
+ __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */\r
+ __I uint32_t RESERVE0[2];\r
+ __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */\r
+ __I uint32_t RESERVE1[3];\r
+ __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */\r
+ __I uint32_t RESERVE2[11];\r
+ __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */\r
+ __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */\r
+ __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */\r
+\r
+} SPI_T;\r
+\r
+/**\r
+ @addtogroup SPI_CONST SPI Bit Field Definition\r
+ Constant Definitions for SPI Controller\r
+@{ */\r
+\r
+#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */\r
+#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */\r
+\r
+#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */\r
+#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */\r
+\r
+#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */\r
+#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */\r
+\r
+#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */\r
+#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */\r
+\r
+#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */\r
+#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */\r
+\r
+#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */\r
+#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */\r
+\r
+#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */\r
+#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */\r
+\r
+#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */\r
+#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */\r
+\r
+#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */\r
+#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */\r
+\r
+#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */\r
+#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */\r
+\r
+#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */\r
+#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */\r
+\r
+#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */\r
+#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */\r
+\r
+#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */\r
+#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */\r
+\r
+#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */\r
+#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */\r
+\r
+#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */\r
+#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */\r
+\r
+#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */\r
+#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */\r
+\r
+#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */\r
+#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */\r
+\r
+#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */\r
+#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */\r
+\r
+#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */\r
+#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */\r
+\r
+#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */\r
+#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */\r
+\r
+#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */\r
+#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */\r
+\r
+#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */\r
+#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */\r
+\r
+#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */\r
+#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */\r
+\r
+#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */\r
+#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */\r
+\r
+#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */\r
+#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */\r
+\r
+#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */\r
+#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */\r
+\r
+#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */\r
+#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */\r
+\r
+#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */\r
+#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */\r
+\r
+#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */\r
+#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */\r
+\r
+#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */\r
+#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */\r
+\r
+#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */\r
+#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */\r
+\r
+#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */\r
+#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */\r
+\r
+#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */\r
+#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */\r
+\r
+#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */\r
+#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */\r
+\r
+#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */\r
+#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */\r
+\r
+#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */\r
+#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */\r
+\r
+#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */\r
+#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */\r
+\r
+#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */\r
+#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */\r
+\r
+#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */\r
+#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */\r
+\r
+#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */\r
+#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */\r
+\r
+#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */\r
+#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */\r
+\r
+#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */\r
+#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */\r
+\r
+#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */\r
+#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */\r
+\r
+#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */\r
+#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */\r
+\r
+#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */\r
+#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */\r
+\r
+#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */\r
+#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */\r
+\r
+#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */\r
+#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */\r
+\r
+#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */\r
+#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */\r
+\r
+#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */\r
+#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */\r
+\r
+#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */\r
+#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */\r
+\r
+#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */\r
+#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */\r
+\r
+#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */\r
+#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */\r
+\r
+#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */\r
+#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */\r
+\r
+#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */\r
+#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */\r
+\r
+#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */\r
+#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */\r
+\r
+#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */\r
+#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */\r
+\r
+#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */\r
+#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */\r
+\r
+#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */\r
+#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */\r
+\r
+#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */\r
+#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */\r
+\r
+#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */\r
+#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */\r
+\r
+#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */\r
+#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */\r
+\r
+#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */\r
+#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */\r
+\r
+#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */\r
+#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */\r
+\r
+#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */\r
+#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */\r
+\r
+#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */\r
+#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */\r
+\r
+#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */\r
+#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */\r
+\r
+#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */\r
+#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */\r
+\r
+#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */\r
+#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */\r
+\r
+#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */\r
+#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */\r
+\r
+#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */\r
+#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */\r
+\r
+#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */\r
+#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */\r
+\r
+#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */\r
+#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */\r
+\r
+#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */\r
+#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */\r
+\r
+#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */\r
+#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */\r
+\r
+#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */\r
+#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */\r
+\r
+#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */\r
+#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */\r
+\r
+#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */\r
+#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */\r
+\r
+#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */\r
+#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */\r
+\r
+#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */\r
+#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */\r
+\r
+#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */\r
+#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */\r
+\r
+#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */\r
+#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */\r
+\r
+#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */\r
+#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */\r
+\r
+#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */\r
+#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */\r
+\r
+#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */\r
+#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */\r
+\r
+#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */\r
+#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */\r
+\r
+#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */\r
+#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */\r
+\r
+#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */\r
+#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */\r
+\r
+#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */\r
+#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */\r
+\r
+#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */\r
+#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */\r
+\r
+#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */\r
+#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */\r
+\r
+#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */\r
+#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */\r
+\r
+/**@}*/ /* SPI_CONST */\r
+/**@}*/ /* end of SPI register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __SPI_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file sys_reg.h\r
+ * @version V1.00\r
+ * @brief SYS register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __SYS_REG_H__\r
+#define __SYS_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- System Manger Controller -------------------------*/\r
+/**\r
+ @addtogroup SYS System Manger Controller(SYS)\r
+ Memory Mapped Structure for SYS Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var SYS_T::PDID\r
+ * Offset: 0x00 Part Device Identification Number Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |PDID |Part Device Identification Number (Read Only)\r
+ * | | |This register reflects device part number code.\r
+ * | | |Software can read this register to identify which device is used.\r
+ * @var SYS_T::RSTSTS\r
+ * Offset: 0x04 System Reset Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PORF |POR Reset Flag\r
+ * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\r
+ * | | |0 = No reset from POR or CHIPRST.\r
+ * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system.\r
+ * | | |Note: Write 1 to clear this bit to 0.\r
+ * |[1] |PINRF |nRESET Pin Reset Flag\r
+ * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.\r
+ * | | |0 = No reset from nRESET pin.\r
+ * | | |1 = Pin nRESET had issued the reset signal to reset the system.\r
+ * | | |Note: Write 1 to clear this bit to 0.\r
+ * |[2] |WDTRF |WDT Reset Flag\r
+ * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\r
+ * | | |0 = No reset from watchdog timer or window watchdog timer.\r
+ * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.\r
+ * | | |Note1: Write 1 to clear this bit to 0.\r
+ * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset.\r
+ * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.\r
+ * |[3] |LVRF |LVR Reset Flag\r
+ * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source.\r
+ * | | |0 = No reset from LVR.\r
+ * | | |1 = LVR controller had issued the reset signal to reset the system.\r
+ * | | |Note: Write 1 to clear this bit to 0.\r
+ * |[4] |BODRF |BOD Reset Flag\r
+ * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-out Detector to indicate the previous reset source.\r
+ * | | |0 = No reset from BOD.\r
+ * | | |1 = The BOD had issued the reset signal to reset the system.\r
+ * | | |Note: Write 1 to clear this bit to 0.\r
+ * |[5] |SYSRF |System Reset Flag\r
+ * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M23 Core to indicate the previous reset source.\r
+ * | | |0 = No reset from Cortex-M23.\r
+ * | | |1 = The Cortex-M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23 core.\r
+ * | | |Note: Write 1 to clear this bit to 0.\r
+ * |[7] |CPURF |CPU Reset Flag\r
+ * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M23 Core and Flash Memory Controller (FMC).\r
+ * | | |0 = No reset from CPU.\r
+ * | | |1 = The Cortex-M23 Core and FMC are reset by software setting CPURST to 1.\r
+ * | | |Note: Write 1 to clear this bit to 0.\r
+ * |[8] |CPULKRF |CPU Lockup Reset Flag\r
+ * | | |The CPULK reset flag is set by hardware if Cortex-M23 lockup happened.\r
+ * | | |0 = No reset from CPU lockup happened.\r
+ * | | |1 = The Cortex-M23 lockup happened and chip is reset.\r
+ * | | |Note1: Write 1 to clear this bit to 0.\r
+ * | | |Note2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset.\r
+ * @var SYS_T::IPRST0\r
+ * Offset: 0x08 Peripheral Reset Control Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CHIPRST |Chip One-shot Reset (Write Protect)\r
+ * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\r
+ * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\r
+ * | | |0 = Chip normal operation.\r
+ * | | |1 = Chip one-shot reset.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[1] |CPURST |Processor Core One-shot Reset (Write Protect)\r
+ * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\r
+ * | | |0 = Processor core normal operation.\r
+ * | | |1 = Processor core one-shot reset.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[2] |PDMA0RST |PDMA0 Controller Reset (Write Protect)\r
+ * | | |Setting this bit to 1 will generate a reset signal to the PDMA0 (always secure).\r
+ * | | |User needs to set this bit to 0 to release from reset state.\r
+ * | | |0 = PDMA0 controller normal operation.\r
+ * | | |1 = PDMA0 controller reset.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[3] |EBIRST |EBI Controller Reset (Write Protect)\r
+ * | | |Set this bit to 1 will generate a reset signal to the EBI\r
+ * | | |User needs to set this bit to 0 to release from the reset state.\r
+ * | | |0 = EBI controller normal operation.\r
+ * | | |1 = EBI controller reset.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[4] |USBHRST |USB Host Controller Reset (Write Protect)\r
+ * | | |Set this bit to 1 will generate a reset signal to the USB Host.\r
+ * | | |User needs to set this bit to 0 to release from the reset state.\r
+ * | | |0 = USB Host controller normal operation.\r
+ * | | |1 = USB Host controller reset.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect)\r
+ * | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller\r
+ * | | |User needs to set this bit to 0 to release from the reset state.\r
+ * | | |0 = SDHOST0 controller normal operation.\r
+ * | | |1 = SDHOST0 controller reset.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect)\r
+ * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller\r
+ * | | |User needs to set this bit to 0 to release from the reset state.\r
+ * | | |0 = CRC calculation controller normal operation.\r
+ * | | |1 = CRC calculation controller reset.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect)\r
+ * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller.\r
+ * | | |User needs to set this bit to 0 to release from the reset state.\r
+ * | | |0 = CRYPTO controller normal operation.\r
+ * | | |1 = CRYPTO controller reset.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[29] |PDMA1RST |PDMA1 Controller Reset (Write Protect)\r
+ * | | |Setting this bit to 1 will generate a reset signal to the PDMA1.\r
+ * | | |User needs to set this bit to 0 to release from reset state.\r
+ * | | |0 = PDMA1 controller normal operation.\r
+ * | | |1 = PDMA1 controller reset.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * @var SYS_T::IPRST1\r
+ * Offset: 0x0C Peripheral Reset Control Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |GPIORST |GPIO Controller Reset\r
+ * | | |0 = GPIO controller normal operation.\r
+ * | | |1 = GPIO controller reset.\r
+ * |[2] |TMR0RST |Timer0 Controller Reset\r
+ * | | |0 = Timer0 controller normal operation.\r
+ * | | |1 = Timer0 controller reset.\r
+ * |[3] |TMR1RST |Timer1 Controller Reset\r
+ * | | |0 = Timer1 controller normal operation.\r
+ * | | |1 = Timer1 controller reset.\r
+ * |[4] |TMR2RST |Timer2 Controller Reset\r
+ * | | |0 = Timer2 controller normal operation.\r
+ * | | |1 = Timer2 controller reset.\r
+ * |[5] |TMR3RST |Timer3 Controller Reset\r
+ * | | |0 = Timer3 controller normal operation.\r
+ * | | |1 = Timer3 controller reset.\r
+ * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset\r
+ * | | |0 = Analog Comparator 0/1 controller normal operation.\r
+ * | | |1 = Analog Comparator 0/1 controller reset.\r
+ * |[8] |I2C0RST |I2C0 Controller Reset\r
+ * | | |0 = I2C0 controller normal operation.\r
+ * | | |1 = I2C0 controller reset.\r
+ * |[9] |I2C1RST |I2C1 Controller Reset\r
+ * | | |0 = I2C1 controller normal operation.\r
+ * | | |1 = I2C1 controller reset.\r
+ * |[10] |I2C2RST |I2C2 Controller Reset\r
+ * | | |0 = I2C2 controller normal operation.\r
+ * | | |1 = I2C2 controller reset.\r
+ * |[12] |QSPI0RST |QSPI0 Controller Reset\r
+ * | | |0 = QSPI0 controller normal operation.\r
+ * | | |1 = QSPI0 controller reset.\r
+ * |[13] |SPI0RST |SPI0 Controller Reset\r
+ * | | |0 = SPI0 controller normal operation.\r
+ * | | |1 = SPI0 controller reset.\r
+ * |[14] |SPI1RST |SPI1 Controller Reset\r
+ * | | |0 = SPI1 controller normal operation.\r
+ * | | |1 = SPI1 controller reset.\r
+ * |[15] |SPI2RST |SPI2 Controller Reset\r
+ * | | |0 = SPI2 controller normal operation.\r
+ * | | |1 = SPI2 controller reset.\r
+ * |[16] |UART0RST |UART0 Controller Reset\r
+ * | | |0 = UART0 controller normal operation.\r
+ * | | |1 = UART0 controller reset.\r
+ * |[17] |UART1RST |UART1 Controller Reset\r
+ * | | |0 = UART1 controller normal operation.\r
+ * | | |1 = UART1 controller reset.\r
+ * |[18] |UART2RST |UART2 Controller Reset\r
+ * | | |0 = UART2 controller normal operation.\r
+ * | | |1 = UART2 controller reset.\r
+ * |[19] |UART3RST |UART3 Controller Reset\r
+ * | | |0 = UART3 controller normal operation.\r
+ * | | |1 = UART3 controller reset.\r
+ * |[20] |UART4RST |UART4 Controller Reset\r
+ * | | |0 = UART4 controller normal operation.\r
+ * | | |1 = UART4 controller reset.\r
+ * |[21] |UART5RST |UART5 Controller Reset\r
+ * | | |0 = UART5 controller normal operation.\r
+ * | | |1 = UART5 controller reset.\r
+ * |[24] |CAN0RST |CAN0 Controller Reset\r
+ * | | |0 = CAN0 controller normal operation.\r
+ * | | |1 = CAN0 controller reset.\r
+ * |[26] |OTGRST |OTG Controller Reset\r
+ * | | |0 = OTG controller normal operation.\r
+ * | | |1 = OTG controller reset.\r
+ * |[27] |USBDRST |USBD Controller Reset\r
+ * | | |0 = USBD controller normal operation.\r
+ * | | |1 = USBD controller reset.\r
+ * |[28] |EADCRST |EADC Controller Reset\r
+ * | | |0 = EADC controller normal operation.\r
+ * | | |1 = EADC controller reset.\r
+ * |[29] |I2S0RST |I2S0 Controller Reset\r
+ * | | |0 = I2S0 controller normal operation.\r
+ * | | |1 = I2S0 controller reset.\r
+ * |[31] |TRNGRST |TRNG Controller Reset\r
+ * | | |0 = TRNG controller normal operation.\r
+ * | | |1 = TRNG controller reset.\r
+ * @var SYS_T::IPRST2\r
+ * Offset: 0x10 Peripheral Reset Control Register 2\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SC0RST |SC0 Controller Reset\r
+ * | | |0 = SC0 controller normal operation.\r
+ * | | |1 = SC0 controller reset.\r
+ * |[1] |SC1RST |SC1 Controller Reset\r
+ * | | |0 = SC1 controller normal operation.\r
+ * | | |1 = SC1 controller reset.\r
+ * |[2] |SC2RST |SC2 Controller Reset\r
+ * | | |0 = SC2 controller normal operation.\r
+ * | | |1 = SC2 controller reset.\r
+ * |[6] |SPI3RST |SPI3 Controller Reset\r
+ * | | |0 = SPI3 controller normal operation.\r
+ * | | |1 = SPI3 controller reset.\r
+ * |[8] |USCI0RST |USCI0 Controller Reset\r
+ * | | |0 = USCI0 controller normal operation.\r
+ * | | |1 = USCI0 controller reset.\r
+ * |[9] |USCI1RST |USCI1 Controller Reset\r
+ * | | |0 = USCI1 controller normal operation.\r
+ * | | |1 = USCI1 controller reset.\r
+ * |[12] |DACRST |DAC Controller Reset\r
+ * | | |0 = DAC controller normal operation.\r
+ * | | |1 = DAC controller reset.\r
+ * |[16] |EPWM0RST |EPWM0 Controller Reset\r
+ * | | |0 = EPWM0 controller normal operation.\r
+ * | | |1 = EPWM0 controller reset.\r
+ * |[17] |EPWM1RST |EPWM1 Controller Reset\r
+ * | | |0 = EPWM1 controller normal operation.\r
+ * | | |1 = EPWM1 controller reset.\r
+ * |[18] |BPWM0RST |BPWM0 Controller Reset\r
+ * | | |0 = BPWM0 controller normal operation.\r
+ * | | |1 = BPWM0 controller reset.\r
+ * |[19] |BPWM1RST |BPWM1 Controller Reset\r
+ * | | |0 = BPWM1 controller normal operation.\r
+ * | | |1 = BPWM1 controller reset.\r
+ * |[22] |QEI0RST |QEI0 Controller Reset\r
+ * | | |0 = QEI0 controller normal operation.\r
+ * | | |1 = QEI0 controller reset.\r
+ * |[23] |QEI1RST |QEI1 Controller Reset\r
+ * | | |0 = QEI1 controller normal operation.\r
+ * | | |1 = QEI1 controller reset.\r
+ * |[26] |ECAP0RST |ECAP0 Controller Reset\r
+ * | | |0 = ECAP0 controller normal operation.\r
+ * | | |1 = ECAP0 controller reset.\r
+ * |[27] |ECAP1RST |ECAP1 Controller Reset\r
+ * | | |0 = ECAP1 controller normal operation.\r
+ * | | |1 = ECAP1 controller reset.\r
+ * @var SYS_T::BODCTL\r
+ * Offset: 0x18 Brown-out Detector Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect)\r
+ * | | |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).\r
+ * | | |0 = Brown-out Detector function Disabled.\r
+ * | | |1 = Brown-out Detector function Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect)\r
+ * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .\r
+ * | | |0 = Brown-out INTERRUPT function Enabled.\r
+ * | | |1 = Brown-out RESET function Enabled.\r
+ * | | |Note1:\r
+ * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).\r
+ * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if AVDD high.than BODVL, BOD interrupt will keep till to the BODIF set to 0.\r
+ * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).\r
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[4] |BODIF |Brown-out Detector Interrupt Flag\r
+ * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.\r
+ * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.\r
+ * | | |Note: Write 1 to clear this bit to 0.\r
+ * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect)\r
+ * | | |0 = BOD operate in normal mode (default).\r
+ * | | |1 = BOD Low Power mode Enabled.\r
+ * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\r
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[6] |BODOUT |Brown-out Detector Output Status\r
+ * | | |0 = Brown-out Detector output status is 0.\r
+ * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0.\r
+ * | | |1 = Brown-out Detector output status is 1.\r
+ * | | |It means the detected voltage is lower than BODVL setting.\r
+ * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0.\r
+ * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect)\r
+ * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting.\r
+ * | | |LVR function is enabled by default.\r
+ * | | |0 = Low Voltage Reset function Disabled.\r
+ * | | |1 = Low Voltage Reset function Enabled.\r
+ * | | |Note1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default).\r
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect)\r
+ * | | |000 = BOD output is sampled by LIRC clock.\r
+ * | | |001 = 4 system clock (HCLK).\r
+ * | | |010 = 8 system clock (HCLK).\r
+ * | | |011 = 16 system clock (HCLK).\r
+ * | | |100 = 32 system clock (HCLK).\r
+ * | | |101 = 64 system clock (HCLK).\r
+ * | | |110 = 128 system clock (HCLK).\r
+ * | | |111 = 256 system clock (HCLK).\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect)\r
+ * | | |000 = Without de-glitch function.\r
+ * | | |001 = 4 system clock (HCLK).\r
+ * | | |010 = 8 system clock (HCLK).\r
+ * | | |011 = 16 system clock (HCLK).\r
+ * | | |100 = 32 system clock (HCLK).\r
+ * | | |101 = 64 system clock (HCLK).\r
+ * | | |110 = 128 system clock (HCLK).\r
+ * | | |111 = 256 system clock (HCLK).\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect)\r
+ * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]).\r
+ * | | |000 = Brown-out Detector threshold voltage is 1.6V.\r
+ * | | |001 = Brown-out Detector threshold voltage is 1.8V.\r
+ * | | |010 = Brown-out Detector threshold voltage is 2.0V.\r
+ * | | |011 = Brown-out Detector threshold voltage is 2.2V.\r
+ * | | |100 = Brown-out Detector threshold voltage is 2.4V.\r
+ * | | |101 = Brown-out Detector threshold voltage is 2.6V.\r
+ * | | |110 = Brown-out Detector threshold voltage is 2.8V.\r
+ * | | |111 = Brown-out Detector threshold voltage is 3.0V.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * @var SYS_T::IVSCTL\r
+ * Offset: 0x1C Internal Voltage Source Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |VTEMPEN |Temperature Sensor Enable Bit\r
+ * | | |This bit is used to enable/disable temperature sensor function.\r
+ * | | |0 = Temperature sensor function Disabled (default).\r
+ * | | |1 = Temperature sensor function Enabled.\r
+ * | | |Note: After this bit is set to 1, the value of temperature sensor output\r
+ * | | |can be obtained through GPC.9.\r
+ * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit\r
+ * | | |This bit is used to enable/disable VBAT unity gain buffer function.\r
+ * | | |0 = VBAT unity gain buffer function Disabled (default).\r
+ * | | |1 = VBAT unity gain buffer function Enabled.\r
+ * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result.\r
+ * @var SYS_T::PORCTL0\r
+ * Offset: 0x24 Power-on Reset Controller Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |PORMASK |Power-on Reset Mask Enable Bit (Write Protect)\r
+ * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.\r
+ * | | |User can mask internal POR signal to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\r
+ * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\r
+ * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * @var SYS_T::VREFCTL\r
+ * Offset: 0x28 VREF Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[4:0] |VREFCTL |VREF Control Bits (Write Protect)\r
+ * | | |00000 = VREF is from external pin.\r
+ * | | |00011 = VREF is internal 1.6V.\r
+ * | | |00111 = VREF is internal 2.0V.\r
+ * | | |01011 = VREF is internal 2.5V.\r
+ * | | |01111 = VREF is internal 3.0V.\r
+ * | | |Others = Reserved.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[5] |IBIASSEL |VREF Bias Current Selection (Write Protect)\r
+ * | | |0 = Bias current from MEGBIAS.\r
+ * | | |1 = Bias current from internal.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[7:6] |PRELOADSEL|Pre-load Timing Selection (Write Protect)\r
+ * | | |00 = pre-load time is 60us for 0.1uF Capacitor.\r
+ * | | |01 = pre-load time is 310us for 1uF Capacitor.\r
+ * | | |10 = pre-load time is 1270us for 4.7uF Capacitor.\r
+ * | | |11 = pre-load time is 2650us for 10uF Capacitor.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * @var SYS_T::USBPHY\r
+ * Offset: 0x2C USB PHY Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |USBROLE |USB Role Option (Write Protect)\r
+ * | | |These two bits are used to select the role of USB.\r
+ * | | |00 = Standard USB Device mode.\r
+ * | | |01 = Standard USB Host mode.\r
+ * | | |10 = ID dependent mode.\r
+ * | | |11 = On-The-Go device mode (default).\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable.\r
+ * |[8] |OTGPHYEN |USB OTG PHY Enable\r
+ * | | |This bit is used to enable/disable OTG PHY function.\r
+ * | | |0 = OTG PHY function Disabled (default).\r
+ * | | |1 = OTG PHY function Enabled.\r
+ * @var SYS_T::GPA_MFPL\r
+ * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection\r
+ * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection\r
+ * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection\r
+ * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection\r
+ * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection\r
+ * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection\r
+ * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection\r
+ * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection\r
+ * @var SYS_T::GPA_MFPH\r
+ * Offset: 0x34 GPIOA High Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection\r
+ * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection\r
+ * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection\r
+ * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection\r
+ * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection\r
+ * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection\r
+ * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection\r
+ * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection\r
+ * @var SYS_T::GPB_MFPL\r
+ * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection\r
+ * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection\r
+ * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection\r
+ * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection\r
+ * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection\r
+ * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection\r
+ * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection\r
+ * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection\r
+ * @var SYS_T::GPB_MFPH\r
+ * Offset: 0x3C GPIOB High Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection\r
+ * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection\r
+ * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection\r
+ * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection\r
+ * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection\r
+ * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection\r
+ * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection\r
+ * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection\r
+ * @var SYS_T::GPC_MFPL\r
+ * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection\r
+ * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection\r
+ * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection\r
+ * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection\r
+ * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection\r
+ * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection\r
+ * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection\r
+ * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection\r
+ * @var SYS_T::GPC_MFPH\r
+ * Offset: 0x44 GPIOC High Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection\r
+ * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection\r
+ * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection\r
+ * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection\r
+ * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection\r
+ * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection\r
+ * @var SYS_T::GPD_MFPL\r
+ * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection\r
+ * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection\r
+ * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection\r
+ * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection\r
+ * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection\r
+ * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection\r
+ * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection\r
+ * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection\r
+ * @var SYS_T::GPD_MFPH\r
+ * Offset: 0x4C GPIOD High Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection\r
+ * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection\r
+ * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection\r
+ * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection\r
+ * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection\r
+ * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection\r
+ * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection\r
+ * @var SYS_T::GPE_MFPL\r
+ * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection\r
+ * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection\r
+ * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection\r
+ * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection\r
+ * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection\r
+ * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection\r
+ * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection\r
+ * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection\r
+ * @var SYS_T::GPE_MFPH\r
+ * Offset: 0x54 GPIOE High Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection\r
+ * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection\r
+ * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection\r
+ * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection\r
+ * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection\r
+ * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection\r
+ * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection\r
+ * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection\r
+ * @var SYS_T::GPF_MFPL\r
+ * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection\r
+ * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection\r
+ * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection\r
+ * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection\r
+ * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection\r
+ * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection\r
+ * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection\r
+ * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection\r
+ * @var SYS_T::GPF_MFPH\r
+ * Offset: 0x5C GPIOF High Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection\r
+ * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection\r
+ * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection\r
+ * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection\r
+ * @var SYS_T::GPG_MFPL\r
+ * Offset: 0x60 GPIOG Low Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection\r
+ * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection\r
+ * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection\r
+ * @var SYS_T::GPG_MFPH\r
+ * Offset: 0x64 GPIOG High Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection\r
+ * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection\r
+ * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection\r
+ * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection\r
+ * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection\r
+ * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection\r
+ * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection\r
+ * @var SYS_T::GPH_MFPL\r
+ * Offset: 0x68 GPIOH Low Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection\r
+ * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection\r
+ * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection\r
+ * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection\r
+ * @var SYS_T::GPH_MFPH\r
+ * Offset: 0x6C GPIOH High Byte Multiple Function Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection\r
+ * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection\r
+ * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection\r
+ * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection\r
+ * @var SYS_T::GPA_MFOS\r
+ * Offset: 0x80/0x84/0x88/0x8C/0x90/0x94/0x9C GPIOA-H Multiple Function Output Select Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[n] |MFOSn |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select\r
+ * | | |This bit used to select multiple function pin output mode type for Px.n pin.\r
+ * | | |0 = Multiple function pin output mode type is Push-pull mode.\r
+ * | | |1 = Multiple function pin output mode type is Open-drain mode.\r
+ * | | |Note:\r
+ * | | |Max. n=15 for port A/B/E.\r
+ * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.\r
+ * | | |Max. n=14 for port D. The PD.15 is ignored.\r
+ * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.\r
+ * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.\r
+ * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.\r
+ * @var SYS_T::SRAMICTL\r
+ * Offset: 0xC0 System SRAM Interrupt Enable Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit\r
+ * | | |0 = SRAM parity check error interrupt Disabled.\r
+ * | | |1 = SRAM parity check error interrupt Enabled.\r
+ * @var SYS_T::SRAMSTS\r
+ * Offset: 0xC4 System SRAM Parity Error Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PERRIF |SRAM Parity Check Error Flag\r
+ * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0.\r
+ * | | |0 = No System SRAM parity error.\r
+ * | | |1 = System SRAM parity error occur.\r
+ * @var SYS_T::SRAMEADR\r
+ * Offset: 0xC8 System SRAM Parity Check Error Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ERRADDR |System SRAM Parity Error Address\r
+ * | | |This register shows system SRAM parity error byte address.\r
+ * @var SYS_T::SRAMPCTL\r
+ * Offset: 0xDC System SRAM Power Mode Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |STACK |System SRAM Stack Position (Write Protect)\r
+ * | | |This field must configure the system SRAM Marco that first SRAM address accessed by CPU in power-on process.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[5:4] |RETCNT |SRAM Retention Count (Write Protect)\r
+ * | | |This field can configure SRAM macro retention time in unit of HIRC period.\r
+ * | | |00 = One HIRC period.\r
+ * | | |01 = Two HIRC periods.\r
+ * | | |10 = Three HIRC periods.\r
+ * | | |11 = Four HIRC periods.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[9:8] |SRAM0PM0 |Bank0 SRAM Power Mode Select 0 (Write Protect)\r
+ * | | |This field can control bank0 SRAM (32k) power mode in system power down mode for range 0x2000_0000 - 0x2000_1FFF.\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |11 = Reserved (Write Ignore).\r
+ * | | |Note1: Bank0 SRAM is always operating in power shut down mode for system enter Deep Power-down mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[11:10] |SRAM0PM1 |Bank0 SRAM Power Mode Select 1 (Write Protect)\r
+ * | | |This field can control bank0 SRAM (32k) power mode in system enter power down mode for range 0x2000_2000 - 0x2000_3FFF.\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |11 = Reserved (Write Ignore).\r
+ * | | |Note1: Bank0 SRAM is always operating in power shut down mode for system enter Deep Power-down mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[13:12] |SRAM0PM2 |Bank0 SRAM Power Mode Select 2 (Write Protect)\r
+ * | | |This field can control bank0 SRAM (32k) power mode in system enter power down mode for range 0x2004_0000 - 0x2000_5FFF.\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |11 = Reserved (Write Ignore).\r
+ * | | |Note1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[15:14] |SRAM0PM3 |Bank0 SRAM Power Mode Select 3 (Write Protect)\r
+ * | | |This field can control bank0 SRAM (32k) power mode in system enter power down mode for range 0x2006_0000 - 0x2000_7FFF.\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |11 = Reserved (Write Ignore).\r
+ * | | |Note1: Bank0 SRAM is always operating in power shut down mode for system enter Deep Power-down mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[17:16] |SRAM1PM0 |Bank1 SRAM Power Mode Select 0 (Write Protect)\r
+ * | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2000_8000 - 0x2000_BFFF.\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |11 = Reserved (Write Ignore).\r
+ * | | |Note1: Bank1 SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[19:18] |SRAM1PM1 |Bank1 SRAM Power Mode Select 1 (Write Protect)\r
+ * | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2000_C000 - 0x2000_FFFF.\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |Note1: Bank1 SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[21:20] |SRAM1PM2 |Bank1 SRAM Power Mode Select 2 (Write Protect)\r
+ * | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2001_0000 - 0x2001_3FFF.\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |11 = Reserved (Write Ignore).\r
+ * | | |Note1: Bank1 SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[23:22] |SRAM1PM3 |Bank1 SRAM Power Mode Select 3 (Write Protect)\r
+ * | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2001_4000 - 0x2001_7FFF\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |11 = Reserved (Write Ignore).\r
+ * | | |Note1: Bank1 SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * @var SYS_T::SRAMPPCT\r
+ * Offset: 0xE0 Peripheral SRAM Power Mode Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |CAN |CAN SRAM Power Mode Select (Write Protect)\r
+ * | | |This field can control CAN SRAM power mode for system enter power down mode.\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |11 = Reserved (Write Ignore)..\r
+ * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[3:2] |USBD |USB Device SRAM Power Mode Select (Write Protect)\r
+ * | | |This field can control USB device SRAM power mode for system enter power down mode.\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |11 = Reserved (Write Ignore).\r
+ * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[5:4] |PDMA0 |PDMA SRAM Power Mode Select (Write Protect)\r
+ * | | |This field can control PDMA0 (always secure) SRAM power mode for system enter power down mode.\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |11 = Reserved (Write Ignore).\r
+ * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[7:6] |PDMA1 |PDMA SRAM Power Mode Select (Write Protect)\r
+ * | | |This field can control PDMA1 SRAM power mode for system enter power down mode.\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |11 = Reserved (Write Ignore).\r
+ * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[9:8] |FMC |FMC SRAM Power Mode Select (Write Protect)\r
+ * | | |This field can control FMC cache SRAM power mode for system enter power down mode.\r
+ * | | |00 = Normal mode.\r
+ * | | |01 = Retention mode.\r
+ * | | |10 = Power shut down mode.\r
+ * | | |11 = Reserved (Write Ignore).\r
+ * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).\r
+ * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * @var SYS_T::TCTL48M\r
+ * Offset: 0xE4 HIRC 48M Trim Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |FREQSEL |Trim Frequency Selection\r
+ * | | |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC48) auto trim.\r
+ * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\r
+ * | | |00 = Disable HIRC auto trim function.\r
+ * | | |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz.\r
+ * | | |10 = Reserved..\r
+ * | | |11 = Reserved.\r
+ * |[5:4] |LOOPSEL |Trim Calculation Loop Selection\r
+ * | | |This field defines that trim value calculation is based on how many reference clocks.\r
+ * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock.\r
+ * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock.\r
+ * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock.\r
+ * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock.\r
+ * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.\r
+ * |[7:6] |RETRYCNT |Trim Value Update Limitation Count\r
+ * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\r
+ * | | |Once the HIRC locked, the internal trim value update counter will be reset.\r
+ * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.\r
+ * | | |00 = Trim retry count limitation is 64 loops.\r
+ * | | |01 = Trim retry count limitation is 128 loops.\r
+ * | | |10 = Trim retry count limitation is 256 loops.\r
+ * | | |11 = Trim retry count limitation is 512 loops.\r
+ * |[8] |CESTOPEN |Clock Error Stop Enable Bit\r
+ * | | |0 = The trim operation is keep going if clock is inaccuracy.\r
+ * | | |1 = The trim operation is stopped if clock is inaccuracy.\r
+ * |[10] |REFCKSEL |Reference Clock Selection\r
+ * | | |0 = HIRC trim 48M reference clock is from external 32.768 kHz crystal oscillator.\r
+ * | | |1 = HIRC trim 48M reference clock is from internal USB synchronous mode.\r
+ * @var SYS_T::TIEN48M\r
+ * Offset: 0xE8 HIRC 48M Trim Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit\r
+ * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL48M[1:0]).\r
+ * | | |If this bit is high and TFAILIF(SYS_TISTS48M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\r
+ * | | |0 = Disable TFAILIF(SYS_SYS_TISTS48M[1]) status to trigger an interrupt to CPU.\r
+ * | | |1 = Enable TFAILIF(SYS_SYS_TISTS48MM[1]) status to trigger an interrupt to CPU.\r
+ * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit\r
+ * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\r
+ * | | |If this bit is set to1, and CLKERRIF(SYS_SYS_TISTS48M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.\r
+ * | | |0 = Disable CLKERRIF(SYS_SYS_TISTS48M[2]) status to trigger an interrupt to CPU.\r
+ * | | |1 = Enable CLKERRIF(SYS_SYS_TISTS48M[2]) status to trigger an interrupt to CPU.\r
+ * @var SYS_T::TISTS48M\r
+ * Offset: 0xEC HIRC 48M Trim Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |FREQLOCK |HIRC Frequency Lock Status\r
+ * | | |This bit indicates the HIRC frequency is locked.\r
+ * | | |This is a status bit and doesn't trigger any interrupt.\r
+ * | | |Write 1 to clear this to 0.\r
+ * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled.\r
+ * | | |0 = The internal high-speed oscillator frequency doesn't lock at 48 MHz yet.\r
+ * | | |1 = The internal high-speed oscillator frequency locked at 48 MHz.\r
+ * |[1] |TFAILIF |Trim Failure Interrupt Status\r
+ * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked.\r
+ * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL48M[1:0]) will be cleared to 00 by hardware automatically.\r
+ * | | |If this bit is set and TFAILIEN(SYS_TIEN48M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\r
+ * | | |Write 1 to clear this to 0.\r
+ * | | |0 = Trim value update limitation count does not reach.\r
+ * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked.\r
+ * |[2] |CLKERRIF |Clock Error Interrupt Status\r
+ * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC48) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\r
+ * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TICTL48M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL48M[8]) is set to 1.\r
+ * | | |If this bit is set and CLKEIEN(SYS_TIEN48M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.\r
+ * | | |Write 1 to clear this to 0.\r
+ * | | |0 = Clock frequency is accuracy.\r
+ * | | |1 = Clock frequency is inaccuracy.\r
+ * @var SYS_T::TCTL12M\r
+ * Offset: 0xF0 HIRC 12M Trim Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |FREQSEL |Trim Frequency Selection\r
+ * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim.\r
+ * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\r
+ * | | |00 = Disable HIRC auto trim function.\r
+ * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz.\r
+ * | | |10 = Reserved..\r
+ * | | |11 = Reserved.\r
+ * |[5:4] |LOOPSEL |Trim Calculation Loop Selection\r
+ * | | |This field defines that trim value calculation is based on how many reference clocks.\r
+ * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock.\r
+ * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock.\r
+ * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock.\r
+ * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock.\r
+ * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.\r
+ * |[7:6] |RETRYCNT |Trim Value Update Limitation Count\r
+ * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\r
+ * | | |Once the HIRC locked, the internal trim value update counter will be reset.\r
+ * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.\r
+ * | | |00 = Trim retry count limitation is 64 loops.\r
+ * | | |01 = Trim retry count limitation is 128 loops.\r
+ * | | |10 = Trim retry count limitation is 256 loops.\r
+ * | | |11 = Trim retry count limitation is 512 loops.\r
+ * |[8] |CESTOPEN |Clock Error Stop Enable Bit\r
+ * | | |0 = The trim operation is keep going if clock is inaccuracy.\r
+ * | | |1 = The trim operation is stopped if clock is inaccuracy.\r
+ * |[10] |REFCKSEL |Reference Clock Selection\r
+ * | | |0 = HIRC trim reference clock is from external 32.768 kHz crystal oscillator.\r
+ * | | |1 = HIRC trim reference clock is from internal USB synchronous mode.\r
+ * @var SYS_T::TIEN12M\r
+ * Offset: 0xF4 HIRC 12M Trim Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit\r
+ * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL12M[1:0]).\r
+ * | | |If this bit is high and TFAILIF(SYS_TISTS12M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\r
+ * | | |0 = Disable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU.\r
+ * | | |1 = Enable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU.\r
+ * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit\r
+ * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\r
+ * | | |If this bit is set to1, and CLKERRIF(SYS_TISTS12M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.\r
+ * | | |0 = Disable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU.\r
+ * | | |1 = Enable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU.\r
+ * @var SYS_T::TISTS12M\r
+ * Offset: 0xF8 HIRC 12M Trim Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |FREQLOCK |HIRC Frequency Lock Status\r
+ * | | |This bit indicates the HIRC frequency is locked.\r
+ * | | |This is a status bit and doesn't trigger any interrupt\r
+ * | | |Write 1 to clear this to 0\r
+ * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled.0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet.\r
+ * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz.\r
+ * |[1] |TFAILIF |Trim Failure Interrupt Status\r
+ * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked.\r
+ * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL12M[1:0]) will be cleared to 00 by hardware automatically.\r
+ * | | |If this bit is set and TFAILIEN(SYS_TIEN12M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\r
+ * | | |Write 1 to clear this to 0.\r
+ * | | |0 = Trim value update limitation count does not reach.\r
+ * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked.\r
+ * |[2] |CLKERRIF |Clock Error Interrupt Status\r
+ * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\r
+ * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TICTL12M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL12M[8]) is set to 1.\r
+ * | | |If this bit is set and CLKEIEN(SYS_TIEN12M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.\r
+ * | | |Write 1 to clear this to 0.\r
+ * | | |0 = Clock frequency is accuracy.\r
+ * | | |1 = Clock frequency is inaccuracy.\r
+ * @var SYS_T::REGLCTL\r
+ * Offset: 0x100 Register Lock Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |REGLCTL |Register Lock Control Code (Write Only)\r
+ * | | |Some registers have write-protection function\r
+ * | | |Writing these registers have to disable the protected function by writing the sequence value 59h, 16h, 88h to this field.\r
+ * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.\r
+ * |[0] |REGLCTL[0]|Register Lock Control Disable Index (Read Only)\r
+ * | | |0 = Write-protection Enabled for writing protected registers.\r
+ * | | |Any write to the protected register is ignored.\r
+ * | | |1 = Write-protection Disabled for writing protected registers.\r
+ * @var SYS_T::PORCTL1\r
+ * Offset: 0x1EC Power-on Reset Controller Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect)\r
+ * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.\r
+ * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\r
+ * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\r
+ * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * @var SYS_T::PLCTL\r
+ * Offset: 0x1F8 Power Level Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |PLSEL |Power Level Select (Write Protect)\r
+ * | | |00 = Set to Power level 0 (PL0).\r
+ * | | |01 = Set to Power level 1 (PL1).\r
+ * | | |Others = Reserved.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[4] |MVRS |Main Voltage Regulator Type Select (Write Protect)\r
+ * | | |This bit filed sets main voltage regulator type.\r
+ * | | |After setting main voltage regulator type to DCDC (MVRS (SYS_PLCTL[4]) = 1) system will set main voltage regulator type change busy flag MVRCBUSY(SYS_PLSTS[1]), detect inductor connection and update inductor connection status LCONS (SYS_PLSTS[3]).\r
+ * | | |If inductor exist LCONS will be cleard and main viltage regulator type can switch to DCDC (CURMVRS (SYS_PLSTS[12])=1).\r
+ * | | |0 = Set main voltage regulator to LDO.\r
+ * | | |1 = Set main voltage regulator to DCDC.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[21:16] |LVSSTEP |LDO Voltage Scaling Step (Write Protect)\r
+ * | | |The LVSSTEP value is LDO voltage rising step.\r
+ * | | |LDO voltage scaling step = (LVSSTEP + 1) * 10mV.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * |[31:24] |LVSPRD |LDO Voltage Scaling Period (Write Protect)\r
+ * | | |The LVSPRD value is the period of each LDO voltage rising step.\r
+ * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us.\r
+ * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.\r
+ * @var SYS_T::PLSTS\r
+ * Offset: 0x1FC Power Level Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only)\r
+ * | | |This bit is set by hardware when power level is changing . After power level change is completed, this bit will be cleared automatically by hardware.\r
+ * | | |0 = Power level change is completed.\r
+ * | | |1 = Power level change is ongoing.\r
+ * |[1] |MVRCBUSY |Main Voltage Regulator Type Change Busy Bit (Read Only)\r
+ * | | |This bit is set by hardware when main voltage regulator type is changing.\r
+ * | | |After main voltage regulator type change is completed, this bit will be cleared automatically by hardware.\r
+ * | | |0 = Main voltage regulator type change is completed.\r
+ * | | |1 = Main voltage regulator type change is ongoing.\r
+ * |[2] |MVRCERR |Main Voltage Regulator Type Change Error Bit (Write Protect)\r
+ * | | |This bit is set to 1 when main voltage regulator type change from LDO to DCDC error, the following conditions will cause change errors:\r
+ * | | |1.System change to DC-DC mode but LDO change voltage process not finish.\r
+ * | | |2.Detect inductor fail.\r
+ * | | |Read:\r
+ * | | |0 = No main voltage regulator type change error.\r
+ * | | |1 = Main voltage regulator type change to DCDC error occurred.\r
+ * | | |Write:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clears MVRCERR to 0.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[3] |LCONS |Inductor for DC-DC Connect Status (Read Only)\r
+ * | | |0 = Inductor connect between Vsw and LDO_CAP pin.\r
+ * | | |This bit is valid when current main voltage regulator type is DCDC (CURMVRS (SYS_PLSTS[12])=1). If current main voltage regulator type is LDO (CURMVRS (SYS_PLSTS[12])=0), this bit is set to 1.\r
+ * | | |0 = Inductor connect between Vsw and LDO_CAP pin.\r
+ * | | |1 = No Inductor connect between Vsw and LDO_CAP pin.\r
+ * | | |Note: This bit is 1 when main viltage regulator is LDO.\r
+ * |[4] |PDINVTRF |Power-down Mode Invalid Transition Flag (Write Protect)\r
+ * | | |This bit is set by hardware if the requested active DCDC mode to Power-down mode transition is invalid.\r
+ * | | |This transition request will be aborted by hardware.\r
+ * | | |The bit can be cleared by software.\r
+ * | | |Read:\r
+ * | | |0 = No Power-down mode invalid transition.\r
+ * | | |1 = Power-down mode invalid transition occurred.\r
+ * | | |Write:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clears this bit to 0.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[9:8] |PLSTATUS |Power Level Status (Read Only)\r
+ * | | |This bit field reflect the current power level.\r
+ * | | |00 = Power level is PL0.\r
+ * | | |01 = Power level is PL1.\r
+ * | | |Others = Reserved.\r
+ * |[12] |CURMVR |Current Main Voltage Regulator Type (Read Only)\r
+ * | | |This bit field reflects current main voltage regulator type.\r
+ * | | |0 = Current main voltage regulator in active and Idle mode is LDO.\r
+ * | | |1 = Current main voltage regulator in active mode and Idle is DCDC.\r
+ * @var SYS_T::AHBMCTL\r
+ * Offset: 0x400 AHB Bus Matrix Priority Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex-M23 Core Enable Bit (Write Protect)\r
+ * | | |Enable Cortex-M23 core with highest AHB bus priority in AHB bus matrix.\r
+ * | | |0 = Run robin mode.\r
+ * | | |1 = Cortex-M23 CPU with highest bus priority when interrupt occurs.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ */\r
+\r
+ __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */\r
+ __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */\r
+ __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */\r
+ __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */\r
+ __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */\r
+ __I uint32_t RESERVE0[1];\r
+ __IO uint32_t BODCTL; /*!< [0x0018] Brown-out Detector Control Register */\r
+ __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */\r
+ __I uint32_t RESERVE1[1];\r
+ __IO uint32_t PORCTL0; /*!< [0x0024] Power-on Reset Controller Register 0 */\r
+ __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */\r
+ __IO uint32_t USBPHY; /*!< [0x002C] USB PHY Control Register */\r
+ __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */\r
+ __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */\r
+ __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */\r
+ __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */\r
+ __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */\r
+ __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */\r
+ __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */\r
+ __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */\r
+ __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */\r
+ __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */\r
+ __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */\r
+ __IO uint32_t GPF_MFPH; /*!< [0x005C] GPIOF High Byte Multiple Function Control Register */\r
+ __IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */\r
+ __IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */\r
+ __IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */\r
+ __IO uint32_t GPH_MFPH; /*!< [0x006C] GPIOH High Byte Multiple Function Control Register */\r
+ __I uint32_t RESERVE2[4];\r
+ __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */\r
+ __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */\r
+ __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */\r
+ __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */\r
+ __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */\r
+ __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */\r
+ __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */\r
+ __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */\r
+ __I uint32_t RESERVE3[8];\r
+ __IO uint32_t SRAMICTL; /*!< [0x00C0] System SRAM Interrupt Enable Control Register */\r
+ __IO uint32_t SRAMSTS; /*!< [0x00C4] System SRAM Parity Error Status Register */\r
+ __IO uint32_t SRAMEADR; /*!< [0x00C8] System SRAM Parity Check Error Address Register */\r
+ __IO uint32_t RESERVE4[4];\r
+ __IO uint32_t SRAMPCTL; /*!< [0x00DC] System SRAM Power Mode Control Register */\r
+ __IO uint32_t SRAMPPCT; /*!< [0x00E0] Peripheral SRAM Power Mode Control Register */\r
+ __IO uint32_t TCTL48M; /*!< [0x00E4] HIRC 48M Trim Control Register */\r
+ __IO uint32_t TIEN48M; /*!< [0x00E8] HIRC 48M Trim Interrupt Enable Register */\r
+ __IO uint32_t TISTS48M; /*!< [0x00EC] HIRC 48M Trim Interrupt Status Register */\r
+ __IO uint32_t TCTL12M; /*!< [0x00F0] HIRC 12M Trim Control Register */\r
+ __IO uint32_t TIEN12M; /*!< [0x00F4] HIRC 12M Trim Interrupt Enable Register */\r
+ __IO uint32_t TISTS12M; /*!< [0x00F8] HIRC 12M Trim Interrupt Status Register */\r
+ __I uint32_t RESERVE6[1];\r
+ __IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */\r
+ __I uint32_t RESERVE7[58];\r
+ __IO uint32_t PORCTL1; /*!< [0x01EC] Power-on Reset Controller Register 1 */\r
+ __I uint32_t RESERVE8[2];\r
+ __IO uint32_t PLCTL; /*!< [0x01F8] Power Level Control Register */\r
+ __IO uint32_t PLSTS; /*!< [0x01FC] Power Level Status Register */\r
+ __I uint32_t RESERVE9[128];\r
+ __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */\r
+\r
+\r
+} SYS_T;\r
+\r
+/**\r
+ @addtogroup SYS_CONST SYS Bit Field Definition\r
+ Constant Definitions for SYS Controller\r
+@{ */\r
+\r
+#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */\r
+#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */\r
+\r
+#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */\r
+#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */\r
+\r
+#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */\r
+#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */\r
+\r
+#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */\r
+#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */\r
+\r
+#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */\r
+#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */\r
+\r
+#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */\r
+#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */\r
+\r
+#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */\r
+#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */\r
+\r
+#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */\r
+#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */\r
+\r
+#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */\r
+#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */\r
+\r
+#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */\r
+#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */\r
+\r
+#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */\r
+#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */\r
+\r
+#define SYS_IPRST0_PDMA0RST_Pos (2) /*!< SYS_T::IPRST0: PDMA0RST Position */\r
+#define SYS_IPRST0_PDMA0RST_Msk (0x1ul << SYS_IPRST0_PDMA0RST_Pos) /*!< SYS_T::IPRST0: PDMA0RST Mask */\r
+\r
+#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */\r
+#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */\r
+\r
+#define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS_T::IPRST0: USBHRST Position */\r
+#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */\r
+\r
+#define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */\r
+#define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */\r
+\r
+#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */\r
+#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */\r
+\r
+#define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */\r
+#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */\r
+\r
+#define SYS_IPRST0_PDMA1RST_Pos (29) /*!< SYS_T::IPRST0: PDMA1RST Position */\r
+#define SYS_IPRST0_PDMA1RST_Msk (0x1ul << SYS_IPRST0_PDMA1RST_Pos) /*!< SYS_T::IPRST0: PDMA1RST Mask */\r
+\r
+#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */\r
+#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */\r
+\r
+#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */\r
+#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */\r
+\r
+#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */\r
+#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */\r
+\r
+#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */\r
+#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */\r
+\r
+#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */\r
+#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */\r
+\r
+#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */\r
+#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */\r
+\r
+#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */\r
+#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */\r
+\r
+#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */\r
+#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */\r
+\r
+#define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */\r
+#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */\r
+\r
+#define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */\r
+#define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */\r
+\r
+#define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */\r
+#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */\r
+\r
+#define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */\r
+#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */\r
+\r
+#define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */\r
+#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */\r
+\r
+#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */\r
+#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */\r
+\r
+#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */\r
+#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */\r
+\r
+#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */\r
+#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */\r
+\r
+#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */\r
+#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */\r
+\r
+#define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */\r
+#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */\r
+\r
+#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */\r
+#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */\r
+\r
+#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */\r
+#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */\r
+\r
+#define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */\r
+#define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */\r
+\r
+#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */\r
+#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */\r
+\r
+#define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */\r
+#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */\r
+\r
+#define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */\r
+#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */\r
+\r
+#define SYS_IPRST1_TRNGRST_Pos (31) /*!< SYS_T::IPRST1: TRNGRST Position */\r
+#define SYS_IPRST1_TRNGRST_Msk (0x1ul << SYS_IPRST1_TRNGRST_Pos) /*!< SYS_T::IPRST1: TRNGRST Mask */\r
+\r
+#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */\r
+#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */\r
+\r
+#define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */\r
+#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */\r
+\r
+#define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */\r
+#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */\r
+\r
+#define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */\r
+#define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */\r
+\r
+#define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */\r
+#define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */\r
+\r
+#define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */\r
+#define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */\r
+\r
+#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */\r
+#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */\r
+\r
+#define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */\r
+#define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */\r
+\r
+#define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */\r
+#define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */\r
+\r
+#define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */\r
+#define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */\r
+\r
+#define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */\r
+#define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */\r
+\r
+#define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */\r
+#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */\r
+\r
+#define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */\r
+#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */\r
+\r
+#define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */\r
+#define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */\r
+\r
+#define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */\r
+#define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */\r
+\r
+#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */\r
+#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */\r
+\r
+#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */\r
+#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */\r
+\r
+#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */\r
+#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */\r
+\r
+#define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */\r
+#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */\r
+\r
+#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */\r
+#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */\r
+\r
+#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */\r
+#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */\r
+\r
+#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */\r
+#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */\r
+\r
+#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */\r
+#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */\r
+\r
+#define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */\r
+#define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */\r
+\r
+#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */\r
+#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */\r
+\r
+#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */\r
+#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */\r
+\r
+#define SYS_PORCTL0_PORMASK_Pos (0) /*!< SYS_T::PORCTL0: PORMASK Position */\r
+#define SYS_PORCTL0_PORMASK_Msk (0xfffful << SYS_PORCTL0_PORMASK_Pos) /*!< SYS_T::PORCTL0: PORMASK Mask */\r
+\r
+#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */\r
+#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */\r
+\r
+#define SYS_VREFCTL_IBIASSEL_Pos (5) /*!< SYS_T::VREFCTL: IBIASSEL Position */\r
+#define SYS_VREFCTL_IBIASSEL_Msk (0x1ul << SYS_VREFCTL_IBIASSEL_Pos) /*!< SYS_T::VREFCTL: IBIASSEL Mask */\r
+\r
+#define SYS_VREFCTL_PRELOADSEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOADSEL Position */\r
+#define SYS_VREFCTL_PRELOADSEL_Msk (0x3ul << SYS_VREFCTL_PRELOADSEL_Pos) /*!< SYS_T::VREFCTL: PRELOADSEL Mask */\r
+\r
+#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */\r
+#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */\r
+\r
+#define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */\r
+#define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */\r
+\r
+#define SYS_USBPHY_OTGPHYEN_Pos (8) /*!< SYS_T::USBPHY: OTGPHYEN Position */\r
+#define SYS_USBPHY_OTGPHYEN_Msk (0x1ul << SYS_USBPHY_OTGPHYEN_Pos) /*!< SYS_T::USBPHY: OTGPHYEN Mask */\r
+\r
+#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */\r
+#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */\r
+\r
+#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */\r
+#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */\r
+\r
+#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */\r
+#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */\r
+\r
+#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */\r
+#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */\r
+\r
+#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */\r
+#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */\r
+\r
+#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */\r
+#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */\r
+\r
+#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */\r
+#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */\r
+\r
+#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */\r
+#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */\r
+\r
+#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */\r
+#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */\r
+\r
+#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */\r
+#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */\r
+\r
+#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */\r
+#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */\r
+\r
+#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */\r
+#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */\r
+\r
+#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */\r
+#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */\r
+\r
+#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */\r
+#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */\r
+\r
+#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */\r
+#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */\r
+\r
+#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */\r
+#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */\r
+\r
+#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */\r
+#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */\r
+\r
+#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */\r
+#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */\r
+\r
+#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */\r
+#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */\r
+\r
+#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */\r
+#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */\r
+\r
+#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */\r
+#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */\r
+\r
+#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */\r
+#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */\r
+\r
+#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */\r
+#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */\r
+\r
+#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */\r
+#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */\r
+\r
+#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */\r
+#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */\r
+\r
+#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */\r
+#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */\r
+\r
+#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */\r
+#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */\r
+\r
+#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */\r
+#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */\r
+\r
+#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */\r
+#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */\r
+\r
+#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */\r
+#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */\r
+\r
+#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */\r
+#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */\r
+\r
+#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */\r
+#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */\r
+\r
+#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */\r
+#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */\r
+\r
+#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */\r
+#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */\r
+\r
+#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */\r
+#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */\r
+\r
+#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */\r
+#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */\r
+\r
+#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */\r
+#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */\r
+\r
+#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */\r
+#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */\r
+\r
+#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */\r
+#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */\r
+\r
+#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */\r
+#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */\r
+\r
+#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */\r
+#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */\r
+\r
+#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */\r
+#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */\r
+\r
+#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */\r
+#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */\r
+\r
+#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */\r
+#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */\r
+\r
+#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */\r
+#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */\r
+\r
+#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */\r
+#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */\r
+\r
+#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */\r
+#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */\r
+\r
+#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */\r
+#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */\r
+\r
+#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */\r
+#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */\r
+\r
+#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */\r
+#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */\r
+\r
+#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */\r
+#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */\r
+\r
+#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */\r
+#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */\r
+\r
+#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */\r
+#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */\r
+\r
+#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */\r
+#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */\r
+\r
+#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */\r
+#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */\r
+\r
+#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */\r
+#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */\r
+\r
+#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */\r
+#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */\r
+\r
+#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */\r
+#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */\r
+\r
+#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */\r
+#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */\r
+\r
+#define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */\r
+#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */\r
+\r
+#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */\r
+#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */\r
+\r
+#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */\r
+#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */\r
+\r
+#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */\r
+#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */\r
+\r
+#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */\r
+#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */\r
+\r
+#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */\r
+#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */\r
+\r
+#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */\r
+#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */\r
+\r
+#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */\r
+#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */\r
+\r
+#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */\r
+#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */\r
+\r
+#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */\r
+#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */\r
+\r
+#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */\r
+#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */\r
+\r
+#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */\r
+#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */\r
+\r
+#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */\r
+#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */\r
+\r
+#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */\r
+#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */\r
+\r
+#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */\r
+#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */\r
+\r
+#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */\r
+#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */\r
+\r
+#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */\r
+#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */\r
+\r
+#define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */\r
+#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */\r
+\r
+#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */\r
+#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */\r
+\r
+#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */\r
+#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */\r
+\r
+#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */\r
+#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */\r
+\r
+#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */\r
+#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */\r
+\r
+#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */\r
+#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */\r
+\r
+#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */\r
+#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */\r
+\r
+#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */\r
+#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */\r
+\r
+#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */\r
+#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */\r
+\r
+#define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */\r
+#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */\r
+\r
+#define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */\r
+#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */\r
+\r
+#define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */\r
+#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */\r
+\r
+#define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */\r
+#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */\r
+\r
+#define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */\r
+#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */\r
+\r
+#define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */\r
+#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */\r
+\r
+#define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */\r
+#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */\r
+\r
+#define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */\r
+#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */\r
+\r
+#define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */\r
+#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */\r
+\r
+#define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */\r
+#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */\r
+\r
+#define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */\r
+#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */\r
+\r
+#define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */\r
+#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */\r
+\r
+#define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */\r
+#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */\r
+\r
+#define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */\r
+#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */\r
+\r
+#define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */\r
+#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */\r
+\r
+#define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */\r
+#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */\r
+\r
+#define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */\r
+#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */\r
+\r
+#define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */\r
+#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */\r
+\r
+#define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */\r
+#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */\r
+\r
+#define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */\r
+#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */\r
+\r
+#define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */\r
+#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */\r
+\r
+#define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */\r
+#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */\r
+#define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */\r
+#define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */\r
+#define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */\r
+#define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */\r
+#define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */\r
+#define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */\r
+#define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */\r
+#define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */\r
+#define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */\r
+#define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */\r
+#define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */\r
+#define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */\r
+#define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */\r
+#define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */\r
+#define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */\r
+\r
+#define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */\r
+#define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */\r
+#define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */\r
+#define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */\r
+#define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */\r
+#define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */\r
+#define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */\r
+#define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */\r
+#define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */\r
+#define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */\r
+#define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */\r
+#define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */\r
+#define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */\r
+#define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */\r
+#define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */\r
+#define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */\r
+#define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */\r
+\r
+#define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */\r
+#define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */\r
+#define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */\r
+#define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */\r
+#define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */\r
+#define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */\r
+#define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */\r
+#define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */\r
+#define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */\r
+#define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */\r
+#define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */\r
+#define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */\r
+#define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */\r
+#define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */\r
+#define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */\r
+\r
+#define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */\r
+#define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */\r
+#define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */\r
+#define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */\r
+#define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */\r
+#define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */\r
+#define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */\r
+#define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */\r
+#define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */\r
+#define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */\r
+#define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */\r
+#define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */\r
+#define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */\r
+#define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */\r
+#define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */\r
+#define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */\r
+\r
+#define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */\r
+#define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */\r
+#define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */\r
+#define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */\r
+#define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */\r
+#define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */\r
+#define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */\r
+#define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */\r
+#define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */\r
+#define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */\r
+#define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */\r
+#define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */\r
+#define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */\r
+#define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */\r
+#define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */\r
+#define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */\r
+#define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */\r
+\r
+#define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */\r
+#define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */\r
+\r
+#define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */\r
+#define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */\r
+\r
+#define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */\r
+#define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */\r
+\r
+#define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */\r
+#define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */\r
+\r
+#define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */\r
+#define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */\r
+\r
+#define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */\r
+#define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */\r
+\r
+#define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */\r
+#define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */\r
+\r
+#define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */\r
+#define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */\r
+\r
+#define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */\r
+#define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */\r
+\r
+#define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */\r
+#define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */\r
+\r
+#define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */\r
+#define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */\r
+\r
+#define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */\r
+#define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */\r
+\r
+#define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */\r
+#define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */\r
+\r
+#define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */\r
+#define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */\r
+\r
+#define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */\r
+#define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */\r
+\r
+#define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */\r
+#define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */\r
+\r
+#define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */\r
+#define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */\r
+\r
+#define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */\r
+#define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */\r
+\r
+#define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */\r
+#define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */\r
+\r
+#define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */\r
+#define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */\r
+\r
+#define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */\r
+#define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */\r
+\r
+#define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */\r
+#define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */\r
+\r
+#define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */\r
+#define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */\r
+\r
+#define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */\r
+#define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */\r
+\r
+#define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */\r
+#define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */\r
+\r
+#define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */\r
+#define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */\r
+\r
+#define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */\r
+#define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */\r
+\r
+#define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */\r
+#define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */\r
+\r
+#define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */\r
+#define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */\r
+\r
+#define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */\r
+#define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */\r
+\r
+#define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */\r
+#define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */\r
+\r
+#define SYS_SRAMICTL_PERRIEN_Pos (0) /*!< SYS_T::SRAMICTL: PERRIEN Position */\r
+#define SYS_SRAMICTL_PERRIEN_Msk (0x1ul << SYS_SRAMICTL_PERRIEN_Pos) /*!< SYS_T::SRAMICTL: PERRIEN Mask */\r
+\r
+#define SYS_SRAMSTS_PERRIF_Pos (0) /*!< SYS_T::SRAMSTS: PERRIF Position */\r
+#define SYS_SRAMSTS_PERRIF_Msk (0x1ul << SYS_SRAMSTS_PERRIF_Pos) /*!< SYS_T::SRAMSTS: PERRIF Mask */\r
+\r
+#define SYS_SRAMEADR_ERRADDR_Pos (0) /*!< SYS_T::SRAMEADR: ERRADDR Position */\r
+#define SYS_SRAMEADR_ERRADDR_Msk (0xfffffffful << SYS_SRAMEADR_ERRADDR_Pos) /*!< SYS_T::SRAMEADR: ERRADDR Mask */\r
+\r
+#define SYS_SRAMPCTL_STACK_Pos (0) /*!< SYS_T::SRAMPCTL: STACK Position */\r
+#define SYS_SRAMPCTL_STACK_Msk (0xful << SYS_SRAMPCTL_STACK_Pos) /*!< SYS_T::SRAMPCTL: STACK Mask */\r
+\r
+#define SYS_SRAMPCTL_RETCNT_Pos (4) /*!< SYS_T::SRAMPCTL: RETCNT Position */\r
+#define SYS_SRAMPCTL_RETCNT_Msk (0x3ul << SYS_SRAMPCTL_RETCNT_Pos) /*!< SYS_T::SRAMPCTL: RETCNT Mask */\r
+\r
+#define SYS_SRAMPCTL_SRAM0PM0_Pos (8) /*!< SYS_T::SRAMPCTL: SRAM0PM0 Position */\r
+#define SYS_SRAMPCTL_SRAM0PM0_Msk (0x3ul << SYS_SRAMPCTL_SRAM0PM0_Pos) /*!< SYS_T::SRAMPCTL: SRAM0PM0 Mask */\r
+\r
+#define SYS_SRAMPCTL_SRAM0PM1_Pos (10) /*!< SYS_T::SRAMPCTL: SRAM0PM1 Position */\r
+#define SYS_SRAMPCTL_SRAM0PM1_Msk (0x3ul << SYS_SRAMPCTL_SRAM0PM1_Pos) /*!< SYS_T::SRAMPCTL: SRAM0PM1 Mask */\r
+\r
+#define SYS_SRAMPCTL_SRAM0PM2_Pos (12) /*!< SYS_T::SRAMPCTL: SRAM0PM2 Position */\r
+#define SYS_SRAMPCTL_SRAM0PM2_Msk (0x3ul << SYS_SRAMPCTL_SRAM0PM2_Pos) /*!< SYS_T::SRAMPCTL: SRAM0PM2 Mask */\r
+\r
+#define SYS_SRAMPCTL_SRAM0PM3_Pos (14) /*!< SYS_T::SRAMPCTL: SRAM0PM3 Position */\r
+#define SYS_SRAMPCTL_SRAM0PM3_Msk (0x3ul << SYS_SRAMPCTL_SRAM0PM3_Pos) /*!< SYS_T::SRAMPCTL: SRAM0PM3 Mask */\r
+\r
+#define SYS_SRAMPCTL_SRAM1PM0_Pos (16) /*!< SYS_T::SRAMPCTL: SRAM1PM0 Position */\r
+#define SYS_SRAMPCTL_SRAM1PM0_Msk (0x3ul << SYS_SRAMPCTL_SRAM1PM0_Pos) /*!< SYS_T::SRAMPCTL: SRAM1PM0 Mask */\r
+\r
+#define SYS_SRAMPCTL_SRAM1PM1_Pos (18) /*!< SYS_T::SRAMPCTL: SRAM1PM1 Position */\r
+#define SYS_SRAMPCTL_SRAM1PM1_Msk (0x3ul << SYS_SRAMPCTL_SRAM1PM1_Pos) /*!< SYS_T::SRAMPCTL: SRAM1PM1 Mask */\r
+\r
+#define SYS_SRAMPCTL_SRAM1PM2_Pos (20) /*!< SYS_T::SRAMPCTL: SRAM1PM2 Position */\r
+#define SYS_SRAMPCTL_SRAM1PM2_Msk (0x3ul << SYS_SRAMPCTL_SRAM1PM2_Pos) /*!< SYS_T::SRAMPCTL: SRAM1PM2 Mask */\r
+\r
+#define SYS_SRAMPCTL_SRAM1PM3_Pos (22) /*!< SYS_T::SRAMPCTL: SRAM1PM3 Position */\r
+#define SYS_SRAMPCTL_SRAM1PM3_Msk (0x3ul << SYS_SRAMPCTL_SRAM1PM3_Pos) /*!< SYS_T::SRAMPCTL: SRAM1PM3 Mask */\r
+\r
+#define SYS_SRAMPPCT_CAN_Pos (0) /*!< SYS_T::SRAMPPCT: CAN Position */\r
+#define SYS_SRAMPPCT_CAN_Msk (0x3ul << SYS_SRAMPPCT_CAN_Pos) /*!< SYS_T::SRAMPPCT: CAN Mask */\r
+\r
+#define SYS_SRAMPPCT_USBD_Pos (2) /*!< SYS_T::SRAMPPCT: USBD Position */\r
+#define SYS_SRAMPPCT_USBD_Msk (0x3ul << SYS_SRAMPPCT_USBD_Pos) /*!< SYS_T::SRAMPPCT: USBD Mask */\r
+\r
+#define SYS_SRAMPPCT_PDMA0_Pos (4) /*!< SYS_T::SRAMPPCT: PDMA0 Position */\r
+#define SYS_SRAMPPCT_PDMA0_Msk (0x3ul << SYS_SRAMPPCT_PDMA0_Pos) /*!< SYS_T::SRAMPPCT: PDMA0 Mask */\r
+\r
+#define SYS_SRAMPPCT_PDMA1_Pos (6) /*!< SYS_T::SRAMPPCT: PDMA1 Position */\r
+#define SYS_SRAMPPCT_PDMA1_Msk (0x3ul << SYS_SRAMPPCT_PDMA1_Pos) /*!< SYS_T::SRAMPPCT: PDMA1 Mask */\r
+\r
+#define SYS_SRAMPPCT_FMC_Pos (8) /*!< SYS_T::SRAMPPCT: FMC Position */\r
+#define SYS_SRAMPPCT_FMC_Msk (0x3ul << SYS_SRAMPPCT_FMC_Pos) /*!< SYS_T::SRAMPPCT: FMC Mask */\r
+\r
+#define SYS_TCTL48M_FREQSEL_Pos (0) /*!< SYS_T::TCTL48M: FREQSEL Position */\r
+#define SYS_TCTL48M_FREQSEL_Msk (0x3ul << SYS_TCTL48M_FREQSEL_Pos) /*!< SYS_T::TCTL48M: FREQSEL Mask */\r
+\r
+#define SYS_TCTL48M_LOOPSEL_Pos (4) /*!< SYS_T::TCTL48M: LOOPSEL Position */\r
+#define SYS_TCTL48M_LOOPSEL_Msk (0x3ul << SYS_TCTL48M_LOOPSEL_Pos) /*!< SYS_T::TCTL48M: LOOPSEL Mask */\r
+\r
+#define SYS_TCTL48M_RETRYCNT_Pos (6) /*!< SYS_T::TCTL48M: RETRYCNT Position */\r
+#define SYS_TCTL48M_RETRYCNT_Msk (0x3ul << SYS_TCTL48M_RETRYCNT_Pos) /*!< SYS_T::TCTL48M: RETRYCNT Mask */\r
+\r
+#define SYS_TCTL48M_CESTOPEN_Pos (8) /*!< SYS_T::TCTL48M: CESTOPEN Position */\r
+#define SYS_TCTL48M_CESTOPEN_Msk (0x1ul << SYS_TCTL48M_CESTOPEN_Pos) /*!< SYS_T::TCTL48M: CESTOPEN Mask */\r
+\r
+#define SYS_TCTL48M_REFCKSEL_Pos (10) /*!< SYS_T::TCTL48M: REFCKSEL Position */\r
+#define SYS_TCTL48M_REFCKSEL_Msk (0x1ul << SYS_TCTL48M_REFCKSEL_Pos) /*!< SYS_T::TCTL48M: REFCKSEL Mask */\r
+\r
+#define SYS_TIEN48M_TFAILIEN_Pos (1) /*!< SYS_T::TIEN48M: TFAILIEN Position */\r
+#define SYS_TIEN48M_TFAILIEN_Msk (0x1ul << SYS_TIEN48M_TFAILIEN_Pos) /*!< SYS_T::TIEN48M: TFAILIEN Mask */\r
+\r
+#define SYS_TIEN48M_CLKEIEN_Pos (2) /*!< SYS_T::TIEN48M: CLKEIEN Position */\r
+#define SYS_TIEN48M_CLKEIEN_Msk (0x1ul << SYS_TIEN48M_CLKEIEN_Pos) /*!< SYS_T::TIEN48M: CLKEIEN Mask */\r
+\r
+#define SYS_TISTS48M_FREQLOCK_Pos (0) /*!< SYS_T::TISTS48M: FREQLOCK Position */\r
+#define SYS_TISTS48M_FREQLOCK_Msk (0x1ul << SYS_TISTS48M_FREQLOCK_Pos) /*!< SYS_T::TISTS48M: FREQLOCK Mask */\r
+\r
+#define SYS_TISTS48M_TFAILIF_Pos (1) /*!< SYS_T::TISTS48M: TFAILIF Position */\r
+#define SYS_TISTS48M_TFAILIF_Msk (0x1ul << SYS_TISTS48M_TFAILIF_Pos) /*!< SYS_T::TISTS48M: TFAILIF Mask */\r
+\r
+#define SYS_TISTS48M_CLKERRIF_Pos (2) /*!< SYS_T::TISTS48M: CLKERRIF Position */\r
+#define SYS_TISTS48M_CLKERRIF_Msk (0x1ul << SYS_TISTS48M_CLKERRIF_Pos) /*!< SYS_T::TISTS48M: CLKERRIF Mask */\r
+\r
+#define SYS_TCTL12M_FREQSEL_Pos (0) /*!< SYS_T::TCTL12M: FREQSEL Position */\r
+#define SYS_TCTL12M_FREQSEL_Msk (0x3ul << SYS_TCTL12M_FREQSEL_Pos) /*!< SYS_T::TCTL12M: FREQSEL Mask */\r
+\r
+#define SYS_TCTL12M_LOOPSEL_Pos (4) /*!< SYS_T::TCTL12M: LOOPSEL Position */\r
+#define SYS_TCTL12M_LOOPSEL_Msk (0x3ul << SYS_TCTL12M_LOOPSEL_Pos) /*!< SYS_T::TCTL12M: LOOPSEL Mask */\r
+\r
+#define SYS_TCTL12M_RETRYCNT_Pos (6) /*!< SYS_T::TCTL12M: RETRYCNT Position */\r
+#define SYS_TCTL12M_RETRYCNT_Msk (0x3ul << SYS_TCTL12M_RETRYCNT_Pos) /*!< SYS_T::TCTL12M: RETRYCNT Mask */\r
+\r
+#define SYS_TCTL12M_CESTOPEN_Pos (8) /*!< SYS_T::TCTL12M: CESTOPEN Position */\r
+#define SYS_TCTL12M_CESTOPEN_Msk (0x1ul << SYS_TCTL12M_CESTOPEN_Pos) /*!< SYS_T::TCTL12M: CESTOPEN Mask */\r
+\r
+#define SYS_TCTL12M_REFCKSEL_Pos (10) /*!< SYS_T::TCTL12M: REFCKSEL Position */\r
+#define SYS_TCTL12M_REFCKSEL_Msk (0x1ul << SYS_TCTL12M_REFCKSEL_Pos) /*!< SYS_T::TCTL12M: REFCKSEL Mask */\r
+\r
+#define SYS_TIEN12M_TFAILIEN_Pos (1) /*!< SYS_T::TIEN12M: TFAILIEN Position */\r
+#define SYS_TIEN12M_TFAILIEN_Msk (0x1ul << SYS_TIEN12M_TFAILIEN_Pos) /*!< SYS_T::TIEN12M: TFAILIEN Mask */\r
+\r
+#define SYS_TIEN12M_CLKEIEN_Pos (2) /*!< SYS_T::TIEN12M: CLKEIEN Position */\r
+#define SYS_TIEN12M_CLKEIEN_Msk (0x1ul << SYS_TIEN12M_CLKEIEN_Pos) /*!< SYS_T::TIEN12M: CLKEIEN Mask */\r
+\r
+#define SYS_TISTS12M_FREQLOCK_Pos (0) /*!< SYS_T::TISTS12M: FREQLOCK Position */\r
+#define SYS_TISTS12M_FREQLOCK_Msk (0x1ul << SYS_TISTS12M_FREQLOCK_Pos) /*!< SYS_T::TISTS12M: FREQLOCK Mask */\r
+\r
+#define SYS_TISTS12M_TFAILIF_Pos (1) /*!< SYS_T::TISTS12M: TFAILIF Position */\r
+#define SYS_TISTS12M_TFAILIF_Msk (0x1ul << SYS_TISTS12M_TFAILIF_Pos) /*!< SYS_T::TISTS12M: TFAILIF Mask */\r
+\r
+#define SYS_TISTS12M_CLKERRIF_Pos (2) /*!< SYS_T::TISTS12M: CLKERRIF Position */\r
+#define SYS_TISTS12M_CLKERRIF_Msk (0x1ul << SYS_TISTS12M_CLKERRIF_Pos) /*!< SYS_T::TISTS12M: CLKERRIF Mask */\r
+\r
+#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */\r
+#define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */\r
+\r
+#define SYS_PORCTL1_POROFF_Pos (0) /*!< SYS_T::PORCTL1: POROFF Position */\r
+#define SYS_PORCTL1_POROFF_Msk (0xfffful << SYS_PORCTL1_POROFF_Pos) /*!< SYS_T::PORCTL1: POROFF Mask */\r
+\r
+#define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */\r
+#define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */\r
+\r
+#define SYS_PLCTL_MVRS_Pos (4) /*!< SYS_T::PLCTL: MVRS Position */\r
+#define SYS_PLCTL_MVRS_Msk (0x1ul << SYS_PLCTL_MVRS_Pos) /*!< SYS_T::PLCTL: MVRS Mask */\r
+\r
+#define SYS_PLCTL_LVSSTP_Pos (16) /*!< SYS_T::PLCTL: LVSSTP Position */\r
+#define SYS_PLCTL_LVSSTP_Msk (0x3ful << SYS_PLCTL_LVSSTP_Pos) /*!< SYS_T::PLCTL: LVSSTP Mask */\r
+\r
+#define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */\r
+#define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */\r
+\r
+#define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */\r
+#define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */\r
+\r
+#define SYS_PLSTS_MVRCBUSY_Pos (1) /*!< SYS_T::PLSTS: MVRCBUSY Position */\r
+#define SYS_PLSTS_MVRCBUSY_Msk (0x1ul << SYS_PLSTS_MVRCBUSY_Pos) /*!< SYS_T::PLSTS: MVRCBUSY Mask */\r
+\r
+#define SYS_PLSTS_MVRCERR_Pos (2) /*!< SYS_T::PLSTS: MVRCERR Position */\r
+#define SYS_PLSTS_MVRCERR_Msk (0x1ul << SYS_PLSTS_MVRCERR_Pos) /*!< SYS_T::PLSTS: MVRCERR Mask */\r
+\r
+#define SYS_PLSTS_LCONS_Pos (3) /*!< SYS_T::PLSTS: LCONS Position */\r
+#define SYS_PLSTS_LCONS_Msk (0x1ul << SYS_PLSTS_LCONS_Pos) /*!< SYS_T::PLSTS: LCONS Mask */\r
+\r
+#define SYS_PLSTS_PDINVTRF_Pos (4) /*!< SYS_T::PLSTS: PDINVTRF Position */\r
+#define SYS_PLSTS_PDINVTRF_Msk (0x1ul << SYS_PLSTS_PDINVTRF_Pos) /*!< SYS_T::PLSTS: PDINVTRF Mask */\r
+\r
+#define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */\r
+#define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */\r
+\r
+#define SYS_PLSTS_CURMVR_Pos (12) /*!< SYS_T::PLSTS: CURMVR Position */\r
+#define SYS_PLSTS_CURMVR_Msk (0x1ul << SYS_PLSTS_CURMVR_Pos) /*!< SYS_T::PLSTS: CURMVR Mask */\r
+\r
+#define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */\r
+#define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */\r
+\r
+\r
+/**@}*/ /* SYS_CONST */\r
+typedef struct\r
+{\r
+\r
+ /**\r
+ * @var SYS_INT_T::NMIEN\r
+ * Offset: 0x00 NMI Source Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BODOUT |BOD NMI Source Enable (Write Protect)\r
+ * | | |0 = BOD NMI source Disabled.\r
+ * | | |1 = BOD NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[1] |IRCINT |IRC TRIM NMI Source Enable (Write Protect)\r
+ * | | |0 = IRC TRIM NMI source Disabled.\r
+ * | | |1 = IRC TRIM NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[2] |PWRWUINT |Power-down Mode Wake-up NMI Source Enable (Write Protect)\r
+ * | | |0 = Power-down mode wake-up NMI source Disabled.\r
+ * | | |1 = Power-down mode wake-up NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[3] |SRAMPERR |SRAM Parity Check Error NMI Source Enable (Write Protect)\r
+ * | | |0 = SRAM parity check error NMI source Disabled.\r
+ * | | |1 = SRAM parity check error NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[4] |CLKFAIL |Clock Fail Detected NMI Source Enable (Write Protect)\r
+ * | | |0 = Clock fail detected interrupt NMI source Disabled.\r
+ * | | |1 = Clock fail detected interrupt NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[6] |RTCINT |RTC NMI Source Enable (Write Protect)\r
+ * | | |0 = RTC NMI source Disabled.\r
+ * | | |1 = RTC NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[7] |TAMPERINT |Tamper Interrupt NMI Source Enable (Write Protect)\r
+ * | | |0 = Backup register tamper detected interrupt NMI source Disabled.\r
+ * | | |1 = Backup register tamper detected interrupt NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[8] |EINT0 |External Interrupt From PA.6, or PB.5 Pin NMI Source Enable (Write Protect)\r
+ * | | |0 = External interrupt from PA.6, or PB.5 pin NMI source Disabled.\r
+ * | | |1 = External interrupt from PA.6, or PB.5 pin NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[9] |EINT1 |External Interrupt From PA.7 or PB.4 Pin NMI Source Enable (Write Protect)\r
+ * | | |0 = External interrupt from PA.7 or PB.4 pin NMI source Disabled.\r
+ * | | |1 = External interrupt from PA.7 or P4.4 pin NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect)\r
+ * | | |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled.\r
+ * | | |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect)\r
+ * | | |0 = External interrupt from PB.2 or PC.7pin NMI source Disabled.\r
+ * | | |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[12] |EINT4 |External Interrupt From PA.8 or PB.6 Pin NMI Source Enable (Write Protect)\r
+ * | | |0 = External interrupt from PA.8 or PB.6 pin NMI source Disabled.\r
+ * | | |1 = External interrupt from PA.8 or PB.6 pin NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[13] |EINT5 |External Interrupt From PB.7 or PD.12 Pin NMI Source Enable (Write Protect)\r
+ * | | |0 = External interrupt from PB.7 or PD.12 pin NMI source Disabled.\r
+ * | | |1 = External interrupt from PB.7 or PD.12 pin NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[14] |UART0INT |UART0 NMI Source Enable (Write Protect)\r
+ * | | |0 = UART0 NMI source Disabled.\r
+ * | | |1 = UART0 NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[15] |UART1INT |UART1 NMI Source Enable (Write Protect)\r
+ * | | |0 = UART1 NMI source Disabled.\r
+ * | | |1 = UART1 NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[16] |EINT6 |External Interrupt From PB.8 or PD.11 Pin NMI Source Enable (Write Protect)\r
+ * | | |0 = External interrupt from PB.8 or PD.11 pin NMI source Disabled.\r
+ * | | |1 = External interrupt from PB.8 or PD.11 pin NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[17] |EINT7 |External Interrupt From PB.9 or PD.10 Pin NMI Source Enable (Write Protect)\r
+ * | | |0 = External interrupt from PB.9 or PD.10 pin NMI source Disabled.\r
+ * | | |1 = External interrupt from PB.9 or PD.10 pin NMI source Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * @var SYS_INT_T::NMISTS\r
+ * Offset: 0x04 NMI source interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BODOUT |BOD Interrupt Flag (Read Only)\r
+ * | | |0 = BOD interrupt is de-asserted.\r
+ * | | |1 = BOD interrupt is asserted.\r
+ * |[1] |IRCINT |IRC TRIM Interrupt Flag (Read Only)\r
+ * | | |0 = HIRC TRIM interrupt is de-asserted.\r
+ * | | |1 = HIRC TRIM interrupt is asserted.\r
+ * |[2] |PWRWUINT |Power-down Mode Wake-up Interrupt Flag (Read Only)\r
+ * | | |0 = Power-down mode wake-up interrupt is de-asserted.\r
+ * | | |1 = Power-down mode wake-up interrupt is asserted.\r
+ * |[3] |SRAMPERR |SRAM Parity Check Error Interrupt Flag (Read Only)\r
+ * | | |0 = SRAM parity check error interrupt is de-asserted.\r
+ * | | |1 = SRAM parity check error interrupt is asserted.\r
+ * |[4] |CLKFAIL |Clock Fail Detected Interrupt Flag (Read Only)\r
+ * | | |0 = Clock fail detected interrupt is de-asserted.\r
+ * | | |1 = Clock fail detected interrupt is asserted.\r
+ * |[6] |RTCINT |RTC Interrupt Flag (Read Only)\r
+ * | | |0 = RTC interrupt is de-asserted.\r
+ * | | |1 = RTC interrupt is asserted.\r
+ * |[7] |TAMPERINT |Tamper Interrupt Flag (Read Only)\r
+ * | | |0 = Backup register tamper detected interrupt is de-asserted.\r
+ * | | |1 = Backup register tamper detected interrupt is asserted.\r
+ * |[8] |EINT0 |External Interrupt From PA.6, or PB.5 Pin Interrupt Flag (Read Only)\r
+ * | | |0 = External Interrupt from PA.6, or PB.5 interrupt is deasserted.\r
+ * | | |1 = External Interrupt from PA.6, or PB.5 interrupt is asserted.\r
+ * |[9] |EINT1 |External Interrupt From PA.7, or PB.4 Pin Interrupt Flag (Read Only)\r
+ * | | |0 = External Interrupt from PA.7, or PB.4 interrupt is deasserted.\r
+ * | | |1 = External Interrupt from PA.7, or PB.4 interrupt is asserted.\r
+ * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only)\r
+ * | | |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted.\r
+ * | | |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted.\r
+ * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only)\r
+ * | | |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted.\r
+ * | | |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted.\r
+ * |[12] |EINT4 |External Interrupt From PA.8 or PB.6 Pin Interrupt Flag (Read Only)\r
+ * | | |0 = External Interrupt from PA.8 or PB.6 interrupt is deasserted.\r
+ * | | |1 = External Interrupt from PA.8 or PB.6 interrupt is asserted.\r
+ * |[13] |EINT5 |External Interrupt From PB.7 or PD.12 Pin Interrupt Flag (Read Only)\r
+ * | | |0 = External Interrupt from PB.7 or PD.12 interrupt is deasserted.\r
+ * | | |1 = External Interrupt from PB.7 or PD.12 interrupt is asserted.\r
+ * |[14] |UART0INT |UART0 Interrupt Flag (Read Only)\r
+ * | | |0 = UART1 interrupt is de-asserted.\r
+ * | | |1 = UART1 interrupt is asserted.\r
+ * |[15] |UART1INT |UART1 Interrupt Flag (Read Only)\r
+ * | | |0 = UART1 interrupt is de-asserted.\r
+ * | | |1 = UART1 interrupt is asserted.\r
+ * |[16] |EINT6 |External Interrupt From PB.8 or PD.11 Pin Interrupt Flag (Read Only)\r
+ * | | |0 = External Interrupt from PB.8 or PD.11 interrupt is deasserted.\r
+ * | | |1 = External Interrupt from PB.8 or PD.11 interrupt is asserted.\r
+ * |[17] |EINT7 |External Interrupt From PB.9 or PD.10 Pin Interrupt Flag (Read Only)\r
+ * | | |0 = External Interrupt from PB.9 or PD.10 interrupt is deasserted.\r
+ * | | |1 = External Interrupt from PB.9 or PD.10 interrupt is asserted.\r
+ */\r
+\r
+ __IO uint32_t NMIEN; /* Offset: 0x00 NMI Source Interrupt Enable Register */\r
+ __I uint32_t NMISTS; /* Offset: 0x04 NMI source interrupt Status Register */\r
+\r
+} SYS_INT_T;\r
+/**\r
+ @addtogroup INT_CONST INT Bit Field Definition\r
+ Constant Definitions for INT Controller\r
+@{ */\r
+\r
+#define SYS_NMIEN_BODOUT_Pos (0) /*!< SYS_INT_T::NMIEN: BODOUT Position */\r
+#define SYS_NMIEN_BODOUT_Msk (0x1ul << SYS_NMIEN_BODOUT_Pos ) /*!< SYS_INT_T::NMIEN: BODOUT Mask */\r
+\r
+#define SYS_NMIEN_IRCINT_Pos (1) /*!< SYS_INT_T::NMIEN: IRCINT Position */\r
+#define SYS_NMIEN_IRCINT_Msk (0x1ul << SYS_NMIEN_IRCINT_Pos ) /*!< SYS_INT_T::NMIEN: IRCINT Mask */\r
+\r
+#define SYS_NMIEN_PWRWUINT_Pos (2) /*!< SYS_INT_T::NMIEN: PWRWUINT Position */\r
+#define SYS_NMIEN_PWRWUINT_Msk (0x1ul << SYS_NMIEN_PWRWUINT_Pos ) /*!< SYS_INT_T::NMIEN: PWRWUINT Mask */\r
+\r
+#define SYS_NMIEN_SRAMPERR_Pos (3) /*!< SYS_INT_T::NMIEN: SRAMPERR Position */\r
+#define SYS_NMIEN_SRAMPERR_Msk (0x1ul << SYS_NMIEN_SRAMPERR_Pos ) /*!< SYS_INT_T::NMIEN: SRAMPERR Mask */\r
+\r
+#define SYS_NMIEN_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMIEN: CLKFAIL Position */\r
+#define SYS_NMIEN_CLKFAIL_Msk (0x1ul << SYS_NMIEN_CLKFAIL_Pos ) /*!< SYS_INT_T::NMIEN: CLKFAIL Mask */\r
+\r
+#define SYS_NMIEN_RTCINT_Pos (6) /*!< SYS_INT_T::NMIEN: RTCINT Position */\r
+#define SYS_NMIEN_RTCINT_Msk (0x1ul << SYS_NMIEN_RTCINT_Pos ) /*!< SYS_INT_T::NMIEN: RTCINT Mask */\r
+\r
+#define SYS_NMIEN_TAMPERINT_Pos (7) /*!< SYS_INT_T::NMIEN: TAMPERINT Position */\r
+#define SYS_NMIEN_TAMPERINT_Msk (0x1ul << SYS_NMIEN_TAMPERINT_Pos ) /*!< SYS_INT_T::NMIEN: TAMPERINT Mask */\r
+\r
+#define SYS_NMIEN_EINT0_Pos (8) /*!< SYS_INT_T::NMIEN: EINT0 Position */\r
+#define SYS_NMIEN_EINT0_Msk (0x1ul << SYS_NMIEN_EINT0_Pos ) /*!< SYS_INT_T::NMIEN: EINT0 Mask */\r
+\r
+#define SYS_NMIEN_EINT1_Pos (9) /*!< SYS_INT_T::NMIEN: EINT1 Position */\r
+#define SYS_NMIEN_EINT1_Msk (0x1ul << SYS_NMIEN_EINT1_Pos ) /*!< SYS_INT_T::NMIEN: EINT1 Mask */\r
+\r
+#define SYS_NMIEN_EINT2_Pos (10) /*!< SYS_INT_T::NMIEN: EINT2 Position */\r
+#define SYS_NMIEN_EINT2_Msk (0x1ul << SYS_NMIEN_EINT2_Pos ) /*!< SYS_INT_T::NMIEN: EINT2 Mask */\r
+\r
+#define SYS_NMIEN_EINT3_Pos (11) /*!< SYS_INT_T::NMIEN: EINT3 Position */\r
+#define SYS_NMIEN_EINT3_Msk (0x1ul << SYS_NMIEN_EINT3_Pos ) /*!< SYS_INT_T::NMIEN: EINT3 Mask */\r
+\r
+#define SYS_NMIEN_EINT4_Pos (12) /*!< SYS_INT_T::NMIEN: EINT4 Position */\r
+#define SYS_NMIEN_EINT4_Msk (0x1ul << SYS_NMIEN_EINT4_Pos ) /*!< SYS_INT_T::NMIEN: EINT4 Mask */\r
+\r
+#define SYS_NMIEN_EINT5_Pos (13) /*!< SYS_INT_T::NMIEN: EINT5 Position */\r
+#define SYS_NMIEN_EINT5_Msk (0x1ul << SYS_NMIEN_EINT5_Pos ) /*!< SYS_INT_T::NMIEN: EINT5 Mask */\r
+\r
+#define SYS_NMIEN_UART0INT_Pos (14) /*!< SYS_INT_T::NMIEN: UART0INT Position */\r
+#define SYS_NMIEN_UART0INT_Msk (0x1ul << SYS_NMIEN_UART0INT_Pos ) /*!< SYS_INT_T::NMIEN: UART0INT Mask */\r
+\r
+#define SYS_NMIEN_UART1INT_Pos (15) /*!< SYS_INT_T::NMIEN: UART1INT Position */\r
+#define SYS_NMIEN_UART1INT_Msk (0x1ul << SYS_NMIEN_UART1INT_Pos ) /*!< SYS_INT_T::NMIEN: UART1INT Mask */\r
+\r
+#define SYS_NMIEN_EINT6_Pos (16) /*!< SYS_INT_T::NMIEN: EINT6 Position */\r
+#define SYS_NMIEN_EINT6_Msk (0x1ul << SYS_NMIEN_EINT6_Pos ) /*!< SYS_INT_T::NMIEN: EINT6 Mask */\r
+\r
+#define SYS_NMIEN_EINT7_Pos (17) /*!< SYS_INT_T::NMIEN: EINT7 Position */\r
+#define SYS_NMIEN_EINT7_Msk (0x1ul << SYS_NMIEN_EINT7_Pos ) /*!< SYS_INT_T::NMIEN: EINT7 Mask */\r
+\r
+#define SYS_NMISTS_BODOUT_Pos (0) /*!< SYS_INT_T::NMISTS: BODOUT Position */\r
+#define SYS_NMISTS_BODOUT_Msk (0x1ul << SYS_NMISTS_BODOUT_Pos ) /*!< SYS_INT_T::NMISTS: BODOUT Mask */\r
+\r
+#define SYS_NMISTS_IRCINT_Pos (1) /*!< SYS_INT_T::NMISTS: IRCINT Position */\r
+#define SYS_NMISTS_IRCINT_Msk (0x1ul << SYS_NMISTS_IRCINT_Pos ) /*!< SYS_INT_T::NMISTS: IRCINT Mask */\r
+\r
+#define SYS_NMISTS_PWRWUINT_Pos (2) /*!< SYS_INT_T::NMISTS: PWRWUINT Position */\r
+#define SYS_NMISTS_PWRWUINT_Msk (0x1ul << SYS_NMISTS_PWRWUINT_Pos ) /*!< SYS_INT_T::NMISTS: PWRWUINT Mask */\r
+\r
+#define SYS_NMISTS_SRAMPERR_Pos (3) /*!< SYS_INT_T::NMISTS: SRAMPERR Position */\r
+#define SYS_NMISTS_SRAMPERR_Msk (0x1ul << SYS_NMISTS_SRAMPERR_Pos ) /*!< SYS_INT_T::NMISTS: SRAMPERR Mask */\r
+\r
+#define SYS_NMISTS_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMISTS: CLKFAIL Position */\r
+#define SYS_NMISTS_CLKFAIL_Msk (0x1ul << SYS_NMISTS_CLKFAIL_Pos ) /*!< SYS_INT_T::NMISTS: CLKFAIL Mask */\r
+\r
+#define SYS_NMISTS_RTCINT_Pos (6) /*!< SYS_INT_T::NMISTS: RTCINT Position */\r
+#define SYS_NMISTS_RTCINT_Msk (0x1ul << SYS_NMISTS_RTCINT_Pos ) /*!< SYS_INT_T::NMISTS: RTCINT Mask */\r
+\r
+#define SYS_NMISTS_TAMPERINT_Pos (7) /*!< SYS_INT_T::NMISTS: TAMPERINT Position */\r
+#define SYS_NMISTS_TAMPERINT_Msk (0x1ul << SYS_NMISTS_TAMPERINT_Pos ) /*!< SYS_INT_T::NMISTS: TAMPERINT Mask */\r
+\r
+#define SYS_NMISTS_EINT0_Pos (8) /*!< SYS_INT_T::NMISTS: EINT0 Position */\r
+#define SYS_NMISTS_EINT0_Msk (0x1ul << SYS_NMISTS_EINT0_Pos ) /*!< SYS_INT_T::NMISTS: EINT0 Mask */\r
+\r
+#define SYS_NMISTS_EINT1_Pos (9) /*!< SYS_INT_T::NMISTS: EINT1 Position */\r
+#define SYS_NMISTS_EINT1_Msk (0x1ul << SYS_NMISTS_EINT1_Pos ) /*!< SYS_INT_T::NMISTS: EINT1 Mask */\r
+\r
+#define SYS_NMISTS_EINT2_Pos (10) /*!< SYS_INT_T::NMISTS: EINT2 Position */\r
+#define SYS_NMISTS_EINT2_Msk (0x1ul << SYS_NMISTS_EINT2_Pos ) /*!< SYS_INT_T::NMISTS: EINT2 Mask */\r
+\r
+#define SYS_NMISTS_EINT3_Pos (11) /*!< SYS_INT_T::NMISTS: EINT3 Position */\r
+#define SYS_NMISTS_EINT3_Msk (0x1ul << SYS_NMISTS_EINT3_Pos ) /*!< SYS_INT_T::NMISTS: EINT3 Mask */\r
+\r
+#define SYS_NMISTS_EINT4_Pos (12) /*!< SYS_INT_T::NMISTS: EINT4 Position */\r
+#define SYS_NMISTS_EINT4_Msk (0x1ul << SYS_NMISTS_EINT4_Pos ) /*!< SYS_INT_T::NMISTS: EINT4 Mask */\r
+\r
+#define SYS_NMISTS_EINT5_Pos (13) /*!< SYS_INT_T::NMISTS: EINT5 Position */\r
+#define SYS_NMISTS_EINT5_Msk (0x1ul << SYS_NMISTS_EINT5_Pos ) /*!< SYS_INT_T::NMISTS: EINT5 Mask */\r
+\r
+#define SYS_NMISTS_UART0INT_Pos (14) /*!< SYS_INT_T::NMISTS: UART0_INT Position */\r
+#define SYS_NMISTS_UART0INT_Msk (0x1ul << SYS_NMISTS_UART0INT_Pos ) /*!< SYS_INT_T::NMISTS: UART0_INT Mask */\r
+\r
+#define SYS_NMISTS_UART1INT_Pos (15) /*!< SYS_INT_T::NMISTS: UART1_INT Position */\r
+#define SYS_NMISTS_UART1INT_Msk (0x1ul << SYS_NMISTS_UART1INT_Pos ) /*!< SYS_INT_T::NMISTS: UART1_INT Mask */\r
+\r
+#define SYS_NMISTS_EINT6_Pos (16) /*!< SYS_INT_T::NMISTS: EINT6 Position */\r
+#define SYS_NMISTS_EINT6_Msk (0x1ul << SYS_NMISTS_EINT6_Pos ) /*!< SYS_INT_T::NMISTS: EINT6 Mask */\r
+\r
+#define SYS_NMISTS_EINT7_Pos (17) /*!< SYS_INT_T::NMISTS: EINT7 Position */\r
+#define SYS_NMISTS_EINT7_Msk (0x1ul << SYS_NMISTS_EINT7_Pos ) /*!< SYS_INT_T::NMISTS: EINT7 Mask */\r
+\r
+\r
+/**@}*/ /* INT_CONST */\r
+/**@}*/ /* end of SYS register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __SYS_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_M2351.h\r
+ * @version V3.00\r
+ * @brief System Setting Header File\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __SYSTEM_M2351_H__\r
+#define __SYSTEM_M2351_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Macro Definition */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#ifndef DEBUG_PORT\r
+# define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */\r
+#endif\r
+\r
+\r
+/* Init ETM Interface Multi-function Pins */\r
+#define ETM_INIT() { \\r
+ SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC0MFP_ETM_TRACE_Msk | SYS_GPC_MFPL_PC1MFP_ETM_TRACE_Msk | \\r
+ SYS_GPC_MFPL_PC2MFP_ETM_TRACE_Msk | SYS_GPC_MFPL_PC3MFP_ETM_TRACE_Msk | \\r
+ SYS_GPC_MFPL_PC4MFP_ETM_TRACE_Msk); \\r
+ SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_ETM_TRACE_CLK | SYS_GPC_MFPL_PC1MFP_ETM_TRACE_DATA0 | \\r
+ SYS_GPC_MFPL_PC2MFP_ETM_TRACE_DATA1 | SYS_GPC_MFPL_PC3MFP_ETM_TRACE_DATA2 | \\r
+ SYS_GPC_MFPL_PC4MFP_ETM_TRACE_DATA3;}\r
+\r
+\r
+\r
+\r
+\r
+/**\r
+ *\r
+ * @details This is used to enable PLL to speed up booting at startup. Remove it will cause system using\r
+ * default clock source (External crystal or internal 22.1184MHz IRC).\r
+ * Enable this option will cause system booting in 72MHz(By XTAL) or 71.8848MHz(By IRC22M) according to\r
+ * user configuration setting in CONFIG0\r
+ *\r
+ */\r
+\r
+/*\r
+#define INIT_SYSCLK_AT_BOOTING\r
+*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ Define SYSCLK\r
+ *----------------------------------------------------------------------------*/\r
+#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */\r
+#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */\r
+#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */\r
+#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */\r
+#define __HSI (48000000UL) /*!< PLL Output Clock Frequency */\r
+#define __HIRC48 (48000000UL) /*!< Internal 48M RC Oscillator Frequency */\r
+#define __LIRC32 (32000UL) /*!< Internal 32K RC Oscillator Frequency */\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L)\r
+# if defined (__ICCARM__)\r
+# define __NONSECURE_ENTRY __cmse_nonsecure_entry\r
+# define __NONSECURE_ENTRY_WEAK __cmse_nonsecure_entry //__weak\r
+# define __NONSECURE_CALL __cmse_nonsecure_call\r
+# else\r
+# define __NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry))\r
+# define __NONSECURE_ENTRY_WEAK __attribute__((cmse_nonsecure_entry,weak))\r
+# define __NONSECURE_CALL __attribute__((cmse_nonsecure_call))\r
+# endif\r
+#else\r
+# define __NONSECURE_ENTRY\r
+# define __NONSECURE_ENTRY_WEAK\r
+# define __NONSECURE_CALL\r
+#endif\r
+\r
+\r
+\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+extern uint32_t CyclesPerUs; /*!< Cycles per micro second */\r
+extern uint32_t PllClock; /*!< PLL Output Clock Frequency */\r
+extern uint32_t __PC(void); /*!< Return the current program counter value */\r
+\r
+#if USE_ASSERT\r
+/**\r
+ * @brief Assert Function\r
+ *\r
+ * @param[in] expr Expression to be evaluated\r
+ *\r
+ * @return None\r
+ *\r
+ * @details If the expression is false, an error message will be printed out\r
+ * from debug port (UART0 or UART1).\r
+ */\r
+#define ASSERT_PARAM(expr) { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } }\r
+\r
+void AssertError(uint8_t* file, uint32_t line);\r
+#else\r
+#define ASSERT_PARAM(expr)\r
+#endif\r
+\r
+#define assert_param(expr) ASSERT_PARAM(expr)\r
+\r
+\r
+/**\r
+ * @brief System Initialization\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The necessary initialization of system.\r
+ */\r
+extern void SystemInit(void);\r
+\r
+\r
+/**\r
+ * @brief Update the Variable SystemCoreClock\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to update the variable SystemCoreClock\r
+ * and must be called whenever the core clock is changed.\r
+ */\r
+extern void SystemCoreClockUpdate(void);\r
+\r
+\r
+\r
+\r
+#if (defined(__ICCARM__) && (__VER__ >= 7080000) && (__VER__ < 8020000))\r
+uint32_t __TZ_get_PSP_NS(void);\r
+void __TZ_set_PSP_NS(uint32_t topOfProcStack);\r
+int32_t __TZ_get_MSP_NS(void);\r
+void __TZ_set_MSP_NS(uint32_t topOfMainStack);\r
+uint32_t __TZ_get_PRIMASK_NS(void);\r
+void __TZ_set_PRIMASK_NS(uint32_t priMask);\r
+#endif\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SYSTEM_M2351_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file timer_reg.h\r
+ * @version V1.00\r
+ * @brief TIMER register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __TIMER_REG_H__\r
+#define __TIMER_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- Timer Controller -------------------------*/\r
+/**\r
+ @addtogroup TIMER Timer Controller(TIMER)\r
+ Memory Mapped Structure for TIMER Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var TIMER_T::CTL\r
+ * Offset: 0x00 Timer Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |PSC |Prescale Counter\r
+ * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter\r
+ * | | |If this field is 0 (PSC = 0), then there is no scaling.\r
+ * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.\r
+ * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Control\r
+ * | | |Setting this bit will enable the inter-timer trigger capture function.\r
+ * | | |The Timer0/2 will be in event counter mode and counting with external clock source or event\r
+ * | | |Also, Timer1/3 will be in trigger-counting mode of capture function.\r
+ * | | |0 = Inter-Timer Trigger Capture mode Disabled.\r
+ * | | |1 = Inter-Timer Trigger Capture mode Enabled.\r
+ * | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0.\r
+ * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit\r
+ * | | |0 = The behavior selection in periodic mode is Disabled.\r
+ * | | |When user updates CMPDAT while timer is running in periodic mode,\r
+ * | | |CNT will be reset to default value.\r
+ * | | |1 = The behavior selection in periodic mode is Enabled.\r
+ * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list,\r
+ * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually.\r
+ * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately.\r
+ * | | |If updated CMPDAT value < CNT, CNT will be reset to default value.\r
+ * |[21] |TGLPINSEL |Toggle-output Pin Select\r
+ * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin).\r
+ * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin).\r
+ * |[22] |CAPSRC |Capture Pin Source Selection\r
+ * | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin.\r
+ * | | |1 = Capture Function source is from internal ACMP output signal\r
+ * | | |User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source.\r
+ * |[23] |WKEN |Wake-up Function Enable Bit\r
+ * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\r
+ * | | |0 = Wake-up function Disabled if timer interrupt signal generated.\r
+ * | | |1 = Wake-up function Enabled if timer interrupt signal generated.\r
+ * |[24] |EXTCNTEN |Event Counter Mode Enable Bit\r
+ * | | |This bit is for external counting pin function enabled.\r
+ * | | |0 = Event counter mode Disabled.\r
+ * | | |1 = Event counter mode Enabled.\r
+ * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.\r
+ * |[25] |ACTSTS |Timer Active Status Bit (Read Only)\r
+ * | | |This bit indicates the 24-bit up counter status.\r
+ * | | |0 = 24-bit up counter is not active.\r
+ * | | |1 = 24-bit up counter is active.\r
+ * | | |Note: This bit may active when CNT 0 transition to CNT 1.\r
+ * |[28:27] |OPMODE |Timer Counting Mode Select\r
+ * | | |00 = The Timer controller is operated in One-shot mode.\r
+ * | | |01 = The Timer controller is operated in Periodic mode.\r
+ * | | |10 = The Timer controller is operated in Toggle-output mode.\r
+ * | | |11 = The Timer controller is operated in Continuous Counting mode.\r
+ * |[29] |INTEN |Timer Interrupt Enable Bit\r
+ * | | |0 = Timer time-out interrupt Disabled.\r
+ * | | |1 = Timer time-out interrupt Enabled.\r
+ * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.\r
+ * |[30] |CNTEN |Timer Counting Enable Bit\r
+ * | | |0 = Stops/Suspends counting.\r
+ * | | |1 = Starts counting.\r
+ * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.\r
+ * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated.\r
+ * | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.\r
+ * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)\r
+ * | | |0 = ICE debug mode acknowledgment effects TIMER counting.\r
+ * | | |TIMER counter will be held while CPU is held by ICE.\r
+ * | | |1 = ICE debug mode acknowledgment Disabled.\r
+ * | | |TIMER counter will keep going no matter CPU is held by ICE or not.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * @var TIMER_T::CMP\r
+ * Offset: 0x04 Timer Comparator Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[23:0] |CMPDAT |Timer Comparator Value\r
+ * | | |CMPDAT is a 24-bit compared value register\r
+ * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\r
+ * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).\r
+ * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\r
+ * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field\r
+ * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.\r
+ * @var TIMER_T::INTSTS\r
+ * Offset: 0x08 Timer Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |TIF |Timer Interrupt Flag\r
+ * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\r
+ * | | |0 = No effect.\r
+ * | | |1 = CNT value matches the CMPDAT value.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[1] |TWKF |Timer Wake-up Flag\r
+ * | | |This bit indicates the interrupt wake-up flag status of timer.\r
+ * | | |0 = Timer does not cause CPU wake-up.\r
+ * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * @var TIMER_T::CNT\r
+ * Offset: 0x0C Timer Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[23:0] |CNT |Timer Data Register\r
+ * | | |Read operation.\r
+ * | | |Read this register to get CNT value. For example:\r
+ * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value.\r
+ * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value.\r
+ * | | |Write operation.\r
+ * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.\r
+ * |[31] |RSTACT |Timer Data Register Reset Active (Read Only)\r
+ * | | |This bit indicates if the counter reset operation active.\r
+ * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter\r
+ * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress\r
+ * | | |Once the counter reset operation done, timer clear this bit to 0 automatically.\r
+ * | | |0 = Reset operation is done.\r
+ * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress.\r
+ * | | |Note: This bit is read only.\r
+ * @var TIMER_T::CAP\r
+ * Offset: 0x10 Timer Capture Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[23:0] |CAPDAT |Timer Capture Data Register\r
+ * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.\r
+ * @var TIMER_T::EXTCTL\r
+ * Offset: 0x14 Timer External Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CNTPHASE |Timer External Count Phase\r
+ * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3).\r
+ * | | |0 = A falling edge of external counting pin will be counted.\r
+ * | | |1 = A rising edge of external counting pin will be counted.\r
+ * |[3] |CAPEN |Timer External Capture Pin Enable Bit\r
+ * | | |This bit enables the TMx_EXT capture pin input function.\r
+ * | | |0 =TMx_EXT (x= 0~3) pin Disabled.\r
+ * | | |1 =TMx_EXT (x= 0~3) pin Enabled.\r
+ * |[4] |CAPFUNCS |Capture Function Selection\r
+ * | | |0 = External Capture Mode Enabled.\r
+ * | | |1 = External Reset Mode Enabled.\r
+ * | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field.\r
+ * | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately.\r
+ * |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit\r
+ * | | |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled.\r
+ * | | |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled.\r
+ * | | |Note: CAPIEN is used to enable timer external interrupt\r
+ * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.\r
+ * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.\r
+ * |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit\r
+ * | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled.\r
+ * | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled.\r
+ * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.\r
+ * |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit\r
+ * | | |0 = TMx (x= 0~3) pin de-bounce Disabled.\r
+ * | | |1 = TMx (x= 0~3) pin de-bounce Enabled.\r
+ * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.\r
+ * |[8] |ACMPSSEL |ACMP Source Selection to Trigger Capture Function\r
+ * | | |0 = Capture Function source is from internal ACMP0 output signal.\r
+ * | | |1 = Capture Function source is from internal ACMP1 output signal.\r
+ * | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.\r
+ * |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect\r
+ * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\r
+ * | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin.\r
+ * | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin.\r
+ * | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer.\r
+ * | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer..\r
+ * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin.\r
+ * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin.\r
+ * | | |100, 101 = Reserved.\r
+ * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function\r
+ * | | |0 = Event Counter input source is from TMx (x= 0~3) pin.\r
+ * | | |1 = Event Counter input source is from USB internal SOF output signal.\r
+ * @var TIMER_T::EINTSTS\r
+ * Offset: 0x18 Timer External Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CAPIF |Timer External Capture Interrupt Flag\r
+ * | | |This bit indicates the timer external capture interrupt flag status.\r
+ * | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur.\r
+ * | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred.\r
+ * | | |Note1: This bit is cleared by writing 1 to it.\r
+ * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.\r
+ * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status\r
+ * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.\r
+ * @var TIMER_T::TRGCTL\r
+ * Offset: 0x1C Timer Trigger Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |TRGSSEL |Trigger Source Select Bit\r
+ * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.\r
+ * | | |0 = Time-out interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC.\r
+ * | | |1 = Capture interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC.\r
+ * |[1] |TRGEPWM |Trigger PWM Enable Bit\r
+ * | | |If this bit is set to 1, each timer time-out event or capture event can be as PWM counter clock source.\r
+ * | | |0 = Timer interrupt trigger PWM Disabled.\r
+ * | | |1 = Timer interrupt trigger PWM Enabled.\r
+ * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as PWM counter clock source.\r
+ * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as PWM counter clock source.\r
+ * |[2] |TRGEADC |Trigger EADC Enable Bit\r
+ * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.\r
+ * | | |0 = Timer interrupt trigger EADC Disabled.\r
+ * | | |1 = Timer interrupt trigger EADC Enabled.\r
+ * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion.\r
+ * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger ADC conversion.\r
+ * |[3] |TRGDAC |Trigger DAC Enable Bit\r
+ * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.\r
+ * | | |0 = Timer interrupt trigger DAC Disabled.\r
+ * | | |1 = Timer interrupt trigger DAC Enabled.\r
+ * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC.\r
+ * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC.\r
+ * |[4] |TRGPDMA |Trigger PDMA Enable Bit\r
+ * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.\r
+ * | | |0 = Timer interrupt trigger PDMA Disabled.\r
+ * | | |1 = Timer interrupt trigger PDMA Enabled.\r
+ * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer.\r
+ * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer.\r
+ * @var TIMER_T::ALTCTL\r
+ * Offset: 0x20 Timer Alternative Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |FUNCSEL |Function Selection\r
+ * | | |0 = Timer controller is used as timer function.\r
+ * | | |1 = Timer controller is used as PWM function.\r
+ * | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.\r
+ * @var TIMER_T::PWMCTL\r
+ * Offset: 0x40 Timer PWM Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CNTEN |PWM Counter Enable Bit\r
+ * | | |0 = PWM counter and clock prescale Stop Running.\r
+ * | | |1 = PWM counter and clock prescale Start Running.\r
+ * |[2:1] |CNTTYPE |PWM Counter Behavior Type\r
+ * | | |00 = Up count type.\r
+ * | | |01 = Down count type.\r
+ * | | |10 = Up-down count type.\r
+ * | | |11 = Reserved.\r
+ * |[3] |CNTMODE |PWM Counter Mode\r
+ * | | |0 = Auto-reload mode.\r
+ * | | |1 = One-shot mode.\r
+ * |[8] |CTRLD |Center Re-load\r
+ * | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period.\r
+ * |[9] |IMMLDEN |Immediately Load Enable Bit\r
+ * | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled\r
+ * | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period.\r
+ * | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP.\r
+ * | | |Note: If IMMLDEN is enabled, CTRLD will be invalid.\r
+ * |[16] |OUTMODE |PWM Output Mode\r
+ * | | |This bit controls the output mode of corresponding PWM channel.\r
+ * | | |0 = PWM independent mode.\r
+ * | | |1 = PWM complementary mode.\r
+ * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)\r
+ * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode.\r
+ * | | |0 = ICE debug mode counter halt disable.\r
+ * | | |1 = ICE debug mode counter halt enable.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect)\r
+ * | | |0 = ICE debug mode acknowledgment effects PWM output.\r
+ * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged.\r
+ * | | |1 = ICE debug mode acknowledgment disabled.\r
+ * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * @var TIMER_T::PWMCLKSRC\r
+ * Offset: 0x44 Timer PWM Counter Clock Source Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |CLKSRC |PWM Counter Clock Source Select\r
+ * | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\r
+ * | | |000 = TMRx_CLK.\r
+ * | | |001 = Internal TIMER0 time-out or capture event.\r
+ * | | |010 = Internal TIMER1 time-out or capture event.\r
+ * | | |011 = Internal TIMER2 time-out or capture event.\r
+ * | | |100 = Internal TIMER3 time-out or capture event.\r
+ * | | |Others = Reserved.\r
+ * | | |Note: If Timer PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events.\r
+ * @var TIMER_T::PWMCLKPSC\r
+ * Offset: 0x48 Timer PWM Counter Clock Pre-scale Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[11:0] |CLKPSC |PWM Counter Clock Pre-scale\r
+ * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)\r
+ * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source.\r
+ * @var TIMER_T::PWMCNTCLR\r
+ * Offset: 0x4C Timer PWM Clear Counter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CNTCLR |Clear PWM Counter Control Bit\r
+ * | | |It is automatically cleared by hardware.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type.\r
+ * @var TIMER_T::PWMPERIOD\r
+ * Offset: 0x50 Timer PWM Period Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |PERIOD |PWM Period Register\r
+ * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.\r
+ * | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.\r
+ * | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.\r
+ * | | |In up and down count type:\r
+ * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK.\r
+ * | | |In up-down count type:\r
+ * | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK.\r
+ * | | |Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type.\r
+ * @var TIMER_T::PWMCMPDAT\r
+ * Offset: 0x54 Timer PWM Comparator Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |CMP |PWM Comparator Register\r
+ * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert.\r
+ * @var TIMER_T::PWMDTCTL\r
+ * Offset: 0x58 Timer PWM Dead-Time Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[11:0] |DTCNT |Dead-time Counter (Write Protect)\r
+ * | | |The dead-time can be calculated from the following two formulas:\r
+ * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0.\r
+ * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\r
+ * | | |Dead-time insertion function is only active when PWM complementary mode is enabled\r
+ * | | |If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.\r
+ * | | |0 = Dead-time insertion Disabled on the pin pair.\r
+ * | | |1 = Dead-time insertion Enabled on the pin pair.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect)\r
+ * | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale.\r
+ * | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * @var TIMER_T::PWMCNT\r
+ * Offset: 0x5C Timer PWM Counter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |CNT |PWM Counter Value Register (Read Only)\r
+ * | | |User can monitor CNT to know the current counter value in 16-bit period counter.\r
+ * |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only)\r
+ * | | |0 = Counter is active in down count.\r
+ * | | |1 = Counter is active up count.\r
+ * @var TIMER_T::PWMMSKEN\r
+ * Offset: 0x60 Timer PWM Output Mask Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit\r
+ * | | |The PWMx_CH0 output signal will be masked when this bit is enabled\r
+ * | | |The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data.\r
+ * | | |0 = PWMx_CH0 output signal is non-masked.\r
+ * | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data.\r
+ * |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit\r
+ * | | |The PWMx_CH1 output signal will be masked when this bit is enabled\r
+ * | | |The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data.\r
+ * | | |0 = PWMx_CH1 output signal is non-masked.\r
+ * | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data.\r
+ * @var TIMER_T::PWMMSK\r
+ * Offset: 0x64 Timer PWM Output Mask Data Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit\r
+ * | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1).\r
+ * | | |0 = Output logic Low to PWMx_CH0.\r
+ * | | |1 = Output logic High to PWMx_CH0.\r
+ * |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit\r
+ * | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1).\r
+ * | | |0 = Output logic Low to PWMx_CH1.\r
+ * | | |1 = Output logic High to PWMx_CH1.\r
+ * @var TIMER_T::PWMBNF\r
+ * Offset: 0x68 Timer PWM Brake Pin Noise Filter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit\r
+ * | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled.\r
+ * | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled.\r
+ * |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection\r
+ * | | |000 = Noise filter clock is PCLKx.\r
+ * | | |001 = Noise filter clock is PCLKx/2.\r
+ * | | |010 = Noise filter clock is PCLKx/4.\r
+ * | | |011 = Noise filter clock is PCLKx/8.\r
+ * | | |100 = Noise filter clock is PCLKx/16.\r
+ * | | |101 = Noise filter clock is PCLKx/32.\r
+ * | | |110 = Noise filter clock is PCLKx/64.\r
+ * | | |111 = Noise filter clock is PCLKx/128.\r
+ * |[6:4] |BRKFCNT |Brake Pin Noise Filter Count\r
+ * | | |The fields is used to control the active noise filter sample time.\r
+ * | | |Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT.\r
+ * |[7] |BRKPINV |Brake Pin Detection Control Bit\r
+ * | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect.\r
+ * | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect .\r
+ * |[17:16] |BKPINSRC |Brake Pin Source Select\r
+ * | | |00 = Brake pin source comes from PWM0_BRAKE0 pin.\r
+ * | | |01 = Brake pin source comes from PWM0_BRAKE1 pin.\r
+ * | | |10 = Brake pin source comes from PWM1_BRAKE0 pin.\r
+ * | | |11 = Brake pin source comes from PWM1_BRAKE1 pin.\r
+ * @var TIMER_T::PWMFAILBRK\r
+ * Offset: 0x6C Timer PWM System Fail Brake Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit\r
+ * | | |0 = Brake Function triggered by clock fail detection Disabled.\r
+ * | | |1 = Brake Function triggered by clock fail detection Enabled.\r
+ * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit\r
+ * | | |0 = Brake Function triggered by BOD event Disabled.\r
+ * | | |1 = Brake Function triggered by BOD event Enabled.\r
+ * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit\r
+ * | | |0 = Brake Function triggered by SRAM parity error detection Disabled.\r
+ * | | |1 = Brake Function triggered by SRAM parity error detection Enabled.\r
+ * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit\r
+ * | | |0 = Brake Function triggered by core lockup event Disabled.\r
+ * | | |1 = Brake Function triggered by core lockup event Enabled.\r
+ * @var TIMER_T::PWMBRKCTL\r
+ * Offset: 0x70 Timer PWM Brake Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CPO0EBEN |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\r
+ * | | |0 = Internal ACMP0_O signal as edge-detect brake source Disabled.\r
+ * | | |1 = Internal ACMP0_O signal as edge-detect brake source Enabled.\r
+ * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.\r
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[1] |CPO1EBEN |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\r
+ * | | |0 = Internal ACMP1_O signal as edge-detect brake source Disabled.\r
+ * | | |1 = Internal ACMP1_O signal as edge-detect brake source Enabled.\r
+ * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.\r
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\r
+ * | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled.\r
+ * | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect)\r
+ * | | |0 = System fail condition as edge-detect brake source Disabled.\r
+ * | | |1 = System fail condition as edge-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[8] |CPO0LBEN |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\r
+ * | | |0 = Internal ACMP0_O signal as level-detect brake source Disabled.\r
+ * | | |1 = Internal ACMP0_O signal as level-detect brake source Enabled.\r
+ * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.\r
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[9] |CPO1LBEN |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\r
+ * | | |0 = Internal ACMP1_O signal as level-detect brake source Disabled.\r
+ * | | |1 = Internal ACMP1_O signal as level-detect brake source Enabled.\r
+ * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\r
+ * | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled.\r
+ * | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect)\r
+ * | | |0 = System fail condition as level-detect brake source Disabled.\r
+ * | | |1 = System fail condition as level-detect brake source Enabled.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect)\r
+ * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output.\r
+ * | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened.\r
+ * | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened.\r
+ * | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect)\r
+ * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output.\r
+ * | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened.\r
+ * | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened.\r
+ * | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * @var TIMER_T::PWMPOLCTL\r
+ * Offset: 0x74 Timer PWM Pin Output Polar Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit\r
+ * | | |The bit is used to control polarity state of PWMx_CH0 output pin.\r
+ * | | |0 = PWMx_CH0 output pin polar inverse Disabled.\r
+ * | | |1 = PWMx_CH0 output pin polar inverse Enabled.\r
+ * |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit\r
+ * | | |The bit is used to control polarity state of PWMx_CH1 output pin.\r
+ * | | |0 = PWMx_CH1 output pin polar inverse Disabled.\r
+ * | | |1 = PWMx_CH1 output pin polar inverse Enabled.\r
+ * @var TIMER_T::PWMPOEN\r
+ * Offset: 0x78 Timer PWM Pin Output Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit\r
+ * | | |0 = PWMx_CH0 pin at tri-state mode.\r
+ * | | |1 = PWMx_CH0 pin in output mode.\r
+ * |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit\r
+ * | | |0 = PWMx_CH1 pin at tri-state mode.\r
+ * | | |1 = PWMx_CH1 pin in output mode.\r
+ * @var TIMER_T::PWMSWBRK\r
+ * Offset: 0x7C Timer PWM Software Trigger Brake Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\r
+ * | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\r
+ * | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * @var TIMER_T::PWMINTEN0\r
+ * Offset: 0x80 Timer PWM Interrupt Enable Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit\r
+ * | | |0 = Zero point interrupt Disabled.\r
+ * | | |1 = Zero point interrupt Enabled.\r
+ * |[1] |PIEN |PWM Period Point Interrupt Enable Bit\r
+ * | | |0 = Period point interrupt Disabled.\r
+ * | | |1 = Period point interrupt Enabled.\r
+ * | | |Note: When in up-down count type, period point means the center point of current PWM period.\r
+ * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit\r
+ * | | |0 = Compare up count interrupt Disabled.\r
+ * | | |1 = Compare up count interrupt Enabled.\r
+ * |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit\r
+ * | | |0 = Compare down count interrupt Disabled.\r
+ * | | |1 = Compare down count interrupt Enabled.\r
+ * @var TIMER_T::PWMINTEN1\r
+ * Offset: 0x84 Timer PWM Interrupt Enable Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable (Write Protect)\r
+ * | | |0 = PWM edge-detect brake interrupt Disabled.\r
+ * | | |1 = PWM edge-detect brake interrupt Enabled.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable (Write Protect)\r
+ * | | |0 = PWM level-detect brake interrupt Disabled.\r
+ * | | |1 = PWM level-detect brake interrupt Enabled.\r
+ * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * @var TIMER_T::PWMINTSTS0\r
+ * Offset: 0x88 Timer PWM Interrupt Status Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ZIF |PWM Zero Point Interrupt Flag\r
+ * | | |This bit is set by hardware when TIMERx_PWM counter reaches zero.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[1] |PIF |PWM Period Point Interrupt Flag\r
+ * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\r
+ * | | |Note1: When in up-down count type, PIF flag means the center point flag of current PWM period.\r
+ * | | |Note2: This bit is cleared by writing 1 to it.\r
+ * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag\r
+ * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\r
+ * | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type..\r
+ * | | |Note2: This bit is cleared by writing 1 to it.\r
+ * |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag\r
+ * | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\r
+ * | | |Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.\r
+ * | | |Note2: This bit is cleared by writing 1 to it.\r
+ * @var TIMER_T::PWMINTSTS1\r
+ * Offset: 0x8C Timer PWM Interrupt Status Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\r
+ * | | |0 = PWMx_CH0 edge-detect brake event do not happened.\r
+ * | | |1 = PWMx_CH0 edge-detect brake event happened.\r
+ * | | |Note1: This bit is cleared by writing 1 to it.\r
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\r
+ * | | |0 = PWMx_CH1 edge-detect brake event do not happened.\r
+ * | | |1 = PWMx_CH1 edge-detect brake event happened.\r
+ * | | |Note1: This bit is cleared by writing 1 to it.\r
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\r
+ * | | |0 = PWMx_CH0 level-detect brake event do not happened.\r
+ * | | |1 = PWMx_CH0 level-detect brake event happened.\r
+ * | | |Note1: This bit is cleared by writing 1 to it.\r
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\r
+ * | | |0 = PWMx_CH1 level-detect brake event do not happened.\r
+ * | | |1 = PWMx_CH1 level-detect brake event happened.\r
+ * | | |Note1: This bit is cleared by writing 1 to it.\r
+ * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.\r
+ * |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only)\r
+ * | | |0 = PWMx_CH0 edge-detect brake state is released.\r
+ * | | |1 = PWMx_CH0 at edge-detect brake state.\r
+ * | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period.\r
+ * |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only)\r
+ * | | |0 = PWMx_CH1 edge-detect brake state is released.\r
+ * | | |1 = PWMx_CH1 at edge-detect brake state.\r
+ * | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period.\r
+ * |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only)\r
+ * | | |0 = PWMx_CH0 level-detect brake state is released.\r
+ * | | |1 = PWMx_CH0 at level-detect brake state.\r
+ * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.\r
+ * |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only)\r
+ * | | |0 = PWMx_CH1 level-detect brake state is released.\r
+ * | | |1 = PWMx_CH1 at level-detect brake state.\r
+ * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.\r
+ * @var TIMER_T::PWMEADCTS\r
+ * Offset: 0x90 Timer PWM ADC Trigger Source Select Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger EADC Conversion\r
+ * | | |000 = Trigger EADC conversion at zero point (ZIF).\r
+ * | | |001 = Trigger EADC conversion at period point (PIF).\r
+ * | | |010 = Trigger EADC conversion at zero or period point (ZIF or PIF).\r
+ * | | |011 = Trigger EADC conversion at compare up count point (CMPUIF).\r
+ * | | |100 = Trigger EADC conversion at compare down count point (CMPDIF).\r
+ * | | |Others = Reserved.\r
+ * |[7] |TRGEN |PWM Counter Event Trigger EADC Conversion Enable Bit\r
+ * | | |0 = PWM counter event trigger EADC conversion Disabled.\r
+ * | | |1 = PWM counter event trigger EADC conversion Enabled.\r
+ * @var TIMER_T::PWMSCTL\r
+ * Offset: 0x94 Timer PWM Synchronous Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select\r
+ * | | |00 = PWM synchronous function Disabled.\r
+ * | | |01 = PWM synchronous counter start function Enabled.\r
+ * | | |10 = Reserved.\r
+ * | | |11 = PWM synchronous counter clear function Enabled.\r
+ * |[8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select\r
+ * | | |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN.\r
+ * | | |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN.\r
+ * | | |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\r
+ * | | |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1.\r
+ * @var TIMER_T::PWMSTRG\r
+ * Offset: 0x98 Timer PWM Synchronous Trigger Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only)\r
+ * | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.\r
+ * | | |Note: This bit is only available in TIMER0 and TIMER2.\r
+ * @var TIMER_T::PWMSTATUS\r
+ * Offset: 0x9C Timer PWM Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag\r
+ * | | |0 = Indicates the PWM counter value never reached its maximum value 0xFFFF.\r
+ * | | |1 = Indicates the PWM counter value has reached its maximum value.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag\r
+ * | | |0 = PWM counter event trigger EADC start conversion is not occurred.\r
+ * | | |1 = PWM counter event trigger EADC start conversion has occurred.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * @var TIMER_T::PWMPBUF\r
+ * Offset: 0xA0 Timer PWM Period Buffer Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |PBUF |PWM Period Buffer Register (Read Only)\r
+ * | | |Used as PERIOD active register.\r
+ * @var TIMER_T::PWMCMPBUF\r
+ * Offset: 0xA4 Timer PWM Comparator Buffer Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only)\r
+ * | | |Used as CMP active register.\r
+ */\r
+ __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */\r
+ __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */\r
+ __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */\r
+ __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */\r
+ __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */\r
+ __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */\r
+ __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */\r
+ __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */\r
+ __IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */\r
+ __I uint32_t RESERVE0[7];\r
+ __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */\r
+ __IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */\r
+ __IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */\r
+ __IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */\r
+ __IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */\r
+ __IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */\r
+ __IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-Time Control Register */\r
+ __I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */\r
+ __IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */\r
+ __IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */\r
+ __IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */\r
+ __IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */\r
+ __IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */\r
+ __IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */\r
+ __IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */\r
+ __O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */\r
+ __IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */\r
+ __IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */\r
+ __IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */\r
+ __IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */\r
+ __IO uint32_t PWMEADCTS; /*!< [0x0090] Timer PWM ADC Trigger Source Select Register */\r
+ __IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */\r
+ __O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */\r
+ __IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */\r
+ __I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */\r
+ __I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */\r
+\r
+} TIMER_T;\r
+\r
+/**\r
+ @addtogroup TIMER_CONST TIMER Bit Field Definition\r
+ Constant Definitions for TIMER Controller\r
+@{ */\r
+\r
+#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */\r
+#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */\r
+\r
+#define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */\r
+#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */\r
+\r
+#define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */\r
+#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */\r
+\r
+#define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */\r
+#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */\r
+\r
+#define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */\r
+#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */\r
+\r
+#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */\r
+#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */\r
+\r
+#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */\r
+#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */\r
+\r
+#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */\r
+#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */\r
+\r
+#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */\r
+#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */\r
+\r
+#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */\r
+#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */\r
+\r
+#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */\r
+#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */\r
+\r
+#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */\r
+#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */\r
+\r
+#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */\r
+#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */\r
+\r
+#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */\r
+#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */\r
+\r
+#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */\r
+#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */\r
+\r
+#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */\r
+#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */\r
+\r
+#define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */\r
+#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */\r
+\r
+#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */\r
+#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */\r
+\r
+#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */\r
+#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */\r
+\r
+#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */\r
+#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */\r
+\r
+#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */\r
+#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */\r
+\r
+#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */\r
+#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */\r
+\r
+#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */\r
+#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */\r
+\r
+#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */\r
+#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */\r
+\r
+#define TIMER_EXTCTL_ACMPSSEL_Pos (8) /*!< TIMER_T::EXTCTL: ACMPSSEL Position */\r
+#define TIMER_EXTCTL_ACMPSSEL_Msk (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos) /*!< TIMER_T::EXTCTL: ACMPSSEL Mask */\r
+\r
+#define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */\r
+#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */\r
+\r
+#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */\r
+#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */\r
+\r
+#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */\r
+#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */\r
+\r
+#define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */\r
+#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */\r
+\r
+#define TIMER_TRGCTL_TRGEPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGEPWM Position */\r
+#define TIMER_TRGCTL_TRGEPWM_Msk (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos) /*!< TIMER_T::TRGCTL: TRGEPWM Mask */\r
+\r
+#define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */\r
+#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */\r
+\r
+#define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */\r
+#define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */\r
+\r
+#define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */\r
+#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */\r
+\r
+#define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */\r
+#define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */\r
+\r
+#define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */\r
+#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */\r
+\r
+#define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */\r
+#define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */\r
+\r
+#define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */\r
+#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */\r
+\r
+#define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */\r
+#define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */\r
+\r
+#define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */\r
+#define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */\r
+\r
+#define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */\r
+#define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */\r
+\r
+#define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */\r
+#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */\r
+\r
+#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */\r
+#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */\r
+\r
+#define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */\r
+#define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */\r
+\r
+#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */\r
+#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */\r
+\r
+#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */\r
+#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */\r
+\r
+#define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */\r
+#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */\r
+\r
+#define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */\r
+#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */\r
+\r
+#define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */\r
+#define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */\r
+\r
+#define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */\r
+#define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */\r
+\r
+#define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */\r
+#define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */\r
+\r
+#define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */\r
+#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */\r
+\r
+#define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */\r
+#define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */\r
+\r
+#define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */\r
+#define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */\r
+\r
+#define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */\r
+#define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */\r
+\r
+#define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */\r
+#define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */\r
+\r
+#define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */\r
+#define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */\r
+\r
+#define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */\r
+#define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */\r
+\r
+#define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */\r
+#define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */\r
+\r
+#define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */\r
+#define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */\r
+\r
+#define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */\r
+#define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */\r
+\r
+#define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */\r
+#define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */\r
+\r
+#define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */\r
+#define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */\r
+\r
+#define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */\r
+#define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask */\r
+\r
+#define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */\r
+#define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask */\r
+\r
+#define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */\r
+#define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */\r
+\r
+#define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position */\r
+#define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask */\r
+\r
+#define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position */\r
+#define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask */\r
+\r
+#define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */\r
+#define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */\r
+\r
+#define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */\r
+#define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */\r
+\r
+#define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position */\r
+#define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask */\r
+\r
+#define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position */\r
+#define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask */\r
+\r
+#define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */\r
+#define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */\r
+\r
+#define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */\r
+#define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */\r
+\r
+#define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */\r
+#define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */\r
+\r
+#define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */\r
+#define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */\r
+\r
+#define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */\r
+#define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */\r
+\r
+#define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */\r
+#define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */\r
+\r
+#define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */\r
+#define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */\r
+\r
+#define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */\r
+#define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */\r
+\r
+#define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */\r
+#define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */\r
+\r
+#define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */\r
+#define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */\r
+\r
+#define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */\r
+#define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */\r
+\r
+#define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */\r
+#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */\r
+\r
+#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */\r
+#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */\r
+\r
+#define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */\r
+#define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */\r
+\r
+#define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */\r
+#define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */\r
+\r
+#define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */\r
+#define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */\r
+\r
+#define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */\r
+#define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */\r
+\r
+#define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */\r
+#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */\r
+\r
+#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */\r
+#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */\r
+\r
+#define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */\r
+#define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */\r
+\r
+#define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */\r
+#define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */\r
+\r
+#define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */\r
+#define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */\r
+\r
+#define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */\r
+#define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */\r
+\r
+#define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */\r
+#define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */\r
+\r
+#define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */\r
+#define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */\r
+\r
+#define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */\r
+#define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */\r
+\r
+#define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */\r
+#define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */\r
+\r
+#define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */\r
+#define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */\r
+\r
+#define TIMER_PWMEADCTS_TRGSEL_Pos (0) /*!< TIMER_T::PWMEADCTS: TRGSEL Position */\r
+#define TIMER_PWMEADCTS_TRGSEL_Msk (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< TIMER_T::PWMEADCTS: TRGSEL Mask */\r
+\r
+#define TIMER_PWMEADCTS_TRGEN_Pos (7) /*!< TIMER_T::PWMEADCTS: TRGEN Position */\r
+#define TIMER_PWMEADCTS_TRGEN_Msk (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos) /*!< TIMER_T::PWMEADCTS: TRGEN Mask */\r
+\r
+#define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */\r
+#define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */\r
+\r
+#define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */\r
+#define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */\r
+\r
+#define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */\r
+#define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */\r
+\r
+#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */\r
+#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */\r
+\r
+#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */\r
+#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */\r
+\r
+#define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */\r
+#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */\r
+\r
+#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */\r
+#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */\r
+\r
+/**@}*/ /* TIMER_CONST */\r
+/**@}*/ /* end of TIMER register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __TIMER_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file trng_reg.h\r
+ * @version V1.00\r
+ * @brief TRNG register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __TRNG_REG_H__\r
+#define __TRNG_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- True Random Number Generator -------------------------*/\r
+/**\r
+ @addtogroup TRNG True Random Number Generator(TRNG)\r
+ Memory Mapped Structure for TRNG Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var TRNG_T::CTL\r
+ * Offset: 0x00 TRNG Control Register and Status\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |TRNGEN |Random Number Generator Enable Bit\r
+ * | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became 1.\r
+ * | | |0 = TRNG disabled.\r
+ * | | |1 = TRNG enabled.\r
+ * | | |Note: TRNGEN is an enable bit of digital part\r
+ * | | |When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption.\r
+ * |[1] |DVIF |Data Valid (Read Only)\r
+ * | | |0 = Data is not valid. Reading from RNGD returns 0x00000000.\r
+ * | | |1 = Data is valid. A valid random number can be read form RNGD.\r
+ * | | |This bit is cleared to u20180u2019 by read TRNG_DATA.\r
+ * |[5:2] |CLKP |Clock Prescaler\r
+ * | | |The CLKP is the peripheral clock frequency range for the selected value , the CLKP must higher than or equal to the actual peripheral clock frequency (for correct random bit generation)\r
+ * | | |To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP; finally, set TRNGEN bit to 1 to re-enable the TRNG module.\r
+ * | | |0000 = 80 ~ 100 MHz.\r
+ * | | |0001 = 60 ~ 80 MHz.\r
+ * | | |0010 = 50 ~60 MHz.\r
+ * | | |0011 = 40 ~50 MHz.\r
+ * | | |0100 = 30 ~40 MHz.\r
+ * | | |0101 = 25 ~30 MHz.\r
+ * | | |0110 = 20 ~25 MHz.\r
+ * | | |0111 = 15 ~20 MHz.\r
+ * | | |1000 = 12 ~15 MHz.\r
+ * | | |1001 = 9 ~12 MHz.\r
+ * | | |1010 = 7 ~9 MHz.\r
+ * | | |1011 = 6 ~7 MHz.\r
+ * | | |1100 = 5 ~6 MHz.\r
+ * | | |1101 = 4 ~5 MHz.\r
+ * | | |1111 = Reserved.\r
+ * |[6] |DVIEN |Data Valid Interrupt Enable Bit\r
+ * | | |0 = Interrupt disabled..\r
+ * | | |1 = Interrupt enabled.\r
+ * |[7] |READY |Random Number Generator Ready (Read Only)\r
+ * | | |After ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us.\r
+ * | | |0 = RNG is not ready or was not activated.\r
+ * | | |1 = RNG is ready to be enabled..\r
+ * |[31:8] |Reversed |Reversed\r
+ * @var TRNG_T::DATA\r
+ * Offset: 0x04 TRNG Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |DATA |Random Number Generator Data (Read Only)\r
+ * | | |The DATA store the random number generated by TRNG and can be read only once.\r
+ * @var TRNG_T::ACT\r
+ * Offset: 0x0C TRNG Activation Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[6:0] |VER |TRNG Version\r
+ * | | |TRNG version number is dependent on TRNG module.\r
+ * | | |0x02:(Current Version Number)\r
+ * |[7] |ACT |Random Number Generator Activation\r
+ * | | |After enable the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1.\r
+ * | | |0 = TRNG inactive.\r
+ * | | |1 = TRNG active.\r
+ * | | |Note: ACT is an enable bit of analog part\r
+ * | | |When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption.\r
+ */\r
+ __IO uint32_t CTL; /*!< [0x0000] TRNG Control Register and Status */\r
+ __I uint32_t DATA; /*!< [0x0004] TRNG Data Register */\r
+ __I uint32_t RESERVE0[1];\r
+ __IO uint32_t ACT; /*!< [0x000c] TRNG Activation Register */\r
+\r
+} TRNG_T;\r
+\r
+/**\r
+ @addtogroup TRNG_CONST TRNG Bit Field Definition\r
+ Constant Definitions for TRNG Controller\r
+@{ */\r
+\r
+#define TRNG_CTL_TRNGEN_Pos (0) /*!< TRNG_T::CTL: TRNGEN Position */\r
+#define TRNG_CTL_TRNGEN_Msk (0x1ul << TRNG_CTL_TRNGEN_Pos) /*!< TRNG_T::CTL: TRNGEN Mask */\r
+\r
+#define TRNG_CTL_DVIF_Pos (1) /*!< TRNG_T::CTL: DVIF Position */\r
+#define TRNG_CTL_DVIF_Msk (0x1ul << TRNG_CTL_DVIF_Pos) /*!< TRNG_T::CTL: DVIF Mask */\r
+\r
+#define TRNG_CTL_CLKP_Pos (2) /*!< TRNG_T::CTL: CLKP Position */\r
+#define TRNG_CTL_CLKP_Msk (0xful << TRNG_CTL_CLKP_Pos) /*!< TRNG_T::CTL: CLKP Mask */\r
+\r
+#define TRNG_CTL_DVIEN_Pos (6) /*!< TRNG_T::CTL: DVIEN Position */\r
+#define TRNG_CTL_DVIEN_Msk (0x1ul << TRNG_CTL_DVIEN_Pos) /*!< TRNG_T::CTL: DVIEN Mask */\r
+\r
+#define TRNG_CTL_READY_Pos (7) /*!< TRNG_T::CTL: READY Position */\r
+#define TRNG_CTL_READY_Msk (0x1ul << TRNG_CTL_READY_Pos) /*!< TRNG_T::CTL: READY Mask */\r
+\r
+#define TRNG_CTL_Reversed_Pos (8) /*!< TRNG_T::CTL: Reversed Position */\r
+#define TRNG_CTL_Reversed_Msk (0xfffffful << TRNG_CTL_Reversed_Pos) /*!< TRNG_T::CTL: Reversed Mask */\r
+\r
+#define TRNG_DATA_DATA_Pos (0) /*!< TRNG_T::DATA: DATA Position */\r
+#define TRNG_DATA_DATA_Msk (0xfful << TRNG_DATA_DATA_Pos) /*!< TRNG_T::DATA: DATA Mask */\r
+\r
+#define TRNG_ACT_VER_Pos (0) /*!< TRNG_T::ACT: VER Position */\r
+#define TRNG_ACT_VER_Msk (0x7ful << TRNG_ACT_VER_Pos) /*!< TRNG_T::ACT: VER Mask */\r
+\r
+#define TRNG_ACT_ACT_Pos (7) /*!< TRNG_T::ACT: ACT Position */\r
+#define TRNG_ACT_ACT_Msk (0x1ul << TRNG_ACT_ACT_Pos) /*!< TRNG_T::ACT: ACT Mask */\r
+\r
+/**@}*/ /* TRNG_CONST */\r
+/**@}*/ /* end of TRNG register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __TRNG_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file uart_reg.h\r
+ * @version V1.00\r
+ * @brief UART register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __UART_REG_H__\r
+#define __UART_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/\r
+/**\r
+ @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)\r
+ Memory Mapped Structure for UART Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var UART_T::DAT\r
+ * Offset: 0x00 UART Receive/Transmit Buffer Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |DAT |Data Receive/Transmit Buffer\r
+ * | | |Write Operation:\r
+ * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO.\r
+ * | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\r
+ * | | |Read Operation:\r
+ * | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.\r
+ * |[8] |PARITY |Parity Bit Receive/Transmit Buffer\r
+ * | | |Write Operation:\r
+ * | | |By writing to this bit, the parity bit will be stored in transmitter FIFO.\r
+ * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\r
+ * | | |Read Operation:\r
+ * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\r
+ * | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.\r
+ * @var UART_T::INTEN\r
+ * Offset: 0x04 UART Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit\r
+ * | | |0 = Receive data available interrupt Disabled.\r
+ * | | |1 = Receive data available interrupt Enabled.\r
+ * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit\r
+ * | | |0 = Transmit holding register empty interrupt Disabled.\r
+ * | | |1 = Transmit holding register empty interrupt Enabled.\r
+ * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit\r
+ * | | |0 = Receive Line Status interrupt Disabled.\r
+ * | | |1 = Receive Line Status interrupt Enabled.\r
+ * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit\r
+ * | | |0 = Modem status interrupt Disabled.\r
+ * | | |1 = Modem status interrupt Enabled.\r
+ * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit\r
+ * | | |0 = RX time-out interrupt Disabled.\r
+ * | | |1 = RX time-out interrupt Enabled.\r
+ * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit\r
+ * | | |0 = Buffer error interrupt Disabled.\r
+ * | | |1 = Buffer error interrupt Enabled.\r
+ * |[6] |WKIEN |Wake-up Interrupt Enable Bit\r
+ * | | |0 = Wake-up Interrupt Disabled.\r
+ * | | |1 = Wake-up Interrupt Enabled.\r
+ * |[8] |LINIEN |LIN Bus Interrupt Enable Bit\r
+ * | | |0 = LIN bus interrupt Disabled.\r
+ * | | |1 = LIN bus interrupt Enabled.\r
+ * | | |Note: This bit is used for LIN function mode.\r
+ * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit\r
+ * | | |0 = Receive Buffer Time-out counter Disabled.\r
+ * | | |1 = Receive Buffer Time-out counter Enabled.\r
+ * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit\r
+ * | | |0 = nRTS auto-flow control Disabled.\r
+ * | | |1 = nRTS auto-flow control Enabled.\r
+ * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.\r
+ * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit\r
+ * | | |0 = nCTS auto-flow control Disabled.\r
+ * | | |1 = nCTS auto-flow control Enabled.\r
+ * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).\r
+ * |[14] |TXPDMAEN |TX PDMA Enable Bit\r
+ * | | |This bit can enable or disable TX PDMA service.\r
+ * | | |0 = TX PDMA Disabled.\r
+ * | | |1 = TX PDMA Enabled.\r
+ * |[15] |RXPDMAEN |RX PDMA Enable Bit\r
+ * | | |This bit can enable or disable RX PDMA service.\r
+ * | | |0 = RX PDMA Disabled.\r
+ * | | |1 = RX PDMA Enabled.\r
+ * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused.\r
+ * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stop.\r
+ * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing 1 to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.\r
+ * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit\r
+ * | | |0 = Auto-baud rate interrupt Disabled.\r
+ * | | |1 = Auto-baud rate interrupt Enabled.\r
+ * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit\r
+ * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).\r
+ * | | |0 = Transmitter empty interrupt Disabled.\r
+ * | | |1 = Transmitter empty interrupt Enabled.\r
+ * @var UART_T::FIFO\r
+ * Offset: 0x08 UART FIFO Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |RXRST |RX Field Software Reset\r
+ * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the RX internal state machine and pointers.\r
+ * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.\r
+ * | | |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.\r
+ * |[2] |TXRST |TX Field Software Reset\r
+ * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the TX internal state machine and pointers.\r
+ * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.\r
+ * | | |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.\r
+ * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level\r
+ * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).\r
+ * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte.\r
+ * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes.\r
+ * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes.\r
+ * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes.\r
+ * | | |Others = Reserved.\r
+ * |[8] |RXOFF |Receiver Disable Bit\r
+ * | | |The receiver is disabled or not (set 1 to disable receiver).\r
+ * | | |0 = Receiver Enabled.\r
+ * | | |1 = Receiver Disabled.\r
+ * | | |Note: This bit is used for RS-485 Normal Multi-drop mode.\r
+ * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.\r
+ * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control Use\r
+ * | | |0000 = nRTS Trigger Level is 1 byte.\r
+ * | | |0001 = nRTS Trigger Level is 4 bytes.\r
+ * | | |0010 = nRTS Trigger Level is 8 bytes.\r
+ * | | |0011 = nRTS Trigger Level is 14 bytes.\r
+ * | | |Others = Reserved.\r
+ * | | |Note: This field is used for auto nRTS flow control.\r
+ * @var UART_T::LINE\r
+ * Offset: 0x0C UART Line Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |WLS |Word Length Selection\r
+ * | | |This field sets UART word length.\r
+ * | | |00 = 5 bits.\r
+ * | | |01 = 6 bits.\r
+ * | | |10 = 7 bits.\r
+ * | | |11 = 8 bits.\r
+ * |[2] |NSB |Number of STOP Bit\r
+ * | | |0 = One STOP bit is generated in the transmitted data.\r
+ * | | |1 = When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data.\r
+ * | | |When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data.\r
+ * |[3] |PBE |Parity Bit Enable Bit\r
+ * | | |0 = Parity bit generated Disabled.\r
+ * | | |1 = Parity bit generated Enabled.\r
+ * | | |Note: Parity bit is generated on each outgoing character and is checked on each incoming data.\r
+ * |[4] |EPE |Even Parity Enable Bit\r
+ * | | |0 = Odd number of logic 1's is transmitted and checked in each word.\r
+ * | | |1 = Even number of logic 1's is transmitted and checked in each word.\r
+ * | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set.\r
+ * |[5] |SPE |Stick Parity Enable Bit\r
+ * | | |0 = Stick parity Disabled.\r
+ * | | |1 = Stick parity Enabled.\r
+ * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0.\r
+ * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.\r
+ * |[6] |BCB |Break Control Bit\r
+ * | | |0 = Break Control Disabled.\r
+ * | | |1 = Break Control Enabled.\r
+ * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0)\r
+ * | | |This bit acts only on TX line and has no effect on the transmitter logic.\r
+ * |[7] |PSS |Parity Bit Source Selection\r
+ * | | |The parity bit can be selected to be generated and checked automatically or by software.\r
+ * | | |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically.\r
+ * | | |1 = Parity bit generated and checked by software.\r
+ * | | |Note1: This bit has effect only when PBE (UART_LINE[3]) is set.\r
+ * | | |Note2: If PSS is 0, the parity bit is transmitted and checked automatically.\r
+ * | | |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).\r
+ * |[8] |TXDINV |TX Data Inverted\r
+ * | | |0 = Transmitted data signal inverted Disabled.\r
+ * | | |1 = Transmitted data signal inverted Enabled.\r
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.\r
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\r
+ * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.\r
+ * |[9] |RXDINV |RX Data Inverted\r
+ * | | |0 = Received data signal inverted Disabled.\r
+ * | | |1 = Received data signal inverted Enabled.\r
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.\r
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\r
+ * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.\r
+ * @var UART_T::MODEM\r
+ * Offset: 0x10 UART Modem Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |RTS |nRTS (Request-to-send) Signal Control\r
+ * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\r
+ * | | |0 = nRTS signal is active.\r
+ * | | |1 = nRTS signal is inactive.\r
+ * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\r
+ * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.\r
+ * |[9] |RTSACTLV |nRTS Pin Active Level\r
+ * | | |This bit defines the active level state of nRTS pin output.\r
+ * | | |0 = nRTS pin output is high level active.\r
+ * | | |1 = nRTS pin output is low level active. (Default)\r
+ * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.\r
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\r
+ * |[13] |RTSSTS |nRTS Pin Status (Read Only)\r
+ * | | |This bit mirror from nRTS pin output of voltage logic status.\r
+ * | | |0 = nRTS pin output is low level voltage logic state.\r
+ * | | |1 = nRTS pin output is high level voltage logic state.\r
+ * @var UART_T::MODEMSTS\r
+ * Offset: 0x14 UART Modem Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CTSDETF |Detect nCTS State Change Flag\r
+ * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\r
+ * | | |0 = nCTS input has not change state.\r
+ * | | |1 = nCTS input has change state.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[4] |CTSSTS |nCTS Pin Status (Read Only)\r
+ * | | |This bit mirror from nCTS pin input of voltage logic status.\r
+ * | | |0 = nCTS pin input is low level voltage logic state.\r
+ * | | |1 = nCTS pin input is high level voltage logic state.\r
+ * | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.\r
+ * |[8] |CTSACTLV |nCTS Pin Active Level\r
+ * | | |This bit defines the active level state of nCTS pin input.\r
+ * | | |0 = nCTS pin input is high level active.\r
+ * | | |1 = nCTS pin input is low level active. (Default)\r
+ * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.\r
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\r
+ * @var UART_T::FIFOSTS\r
+ * Offset: 0x18 UART FIFO Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RXOVIF |RX Overflow Error Interrupt Flag\r
+ * | | |This bit is set when RX FIFO overflow.\r
+ * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\r
+ * | | |0 = RX FIFO is not overflow.\r
+ * | | |1 = RX FIFO is overflow.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag\r
+ * | | |This bit is set to logic 1 when auto-baud rate detect function is finished.\r
+ * | | |0 = Auto-baud rate detect function is not finished.\r
+ * | | |1 = Auto-baud rate detect function is finished.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag\r
+ * | | |This bit is set to logic 1 in Auto-baud Rate Detect mode when the baud rate counter is overflow.\r
+ * | | |0 = Auto-baud rate counter is underflow.\r
+ * | | |1 = Auto-baud rate counter is overflow.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag\r
+ * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0').\r
+ * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1').\r
+ * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\r
+ * | | |Note2: This bit can be cleared by writing 1 to it.\r
+ * |[4] |PEF |Parity Error Flag\r
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit.\r
+ * | | |0 = No parity error is generated.\r
+ * | | |1 = Parity error is generated.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[5] |FEF |Framing Error Flag\r
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\r
+ * | | |0 = No framing error is generated.\r
+ * | | |1 = Framing error is generated.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[6] |BIF |Break Interrupt Flag\r
+ * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).\r
+ * | | |0 = No Break interrupt is generated.\r
+ * | | |1 = Break interrupt is generated.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[13:8] |RXPTR |RX FIFO Pointer (Read Only)\r
+ * | | |This field indicates the RX FIFO Buffer Pointer.\r
+ * | | |When UART receives one byte from external device, RXPTR increases one.\r
+ * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one.\r
+ * | | |The Maximum value shown in RXPTR is 15\r
+ * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0.\r
+ * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.\r
+ * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only)\r
+ * | | |This bit initiate RX FIFO empty or not.\r
+ * | | |0 = RX FIFO is not empty.\r
+ * | | |1 = RX FIFO is empty.\r
+ * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.\r
+ * | | |It will be cleared when UART receives any new data.\r
+ * |[15] |RXFULL |Receiver FIFO Full (Read Only)\r
+ * | | |This bit initiates RX FIFO full or not.\r
+ * | | |0 = RX FIFO is not full.\r
+ * | | |1 = RX FIFO is full.\r
+ * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.\r
+ * |[21:16] |TXPTR |TX FIFO Pointer (Read Only)\r
+ * | | |This field indicates the TX FIFO Buffer Pointer.\r
+ * | | |When CPU writes one byte into UART_DAT, TXPTR increases one.\r
+ * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\r
+ * | | |The Maximum value shown in TXPTR is 15.\r
+ * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0.\r
+ * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.\r
+ * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only)\r
+ * | | |This bit indicates TX FIFO empty or not.\r
+ * | | |0 = TX FIFO is not empty.\r
+ * | | |1 = TX FIFO is empty.\r
+ * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.\r
+ * | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty).\r
+ * |[23] |TXFULL |Transmitter FIFO Full (Read Only)\r
+ * | | |This bit indicates TX FIFO full or not.\r
+ * | | |0 = TX FIFO is not full.\r
+ * | | |1 = TX FIFO is full.\r
+ * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.\r
+ * |[24] |TXOVIF |TX Overflow Error Interrupt Flag\r
+ * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\r
+ * | | |0 = TX FIFO is not overflow.\r
+ * | | |1 = TX FIFO is overflow.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only)\r
+ * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\r
+ * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted.\r
+ * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted.\r
+ * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.\r
+ * |[29] |RXIDLE |RX Idle Status (Read Only)\r
+ * | | |This bit is set by hardware when RX is idle.\r
+ * | | |0 = RX is busy.\r
+ * | | |1 = RX is idle. (Default)\r
+ * |[31] |TXRXACT |TX and RX Active Status (Read Only)\r
+ * | | |This bit indicates TX and RX are active or inactive.\r
+ * | | |0 = TX and RX are inactive.\r
+ * | | |1 = TX and RX are active. (Default)\r
+ * | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared.\r
+ * | | |The UART controller can not transmit or receive data at this moment.\r
+ * | | |Otherwise this bit is set.\r
+ * @var UART_T::INTSTS\r
+ * Offset: 0x1C UART Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RDAIF |Receive Data Available Interrupt Flag\r
+ * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set.\r
+ * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\r
+ * | | |0 = No RDA interrupt flag is generated.\r
+ * | | |1 = RDA interrupt flag is generated.\r
+ * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).\r
+ * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag\r
+ * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.\r
+ * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\r
+ * | | |0 = No THRE interrupt flag is generated.\r
+ * | | |1 = THRE interrupt flag is generated.\r
+ * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).\r
+ * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only)\r
+ * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set).\r
+ * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\r
+ * | | |0 = No RLS interrupt flag is generated.\r
+ * | | |1 = RLS interrupt flag is generated.\r
+ * | | |Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = 1) bit.\r
+ * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.\r
+ * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\r
+ * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.\r
+ * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only)\r
+ * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1).\r
+ * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.\r
+ * | | |0 = No Modem interrupt flag is generated.\r
+ * | | |1 = Modem interrupt flag is generated.\r
+ * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).\r
+ * |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only)\r
+ * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]).\r
+ * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\r
+ * | | |0 = No RX time-out interrupt flag is generated.\r
+ * | | |1 = RX time-out interrupt flag is generated.\r
+ * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.\r
+ * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only)\r
+ * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set).\r
+ * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct.\r
+ * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\r
+ * | | |0 = No buffer error interrupt flag is generated.\r
+ * | | |1 = Buffer error interrupt flag is generated.\r
+ * | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).\r
+ * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only)\r
+ * | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\r
+ * | | |0 = No UART wake-up interrupt flag is generated.\r
+ * | | |1 = UART wake-up interrupt flag is generated.\r
+ * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.\r
+ * |[7] |LINIF |LIN Bus Interrupt Flag\r
+ * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0]=1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1]))\r
+ * | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.\r
+ * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.\r
+ * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.\r
+ * | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing 1 to LINIF(UART_INTSTS[7]).\r
+ * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.\r
+ * | | |0 = No RDA interrupt is generated.\r
+ * | | |1 = RDA interrupt is generated.\r
+ * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.\r
+ * | | |0 = No THRE interrupt is generated.\r
+ * | | |1 = THRE interrupt is generated.\r
+ * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.\r
+ * | | |0 = No RLS interrupt is generated.\r
+ * | | |1 = RLS interrupt is generated.\r
+ * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1\r
+ * | | |0 = No Modem interrupt is generated.\r
+ * | | |1 = Modem interrupt is generated..\r
+ * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.\r
+ * | | |0 = No RX time-out interrupt is generated.\r
+ * | | |1 = RX time-out interrupt is generated.\r
+ * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.\r
+ * | | |0 = No buffer error interrupt is generated.\r
+ * | | |1 = Buffer error interrupt is generated.\r
+ * |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.\r
+ * | | |0 = No UART wake-up interrupt is generated.\r
+ * | | |1 = UART wake-up interrupt is generated.\r
+ * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1.\r
+ * | | |0 = No LIN Bus interrupt is generated.\r
+ * | | |1 = The LIN Bus interrupt is generated.\r
+ * |[18] |HWRLSIF |PDMA Mode Receive Line Status Flag (Read Only)\r
+ * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set).\r
+ * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\r
+ * | | |0 = No RLS interrupt flag is generated in PDMA mode.\r
+ * | | |1 = RLS interrupt flag is generated in PDMA mode.\r
+ * | | |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = 1) bit.\r
+ * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\r
+ * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.\r
+ * |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only)\r
+ * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]=1)).\r
+ * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.\r
+ * | | |0 = No Modem interrupt flag is generated in PDMA mode.\r
+ * | | |1 = Modem interrupt flag is generated in PDMA mode.\r
+ * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).\r
+ * |[20] |HWTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only)\r
+ * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]).\r
+ * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\r
+ * | | |0 = No RX time-out interrupt flag is generated in PDMA mode.\r
+ * | | |1 = RX time-out interrupt flag is generated in PDMA mode.\r
+ * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.\r
+ * |[21] |HWBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only)\r
+ * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set).\r
+ * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct.\r
+ * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\r
+ * | | |0 = No buffer error interrupt flag is generated in PDMA mode.\r
+ * | | |1 = Buffer error interrupt flag is generated in PDMA mode.\r
+ * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.\r
+ * |[22] |TXENDIF |Transmitter Empty Interrupt Flag\r
+ * | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set).\r
+ * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\r
+ * | | |0 = No transmitter empty interrupt flag is generated.\r
+ * | | |1 = Transmitter empty interrupt flag is generated.\r
+ * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.\r
+ * |[26] |HWRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.\r
+ * | | |0 = No RLS interrupt is generated in PDMA mode.\r
+ * | | |1 = RLS interrupt is generated in PDMA mode.\r
+ * |[27] |HWMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.\r
+ * | | |0 = No Modem interrupt is generated in PDMA mode.\r
+ * | | |1 = Modem interrupt is generated in PDMA mode.\r
+ * |[28] |HWTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.\r
+ * | | |0 = No RX time-out interrupt is generated in PDMA mode.\r
+ * | | |1 = RX time-out interrupt is generated in PDMA mode.\r
+ * |[29] |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.\r
+ * | | |0 = No buffer error interrupt is generated in PDMA mode.\r
+ * | | |1 = Buffer error interrupt is generated in PDMA mode.\r
+ * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.\r
+ * | | |0 = No Transmitter Empty interrupt is generated.\r
+ * | | |1 = Transmitter Empty interrupt is generated.\r
+ * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only)\r
+ * | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.\r
+ * | | |0 = No Auto-baud Rate interrupt is generated.\r
+ * | | |1 = The Auto-baud Rate interrupt is generated.\r
+ * @var UART_T::TOUT\r
+ * Offset: 0x20 UART Time-out Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |TOIC |Time-out Interrupt Comparator\r
+ * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11]).\r
+ * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled.\r
+ * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4]).\r
+ * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.\r
+ * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.\r
+ * |[15:8] |DLY |TX Delay Time Value\r
+ * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit.\r
+ * | | |The unit is bit time.\r
+ * @var UART_T::BAUD\r
+ * Offset: 0x24 UART Baud Rate Divider Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |BRD |Baud Rate Divider\r
+ * | | |The field indicates the baud rate divider.\r
+ * | | |This filed is used in baud rate calculation.\r
+ * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1\r
+ * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2.\r
+ * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0\r
+ * | | |This bit is baud rate mode selection bit 0\r
+ * | | |UART provides three baud rate calculation modes.\r
+ * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode.\r
+ * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1\r
+ * | | |This bit is baud rate mode selection bit 1.\r
+ * | | |UART provides three baud rate calculation modes.\r
+ * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode.\r
+ * | | |Note: In IrDA mode must be operated in mode 0.\r
+ * @var UART_T::IRDA\r
+ * Offset: 0x28 UART IrDA Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit\r
+ * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)\r
+ * | | |1 = IrDA Transmitter Enabled and Receiver Disabled.\r
+ * |[5] |TXINV |IrDA Inverse Transmitting Output Signal\r
+ * | | |0 = None inverse transmitting signal. (Default).\r
+ * | | |1 = Inverse transmitting output signal.\r
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.\r
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\r
+ * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.\r
+ * |[6] |RXINV |IrDA Inverse Receive Input Signal\r
+ * | | |0 = None inverse receiving input signal.\r
+ * | | |1 = Inverse receiving input signal. (Default)\r
+ * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.\r
+ * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\r
+ * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.\r
+ * @var UART_T::ALTCTL\r
+ * Offset: 0x2C UART Alternate Control/Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |BRKFL |UART LIN Break Field Length\r
+ * | | |This field indicates a 4-bit LIN TX break field count.\r
+ * | | |Note1: This break field length is BRKFL + 1.\r
+ * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).\r
+ * |[6] |LINRXEN |LIN RX Enable Bit\r
+ * | | |0 = LIN RX mode Disabled.\r
+ * | | |1 = LIN RX mode Enabled.\r
+ * |[7] |LINTXEN |LIN TX Break Mode Enable Bit\r
+ * | | |0 = LIN TX Break mode Disabled.\r
+ * | | |1 = LIN TX Break mode Enabled.\r
+ * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically.\r
+ * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode (NMM)\r
+ * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.\r
+ * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.\r
+ * | | |Note: It cannot be active with RS-485_AAD operation mode.\r
+ * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD)\r
+ * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.\r
+ * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.\r
+ * | | |Note: It cannot be active with RS-485_NMM operation mode.\r
+ * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD)\r
+ * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled.\r
+ * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled.\r
+ * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.\r
+ * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit\r
+ * | | |This bit is used to enable RS-485 Address Detection mode.\r
+ * | | |0 = Address detection mode Disabled.\r
+ * | | |1 = Address detection mode Enabled.\r
+ * | | |Note: This bit is used for RS-485 any operation mode.\r
+ * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only)\r
+ * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.\r
+ * | | |0 = No auto-baud rate interrupt flag is generated.\r
+ * | | |1 = Auto-baud rate interrupt flag is generated.\r
+ * | | |Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).\r
+ * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit\r
+ * | | |0 = Auto-baud rate detect function Disabled.\r
+ * | | |1 = Auto-baud rate detect function Enabled.\r
+ * | | |Note : This bit is cleared automatically after auto-baud detection is finished.\r
+ * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length\r
+ * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.\r
+ * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.\r
+ * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.\r
+ * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.\r
+ * | | |Note : The calculation of bit number includes the START bit.\r
+ * |[31:24] |ADDRMV |Address Match Value\r
+ * | | |This field contains the RS-485 address match values.\r
+ * | | |Note: This field is used for RS-485 auto address detection mode.\r
+ * @var UART_T::FUNCSEL\r
+ * Offset: 0x30 UART Function Select Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |FUNCSEL |Function Select\r
+ * | | |00 = UART function.\r
+ * | | |01 = LIN function.\r
+ * | | |10 = IrDA function.\r
+ * | | |11 = RS-485 function.\r
+ * |[3] |TXRXDIS |TX and RX Disable Bit\r
+ * | | |Setting this bit can disable TX and RX.\r
+ * | | |0 = TX and RX Enabled.\r
+ * | | |1 = TX and RX Disabled.\r
+ * | | |Note: The TX and RX will not disable immediately when this bit is set.\r
+ * | | |The TX and RX complete current task before disable TX and RX.\r
+ * | | |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.\r
+ * @var UART_T::LINCTL\r
+ * Offset: 0x34 UART LIN Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SLVEN |LIN Slave Mode Enable Bit\r
+ * | | |0 = LIN slave mode Disabled.\r
+ * | | |1 = LIN slave mode Enabled.\r
+ * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit\r
+ * | | |0 = LIN slave header detection Disabled.\r
+ * | | |1 = LIN slave header detection Enabled.\r
+ * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).\r
+ * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted.\r
+ * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.\r
+ * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit\r
+ * | | |0 = LIN automatic resynchronization Disabled.\r
+ * | | |1 = LIN automatic resynchronization Enabled.\r
+ * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).\r
+ * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\r
+ * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit\r
+ * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time).\r
+ * | | |1 = UART_BAUD is updated at the next received character\r
+ * | | |User must set the bit before checksum reception.\r
+ * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).\r
+ * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared)\r
+ * |[4] |MUTE |LIN Mute Mode Enable Bit\r
+ * | | |0 = LIN mute mode Disabled.\r
+ * | | |1 = LIN mute mode Enabled.\r
+ * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.16.5.10 (LIN slave mode).\r
+ * |[8] |SENDH |LIN TX Send Header Enable Bit\r
+ * | | |The LIN TX header can be break field or break and sync field or break, sync and frame ID field, it is depend on setting HSEL (UART_LINCTL[23:22]).\r
+ * | | |0 = Send LIN TX header Disabled.\r
+ * | | |1 = Send LIN TX header Enabled.\r
+ * | | |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).\r
+ * | | |Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.\r
+ * |[9] |IDPEN |LIN ID Parity Enable Bit\r
+ * | | |0 = LIN frame ID parity Disabled.\r
+ * | | |1 = LIN frame ID parity Enabled.\r
+ * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked.\r
+ * | | |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10.\r
+ * |[10] |BRKDETEN |LIN Break Detection Enable Bit\r
+ * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field.\r
+ * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated.\r
+ * | | |0 = LIN break detection Disabled .\r
+ * | | |1 = LIN break detection Enabled.\r
+ * |[11] |LINRXOFF |LIN Receiver Disable Bit\r
+ * | | |If the receiver is enabled (RXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (RXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore.\r
+ * | | |0 = LIN receiver Enabled.\r
+ * | | |1 = LIN receiver Disabled.\r
+ * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01).\r
+ * |[12] |BITERREN |Bit Error Detect Enable Bit\r
+ * | | |0 = Bit error detection function Disabled.\r
+ * | | |1 = Bit error detection function Enabled.\r
+ * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted.\r
+ * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.\r
+ * |[19:16] |BRKFL |LIN Break Field Length\r
+ * | | |This field indicates a 4-bit LIN TX break field count.\r
+ * | | |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\r
+ * | | |Note2: This break field length is BRKFL + 1.\r
+ * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13).\r
+ * |[21:20] |BSL |LIN Break/Sync Delimiter Length\r
+ * | | |00 = The LIN break/sync delimiter length is 1-bit time.\r
+ * | | |01 = The LIN break/sync delimiter length is 2-bit time.\r
+ * | | |10 = The LIN break/sync delimiter length is 3-bit time.\r
+ * | | |11 = The LIN break/sync delimiter length is 4-bit time.\r
+ * | | |Note: This bit used for LIN master to sending header field.\r
+ * |[23:22] |HSEL |LIN Header Select\r
+ * | | |00 = The LIN header includes break field.\r
+ * | | |01 = The LIN header includes break field and sync field.\r
+ * | | |10 = The LIN header includes break field, sync field and frame ID field.\r
+ * | | |11 = Reserved.\r
+ * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1).\r
+ * |[31:24] |PID |LIN PID Bits\r
+ * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.\r
+ * | | |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.\r
+ * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\r
+ * | | |Note2: This field can be used for LIN master mode or slave mode.\r
+ * @var UART_T::LINSTS\r
+ * Offset: 0x38 UART LIN Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SLVHDETF |LIN Slave Header Detection Flag\r
+ * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\r
+ * | | |0 = LIN header not detected.\r
+ * | | |1 = LIN header detected (break + sync + frame ID).\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).\r
+ * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header (break + sync + frame ID), the SLVHDETF will be set whether the frame ID correct or not.\r
+ * |[1] |SLVHEF |LIN Slave Header Error Flag\r
+ * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it\r
+ * | | |The header errors include break delimiter is too short (less than 0.5 bit time), frame error in sync field or Identifier field, sync field data is not 0x55 in Non-Automatic Resynchronization mode, sync field deviation error with Automatic Resynchronization mode, sync field measure time-out with Automatic Resynchronization mode and LIN header reception time-out.\r
+ * | | |0 = LIN header error not detected.\r
+ * | | |1 = LIN header error detected.\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).\r
+ * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag\r
+ * | | |This bit is set by hardware when receipted frame ID parity is not correct.\r
+ * | | |0 = No active.\r
+ * | | |1 = Receipted frame ID parity is not correct.\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).\r
+ * |[3] |SLVSYNCF |LIN Slave Sync Field\r
+ * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode.\r
+ * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\r
+ * | | |0 = The current character is not at LIN sync state.\r
+ * | | |1 = The current character is at LIN sync state.\r
+ * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1).\r
+ * | | |Note2: This bit can be cleared by writing 1 to it.\r
+ * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.\r
+ * |[8] |BRKDETF |LIN Break Detection Flag\r
+ * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\r
+ * | | |0 = LIN break not detected.\r
+ * | | |1 = LIN break detected.\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) = 1).\r
+ * |[9] |BITEF |Bit Error Detect Status Flag\r
+ * | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set.\r
+ * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.\r
+ * | | |0 = Bit error not detected.\r
+ * | | |1 = Bit error detected.\r
+ * | | |Note1: This bit can be cleared by writing 1 to it.\r
+ * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1).\r
+ * @var UART_T::BRCOMP\r
+ * Offset: 0x3C UART Baud Rate Compensation Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[8:0] |BRCOMP |Baud Rate Compensation Patten\r
+ * | | |These 9-bits are used to define the relative bit is compensated or not.\r
+ * | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOMP[8] is used to define the parity bit.\r
+ * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease\r
+ * | | |0 = Positive (increase one module clock) compensation for each compensated bit.\r
+ * | | |1 = Negative (decrease one module clock) compensation for each compensated bit.\r
+ * @var UART_T::WKCTL\r
+ * Offset: 0x40 UART Wake-up Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKCTSEN |nCTS Wake-up Enable Bit\r
+ * | | |0 = nCTS Wake-up system function Disabled.\r
+ * | | |1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external.\r
+ * | | |nCTS change will wake-up system from Power-down mode.\r
+ * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit\r
+ * | | |0 = Incoming data wake-up system function Disabled.\r
+ * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,.\r
+ * | | |incoming data will wake-up system from Power-down mode.\r
+ * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit\r
+ * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled.\r
+ * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is.\r
+ * | | |in Power-down mode, Received Data FIFO reached threshold will wake-up system from\r
+ * | | |Power-down mode.\r
+ * |[3] |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit\r
+ * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled.\r
+ * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.\r
+ * | | |Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.\r
+ * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\r
+ * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled.\r
+ * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up system from Power-down mode.\r
+ * | | |Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.\r
+ * @var UART_T::WKSTS\r
+ * Offset: 0x44 UART Wake-up Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CTSWKF |nCTS Wake-up Flag\r
+ * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up.\r
+ * | | |0 = Chip stays in power-down state.\r
+ * | | |1 = Chip wake-up from power-down state by nCTS wake-up.\r
+ * | | |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to 1.\r
+ * | | |Note2: This bit can be cleared by writing 1 to it.\r
+ * |[1] |DATWKF |Incoming Data Wake-up Flag\r
+ * | | |This bit is set if chip wake-up from power-down state by data wake-up.\r
+ * | | |0 = Chip stays in power-down state.\r
+ * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up.\r
+ * | | |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to 1.\r
+ * | | |Note2: This bit can be cleared by writing 1 to it.\r
+ * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag\r
+ * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\r
+ * | | |0 = Chip stays in power-down state.\r
+ * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up.\r
+ * | | |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to 1.\r
+ * | | |Note2: This bit can be cleared by writing 1 to it.\r
+ * |[3] |RS485WKF |RS-485 Address Match (AAD Mode) Wake-up Flag\r
+ * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\r
+ * | | |0 = Chip stays in power-down state.\r
+ * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up.\r
+ * | | |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to 1.\r
+ * | | |Note2: This bit can be cleared by writing 1 to it.\r
+ * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag\r
+ * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\r
+ * | | |0 = Chip stays in power-down state.\r
+ * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out wake-up.\r
+ * | | |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to 1.\r
+ * | | |Note2: This bit can be cleared by writing 1 to it.\r
+ * @var UART_T::DWKCOMP\r
+ * Offset: 0x48 UART Incoming Data Wake-up Compensation Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |STCOMP |Start Bit Compensation Value\r
+ * | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.\r
+ * | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.\r
+ */\r
+\r
+\r
+ __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */\r
+ __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */\r
+ __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */\r
+ __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */\r
+ __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */\r
+ __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */\r
+ __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */\r
+ __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */\r
+ __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */\r
+ __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */\r
+ __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */\r
+ __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */\r
+ __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */\r
+ __IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */\r
+ __IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */\r
+ __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */\r
+ __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */\r
+ __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */\r
+ __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */\r
+\r
+\r
+} UART_T;\r
+\r
+/**\r
+ @addtogroup UART_CONST UART Bit Field Definition\r
+ Constant Definitions for UART Controller\r
+@{ */\r
+\r
+#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */\r
+#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */\r
+\r
+#define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */\r
+#define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */\r
+\r
+#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */\r
+#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */\r
+\r
+#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */\r
+#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */\r
+\r
+#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */\r
+#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */\r
+\r
+#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */\r
+#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */\r
+\r
+#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */\r
+#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */\r
+\r
+#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */\r
+#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */\r
+\r
+#define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */\r
+#define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */\r
+\r
+#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */\r
+#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */\r
+\r
+#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */\r
+#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */\r
+\r
+#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */\r
+#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */\r
+\r
+#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */\r
+#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */\r
+\r
+#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */\r
+#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */\r
+\r
+#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */\r
+#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */\r
+\r
+#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */\r
+#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */\r
+\r
+#define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */\r
+#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */\r
+\r
+#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */\r
+#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */\r
+\r
+#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */\r
+#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */\r
+\r
+#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */\r
+#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */\r
+\r
+#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */\r
+#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */\r
+\r
+#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */\r
+#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */\r
+\r
+#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */\r
+#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */\r
+\r
+#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */\r
+#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */\r
+\r
+#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */\r
+#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */\r
+\r
+#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */\r
+#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */\r
+\r
+#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */\r
+#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */\r
+\r
+#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */\r
+#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */\r
+\r
+#define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */\r
+#define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */\r
+\r
+#define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */\r
+#define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */\r
+\r
+#define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */\r
+#define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */\r
+\r
+#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */\r
+#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */\r
+\r
+#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */\r
+#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */\r
+\r
+#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */\r
+#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */\r
+\r
+#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */\r
+#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */\r
+\r
+#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */\r
+#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */\r
+\r
+#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */\r
+#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */\r
+\r
+#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */\r
+#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */\r
+\r
+#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */\r
+#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */\r
+\r
+#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */\r
+#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */\r
+\r
+#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */\r
+#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */\r
+\r
+#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */\r
+#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */\r
+\r
+#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */\r
+#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */\r
+\r
+#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */\r
+#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */\r
+\r
+#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */\r
+#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */\r
+\r
+#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */\r
+#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */\r
+\r
+#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */\r
+#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */\r
+\r
+#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */\r
+#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */\r
+\r
+#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */\r
+#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */\r
+\r
+#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */\r
+#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */\r
+\r
+#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */\r
+#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */\r
+\r
+#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */\r
+#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */\r
+\r
+#define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */\r
+#define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */\r
+\r
+#define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */\r
+#define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */\r
+\r
+#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */\r
+#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */\r
+\r
+#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */\r
+#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */\r
+\r
+#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */\r
+#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */\r
+\r
+#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */\r
+#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */\r
+\r
+#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */\r
+#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */\r
+\r
+#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */\r
+#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */\r
+\r
+#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */\r
+#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */\r
+\r
+#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */\r
+#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */\r
+\r
+#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */\r
+#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */\r
+\r
+#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */\r
+#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */\r
+\r
+#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */\r
+#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */\r
+\r
+#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */\r
+#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */\r
+\r
+#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */\r
+#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */\r
+\r
+#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */\r
+#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */\r
+\r
+#define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */\r
+#define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */\r
+\r
+#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */\r
+#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */\r
+\r
+#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */\r
+#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */\r
+\r
+#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */\r
+#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */\r
+\r
+#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */\r
+#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */\r
+\r
+#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */\r
+#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */\r
+\r
+#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */\r
+#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */\r
+\r
+#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */\r
+#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */\r
+\r
+#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */\r
+#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */\r
+\r
+#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */\r
+#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */\r
+\r
+#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */\r
+#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */\r
+\r
+#define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */\r
+#define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */\r
+\r
+#define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */\r
+#define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */\r
+\r
+#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */\r
+#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */\r
+\r
+#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */\r
+#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */\r
+\r
+#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */\r
+#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */\r
+\r
+#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */\r
+#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */\r
+\r
+#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */\r
+#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */\r
+\r
+#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */\r
+#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */\r
+\r
+#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */\r
+#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */\r
+\r
+#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */\r
+#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */\r
+\r
+#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */\r
+#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */\r
+\r
+#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */\r
+#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */\r
+\r
+#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */\r
+#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */\r
+\r
+#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */\r
+#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */\r
+\r
+#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */\r
+#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */\r
+\r
+#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */\r
+#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */\r
+\r
+#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */\r
+#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */\r
+\r
+#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */\r
+#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */\r
+\r
+#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */\r
+#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */\r
+\r
+#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */\r
+#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */\r
+\r
+#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */\r
+#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */\r
+\r
+#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */\r
+#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */\r
+\r
+#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */\r
+#define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */\r
+\r
+#define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */\r
+#define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */\r
+\r
+#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */\r
+#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */\r
+\r
+#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */\r
+#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */\r
+\r
+#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */\r
+#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */\r
+\r
+#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */\r
+#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */\r
+\r
+#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */\r
+#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */\r
+\r
+#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */\r
+#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */\r
+\r
+#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */\r
+#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */\r
+\r
+#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */\r
+#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */\r
+\r
+#define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */\r
+#define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */\r
+\r
+#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */\r
+#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */\r
+\r
+#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */\r
+#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */\r
+\r
+#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */\r
+#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */\r
+\r
+#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */\r
+#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */\r
+\r
+#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */\r
+#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */\r
+\r
+#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */\r
+#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */\r
+\r
+#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */\r
+#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */\r
+\r
+#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */\r
+#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */\r
+\r
+#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */\r
+#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */\r
+\r
+#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */\r
+#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */\r
+\r
+#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */\r
+#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */\r
+\r
+#define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */\r
+#define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */\r
+\r
+#define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */\r
+#define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */\r
+\r
+#define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */\r
+#define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */\r
+\r
+#define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */\r
+#define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */\r
+\r
+#define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */\r
+#define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */\r
+\r
+#define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */\r
+#define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */\r
+\r
+#define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */\r
+#define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */\r
+\r
+#define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */\r
+#define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */\r
+\r
+#define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */\r
+#define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */\r
+\r
+#define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */\r
+#define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */\r
+\r
+#define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */\r
+#define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */\r
+\r
+#define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */\r
+#define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */\r
+\r
+#define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */\r
+#define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */\r
+\r
+/**@}*/ /* UART_CONST */\r
+/**@}*/ /* end of UART register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __UART_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file ui2c_reg.h\r
+ * @version V1.00\r
+ * @brief UI2C register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __UI2C_REG_H__\r
+#define __UI2C_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- I2C Mode of USCI Controller -------------------------*/\r
+/**\r
+ @addtogroup UI2C I2C Mode of USCI Controller(UI2C)\r
+ Memory Mapped Structure for UI2C Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var UI2C_T::CTL\r
+ * Offset: 0x00 USCI Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |FUNMODE |Function Mode\r
+ * | | |This bit field selects the protocol for this USCI controller\r
+ * | | |Selecting a protocol that is not available or a reserved combination disables the USCI\r
+ * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol\r
+ * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\r
+ * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.\r
+ * | | |001 = The SPI protocol is selected.\r
+ * | | |010 = The UART protocol is selected.\r
+ * | | |100 = The I2C protocol is selected.\r
+ * | | |Note: Other bit combinations are reserved.\r
+ * @var UI2C_T::BRGEN\r
+ * Offset: 0x08 USCI Baud Rate Generator Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RCLKSEL |Reference Clock Source Selection\r
+ * | | |This bit selects the source signal of reference clock (fREF_CLK).\r
+ * | | |0 = Peripheral device clock fPCLK.\r
+ * | | |1 = Reserved.\r
+ * |[1] |PTCLKSEL |Protocol Clock Source Selection\r
+ * | | |This bit selects the source signal of protocol clock (fPROT_CLK).\r
+ * | | |0 = Reference clock fREF_CLK.\r
+ * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).\r
+ * |[3:2] |SPCLKSEL |Sample Clock Source Selection\r
+ * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.\r
+ * | | |00 = fSAMP_CLK = fDIV_CLK.\r
+ * | | |01 = fSAMP_CLK = fPROT_CLK.\r
+ * | | |10 = fSAMP_CLK = fSCLK.\r
+ * | | |11 = fSAMP_CLK = fREF_CLK.\r
+ * |[4] |TMCNTEN |Time Measurement Counter Enable Bit\r
+ * | | |This bit enables the 10-bit timing measurement counter.\r
+ * | | |0 = Time measurement counter is Disabled.\r
+ * | | |1 = Time measurement counter is Enabled.\r
+ * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection\r
+ * | | |0 = Time measurement counter with fPROT_CLK.\r
+ * | | |1 = Time measurement counter with fDIV_CLK.\r
+ * |[9:8] |PDSCNT |Pre-divider for Sample Counter\r
+ * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK\r
+ * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).\r
+ * |[14:10] |DSCNT |Denominator for Sample Counter\r
+ * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.\r
+ * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).\r
+ * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value\r
+ * |[25:16] |CLKDIV |Clock Divider\r
+ * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).\r
+ * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled\r
+ * | | |The revised value is the average bit time between bit 5 and bit 6\r
+ * | | |The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate.\r
+ * @var UI2C_T::LINECTL\r
+ * Offset: 0x2C USCI Line Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |LSB |LSB First Transmission Selection\r
+ * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.\r
+ * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.\r
+ * |[11:8] |DWIDTH |Word Length of Transmission\r
+ * | | |This bit field defines the data word length (amount of bits) for reception and transmission\r
+ * | | |The data word is always right-aligned in the data buffer\r
+ * | | |USCI support word length from 4 to 16 bits.\r
+ * | | |0x0: The data word contains 16 bits located at bit positions [15:0].\r
+ * | | |0x1: Reserved.\r
+ * | | |0x2: Reserved.\r
+ * | | |0x3: Reserved.\r
+ * | | |0x4: The data word contains 4 bits located at bit positions [3:0].\r
+ * | | |0x5: The data word contains 5 bits located at bit positions [4:0].\r
+ * | | |...\r
+ * | | |0xF: The data word contains 15 bits located at bit positions [14:0].\r
+ * | | |Note: In UART protocol, the length can be configured as 6~13 bits.\r
+ * @var UI2C_T::TXDAT\r
+ * Offset: 0x30 USCI Transmit Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |TXDAT |Transmit Data\r
+ * | | |Software can use this bit field to write 16-bit transmit data for transmission.\r
+ * @var UI2C_T::RXDAT\r
+ * Offset: 0x34 USCI Receive Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |RXDAT |Received Data\r
+ * | | |This bit field monitors the received data which stored in receive data buffer.\r
+ * | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.\r
+ * | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UI2C_PROTSTS[7:5]).\r
+ * @var UI2C_T::DEVADDR0\r
+ * Offset: 0x44 USCI Device Address Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[9:0] |DEVADDR |Device Address\r
+ * | | |In I2C protocol, this bit field contains the programmed slave address\r
+ * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit\r
+ * | | |Then the second address byte is also compared to DEVADDR[7:0].\r
+ * | | |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.\r
+ * @var UI2C_T::DEVADDR1\r
+ * Offset: 0x48 USCI Device Address Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[9:0] |DEVADDR |Device Address\r
+ * | | |In I2C protocol, this bit field contains the programmed slave address\r
+ * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit\r
+ * | | |Then the second address byte is also compared to DEVADDR[7:0].\r
+ * | | |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.\r
+ * @var UI2C_T::ADDRMSK0\r
+ * Offset: 0x4C USCI Device Address Mask Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[9:0] |ADDRMSK |USCI Device Address Mask\r
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).\r
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).\r
+ * | | |USCI support multiple address recognition with two address mask register\r
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care\r
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\r
+ * | | |Note: The wake-up function can not set address mask.\r
+ * @var UI2C_T::ADDRMSK1\r
+ * Offset: 0x50 USCI Device Address Mask Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[9:0] |ADDRMSK |USCI Device Address Mask\r
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).\r
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).\r
+ * | | |USCI support multiple address recognition with two address mask register\r
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care\r
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\r
+ * | | |Note: The wake-up function can not set address mask.\r
+ * @var UI2C_T::WKCTL\r
+ * Offset: 0x54 USCI Wake-up Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKEN |Wake-up Enable Bit\r
+ * | | |0 = Wake-up function Disabled.\r
+ * | | |1 = Wake-up function Enabled.\r
+ * |[1] |WKADDREN |Wake-up Address Match Enable Bit\r
+ * | | |0 = The chip is woken up according data toggle.\r
+ * | | |1 = The chip is woken up according address match.\r
+ * @var UI2C_T::WKSTS\r
+ * Offset: 0x58 USCI Wake-up Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKF |Wake-up Flag\r
+ * | | |When chip is woken up from Power-down mode, this bit is set to 1\r
+ * | | |Software can write 1 to clear this bit.\r
+ * @var UI2C_T::PROTCTL\r
+ * Offset: 0x5C USCI Protocol Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |GCFUNC |General Call Function\r
+ * | | |0 = General Call Function Disabled.\r
+ * | | |1 = General Call Function Enabled.\r
+ * |[1] |AA |Assert Acknowledge Control\r
+ * | | |When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter\r
+ * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.\r
+ * |[2] |STO |I2C STOP Control\r
+ * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically\r
+ * | | |In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode when bus error (UI2C_PROTSTS.ERRIF = 1).\r
+ * |[3] |STA |I2C START Control\r
+ * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.\r
+ * |[4] |ADDR10EN |Address 10-bit Function Enable Bit\r
+ * | | |0 = Address match 10 bit function is disabled.\r
+ * | | |1 = Address match 10 bit function is enabled.\r
+ * |[5] |PTRG |I2C Protocol Trigger (Write Only)\r
+ * | | |When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested\r
+ * | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.\r
+ * | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead.\r
+ * | | |1 = I2C's stretch active.\r
+ * |[8] |SCLOUTEN |SCL Output Enable Bit\r
+ * | | |This bit enables monitor pulling SCL to low\r
+ * | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.\r
+ * | | |0 = SCL output will be forced high due to open drain mechanism.\r
+ * | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt.\r
+ * |[9] |MONEN |Monitor Mode Enable Bit\r
+ * | | |This bit enables monitor mode\r
+ * | | |In monitor mode the SDA output will be put in high impedance mode\r
+ * | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\r
+ * | | |0 = The monitor mode is disabled.\r
+ * | | |1 = The monitor mode is enabled.\r
+ * | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.\r
+ * |[25:16] |TOCNT |Time-out Clock Cycle\r
+ * | | |This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear\r
+ * | | |The time-out is enable when TOCNT bigger than 0.\r
+ * | | |Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.\r
+ * |[31] |PROTEN |I2C Protocol Enable Bit\r
+ * | | |0 = I2C Protocol disable.\r
+ * | | |1 = I2C Protocol enable.\r
+ * @var UI2C_T::PROTIEN\r
+ * Offset: 0x60 USCI Protocol Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |TOIEN |Time-out Interrupt Enable Control\r
+ * | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event.\r
+ * | | |0 = The time-out interrupt is disabled.\r
+ * | | |1 = The time-out interrupt is enabled.\r
+ * |[1] |STARIEN |Start Condition Received Interrupt Enable Control\r
+ * | | |This bit enables the generation of a protocol interrupt if a start condition is detected.\r
+ * | | |0 = The start condition interrupt is disabled.\r
+ * | | |1 = The start condition interrupt is enabled.\r
+ * |[2] |STORIEN |Stop Condition Received Interrupt Enable Control\r
+ * | | |This bit enables the generation of a protocol interrupt if a stop condition is detected.\r
+ * | | |0 = The stop condition interrupt is disabled.\r
+ * | | |1 = The stop condition interrupt is enabled.\r
+ * |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control\r
+ * | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.\r
+ * | | |0 = The non - acknowledge interrupt is disabled.\r
+ * | | |1 = The non - acknowledge interrupt is enabled.\r
+ * |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control\r
+ * | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.\r
+ * | | |0 = The arbitration lost interrupt is disabled.\r
+ * | | |1 = The arbitration lost interrupt is enabled.\r
+ * |[5] |ERRIEN |Error Interrupt Enable Control\r
+ * | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).\r
+ * | | |0 = The error interrupt is disabled.\r
+ * | | |1 = The error interrupt is enabled.\r
+ * |[6] |ACKIEN |Acknowledge Interrupt Enable Control\r
+ * | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.\r
+ * | | |0 = The acknowledge interrupt is disabled.\r
+ * | | |1 = The acknowledge interrupt is enabled.\r
+ * @var UI2C_T::PROTSTS\r
+ * Offset: 0x64 USCI Protocol Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[5] |TOIF |Time-out Interrupt Flag\r
+ * | | |0 = A time-out interrupt status has not occurred.\r
+ * | | |1 = A time-out interrupt status has occurred.\r
+ * | | |Note: It is cleared by software writing one into this bit\r
+ * |[6] |ONBUSY |On Bus Busy\r
+ * | | |Indicates that a communication is in progress on the bus\r
+ * | | |It is set by hardware when a START condition is detected\r
+ * | | |It is cleared by hardware when a STOP condition is detected\r
+ * | | |0 = The bus is IDLE (both SCLK and SDA High).\r
+ * | | |1 = The bus is busy.\r
+ * |[8] |STARIF |Start Condition Received Interrupt Flag\r
+ * | | |This bit indicates that a start condition or repeated start condition has been detected on master mode\r
+ * | | |However, this bit also indicates that a repeated start condition has been detected on slave mode.\r
+ * | | |A protocol interrupt can be generated if UI2C_PROTCTL.STARIEN = 1.\r
+ * | | |0 = A start condition has not yet been detected.\r
+ * | | |1 = A start condition has been detected.\r
+ * | | |It is cleared by software writing one into this bit\r
+ * |[9] |STORIF |Stop Condition Received Interrupt Flag\r
+ * | | |This bit indicates that a stop condition has been detected on the I2C bus lines\r
+ * | | |A protocol interrupt can be generated if UI2C_PROTCTL.STORIEN = 1.\r
+ * | | |0 = A stop condition has not yet been detected.\r
+ * | | |1 = A stop condition has been detected.\r
+ * | | |It is cleared by software writing one into this bit\r
+ * | | |Note: This bit is set when slave RX mode.\r
+ * |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag\r
+ * | | |This bit indicates that a non - acknowledge has been received in master mode\r
+ * | | |A protocol interrupt can be generated if UI2C_PROTCTL.NACKIEN = 1.\r
+ * | | |0 = A non - acknowledge has not been received.\r
+ * | | |1 = A non - acknowledge has been received.\r
+ * | | |It is cleared by software writing one into this bit\r
+ * |[11] |ARBLOIF |Arbitration Lost Interrupt Flag\r
+ * | | |This bit indicates that an arbitration has been lost\r
+ * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ARBLOIEN = 1.\r
+ * | | |0 = An arbitration has not been lost.\r
+ * | | |1 = An arbitration has been lost.\r
+ * | | |It is cleared by software writing one into this bit\r
+ * |[12] |ERRIF |Error Interrupt Flag\r
+ * | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame\r
+ * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit\r
+ * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ERRIEN = 1.\r
+ * | | |0 = An I2C error has not been detected.\r
+ * | | |1 = An I2C error has been detected.\r
+ * | | |It is cleared by software writing one into this bit\r
+ * | | |Note: This bit is set when slave mode, user must write one into STO register to the defined not addressed slave mode.\r
+ * |[13] |ACKIF |Acknowledge Received Interrupt Flag\r
+ * | | |This bit indicates that an acknowledge has been received in master mode\r
+ * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ACKIEN = 1.\r
+ * | | |0 = An acknowledge has not been received.\r
+ * | | |1 = An acknowledge has been received.\r
+ * | | |It is cleared by software writing one into this bit\r
+ * |[14] |SLASEL |Slave Select Status\r
+ * | | |This bit indicates that this device has been selected as slave.\r
+ * | | |0 = The device is not selected as slave.\r
+ * | | |1 = The device is selected as slave.\r
+ * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.\r
+ * |[15] |SLAREAD |Slave Read Request Status\r
+ * | | |This bit indicates that a slave read request has been detected.\r
+ * | | |0 = A slave R/W bit is 1 has not been detected.\r
+ * | | |1 = A slave R/W bit is 1 has been detected.\r
+ * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.\r
+ * |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done\r
+ * | | |0 = The ACK bit cycle of address match frame isn't done.\r
+ * | | |1 = The ACK bit cycle of address match frame is done in power-down.\r
+ * | | |Note: This bit can't release when WKUPIF is set.\r
+ * |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame\r
+ * | | |0 = Write command be record on the address match wakeup frame.\r
+ * | | |1 = Read command be record on the address match wakeup frame.\r
+ * |[18] |BUSHANG |Bus Hang-up\r
+ * | | |This bit indicates bus hang-up status\r
+ * | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK\r
+ * | | |The hang-up counter will count to overflow and set this bit when SDA is low\r
+ * | | |The counter will be reset by falling edge of SCL signal.\r
+ * | | |0 = The bus is normal status for transmission.\r
+ * | | |1 = The bus is hang-up status for transmission.\r
+ * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.\r
+ * |[19] |ERRARBLO |Error Arbitration Lost\r
+ * | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor\r
+ * | | |The I2C can send start condition when ERRARBLO is set\r
+ * | | |Thus this bit doesn't be cared on slave mode.\r
+ * | | |0 = The bus is normal status for transmission.\r
+ * | | |1 = The bus is error arbitration lost status for transmission.\r
+ * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.\r
+ * @var UI2C_T::ADMAT\r
+ * Offset: 0x88 I2C Slave Match Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ADMAT0 |USCI Address 0 Match Status Register\r
+ * | | |When address 0 is matched, hardware will inform which address used\r
+ * | | |This bit will set to 1, and software can write 1 to clear this bit.\r
+ * |[1] |ADMAT1 |USCI Address 1 Match Status Register\r
+ * | | |When address 1 is matched, hardware will inform which address used\r
+ * | | |This bit will set to 1, and software can write 1 to clear this bit.\r
+ * @var UI2C_T::TMCTL\r
+ * Offset: 0x8C I2C Timing Configure Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[8:0] |STCTL |Setup Time Configure Control Register\r
+ * | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..\r
+ * | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK.\r
+ * |[24:16] |HTCTL |Hold Time Configure Control Register\r
+ * | | |This field is used to generate the delay timing between SCL falling edge SDA edge in\r
+ * | | |transmission mode.\r
+ * | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK.\r
+ */\r
+ __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */\r
+ __I uint32_t RESERVE0[1];\r
+ __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */\r
+ __I uint32_t RESERVE1[8];\r
+ __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */\r
+ __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */\r
+ __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */\r
+ __I uint32_t RESERVE2[3];\r
+ __IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */\r
+ __IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */\r
+ __IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */\r
+ __IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */\r
+ __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */\r
+ __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */\r
+ __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */\r
+ __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */\r
+ __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */\r
+ __I uint32_t RESERVE3[8];\r
+ __IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */\r
+ __IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */\r
+\r
+} UI2C_T;\r
+\r
+/**\r
+ @addtogroup UI2C_CONST UI2C Bit Field Definition\r
+ Constant Definitions for UI2C Controller\r
+@{ */\r
+\r
+#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */\r
+#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */\r
+\r
+#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */\r
+#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */\r
+\r
+#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */\r
+#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */\r
+\r
+#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */\r
+#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */\r
+\r
+#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */\r
+#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */\r
+\r
+#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */\r
+#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */\r
+\r
+#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */\r
+#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */\r
+\r
+#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */\r
+#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */\r
+\r
+#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */\r
+#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */\r
+\r
+#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */\r
+#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */\r
+\r
+#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */\r
+#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */\r
+\r
+#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */\r
+#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */\r
+\r
+#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */\r
+#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */\r
+\r
+#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */\r
+#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */\r
+\r
+#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */\r
+#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */\r
+\r
+#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */\r
+#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */\r
+\r
+#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */\r
+#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */\r
+\r
+#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */\r
+#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */\r
+\r
+#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */\r
+#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */\r
+\r
+#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */\r
+#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */\r
+\r
+#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */\r
+#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */\r
+\r
+#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */\r
+#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */\r
+\r
+#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */\r
+#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */\r
+\r
+#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */\r
+#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */\r
+\r
+#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */\r
+#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */\r
+\r
+#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */\r
+#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */\r
+\r
+#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */\r
+#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */\r
+\r
+#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */\r
+#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */\r
+\r
+#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */\r
+#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */\r
+\r
+#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */\r
+#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */\r
+\r
+#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */\r
+#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */\r
+\r
+#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */\r
+#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */\r
+\r
+#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */\r
+#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */\r
+\r
+#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */\r
+#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */\r
+\r
+#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */\r
+#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */\r
+\r
+#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */\r
+#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */\r
+\r
+#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */\r
+#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */\r
+\r
+#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */\r
+#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */\r
+\r
+#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */\r
+#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */\r
+\r
+#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */\r
+#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */\r
+\r
+#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */\r
+#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */\r
+\r
+#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */\r
+#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */\r
+\r
+#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */\r
+#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */\r
+\r
+#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */\r
+#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */\r
+\r
+#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */\r
+#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */\r
+\r
+#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */\r
+#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */\r
+\r
+#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */\r
+#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */\r
+\r
+#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */\r
+#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */\r
+\r
+#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */\r
+#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */\r
+\r
+#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */\r
+#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */\r
+\r
+#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */\r
+#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */\r
+\r
+#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */\r
+#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */\r
+\r
+#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */\r
+#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */\r
+\r
+#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */\r
+#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */\r
+\r
+#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */\r
+#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */\r
+\r
+/**@}*/ /* UI2C_CONST */\r
+/**@}*/ /* end of UI2C register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __UI2C_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file usbd_reg.h\r
+ * @version V1.00\r
+ * @brief USBD register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __USBD_REG_H__\r
+#define __USBD_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+/*---------------------- USB Device Controller -------------------------*/\r
+/**\r
+ @addtogroup USBD USB Device Controller(USBD)\r
+ Memory Mapped Structure for USBD Controller\r
+@{ */\r
+\r
+\r
+\r
+/**\r
+ * @brief USBD endpoints register\r
+ */\r
+typedef struct\r
+{\r
+ /**\r
+ * @var USBD_EP_T::BUFSEG\r
+ * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570/0x580/0x590/0x5A0/0x5B0 Endpoint Buffer Segmentation Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[8:3] |BUFSEG |Endpoint Buffer Segmentation\r
+ * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\r
+ * | | |USBD_SRAM address + { BUFSEG, 3'b000}\r
+ * | | |Where the USBD_SRAM address = USBD_BA+0x100h.\r
+ * | | |Refer to the section 6.29.5.7 for the endpoint SRAM structure and its description.\r
+ * @var USBD_EP_T::MXPLD\r
+ * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574/0x584/0x594/0x5A4/0x5B4 Endpoint Maximal Payload Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[8:0] |MXPLD |Maximal Payload\r
+ * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)\r
+ * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.\r
+ * | | |(1) When the register is written by CPU,\r
+ * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\r
+ * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\r
+ * | | |(2) When the register is read by CPU,\r
+ * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host\r
+ * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.\r
+ * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.\r
+ * @var USBD_EP_T::CFG\r
+ * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578/0x588/0x598/0x5A8/0x5B8 Endpoint Configuration Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |EPNUM |Endpoint Number\r
+ * | | |These bits are used to define the endpoint number of the current endpoint\r
+ * |[4] |ISOCH |Isochronous Endpoint\r
+ * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.\r
+ * | | |0 = No Isochronous endpoint.\r
+ * | | |1 = Isochronous endpoint.\r
+ * |[6:5] |STATE |Endpoint STATE\r
+ * | | |00 = Endpoint is Disabled.\r
+ * | | |01 = Out endpoint.\r
+ * | | |10 = IN endpoint.\r
+ * | | |11 = Undefined.\r
+ * |[7] |DSQSYNC |Data Sequence Synchronization\r
+ * | | |0 = DATA0 PID.\r
+ * | | |1 = DATA1 PID.\r
+ * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction\r
+ * | | |hardware will toggle automatically in IN token base on the bit.\r
+ * |[9] |CSTALL |Clear STALL Response\r
+ * | | |0 = Disable the device to clear the STALL handshake in setup stage.\r
+ * | | |1 = Clear the device to response STALL handshake in setup stage.\r
+ * @var USBD_EP_T::CFGP\r
+ * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C/0x58C/0x59C/0x5AC/0x5BC Endpoint Set Stall and Clear In/Out Ready Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CLRRDY |Clear Ready\r
+ * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data\r
+ * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.\r
+ * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB.\r
+ * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.\r
+ * | | |This bit is write 1 only and is always 0 when it is read back.\r
+ * |[1] |SSTALL |Set STALL\r
+ * | | |0 = Disable the device to response STALL.\r
+ * | | |1 = Set the device to respond STALL automatically.\r
+ */\r
+ __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint Buffer Segmentation Register */\r
+ __IO uint32_t MXPLD; /*!< [0x0004] Endpoint Maximal Payload Register */\r
+ __IO uint32_t CFG; /*!< [0x0008] Endpoint Configuration Register */\r
+ __IO uint32_t CFGP; /*!< [0x000c] Endpoint Set Stall and Clear In/Out Ready Control Register */\r
+\r
+} USBD_EP_T;\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var USBD_T::INTEN\r
+ * Offset: 0x00 USB Device Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BUSIEN |Bus Event Interrupt Enable Bit\r
+ * | | |0 = BUS event interrupt Disabled.\r
+ * | | |1 = BUS event interrupt Enabled.\r
+ * |[1] |USBIEN |USB Event Interrupt Enable Bit\r
+ * | | |0 = USB event interrupt Disabled.\r
+ * | | |1 = USB event interrupt Enabled.\r
+ * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit\r
+ * | | |0 = VBUS detection Interrupt Disabled.\r
+ * | | |1 = VBUS detection Interrupt Enabled.\r
+ * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit\r
+ * | | |0 = No-event-wake-up Interrupt Disabled.\r
+ * | | |1 = No-event-wake-up Interrupt Enabled.\r
+ * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit\r
+ * | | |0 = SOF Interrupt Disabled.\r
+ * | | |1 = SOF Interrupt Enabled.\r
+ * |[8] |WKEN |Wake-up Function Enable Bit\r
+ * | | |0 = USB wake-up function Disabled.\r
+ * | | |1 = USB wake-up function Enabled.\r
+ * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token\r
+ * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted.\r
+ * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token.\r
+ * @var USBD_T::INTSTS\r
+ * Offset: 0x04 USB Device Interrupt Event Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |BUSIF |BUS Interrupt Status\r
+ * | | |The BUS event means that there is one of the suspense or the resume function in the bus.\r
+ * | | |0 = No BUS event occurred.\r
+ * | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0].\r
+ * |[1] |USBIF |USB Event Interrupt Status\r
+ * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.\r
+ * | | |0 = No USB event occurred.\r
+ * | | |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]).\r
+ * |[2] |VBDETIF |VBUS Detection Interrupt Status\r
+ * | | |0 = There is not attached/detached event in the USB.\r
+ * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2].\r
+ * |[3] |NEVWKIF |No-event-wake-up Interrupt Status\r
+ * | | |0 = NEVWK event does not occur.\r
+ * | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3].\r
+ * |[4] |SOFIF |Start of Frame Interrupt Status\r
+ * | | |0 = SOF event does not occur.\r
+ * | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4].\r
+ * |[16] |EPEVT0 |Endpoint 0's USB Event Status\r
+ * | | |0 = No event occurred in endpoint 0.\r
+ * | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1].\r
+ * |[17] |EPEVT1 |Endpoint 1's USB Event Status\r
+ * | | |0 = No event occurred in endpoint 1.\r
+ * | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1].\r
+ * |[18] |EPEVT2 |Endpoint 2's USB Event Status\r
+ * | | |0 = No event occurred in endpoint 2.\r
+ * | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1].\r
+ * |[19] |EPEVT3 |Endpoint 3's USB Event Status\r
+ * | | |0 = No event occurred in endpoint 3.\r
+ * | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1].\r
+ * |[20] |EPEVT4 |Endpoint 4's USB Event Status\r
+ * | | |0 = No event occurred in endpoint 4.\r
+ * | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1].\r
+ * |[21] |EPEVT5 |Endpoint 5's USB Event Status\r
+ * | | |0 = No event occurred in endpoint 5.\r
+ * | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1].\r
+ * |[22] |EPEVT6 |Endpoint 6's USB Event Status\r
+ * | | |0 = No event occurred in endpoint 6.\r
+ * | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1].\r
+ * |[23] |EPEVT7 |Endpoint 7's USB Event Status\r
+ * | | |0 = No event occurred in endpoint 7.\r
+ * | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1].\r
+ * |[24] |EPEVT8 |Endpoint 8's USB Event Status\r
+ * | | |0 = No event occurred in endpoint 8.\r
+ * | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1].\r
+ * |[25] |EPEVT9 |Endpoint 9's USB Event Status\r
+ * | | |0 = No event occurred in endpoint 9.\r
+ * | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1].\r
+ * |[26] |EPEVT10 |Endpoint 10's USB Event Status\r
+ * | | |0 = No event occurred in endpoint 10.\r
+ * | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1].\r
+ * |[27] |EPEVT11 |Endpoint 11's USB Event Status\r
+ * | | |0 = No event occurred in endpoint 11.\r
+ * | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1].\r
+ * |[31] |SETUP |Setup Event Status\r
+ * | | |0 = No Setup event.\r
+ * | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31].\r
+ * @var USBD_T::FADDR\r
+ * Offset: 0x08 USB Device Function Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[6:0] |FADDR |USB Device Function Address\r
+ * @var USBD_T::EPSTS\r
+ * Offset: 0x0C USB Device Endpoint Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7] |OV |Overrun\r
+ * | | |It indicates that the received data is over the maximum payload number or not.\r
+ * | | |0 = No overrun.\r
+ * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.\r
+ * @var USBD_T::ATTR\r
+ * Offset: 0x10 USB Device Bus Status and Attribution Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |USBRST |USB Reset Status\r
+ * | | |0 = Bus no reset.\r
+ * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us.\r
+ * | | |Note: This bit is read only.\r
+ * |[1] |SUSPEND |Suspend Status\r
+ * | | |0 = Bus no suspend.\r
+ * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.\r
+ * | | |Note: This bit is read only.\r
+ * |[2] |RESUME |Resume Status\r
+ * | | |0 = No bus resume.\r
+ * | | |1 = Resume from suspend.\r
+ * | | |Note: This bit is read only.\r
+ * |[3] |TOUT |Time-out Status\r
+ * | | |0 = No time-out.\r
+ * | | |1 = No Bus response more than 18 bits time.\r
+ * | | |Note: This bit is read only.\r
+ * |[4] |PHYEN |PHY Transceiver Function Enable Bit\r
+ * | | |0 = PHY transceiver function Disabled.\r
+ * | | |1 = PHY transceiver function Enabled.\r
+ * |[5] |RWAKEUP |Remote Wake-up\r
+ * | | |0 = Release the USB bus from K state.\r
+ * | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up.\r
+ * |[7] |USBEN |USB Controller Enable Bit\r
+ * | | |0 = USB Controller Disabled.\r
+ * | | |1 = USB Controller Enabled.\r
+ * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit\r
+ * | | |0 = Pull-up resistor in USB_D+ bus Disabled.\r
+ * | | |1 = Pull-up resistor in USB_D+ bus Active.\r
+ * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection\r
+ * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.\r
+ * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.\r
+ * |[11] |LPMACK |LPM Token Acknowledge Enable Bit\r
+ * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively.\r
+ * | | |0= the valid LPM Token will be NYET.\r
+ * | | |1= the valid LPM Token will be ACK.\r
+ * |[12] |L1SUSPEND |LPM L1 Suspend\r
+ * | | |0 = Bus no L1 state suspend.\r
+ * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged.\r
+ * | | |Note: This bit is read only.\r
+ * |[13] |L1RESUME |LPM L1 Resume\r
+ * | | |0 = Bus no LPM L1 state resume.\r
+ * | | |1 = LPM L1 state Resume from LPM L1 state suspend.\r
+ * | | |Note: This bit is read only.\r
+ * @var USBD_T::VBUSDET\r
+ * Offset: 0x14 USB Device VBUS Detection Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |VBUSDET |Device VBUS Detection\r
+ * | | |0 = Controller is not attached to the USB host.\r
+ * | | |1 = Controller is attached to the USB host.\r
+ * @var USBD_T::STBUFSEG\r
+ * Offset: 0x18 SETUP Token Buffer Segmentation Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation\r
+ * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is\r
+ * | | |USBD_SRAM address + {STBUFSEG, 3'b000}\r
+ * | | |Where the USBD_SRAM address = USBD_BA+0x100h.\r
+ * | | |Note: It is used for SETUP token only.\r
+ * @var USBD_T::EPSTS0\r
+ * Offset: 0x20 USB Device Endpoint Status Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |EPSTS0 |Endpoint 0 Status\r
+ * | | |These bits are used to indicate the current status of this endpoint\r
+ * | | |0000 = In ACK.\r
+ * | | |0001 = In NAK.\r
+ * | | |0010 = Out Packet Data0 ACK.\r
+ * | | |0011 = Setup ACK.\r
+ * | | |0110 = Out Packet Data1 ACK.\r
+ * | | |0111 = Isochronous transfer end.\r
+ * |[7:4] |EPSTS1 |Endpoint 1 Status\r
+ * | | |These bits are used to indicate the current status of this endpoint\r
+ * | | |0000 = In ACK.\r
+ * | | |0001 = In NAK.\r
+ * | | |0010 = Out Packet Data0 ACK.\r
+ * | | |0011 = Setup ACK.\r
+ * | | |0110 = Out Packet Data1 ACK.\r
+ * | | |0111 = Isochronous transfer end.\r
+ * |[11:8] |EPSTS2 |Endpoint 2 Status\r
+ * | | |These bits are used to indicate the current status of this endpoint\r
+ * | | |0000 = In ACK.\r
+ * | | |0001 = In NAK.\r
+ * | | |0010 = Out Packet Data0 ACK.\r
+ * | | |0011 = Setup ACK.\r
+ * | | |0110 = Out Packet Data1 ACK.\r
+ * | | |0111 = Isochronous transfer end.\r
+ * |[15:12] |EPSTS3 |Endpoint 3 Status\r
+ * | | |These bits are used to indicate the current status of this endpoint\r
+ * | | |0000 = In ACK.\r
+ * | | |0001 = In NAK.\r
+ * | | |0010 = Out Packet Data0 ACK.\r
+ * | | |0011 = Setup ACK.\r
+ * | | |0110 = Out Packet Data1 ACK.\r
+ * | | |0111 = Isochronous transfer end.\r
+ * |[19:16] |EPSTS4 |Endpoint 4 Status\r
+ * | | |These bits are used to indicate the current status of this endpoint\r
+ * | | |0000 = In ACK.\r
+ * | | |0001 = In NAK.\r
+ * | | |0010 = Out Packet Data0 ACK.\r
+ * | | |0011 = Setup ACK.\r
+ * | | |0110 = Out Packet Data1 ACK.\r
+ * | | |0111 = Isochronous transfer end.\r
+ * |[23:20] |EPSTS5 |Endpoint 5 Status\r
+ * | | |These bits are used to indicate the current status of this endpoint\r
+ * | | |0000 = In ACK.\r
+ * | | |0001 = In NAK.\r
+ * | | |0010 = Out Packet Data0 ACK.\r
+ * | | |0011 = Setup ACK.\r
+ * | | |0110 = Out Packet Data1 ACK.\r
+ * | | |0111 = Isochronous transfer end.\r
+ * |[27:24] |EPSTS6 |Endpoint 6 Status\r
+ * | | |These bits are used to indicate the current status of this endpoint\r
+ * | | |0000 = In ACK.\r
+ * | | |0001 = In NAK.\r
+ * | | |0010 = Out Packet Data0 ACK.\r
+ * | | |0011 = Setup ACK.\r
+ * | | |0110 = Out Packet Data1 ACK.\r
+ * | | |0111 = Isochronous transfer end.\r
+ * |[31:28] |EPSTS7 |Endpoint 7 Status\r
+ * | | |These bits are used to indicate the current status of this endpoint\r
+ * | | |0000 = In ACK.\r
+ * | | |0001 = In NAK.\r
+ * | | |0010 = Out Packet Data0 ACK.\r
+ * | | |0011 = Setup ACK.\r
+ * | | |0110 = Out Packet Data1 ACK.\r
+ * | | |0111 = Isochronous transfer end.\r
+ * @var USBD_T::EPSTS1\r
+ * Offset: 0x24 USB Device Endpoint Status Register 1\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |EPSTS8 |Endpoint 8 Status\r
+ * | | |These bits are used to indicate the current status of this endpoint\r
+ * | | |0000 = In ACK.\r
+ * | | |0001 = In NAK.\r
+ * | | |0010 = Out Packet Data0 ACK.\r
+ * | | |0011 = Setup ACK.\r
+ * | | |0110 = Out Packet Data1 ACK.\r
+ * | | |0111 = Isochronous transfer end.\r
+ * |[7:4] |EPSTS9 |Endpoint 9 Status\r
+ * | | |These bits are used to indicate the current status of this endpoint\r
+ * | | |0000 = In ACK.\r
+ * | | |0001 = In NAK.\r
+ * | | |0010 = Out Packet Data0 ACK.\r
+ * | | |0011 = Setup ACK.\r
+ * | | |0110 = Out Packet Data1 ACK.\r
+ * | | |0111 = Isochronous transfer end.\r
+ * |[11:8] |EPSTS10 |Endpoint 10 Status\r
+ * | | |These bits are used to indicate the current status of this endpoint\r
+ * | | |0000 = In ACK.\r
+ * | | |0001 = In NAK.\r
+ * | | |0010 = Out Packet Data0 ACK.\r
+ * | | |0011 = Setup ACK.\r
+ * | | |0110 = Out Packet Data1 ACK.\r
+ * | | |0111 = Isochronous transfer end.\r
+ * |[15:12] |EPSTS11 |Endpoint 11 Status\r
+ * | | |These bits are used to indicate the current status of this endpoint\r
+ * | | |0000 = In ACK.\r
+ * | | |0001 = In NAK.\r
+ * | | |0010 = Out Packet Data0 ACK.\r
+ * | | |0011 = Setup ACK.\r
+ * | | |0110 = Out Packet Data1 ACK.\r
+ * | | |0111 = Isochronous transfer end.\r
+ * @var USBD_T::LPMATTR\r
+ * Offset: 0x88 USB LPM Attribution Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |LPMLINKSTS|LPM Link State\r
+ * | | |These bits contain the bLinkState received with last ACK LPM Token\r
+ * | | |0000 = Reserve.\r
+ * | | |0001 = L1 (Sleep).\r
+ * | | |0010 - 1111 = Reserve.\r
+ * |[7:4] |LPMBESL |LPM Best Effort Service Latency\r
+ * | | |These bits contain the BESL value received with last ACK LPM Token\r
+ * | | |0000 = 125us.\r
+ * | | |0001 = 150us.\r
+ * | | |0010 = 200us.\r
+ * | | |0011 = 300us.\r
+ * | | |0100 = 400us.\r
+ * | | |0101 = 500us.\r
+ * | | |0110 = 1000us.\r
+ * | | |0111 = 2000us.\r
+ * | | |1000 = 3000us.\r
+ * | | |1001 = 4000us.\r
+ * | | |1010 = 5000us.\r
+ * | | |1011 = 6000us.\r
+ * | | |1100 = 7000us.\r
+ * | | |1101 = 8000us.\r
+ * | | |1110 = 9000us.\r
+ * | | |1111 = 10000us.\r
+ * |[8] |LPMRWAKUP |LPM Remote Wakeup\r
+ * | | |This bit contains the bRemoteWake value received with last ACK LPM Token\r
+ * @var USBD_T::FN\r
+ * Offset: 0x8C USB Frame number Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[10:0] |FN |Frame Number\r
+ * | | |These bits contain the 11-bits frame number in the last received SOF packet.\r
+ * @var USBD_T::SE0\r
+ * Offset: 0x90 USB Device Drive SE0 Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SE0 |Drive Single Ended Zero in USB Bus\r
+ * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.\r
+ * | | |0 = Normal operation.\r
+ * | | |1 = Force USB PHY transceiver to drive SE0.\r
+ */\r
+\r
+ __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */\r
+ __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */\r
+ __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */\r
+ __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */\r
+ __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */\r
+ __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */\r
+ __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */\r
+ __I uint32_t RESERVE0[1];\r
+ __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */\r
+ __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */\r
+ __I uint32_t RESERVE1[24];\r
+ __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */\r
+ __I uint32_t FN; /*!< [0x008c] USB Frame number Register */\r
+ __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */\r
+ __I uint32_t RESERVE2[283];\r
+ USBD_EP_T EP[12]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */\r
+\r
+} USBD_T;\r
+\r
+/**\r
+ @addtogroup USBD_CONST USBD Bit Field Definition\r
+ Constant Definitions for USBD Controller\r
+@{ */\r
+\r
+#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */\r
+#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */\r
+\r
+#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */\r
+#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */\r
+\r
+#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */\r
+#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */\r
+\r
+#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */\r
+#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */\r
+\r
+#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */\r
+#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */\r
+\r
+#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */\r
+#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */\r
+\r
+#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */\r
+#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */\r
+\r
+#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */\r
+#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */\r
+\r
+#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */\r
+#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */\r
+\r
+#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */\r
+#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */\r
+\r
+#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */\r
+#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */\r
+\r
+#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */\r
+#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */\r
+\r
+#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */\r
+#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */\r
+\r
+#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */\r
+#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */\r
+\r
+#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */\r
+#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */\r
+\r
+#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */\r
+#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */\r
+\r
+#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */\r
+#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */\r
+\r
+#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */\r
+#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */\r
+\r
+#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */\r
+#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */\r
+\r
+#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */\r
+#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */\r
+\r
+#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */\r
+#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */\r
+\r
+#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */\r
+#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */\r
+\r
+#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */\r
+#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */\r
+\r
+#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */\r
+#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */\r
+\r
+#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */\r
+#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */\r
+\r
+#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */\r
+#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */\r
+\r
+#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */\r
+#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */\r
+\r
+#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */\r
+#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */\r
+\r
+#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */\r
+#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */\r
+\r
+#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */\r
+#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */\r
+\r
+#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */\r
+#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */\r
+\r
+#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */\r
+#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */\r
+\r
+#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */\r
+#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */\r
+\r
+#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */\r
+#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */\r
+\r
+#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */\r
+#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */\r
+\r
+#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */\r
+#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */\r
+\r
+#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */\r
+#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */\r
+\r
+#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */\r
+#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */\r
+\r
+#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */\r
+#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */\r
+\r
+#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */\r
+#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */\r
+\r
+#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */\r
+#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */\r
+\r
+#define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */\r
+#define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */\r
+\r
+#define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */\r
+#define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */\r
+\r
+#define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */\r
+#define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */\r
+\r
+#define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */\r
+#define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */\r
+\r
+#define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */\r
+#define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */\r
+\r
+#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */\r
+#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */\r
+\r
+#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */\r
+#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */\r
+\r
+#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */\r
+#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */\r
+\r
+#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */\r
+#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */\r
+\r
+#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */\r
+#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */\r
+\r
+#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */\r
+#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */\r
+\r
+#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */\r
+#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */\r
+\r
+#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */\r
+#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */\r
+\r
+#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */\r
+#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */\r
+\r
+#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */\r
+#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */\r
+\r
+#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */\r
+#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */\r
+\r
+#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */\r
+#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */\r
+\r
+#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */\r
+#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */\r
+\r
+#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */\r
+#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */\r
+\r
+#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */\r
+#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */\r
+\r
+#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */\r
+#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */\r
+\r
+#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */\r
+#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */\r
+\r
+#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */\r
+#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */\r
+\r
+#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */\r
+#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */\r
+\r
+#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */\r
+#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */\r
+\r
+#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */\r
+#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */\r
+\r
+\r
+/**@}*/ /* USBD_CONST */\r
+/**@}*/ /* end of USBD register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __USBD_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file usbh_reg.h\r
+ * @version V1.00\r
+ * @brief USBH register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __USBH_REG_H__\r
+#define __USBH_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- USB Host Controller -------------------------*/\r
+/**\r
+ @addtogroup USBH USB Host Controller(USBH)\r
+ Memory Mapped Structure for USBH Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var USBH_T::HcRevision\r
+ * Offset: 0x00 Host Controller Revision Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |REV |Revision Number\r
+ * | | |Indicates the Open HCI Specification revision number implemented by the Hardware\r
+ * | | |Host Controller supports 1.1 specification.\r
+ * | | |(X.Y = XYh).\r
+ * @var USBH_T::HcControl\r
+ * Offset: 0x04 Host Controller Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |CBSR |Control Bulk Service Ratio\r
+ * | | |This specifies the service ratio between Control and Bulk EDs\r
+ * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs\r
+ * | | |The internal count will be retained when crossing the frame boundary\r
+ * | | |In case of reset, HCD is responsible for restoring this\r
+ * | | |Value.\r
+ * | | |00 = Number of Control EDs over Bulk EDs served is 1:1.\r
+ * | | |01 = Number of Control EDs over Bulk EDs served is 2:1.\r
+ * | | |10 = Number of Control EDs over Bulk EDs served is 3:1.\r
+ * | | |11 = Number of Control EDs over Bulk EDs served is 4:1.\r
+ * |[2] |PLE |Periodic List Enable Bit\r
+ * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list\r
+ * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.\r
+ * | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled.\r
+ * | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled.\r
+ * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.\r
+ * |[3] |IE |Isochronous List Enable Bit\r
+ * | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list\r
+ * | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.\r
+ * | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled.\r
+ * | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too.\r
+ * |[4] |CLE |Control List Enable Bit\r
+ * | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled.\r
+ * | | |1 = Processing of the Control list in the next frame Enabled.\r
+ * |[5] |BLE |Bulk List Enable Bit\r
+ * | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled.\r
+ * | | |1 = Processing of the Bulk list in the next frame Enabled.\r
+ * |[7:6] |HCFS |Host Controller Functional State\r
+ * | | |This field sets the Host Controller state\r
+ * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port\r
+ * | | |States are:\r
+ * | | |00 = USBSUSPEND.\r
+ * | | |01 = USBOPERATIONAL.\r
+ * | | |10 = USBRESUME.\r
+ * | | |11 = USBRESET.\r
+ * @var USBH_T::HcCommandStatus\r
+ * Offset: 0x08 Host Controller Command Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |HCR |Host Controller Reset\r
+ * | | |This bit is set to initiate the software reset of Host Controller\r
+ * | | |This bit is cleared by the Host Controller, upon completed of the reset operation.\r
+ * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.\r
+ * | | |0 = Host Controller is not in software reset state.\r
+ * | | |1 = Host Controller is in software reset state.\r
+ * |[1] |CLF |Control List Filled\r
+ * | | |Set high to indicate there is an active TD on the Control List\r
+ * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.\r
+ * | | |0 = No active TD found or Host Controller begins to process the head of the Control list.\r
+ * | | |1 = An active TD added or found on the Control list.\r
+ * |[2] |BLF |Bulk List Filled\r
+ * | | |Set high to indicate there is an active TD on the Bulk list\r
+ * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.\r
+ * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list.\r
+ * | | |1 = An active TD added or found on the Bulk list.\r
+ * |[17:16] |SOC |Schedule Overrun Count\r
+ * | | |These bits are incremented on each scheduling overrun error\r
+ * | | |It is initialized to 00b and wraps around at 11b\r
+ * | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.\r
+ * @var USBH_T::HcInterruptStatus\r
+ * Offset: 0x0C Host Controller Interrupt Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SO |Scheduling Overrun\r
+ * | | |Set when the List Processor determines a Schedule Overrun has occurred.\r
+ * | | |0 = Schedule Overrun didn't occur.\r
+ * | | |1 = Schedule Overrun has occurred.\r
+ * |[1] |WDH |Write Back Done Head\r
+ * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead\r
+ * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared.\r
+ * | | |0 =.Host Controller didn't update HccaDoneHead.\r
+ * | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead.\r
+ * |[2] |SF |Start of Frame\r
+ * | | |Set when the Frame Management functional block signals a u2018Start of Frame' event\r
+ * | | |Host Control generates a SOF token at the same time.\r
+ * | | |0 =.Not the start of a frame.\r
+ * | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token.\r
+ * |[3] |RD |Resume Detected\r
+ * | | |Set when Host Controller detects resume signaling on a downstream port.\r
+ * | | |0 = No resume signaling detected on a downstream port.\r
+ * | | |1 = Resume signaling detected on a downstream port.\r
+ * |[5] |FNO |Frame Number Overflow\r
+ * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.\r
+ * | | |0 = The bit 15 of Frame Number didn't change.\r
+ * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.\r
+ * |[6] |RHSC |Root Hub Status Change\r
+ * | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed.\r
+ * | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change.\r
+ * | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed.\r
+ * @var USBH_T::HcInterruptEnable\r
+ * Offset: 0x10 Host Controller Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SO |Scheduling Overrun Enable Bit\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.\r
+ * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.\r
+ * |[1] |WDH |Write Back Done Head Enable Bit\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.\r
+ * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.\r
+ * |[2] |SF |Start of Frame Enable Bit\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.\r
+ * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.\r
+ * |[3] |RD |Resume Detected Enable Bit\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.\r
+ * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.\r
+ * |[5] |FNO |Frame Number Overflow Enable Bit\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.\r
+ * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.\r
+ * |[6] |RHSC |Root Hub Status Change Enable Bit\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.\r
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.\r
+ * |[31] |MIE |Master Interrupt Enable Bit\r
+ * | | |This bit is a global interrupt enable\r
+ * | | |A write of u20181' allows interrupts to be enabled via the specific enable bits listed above.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.\r
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.\r
+ * @var USBH_T::HcInterruptDisable\r
+ * Offset: 0x14 Host Controller Interrupt Disable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SO |Scheduling Overrun Disable Bit\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.\r
+ * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.\r
+ * |[1] |WDH |Write Back Done Head Disable Bit\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.\r
+ * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.\r
+ * |[2] |SF |Start of Frame Disable Bit\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.\r
+ * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.\r
+ * |[3] |RD |Resume Detected Disable Bit\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.\r
+ * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.\r
+ * |[5] |FNO |Frame Number Overflow Disable Bit\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.\r
+ * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.\r
+ * |[6] |RHSC |Root Hub Status Change Disable Bit\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.\r
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.\r
+ * |[31] |MIE |Master Interrupt Disable Bit\r
+ * | | |Global interrupt disable. Writing u20181' to disable all interrupts.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.\r
+ * | | |Read Operation:\r
+ * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.\r
+ * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.\r
+ * @var USBH_T::HcHCCA\r
+ * Offset: 0x18 Host Controller Communication Area Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:8] |HCCA |Host Controller Communication Area\r
+ * | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA).\r
+ * @var USBH_T::HcPeriodCurrentED\r
+ * Offset: 0x1C Host Controller Period Current ED Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:4] |PCED |Periodic Current ED\r
+ * | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.\r
+ * @var USBH_T::HcControlHeadED\r
+ * Offset: 0x20 Host Controller Control Head ED Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:4] |CHED |Control Head ED\r
+ * | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.\r
+ * @var USBH_T::HcControlCurrentED\r
+ * Offset: 0x24 Host Controller Control Current ED Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:4] |CCED |Control Current Head ED\r
+ * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.\r
+ * @var USBH_T::HcBulkHeadED\r
+ * Offset: 0x28 Host Controller Bulk Head ED Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:4] |BHED |Bulk Head ED\r
+ * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.\r
+ * @var USBH_T::HcBulkCurrentED\r
+ * Offset: 0x2C Host Controller Bulk Current ED Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:4] |BCED |Bulk Current Head ED\r
+ * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list.\r
+ * @var USBH_T::HcDoneHead\r
+ * Offset: 0x30 Host Controller Done Head Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:4] |DH |Done Head\r
+ * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.\r
+ * @var USBH_T::HcFmInterval\r
+ * Offset: 0x34 Host Controller Frame Interval Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[13:0] |FI |Frame Interval\r
+ * | | |This field specifies the length of a frame as (bit times - 1)\r
+ * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.\r
+ * |[30:16] |FSMPS |FS Largest Data Packet\r
+ * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.\r
+ * |[31] |FIT |Frame Interval Toggle\r
+ * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).\r
+ * | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]).\r
+ * | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]).\r
+ * @var USBH_T::HcFmRemaining\r
+ * Offset: 0x38 Host Controller Frame Remaining Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[13:0] |FR |Frame Remaining\r
+ * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period\r
+ * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval\r
+ * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.\r
+ * |[31] |FRT |Frame Remaining Toggle\r
+ * | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.\r
+ * @var USBH_T::HcFmNumber\r
+ * Offset: 0x3C Host Controller Frame Number Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |FN |Frame Number\r
+ * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0])\r
+ * | | |The count rolls over from u2018FFFFh' to u20180h.'\r
+ * @var USBH_T::HcPeriodicStart\r
+ * Offset: 0x40 Host Controller Periodic Start Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[13:0] |PS |Periodic Start\r
+ * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.\r
+ * @var USBH_T::HcLSThreshold\r
+ * Offset: 0x44 Host Controller Low-speed Threshold Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[11:0] |LST |Low-speed Threshold\r
+ * | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction\r
+ * | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field\r
+ * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.\r
+ * @var USBH_T::HcRhDescriptorA\r
+ * Offset: 0x48 Host Controller Root Hub Descriptor A Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |NDP |Number Downstream Ports\r
+ * | | |USB host control supports two downstream ports and only one port is available in this series of chip.\r
+ * |[8] |PSM |Power Switching Mode\r
+ * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled.\r
+ * | | |0 = Global Switching.\r
+ * | | |1 = Individual Switching.\r
+ * |[11] |OCPM |over Current Protection Mode\r
+ * | | |This bit describes how the over current status for the Root Hub ports reported\r
+ * | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.\r
+ * | | |0 = Global Over current.\r
+ * | | |1 = Individual Over current.\r
+ * |[12] |NOCP |No over Current Protection\r
+ * | | |This bit describes how the over current status for the Root Hub ports reported.\r
+ * | | |0 = Over current status is reported.\r
+ * | | |1 = Over current status is not reported.\r
+ * @var USBH_T::HcRhDescriptorB\r
+ * Offset: 0x4C Host Controller Root Hub Descriptor B Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:16] |PPCM |Port Power Control Mask\r
+ * | | |Global power switching\r
+ * | | |This field is only valid if PowerSwitchingMode is set (individual port switching)\r
+ * | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower)\r
+ * | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).\r
+ * | | |0 = Port power controlled by global power switching.\r
+ * | | |1 = Port power controlled by port power switching.\r
+ * | | |Note: PPCM[15:2] and PPCM[0] are reserved.\r
+ * @var USBH_T::HcRhStatus\r
+ * Offset: 0x50 Host Controller Root Hub Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |LPS |Clear Global Power\r
+ * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power.\r
+ * | | |This bit always read as zero.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear global power.\r
+ * |[1] |OCI |over Current Indicator\r
+ * | | |This bit reflects the state of the over current status pin\r
+ * | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.\r
+ * | | |0 = No over current condition.\r
+ * | | |1 = Over current condition.\r
+ * |[15] |DRWE |Device Remote Wakeup Enable Bit\r
+ * | | |This bit controls if port's Connect Status Change as a remote wake-up event.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Connect Status Change as a remote wake-up event Enabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Connect Status Change as a remote wake-up event Disabled.\r
+ * | | |1 = Connect Status Change as a remote wake-up event Enabled.\r
+ * |[16] |LPSC |Set Global Power\r
+ * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports.\r
+ * | | |This bit always read as zero.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Set global power.\r
+ * |[17] |OCIC |over Current Indicator Change\r
+ * | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).\r
+ * | | |Write 1 to clear this bit to zero.\r
+ * | | |0 = OCI (HcRhStatus[1]) didn't change.\r
+ * | | |1 = OCI (HcRhStatus[1]) change.\r
+ * |[31] |CRWE |Clear Remote Wake-up Enable Bit\r
+ * | | |This bit is use to clear DRWE (HcRhStatus[15]).\r
+ * | | |This bit always read as zero.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear DRWE (HcRhStatus[15]).\r
+ * @var USBH_T::HcRhPortStatus[2]\r
+ * Offset: 0x54 Host Controller Root Hub Port Status\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |CCS |CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear port enable.\r
+ * | | |Read Operation:\r
+ * | | |0 = No device connected.\r
+ * | | |1 = Device connected.\r
+ * |[1] |PES |Port Enable Status\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Set port enable.\r
+ * | | |Read Operation:\r
+ * | | |0 = Port Disabled.\r
+ * | | |1 = Port Enabled.\r
+ * |[2] |PSS |Port Suspend Status\r
+ * | | |This bit indicates the port is suspended\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Set port suspend.\r
+ * | | |Read Operation:\r
+ * | | |0 = Port is not suspended.\r
+ * | | |1 = Port is selectively suspended.\r
+ * |[3] |POCI |Port over Current Indicator (Read) or Clear Port Suspend (Write)\r
+ * | | |This bit reflects the state of the over current status pin dedicated to this port\r
+ * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.\r
+ * | | |This bit is also used to initiate the selective result sequence for the port.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear port suspend.\r
+ * | | |Read Operation:\r
+ * | | |0 = No over current condition.\r
+ * | | |1 = Over current condition.\r
+ * |[4] |PRS |Port Reset Status\r
+ * | | |This bit reflects the reset state of the port.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Set port reset.\r
+ * | | |Read Operation\r
+ * | | |0 = Port reset signal is not active.\r
+ * | | |1 = Port reset signal is active.\r
+ * |[8] |PPS |Port Power Status\r
+ * | | |This bit reflects the power state of the port regardless of the power switching mode.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Port Power Enabled.\r
+ * | | |Read Operation:\r
+ * | | |0 = Port power is Disabled.\r
+ * | | |1 = Port power is Enabled.\r
+ * |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write)\r
+ * | | |This bit defines the speed (and bud idle) of the attached device\r
+ * | | |It is only valid when CCS (HcRhPortStatus[0]) is set.\r
+ * | | |This bit is also used to clear port power.\r
+ * | | |Write Operation:\r
+ * | | |0 = No effect.\r
+ * | | |1 = Clear PPS (HcRhPortStatus[8]).\r
+ * | | |Read Operation:\r
+ * | | |0 = Full Speed device.\r
+ * | | |1 = Low-speed device.\r
+ * |[16] |CSC |Connect Status Change\r
+ * | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus[0]) changed).\r
+ * | | |Write 1 to clear this bit to zero.\r
+ * | | |0 = No connect/disconnect event (CCS (HcRhPortStatus[0]) didn't change).\r
+ * | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus[0]) changed).\r
+ * |[17] |PESC |Port Enable Status Change\r
+ * | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus[1]) cleared) due to a hardware event.\r
+ * | | |Write 1 to clear this bit to zero.\r
+ * | | |0 = PES (HcRhPortStatus[1]) didn't change.\r
+ * | | |1 = PES (HcRhPortStatus[1]) changed.\r
+ * |[18] |PSSC |Port Suspend Status Change\r
+ * | | |This bit indicates the completion of the selective resume sequence for the port.\r
+ * | | |Write 1 to clear this bit to zero.\r
+ * | | |0 = Port resume is not completed.\r
+ * | | |1 = Port resume completed.\r
+ * |[19] |OCIC |Port over Current Indicator Change\r
+ * | | |This bit is set when POCI (HcRhPortStatus[3]) changes.\r
+ * | | |Write 1 to clear this bit to zero.\r
+ * | | |0 = POCI (HcRhPortStatus[3]) didn't change.\r
+ * | | |1 = POCI (HcRhPortStatus[3]) changes.\r
+ * |[20] |PRSC |Port Reset Status Change\r
+ * | | |This bit indicates that the port reset signal has completed.\r
+ * | | |Write 1 to clear this bit to zero.\r
+ * | | |0 = Port reset is not complete.\r
+ * | | |1 = Port reset is complete.\r
+ * @var USBH_T::HcPhyControl\r
+ * Offset: 0x200 Host Controller PHY Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[27] |STBYEN |USB Transceiver Standby Enable Bit\r
+ * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.\r
+ * | | |0 = The USB transceiver would never enter the standby mode.\r
+ * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).\r
+ * @var USBH_T::HcMiscControl\r
+ * Offset: 0x204 Host Controller Miscellaneous Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |ABORT |AHB Bus ERROR Response\r
+ * | | |This bit indicates there is an ERROR response received in AHB bus.\r
+ * | | |0 = No ERROR response received.\r
+ * | | |1 = ERROR response received.\r
+ * |[3] |OCAL |over Current Active Low\r
+ * | | |This bit controls the polarity of over current flag from external power IC.\r
+ * | | |0 = Over current flag is high active.\r
+ * | | |1 = Over current flag is low active.\r
+ * |[16] |DPRT1 |Disable Port 1\r
+ * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled\r
+ * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.\r
+ * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.\r
+ * | | |0 = The connection between USB host controller and transceiver of port 1 Enabled.\r
+ * | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode.\r
+ */\r
+ __I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */\r
+ __IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */\r
+ __IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */\r
+ __IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */\r
+ __IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */\r
+ __IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */\r
+ __IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */\r
+ __IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */\r
+ __IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */\r
+ __IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */\r
+ __IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */\r
+ __IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */\r
+ __IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */\r
+ __IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */\r
+ __I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */\r
+ __I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */\r
+ __IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */\r
+ __IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */\r
+ __IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */\r
+ __IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */\r
+ __IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */\r
+ __IO uint32_t HcRhPortStatus[2]; /*!< [0x0054] Host Controller Root Hub Port Status */\r
+ __I uint32_t RESERVE0[105];\r
+ __IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */\r
+ __IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */\r
+\r
+} USBH_T;\r
+\r
+/**\r
+ @addtogroup USBH_CONST USBH Bit Field Definition\r
+ Constant Definitions for USBH Controller\r
+@{ */\r
+\r
+#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */\r
+#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */\r
+\r
+#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */\r
+#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */\r
+\r
+#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */\r
+#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */\r
+\r
+#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */\r
+#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */\r
+\r
+#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */\r
+#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */\r
+\r
+#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */\r
+#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */\r
+\r
+#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */\r
+#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */\r
+\r
+#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */\r
+#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */\r
+\r
+#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */\r
+#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */\r
+\r
+#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */\r
+#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */\r
+\r
+#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */\r
+#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */\r
+\r
+#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */\r
+#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */\r
+\r
+#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/\r
+#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */\r
+\r
+#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */\r
+#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */\r
+\r
+#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */\r
+#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */\r
+\r
+#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/\r
+#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */\r
+\r
+#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/\r
+#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */\r
+\r
+#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */\r
+#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */\r
+\r
+#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/\r
+#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */\r
+\r
+#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */\r
+#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */\r
+\r
+#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */\r
+#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */\r
+\r
+#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/\r
+#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */\r
+\r
+#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/\r
+#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */\r
+\r
+#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/\r
+#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */\r
+\r
+#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/\r
+#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */\r
+\r
+#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/\r
+#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */\r
+\r
+#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/\r
+#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */\r
+\r
+#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/\r
+#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */\r
+\r
+#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/\r
+#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */\r
+\r
+#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/\r
+#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */\r
+\r
+#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/\r
+#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */\r
+\r
+#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */\r
+#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */\r
+\r
+#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/\r
+#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */\r
+\r
+#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */\r
+#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */\r
+\r
+#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/\r
+#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */\r
+\r
+#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */\r
+#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */\r
+\r
+#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */\r
+#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */\r
+\r
+#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */\r
+#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */\r
+\r
+#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */\r
+#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */\r
+\r
+#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */\r
+#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */\r
+\r
+#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */\r
+#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */\r
+\r
+#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */\r
+#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */\r
+\r
+#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */\r
+#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */\r
+\r
+#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */\r
+#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */\r
+\r
+#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */\r
+#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */\r
+\r
+#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */\r
+#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */\r
+\r
+#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */\r
+#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */\r
+\r
+#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */\r
+#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */\r
+\r
+#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */\r
+#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */\r
+\r
+#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */\r
+#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */\r
+\r
+#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */\r
+#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */\r
+\r
+#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */\r
+#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */\r
+\r
+#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */\r
+#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */\r
+\r
+#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */\r
+#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */\r
+\r
+#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */\r
+#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */\r
+\r
+#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */\r
+#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */\r
+\r
+#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */\r
+#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */\r
+\r
+#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus: CCS Position */\r
+#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus: CCS Mask */\r
+\r
+#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus: PES Position */\r
+#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus: PES Mask */\r
+\r
+#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus: PSS Position */\r
+#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus: PSS Mask */\r
+\r
+#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus: POCI Position */\r
+#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus: POCI Mask */\r
+\r
+#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus: PRS Position */\r
+#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus: PRS Mask */\r
+\r
+#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus: PPS Position */\r
+#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus: PPS Mask */\r
+\r
+#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus: LSDA Position */\r
+#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus: LSDA Mask */\r
+\r
+#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus: CSC Position */\r
+#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus: CSC Mask */\r
+\r
+#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus: PESC Position */\r
+#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus: PESC Mask */\r
+\r
+#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus: PSSC Position */\r
+#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus: PSSC Mask */\r
+\r
+#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus: OCIC Position */\r
+#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus: OCIC Mask */\r
+\r
+#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus: PRSC Position */\r
+#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus: PRSC Mask */\r
+\r
+#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */\r
+#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */\r
+\r
+#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */\r
+#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */\r
+\r
+#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */\r
+#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */\r
+\r
+#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */\r
+#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */\r
+\r
+/**@}*/ /* USBH_CONST */\r
+/**@}*/ /* end of USBH register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __USBH_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file uspi_reg.h\r
+ * @version V1.00\r
+ * @brief USPI register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __USPI_REG_H__\r
+#define __USPI_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- SPI Mode of USCI Controller -------------------------*/\r
+/**\r
+ @addtogroup USPI SPI Mode of USCI Controller(USPI)\r
+ Memory Mapped Structure for USPI Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var USPI_T::CTL\r
+ * Offset: 0x00 USCI Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |FUNMODE |Function Mode\r
+ * | | |This bit field selects the protocol for this USCI controller\r
+ * | | |Selecting a protocol that is not available or a reserved combination disables the USCI\r
+ * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol\r
+ * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\r
+ * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.\r
+ * | | |001 = The SPI protocol is selected.\r
+ * | | |010 = The UART protocol is selected.\r
+ * | | |100 = The I2C protocol is selected.\r
+ * | | |Note: Other bit combinations are reserved.\r
+ * @var USPI_T::INTEN\r
+ * Offset: 0x04 USCI Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit\r
+ * | | |This bit enables the interrupt generation in case of a transmit start event.\r
+ * | | |0 = The transmit start interrupt is disabled.\r
+ * | | |1 = The transmit start interrupt is enabled.\r
+ * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit\r
+ * | | |This bit enables the interrupt generation in case of a transmit finish event.\r
+ * | | |0 = The transmit finish interrupt is disabled.\r
+ * | | |1 = The transmit finish interrupt is enabled.\r
+ * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit\r
+ * | | |This bit enables the interrupt generation in case of a receive start event.\r
+ * | | |0 = The receive start interrupt is disabled.\r
+ * | | |1 = The receive start interrupt is enabled.\r
+ * |[4] |RXENDIEN |Receive End Interrupt Enable Bit\r
+ * | | |This bit enables the interrupt generation in case of a receive finish event.\r
+ * | | |0 = The receive end interrupt is disabled.\r
+ * | | |1 = The receive end interrupt is enabled.\r
+ * @var USPI_T::BRGEN\r
+ * Offset: 0x08 USCI Baud Rate Generator Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RCLKSEL |Reference Clock Source Selection\r
+ * | | |This bit selects the source of reference clock (fREF_CLK).\r
+ * | | |0 = Peripheral device clock fPCLK.\r
+ * | | |1 = Reserved.\r
+ * |[1] |PTCLKSEL |Protocol Clock Source Selection\r
+ * | | |This bit selects the source of protocol clock (fPROT_CLK).\r
+ * | | |0 = Reference clock fREF_CLK.\r
+ * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).\r
+ * |[3:2] |SPCLKSEL |Sample Clock Source Selection\r
+ * | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.\r
+ * | | |00 = fDIV_CLK.\r
+ * | | |01 = fPROT_CLK.\r
+ * | | |10 = fSCLK.\r
+ * | | |11 = fREF_CLK.\r
+ * |[4] |TMCNTEN |Time Measurement Counter Enable Bit\r
+ * | | |This bit enables the 10-bit timing measurement counter.\r
+ * | | |0 = Time measurement counter is Disabled.\r
+ * | | |1 = Time measurement counter is Enabled.\r
+ * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection\r
+ * | | |0 = Time measurement counter with fPROT_CLK.\r
+ * | | |1 = Time measurement counter with fDIV_CLK.\r
+ * |[25:16] |CLKDIV |Clock Divider\r
+ * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).\r
+ * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled\r
+ * | | |The revised value is the average bit time between bit 5 and bit 6\r
+ * | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate.\r
+ * @var USPI_T::DATIN0\r
+ * Offset: 0x10 USCI Input Data Signal Configuration Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SYNCSEL |Input Signal Synchronization Selection\r
+ * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\r
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.\r
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.\r
+ * | | |Note: In SPI protocol, we suggest this bit should be set as 0.\r
+ * |[2] |ININV |Input Signal Inverse Selection\r
+ * | | |This bit defines the inverter enable of the input asynchronous signal.\r
+ * | | |0 = The un-synchronized input signal will not be inverted.\r
+ * | | |1 = The un-synchronized input signal will be inverted.\r
+ * | | |Note: In SPI protocol, we suggest this bit should be set as 0.\r
+ * @var USPI_T::CTLIN0\r
+ * Offset: 0x20 USCI Input Control Signal Configuration Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SYNCSEL |Input Synchronization Signal Selection\r
+ * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\r
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.\r
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.\r
+ * | | |Note: In SPI protocol, we suggest this bit should be set as 0.\r
+ * |[2] |ININV |Input Signal Inverse Selection\r
+ * | | |This bit defines the inverter enable of the input asynchronous signal.\r
+ * | | |0 = The un-synchronized input signal will not be inverted.\r
+ * | | |1 = The un-synchronized input signal will be inverted.\r
+ * @var USPI_T::CLKIN\r
+ * Offset: 0x28 USCI Input Clock Signal Configuration Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SYNCSEL |Input Synchronization Signal Selection\r
+ * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\r
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.\r
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.\r
+ * | | |Note: In SPI protocol, we suggest this bit should be set as 0.\r
+ * @var USPI_T::LINECTL\r
+ * Offset: 0x2C USCI Line Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |LSB |LSB First Transmission Selection\r
+ * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.\r
+ * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.\r
+ * |[5] |DATOINV |Data Output Inverse Selection\r
+ * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.\r
+ * | | |0 = Data output level is not inverted.\r
+ * | | |1 = Data output level is inverted.\r
+ * |[7] |CTLOINV |Control Signal Output Inverse Selection\r
+ * | | |This bit defines the relation between the internal control signal and the output control signal.\r
+ * | | |0 = No effect.\r
+ * | | |1 = The control signal will be inverted before its output.\r
+ * | | |Note: The control signal has different definitions in different protocol\r
+ * | | |In SPI protocol, the control signal means slave select signal\r
+ * |[11:8] |DWIDTH |Word Length of Transmission\r
+ * | | |This bit field defines the data word length (amount of bits) for reception and transmission\r
+ * | | |The data word is always right-aligned in the data buffer\r
+ * | | |USCI support word length from 4 to 16 bits.\r
+ * | | |0x0: The data word contains 16 bits located at bit positions [15:0].\r
+ * | | |0x1: Reserved.\r
+ * | | |0x2: Reserved.\r
+ * | | |0x3: Reserved.\r
+ * | | |0x4: The data word contains 4 bits located at bit positions [3:0].\r
+ * | | |0x5: The data word contains 5 bits located at bit positions [4:0].\r
+ * | | |...\r
+ * | | |0xF: The data word contains 15 bits located at bit positions [14:0].\r
+ * @var USPI_T::TXDAT\r
+ * Offset: 0x30 USCI Transmit Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |TXDAT |Transmit Data\r
+ * | | |Software can use this bit field to write 16-bit transmit data for transmission\r
+ * | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.\r
+ * |[16] |PORTDIR |Port Direction Control\r
+ * | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer\r
+ * | | |It is used to define the direction of the data port pin\r
+ * | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously.\r
+ * | | |0 = The data pin is configured as output mode.\r
+ * | | |1 = The data pin is configured as input mode.\r
+ * @var USPI_T::RXDAT\r
+ * Offset: 0x34 USCI Receive Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |RXDAT |Received Data\r
+ * | | |This bit field monitors the received data which stored in receive data buffer.\r
+ * @var USPI_T::BUFCTL\r
+ * Offset: 0x38 USCI Transmit/Receive Buffer Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[6] |TXUDRIEN |Slave Transmit Under-run Interrupt Enable Bit\r
+ * | | |0 = Transmit under-run interrupt Disabled.\r
+ * | | |1 = Transmit under-run interrupt Enabled.\r
+ * |[7] |TXCLR |Clear Transmit Buffer\r
+ * | | |0 = No effect.\r
+ * | | |1 = The transmit buffer is cleared\r
+ * | | |Should only be used while the buffer is not taking part in data traffic.\r
+ * | | |Note: It is cleared automatically after one PCLK cycle.\r
+ * |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit\r
+ * | | |0 = Receive overrun interrupt Disabled.\r
+ * | | |1 = Receive overrun interrupt Enabled.\r
+ * |[15] |RXCLR |Clear Receive Buffer\r
+ * | | |0 = No effect.\r
+ * | | |1 = The receive buffer is cleared\r
+ * | | |Should only be used while the buffer is not taking part in data traffic.\r
+ * | | |Note: It is cleared automatically after one PCLK cycle.\r
+ * |[16] |TXRST |Transmit Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.\r
+ * | | |Note: It is cleared automatically after one PCLK cycle.\r
+ * |[17] |RXRST |Receive Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.\r
+ * | | |Note: It is cleared automatically after one PCLK cycle.\r
+ * @var USPI_T::BUFSTS\r
+ * Offset: 0x3C USCI Transmit/Receive Buffer Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RXEMPTY |Receive Buffer Empty Indicator\r
+ * | | |0 = Receive buffer is not empty.\r
+ * | | |1 = Receive buffer is empty.\r
+ * |[1] |RXFULL |Receive Buffer Full Indicator\r
+ * | | |0 = Receive buffer is not full.\r
+ * | | |1 = Receive buffer is full.\r
+ * |[3] |RXOVIF |Receive Buffer Overrun Interrupt Status\r
+ * | | |This bit indicates that a receive buffer overrun event has been detected\r
+ * | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated\r
+ * | | |It is cleared by software writes 1 to this bit.\r
+ * | | |0 = A receive buffer overrun event has not been detected.\r
+ * | | |1 = A receive buffer overrun event has been detected.\r
+ * |[8] |TXEMPTY |Transmit Buffer Empty Indicator\r
+ * | | |0 = Transmit buffer is not empty.\r
+ * | | |1 = Transmit buffer is empty and available for the next transmission datum.\r
+ * |[9] |TXFULL |Transmit Buffer Full Indicator\r
+ * | | |0 = Transmit buffer is not full.\r
+ * | | |1 = Transmit buffer is full.\r
+ * |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status\r
+ * | | |This bit indicates that a transmit buffer under-run event has been detected\r
+ * | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated\r
+ * | | |It is cleared by software writes 1 to this bit\r
+ * | | |0 = A transmit buffer under-run event has not been detected.\r
+ * | | |1 = A transmit buffer under-run event has been detected.\r
+ * @var USPI_T::PDMACTL\r
+ * Offset: 0x40 USCI PDMA Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PDMARST |PDMA Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.\r
+ * |[1] |TXPDMAEN |PDMA Transmit Channel Available\r
+ * | | |0 = Transmit PDMA function Disabled.\r
+ * | | |1 = Transmit PDMA function Enabled.\r
+ * |[2] |RXPDMAEN |PDMA Receive Channel Available\r
+ * | | |0 = Receive PDMA function Disabled.\r
+ * | | |1 = Receive PDMA function Enabled.\r
+ * |[3] |PDMAEN |PDMA Mode Enable Bit\r
+ * | | |0 = PDMA function Disabled.\r
+ * | | |1 = PDMA function Enabled.\r
+ * | | |Notice: The I2C is not supporting PDMA function.\r
+ * @var USPI_T::WKCTL\r
+ * Offset: 0x54 USCI Wake-up Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKEN |Wake-up Enable Bit\r
+ * | | |0 = Wake-up function Disabled.\r
+ * | | |1 = Wake-up function Enabled.\r
+ * |[1] |WKADDREN |Wake-up Address Match Enable Bit\r
+ * | | |0 = The chip is woken up according data toggle.\r
+ * | | |1 = The chip is woken up according address match.\r
+ * |[2] |PDBOPT |Power Down Blocking Option\r
+ * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.\r
+ * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.\r
+ * @var USPI_T::WKSTS\r
+ * Offset: 0x58 USCI Wake-up Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKF |Wake-up Flag\r
+ * | | |When chip is woken up from Power-down mode, this bit is set to 1\r
+ * | | |Software can write 1 to clear this bit.\r
+ * @var USPI_T::PROTCTL\r
+ * Offset: 0x5C USCI Protocol Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SLAVE |Slave Mode Selection\r
+ * | | |0 = Master mode.\r
+ * | | |1 = Slave mode.\r
+ * |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only)\r
+ * | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.\r
+ * | | |0 = 4-wire bi-direction interface.\r
+ * | | |1 = 3-wire bi-direction interface.\r
+ * |[2] |SS |Slave Select Control (Master Only)\r
+ * | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.\r
+ * | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal.\r
+ * | | |Note: In SPI protocol, the internal slave select signal is active high.\r
+ * |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only)\r
+ * | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit.\r
+ * | | |1 = Slave select signal will be generated automatically\r
+ * | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.\r
+ * |[7:6] |SCLKMODE |Serial Bus Clock Mode\r
+ * | | |This bit field defines the SCLK idle status, data transmit, and data receive edge.\r
+ * | | |MODE0 = The idle state of SPI clock is low level\r
+ * | | |Data is transmitted with falling edge and received with rising edge.\r
+ * | | |MODE1 = The idle state of SPI clock is low level\r
+ * | | |Data is transmitted with rising edge and received with falling edge.\r
+ * | | |MODE2 = The idle state of SPI clock is high level\r
+ * | | |Data is transmitted with rising edge and received with falling edge.\r
+ * | | |MODE3 = The idle state of SPI clock is high level\r
+ * | | |Data is transmitted with falling edge and received with rising edge.\r
+ * |[11:8] |SUSPITV |Suspend Interval (Master Only)\r
+ * | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer\r
+ * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word\r
+ * | | |The default value is 0x3\r
+ * | | |The period of the suspend interval is obtained according to the following equation.\r
+ * | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\r
+ * | | |Example:\r
+ * | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle.\r
+ * | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle.\r
+ * | | |.....\r
+ * | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle.\r
+ * | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle.\r
+ * |[14:12] |TSMSEL |Transmit Data Mode Selection\r
+ * | | |This bit field describes how receive and transmit data is shifted in and out.\r
+ * | | |TSMSEL = 000b: Full-duplex SPI.\r
+ * | | |TSMSEL = 100b: Half-duplex SPI.\r
+ * | | |Other values are reserved.\r
+ * | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.\r
+ * |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only)\r
+ * | | |In Slave mode, this bit field is used for Slave time-out period\r
+ * | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event\r
+ * | | |Writing 0x0 into this bit field will disable the Slave time-out function.\r
+ * | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.\r
+ * |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave)\r
+ * | | |This bit defines the transmitting data level when no data is available for transferring.\r
+ * | | |0 = The output data level is 0 if TX under-run event occurs.\r
+ * | | |1 = The output data level is 1 if TX under-run event occurs.\r
+ * |[31] |PROTEN |SPI Protocol Enable Bit\r
+ * | | |0 = SPI Protocol Disabled.\r
+ * | | |1 = SPI Protocol Enabled.\r
+ * @var USPI_T::PROTIEN\r
+ * Offset: 0x60 USCI Protocol Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Control\r
+ * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.\r
+ * | | |0 = Slave select inactive interrupt generation Disabled.\r
+ * | | |1 = Slave select inactive interrupt generation Enabled.\r
+ * |[1] |SSACTIEN |Slave Select Active Interrupt Enable Control\r
+ * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active.\r
+ * | | |0 = Slave select active interrupt generation Disabled.\r
+ * | | |1 = Slave select active interrupt generation Enabled.\r
+ * |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Control\r
+ * | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.\r
+ * | | |0 = The Slave time-out interrupt Disabled.\r
+ * | | |1 = The Slave time-out interrupt Enabled.\r
+ * |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Control\r
+ * | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])\r
+ * | | |Bit count error event occurs.\r
+ * | | |0 = The Slave mode bit count error interrupt Disabled.\r
+ * | | |1 = The Slave mode bit count error interrupt Enabled.\r
+ * @var USPI_T::PROTSTS\r
+ * Offset: 0x64 USCI Protocol Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |TXSTIF |Transmit Start Interrupt Flag\r
+ * | | |0 = Transmit start event does not occur.\r
+ * | | |1 = Transmit start event occurs.\r
+ * | | |Note: It is cleared by software writes 1 to this bit\r
+ * |[2] |TXENDIF |Transmit End Interrupt Flag\r
+ * | | |0 = Transmit end event does not occur.\r
+ * | | |1 = Transmit end event occurs.\r
+ * | | |Note: It is cleared by software writes 1 to this bit\r
+ * |[3] |RXSTIF |Receive Start Interrupt Flag\r
+ * | | |0 = Receive start event does not occur.\r
+ * | | |1 = Receive start event occurs.\r
+ * | | |Note: It is cleared by software writes 1 to this bit\r
+ * |[4] |RXENDIF |Receive End Interrupt Flag\r
+ * | | |0 = Receive end event does not occur.\r
+ * | | |1 = Receive end event occurs.\r
+ * | | |Note: It is cleared by software writes 1 to this bit\r
+ * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only)\r
+ * | | |0 = Slave time-out event does not occur.\r
+ * | | |1 = Slave time-out event occurs.\r
+ * | | |Note: It is cleared by software writes 1 to this bit\r
+ * |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only)\r
+ * | | |0 = Slave bit count error event does not occur.\r
+ * | | |1 = Slave bit count error event occurs.\r
+ * | | |Note: It is cleared by software writes 1 to this bit.\r
+ * |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only)\r
+ * | | |This bit indicates that the internal slave select signal has changed to inactive\r
+ * | | |It is cleared by software writes 1 to this bit\r
+ * | | |0 = The slave select signal has not changed to inactive.\r
+ * | | |1 = The slave select signal has changed to inactive.\r
+ * | | |Note: The internal slave select signal is active high.\r
+ * |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only)\r
+ * | | |This bit indicates that the internal slave select signal has changed to active\r
+ * | | |It is cleared by software writes one to this bit\r
+ * | | |0 = The slave select signal has not changed to active.\r
+ * | | |1 = The slave select signal has changed to active.\r
+ * | | |Note: The internal slave select signal is active high.\r
+ * |[16] |SSLINE |Slave Select Line Bus Status (Read Only)\r
+ * | | |This bit is only available in Slave mode\r
+ * | | |It used to monitor the current status of the input slave select signal on the bus.\r
+ * | | |0 = The slave select line status is 0.\r
+ * | | |1 = The slave select line status is 1.\r
+ * |[17] |BUSY |Busy Status (Read Only)\r
+ * | | |0 = SPI is in idle state.\r
+ * | | |1 = SPI is in busy state.\r
+ * | | |The following listing are the bus busy conditions:\r
+ * | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0.\r
+ * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.\r
+ * | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active.\r
+ * | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.\r
+ * |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only)\r
+ * | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1\r
+ * | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.\r
+ * | | |0 = Slave transmit under-run event does not occur.\r
+ * | | |1 = Slave transmit under-run event occurs.\r
+ */\r
+ __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */\r
+ __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */\r
+ __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */\r
+ __I uint32_t RESERVE0[1];\r
+ __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */\r
+ __I uint32_t RESERVE1[3];\r
+ __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */\r
+ __I uint32_t RESERVE2[1];\r
+ __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */\r
+ __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */\r
+ __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */\r
+ __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */\r
+ __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */\r
+ __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */\r
+ __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */\r
+ __I uint32_t RESERVE3[4];\r
+ __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */\r
+ __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */\r
+ __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */\r
+ __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */\r
+ __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */\r
+\r
+} USPI_T;\r
+\r
+/**\r
+ @addtogroup USPI_CONST USPI Bit Field Definition\r
+ Constant Definitions for USPI Controller\r
+@{ */\r
+\r
+#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */\r
+#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */\r
+\r
+#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */\r
+#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */\r
+\r
+#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */\r
+#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */\r
+\r
+#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */\r
+#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */\r
+\r
+#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */\r
+#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */\r
+\r
+#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */\r
+#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */\r
+\r
+#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */\r
+#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */\r
+\r
+#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */\r
+#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */\r
+\r
+#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */\r
+#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */\r
+\r
+#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */\r
+#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */\r
+\r
+#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */\r
+#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */\r
+\r
+#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */\r
+#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */\r
+\r
+#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */\r
+#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */\r
+\r
+#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */\r
+#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */\r
+\r
+#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */\r
+#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */\r
+\r
+#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */\r
+#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */\r
+\r
+#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */\r
+#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */\r
+\r
+#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */\r
+#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */\r
+\r
+#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */\r
+#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */\r
+\r
+#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */\r
+#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */\r
+\r
+#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */\r
+#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */\r
+\r
+#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */\r
+#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */\r
+\r
+#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */\r
+#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */\r
+\r
+#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */\r
+#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */\r
+\r
+#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */\r
+#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */\r
+\r
+#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */\r
+#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */\r
+\r
+#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */\r
+#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */\r
+\r
+#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */\r
+#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */\r
+\r
+#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */\r
+#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */\r
+\r
+#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */\r
+#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */\r
+\r
+#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */\r
+#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */\r
+\r
+#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */\r
+#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */\r
+\r
+#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */\r
+#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */\r
+\r
+#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */\r
+#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */\r
+\r
+#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */\r
+#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */\r
+\r
+#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */\r
+#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */\r
+\r
+#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */\r
+#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */\r
+\r
+#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */\r
+#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */\r
+\r
+#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */\r
+#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */\r
+\r
+#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */\r
+#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */\r
+\r
+#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */\r
+#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */\r
+\r
+#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */\r
+#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */\r
+\r
+#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */\r
+#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */\r
+\r
+#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */\r
+#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */\r
+\r
+#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */\r
+#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */\r
+\r
+#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */\r
+#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */\r
+\r
+#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */\r
+#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */\r
+\r
+#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */\r
+#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */\r
+\r
+#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */\r
+#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */\r
+\r
+#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */\r
+#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */\r
+\r
+#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */\r
+#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */\r
+\r
+#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */\r
+#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */\r
+\r
+#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */\r
+#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */\r
+\r
+#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */\r
+#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */\r
+\r
+#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */\r
+#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */\r
+\r
+#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */\r
+#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */\r
+\r
+#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */\r
+#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */\r
+\r
+#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */\r
+#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */\r
+\r
+#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */\r
+#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */\r
+\r
+#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */\r
+#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */\r
+\r
+#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */\r
+#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */\r
+\r
+#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */\r
+#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */\r
+\r
+#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */\r
+#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */\r
+\r
+#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */\r
+#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */\r
+\r
+#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */\r
+#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */\r
+\r
+#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */\r
+#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */\r
+\r
+#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */\r
+#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */\r
+\r
+#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */\r
+#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */\r
+\r
+/**@}*/ /* USPI_CONST */\r
+/**@}*/ /* end of USPI register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __USPI_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file uuart_reg.h\r
+ * @version V1.00\r
+ * @brief UUART register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __UUART_REG_H__\r
+#define __UUART_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- UART Mode of USCI Controller -------------------------*/\r
+/**\r
+ @addtogroup UUART UART Mode of USCI Controller(UUART)\r
+ Memory Mapped Structure for UUART Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var UUART_T::CTL\r
+ * Offset: 0x00 USCI Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |FUNMODE |Function Mode\r
+ * | | |This bit field selects the protocol for this USCI controller.\r
+ * | | |Selecting a protocol that is not available or a reserved combination disables the USCI.\r
+ * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol.\r
+ * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\r
+ * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.\r
+ * | | |001 = The SPI protocol is selected.\r
+ * | | |010 = The UART protocol is selected.\r
+ * | | |100 = The I2C protocol is selected.\r
+ * | | |Others = Reserved.\r
+ * @var UUART_T::INTEN\r
+ * Offset: 0x04 USCI Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit\r
+ * | | |This bit enables the interrupt generation in case of a transmit start event.\r
+ * | | |0 = The transmit start interrupt is disabled.\r
+ * | | |1 = The transmit start interrupt is enabled.\r
+ * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit\r
+ * | | |This bit enables the interrupt generation in case of a transmit finish event.\r
+ * | | |0 = The transmit finish interrupt is disabled.\r
+ * | | |1 = The transmit finish interrupt is enabled.\r
+ * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit\r
+ * | | |This bit enables the interrupt generation in case of a receive start event.\r
+ * | | |0 = The receive start interrupt is disabled.\r
+ * | | |1 = The receive start interrupt is enabled.\r
+ * |[4] |RXENDIEN |Receive End Interrupt Enable Bit\r
+ * | | |This bit enables the interrupt generation in case of a receive finish event.\r
+ * | | |0 = The receive end interrupt is disabled.\r
+ * | | |1 = The receive end interrupt is enabled.\r
+ * @var UUART_T::BRGEN\r
+ * Offset: 0x08 USCI Baud Rate Generator Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RCLKSEL |Reference Clock Source Selection\r
+ * | | |This bit selects the source signal of reference clock (fREF_CLK).\r
+ * | | |0 = Peripheral device clock fPCLK.\r
+ * | | |1 = Reserved.\r
+ * |[1] |PTCLKSEL |Protocol Clock Source Selection\r
+ * | | |This bit selects the source signal of protocol clock (fPROT_CLK).\r
+ * | | |0 = Reference clock fREF_CLK.\r
+ * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).\r
+ * |[3:2] |SPCLKSEL |Sample Clock Source Selection\r
+ * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.\r
+ * | | |00 = fSAMP_CLK frequency is fDIV_CLK.\r
+ * | | |01 = fSAMP_CLK frequency is from fPROT_CLK.\r
+ * | | |10 = fSAMP_CLK frequency is from fSCLK.\r
+ * | | |11 = fSAMP_CLK frequency is from fREF_CLK.\r
+ * |[4] |TMCNTEN |Timing Measurement Counter Enable Bit\r
+ * | | |This bit enables the 10-bit timing measurement counter.\r
+ * | | |0 = Timing measurement counter is Disabled.\r
+ * | | |1 = Timing measurement counter is Enabled.\r
+ * |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection\r
+ * | | |0 = Timing measurement counter with fPROT_CLK.\r
+ * | | |1 = Timing measurement counter with fDIV_CLK.\r
+ * |[9:8] |PDSCNT |Pre-divider for Sample Counter\r
+ * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK.\r
+ * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).\r
+ * |[14:10] |DSCNT |Denominator for Sample Counter\r
+ * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.\r
+ * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).\r
+ * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.\r
+ * |[25:16] |CLKDIV |Clock Divider\r
+ * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).\r
+ * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled.\r
+ * | | |The revised value is the average bit time between bit 5 and bit 6.\r
+ * | | |The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.\r
+ * @var UUART_T::DATIN0\r
+ * Offset: 0x10 USCI Input Data Signal Configuration Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SYNCSEL |Input Signal Synchronization Selection\r
+ * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\r
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.\r
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.\r
+ * |[2] |ININV |Input Signal Inverse Selection\r
+ * | | |This bit defines the inverter enable of the input asynchronous signal.\r
+ * | | |0 = The un-synchronized input signal will not be inverted.\r
+ * | | |1 = The un-synchronized input signal will be inverted.\r
+ * |[4:3] |EDGEDET |Input Signal Edge Detection Mode\r
+ * | | |This bit field selects which edge actives the trigger event of input data signal.\r
+ * | | |00 = The trigger event activation is disabled.\r
+ * | | |01 = A rising edge activates the trigger event of input data signal.\r
+ * | | |10 = A falling edge activates the trigger event of input data signal.\r
+ * | | |11 = Both edges activate the trigger event of input data signal.\r
+ * | | |Note: In UART function mode, it is suggested to set this bit field as 10.\r
+ * @var UUART_T::CTLIN0\r
+ * Offset: 0x20 USCI Input Control Signal Configuration Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SYNCSEL |Input Synchronization Signal Selection\r
+ * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\r
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.\r
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.\r
+ * |[2] |ININV |Input Signal Inverse Selection\r
+ * | | |This bit defines the inverter enable of the input asynchronous signal.\r
+ * | | |0 = The un-synchronized input signal will not be inverted.\r
+ * | | |1 = The un-synchronized input signal will be inverted.\r
+ * @var UUART_T::CLKIN\r
+ * Offset: 0x28 USCI Input Clock Signal Configuration Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SYNCSEL |Input Synchronization Signal Selection\r
+ * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\r
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.\r
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.\r
+ * @var UUART_T::LINECTL\r
+ * Offset: 0x2C USCI Line Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |LSB |LSB First Transmission Selection\r
+ * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.\r
+ * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.\r
+ * |[5] |DATOINV |Data Output Inverse Selection\r
+ * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.\r
+ * | | |0 = The value of USCIx_DAT1 is equal to the data shift register.\r
+ * | | |1 = The value of USCIx_DAT1 is the inversion of data shift register.\r
+ * |[7] |CTLOINV |Control Signal Output Inverse Selection\r
+ * | | |This bit defines the relation between the internal control signal and the output control signal.\r
+ * | | |0 = No effect.\r
+ * | | |1 = The control signal will be inverted before its output.\r
+ * | | |Note: In UART protocol, the control signal means nRTS signal.\r
+ * |[11:8] |DWIDTH |Word Length of Transmission\r
+ * | | |This bit field defines the data word length (amount of bits) for reception and transmission\r
+ * | | |The data word is always right-aligned in the data buffer\r
+ * | | |USCI support word length from 4 to 16 bits.\r
+ * | | |0x0 = The data word contains 16 bits located at bit positions [15:0].\r
+ * | | |0x1 = Reserved.\r
+ * | | |0x2 = Reserved.\r
+ * | | |0x3 = Reserved.\r
+ * | | |0x4 = The data word contains 4 bits located at bit positions [3:0].\r
+ * | | |0x5 = The data word contains 5 bits located at bit positions [4:0].\r
+ * | | |...\r
+ * | | |0xF = The data word contains 15 bits located at bit positions [14:0].\r
+ * | | |Note: In UART protocol, the length can be configured as 6~13 bits.\r
+ * @var UUART_T::TXDAT\r
+ * Offset: 0x30 USCI Transmit Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |TXDAT |Transmit Data\r
+ * | | |Software can use this bit field to write 16-bit transmit data for transmission.\r
+ * @var UUART_T::RXDAT\r
+ * Offset: 0x34 USCI Receive Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |RXDAT |Received Data\r
+ * | | |This bit field monitors the received data which stored in receive data buffer.\r
+ * | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).\r
+ * @var UUART_T::BUFCTL\r
+ * Offset: 0x38 USCI Transmit/Receive Buffer Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7] |TXCLR |Clear Transmit Buffer\r
+ * | | |0 = No effect.\r
+ * | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value).\r
+ * | | |Should only be used while the buffer is not taking part in data traffic.\r
+ * | | |Note: It is cleared automatically after one PCLK cycle.\r
+ * |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control\r
+ * | | |0 = Receive overrun interrupt Disabled.\r
+ * | | |1 = Receive overrun interrupt Enabled.\r
+ * |[15] |RXCLR |Clear Receive Buffer\r
+ * | | |0 = No effect.\r
+ * | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value).\r
+ * | | |Should only be used while the buffer is not taking part in data traffic.\r
+ * | | |Note: It is cleared automatically after one PCLK cycle.\r
+ * |[16] |TXRST |Transmit Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.\r
+ * | | |Note: It is cleared automatically after one PCLK cycle.\r
+ * |[17] |RXRST |Receive Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.\r
+ * | | |Note1: It is cleared automatically after one PCLK cycle.\r
+ * | | |Note2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.\r
+ * @var UUART_T::BUFSTS\r
+ * Offset: 0x3C USCI Transmit/Receive Buffer Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RXEMPTY |Receive Buffer Empty Indicator\r
+ * | | |0 = Receive buffer is not empty.\r
+ * | | |1 = Receive buffer is empty.\r
+ * |[1] |RXFULL |Receive Buffer Full Indicator\r
+ * | | |0 = Receive buffer is not full.\r
+ * | | |1 = Receive buffer is full.\r
+ * |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status\r
+ * | | |This bit indicates that a receive buffer overrun error event has been detected.\r
+ * | | |If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated.\r
+ * | | |It is cleared by software writes 1 to this bit.\r
+ * | | |0 = A receive buffer overrun error event has not been detected.\r
+ * | | |1 = A receive buffer overrun error event has been detected.\r
+ * |[8] |TXEMPTY |Transmit Buffer Empty Indicator\r
+ * | | |0 = Transmit buffer is not empty.\r
+ * | | |1 = Transmit buffer is empty.\r
+ * |[9] |TXFULL |Transmit Buffer Full Indicator\r
+ * | | |0 = Transmit buffer is not full.\r
+ * | | |1 = Transmit buffer is full.\r
+ * @var UUART_T::PDMACTL\r
+ * Offset: 0x40 USCI PDMA Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PDMARST |PDMA Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the USCI PDMA control logic. This bit will be cleared to 0 automatically.\r
+ * |[1] |TXPDMAEN |PDMA Transmit Channel Available\r
+ * | | |0 = Transmit PDMA function Disabled.\r
+ * | | |1 = Transmit PDMA function Enabled.\r
+ * |[2] |RXPDMAEN |PDMA Receive Channel Available\r
+ * | | |0 = Receive PDMA function Disabled.\r
+ * | | |1 = Receive PDMA function Enabled.\r
+ * |[3] |PDMAEN |PDMA Mode Enable Bit\r
+ * | | |0 = PDMA function Disabled.\r
+ * | | |1 = PDMA function Enabled.\r
+ * @var UUART_T::WKCTL\r
+ * Offset: 0x54 USCI Wake-up Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKEN |Wake-up Enable Bit\r
+ * | | |0 = Wake-up function Disabled.\r
+ * | | |1 = Wake-up function Enabled.\r
+ * |[2] |PDBOPT |Power Down Blocking Option\r
+ * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.\r
+ * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.\r
+ * @var UUART_T::WKSTS\r
+ * Offset: 0x58 USCI Wake-up Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKF |Wake-up Flag\r
+ * | | |When chip is woken up from Power-down mode, this bit is set to 1\r
+ * | | |Software can write 1 to clear this bit.\r
+ * @var UUART_T::PROTCTL\r
+ * Offset: 0x5C USCI Protocol Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |STOPB |Stop Bits\r
+ * | | |This bit defines the number of stop bits in an UART frame.\r
+ * | | |0 = The number of stop bits is 1.\r
+ * | | |1 = The number of stop bits is 2.\r
+ * |[1] |PARITYEN |Parity Enable Bit\r
+ * | | |This bit defines the parity bit is enabled in an UART frame.\r
+ * | | |0 = The parity bit Disabled.\r
+ * | | |1 = The parity bit Enabled.\r
+ * |[2] |EVENPARITY|Even Parity Enable Bit\r
+ * | | |0 = Odd number of logic 1's is transmitted and checked in each word.\r
+ * | | |1 = Even number of logic 1's is transmitted and checked in each word.\r
+ * | | |Note: This bit has effect only when PARITYEN is set.\r
+ * |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit\r
+ * | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (UUART_BUFSTS[1] = 1)), the UART will de-assert nRTS signal.\r
+ * | | |0 = nRTS auto-flow control Disabled.\r
+ * | | |1 = nRTS auto-flow control Enabled.\r
+ * | | |Note: This bit has effect only when the RTSAUDIREN is not set.\r
+ * |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit\r
+ * | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).\r
+ * | | |0 = nCTS auto-flow control Disabled.\r
+ * | | |1 = nCTS auto-flow control Enabled.\r
+ * |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit\r
+ * | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the nRTS signal is inactive.\r
+ * | | |0 = nRTS auto direction control Disabled.\r
+ * | | |1 = nRTS auto direction control Enabled.\r
+ * | | |Note1: This bit is used for nRTS auto direction control for RS485.\r
+ * | | |Note2: This bit has effect only when the RTSAUTOEN is not set.\r
+ * |[6] |ABREN |Auto-baud Rate Detect Enable Bit\r
+ * | | |0 = Auto-baud rate detect function Disabled.\r
+ * | | |1 = Auto-baud rate detect function Enabled.\r
+ * | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit.\r
+ * | | |The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).\r
+ * |[9] |DATWKEN |Data Wake-up Mode Enable Bit\r
+ * | | |0 = Data wake-up mode Disabled.\r
+ * | | |1 = Data wake-up mode Enabled.\r
+ * |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit\r
+ * | | |0 = nCTS wake-up mode Disabled.\r
+ * | | |1 = nCTS wake-up mode Enabled.\r
+ * |[14:11] |WAKECNT |Wake-up Counter\r
+ * | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\r
+ * |[24:16] |BRDETITV |Baud Rate Detection Interval\r
+ * | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits.\r
+ * | | |The order of the bus shall be 1 and 0 step by step (e.g\r
+ * | | |the input data pattern shall be 0x55)\r
+ * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.\r
+ * | | |Note: This bit can be cleared to 0 by software writing 1 to the BRDETITV.\r
+ * |[26] |STICKEN |Stick Parity Enable Bit\r
+ * | | |0 = Stick parity Disabled.\r
+ * | | |1 = Stick parity Enabled.\r
+ * | | |Note: Refer to RS-485 Support section for detail information.\r
+ * |[29] |BCEN |Transmit Break Control Enable Bit\r
+ * | | |0 = Transmit Break Control Disabled.\r
+ * | | |1 = Transmit Break Control Enabled.\r
+ * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).\r
+ * | | |This bit acts only on TX line and has no effect on the transmitter logic.\r
+ * |[31] |PROTEN |UART Protocol Enable Bit\r
+ * | | |0 = UART Protocol Disabled.\r
+ * | | |1 = UART Protocol Enabled.\r
+ * @var UUART_T::PROTIEN\r
+ * Offset: 0x60 USCI Protocol Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit\r
+ * | | |0 = Auto-baud rate interrupt Disabled.\r
+ * | | |1 = Auto-baud rate interrupt Enabled.\r
+ * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit\r
+ * | | |0 = Receive line status interrupt Disabled.\r
+ * | | |1 = Receive line status interrupt Enabled.\r
+ * | | |Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.\r
+ * @var UUART_T::PROTSTS\r
+ * Offset: 0x64 USCI Protocol Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |TXSTIF |Transmit Start Interrupt Flag\r
+ * | | |0 = A transmit start interrupt status has not occurred.\r
+ * | | |1 = A transmit start interrupt status has occurred.\r
+ * | | |Note1: It is cleared by software writing one into this bit.\r
+ * | | |Note2: Used for user to load next transmit data when there is no data in transmit buffer.\r
+ * |[2] |TXENDIF |Transmit End Interrupt Flag\r
+ * | | |0 = A transmit end interrupt status has not occurred.\r
+ * | | |1 = A transmit end interrupt status has occurred.\r
+ * | | |Note: It is cleared by software writing one into this bit.\r
+ * |[3] |RXSTIF |Receive Start Interrupt Flag\r
+ * | | |0 = A receive start interrupt status has not occurred.\r
+ * | | |1 = A receive start interrupt status has occurred.\r
+ * | | |Note: It is cleared by software writing one into this bit.\r
+ * |[4] |RXENDIF |Receive End Interrupt Flag\r
+ * | | |0 = A receive finish interrupt status has not occurred.\r
+ * | | |1 = A receive finish interrupt status has occurred.\r
+ * | | |Note: It is cleared by software writing one into this bit.\r
+ * |[5] |PARITYERR |Parity Error Flag\r
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit.\r
+ * | | |0 = No parity error is generated.\r
+ * | | |1 = Parity error is generated.\r
+ * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits.\r
+ * |[6] |FRMERR |Framing Error Flag\r
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\r
+ * | | |0 = No framing error is generated.\r
+ * | | |1 = Framing error is generated.\r
+ * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits.\r
+ * |[7] |BREAK |Break Flag\r
+ * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).\r
+ * | | |0 = No Break is generated.\r
+ * | | |1 = Break is generated in the receiver bus.\r
+ * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits.\r
+ * |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag\r
+ * | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data.\r
+ * | | |If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated.\r
+ * | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.\r
+ * | | |0 = Auto-baud rate detect function is not done.\r
+ * | | |1 = One Bit auto-baud rate detect function is done.\r
+ * | | |Note: This bit can be cleared by writing 1 to it.\r
+ * |[10] |RXBUSY |RX Bus Status Flag (Read Only)\r
+ * | | |This bit indicates the busy status of the receiver.\r
+ * | | |0 = The receiver is Idle.\r
+ * | | |1 = The receiver is BUSY.\r
+ * |[11] |ABERRSTS |Auto-baud Rate Error Status\r
+ * | | |This bit is set when auto-baud rate detection counter overrun.\r
+ * | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\r
+ * | | |0 = Auto-baud rate detect counter is not overrun.\r
+ * | | |1 = Auto-baud rate detect counter is overrun.\r
+ * | | |Note1: This bit is set at the same time of ABRDETIF.\r
+ * | | |Note2: This bit can be cleared by writing 1 to ABRDETIF or ABERRSTS.\r
+ * |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only)\r
+ * | | |This bit used to indicate the current status of the internal synchronized nCTS signal.\r
+ * | | |0 = The internal synchronized nCTS is low.\r
+ * | | |1 = The internal synchronized nCTS is high.\r
+ * |[17] |CTSLV |nCTS Pin Status (Read Only)\r
+ * | | |This bit used to monitor the current status of nCTS pin input.\r
+ * | | |0 = nCTS pin input is low level voltage logic state.\r
+ * | | |1 = nCTS pin input is high level voltage logic state.\r
+ */\r
+\r
+ __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */\r
+ __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */\r
+ __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */\r
+ __I uint32_t RESERVE0[1];\r
+ __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */\r
+ __I uint32_t RESERVE1[3];\r
+ __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */\r
+ __I uint32_t RESERVE2[1];\r
+ __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */\r
+ __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */\r
+ __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */\r
+ __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */\r
+ __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */\r
+ __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */\r
+ __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */\r
+ __I uint32_t RESERVE3[4];\r
+ __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */\r
+ __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */\r
+ __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */\r
+ __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */\r
+ __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */\r
+\r
+} UUART_T;\r
+\r
+/**\r
+ @addtogroup UUART_CONST UUART Bit Field Definition\r
+ Constant Definitions for UUART Controller\r
+@{ */\r
+\r
+#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */\r
+#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */\r
+\r
+#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */\r
+#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */\r
+\r
+#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */\r
+#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */\r
+\r
+#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */\r
+#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */\r
+\r
+#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */\r
+#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */\r
+\r
+#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */\r
+#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */\r
+\r
+#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */\r
+#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */\r
+\r
+#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */\r
+#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */\r
+\r
+#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */\r
+#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */\r
+\r
+#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */\r
+#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */\r
+\r
+#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */\r
+#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */\r
+\r
+#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */\r
+#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */\r
+\r
+#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */\r
+#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */\r
+\r
+#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */\r
+#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */\r
+\r
+#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */\r
+#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */\r
+\r
+#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */\r
+#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */\r
+\r
+#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */\r
+#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */\r
+\r
+#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */\r
+#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */\r
+\r
+#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */\r
+#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */\r
+\r
+#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */\r
+#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */\r
+\r
+#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */\r
+#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */\r
+\r
+#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */\r
+#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */\r
+\r
+#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */\r
+#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */\r
+\r
+#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */\r
+#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */\r
+\r
+#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */\r
+#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */\r
+\r
+#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */\r
+#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */\r
+\r
+#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */\r
+#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */\r
+\r
+#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */\r
+#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */\r
+\r
+#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */\r
+#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */\r
+\r
+#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */\r
+#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */\r
+\r
+#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */\r
+#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */\r
+\r
+#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */\r
+#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */\r
+\r
+#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */\r
+#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */\r
+\r
+#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */\r
+#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */\r
+\r
+#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */\r
+#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */\r
+\r
+#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */\r
+#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */\r
+\r
+#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */\r
+#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */\r
+\r
+#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */\r
+#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */\r
+\r
+#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */\r
+#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */\r
+\r
+#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */\r
+#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */\r
+\r
+#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */\r
+#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */\r
+\r
+#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */\r
+#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */\r
+\r
+#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */\r
+#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */\r
+\r
+#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */\r
+#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */\r
+\r
+#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */\r
+#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */\r
+\r
+#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */\r
+#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */\r
+\r
+#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */\r
+#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */\r
+\r
+#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */\r
+#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */\r
+\r
+#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */\r
+#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */\r
+\r
+#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */\r
+#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */\r
+\r
+#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */\r
+#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */\r
+\r
+#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */\r
+#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */\r
+\r
+#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */\r
+#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */\r
+\r
+#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */\r
+#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */\r
+\r
+#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */\r
+#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */\r
+\r
+#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */\r
+#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */\r
+\r
+#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */\r
+#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */\r
+\r
+#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */\r
+#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */\r
+\r
+#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */\r
+#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */\r
+\r
+#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */\r
+#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */\r
+\r
+#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */\r
+#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */\r
+\r
+#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */\r
+#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */\r
+\r
+#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */\r
+#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */\r
+\r
+#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */\r
+#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */\r
+\r
+#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */\r
+#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */\r
+\r
+#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */\r
+#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */\r
+\r
+#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */\r
+#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */\r
+\r
+#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */\r
+#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */\r
+\r
+#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */\r
+#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */\r
+\r
+#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */\r
+#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */\r
+\r
+/**@}*/ /* UUART_CONST */\r
+/**@}*/ /* end of UUART register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __UUART_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file wdt_reg.h\r
+ * @version V1.00\r
+ * @brief WDT register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __WDT_REG_H__\r
+#define __WDT_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- Watch Dog Timer Controller -------------------------*/\r
+/**\r
+ @addtogroup WDT Watch Dog Timer Controller(WDT)\r
+ Memory Mapped Structure for WDT Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var WDT_T::CTL\r
+ * Offset: 0x00 WDT Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect)\r
+ * | | |Setting this bit will enable the WDT time-out reset system function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\r
+ * | | |0 = WDT time-out reset system function Disabled.\r
+ * | | |1 = WDT time-out reset system function Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[2] |RSTF |WDT Time-out Reset Flag\r
+ * | | |This bit indicates the system has been reset by WDT time-out reset system event or not.\r
+ * | | |0 = WDT time-out reset system event did not occur.\r
+ * | | |1 = WDT time-out reset system event has been occurred.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[3] |IF |WDT Time-out Interrupt Flag\r
+ * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\r
+ * | | |0 = WDT time-out interrupt event interrupt did not occur.\r
+ * | | |1 = WDT time-out interrupt interrupt event occurred.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect)\r
+ * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a event to trigger CPU wake-up trigger event to chip.\r
+ * | | |0 = Trigger wWake-up trigger event function Disabled if WDT time-out interrupt signal generated.\r
+ * | | |1 = Trigger Wake-up trigger event function Enabled if WDT time-out interrupt signal generated.\r
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * | | |Note2: Chip can be woken-up by while WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz (LIRC (10 kHz) or LXT (32 kHz).\r
+ * |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect)\r
+ * | | |This bit indicates the WDT time-out event has triggered interrupt chip wake-up or not.flag status of WDT\r
+ * | | |0 = WDT does not cause chip wake-up.\r
+ * | | |1 = Chip wake-up from Idle or Power-down mode if when WDT time-out interrupt signal is generated.\r
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * | | |Note2: This bit is cleared by writing 1 to it.\r
+ * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect)\r
+ * | | |If this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and the WDT time-out interrupt signal is generated and inform to CPU.\r
+ * | | |0 = WDT time-out interrupt Disabled.\r
+ * | | |1 = WDT time-out interrupt Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[7] |WDTEN |WDT Enable Control (Write Protect)\r
+ * | | |0 = Set WDT counter stop Disabled, and (This action will reset the internal up counter value will be reset also).\r
+ * | | |1 = Set WDT counter start Enabled.\r
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * | | |Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enable/disable command is completed or not.\r
+ * | | |Note32: If CWDTEN[2:0] (combined by with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0.\r
+ * | | |Note3: This bit disabled needs 2 * WDT_CLK.\r
+ * |[10:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect)\r
+ * | | |These three bits select the time-out interval period after for the WDT starts counting.\r
+ * | | |000 = 24 * WDT_CLK.\r
+ * | | |001 = 26 * WDT_CLK.\r
+ * | | |010 = 28 * WDT_CLK.\r
+ * | | |011 = 210 * WDT_CLK.\r
+ * | | |100 = 212 * WDT_CLK.\r
+ * | | |101 = 214 * WDT_CLK.\r
+ * | | |110 = 216 * WDT_CLK.\r
+ * | | |111 = 218 * WDT_CLK.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[30] |SYNC |WDT Enable Control SYNC SYNC Flag Indicator (Read Only)\r
+ * | | |If use to synchronization, software er can check execute enable/disable this flag after enable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is become completed or not active or not..\r
+ * | | |SYNC delay is\r
+ * | | |0 = Set WDTEN bit is WDT enable control synccompletedhronizing is completion.\r
+ * | | |1 = Set WDTEN bit WDT enable control is synchronizing and not become active yet..\r
+ * | | |Note: Perform enable or disable WDTEN bit\r
+ * | | |This bit enabled needs 2 * WDT_CLK period to become active.\r
+ * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)\r
+ * | | |0 = ICE debug mode acknowledgment affects WDT counting.\r
+ * | | |WDT up counter will be held while CPU is held by ICE.\r
+ * | | |1 = ICE debug mode acknowledgment Disabled.\r
+ * | | |WDT up counter will keep going no matter CPU is held by ICE or not.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * @var WDT_T::ALTCTL\r
+ * Offset: 0x04 WDT Alternative Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1:0] |RSTDSEL |WDT Reset Delay Period Selection (Write Protect)\r
+ * | | |When WDT time-out event happened, user has a time named WDT Reset Delay Period to clear execute WDT counter by setting RSTCNT (WDT_CTL[0]) reset to prevent WDT time-out reset system occurred happened\r
+ * | | |User can select a suitable setting of RSTDSEL for different application program WDT Reset Delay Period.\r
+ * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.\r
+ * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.\r
+ * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.\r
+ * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.\r
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * | | |Note2: This register will be reset to 0 if WDT time-out reset system event occurred happened.\r
+ * @var WDT_T::RSTCNT\r
+ * Offset: 0x08 WDT Reset Counter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |RSTCNT |WDT Reset Counter Register\r
+ * | | |Writing 0x00005AA5 to this register field will reset the internal 18-bit WDT up counter value to 0.\r
+ * | | |Note: This WDT_RSTCNT is not write protected, but this RSTCNT (WDT_CTL[0]) is write protected.\r
+ * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.\r
+ */\r
+ __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */\r
+ __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */\r
+ __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */\r
+\r
+} WDT_T;\r
+\r
+/**\r
+ @addtogroup WDT_CONST WDT Bit Field Definition\r
+ Constant Definitions for WDT Controller\r
+@{ */\r
+\r
+#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */\r
+#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */\r
+\r
+#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */\r
+#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */\r
+\r
+#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */\r
+#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */\r
+\r
+#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */\r
+#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */\r
+\r
+#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */\r
+#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */\r
+\r
+#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */\r
+#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */\r
+\r
+#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */\r
+#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */\r
+\r
+#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */\r
+#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */\r
+\r
+#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */\r
+#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */\r
+\r
+#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */\r
+#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */\r
+\r
+#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */\r
+#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */\r
+\r
+#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */\r
+#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */\r
+\r
+\r
+/**@}*/ /* WDT_CONST */\r
+/**@}*/ /* end of WDT register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __WDT_REG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file wwdt_reg.h\r
+ * @version V1.00\r
+ * @brief WWDT register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __WWDT_REG_H__\r
+#define __WWDT_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- Window Watchdog Timer -------------------------*/\r
+/**\r
+ @addtogroup WWDT Window Watchdog Timer(WWDT)\r
+ Memory Mapped Structure for WWDT Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var WWDT_T::RLDCNT\r
+ * Offset: 0x00 WWDT Reload Counter Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |RLDCNT |WWDT Reload Counter Register\r
+ * | | |Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\r
+ * | | |Note1: User can only write execute WWDT_RLDCNT register to the reload WWDT counter value command when current current WWDT counter value CNTDAT (WWDT_CNT[5:0]) is between 10 and CMPDAT (WWDT_CTL[21:16])\r
+ * | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current current CNTDATWWDT counter value is larger than CMPDAT, WWDT reset signal system event will be generated immediately.\r
+ * | | |Note2: Execute WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also.\r
+ * @var WWDT_T::CTL\r
+ * Offset: 0x04 WWDT Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WWDTEN |WWDT Enable Control Bit\r
+ * | | |Set this bit to enable start WWDT counter counting.\r
+ * | | |0 = WWDT counter is stopped.\r
+ * | | |1 = WWDT counter is starting counting.\r
+ * |[1] |INTEN |WWDT Interrupt Enable Control Bit\r
+ * | | |If this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU.\r
+ * | | |0 = WWDT counter compare match interrupt Disabled.\r
+ * | | |1 = WWDT counter compare match interrupt Enabled.\r
+ * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection\r
+ * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.\r
+ * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.\r
+ * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.\r
+ * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.\r
+ * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.\r
+ * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.\r
+ * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.\r
+ * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.\r
+ * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.\r
+ * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.\r
+ * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.\r
+ * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.\r
+ * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.\r
+ * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.\r
+ * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.\r
+ * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.\r
+ * |[21:16] |CMPDAT |WWDT Window Compare Register Value\r
+ * | | |Set this register field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated..\r
+ * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT CNTDAT (WWDT_CNT[5:]) is counter value between 10 and CMPDAT\r
+ * | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current WWDT counter value CNTDAT is larger than CMPDAT, WWDT reset system event signal will be generated immediately.\r
+ * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control\r
+ * | | |0 = ICE debug mode acknowledgment effects WWDT counter counting.\r
+ * | | |WWDT down counter will be held while CPU is held by ICE.\r
+ * | | |1 = ICE debug mode acknowledgment Disabled.\r
+ * | | |WWDT down counter will keep going counting no matter CPU is held by ICE or not.\r
+ * @var WWDT_T::STATUS\r
+ * Offset: 0x08 WWDT Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag\r
+ * | | |This bit indicates the that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16])interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\r
+ * | | |0 = No effect.\r
+ * | | |1 = WWDT WWDT CNTDAT counter value matches the CMPDAT.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * |[1] |WWDTRF |WWDT Timer-out Reset System Flag\r
+ * | | |If this bit is set to 1, it This bit indicates the that system has been reset by WWDT counter time-out reset system event.or not.\r
+ * | | |0 = WWDT time-out reset system event did not occur.\r
+ * | | |1 = WWDT time-out reset system event occurred.\r
+ * | | |Note: This bit is cleared by writing 1 to it.\r
+ * @var WWDT_T::CNT\r
+ * Offset: 0x0C WWDT Counter Value Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[5:0] |CNTDAT |WWDT Counter Value\r
+ * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.\r
+ */\r
+ __O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */\r
+ __IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */\r
+ __IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */\r
+ __I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */\r
+\r
+} WWDT_T;\r
+\r
+\r
+/**\r
+ @addtogroup WWDT_CONST WWDT Bit Field Definition\r
+ Constant Definitions for WWDT Controller\r
+@{ */\r
+\r
+#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */\r
+#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */\r
+\r
+#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */\r
+#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */\r
+\r
+#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */\r
+#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */\r
+\r
+#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */\r
+#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */\r
+\r
+#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */\r
+#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */\r
+\r
+#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */\r
+#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */\r
+\r
+#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */\r
+#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */\r
+\r
+#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */\r
+#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */\r
+\r
+#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */\r
+#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */\r
+\r
+/**@}*/ /* WWDT_CONST */\r
+/**@}*/ /* end of WWDT register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __WWDT_REG_H__ */\r
--- /dev/null
+;/**************************************************************************//**\r
+; * @file startup_TC8234.s\r
+; * @version V2.00\r
+; * $Revision: 9 $\r
+; * $Date: 16/08/27 12:33p $ \r
+; * @brief Startup Source File\r
+; *\r
+; * @note\r
+; * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+; *\r
+; ******************************************************************************/\r
+ \r
+ \r
+;/*\r
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+;*/\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+ IF :LNOT: :DEF: Stack_Size\r
+Stack_Size EQU 0x00000800\r
+ ENDIF\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+ IF :LNOT: :DEF: Heap_Size\r
+Heap_Size EQU 0x00000000\r
+ ENDIF\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+ IMPORT SendChar_ToUART\r
+\r
+__Vectors DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ ; maximum of 32 External Interrupts are possible\r
+ DCD BOD_IRQHandler ; 0 \r
+ DCD IRC_IRQHandler ; 1 \r
+ DCD PWRWU_IRQHandler ; 2 \r
+ DCD SRAM_IRQHandler ; 3 \r
+ DCD CLKFAIL_IRQHandler ; 4 \r
+ DCD DEFAULT_IRQHandler ; 5 \r
+ DCD RTC_IRQHandler ; 6 \r
+ DCD TAMPER_IRQHandler ; 7 \r
+ DCD WDT_IRQHandler ; 8 \r
+ DCD WWDT_IRQHandler ; 9 \r
+ DCD EINT0_IRQHandler ; 10 \r
+ DCD EINT1_IRQHandler ; 11 \r
+ DCD EINT2_IRQHandler ; 12 \r
+ DCD EINT3_IRQHandler ; 13 \r
+ DCD EINT4_IRQHandler ; 14 \r
+ DCD EINT5_IRQHandler ; 15 \r
+ DCD GPA_IRQHandler ; 16 \r
+ DCD GPB_IRQHandler ; 17 \r
+ DCD GPC_IRQHandler ; 18 \r
+ DCD GPD_IRQHandler ; 19 \r
+ DCD GPE_IRQHandler ; 20 \r
+ DCD GPF_IRQHandler ; 21 \r
+ DCD QSPI0_IRQHandler ; 22 \r
+ DCD SPI0_IRQHandler ; 23 \r
+ DCD BRAKE0_IRQHandler ; 24 \r
+ DCD EPWM0_P0_IRQHandler ; 25 \r
+ DCD EPWM0_P1_IRQHandler ; 26 \r
+ DCD EPWM0_P2_IRQHandler ; 27 \r
+ DCD BRAKE1_IRQHandler ; 28 \r
+ DCD EPWM1_P0_IRQHandler ; 29 \r
+ DCD EPWM1_P1_IRQHandler ; 30 \r
+ DCD EPWM1_P2_IRQHandler ; 31 \r
+ DCD TMR0_IRQHandler ; 32 \r
+ DCD TMR1_IRQHandler ; 33 \r
+ DCD TMR2_IRQHandler ; 34 \r
+ DCD TMR3_IRQHandler ; 35 \r
+ DCD UART0_IRQHandler ; 36 \r
+ DCD UART1_IRQHandler ; 37 \r
+ DCD I2C0_IRQHandler ; 38 \r
+ DCD I2C1_IRQHandler ; 39 \r
+ DCD PDMA0_IRQHandler ; 40 \r
+ DCD DAC_IRQHandler ; 41 \r
+ DCD EADC0_IRQHandler ; 42 \r
+ DCD EADC1_IRQHandler ; 43 \r
+ DCD ACMP01_IRQHandler ; 44 \r
+ DCD DEFAULT_IRQHandler ; 45 \r
+ DCD EADC2_IRQHandler ; 46 \r
+ DCD EADC3_IRQHandler ; 47 \r
+ DCD UART2_IRQHandler ; 48 \r
+ DCD UART3_IRQHandler ; 49 \r
+ DCD DEFAULT_IRQHandler ; 50 \r
+ DCD SPI1_IRQHandler ; 51 \r
+ DCD SPI2_IRQHandler ; 52 \r
+ DCD USBD_IRQHandler ; 53 \r
+ DCD USBH_IRQHandler ; 54 \r
+ DCD USBOTG_IRQHandler ; 55 \r
+ DCD CAN0_IRQHandler ; 56 \r
+ DCD DEFAULT_IRQHandler ; 57 \r
+ DCD SC0_IRQHandler ; 58 \r
+ DCD SC1_IRQHandler ; 59 \r
+ DCD SC2_IRQHandler ; 60 \r
+ DCD DEFAULT_IRQHandler ; 61 \r
+ DCD SPI3_IRQHandler ; 62 \r
+ DCD DEFAULT_IRQHandler ; 63 \r
+ DCD SDH0_IRQHandler ; 64 \r
+ DCD DEFAULT_IRQHandler ; 65 \r
+ DCD DEFAULT_IRQHandler ; 66 \r
+ DCD DEFAULT_IRQHandler ; 67 \r
+ DCD I2S0_IRQHandler ; 68 \r
+ DCD DEFAULT_IRQHandler ; 69 \r
+ DCD OPA0_IRQHandler ; 70 \r
+ DCD CRPT_IRQHandler ; 71 \r
+ DCD GPG_IRQHandler ; 72 \r
+ DCD EINT6_IRQHandler ; 73 \r
+ DCD UART4_IRQHandler ; 74 \r
+ DCD UART5_IRQHandler ; 75 \r
+ DCD USCI0_IRQHandler ; 76 \r
+ DCD USCI1_IRQHandler ; 77 \r
+ DCD BPWM0_IRQHandler ; 78 \r
+ DCD BPWM1_IRQHandler ; 79 \r
+ DCD DEFAULT_IRQHandler ; 80 \r
+ DCD DEFAULT_IRQHandler ; 81 \r
+ DCD I2C2_IRQHandler ; 82 \r
+ DCD DEFAULT_IRQHandler ; 83 \r
+ DCD QEI0_IRQHandler ; 84 \r
+ DCD QEI1_IRQHandler ; 85 \r
+ DCD ECAP0_IRQHandler ; 86 \r
+ DCD ECAP1_IRQHandler ; 87 \r
+ DCD GPH_IRQHandler ; 88 \r
+ DCD EINT7_IRQHandler ; 89 \r
+ DCD DEFAULT_IRQHandler ; 90 \r
+ DCD DEFAULT_IRQHandler ; 91 \r
+ DCD DEFAULT_IRQHandler ; 92 \r
+ DCD DEFAULT_IRQHandler ; 93 \r
+ DCD DEFAULT_IRQHandler ; 94 \r
+ DCD DEFAULT_IRQHandler ; 95 \r
+ DCD DEFAULT_IRQHandler ; 96 \r
+ DCD DEFAULT_IRQHandler ; 97 \r
+ DCD PDMA1_IRQHandler ; 98 \r
+ DCD SCU_IRQHandler ; 99 \r
+ DCD DEFAULT_IRQHandler ; 100\r
+ DCD TRNG_IRQHandler ; 101\r
+ \r
+ \r
+ \r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+ AREA |.text|, CODE, READONLY\r
+\r
+\r
+; Reset Handler\r
+\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT SystemInit\r
+ IMPORT __main\r
+ \r
+\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ IMPORT ProcessHardFault\r
+ EXPORT HardFault_Handler [WEAK]\r
+ MOV R0, LR \r
+ MRS R1, MSP \r
+ MRS R2, PSP \r
+ LDR R3, =ProcessHardFault \r
+ BLX R3 \r
+ BX R0 \r
+ ENDP\r
+ProcessHardFaultx\\r
+ PROC\r
+ EXPORT ProcessHardFaultx [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ EXPORT BOD_IRQHandler [WEAK] ; 0 \r
+ EXPORT IRC_IRQHandler [WEAK] ; 1 \r
+ EXPORT PWRWU_IRQHandler [WEAK] ; 2 \r
+ EXPORT SRAM_IRQHandler [WEAK] ; 3 \r
+ EXPORT CLKFAIL_IRQHandler [WEAK] ; 4 \r
+ ;EXPORT 0 [WEAK] ; 5 \r
+ EXPORT RTC_IRQHandler [WEAK] ; 6 \r
+ EXPORT TAMPER_IRQHandler [WEAK] ; 7 \r
+ EXPORT WDT_IRQHandler [WEAK] ; 8 \r
+ EXPORT WWDT_IRQHandler [WEAK] ; 9 \r
+ EXPORT EINT0_IRQHandler [WEAK] ; 10 \r
+ EXPORT EINT1_IRQHandler [WEAK] ; 11 \r
+ EXPORT EINT2_IRQHandler [WEAK] ; 12 \r
+ EXPORT EINT3_IRQHandler [WEAK] ; 13 \r
+ EXPORT EINT4_IRQHandler [WEAK] ; 14 \r
+ EXPORT EINT5_IRQHandler [WEAK] ; 15 \r
+ EXPORT GPA_IRQHandler [WEAK] ; 16 \r
+ EXPORT GPB_IRQHandler [WEAK] ; 17 \r
+ EXPORT GPC_IRQHandler [WEAK] ; 18 \r
+ EXPORT GPD_IRQHandler [WEAK] ; 19 \r
+ EXPORT GPE_IRQHandler [WEAK] ; 20 \r
+ EXPORT GPF_IRQHandler [WEAK] ; 21 \r
+ EXPORT QSPI0_IRQHandler [WEAK] ; 22 \r
+ EXPORT SPI0_IRQHandler [WEAK] ; 23 \r
+ EXPORT BRAKE0_IRQHandler [WEAK] ; 24 \r
+ EXPORT EPWM0_P0_IRQHandler [WEAK] ; 25 \r
+ EXPORT EPWM0_P1_IRQHandler [WEAK] ; 26 \r
+ EXPORT EPWM0_P2_IRQHandler [WEAK] ; 27 \r
+ EXPORT BRAKE1_IRQHandler [WEAK] ; 28 \r
+ EXPORT EPWM1_P0_IRQHandler [WEAK] ; 29 \r
+ EXPORT EPWM1_P1_IRQHandler [WEAK] ; 30 \r
+ EXPORT EPWM1_P2_IRQHandler [WEAK] ; 31 \r
+ EXPORT TMR0_IRQHandler [WEAK] ; 32 \r
+ EXPORT TMR1_IRQHandler [WEAK] ; 33 \r
+ EXPORT TMR2_IRQHandler [WEAK] ; 34 \r
+ EXPORT TMR3_IRQHandler [WEAK] ; 35 \r
+ EXPORT UART0_IRQHandler [WEAK] ; 36 \r
+ EXPORT UART1_IRQHandler [WEAK] ; 37 \r
+ EXPORT I2C0_IRQHandler [WEAK] ; 38 \r
+ EXPORT I2C1_IRQHandler [WEAK] ; 39 \r
+ EXPORT PDMA0_IRQHandler [WEAK] ; 40 \r
+ EXPORT DAC_IRQHandler [WEAK] ; 41 \r
+ EXPORT EADC0_IRQHandler [WEAK] ; 42 \r
+ EXPORT EADC1_IRQHandler [WEAK] ; 43 \r
+ EXPORT ACMP01_IRQHandler [WEAK] ; 44 \r
+ ;EXPORT 0 [WEAK] ; 45 \r
+ EXPORT EADC2_IRQHandler [WEAK] ; 46 \r
+ EXPORT EADC3_IRQHandler [WEAK] ; 47 \r
+ EXPORT UART2_IRQHandler [WEAK] ; 48 \r
+ EXPORT UART3_IRQHandler [WEAK] ; 49 \r
+ ;EXPORT 0 [WEAK] ; 50 \r
+ EXPORT SPI1_IRQHandler [WEAK] ; 51 \r
+ EXPORT SPI2_IRQHandler [WEAK] ; 52 \r
+ EXPORT USBD_IRQHandler [WEAK] ; 53 \r
+ EXPORT USBH_IRQHandler [WEAK] ; 54 \r
+ EXPORT USBOTG_IRQHandler [WEAK] ; 55 \r
+ EXPORT CAN0_IRQHandler [WEAK] ; 56 \r
+ EXPORT CAN1_IRQHandler [WEAK] ; 57 \r
+ EXPORT SC0_IRQHandler [WEAK] ; 58 \r
+ EXPORT SC1_IRQHandler [WEAK] ; 59 \r
+ EXPORT SC2_IRQHandler [WEAK] ; 60 \r
+ EXPORT SC3_IRQHandler [WEAK] ; 61 \r
+ EXPORT SPI3_IRQHandler [WEAK] ; 62 \r
+ ;EXPORT 0 [WEAK] ; 63 \r
+ EXPORT SDH0_IRQHandler [WEAK] ; 64 \r
+ ;EXPORT 0 [WEAK] ; 65 \r
+ ;EXPORT 0 [WEAK] ; 66 \r
+ ;EXPORT 0 [WEAK] ; 67 \r
+ EXPORT I2S0_IRQHandler [WEAK] ; 68 \r
+ ;EXPORT 0 [WEAK] ; 69 \r
+ EXPORT OPA0_IRQHandler [WEAK] ; 70 \r
+ EXPORT CRPT_IRQHandler [WEAK] ; 71 \r
+ EXPORT GPG_IRQHandler [WEAK] ; 72 \r
+ EXPORT EINT6_IRQHandler [WEAK] ; 73 \r
+ EXPORT UART4_IRQHandler [WEAK] ; 74 \r
+ EXPORT UART5_IRQHandler [WEAK] ; 75 \r
+ EXPORT USCI0_IRQHandler [WEAK] ; 76 \r
+ EXPORT USCI1_IRQHandler [WEAK] ; 77 \r
+ EXPORT BPWM0_IRQHandler [WEAK] ; 78 \r
+ EXPORT BPWM1_IRQHandler [WEAK] ; 79 \r
+ ;EXPORT 0 [WEAK] ; 80 \r
+ ;EXPORT 0 [WEAK] ; 81 \r
+ EXPORT I2C2_IRQHandler [WEAK] ; 82 \r
+ ;EXPORT 0 [WEAK] ; 83 \r
+ EXPORT QEI0_IRQHandler [WEAK] ; 84 \r
+ EXPORT QEI1_IRQHandler [WEAK] ; 85 \r
+ EXPORT ECAP0_IRQHandler [WEAK] ; 86 \r
+ EXPORT ECAP1_IRQHandler [WEAK] ; 87 \r
+ EXPORT GPH_IRQHandler [WEAK] ; 88 \r
+ EXPORT EINT7_IRQHandler [WEAK] ; 89 \r
+ EXPORT SDH1_IRQHandler [WEAK] ; 90 \r
+ ;EXPORT 0 [WEAK] ; 91 \r
+ ;EXPORT USBH_IRQHandler [WEAK] ; 92 \r
+ ;EXPORT 0 [WEAK] ; 93 \r
+ ;EXPORT 0 [WEAK] ; 94 \r
+ ;EXPORT 0 [WEAK] ; 95 \r
+ ;EXPORT 0 [WEAK] ; 96 \r
+ ;EXPORT 0 [WEAK] ; 97 \r
+ EXPORT PDMA1_IRQHandler [WEAK] ; 98 \r
+ EXPORT SCU_IRQHandler [WEAK] ; 99 \r
+ ;EXPORT 0 [WEAK] ; 100\r
+ EXPORT TRNG_IRQHandler [WEAK] ; 101\r
+ \r
+\r
+\r
+ EXPORT DEFAULT_IRQHandler [WEAK] \r
+ \r
+BOD_IRQHandler ; 0 \r
+IRC_IRQHandler ; 1 \r
+PWRWU_IRQHandler ; 2 \r
+SRAM_IRQHandler ; 3 \r
+CLKFAIL_IRQHandler ; 4 \r
+;0 ; 5 \r
+RTC_IRQHandler ; 6 \r
+TAMPER_IRQHandler ; 7 \r
+WDT_IRQHandler ; 8 \r
+WWDT_IRQHandler ; 9 \r
+EINT0_IRQHandler ; 10 \r
+EINT1_IRQHandler ; 11 \r
+EINT2_IRQHandler ; 12 \r
+EINT3_IRQHandler ; 13 \r
+EINT4_IRQHandler ; 14 \r
+EINT5_IRQHandler ; 15 \r
+GPA_IRQHandler ; 16 \r
+GPB_IRQHandler ; 17 \r
+GPC_IRQHandler ; 18 \r
+GPD_IRQHandler ; 19 \r
+GPE_IRQHandler ; 20 \r
+GPF_IRQHandler ; 21 \r
+QSPI0_IRQHandler ; 22 \r
+SPI0_IRQHandler ; 23 \r
+BRAKE0_IRQHandler ; 24 \r
+EPWM0_P0_IRQHandler ; 25 \r
+EPWM0_P1_IRQHandler ; 26 \r
+EPWM0_P2_IRQHandler ; 27 \r
+BRAKE1_IRQHandler ; 28 \r
+EPWM1_P0_IRQHandler ; 29 \r
+EPWM1_P1_IRQHandler ; 30 \r
+EPWM1_P2_IRQHandler ; 31 \r
+TMR0_IRQHandler ; 32 \r
+TMR1_IRQHandler ; 33 \r
+TMR2_IRQHandler ; 34 \r
+TMR3_IRQHandler ; 35 \r
+UART0_IRQHandler ; 36 \r
+UART1_IRQHandler ; 37 \r
+I2C0_IRQHandler ; 38 \r
+I2C1_IRQHandler ; 39 \r
+PDMA0_IRQHandler ; 40 \r
+DAC_IRQHandler ; 41 \r
+EADC0_IRQHandler ; 42 \r
+EADC1_IRQHandler ; 43 \r
+ACMP01_IRQHandler ; 44 \r
+;0 ; 45 \r
+EADC2_IRQHandler ; 46 \r
+EADC3_IRQHandler ; 47 \r
+UART2_IRQHandler ; 48 \r
+UART3_IRQHandler ; 49 \r
+;0 ; 50 \r
+SPI1_IRQHandler ; 51 \r
+SPI2_IRQHandler ; 52 \r
+USBD_IRQHandler ; 53 \r
+USBH_IRQHandler ; 54 \r
+USBOTG_IRQHandler ; 55 \r
+CAN0_IRQHandler ; 56 \r
+CAN1_IRQHandler ; 57 \r
+SC0_IRQHandler ; 58 \r
+SC1_IRQHandler ; 59 \r
+SC2_IRQHandler ; 60 \r
+SC3_IRQHandler ; 61 \r
+SPI3_IRQHandler ; 62 \r
+;0 ; 63 \r
+SDH0_IRQHandler ; 64 \r
+;0 ; 65 \r
+;0 ; 66 \r
+;0 ; 67 \r
+I2S0_IRQHandler ; 68 \r
+;0 ; 69 \r
+OPA0_IRQHandler ; 70 \r
+CRPT_IRQHandler ; 71 \r
+GPG_IRQHandler ; 72 \r
+EINT6_IRQHandler ; 73 \r
+UART4_IRQHandler ; 74 \r
+UART5_IRQHandler ; 75 \r
+USCI0_IRQHandler ; 76 \r
+USCI1_IRQHandler ; 77 \r
+BPWM0_IRQHandler ; 78 \r
+BPWM1_IRQHandler ; 79 \r
+;0 ; 80 \r
+;0 ; 81 \r
+I2C2_IRQHandler ; 82 \r
+;0 ; 83 \r
+QEI0_IRQHandler ; 84 \r
+QEI1_IRQHandler ; 85 \r
+ECAP0_IRQHandler ; 86 \r
+ECAP1_IRQHandler ; 87 \r
+GPH_IRQHandler ; 88 \r
+EINT7_IRQHandler ; 89 \r
+SDH1_IRQHandler ; 90 \r
+;0 ; 91 \r
+;USBH_IRQHandler ; 92 \r
+;0 ; 93 \r
+;0 ; 94 \r
+;0 ; 95 \r
+;0 ; 96 \r
+;0 ; 97 \r
+PDMA1_IRQHandler ; 98 \r
+SCU_IRQHandler ; 99 \r
+;0 ; 100\r
+TRNG_IRQHandler ; 101\r
+DEFAULT_IRQHandler\r
+ B .\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+\r
+; User Initial Stack & Heap\r
+\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+\r
+__user_initial_stackheap PROC\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, = (Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+ ENDP\r
+\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+;int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)\r
+SH_DoCommand PROC\r
+ \r
+ EXPORT SH_DoCommand\r
+ IMPORT SH_Return\r
+ \r
+ BKPT 0xAB ; Wait ICE or HardFault\r
+ LDR R3, =SH_Return \r
+ MOV R4, lr \r
+ BLX R3 ; Call SH_Return. The return value is in R0\r
+ BX R4 ; Return value = R0\r
+ \r
+ ENDP\r
+\r
+__PC PROC\r
+ EXPORT __PC\r
+ \r
+ MOV r0, lr\r
+ BLX lr\r
+ ALIGN\r
+ \r
+ ENDP\r
+ \r
+ END\r
--- /dev/null
+//
+// This file is part of the uOS++ III distribution
+// Parts of this file are from the newlib sources, issued under GPL.
+// Copyright (c) 2014 Liviu Ionescu
+//
+
+// ----------------------------------------------------------------------------
+
+int errno;
+void *__dso_handle __attribute__ ((weak));
+
+// ----------------------------------------------------------------------------
+
+#if !defined(OS_USE_SEMIHOSTING)
+
+#include <_ansi.h>
+#include <_syslist.h>
+#include <errno.h>
+//#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <sys/times.h>
+#include <limits.h>
+#include <signal.h>
+
+void
+__initialize_args(int* p_argc, char*** p_argv);
+
+// This is the standard default implementation for the routine to
+// process args. It returns a single empty arg.
+// For semihosting applications, this is redefined to get the real
+// args from the debugger. You can also use it if you decide to keep
+// some args in a non-volatile memory.
+
+void __attribute__((weak))
+__initialize_args(int* p_argc, char*** p_argv)
+{
+ // By the time we reach this, the data and bss should have been initialised.
+
+ // The strings pointed to by the argv array shall be modifiable by the
+ // program, and retain their last-stored values between program startup
+ // and program termination. (static, no const)
+ static char name[] = "";
+
+ // The string pointed to by argv[0] represents the program name;
+ // argv[0][0] shall be the null character if the program name is not
+ // available from the host environment. argv[argc] shall be a null pointer.
+ // (static, no const)
+ static char* argv[2] =
+ { name, NULL };
+
+ *p_argc = 1;
+ *p_argv = &argv[0];
+ return;
+}
+
+// These functions are defined here to avoid linker errors in freestanding
+// applications. They might be called in some error cases from library
+// code.
+//
+// If you detect other functions to be needed, just let us know
+// and we'll add them.
+
+int
+raise(int sig __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int
+kill(pid_t pid, int sig);
+
+int
+kill(pid_t pid __attribute__((unused)), int sig __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+#endif // !defined(OS_USE_SEMIHOSTING)
+
+// ----------------------------------------------------------------------------
+
+// If you need the empty definitions, remove the -ffreestanding option.
+
+#if __STDC_HOSTED__ == 1
+
+char* __env[1] =
+{ 0 };
+char** environ = __env;
+
+#if !defined(OS_USE_SEMIHOSTING)
+
+// Forward declarations
+
+int
+_chown(const char* path, uid_t owner, gid_t group);
+
+int
+_close(int fildes);
+
+int
+_execve(char* name, char** argv, char** env);
+
+int
+_fork(void);
+
+int
+_fstat(int fildes, struct stat* st);
+
+int
+_getpid(void);
+
+int
+_gettimeofday(struct timeval* ptimeval, void* ptimezone);
+
+int
+_isatty(int file);
+
+int
+_kill(int pid, int sig);
+
+int
+_link(char* existing, char* _new);
+
+int
+_lseek(int file, int ptr, int dir);
+
+int
+_open(char* file, int flags, int mode);
+
+int
+_read(int file, char* ptr, int len);
+
+int
+_readlink(const char* path, char* buf, size_t bufsize);
+
+int
+_stat(const char* file, struct stat* st);
+
+int
+_symlink(const char* path1, const char* path2);
+
+clock_t
+_times(struct tms* buf);
+
+int
+_unlink(char* name);
+
+int
+_wait(int* status);
+
+int
+_write(int file, char* ptr, int len);
+
+// Definitions
+
+int __attribute__((weak))
+_chown(const char* path __attribute__((unused)),
+ uid_t owner __attribute__((unused)), gid_t group __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_close(int fildes __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_execve(char* name __attribute__((unused)), char** argv __attribute__((unused)),
+ char** env __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_fork(void)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_fstat(int fildes __attribute__((unused)),
+ struct stat* st __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_getpid(void)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_gettimeofday(struct timeval* ptimeval __attribute__((unused)),
+ void* ptimezone __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_isatty(int file __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return 0;
+}
+
+int __attribute__((weak))
+_kill(int pid __attribute__((unused)), int sig __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_link(char* existing __attribute__((unused)),
+ char* _new __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_lseek(int file __attribute__((unused)), int ptr __attribute__((unused)),
+ int dir __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_open(char* file __attribute__((unused)), int flags __attribute__((unused)),
+ int mode __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_read(int file __attribute__((unused)), char* ptr __attribute__((unused)),
+ int len __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_readlink(const char* path __attribute__((unused)),
+ char* buf __attribute__((unused)), size_t bufsize __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_stat(const char* file __attribute__((unused)),
+ struct stat* st __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_symlink(const char* path1 __attribute__((unused)),
+ const char* path2 __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+clock_t __attribute__((weak))
+_times(struct tms* buf __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return ((clock_t) -1);
+}
+
+int __attribute__((weak))
+_unlink(char* name __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_wait(int* status __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int __attribute__((weak))
+_write(int file __attribute__((unused)), char* ptr __attribute__((unused)),
+ int len __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+// ----------------------------------------------------------------------------
+
+#else // defined(OS_USE_SEMIHOSTING)
+
+// ----------------------------------------------------------------------------
+
+/* Support files for GNU libc. Files in the system namespace go here.
+ Files in the C namespace (ie those that do not start with an
+ underscore) go in .c. */
+
+#include <_ansi.h>
+#include <stdint.h>
+//#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/fcntl.h>
+#include <stdio.h>
+#include <string.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+#include <errno.h>
+#include <reent.h>
+#include <unistd.h>
+#include <sys/wait.h>
+#include <ctype.h>
+#include <signal.h>
+
+#include "semihosting.h"
+
+int _kill (int pid, int sig);
+
+void __attribute__((noreturn)) _exit (int status);
+
+// Forward declarations.
+int _system (const char*);
+int _rename (const char*, const char*);
+int _isatty (int);
+clock_t _times (struct tms*);
+int _gettimeofday (struct timeval *, void*);
+int _unlink (const char*);
+int _link (void);
+
+int _stat (const char*, struct stat*);
+
+int _fstat (int, struct stat*);
+int _swistat (int fd, struct stat* st);
+int _getpid (int);
+int _close (int);
+clock_t _clock (void);
+int _swiclose (int);
+int _open (const char*, int, ...);
+int _swiopen (const char*, int);
+int _write (int, char*, int);
+int _swiwrite (int, char*, int);
+int _lseek (int, int, int);
+int _swilseek (int, int, int);
+int _read (int, char*, int);
+int _swiread (int, char*, int);
+
+void initialise_monitor_handles (void);
+
+void __initialize_args (int* p_argc, char*** p_argv);
+
+static int
+checkerror (int);
+static int
+error (int);
+static int
+get_errno (void);
+
+// ----------------------------------------------------------------------------
+
+#define ARGS_BUF_ARRAY_SIZE 80
+#define ARGV_BUF_ARRAY_SIZE 10
+
+typedef struct
+{
+ char* pCommandLine;
+ int size;
+} CommandLineBlock;
+
+void __initialize_args (int* p_argc, char*** p_argv)
+{
+ // Array of chars to receive the command line from the host
+ static char args_buf[ARGS_BUF_ARRAY_SIZE];
+
+ // Array of pointers to store the final argv pointers (pointing
+ // in the above array).
+ static char* argv_buf[ARGV_BUF_ARRAY_SIZE];
+
+ int argc = 0;
+ int isInArgument = 0;
+
+ CommandLineBlock cmdBlock;
+ cmdBlock.pCommandLine = args_buf;
+ cmdBlock.size = sizeof(args_buf) - 1;
+
+ int ret = call_host (SEMIHOSTING_SYS_GET_CMDLINE, &cmdBlock);
+ if (ret == 0)
+ {
+
+ // In case the host send more than we can chew, limit the
+ // string to our buffer.
+ args_buf[ARGS_BUF_ARRAY_SIZE - 1] = '\0';
+
+ // The command line is a null terminated string
+ char* p = cmdBlock.pCommandLine;
+
+ int delim = '\0';
+ int ch;
+
+ while ((ch = *p) != '\0')
+ {
+ if (isInArgument == 0)
+ {
+ if (!isblank(ch))
+ {
+ if (argc >= (int) ((sizeof(argv_buf) / sizeof(argv_buf[0])) - 1))
+ break;
+
+ if (ch == '"' || ch == '\'')
+ {
+ // Remember the delimiter to search for the
+ // corresponding terminator
+ delim = ch;
+ ++p; // skip the delimiter
+ ch = *p;
+ }
+ // Remember the arg beginning address
+ argv_buf[argc++] = p;
+ isInArgument = 1;
+ }
+ }
+ else if (delim != '\0')
+ {
+ if ((ch == delim))
+ {
+ delim = '\0';
+ *p = '\0';
+ isInArgument = 0;
+ }
+ }
+ else if (isblank(ch))
+ {
+ delim = '\0';
+ *p = '\0';
+ isInArgument = 0;
+ }
+ ++p;
+ }
+ }
+
+ if (argc == 0)
+ {
+ // No args found in string, return a single empty name.
+ args_buf[0] = '\0';
+ argv_buf[0] = &args_buf[0];
+ ++argc;
+ }
+
+ // Must end the array with a null pointer.
+ argv_buf[argc] = NULL;
+
+ *p_argc = argc;
+ *p_argv = &argv_buf[0];
+
+ // temporary here
+ initialise_monitor_handles ();
+
+ return;
+}
+
+// ----------------------------------------------------------------------------
+
+void _exit (int status)
+{
+ /* There is only one SWI for both _exit and _kill. For _exit, call
+ the SWI with the second argument set to -1, an invalid value for
+ signum, so that the SWI handler can distinguish the two calls.
+ Note: The RDI implementation of _kill throws away both its
+ arguments. */
+ report_exception (status == 0 ? ADP_Stopped_ApplicationExit : ADP_Stopped_RunTimeError);
+}
+
+// ----------------------------------------------------------------------------
+
+int __attribute__((weak))
+_kill (int pid __attribute__((unused)), int sig __attribute__((unused)))
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+// ----------------------------------------------------------------------------
+
+/* Struct used to keep track of the file position, just so we
+ can implement fseek(fh,x,SEEK_CUR). */
+struct fdent
+{
+ int handle;
+ int pos;
+};
+
+#define MAX_OPEN_FILES 20
+
+/* User file descriptors (fd) are integer indexes into
+ the openfiles[] array. Error checking is done by using
+ findslot().
+
+ This openfiles array is manipulated directly by only
+ these 5 functions:
+
+ findslot() - Translate entry.
+ newslot() - Find empty entry.
+ initilise_monitor_handles() - Initialize entries.
+ _swiopen() - Initialize entry.
+ _close() - Handle stdout == stderr case.
+
+ Every other function must use findslot(). */
+
+static struct fdent openfiles[MAX_OPEN_FILES];
+
+static struct fdent* findslot (int);
+static int newslot (void);
+
+/* Register name faking - works in collusion with the linker. */
+register char* stack_ptr asm ("sp");
+
+/* following is copied from libc/stdio/local.h to check std streams */
+extern void _EXFUN(__sinit,(struct _reent*));
+#define CHECK_INIT(ptr) \
+ do \
+ { \
+ if ((ptr) && !(ptr)->__sdidinit) \
+ __sinit (ptr); \
+ } \
+ while (0)
+
+static int monitor_stdin;
+static int monitor_stdout;
+static int monitor_stderr;
+
+/* Return a pointer to the structure associated with
+ the user file descriptor fd. */
+static struct fdent*
+findslot (int fd)
+{
+ CHECK_INIT(_REENT);
+
+ /* User file descriptor is out of range. */
+ if ((unsigned int) fd >= MAX_OPEN_FILES)
+ {
+ return NULL;
+ }
+
+ /* User file descriptor is open? */
+ if (openfiles[fd].handle == -1)
+ {
+ return NULL;
+ }
+
+ /* Valid. */
+ return &openfiles[fd];
+}
+
+/* Return the next lowest numbered free file
+ structure, or -1 if we can't find one. */
+static int
+newslot (void)
+{
+ int i;
+
+ for (i = 0; i < MAX_OPEN_FILES; i++)
+ {
+ if (openfiles[i].handle == -1)
+ {
+ break;
+ }
+ }
+
+ if (i == MAX_OPEN_FILES)
+ {
+ return -1;
+ }
+
+ return i;
+}
+
+void
+initialise_monitor_handles (void)
+{
+ int i;
+
+ /* Open the standard file descriptors by opening the special
+ * teletype device, ":tt", read-only to obtain a descriptor for
+ * standard input and write-only to obtain a descriptor for standard
+ * output. Finally, open ":tt" in append mode to obtain a descriptor
+ * for standard error. Since this is a write mode, most kernels will
+ * probably return the same value as for standard output, but the
+ * kernel can differentiate the two using the mode flag and return a
+ * different descriptor for standard error.
+ */
+
+ int volatile block[3];
+
+ block[0] = (int) ":tt";
+ block[2] = 3; /* length of filename */
+ block[1] = 0; /* mode "r" */
+ monitor_stdin = call_host (SEMIHOSTING_SYS_OPEN, (void*) block);
+
+ block[0] = (int) ":tt";
+ block[2] = 3; /* length of filename */
+ block[1] = 4; /* mode "w" */
+ monitor_stdout = call_host (SEMIHOSTING_SYS_OPEN, (void*) block);
+
+ block[0] = (int) ":tt";
+ block[2] = 3; /* length of filename */
+ block[1] = 8; /* mode "a" */
+ monitor_stderr = call_host (SEMIHOSTING_SYS_OPEN, (void*) block);
+
+ /* If we failed to open stderr, redirect to stdout. */
+ if (monitor_stderr == -1)
+ {
+ monitor_stderr = monitor_stdout;
+ }
+
+ for (i = 0; i < MAX_OPEN_FILES; i++)
+ {
+ openfiles[i].handle = -1;
+ }
+
+ openfiles[0].handle = monitor_stdin;
+ openfiles[0].pos = 0;
+ openfiles[1].handle = monitor_stdout;
+ openfiles[1].pos = 0;
+ openfiles[2].handle = monitor_stderr;
+ openfiles[2].pos = 0;
+}
+
+static int
+get_errno (void)
+{
+ return call_host (SEMIHOSTING_SYS_ERRNO, NULL);
+}
+
+/* Set errno and return result. */
+static int
+error (int result)
+{
+ errno = get_errno ();
+ return result;
+}
+
+/* Check the return and set errno appropriately. */
+static int
+checkerror (int result)
+{
+ if (result == -1)
+ {
+ return error (-1);
+ }
+
+ return result;
+}
+
+/* fh, is a valid internal file handle.
+ ptr, is a null terminated string.
+ len, is the length in bytes to read.
+ Returns the number of bytes *not* written. */
+int
+_swiread (int fh, char* ptr, int len)
+{
+ int block[3];
+
+ block[0] = fh;
+ block[1] = (int) ptr;
+ block[2] = len;
+
+ return checkerror (call_host (SEMIHOSTING_SYS_READ, block));
+}
+
+/* fd, is a valid user file handle.
+ Translates the return of _swiread into
+ bytes read. */
+int
+_read (int fd, char* ptr, int len)
+{
+ int res;
+ struct fdent *pfd;
+
+ pfd = findslot (fd);
+ if (pfd == NULL)
+ {
+ errno = EBADF;
+ return -1;
+ }
+
+ res = _swiread (pfd->handle, ptr, len);
+
+ if (res == -1)
+ {
+ return res;
+ }
+
+ pfd->pos += len - res;
+
+ /* res == len is not an error,
+ at least if we want feof() to work. */
+ return len - res;
+}
+
+/* fd, is a user file descriptor. */
+int _swilseek (int fd, int ptr, int dir)
+{
+ int res;
+ struct fdent *pfd;
+
+ /* Valid file descriptor? */
+ pfd = findslot (fd);
+ if (pfd == NULL)
+ {
+ errno = EBADF;
+ return -1;
+ }
+
+ /* Valid whence? */
+ if ((dir != SEEK_CUR) && (dir != SEEK_SET) && (dir != SEEK_END))
+ {
+ errno = EINVAL;
+ return -1;
+ }
+
+ /* Convert SEEK_CUR to SEEK_SET */
+ if (dir == SEEK_CUR)
+ {
+ ptr = pfd->pos + ptr;
+ /* The resulting file offset would be negative. */
+ if (ptr < 0)
+ {
+ errno = EINVAL;
+ if ((pfd->pos > 0) && (ptr > 0))
+ {
+ errno = EOVERFLOW;
+ }
+ return -1;
+ }
+ dir = SEEK_SET;
+ }
+
+ int block[2];
+ if (dir == SEEK_END)
+ {
+ block[0] = pfd->handle;
+ res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, block));
+ if (res == -1)
+ {
+ return -1;
+ }
+ ptr += res;
+ }
+
+ /* This code only does absolute seeks. */
+ block[0] = pfd->handle;
+ block[1] = ptr;
+ res = checkerror (call_host (SEMIHOSTING_SYS_SEEK, block));
+
+ /* At this point ptr is the current file position. */
+ if (res >= 0)
+ {
+ pfd->pos = ptr;
+ return ptr;
+ }
+ else
+ {
+ return -1;
+ }
+}
+
+int _lseek (int fd, int ptr, int dir)
+{
+ return _swilseek (fd, ptr, dir);
+}
+
+/* fh, is a valid internal file handle.
+ Returns the number of bytes *not* written. */
+int _swiwrite (int fh, char* ptr, int len)
+{
+ int block[3];
+
+ block[0] = fh;
+ block[1] = (int) ptr;
+ block[2] = len;
+
+ return checkerror (call_host (SEMIHOSTING_SYS_WRITE, block));
+}
+
+/* fd, is a user file descriptor. */
+int _write (int fd, char* ptr, int len)
+{
+ int res;
+ struct fdent *pfd;
+
+ pfd = findslot (fd);
+ if (pfd == NULL)
+ {
+ errno = EBADF;
+ return -1;
+ }
+
+ res = _swiwrite (pfd->handle, ptr, len);
+
+ /* Clearly an error. */
+ if (res < 0)
+ {
+ return -1;
+ }
+
+ pfd->pos += len - res;
+
+ /* We wrote 0 bytes?
+ Retrieve errno just in case. */
+ if ((len - res) == 0)
+ {
+ return error (0);
+ }
+
+ return (len - res);
+}
+
+int _swiopen (const char* path, int flags)
+{
+ int aflags = 0, fh;
+ uint32_t block[3];
+
+ int fd = newslot ();
+
+ if (fd == -1)
+ {
+ errno = EMFILE;
+ return -1;
+ }
+
+ /* It is an error to open a file that already exists. */
+ if ((flags & O_CREAT) && (flags & O_EXCL))
+ {
+ struct stat st;
+ int res;
+ res = _stat (path, &st);
+ if (res != -1)
+ {
+ errno = EEXIST;
+ return -1;
+ }
+ }
+
+ /* The flags are Unix-style, so we need to convert them. */
+#ifdef O_BINARY
+ if (flags & O_BINARY)
+ {
+ aflags |= 1;
+ }
+#endif
+
+ /* In O_RDONLY we expect aflags == 0. */
+
+ if (flags & O_RDWR)
+ {
+ aflags |= 2;
+ }
+
+ if ((flags & O_CREAT) || (flags & O_TRUNC) || (flags & O_WRONLY))
+ {
+ aflags |= 4;
+ }
+
+ if (flags & O_APPEND)
+ {
+ /* Can't ask for w AND a; means just 'a'. */
+ aflags &= ~4;
+ aflags |= 8;
+ }
+
+ block[0] = (uint32_t) path;
+ block[2] = strlen (path);
+ block[1] = (uint32_t) aflags;
+
+ fh = call_host (SEMIHOSTING_SYS_OPEN, block);
+
+ /* Return a user file descriptor or an error. */
+ if (fh >= 0)
+ {
+ openfiles[fd].handle = fh;
+ openfiles[fd].pos = 0;
+ return fd;
+ }
+ else
+ {
+ return error (fh);
+ }
+}
+
+int _open (const char* path, int flags, ...)
+{
+ return _swiopen (path, flags);
+}
+
+/* fh, is a valid internal file handle. */
+int _swiclose (int fh)
+{
+ return checkerror (call_host (SEMIHOSTING_SYS_CLOSE, &fh));
+}
+
+/* fd, is a user file descriptor. */
+int _close (int fd)
+{
+ int res;
+ struct fdent *pfd;
+
+ pfd = findslot (fd);
+ if (pfd == NULL)
+ {
+ errno = EBADF;
+ return -1;
+ }
+
+ /* Handle stderr == stdout. */
+ if ((fd == 1 || fd == 2) && (openfiles[1].handle == openfiles[2].handle))
+ {
+ pfd->handle = -1;
+ return 0;
+ }
+
+ /* Attempt to close the handle. */
+ res = _swiclose (pfd->handle);
+
+ /* Reclaim handle? */
+ if (res == 0)
+ {
+ pfd->handle = -1;
+ }
+
+ return res;
+}
+
+int __attribute__((weak))
+_getpid (int n __attribute__ ((unused)))
+{
+ return 1;
+}
+
+int
+_swistat (int fd, struct stat* st)
+{
+ struct fdent *pfd;
+ int res;
+
+ pfd = findslot (fd);
+ if (pfd == NULL)
+ {
+ errno = EBADF;
+ return -1;
+ }
+
+ /* Always assume a character device,
+ with 1024 byte blocks. */
+ st->st_mode |= S_IFCHR;
+ st->st_blksize = 1024;
+ res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, &pfd->handle));
+ if (res == -1)
+ {
+ return -1;
+ }
+
+ /* Return the file size. */
+ st->st_size = res;
+ return 0;
+}
+
+int __attribute__((weak))
+_fstat (int fd, struct stat* st)
+{
+ memset (st, 0, sizeof(*st));
+ return _swistat (fd, st);
+}
+
+int __attribute__((weak))
+_stat (const char*fname, struct stat *st)
+{
+ int fd, res;
+ memset (st, 0, sizeof(*st));
+ /* The best we can do is try to open the file readonly.
+ If it exists, then we can guess a few things about it. */
+ if ((fd = _open (fname, O_RDONLY)) == -1)
+ {
+ return -1;
+ }
+ st->st_mode |= S_IFREG | S_IREAD;
+ res = _swistat (fd, st);
+ /* Not interested in the error. */
+ _close (fd);
+ return res;
+}
+
+int __attribute__((weak))
+_link (void)
+{
+ errno = ENOSYS;
+ return -1;
+}
+
+int _unlink (const char* path)
+{
+ int res;
+ uint32_t block[2];
+ block[0] = (uint32_t) path;
+ block[1] = strlen (path);
+ res = call_host (SEMIHOSTING_SYS_REMOVE, block);
+
+ if (res == -1)
+ {
+ return error (res);
+ }
+ return 0;
+}
+
+int _gettimeofday (struct timeval* tp, void* tzvp)
+{
+ struct timezone* tzp = tzvp;
+ if (tp)
+ {
+ /* Ask the host for the seconds since the Unix epoch. */
+ tp->tv_sec = call_host (SEMIHOSTING_SYS_TIME, NULL);
+ tp->tv_usec = 0;
+ }
+
+ /* Return fixed data for the timezone. */
+ if (tzp)
+ {
+ tzp->tz_minuteswest = 0;
+ tzp->tz_dsttime = 0;
+ }
+
+ return 0;
+}
+
+/* Return a clock that ticks at 100Hz. */
+clock_t _clock (void)
+{
+ clock_t timeval;
+
+ timeval = (clock_t) call_host (SEMIHOSTING_SYS_CLOCK, NULL);
+ return timeval;
+}
+
+/* Return a clock that ticks at 100Hz. */
+clock_t
+_times (struct tms* tp)
+{
+ clock_t timeval = _clock ();
+
+ if (tp)
+ {
+ tp->tms_utime = timeval; /* user time */
+ tp->tms_stime = 0; /* system time */
+ tp->tms_cutime = 0; /* user time, children */
+ tp->tms_cstime = 0; /* system time, children */
+ }
+
+ return timeval;
+}
+
+int _isatty (int fd)
+{
+ struct fdent *pfd;
+ int tty;
+
+ pfd = findslot (fd);
+ if (pfd == NULL)
+ {
+ errno = EBADF;
+ return 0;
+ }
+
+ tty = call_host (SEMIHOSTING_SYS_ISTTY, &pfd->handle);
+
+ if (tty == 1)
+ {
+ return 1;
+ }
+
+ errno = get_errno ();
+ return 0;
+}
+
+int _system (const char* s)
+{
+ uint32_t block[2];
+ int e;
+
+ /* Hmmm. The ARM debug interface specification doesn't say whether
+ SYS_SYSTEM does the right thing with a null argument, or assign any
+ meaning to its return value. Try to do something reasonable.... */
+ if (!s)
+ {
+ return 1; /* maybe there is a shell available? we can hope. :-P */
+ }
+ block[0] = (uint32_t) s;
+ block[1] = strlen (s);
+ e = checkerror (call_host (SEMIHOSTING_SYS_SYSTEM, block));
+ if ((e >= 0) && (e < 256))
+ {
+ /* We have to convert e, an exit status to the encoded status of
+ the command. To avoid hard coding the exit status, we simply
+ loop until we find the right position. */
+ int exit_code;
+
+ for (exit_code = e; e && WEXITSTATUS (e) != exit_code; e <<= 1)
+ {
+ continue;
+ }
+ }
+ return e;
+}
+
+int _rename (const char* oldpath, const char* newpath)
+{
+ uint32_t block[4];
+ block[0] = (uint32_t) oldpath;
+ block[1] = strlen (oldpath);
+ block[2] = (uint32_t) newpath;
+ block[3] = strlen (newpath);
+ return checkerror (call_host (SEMIHOSTING_SYS_RENAME, block)) ? -1 : 0;
+}
+
+// ----------------------------------------------------------------------------
+// Required by Google Tests
+
+int mkdir (const char *path __attribute__((unused)), mode_t mode __attribute__((unused)))
+{
+#if 0
+ // always return true
+ return 0;
+#else
+ errno = ENOSYS;
+ return -1;
+#endif
+}
+
+char *getcwd (char *buf, size_t size)
+{
+ // no cwd available via semihosting, so we use the temporary folder
+ strncpy (buf, "/tmp", size);
+ return buf;
+}
+
+#endif // defined OS_USE_SEMIHOSTING
+
+#endif // __STDC_HOSTED__ == 1
--- /dev/null
+
+#ifndef ARM_SEMIHOSTING_H_
+#define ARM_SEMIHOSTING_H_
+
+// ----------------------------------------------------------------------------
+
+// Semihosting operations.
+enum OperationNumber
+{
+ // Regular operations
+ SEMIHOSTING_EnterSVC = 0x17,
+ SEMIHOSTING_ReportException = 0x18,
+ SEMIHOSTING_SYS_CLOSE = 0x02,
+ SEMIHOSTING_SYS_CLOCK = 0x10,
+ SEMIHOSTING_SYS_ELAPSED = 0x30,
+ SEMIHOSTING_SYS_ERRNO = 0x13,
+ SEMIHOSTING_SYS_FLEN = 0x0C,
+ SEMIHOSTING_SYS_GET_CMDLINE = 0x15,
+ SEMIHOSTING_SYS_HEAPINFO = 0x16,
+ SEMIHOSTING_SYS_ISERROR = 0x08,
+ SEMIHOSTING_SYS_ISTTY = 0x09,
+ SEMIHOSTING_SYS_OPEN = 0x01,
+ SEMIHOSTING_SYS_READ = 0x06,
+ SEMIHOSTING_SYS_READC = 0x07,
+ SEMIHOSTING_SYS_REMOVE = 0x0E,
+ SEMIHOSTING_SYS_RENAME = 0x0F,
+ SEMIHOSTING_SYS_SEEK = 0x0A,
+ SEMIHOSTING_SYS_SYSTEM = 0x12,
+ SEMIHOSTING_SYS_TICKFREQ = 0x31,
+ SEMIHOSTING_SYS_TIME = 0x11,
+ SEMIHOSTING_SYS_TMPNAM = 0x0D,
+ SEMIHOSTING_SYS_WRITE = 0x05,
+ SEMIHOSTING_SYS_WRITEC = 0x03,
+ SEMIHOSTING_SYS_WRITE0 = 0x04,
+
+ // Codes returned by SEMIHOSTING_ReportException
+ ADP_Stopped_ApplicationExit = ((2 << 16) + 38),
+ ADP_Stopped_RunTimeError = ((2 << 16) + 35),
+
+};
+
+// ----------------------------------------------------------------------------
+
+// SWI numbers and reason codes for RDI (Angel) monitors.
+#define AngelSWI_ARM 0x123456
+#ifdef __thumb__
+#define AngelSWI 0xAB
+#else
+#define AngelSWI AngelSWI_ARM
+#endif
+// For thumb only architectures use the BKPT instruction instead of SWI.
+#if defined(__ARM_ARCH_7M__) \
+ || defined(__ARM_ARCH_7EM__) \
+ || defined(__ARM_ARCH_6M__) \
+ || defined(__ARM_ARCH_8M_BASE__)
+#define AngelSWIInsn "bkpt"
+#define AngelSWIAsm bkpt
+#else
+#define AngelSWIInsn "swi"
+#define AngelSWIAsm swi
+#endif
+
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+// Testing the local semihosting handler cannot use another BKPT, since this
+// configuration cannot trigger HaedFault exceptions while the debugger is
+// connected, so we use an illegal op code, that will trigger an
+// UsageFault exception.
+#define AngelSWITestFault "setend be"
+#define AngelSWITestFaultOpCode (0xB658)
+#endif
+
+static inline int
+__attribute__ ((always_inline))
+call_host (int reason, void* arg)
+{
+ int value;
+ asm volatile (
+
+ " mov r0, %[rsn] \n"
+ " mov r1, %[arg] \n"
+#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
+ " " AngelSWITestFault " \n"
+#else
+ " " AngelSWIInsn " %[swi] \n"
+#endif
+ " mov %[val], r0"
+
+ : [val] "=r" (value) /* Outputs */
+ : [rsn] "r" (reason), [arg] "r" (arg), [swi] "i" (AngelSWI) /* Inputs */
+ : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"
+ // Clobbers r0 and r1, and lr if in supervisor mode
+ );
+
+ // Accordingly to page 13-77 of ARM DUI 0040D other registers
+ // can also be clobbered. Some memory positions may also be
+ // changed by a system call, so they should not be kept in
+ // registers. Note: we are assuming the manual is right and
+ // Angel is respecting the APCS.
+ return value;
+}
+
+// ----------------------------------------------------------------------------
+
+// Function used in _exit() to return the status code as Angel exception.
+static inline void
+__attribute__ ((always_inline,noreturn))
+report_exception (int reason)
+{
+ call_host (SEMIHOSTING_ReportException, (void*) reason);
+
+ for (;;)
+ ;
+}
+
+// ----------------------------------------------------------------------------
+
+#endif // ARM_SEMIHOSTING_H_
--- /dev/null
+/****************************************************************************//**
+ * @file startup_M2351.S
+ * @version V1.00
+ * @brief CMSIS Device Startup File
+ *
+ * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+
+
+ .syntax unified
+ .arch armv8 - m.base
+
+ .section .stack
+ .align 3
+#ifndef Stack_Size
+ .equ Stack_Size, 0x00000800
+#endif
+ .global __StackTop
+ .global __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifndef Heap_Size
+ .equ Heap_Size, 0x00000100
+#endif
+
+ .global __HeapBase
+ .global __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .global __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long BOD_IRQHandler /* 0 */
+ .long IRC_IRQHandler /* 1 */
+ .long PWRWU_IRQHandler /* 2 */
+ .long SRAM_IRQHandler /* 3 */
+ .long CLKFAIL_IRQHandler /* 4 */
+ .long Default_Handler /* 5 */
+ .long RTC_IRQHandler /* 6 */
+ .long TAMPER_IRQHandler /* 7 */
+ .long WDT_IRQHandler /* 8 */
+ .long WWDT_IRQHandler /* 9 */
+ .long EINT0_IRQHandler /* 10 */
+ .long EINT1_IRQHandler /* 11 */
+ .long EINT2_IRQHandler /* 12 */
+ .long EINT3_IRQHandler /* 13 */
+ .long EINT4_IRQHandler /* 14 */
+ .long EINT5_IRQHandler /* 15 */
+ .long GPA_IRQHandler /* 16 */
+ .long GPB_IRQHandler /* 17 */
+ .long GPC_IRQHandler /* 18 */
+ .long GPD_IRQHandler /* 19 */
+ .long GPE_IRQHandler /* 20 */
+ .long GPF_IRQHandler /* 21 */
+ .long QSPI0_IRQHandler /* 22 */
+ .long SPI0_IRQHandler /* 23 */
+ .long BRAKE0_IRQHandler /* 24 */
+ .long EPWM0_P0_IRQHandler /* 25 */
+ .long EPWM0_P1_IRQHandler /* 26 */
+ .long EPWM0_P2_IRQHandler /* 27 */
+ .long BRAKE1_IRQHandler /* 28 */
+ .long EPWM1_P0_IRQHandler /* 29 */
+ .long EPWM1_P1_IRQHandler /* 30 */
+ .long EPWM1_P2_IRQHandler /* 31 */
+ .long TMR0_IRQHandler /* 32 */
+ .long TMR1_IRQHandler /* 33 */
+ .long TMR2_IRQHandler /* 34 */
+ .long TMR3_IRQHandler /* 35 */
+ .long UART0_IRQHandler /* 36 */
+ .long UART1_IRQHandler /* 37 */
+ .long I2C0_IRQHandler /* 38 */
+ .long I2C1_IRQHandler /* 39 */
+ .long PDMA0_IRQHandler /* 40 */
+ .long DAC_IRQHandler /* 41 */
+ .long EADC0_IRQHandler /* 42 */
+ .long EADC1_IRQHandler /* 43 */
+ .long ACMP01_IRQHandler /* 44 */
+ .long Default_Handler /* 45 */
+ .long EADC2_IRQHandler /* 46 */
+ .long EADC3_IRQHandler /* 47 */
+ .long UART2_IRQHandler /* 48 */
+ .long UART3_IRQHandler /* 49 */
+ .long Default_Handler /* 50 */
+ .long SPI1_IRQHandler /* 51 */
+ .long SPI2_IRQHandler /* 52 */
+ .long USBD_IRQHandler /* 53 */
+ .long USBH_IRQHandler /* 54 */
+ .long USBOTG_IRQHandler /* 55 */
+ .long CAN0_IRQHandler /* 56 */
+ .long Default_Handler /* 57 */
+ .long SC0_IRQHandler /* 58 */
+ .long SC1_IRQHandler /* 59 */
+ .long SC2_IRQHandler /* 60 */
+ .long Default_Handler /* 61 */
+ .long SPI3_IRQHandler /* 62 */
+ .long Default_Handler /* 63 */
+ .long SDH0_IRQHandler /* 64 */
+ .long Default_Handler /* 65 */
+ .long Default_Handler /* 66 */
+ .long Default_Handler /* 67 */
+ .long I2S0_IRQHandler /* 68 */
+ .long Default_Handler /* 69 */
+ .long OPA0_IRQHandler /* 70 */
+ .long CRPT_IRQHandler /* 71 */
+ .long GPG_IRQHandler /* 72 */
+ .long EINT6_IRQHandler /* 73 */
+ .long UART4_IRQHandler /* 74 */
+ .long UART5_IRQHandler /* 75 */
+ .long USCI0_IRQHandler /* 76 */
+ .long USCI1_IRQHandler /* 77 */
+ .long BPWM0_IRQHandler /* 78 */
+ .long BPWM1_IRQHandler /* 79 */
+ .long Default_Handler /* 80 */
+ .long Default_Handler /* 81 */
+ .long I2C2_IRQHandler /* 82 */
+ .long Default_Handler /* 83 */
+ .long QEI0_IRQHandler /* 84 */
+ .long QEI1_IRQHandler /* 85 */
+ .long ECAP0_IRQHandler /* 86 */
+ .long ECAP1_IRQHandler /* 87 */
+ .long GPH_IRQHandler /* 88 */
+ .long EINT7_IRQHandler /* 89 */
+ .long Default_Handler /* 90 */
+ .long Default_Handler /* 91 */
+ .long Default_Handler /* 92 */
+ .long Default_Handler /* 93 */
+ .long Default_Handler /* 94 */
+ .long Default_Handler /* 95 */
+ .long Default_Handler /* 96 */
+ .long Default_Handler /* 97 */
+ .long PDMA1_IRQHandler /* 98 */
+ .long SCU_IRQHandler /* 99 */
+ .long Default_Handler /* 100 */
+ .long TRNG_IRQHandler /* 101 */
+
+
+ .size __Vectors, . - __Vectors
+
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .global Reset_Handler
+ .type Reset_Handler, % function
+
+
+Reset_Handler:
+ /* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+ /* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, = __copy_table_start__
+ ldr r5, = __copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+ /* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, = __etext
+ ldr r2, = __data_start__
+ ldr r3, = __data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+ /* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+ /* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, = __zero_table_start__
+ ldr r4, = __zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+
+#elif defined (__STARTUP_CLEAR_BSS)
+ /* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, = __bss_start__
+ ldr r2, = __bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, % function
+
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+ /* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler BOD_IRQHandler
+ def_irq_handler IRC_IRQHandler
+ def_irq_handler PWRWU_IRQHandler
+ def_irq_handler SRAM_IRQHandler
+ def_irq_handler CLKFAIL_IRQHandler
+
+ def_irq_handler RTC_IRQHandler
+ def_irq_handler TAMPER_IRQHandler
+ def_irq_handler WDT_IRQHandler
+ def_irq_handler WWDT_IRQHandler
+ def_irq_handler EINT0_IRQHandler
+ def_irq_handler EINT1_IRQHandler
+ def_irq_handler EINT2_IRQHandler
+ def_irq_handler EINT3_IRQHandler
+ def_irq_handler EINT4_IRQHandler
+ def_irq_handler EINT5_IRQHandler
+ def_irq_handler GPA_IRQHandler
+ def_irq_handler GPB_IRQHandler
+ def_irq_handler GPC_IRQHandler
+ def_irq_handler GPD_IRQHandler
+ def_irq_handler GPE_IRQHandler
+ def_irq_handler GPF_IRQHandler
+ def_irq_handler QSPI0_IRQHandler
+ def_irq_handler SPI0_IRQHandler
+ def_irq_handler BRAKE0_IRQHandler
+ def_irq_handler EPWM0_P0_IRQHandler
+ def_irq_handler EPWM0_P1_IRQHandler
+ def_irq_handler EPWM0_P2_IRQHandler
+ def_irq_handler BRAKE1_IRQHandler
+ def_irq_handler EPWM1_P0_IRQHandler
+ def_irq_handler EPWM1_P1_IRQHandler
+ def_irq_handler EPWM1_P2_IRQHandler
+ def_irq_handler TMR0_IRQHandler
+ def_irq_handler TMR1_IRQHandler
+ def_irq_handler TMR2_IRQHandler
+ def_irq_handler TMR3_IRQHandler
+ def_irq_handler UART0_IRQHandler
+ def_irq_handler UART1_IRQHandler
+ def_irq_handler I2C0_IRQHandler
+ def_irq_handler I2C1_IRQHandler
+ def_irq_handler PDMA0_IRQHandler
+ def_irq_handler DAC_IRQHandler
+ def_irq_handler EADC0_IRQHandler
+ def_irq_handler EADC1_IRQHandler
+ def_irq_handler ACMP01_IRQHandler
+
+ def_irq_handler EADC2_IRQHandler
+ def_irq_handler EADC3_IRQHandler
+ def_irq_handler UART2_IRQHandler
+ def_irq_handler UART3_IRQHandler
+
+ def_irq_handler SPI1_IRQHandler
+ def_irq_handler SPI2_IRQHandler
+ def_irq_handler USBD_IRQHandler
+ def_irq_handler USBH_IRQHandler
+ def_irq_handler USBOTG_IRQHandler
+ def_irq_handler CAN0_IRQHandler
+
+ def_irq_handler SC0_IRQHandler
+ def_irq_handler SC1_IRQHandler
+ def_irq_handler SC2_IRQHandler
+
+ def_irq_handler SPI3_IRQHandler
+
+ def_irq_handler SDH0_IRQHandler
+
+
+
+ def_irq_handler I2S0_IRQHandler
+
+ def_irq_handler OPA0_IRQHandler
+ def_irq_handler CRPT_IRQHandler
+ def_irq_handler GPG_IRQHandler
+ def_irq_handler EINT6_IRQHandler
+ def_irq_handler UART4_IRQHandler
+ def_irq_handler UART5_IRQHandler
+ def_irq_handler USCI0_IRQHandler
+ def_irq_handler USCI1_IRQHandler
+ def_irq_handler BPWM0_IRQHandler
+ def_irq_handler BPWM1_IRQHandler
+
+
+ def_irq_handler I2C2_IRQHandler
+
+ def_irq_handler QEI0_IRQHandler
+ def_irq_handler QEI1_IRQHandler
+ def_irq_handler ECAP0_IRQHandler
+ def_irq_handler ECAP1_IRQHandler
+ def_irq_handler GPH_IRQHandler
+ def_irq_handler EINT7_IRQHandler
+
+
+
+
+
+
+
+
+ def_irq_handler PDMA1_IRQHandler
+ def_irq_handler SCU_IRQHandler
+
+ def_irq_handler TRNG_IRQHandler
+
+
+
+ /* ;int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0) */
+ .align 2
+ .thumb_func
+ .type SH_DoCommand, % function
+
+SH_DoCommand:
+
+ BKPT 0xAB /* ; Wait ICE or HardFault */
+ LDR R3, = SH_Return
+ MOV R4, lr
+ BLX R3 /* ; Call SH_Return. The return value is in R0 */
+ BX R4 /* ; Return value = R0 */
+ .size SH_DoCommand, . - SH_DoCommand
+
+ .align 2
+ .thumb_func
+ .global __PC
+ .type __PC, % function
+__PC:
+
+ MOV r0, lr
+ BLX lr
+ .size __PC, . - __PC
+
+
+ .end
--- /dev/null
+;/*---------------------------------------------------------------------------------------------------------*/\r
+;/* */\r
+;/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved. */\r
+;/* */\r
+;/*---------------------------------------------------------------------------------------------------------*/\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION CSTACK:DATA:NOROOT(3) ;; 8 bytes alignment\r
+\r
+ SECTION .intvec:CODE:NOROOT(2);; 4 bytes alignment\r
+\r
+ EXTERN SystemInit \r
+ EXTERN __iar_program_start\r
+ PUBLIC __vector_table\r
+ PUBLIC __Vectors\r
+\r
+ DATA\r
+__Vectors \r
+__vector_table\r
+ DCD sfe(CSTACK)\r
+ DCD Reset_Handler\r
+\r
+ DCD NMI_Handler\r
+ DCD HardFault_Handler\r
+ DCD 0\r
+ DCD 0\r
+ DCD 0\r
+ DCD 0\r
+ DCD 0\r
+ DCD 0\r
+ DCD 0\r
+ DCD SVC_Handler\r
+ DCD 0\r
+ DCD 0\r
+ DCD PendSV_Handler\r
+ DCD SysTick_Handler\r
+\r
+ ; External Interrupts\r
+ ; maximum of 32 External Interrupts are possible\r
+ DCD BOD_IRQHandler ; 0 \r
+ DCD IRC_IRQHandler ; 1 \r
+ DCD PWRWU_IRQHandler ; 2 \r
+ DCD SRAM_IRQHandler ; 3 \r
+ DCD CLKFAIL_IRQHandler ; 4 \r
+ DCD DEFAULT_IRQHandler ; 5 \r
+ DCD RTC_IRQHandler ; 6 \r
+ DCD TAMPER_IRQHandler ; 7 \r
+ DCD WDT_IRQHandler ; 8 \r
+ DCD WWDT_IRQHandler ; 9 \r
+ DCD EINT0_IRQHandler ; 10 \r
+ DCD EINT1_IRQHandler ; 11 \r
+ DCD EINT2_IRQHandler ; 12 \r
+ DCD EINT3_IRQHandler ; 13 \r
+ DCD EINT4_IRQHandler ; 14 \r
+ DCD EINT5_IRQHandler ; 15 \r
+ DCD GPA_IRQHandler ; 16 \r
+ DCD GPB_IRQHandler ; 17 \r
+ DCD GPC_IRQHandler ; 18 \r
+ DCD GPD_IRQHandler ; 19 \r
+ DCD GPE_IRQHandler ; 20 \r
+ DCD GPF_IRQHandler ; 21 \r
+ DCD QSPI0_IRQHandler ; 22 \r
+ DCD SPI0_IRQHandler ; 23 \r
+ DCD BRAKE0_IRQHandler ; 24 \r
+ DCD EPWM0_P0_IRQHandler ; 25 \r
+ DCD EPWM0_P1_IRQHandler ; 26 \r
+ DCD EPWM0_P2_IRQHandler ; 27 \r
+ DCD BRAKE1_IRQHandler ; 28 \r
+ DCD EPWM1_P0_IRQHandler ; 29 \r
+ DCD EPWM1_P1_IRQHandler ; 30 \r
+ DCD EPWM1_P2_IRQHandler ; 31 \r
+ DCD TMR0_IRQHandler ; 32 \r
+ DCD TMR1_IRQHandler ; 33 \r
+ DCD TMR2_IRQHandler ; 34 \r
+ DCD TMR3_IRQHandler ; 35 \r
+ DCD UART0_IRQHandler ; 36 \r
+ DCD UART1_IRQHandler ; 37 \r
+ DCD I2C0_IRQHandler ; 38 \r
+ DCD I2C1_IRQHandler ; 39 \r
+ DCD PDMA0_IRQHandler ; 40 \r
+ DCD DAC_IRQHandler ; 41 \r
+ DCD EADC0_IRQHandler ; 42 \r
+ DCD EADC1_IRQHandler ; 43 \r
+ DCD ACMP01_IRQHandler ; 44 \r
+ DCD DEFAULT_IRQHandler ; 45 \r
+ DCD EADC2_IRQHandler ; 46 \r
+ DCD EADC3_IRQHandler ; 47 \r
+ DCD UART2_IRQHandler ; 48 \r
+ DCD UART3_IRQHandler ; 49 \r
+ DCD DEFAULT_IRQHandler ; 50 \r
+ DCD SPI1_IRQHandler ; 51 \r
+ DCD SPI2_IRQHandler ; 52 \r
+ DCD USBD_IRQHandler ; 53 \r
+ DCD USBH_IRQHandler ; 54 \r
+ DCD USBOTG_IRQHandler ; 55 \r
+ DCD CAN0_IRQHandler ; 56 \r
+ DCD DEFAULT_IRQHandler ; 57 \r
+ DCD SC0_IRQHandler ; 58 \r
+ DCD SC1_IRQHandler ; 59 \r
+ DCD SC2_IRQHandler ; 60 \r
+ DCD DEFAULT_IRQHandler ; 61 \r
+ DCD SPI3_IRQHandler ; 62 \r
+ DCD DEFAULT_IRQHandler ; 63 \r
+ DCD SDH0_IRQHandler ; 64 \r
+ DCD DEFAULT_IRQHandler ; 65 \r
+ DCD DEFAULT_IRQHandler ; 66 \r
+ DCD DEFAULT_IRQHandler ; 67 \r
+ DCD I2S0_IRQHandler ; 68 \r
+ DCD DEFAULT_IRQHandler ; 69 \r
+ DCD OPA0_IRQHandler ; 70 \r
+ DCD CRPT_IRQHandler ; 71 \r
+ DCD GPG_IRQHandler ; 72 \r
+ DCD EINT6_IRQHandler ; 73 \r
+ DCD UART4_IRQHandler ; 74 \r
+ DCD UART5_IRQHandler ; 75 \r
+ DCD USCI0_IRQHandler ; 76 \r
+ DCD USCI1_IRQHandler ; 77 \r
+ DCD BPWM0_IRQHandler ; 78 \r
+ DCD BPWM1_IRQHandler ; 79 \r
+ DCD DEFAULT_IRQHandler ; 80 \r
+ DCD DEFAULT_IRQHandler ; 81 \r
+ DCD I2C2_IRQHandler ; 82 \r
+ DCD DEFAULT_IRQHandler ; 83 \r
+ DCD QEI0_IRQHandler ; 84 \r
+ DCD QEI1_IRQHandler ; 85 \r
+ DCD ECAP0_IRQHandler ; 86 \r
+ DCD ECAP1_IRQHandler ; 87 \r
+ DCD GPH_IRQHandler ; 88 \r
+ DCD EINT7_IRQHandler ; 89 \r
+ DCD SDH1_IRQHandler ; 90 \r
+ DCD DEFAULT_IRQHandler ; 91 \r
+ DCD DEFAULT_IRQHandler ; 92 \r
+ DCD DEFAULT_IRQHandler ; 93 \r
+ DCD DEFAULT_IRQHandler ; 94 \r
+ DCD DEFAULT_IRQHandler ; 95 \r
+ DCD DEFAULT_IRQHandler ; 96 \r
+ DCD DEFAULT_IRQHandler ; 97 \r
+ DCD PDMA1_IRQHandler ; 98 \r
+ DCD SCU_IRQHandler ; 99 \r
+ DCD LCD_IRQHandler ; 100\r
+ DCD TRNG_IRQHandler ; 101\r
+ \r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+ THUMB\r
+ PUBWEAK Reset_Handler \r
+ SECTION .text:CODE:NOROOT:REORDER(2) ; 4 bytes alignment\r
+Reset_Handler\r
+ \r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__iar_program_start\r
+ BX R0\r
+\r
+ PUBWEAK HardFault_Handler\r
+ PUBWEAK NMI_Handler \r
+ PUBWEAK SVC_Handler \r
+ PUBWEAK PendSV_Handler \r
+ PUBWEAK SysTick_Handler \r
+\r
+ PUBWEAK BOD_IRQHandler ; 0 \r
+ PUBWEAK IRC_IRQHandler ; 1 \r
+ PUBWEAK PWRWU_IRQHandler ; 2 \r
+ PUBWEAK SRAM_IRQHandler ; 3 \r
+ PUBWEAK CLKFAIL_IRQHandler ; 4 \r
+ ;PUBWEAK 0 ; 5 \r
+ PUBWEAK RTC_IRQHandler ; 6 \r
+ PUBWEAK TAMPER_IRQHandler ; 7 \r
+ PUBWEAK WDT_IRQHandler ; 8 \r
+ PUBWEAK WWDT_IRQHandler ; 9 \r
+ PUBWEAK EINT0_IRQHandler ; 10 \r
+ PUBWEAK EINT1_IRQHandler ; 11 \r
+ PUBWEAK EINT2_IRQHandler ; 12 \r
+ PUBWEAK EINT3_IRQHandler ; 13 \r
+ PUBWEAK EINT4_IRQHandler ; 14 \r
+ PUBWEAK EINT5_IRQHandler ; 15 \r
+ PUBWEAK GPA_IRQHandler ; 16 \r
+ PUBWEAK GPB_IRQHandler ; 17 \r
+ PUBWEAK GPC_IRQHandler ; 18 \r
+ PUBWEAK GPD_IRQHandler ; 19 \r
+ PUBWEAK GPE_IRQHandler ; 20 \r
+ PUBWEAK GPF_IRQHandler ; 21 \r
+ PUBWEAK QSPI0_IRQHandler ; 22 \r
+ PUBWEAK SPI0_IRQHandler ; 23 \r
+ PUBWEAK BRAKE0_IRQHandler ; 24 \r
+ PUBWEAK EPWM0_P0_IRQHandler ; 25 \r
+ PUBWEAK EPWM0_P1_IRQHandler ; 26 \r
+ PUBWEAK EPWM0_P2_IRQHandler ; 27 \r
+ PUBWEAK BRAKE1_IRQHandler ; 28 \r
+ PUBWEAK EPWM1_P0_IRQHandler ; 29 \r
+ PUBWEAK EPWM1_P1_IRQHandler ; 30 \r
+ PUBWEAK EPWM1_P2_IRQHandler ; 31 \r
+ PUBWEAK TMR0_IRQHandler ; 32 \r
+ PUBWEAK TMR1_IRQHandler ; 33 \r
+ PUBWEAK TMR2_IRQHandler ; 34 \r
+ PUBWEAK TMR3_IRQHandler ; 35 \r
+ PUBWEAK UART0_IRQHandler ; 36 \r
+ PUBWEAK UART1_IRQHandler ; 37 \r
+ PUBWEAK I2C0_IRQHandler ; 38 \r
+ PUBWEAK I2C1_IRQHandler ; 39 \r
+ PUBWEAK PDMA0_IRQHandler ; 40 \r
+ PUBWEAK DAC_IRQHandler ; 41 \r
+ PUBWEAK EADC0_IRQHandler ; 42 \r
+ PUBWEAK EADC1_IRQHandler ; 43 \r
+ PUBWEAK ACMP01_IRQHandler ; 44 \r
+ ;PUBWEAK 0 ; 45 \r
+ PUBWEAK EADC2_IRQHandler ; 46 \r
+ PUBWEAK EADC3_IRQHandler ; 47 \r
+ PUBWEAK UART2_IRQHandler ; 48 \r
+ PUBWEAK UART3_IRQHandler ; 49 \r
+ ;PUBWEAK 0 ; 50 \r
+ PUBWEAK SPI1_IRQHandler ; 51 \r
+ PUBWEAK SPI2_IRQHandler ; 52 \r
+ PUBWEAK USBD_IRQHandler ; 53 \r
+ PUBWEAK USBH_IRQHandler ; 54 \r
+ PUBWEAK USBOTG_IRQHandler ; 55 \r
+ PUBWEAK CAN0_IRQHandler ; 56 \r
+ PUBWEAK CAN1_IRQHandler ; 57 \r
+ PUBWEAK SC0_IRQHandler ; 58 \r
+ PUBWEAK SC1_IRQHandler ; 59 \r
+ PUBWEAK SC2_IRQHandler ; 60 \r
+ PUBWEAK SC3_IRQHandler ; 61 \r
+ PUBWEAK SPI3_IRQHandler ; 62 \r
+ ;PUBWEAK 0 ; 63 \r
+ PUBWEAK SDH0_IRQHandler ; 64 \r
+ ;PUBWEAK 0 ; 65 \r
+ ;PUBWEAK 0 ; 66 \r
+ ;PUBWEAK 0 ; 67 \r
+ PUBWEAK I2S0_IRQHandler ; 68 \r
+ ;PUBWEAK 0 ; 69 \r
+ PUBWEAK OPA0_IRQHandler ; 70 \r
+ PUBWEAK CRPT_IRQHandler ; 71 \r
+ PUBWEAK GPG_IRQHandler ; 72 \r
+ PUBWEAK EINT6_IRQHandler ; 73 \r
+ PUBWEAK UART4_IRQHandler ; 74 \r
+ PUBWEAK UART5_IRQHandler ; 75 \r
+ PUBWEAK USCI0_IRQHandler ; 76 \r
+ PUBWEAK USCI1_IRQHandler ; 77 \r
+ PUBWEAK BPWM0_IRQHandler ; 78 \r
+ PUBWEAK BPWM1_IRQHandler ; 79 \r
+ ;PUBWEAK 0 ; 80 \r
+ ;PUBWEAK 0 ; 81 \r
+ PUBWEAK I2C2_IRQHandler ; 82 \r
+ ;PUBWEAK 0 ; 83 \r
+ PUBWEAK QEI0_IRQHandler ; 84 \r
+ PUBWEAK QEI1_IRQHandler ; 85 \r
+ PUBWEAK ECAP0_IRQHandler ; 86 \r
+ PUBWEAK ECAP1_IRQHandler ; 87 \r
+ PUBWEAK GPH_IRQHandler ; 88 \r
+ PUBWEAK EINT7_IRQHandler ; 89 \r
+ PUBWEAK SDH1_IRQHandler ; 90 \r
+ ;PUBWEAK 0 ; 91 \r
+ ;PUBWEAK USBH_IRQHandler ; 92 \r
+ ;PUBWEAK 0 ; 93 \r
+ ;PUBWEAK 0 ; 94 \r
+ ;PUBWEAK 0 ; 95 \r
+ ;PUBWEAK 0 ; 96 \r
+ ;PUBWEAK 0 ; 97 \r
+ PUBWEAK PDMA1_IRQHandler ; 98 \r
+ PUBWEAK SCU_IRQHandler ; 99 \r
+ PUBWEAK LCD_IRQHandler ; 100\r
+ PUBWEAK TRNG_IRQHandler ; 101\r
+ \r
+\r
+\r
+ PUBWEAK DEFAULT_IRQHandler \r
+\r
+ SECTION .text:CODE:NOROOT:REORDER(2)\r
+\r
+HardFault_Handler\r
+NMI_Handler \r
+SVC_Handler \r
+PendSV_Handler \r
+SysTick_Handler \r
+\r
+BOD_IRQHandler ; 0 \r
+IRC_IRQHandler ; 1 \r
+PWRWU_IRQHandler ; 2 \r
+SRAM_IRQHandler ; 3 \r
+CLKFAIL_IRQHandler ; 4 \r
+;0 ; 5 \r
+RTC_IRQHandler ; 6 \r
+TAMPER_IRQHandler ; 7 \r
+WDT_IRQHandler ; 8 \r
+WWDT_IRQHandler ; 9 \r
+EINT0_IRQHandler ; 10 \r
+EINT1_IRQHandler ; 11 \r
+EINT2_IRQHandler ; 12 \r
+EINT3_IRQHandler ; 13 \r
+EINT4_IRQHandler ; 14 \r
+EINT5_IRQHandler ; 15 \r
+GPA_IRQHandler ; 16 \r
+GPB_IRQHandler ; 17 \r
+GPC_IRQHandler ; 18 \r
+GPD_IRQHandler ; 19 \r
+GPE_IRQHandler ; 20 \r
+GPF_IRQHandler ; 21 \r
+QSPI0_IRQHandler ; 22 \r
+SPI0_IRQHandler ; 23 \r
+BRAKE0_IRQHandler ; 24 \r
+EPWM0_P0_IRQHandler ; 25 \r
+EPWM0_P1_IRQHandler ; 26 \r
+EPWM0_P2_IRQHandler ; 27 \r
+BRAKE1_IRQHandler ; 28 \r
+EPWM1_P0_IRQHandler ; 29 \r
+EPWM1_P1_IRQHandler ; 30 \r
+EPWM1_P2_IRQHandler ; 31 \r
+TMR0_IRQHandler ; 32 \r
+TMR1_IRQHandler ; 33 \r
+TMR2_IRQHandler ; 34 \r
+TMR3_IRQHandler ; 35 \r
+UART0_IRQHandler ; 36 \r
+UART1_IRQHandler ; 37 \r
+I2C0_IRQHandler ; 38 \r
+I2C1_IRQHandler ; 39 \r
+PDMA0_IRQHandler ; 40 \r
+DAC_IRQHandler ; 41 \r
+EADC0_IRQHandler ; 42 \r
+EADC1_IRQHandler ; 43 \r
+ACMP01_IRQHandler ; 44 \r
+;0 ; 45 \r
+EADC2_IRQHandler ; 46 \r
+EADC3_IRQHandler ; 47 \r
+UART2_IRQHandler ; 48 \r
+UART3_IRQHandler ; 49 \r
+;0 ; 50 \r
+SPI1_IRQHandler ; 51 \r
+SPI2_IRQHandler ; 52 \r
+USBD_IRQHandler ; 53 \r
+USBH_IRQHandler ; 54 \r
+USBOTG_IRQHandler ; 55 \r
+CAN0_IRQHandler ; 56 \r
+CAN1_IRQHandler ; 57 \r
+SC0_IRQHandler ; 58 \r
+SC1_IRQHandler ; 59 \r
+SC2_IRQHandler ; 60 \r
+SC3_IRQHandler ; 61 \r
+SPI3_IRQHandler ; 62 \r
+;0 ; 63 \r
+SDH0_IRQHandler ; 64 \r
+;0 ; 65 \r
+;0 ; 66 \r
+;0 ; 67 \r
+I2S0_IRQHandler ; 68 \r
+;0 ; 69 \r
+OPA0_IRQHandler ; 70 \r
+CRPT_IRQHandler ; 71 \r
+GPG_IRQHandler ; 72 \r
+EINT6_IRQHandler ; 73 \r
+UART4_IRQHandler ; 74 \r
+UART5_IRQHandler ; 75 \r
+USCI0_IRQHandler ; 76 \r
+USCI1_IRQHandler ; 77 \r
+BPWM0_IRQHandler ; 78 \r
+BPWM1_IRQHandler ; 79 \r
+;0 ; 80 \r
+;0 ; 81 \r
+I2C2_IRQHandler ; 82 \r
+;0 ; 83 \r
+QEI0_IRQHandler ; 84 \r
+QEI1_IRQHandler ; 85 \r
+ECAP0_IRQHandler ; 86 \r
+ECAP1_IRQHandler ; 87 \r
+GPH_IRQHandler ; 88 \r
+EINT7_IRQHandler ; 89 \r
+SDH1_IRQHandler ; 90 \r
+;0 ; 91 \r
+;USBH_IRQHandler ; 92 \r
+;0 ; 93 \r
+;0 ; 94 \r
+;0 ; 95 \r
+;0 ; 96 \r
+;0 ; 97 \r
+PDMA1_IRQHandler ; 98 \r
+SCU_IRQHandler ; 99 \r
+LCD_IRQHandler ; 100\r
+TRNG_IRQHandler ; 101\r
+DEFAULT_IRQHandler\r
+ B DEFAULT_IRQHandler \r
+\r
+\r
+;void SH_ICE(void)\r
+ PUBLIC SH_ICE\r
+SH_ICE \r
+ CMP R2,#0\r
+ BEQ SH_End\r
+ STR R0,[R2] ; Save the return value to *pn32Out_R0\r
+\r
+;void SH_End(void)\r
+ PUBLIC SH_End\r
+SH_End\r
+ MOVS R0,#1 ; Set return value to 1\r
+ BX lr ; Return\r
+\r
+\r
+;int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)\r
+ PUBLIC SH_DoCommand\r
+SH_DoCommand\r
+ BKPT 0xAB ; This instruction will cause ICE trap or system HardFault\r
+ B SH_ICE\r
+SH_HardFault ; Captured by HardFault\r
+ MOVS R0,#0 ; Set return value to 0\r
+ BX lr ; Return\r
+ \r
+ \r
+ PUBLIC __PC\r
+__PC \r
+ MOV r0, lr\r
+ BLX lr\r
+ \r
+ END\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_M2351.c\r
+ * @version V2.00\r
+ * @brief System Setting Source File\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler 6 */\r
+#include <arm_cmse.h>\r
+#endif\r
+\r
+#include <stdio.h>\r
+#include <stdint.h>\r
+#include "NuMicro.h"\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+#include "partition_M2351.h"\r
+#endif\r
+\r
+extern void *__Vectors; /* see startup file */\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */\r
+uint32_t CyclesPerUs = (__HSI / 1000000UL);/*!< Cycles per micro second */\r
+uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */\r
+const uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, __HIRC48, 0UL, __HIRC};\r
+\r
+\r
+/**\r
+ * @brief Update the Variable SystemCoreClock\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to update the variable SystemCoreClock\r
+ * and must be called whenever the core clock is changed.\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ /* Update PLL Clock */\r
+ PllClock = CLK_GetPLLClockFreq();\r
+\r
+ /* Update System Core Clock */\r
+ SystemCoreClock = CLK_GetCPUFreq();\r
+\r
+ /* Update Cycles per micro second */\r
+ CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief System Initialization\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The necessary initialization of system. Global variables are forbidden here.\r
+ */\r
+void SystemInit(void)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ SCB->VTOR = (uint32_t) &__Vectors;\r
+#endif\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)\r
+ TZ_SAU_Setup();\r
+ SCU_Setup();\r
+ FMC_NSBA_Setup();\r
+#endif\r
+\r
+#ifdef INIT_SYSCLK_AT_BOOTING\r
+\r
+#endif\r
+\r
+}\r
+\r
+\r
+#if USE_ASSERT\r
+\r
+/**\r
+ * @brief Assert Error Message\r
+ *\r
+ * @param[in] file the source file name\r
+ * @param[in] line line number\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function prints the source file name and line number where\r
+ * the ASSERT_PARAM() error occurs, and then stops in an infinite loop.\r
+ */\r
+void AssertError(uint8_t * file, uint32_t line)\r
+{\r
+\r
+ printf("[%s] line %d : wrong parameters.\r\n", file, line);\r
+\r
+ /* Infinite loop */\r
+ while(1) ;\r
+}\r
+#endif\r
+\r
+\r
+#if (defined(__ICCARM__) && (__VER__ >= 7080000) && (__VER__ < 8020000))\r
+\r
+#if (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Process Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \return PSP Register value\r
+ */\r
+uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile("MRS %0, psp_ns" : "=r"(result));\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack));\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \return MSP Register value\r
+ */\r
+int32_t __TZ_get_MSP_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile("MRS %0, msp_ns" : "=r"(result));\r
+ return(result);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack));\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask (non-secure)\r
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+ \return Priority Mask value\r
+ */\r
+uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile("MRS %0, primask_ns" : "=r"(result));\r
+ return(result);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+ __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory");\r
+}\r
+\r
+\r
+#endif\r
+\r
+\r
+#endif\r
+\r
+\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file ACMP.h\r
+ * @version V0.10\r
+ * $Revision: 1 $\r
+ * $Date: 16/07/07 7:50p $\r
+ * @brief M0564 Series ACMP Driver Header File\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __ACMP_H__\r
+#define __ACMP_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup ACMP_Driver ACMP Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants\r
+ @{\r
+*/\r
+\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* ACMP_CTL constant definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define ACMP_CTL_FILTSEL_OFF (0UL << 13) /*!< ACMP_CTL setting for filter function disabled. */\r
+#define ACMP_CTL_FILTSEL_1PCLK (1UL << 13) /*!< ACMP_CTL setting for 1 PCLK filter count. */\r
+#define ACMP_CTL_FILTSEL_2PCLK (2UL << 13) /*!< ACMP_CTL setting for 2 PCLK filter count. */\r
+#define ACMP_CTL_FILTSEL_4PCLK (3UL << 13) /*!< ACMP_CTL setting for 4 PCLK filter count. */\r
+#define ACMP_CTL_FILTSEL_8PCLK (4UL << 13) /*!< ACMP_CTL setting for 8 PCLK filter count. */\r
+#define ACMP_CTL_FILTSEL_16PCLK (5UL << 13) /*!< ACMP_CTL setting for 16 PCLK filter count. */\r
+#define ACMP_CTL_FILTSEL_32PCLK (6UL << 13) /*!< ACMP_CTL setting for 32 PCLK filter count. */\r
+#define ACMP_CTL_FILTSEL_64PCLK (7UL << 13) /*!< ACMP_CTL setting for 64 PCLK filter count. */\r
+#define ACMP_CTL_INTPOL_RF (0UL << 8) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. */\r
+#define ACMP_CTL_INTPOL_R (1UL << 8) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. */\r
+#define ACMP_CTL_INTPOL_F (2UL << 8) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. */\r
+#define ACMP_CTL_POSSEL_P0 (0UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. */\r
+#define ACMP_CTL_POSSEL_P1 (1UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. */\r
+#define ACMP_CTL_POSSEL_P2 (2UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. */\r
+#define ACMP_CTL_POSSEL_P3 (3UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. */\r
+#define ACMP_CTL_NEGSEL_PIN (0UL << 4) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */\r
+#define ACMP_CTL_NEGSEL_CRV (1UL << 4) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. */\r
+#define ACMP_CTL_NEGSEL_VBG (2UL << 4) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. */\r
+#define ACMP_CTL_NEGSEL_DAC (3UL << 4) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. */\r
+#define ACMP_CTL_HYSTERESIS_30MV (3UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. */\r
+#define ACMP_CTL_HYSTERESIS_20MV (2UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. */\r
+#define ACMP_CTL_HYSTERESIS_10MV (1UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. */\r
+#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << 2) /*!< ACMP_CTL setting for disabling the hysteresis function. */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* ACMP_VREF constant definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define ACMP_VREF_CRVSSEL_VDDA (0UL << 6) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage */\r
+#define ACMP_VREF_CRVSSEL_INTVREF (1UL << 6) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage */\r
+\r
+\r
+/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Define Macros and functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * @brief This macro is used to enable output inverse function\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function.\r
+ */\r
+#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable output inverse function\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function.\r
+ */\r
+#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to select ACMP negative input source\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @param[in] u32Src is comparator negative input selection. Including:\r
+ * - \ref ACMP_CTL_NEGSEL_PIN\r
+ * - \ref ACMP_CTL_NEGSEL_CRV\r
+ * - \ref ACMP_CTL_NEGSEL_VBG\r
+ * - \ref ACMP_CTL_NEGSEL_DAC\r
+ * @return None\r
+ * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input.\r
+ */\r
+#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src))\r
+\r
+/**\r
+ * @brief This macro is used to enable hysteresis function\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ */\r
+#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV)\r
+\r
+/**\r
+ * @brief This macro is used to disable hysteresis function\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will set HYSSEL of ACMP_CTL register to disable hysteresis function.\r
+ */\r
+#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to select hysteresis level\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @param[in] u32HysSel The hysteresis function option. Including:\r
+ * - \ref ACMP_CTL_HYSTERESIS_30MV\r
+ * - \ref ACMP_CTL_HYSTERESIS_20MV\r
+ * - \ref ACMP_CTL_HYSTERESIS_10MV\r
+ * - \ref ACMP_CTL_HYSTERESIS_DISABLE\r
+ * @return None\r
+ */\r
+#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel))\r
+\r
+/**\r
+ * @brief This macro is used to enable interrupt\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function.\r
+ * If wake-up function is enabled, the wake-up interrupt will be enabled as well.\r
+ */\r
+#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable interrupt\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function.\r
+ */\r
+#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to enable ACMP\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator.\r
+ */\r
+#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable ACMP\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.\r
+ */\r
+#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to get ACMP output value\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return ACMP output value\r
+ * @details This macro will return the ACMP output value.\r
+ */\r
+#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0)\r
+\r
+/**\r
+ * @brief This macro is used to get ACMP interrupt flag\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return ACMP interrupt occurred (1) or not (0)\r
+ * @details This macro will return the ACMP interrupt flag.\r
+ */\r
+#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0)\r
+\r
+/**\r
+ * @brief This macro is used to clear ACMP interrupt flag\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag.\r
+ */\r
+#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))\r
+\r
+/**\r
+ * @brief This macro is used to clear ACMP wake-up interrupt flag\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag.\r
+ */\r
+#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum))))\r
+\r
+/**\r
+ * @brief This macro is used to enable ACMP wake-up function\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function.\r
+ */\r
+#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable ACMP wake-up function\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function.\r
+ */\r
+#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to select ACMP positive input pin\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @param[in] u32Pin Comparator positive pin selection. Including:\r
+ * - \ref ACMP_CTL_POSSEL_P0\r
+ * - \ref ACMP_CTL_POSSEL_P1\r
+ * - \ref ACMP_CTL_POSSEL_P2\r
+ * - \ref ACMP_CTL_POSSEL_P3\r
+ * @return None\r
+ * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin.\r
+ */\r
+#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))\r
+\r
+/**\r
+ * @brief This macro is used to enable ACMP filter function\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function.\r
+ */\r
+#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable ACMP filter function\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function.\r
+ */\r
+#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to set ACMP filter function\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @param[in] u32Cnt is comparator filter count setting.\r
+ * - \ref ACMP_CTL_FILTSEL_OFF\r
+ * - \ref ACMP_CTL_FILTSEL_1PCLK\r
+ * - \ref ACMP_CTL_FILTSEL_2PCLK\r
+ * - \ref ACMP_CTL_FILTSEL_4PCLK\r
+ * - \ref ACMP_CTL_FILTSEL_8PCLK\r
+ * - \ref ACMP_CTL_FILTSEL_16PCLK\r
+ * - \ref ACMP_CTL_FILTSEL_32PCLK\r
+ * - \ref ACMP_CTL_FILTSEL_64PCLK\r
+ * @return None\r
+ * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]).\r
+ */\r
+#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))\r
+\r
+/**\r
+ * @brief This macro is used to select comparator reference voltage\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32Level The comparator reference voltage setting.\r
+ * The formula is:\r
+ * comparator reference voltage = CRV source voltage x (1/6 + u32Level/24)\r
+ * The range of u32Level is 0 ~ 15.\r
+ * @return None\r
+ * @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]).\r
+ */\r
+#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<<ACMP_VREF_CRVCTL_Pos))\r
+\r
+/**\r
+ * @brief This macro is used to select the source of CRV\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32Src is the source of CRV. Including:\r
+ * - \ref ACMP_VREF_CRVSSEL_VDDA\r
+ * - \ref ACMP_VREF_CRVSSEL_INTVREF\r
+ * @return None\r
+ * @details The source of CRV can be VDDA or internal reference voltage. The internal reference voltage level is determined by SYS_VREFCTL register.\r
+ */\r
+#define ACMP_SELECT_CRV_SRC(acmp, u32Src) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src))\r
+\r
+/**\r
+ * @brief This macro is used to select ACMP interrupt condition\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @param[in] u32Cond Comparator interrupt condition selection. Including:\r
+ * - \ref ACMP_CTL_INTPOL_RF\r
+ * - \ref ACMP_CTL_INTPOL_R\r
+ * - \ref ACMP_CTL_INTPOL_F\r
+ * @return None\r
+ * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge.\r
+ */\r
+#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond))\r
+\r
+/**\r
+ * @brief This macro is used to enable ACMP window latch mode\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode.\r
+ * When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch\r
+ * block; when ACMP0/1_WLAT pin is at low level, the output of window latch block,\r
+ * WLATOUT, is frozen.\r
+ */\r
+#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable ACMP window latch mode\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode.\r
+ */\r
+#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to enable ACMP window compare mode\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode.\r
+ * When window compare mode is enabled, user can connect the specific analog voltage\r
+ * source to either the positive inputs of both comparators or the negative inputs of\r
+ * both comparators. The upper bound and lower bound of the designated range are\r
+ * determined by the voltages applied to the other inputs of both comparators. If the\r
+ * output of a comparator is low and the other comparator outputs high, which means two\r
+ * comparators implies the upper and lower bound. User can directly monitor a specific\r
+ * analog voltage source via ACMPWO (ACMP_STATUS[16]).\r
+ */\r
+#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable ACMP window compare mode\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum The ACMP number\r
+ * @return None\r
+ * @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode.\r
+ */\r
+#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk)\r
+\r
+\r
+\r
+\r
+/* Function prototype declaration */\r
+void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel);\r
+void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum);\r
+\r
+\r
+\r
+/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group ACMP_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __ACMP_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file bpwm.h\r
+ * @version V1.00\r
+ * @brief M2351 series BPWM driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __BPWM_H__\r
+#define __BPWM_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup BPWM_Driver BPWM Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants\r
+ @{\r
+*/\r
+#define BPWM_CHANNEL_NUM (6UL) /*!< BPWM channel number */\r
+#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask \hideinitializer */\r
+#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask \hideinitializer */\r
+#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask \hideinitializer */\r
+#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask \hideinitializer */\r
+#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask \hideinitializer */\r
+#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Counter Type Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define BPWM_UP_COUNTER (0UL) /*!< Up counter type */\r
+#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type */\r
+#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Aligned Type Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) */\r
+#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Output Level Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing */\r
+#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low */\r
+#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high */\r
+#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Synchronous Start Function Control Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define BPWM_SSCTL_SSRC_PWM0 (0UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM0 */\r
+#define BPWM_SSCTL_SSRC_PWM1 (1UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM1 */\r
+#define BPWM_SSCTL_SSRC_BPWM0 (2UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 */\r
+#define BPWM_SSCTL_SSRC_BPWM1 (3UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Trigger Source Select Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define BPWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< BPWM trigger ADC while counter of even channel matches zero point \hideinitializer */\r
+#define BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< BPWM trigger ADC while counter of even channel matches period point \hideinitializer */\r
+#define BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< BPWM trigger ADC while counter of even channel matches zero or period point \hideinitializer */\r
+#define BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT (3UL) /*!< BPWM trigger ADC while counter of even channel matches up count to comparator point \hideinitializer */\r
+#define BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT (4UL) /*!< BPWM trigger ADC while counter of even channel matches down count to comparator point \hideinitializer */\r
+#define BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT (8UL) /*!< BPWM trigger ADC while counter of odd channel matches up count to comparator point \hideinitializer */\r
+#define BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT (9UL) /*!< BPWM trigger ADC while counter of odd channel matches down count to comparator point \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Capture Control Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define BPWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< BPWM capture interrupt if channel has rising transition */\r
+#define BPWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< BPWM capture interrupt if channel has falling transition */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Duty Interrupt Type Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (1 << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM duty interrupt triggered if down count match comparator \hideinitializer */\r
+#define BPWM_DUTY_INT_UP_COUNT_MATCH_CMP (1 << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM duty interrupt triggered if up down match comparator \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Load Mode Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define BPWM_LOAD_MODE_IMMEDIATE (1 << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM immediately load mode \hideinitializer */\r
+#define BPWM_LOAD_MODE_CENTER (1 << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM center load mode \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Clock Source Select Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define BPWM_CLKSRC_BPWM_CLK (0UL) /*!< BPWM Clock source selects to BPWM0_CLK or BPWM1_CLK \hideinitializer */\r
+#define BPWM_CLKSRC_TIMER0 (1UL) /*!< BPWM Clock source selects to TIMER0 overflow \hideinitializer */\r
+#define BPWM_CLKSRC_TIMER1 (2UL) /*!< BPWM Clock source selects to TIMER1 overflow \hideinitializer */\r
+#define BPWM_CLKSRC_TIMER2 (3UL) /*!< BPWM Clock source selects to TIMER2 overflow \hideinitializer */\r
+#define BPWM_CLKSRC_TIMER3 (4UL) /*!< BPWM Clock source selects to TIMER3 overflow \hideinitializer */\r
+\r
+/*@}*/ /* end of group BPWM_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Enable timer synchronous start counting function of specified channel(s)\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.\r
+ * @param[in] u32SyncSrc Synchronous start source selection, valid values are:\r
+ * - \ref BPWM_SSCTL_SSRC_PWM0\r
+ * - \ref BPWM_SSCTL_SSRC_PWM1\r
+ * - \ref BPWM_SSCTL_SSRC_BPWM0\r
+ * - \ref BPWM_SSCTL_SSRC_BPWM1\r
+ * @return None\r
+ * @details This macro is used to enable timer synchronous start counting function of specified channel(s).\r
+ * @note All channels share channel 0's setting.\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_ENABLE_TIMER_SYNC(bpwm, u32ChannelMask, u32SyncSrc) ((bpwm)->SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk)\r
+\r
+/**\r
+ * @brief Disable timer synchronous start counting function of specified channel(s)\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.\r
+ * @return None\r
+ * @details This macro is used to disable timer synchronous start counting function of specified channel(s).\r
+ * @note All channels share channel 0's setting.\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk)\r
+\r
+/**\r
+ * @brief This macro enable BPWM counter synchronous start counting function.\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @return None\r
+ * @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time.\r
+ * To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC().\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk)\r
+\r
+/**\r
+ * @brief This macro enable output inverter of specified channel(s)\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel\r
+ * Bit 0 represents channel 0, bit 1 represents channel 1...\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask))\r
+\r
+/**\r
+ * @brief This macro get captured rising data\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT)\r
+\r
+/**\r
+ * @brief This macro get captured falling data\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT)\r
+\r
+/**\r
+ * @brief This macro mask output logic to high or low\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel\r
+ * Bit 0 represents channel 0, bit 1 represents channel 1...\r
+ * @param[in] u32LevelMask Output logic to high or low\r
+ * @return None\r
+ * @details This macro is used to mask output logic to high or low of specified channel(s).\r
+ * @note If u32ChannelMask parameter is 0, then mask function will be disabled.\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \\r
+ { \\r
+ (bpwm)->MSKEN = (u32ChannelMask); \\r
+ (bpwm)->MSK = (u32LevelMask); \\r
+ }\r
+\r
+/**\r
+ * @brief This macro set the prescaler of all channels\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler))\r
+\r
+/**\r
+ * @brief This macro set the duty of the selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF\r
+ * @return None\r
+ * @note This new setting will take effect on next BPWM period\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))\r
+\r
+/**\r
+ * @brief This macro get the duty of the selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF\r
+ * @details This macro is used to get the comparator of specified channel.\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)])\r
+\r
+/**\r
+ * @brief This macro set the period of all channels\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF\r
+ * @return None\r
+ * @note This new setting will take effect on next BPWM period\r
+ * @note BPWM counter will stop if period length set to 0\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR))\r
+\r
+/**\r
+ * @brief This macro get the period of all channels\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD)\r
+\r
+/**\r
+ * @brief This macro set the BPWM aligned type\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.\r
+ * @param[in] u32AlignedType BPWM aligned type, valid values are:\r
+ * - \ref BPWM_EDGE_ALIGNED\r
+ * - \ref BPWM_CENTER_ALIGNED\r
+ * @return None\r
+ * @note All channels share channel 0's setting.\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType))\r
+\r
+/**\r
+ * @brief Clear counter of channel 0\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.\r
+ * @return None\r
+ * @details This macro is used to clear counter of channel 0\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk))\r
+\r
+/**\r
+ * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel\r
+ * Bit 0 represents channel 0, bit 1 represents channel 1...\r
+ * @param[in] u32ZeroLevel output level at zero point, valid values are:\r
+ * - \ref BPWM_OUTPUT_NOTHING\r
+ * - \ref BPWM_OUTPUT_LOW\r
+ * - \ref BPWM_OUTPUT_HIGH\r
+ * - \ref BPWM_OUTPUT_TOGGLE\r
+ * @param[in] u32CmpUpLevel output level at compare up point, valid values are:\r
+ * - \ref BPWM_OUTPUT_NOTHING\r
+ * - \ref BPWM_OUTPUT_LOW\r
+ * - \ref BPWM_OUTPUT_HIGH\r
+ * - \ref BPWM_OUTPUT_TOGGLE\r
+ * @param[in] u32PeriodLevel output level at period(center) point, valid values are:\r
+ * - \ref BPWM_OUTPUT_NOTHING\r
+ * - \ref BPWM_OUTPUT_LOW\r
+ * - \ref BPWM_OUTPUT_HIGH\r
+ * - \ref BPWM_OUTPUT_TOGGLE\r
+ * @param[in] u32CmpDownLevel output level at compare down point, valid values are:\r
+ * - \ref BPWM_OUTPUT_NOTHING\r
+ * - \ref BPWM_OUTPUT_LOW\r
+ * - \ref BPWM_OUTPUT_HIGH\r
+ * - \ref BPWM_OUTPUT_TOGGLE\r
+ * @return None\r
+ * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s)\r
+ * \hideinitializer\r
+ */\r
+#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \\r
+ do{ \\r
+ uint32_t i; \\r
+ for(i = 0UL; i < 6UL; i++) { \\r
+ if((u32ChannelMask) & (1UL << i)) { \\r
+ (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \\r
+ (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \\r
+ (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \\r
+ (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \\r
+ } \\r
+ } \\r
+ }while(0)\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Define BPWM functions prototype */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);\r
+uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);\r
+void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask);\r
+void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask);\r
+void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask);\r
+void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);\r
+void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);\r
+uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);\r
+void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);\r
+void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);\r
+void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);\r
+void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);\r
+void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);\r
+void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);\r
+uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);\r
+void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);\r
+void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);\r
+void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);\r
+void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);\r
+uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);\r
+\r
+\r
+/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group BPWM_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __BPWM_H__ */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file can.h\r
+ * @version V1.00\r
+ * @brief M2351 Series CAN Driver Header File\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __CAN_H__\r
+#define __CAN_H__\r
+\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CAN_Driver CAN Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants\r
+ @{\r
+*/\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* CAN Test Mode Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CAN_NORMAL_MODE 0U /*!< CAN select normal mode */\r
+#define CAN_BASIC_MODE 1U /*!< CAN select basic mode */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Message ID Type Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CAN_STD_ID 0UL /*!< CAN select standard ID */\r
+#define CAN_EXT_ID 1UL /*!< CAN select extended ID */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Message Frame Type Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CAN_REMOTE_FRAME 0 /*!< CAN frame select remote frame */\r
+#define CAN_DATA_FRAME 1 /*!< CAN frame select data frame */\r
+\r
+/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs\r
+ @{\r
+*/\r
+/**\r
+ * @details CAN message structure\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t IdType; /*!< ID type */\r
+ uint32_t FrameType; /*!< Frame type */\r
+ uint32_t Id; /*!< Message ID */\r
+ uint8_t DLC; /*!< Data length */\r
+ uint8_t Data[8]; /*!< Data */\r
+} STR_CANMSG_T;\r
+\r
+/**\r
+ * @details CAN mask message structure\r
+ */\r
+typedef struct\r
+{\r
+ uint8_t u8Xtd; /*!< Extended ID */\r
+ uint8_t u8Dir; /*!< Direction */\r
+ uint32_t u32Id; /*!< Message ID */\r
+ uint8_t u8IdType; /*!< ID type*/\r
+} STR_CANMASK_T;\r
+\r
+/*@}*/ /* end of group CAN_EXPORTED_STRUCTS */\r
+\r
+/** @cond HIDDEN_SYMBOLS */\r
+#define MSG(id) (id)\r
+/** @endcond HIDDEN_SYMBOLS */\r
+\r
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Get interrupt status.\r
+ *\r
+ * @param[in] can The base address of can module.\r
+ *\r
+ * @return CAN module status register value.\r
+ *\r
+ * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]),\r
+ * EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]).\r
+ */\r
+#define CAN_GET_INT_STATUS(can) ((can)->STATUS)\r
+\r
+/**\r
+ * @brief Get specified interrupt pending status.\r
+ *\r
+ * @param[in] can The base address of can module.\r
+ *\r
+ * @return The source of the interrupt.\r
+ *\r
+ * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt\r
+ * with the highest priority, disregarding their chronological order.\r
+ */\r
+#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR)\r
+\r
+/**\r
+ * @brief Disable wake-up function.\r
+ *\r
+ * @param[in] can The base address of can module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The macro is used to disable wake-up function.\r
+ */\r
+#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0)\r
+\r
+/**\r
+ * @brief Enable wake-up function.\r
+ *\r
+ * @param[in] can The base address of can module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details User can wake-up system when there is a falling edge in the CAN_Rx pin.\r
+ */\r
+#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk)\r
+\r
+/**\r
+ * @brief Get specified Message Object new data into bit value.\r
+ *\r
+ * @param[in] can The base address of can module.\r
+ * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31.\r
+ *\r
+ * @return Specified Message Object new data into bit value.\r
+ *\r
+ * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers\r
+ * or by the Message Handler after reception of a Data Frame or after a successful transmission.\r
+ */\r
+#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16)))\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Define CAN functions prototype */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);\r
+void CAN_Close(CAN_T *tCAN);\r
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);\r
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);\r
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);\r
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);\r
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg);\r
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg);\r
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);\r
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID);\r
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);\r
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg);\r
+int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum);\r
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask);\r
+void CAN_LeaveInitMode(CAN_T *tCAN);\r
+void CAN_WaitMsg(CAN_T *tCAN);\r
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN);\r
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);\r
+void CAN_LeaveTestMode(CAN_T *tCAN);\r
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj);\r
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg);\r
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg);\r
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast);\r
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast);\r
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg);\r
+\r
+\r
+/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group CAN_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CAN_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file clk.h\r
+ * @version V3.0\r
+ * @brief M2351 series Clock Controller (CLK) driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __CLK_H__\r
+#define __CLK_H__\r
+\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CLK_Driver CLK Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants\r
+ @{\r
+*/\r
+\r
+\r
+#define FREQ_2MHZ 2000000UL\r
+#define FREQ_8MHZ 8000000UL\r
+#define FREQ_24MHZ 24000000UL\r
+#define FREQ_48MHZ 48000000UL\r
+#define FREQ_64MHZ 64000000UL\r
+#define FREQ_96MHZ 96000000UL\r
+#define FREQ_144MHZ 144000000UL\r
+#define FREQ_200MHZ 200000000UL\r
+\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* CLKSEL0 constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as HXT */\r
+#define CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as LXT */\r
+#define CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as PLL */\r
+#define CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as LIRC */\r
+#define CLK_CLKSEL0_HCLKSEL_HIRC48 (0x05UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as HIRC48 */\r
+#define CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as HIRC */\r
+\r
+#define CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HXT */\r
+#define CLK_CLKSEL0_STCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as LXT */\r
+#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HXT */\r
+#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HCLK/2 */\r
+#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HIRC/2 */\r
+#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) /*!< Setting SysTick clock source as HCLK */\r
+\r
+#define CLK_CLKSEL0_SDH0SEL_HXT (0x00UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HXT */\r
+#define CLK_CLKSEL0_SDH0SEL_PLL (0x01UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as PLL */\r
+#define CLK_CLKSEL0_SDH0SEL_HCLK (0x02UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HCLK */\r
+#define CLK_CLKSEL0_SDH0SEL_HIRC (0x03UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL0_USBSEL_HIRC48 (0x00UL<<CLK_CLKSEL0_USBSEL_Pos) /*!< Setting USB clock source as HIRC48 */\r
+#define CLK_CLKSEL0_USBSEL_PLL (0x01UL<<CLK_CLKSEL0_USBSEL_Pos) /*!< Setting USB clock source as PLL */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* CLKSEL1 constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as LXT */\r
+#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as HCLK/2048 */\r
+#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as LIRC */\r
+\r
+#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as HXT */\r
+#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as LXT */\r
+#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as PCLK0 */\r
+#define CLK_CLKSEL1_TMR0SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external trigger */\r
+#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as LIRC */\r
+#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as HXT */\r
+#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as LXT */\r
+#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as PCLK0 */\r
+#define CLK_CLKSEL1_TMR1SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external trigger */\r
+#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as LIRC */\r
+#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as HXT */\r
+#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as LXT */\r
+#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as PCLK1 */\r
+#define CLK_CLKSEL1_TMR2SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external trigger */\r
+#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as LIRC */\r
+#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as HXT */\r
+#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as LXT */\r
+#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as PCLK1 */\r
+#define CLK_CLKSEL1_TMR3SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external trigger */\r
+#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as LIRC */\r
+#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as HXT */\r
+#define CLK_CLKSEL1_UART0SEL_PLL (0x1UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as PLL */\r
+#define CLK_CLKSEL1_UART0SEL_LXT (0x2UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as LXT */\r
+#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL1_UART1SEL_HXT (0x0UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as HXT */\r
+#define CLK_CLKSEL1_UART1SEL_PLL (0x1UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as PLL */\r
+#define CLK_CLKSEL1_UART1SEL_LXT (0x2UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as LXT */\r
+#define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HXT */\r
+#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as LXT */\r
+#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HCLK */\r
+#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HIRC */\r
+\r
+#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WWDT clock source as HCLK/2048 */\r
+#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WWDT clock source as LIRC */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* CLKSEL2 constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Setting EPWM0 clock source as PCLK0 */\r
+#define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Setting EPWM1 clock source as PCLK1 */\r
+\r
+#define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Setting BPWM0 clock source as PCLK0 */\r
+#define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Setting BPWM1 clock source as PCLK1 */\r
+\r
+#define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting QSPI0 clock source as HXT */\r
+#define CLK_CLKSEL2_QSPI0SEL_PLL (0x1UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting QSPI0 clock source as PLL */\r
+#define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting QSPI0 clock source as PCLK0 */\r
+#define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting QSPI0 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as HXT */\r
+#define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PLL */\r
+#define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PCLK1 */\r
+#define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as HXT */\r
+#define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PLL */\r
+#define CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PCLK0 */\r
+#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL2_SPI2SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as HXT */\r
+#define CLK_CLKSEL2_SPI2SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PLL */\r
+#define CLK_CLKSEL2_SPI2SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PCLK1 */\r
+#define CLK_CLKSEL2_SPI2SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL2_SPI3SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as HXT */\r
+#define CLK_CLKSEL2_SPI3SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PLL */\r
+#define CLK_CLKSEL2_SPI3SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PCLK0 */\r
+#define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as HIRC */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* CLKSEL3 constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as HXT */\r
+#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PLL */\r
+#define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PCLK0 */\r
+#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL3_SC1SEL_HXT (0x0UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as HXT */\r
+#define CLK_CLKSEL3_SC1SEL_PLL (0x1UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as PLL */\r
+#define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as PCLK1 */\r
+#define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL3_SC2SEL_HXT (0x0UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as HXT */\r
+#define CLK_CLKSEL3_SC2SEL_PLL (0x1UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as PLL */\r
+#define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as PCLK1 */\r
+#define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL3_RTCSEL_LXT (0x0UL<<CLK_CLKSEL3_RTCSEL_Pos) /*!< Setting RTC clock source as LXT */\r
+#define CLK_CLKSEL3_RTCSEL_LIRC (0x1UL<<CLK_CLKSEL3_RTCSEL_Pos) /*!< Setting RTC clock source as LIRC */\r
+\r
+#define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as HXT */\r
+#define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as PLL */\r
+#define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as PCLK0 */\r
+#define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL3_UART2SEL_HXT (0x0UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as HXT */\r
+#define CLK_CLKSEL3_UART2SEL_PLL (0x1UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as PLL */\r
+#define CLK_CLKSEL3_UART2SEL_LXT (0x2UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as LXT */\r
+#define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL3_UART3SEL_HXT (0x0UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as HXT */\r
+#define CLK_CLKSEL3_UART3SEL_PLL (0x1UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as PLL */\r
+#define CLK_CLKSEL3_UART3SEL_LXT (0x2UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as LXT */\r
+#define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL3_UART4SEL_HXT (0x0UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as HXT */\r
+#define CLK_CLKSEL3_UART4SEL_PLL (0x1UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as PLL */\r
+#define CLK_CLKSEL3_UART4SEL_LXT (0x2UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as LXT */\r
+#define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as HIRC */\r
+\r
+#define CLK_CLKSEL3_UART5SEL_HXT (0x0UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as HXT */\r
+#define CLK_CLKSEL3_UART5SEL_PLL (0x1UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as PLL */\r
+#define CLK_CLKSEL3_UART5SEL_LXT (0x2UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as LXT */\r
+#define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as HIRC */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* CLKDIV0 constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_CLKDIV0_HCLK(x) (((x)-1UL) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 */\r
+#define CLK_CLKDIV0_USB(x) (((x)-1UL) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 */\r
+#define CLK_CLKDIV0_UART0(x) (((x)-1UL) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 */\r
+#define CLK_CLKDIV0_UART1(x) (((x)-1UL) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 */\r
+#define CLK_CLKDIV0_EADC(x) (((x)-1UL) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 */\r
+#define CLK_CLKDIV0_SDH0(x) (((x)-1UL) << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* CLKDIV1 constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_CLKDIV1_SC0(x) (((x)-1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 */\r
+#define CLK_CLKDIV1_SC1(x) (((x)-1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 */\r
+#define CLK_CLKDIV1_SC2(x) (((x)-1UL) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* CLKDIV4 constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_CLKDIV4_UART2(x) (((x)-1UL) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 */\r
+#define CLK_CLKDIV4_UART3(x) (((x)-1UL) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 */\r
+#define CLK_CLKDIV4_UART4(x) (((x)-1UL) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 */\r
+#define CLK_CLKDIV4_UART5(x) (((x)-1UL) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* PCLKDIV constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_PCLKDIV_APB0DIV_HCLK (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK */\r
+#define CLK_PCLKDIV_APB0DIV_HCLK_DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK */\r
+#define CLK_PCLKDIV_APB0DIV_HCLK_DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK */\r
+#define CLK_PCLKDIV_APB0DIV_HCLK_DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK */\r
+#define CLK_PCLKDIV_APB0DIV_HCLK_DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK */\r
+#define CLK_PCLKDIV_APB0DIV_HCLK_DIV32 (0x5UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/32 HCLK */\r
+\r
+#define CLK_PCLKDIV_APB1DIV_HCLK (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK */\r
+#define CLK_PCLKDIV_APB1DIV_HCLK_DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK */\r
+#define CLK_PCLKDIV_APB1DIV_HCLK_DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK */\r
+#define CLK_PCLKDIV_APB1DIV_HCLK_DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK */\r
+#define CLK_PCLKDIV_APB1DIV_HCLK_DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK */\r
+#define CLK_PCLKDIV_APB1DIV_HCLK_DIV32 (0x5UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/32 HCLK */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* PLLCTL constant definitions. PLL = FIN * (2*NF) / NR / NO */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 2MHz < FIN/NR < 8MHz */\r
+#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 2MHz < FIN/NR < 8MHz */\r
+\r
+#define CLK_PLLCTL_NF(x) ((x)-2UL) /*!< x must be constant and 2 <= x <= 513. 96MHz < FIN*(2*NF)/NR < 200MHz */\r
+#define CLK_PLLCTL_NR(x) (((x)-1UL)<<9) /*!< x must be constant and 2 <= x <= 33. 2MHz < FIN/NR < 8MHz */\r
+\r
+#define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 */\r
+#define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 */\r
+#define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 */\r
+\r
+#define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48MHz PLL output with HXT */\r
+#define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48MHz PLL output with HIRC */\r
+\r
+#define CLK_PLLCTL_64MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 64MHz PLL output with HXT */\r
+#define CLK_PLLCTL_64MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 64Hz PLL output with HIRC */\r
+\r
+#define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96MHz PLL output with HXT */\r
+#define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96MHz PLL output with HIRC */\r
+\r
+#define CLK_PLLCTL_128MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 128MHz PLL output with HXT */\r
+#define CLK_PLLCTL_128MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 128MHz PLL output with HIRC */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* MODULE constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */\r
+\r
+#define MODULE_APBCLK(x) (((x) >>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */\r
+#define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */\r
+#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index */\r
+#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index */\r
+#define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x4:CLKDIV4 */\r
+#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index */\r
+#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index */\r
+#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index */\r
+#define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index */\r
+#define NA MODULE_NoMsk /*!< Not Available */\r
+\r
+#define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */\r
+#define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */\r
+#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index */\r
+#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index */\r
+#define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1, 0x4:CLKDIV4 */\r
+#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index */\r
+#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index */\r
+#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index */\r
+\r
+\r
+/* AHBCLK */\r
+#define PDMA0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_PDMA0CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */\r
+\r
+#define PDMA1_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_PDMA1CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */\r
+\r
+#define ISP_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_ISPCKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */\r
+\r
+#define EBI_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_EBICKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module */\r
+\r
+#define SDH0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SDH0CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\\r
+ MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(24UL))/*!< SDH0 Module */\r
+\r
+#define CRC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRCCKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */\r
+\r
+#define CRPT_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRPTCKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRPT Module */\r
+\r
+#define USBH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_USBHCKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\\r
+ MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< USBH Module */\r
+\r
+/* APBCLK0 */\r
+#define WDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< WDT Module */\r
+\r
+#define WWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WWDT Module */\r
+\r
+#define RTC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_RTCCKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */\r
+\r
+#define TMR0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR0CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR0 Module */\r
+\r
+#define TMR1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR1CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR1 Module */\r
+\r
+#define TMR2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR2CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR2 Module */\r
+\r
+#define TMR3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR3CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR3 Module */\r
+\r
+#define CLKO_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CLKOCKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< CLKO Module */\r
+\r
+#define ACMP01_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_ACMP01CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP01 Module */\r
+\r
+#define I2C0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C0CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */\r
+\r
+#define I2C1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C1CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */\r
+\r
+#define I2C2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C2CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C2 Module */\r
+\r
+#define QSPI0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_QSPI0CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< QSPI0 Module */\r
+\r
+#define SPI0_MODULE (MODULE_APBCLK_ENC(1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI0CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC(2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\\r
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI0 Module */\r
+\r
+#define SPI1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI1CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI1 Module */\r
+\r
+#define SPI2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI2CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(10UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI2 Module */\r
+\r
+#define UART0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART0CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\\r
+ MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART0 Module */\r
+\r
+#define UART1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART1CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\\r
+ MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART1 Module */\r
+\r
+#define UART2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART2CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\\r
+ MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< UART2 Module */\r
+\r
+#define UART3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART3CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\\r
+ MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< UART3 Module */\r
+\r
+#define UART4_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART4CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\\r
+ MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART4 Module */\r
+\r
+#define UART5_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART5CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\\r
+ MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART5 Module */\r
+\r
+#define CAN0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CAN0CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CAN0 Module */\r
+\r
+#define OTG_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_OTGCKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\\r
+ MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< OTG Module */\r
+\r
+#define USBD_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_USBDCKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\\r
+ MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(4UL)) /*!< USBD Module */\r
+\r
+#define EADC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EADCCKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC( NA)|\\r
+ MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< EADC Module */\r
+\r
+#define I2S0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2S0CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< I2S0 Module */\r
+\r
+/* APBCLK1 */\r
+#define SC0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC0CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\\r
+ MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< SC0 Module */\r
+\r
+#define SC1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC1CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\\r
+ MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< SC1 Module */\r
+\r
+#define SC2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC2CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\\r
+ MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< SC2 Module */\r
+\r
+#define SPI3_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI3CKEN_Pos) |\\r
+ MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI3 Module */\r
+\r
+#define USCI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI0CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module */\r
+\r
+#define USCI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI1CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI1 Module */\r
+\r
+#define DAC_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_DACCKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< DAC Module */\r
+\r
+#define EPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM0CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM0 Module */\r
+\r
+#define EPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM1CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM1 Module */\r
+\r
+#define BPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM0CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module */\r
+\r
+#define BPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM1CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM1 Module */\r
+\r
+#define QEI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QEI0CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QEI0 Module */\r
+\r
+#define QEI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QEI1CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QEI1 Module */\r
+\r
+#define TRNG_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TRNGCKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRNG Module */\r
+\r
+#define ECAP0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP0CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP0 Module */\r
+\r
+#define ECAP1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP1CKEN_Pos)|\\r
+ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\\r
+ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP1 Module */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* PDMSEL constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Power-down mode */\r
+#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Low leakage Power-down mode */\r
+#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Fast Wake-up Power-down mode */\r
+#define CLK_PMUCTL_PDMSEL_ULLPD (0x3UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Ultra Low leakage Power-down mode */\r
+#define CLK_PMUCTL_PDMSEL_SPD (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Standby Power-down mode */\r
+#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Deep Power-down mode */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* WKTMRIS constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 LIRC clocks (12.8 ms) */\r
+#define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 LIRC clocks (25.6 ms) */\r
+#define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 LIRC clocks (51.2 ms) */\r
+#define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 LIRC clocks (102.4ms) */\r
+#define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 LIRC clocks (409.6ms) */\r
+#define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 LIRC clocks (819.2ms) */\r
+#define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 LIRC clocks (1638.4ms) */\r
+#define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 LIRC clocks (6553.6ms) */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* SWKDBCLKSEL constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks */\r
+#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin at Deep Power-down mode */\r
+#define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin rising edge at Deep Power-down mode */\r
+#define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin falling edge at Deep Power-down mode */\r
+#define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin both edge at Deep Power-down mode */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up */\r
+#define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge */\r
+#define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge */\r
+#define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function */\r
+#define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function */\r
+\r
+#define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */\r
+#define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */\r
+#define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */\r
+#define CLK_DISABLE_SPDACMP(void) (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk) /*!< Disable ACMP wake-up at Standby Power-down mode \hideinitializer */\r
+#define CLK_ENABLE_SPDACMP(void) (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk) /*!< Enable ACMP wake-up at Standby Power-down mode \hideinitializer */\r
+#define CLK_DISABLE_RTCWK(void) (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk) /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */\r
+#define CLK_ENABLE_RTCWK(void) (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk) /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */\r
+\r
+\r
+/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */\r
+\r
+/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions\r
+ @{\r
+*/\r
+\r
+\r
+/**\r
+ * @brief Set Wake-up Timer Time-out Interval\r
+ *\r
+ * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be\r
+ * - \ref CLK_PMUCTL_WKTMRIS_128\r
+ * - \ref CLK_PMUCTL_WKTMRIS_256\r
+ * - \ref CLK_PMUCTL_WKTMRIS_512\r
+ * - \ref CLK_PMUCTL_WKTMRIS_1024\r
+ * - \ref CLK_PMUCTL_WKTMRIS_4096\r
+ * - \ref CLK_PMUCTL_WKTMRIS_8192\r
+ * - \ref CLK_PMUCTL_WKTMRIS_16384\r
+ * - \ref CLK_PMUCTL_WKTMRIS_65536\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function set Wake-up Timer Time-out Interval.\r
+ *\r
+ *\r
+ */\r
+#define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_WKTMRIS_Msk)) | (u32Interval))\r
+\r
+/**\r
+ * @brief Set De-bounce Sampling Cycle Time\r
+ *\r
+ * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256\r
+ * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function set Set De-bounce Sampling Cycle Time for Standby Power-down pin wake-up.\r
+ *\r
+ *\r
+ */\r
+#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel))\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* static inline functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */\r
+__STATIC_INLINE void CLK_SysTickDelay(uint32_t us);\r
+__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us);\r
+\r
+\r
+/**\r
+ * @brief This function execute delay function.\r
+ * @param[in] us Delay time. The Max value is (2^24-1) / CPU Clock(MHz). Ex:\r
+ * 64MHz => 262143us, 48MHz => 349525us ...\r
+ * @return None\r
+ * @details Use the SysTick to generate the delay time and the UNIT is in us.\r
+ * The SysTick clock source is from HCLK, i.e the same as system core clock.\r
+ * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.\r
+ */\r
+__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)\r
+{\r
+ SysTick->LOAD = us * CyclesPerUs;\r
+ SysTick->VAL = (0x0UL);\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r
+\r
+ /* Waiting for down-count to zero */\r
+ while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)\r
+ {\r
+ }\r
+\r
+ /* Disable SysTick counter */\r
+ SysTick->CTRL = 0UL;\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L)\r
+\r
+__STATIC_INLINE void CLK_SysTickDelay_NS(uint32_t us);\r
+\r
+/**\r
+ * @brief This function execute delay function.\r
+ * @param[in] us Delay time. The Max value is (2^24-1) / CPU Clock(MHz). Ex:\r
+ * 64MHz => 262143us, 48MHz => 349525us ...\r
+ * @return None\r
+ * @details Use the SysTick to generate the delay time and the UNIT is in us.\r
+ * The SysTick clock source is from HCLK, i.e the same as system core clock.\r
+ * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.\r
+ */\r
+__STATIC_INLINE void CLK_SysTickDelay_NS(uint32_t us)\r
+{\r
+ SysTick_NS->LOAD = us * CyclesPerUs;\r
+ SysTick_NS->VAL = (0x00UL);\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r
+\r
+ /* Waiting for down-count to zero */\r
+ while((SysTick_NS->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);\r
+\r
+ /* Disable SysTick counter */\r
+ SysTick_NS->CTRL = 0UL;\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L) */\r
+\r
+\r
+\r
+\r
+/**\r
+ * @brief This function execute long delay function.\r
+ * @param[in] us Delay time.\r
+ * @return None\r
+ * @details Use the SysTick to generate the long delay time and the UNIT is in us.\r
+ * The SysTick clock source is from HCLK, i.e the same as system core clock.\r
+ * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.\r
+ */\r
+__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)\r
+{\r
+ uint32_t u32Delay;\r
+\r
+ /* It should <= 65536us for each delay loop */\r
+ u32Delay = 65536UL;\r
+\r
+ do\r
+ {\r
+ if(us > u32Delay)\r
+ {\r
+ us -= u32Delay;\r
+ }\r
+ else\r
+ {\r
+ u32Delay = us;\r
+ us = 0UL;\r
+ }\r
+\r
+ SysTick->LOAD = u32Delay * CyclesPerUs;\r
+ SysTick->VAL = (0x0UL);\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r
+\r
+ /* Waiting for down-count to zero */\r
+ while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);\r
+\r
+ /* Disable SysTick counter */\r
+ SysTick->CTRL = 0UL;\r
+\r
+ }\r
+ while(us > 0UL);\r
+\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L)\r
+\r
+__STATIC_INLINE void CLK_SysTickLongDelay_NS(uint32_t us);\r
+\r
+/**\r
+ * @brief This function execute long delay function.\r
+ * @param[in] us Delay time.\r
+ * @return None\r
+ * @details Use the SysTick to generate the long delay time and the UNIT is in us.\r
+ * The SysTick clock source is from HCLK, i.e the same as system core clock.\r
+ * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.\r
+ */\r
+__STATIC_INLINE void CLK_SysTickLongDelay_NS(uint32_t us)\r
+{\r
+ uint32_t u32Delay;\r
+\r
+ /* It should <= 65536us for each delay loop */\r
+ u32Delay = 65536UL;\r
+\r
+ do\r
+ {\r
+ if(us > u32Delay)\r
+ {\r
+ us -= u32Delay;\r
+ }\r
+ else\r
+ {\r
+ u32Delay = us;\r
+ us = 0UL;\r
+ }\r
+\r
+ SysTick_NS->LOAD = u32Delay * CyclesPerUs;\r
+ SysTick_NS->VAL = (0x0UL);\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r
+\r
+ /* Waiting for down-count to zero */\r
+ while((SysTick_NS->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);\r
+\r
+ /* Disable SysTick counter */\r
+ SysTick_NS->CTRL = 0UL;\r
+\r
+ }\r
+ while(us > 0UL);\r
+\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L) */\r
+\r
+\r
+void CLK_DisableCKO(void);\r
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);\r
+void CLK_PowerDown(void);\r
+void CLK_Idle(void);\r
+uint32_t CLK_GetHXTFreq(void);\r
+uint32_t CLK_GetLXTFreq(void);\r
+uint32_t CLK_GetHCLKFreq(void);\r
+uint32_t CLK_GetPCLK0Freq(void);\r
+uint32_t CLK_GetPCLK1Freq(void);\r
+uint32_t CLK_GetCPUFreq(void);\r
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk);\r
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);\r
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);\r
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);\r
+void CLK_EnableXtalRC(uint32_t u32ClkMask);\r
+void CLK_DisableXtalRC(uint32_t u32ClkMask);\r
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx);\r
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx);\r
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);\r
+void CLK_DisablePLL(void);\r
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);\r
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);\r
+void CLK_DisableSysTick(void);\r
+void CLK_SetPowerDownMode(uint32_t u32PDMode);\r
+void CLK_EnableDPDWKPin(uint32_t u32TriggerType);\r
+uint32_t CLK_GetPMUWKSrc(void);\r
+void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);\r
+uint32_t CLK_GetPLLClockFreq(void);\r
+uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);\r
+uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);\r
+\r
+\r
+\r
+/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group CLK_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __CLK_H__ */\r
+\r
+\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file crc.h\r
+ * @version V3.00\r
+ * @brief Cyclic Redundancy Check(CRC) driver header file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __CRC_H__\r
+#define __CRC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CRC_Driver CRC Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants\r
+ @{\r
+*/\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* CRC Polynomial Mode Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CCITT \hideinitializer */\r
+#define CRC_8 (1UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC8 \hideinitializer */\r
+#define CRC_16 (2UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC16 \hideinitializer */\r
+#define CRC_32 (3UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC32 \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Checksum, Write data Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CRC_CHECKSUM_COM (CRC_CTL_CHKSFMT_Msk) /*!<CRC Checksum Complement \hideinitializer */\r
+#define CRC_CHECKSUM_RVS (CRC_CTL_CHKSREV_Msk) /*!<CRC Checksum Reverse \hideinitializer */\r
+#define CRC_WDATA_COM (CRC_CTL_DATFMT_Msk) /*!<CRC Write Data Complement \hideinitializer */\r
+#define CRC_WDATA_RVS (CRC_CTL_DATREV_Msk) /*!<CRC Write Data Reverse \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* CPU Write Data Length Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define CRC_CPU_WDATA_8 (0UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 8-bit \hideinitializer */\r
+#define CRC_CPU_WDATA_16 (1UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 16-bit \hideinitializer */\r
+#define CRC_CPU_WDATA_32 (2UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 32-bit \hideinitializer */\r
+\r
+/*@}*/ /* end of group CRC_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Set CRC Seed Value\r
+ *\r
+ * @param[in] crc The pointer of CRC module.\r
+ * @param[in] u32Seed Seed value\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to set CRC seed value.\r
+ *\r
+ * @note User must to perform CRC_CHKSINIT(CRC_CTL[1] CRC Engine Reset) to reload the new seed value\r
+ * to CRC controller.\r
+ * \hideinitializer\r
+ */\r
+#define CRC_SET_SEED(crc, u32Seed) do{ (crc)->SEED = (u32Seed); (crc)->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0)\r
+\r
+/**\r
+ * @brief Get CRC Seed Value\r
+ *\r
+ * @param[in] crc The pointer of CRC module.\r
+ *\r
+ * @return CRC seed value\r
+ *\r
+ * @details This macro gets the current CRC seed value.\r
+ * \hideinitializer\r
+ */\r
+#define CRC_GET_SEED(crc) ((crc)->SEED)\r
+\r
+/**\r
+ * @brief CRC Write Data\r
+ *\r
+ * @param[in] crc The pointer of CRC module.\r
+ * @param[in] u32Data Write data\r
+ *\r
+ * @return None\r
+ *\r
+ * @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.\r
+ * \hideinitializer\r
+ */\r
+#define CRC_WRITE_DATA(crc, u32Data) ((crc)->DAT = (u32Data))\r
+\r
+\r
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);\r
+uint32_t CRC_GetChecksum(void);\r
+\r
+/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group CRC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CRC_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file crypto.h\r
+ * @version V1.10\r
+ * @brief Cryptographic Accelerator driver header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ ******************************************************************************/\r
+#ifndef __CRYPTO_H__\r
+#define __CRYPTO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CRYPTO_Driver CRYPTO Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants\r
+ @{\r
+*/\r
+\r
+#define PRNG_KEY_SIZE_64 0UL /*!< Select to generate 64-bit random key \hideinitializer */\r
+#define PRNG_KEY_SIZE_128 1UL /*!< Select to generate 128-bit random key \hideinitializer */\r
+#define PRNG_KEY_SIZE_192 2UL /*!< Select to generate 192-bit random key \hideinitializer */\r
+#define PRNG_KEY_SIZE_256 3UL /*!< Select to generate 256-bit random key \hideinitializer */\r
+\r
+#define PRNG_SEED_CONT 0UL /*!< PRNG using current seed \hideinitializer */\r
+#define PRNG_SEED_RELOAD 1UL /*!< PRNG reload new seed \hideinitializer */\r
+\r
+#define AES_KEY_SIZE_128 0UL /*!< AES select 128-bit key length \hideinitializer */\r
+#define AES_KEY_SIZE_192 1UL /*!< AES select 192-bit key length \hideinitializer */\r
+#define AES_KEY_SIZE_256 2UL /*!< AES select 256-bit key length \hideinitializer */\r
+\r
+#define AES_MODE_ECB 0UL /*!< AES select ECB mode \hideinitializer */\r
+#define AES_MODE_CBC 1UL /*!< AES select CBC mode \hideinitializer */\r
+#define AES_MODE_CFB 2UL /*!< AES select CFB mode \hideinitializer */\r
+#define AES_MODE_OFB 3UL /*!< AES select OFB mode \hideinitializer */\r
+#define AES_MODE_CTR 4UL /*!< AES select CTR mode \hideinitializer */\r
+#define AES_MODE_CBC_CS1 0x10UL /*!< AES select CBC CS1 mode \hideinitializer */\r
+#define AES_MODE_CBC_CS2 0x11UL /*!< AES select CBC CS2 mode \hideinitializer */\r
+#define AES_MODE_CBC_CS3 0x12UL /*!< AES select CBC CS3 mode \hideinitializer */\r
+\r
+#define AES_NO_SWAP 0UL /*!< AES do not swap input and output data \hideinitializer */\r
+#define AES_OUT_SWAP 1UL /*!< AES swap output data \hideinitializer */\r
+#define AES_IN_SWAP 2UL /*!< AES swap input data \hideinitializer */\r
+#define AES_IN_OUT_SWAP 3UL /*!< AES swap both input and output data \hideinitializer */\r
+\r
+#define DES_MODE_ECB 0x000UL /*!< DES select ECB mode \hideinitializer */\r
+#define DES_MODE_CBC 0x100UL /*!< DES select CBC mode \hideinitializer */\r
+#define DES_MODE_CFB 0x200UL /*!< DES select CFB mode \hideinitializer */\r
+#define DES_MODE_OFB 0x300UL /*!< DES select OFB mode \hideinitializer */\r
+#define DES_MODE_CTR 0x400UL /*!< DES select CTR mode \hideinitializer */\r
+#define TDES_MODE_ECB 0x004UL /*!< TDES select ECB mode \hideinitializer */\r
+#define TDES_MODE_CBC 0x104UL /*!< TDES select CBC mode \hideinitializer */\r
+#define TDES_MODE_CFB 0x204UL /*!< TDES select CFB mode \hideinitializer */\r
+#define TDES_MODE_OFB 0x304UL /*!< TDES select OFB mode \hideinitializer */\r
+#define TDES_MODE_CTR 0x404UL /*!< TDES select CTR mode \hideinitializer */\r
+\r
+#define TDES_NO_SWAP 0UL /*!< TDES do not swap data \hideinitializer */\r
+#define TDES_WHL_SWAP 1UL /*!< TDES swap high-low word \hideinitializer */\r
+#define TDES_OUT_SWAP 2UL /*!< TDES swap output data \hideinitializer */\r
+#define TDES_OUT_WHL_SWAP 3UL /*!< TDES swap output data and high-low word \hideinitializer */\r
+#define TDES_IN_SWAP 4UL /*!< TDES swap input data \hideinitializer */\r
+#define TDES_IN_WHL_SWAP 5UL /*!< TDES swap input data and high-low word \hideinitializer */\r
+#define TDES_IN_OUT_SWAP 6UL /*!< TDES swap both input and output data \hideinitializer */\r
+#define TDES_IN_OUT_WHL_SWAP 7UL /*!< TDES swap input, output and high-low word \hideinitializer */\r
+\r
+#define SHA_MODE_SHA1 0UL /*!< SHA select SHA-1 160-bit \hideinitializer */\r
+#define SHA_MODE_SHA224 5UL /*!< SHA select SHA-224 224-bit \hideinitializer */\r
+#define SHA_MODE_SHA256 4UL /*!< SHA select SHA-256 256-bit \hideinitializer */\r
+#define SHA_MODE_SHA384 7UL /*!< SHA select SHA-384 384-bit \hideinitializer */\r
+#define SHA_MODE_SHA512 6UL /*!< SHA select SHA-512 512-bit \hideinitializer */\r
+\r
+#define SHA_NO_SWAP 0UL /*!< SHA do not swap input and output data \hideinitializer */\r
+#define SHA_OUT_SWAP 1UL /*!< SHA swap output data \hideinitializer */\r
+#define SHA_IN_SWAP 2UL /*!< SHA swap input data \hideinitializer */\r
+#define SHA_IN_OUT_SWAP 3UL /*!< SHA swap both input and output data \hideinitializer */\r
+\r
+#define CRYPTO_DMA_FIRST 0x4UL /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */\r
+#define CRYPTO_DMA_ONE_SHOT 0x5UL /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */\r
+#define CRYPTO_DMA_CONTINUE 0x6UL /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */\r
+#define CRYPTO_DMA_LAST 0x7UL /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */\r
+\r
+\r
+\r
+typedef enum\r
+{\r
+ CURVE_P_192,\r
+ CURVE_P_224,\r
+ CURVE_P_256,\r
+ CURVE_P_384,\r
+ CURVE_P_521,\r
+ CURVE_K_163,\r
+ CURVE_K_233,\r
+ CURVE_K_283,\r
+ CURVE_K_409,\r
+ CURVE_K_571,\r
+ CURVE_B_163,\r
+ CURVE_B_233,\r
+ CURVE_B_283,\r
+ CURVE_B_409,\r
+ CURVE_B_571\r
+}\r
+E_ECC_CURVE;\r
+\r
+\r
+\r
+typedef struct e_curve_t\r
+{\r
+ E_ECC_CURVE curve_id;\r
+ int32_t Echar;\r
+ char Ea[144];\r
+ char Eb[144];\r
+ char Px[144];\r
+ char Py[144];\r
+ int32_t Epl;\r
+ char Pp[176];\r
+ int32_t Eol;\r
+ char Eorder[176];\r
+ int32_t key_len;\r
+ int32_t irreducible_k1;\r
+ int32_t irreducible_k2;\r
+ int32_t irreducible_k3;\r
+ int32_t GF;\r
+} ECC_CURVE;\r
+\r
+\r
+\r
+/*@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros\r
+ @{\r
+*/\r
+\r
+/*----------------------------------------------------------------------------------------------*/\r
+/* Macros */\r
+/*----------------------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief This macro enables PRNG interrupt.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk)\r
+\r
+/**\r
+ * @brief This macro disables PRNG interrupt.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk)\r
+\r
+/**\r
+ * @brief This macro gets PRNG interrupt flag.\r
+ * @param crpt Specified cripto module\r
+ * @return PRNG interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk)\r
+\r
+/**\r
+ * @brief This macro clears PRNG interrupt flag.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk)\r
+\r
+/**\r
+ * @brief This macro enables AES interrupt.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))\r
+\r
+/**\r
+ * @brief This macro disables AES interrupt.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))\r
+\r
+/**\r
+ * @brief This macro gets AES interrupt flag.\r
+ * @param crpt Specified cripto module\r
+ * @return AES interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))\r
+\r
+/**\r
+ * @brief This macro clears AES interrupt flag.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))\r
+\r
+/**\r
+ * @brief This macro enables AES key protection.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk)\r
+\r
+/**\r
+ * @brief This macro disables AES key protection.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<<CRPT_AES_CTL_KEYUNPRT_Pos)); \\r
+ ((crpt)->AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk)\r
+\r
+/**\r
+ * @brief This macro enables TDES interrupt.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define TDES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk))\r
+\r
+/**\r
+ * @brief This macro disables TDES interrupt.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define TDES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk))\r
+\r
+/**\r
+ * @brief This macro gets TDES interrupt flag.\r
+ * @param crpt Specified cripto module\r
+ * @return TDES interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define TDES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk))\r
+\r
+/**\r
+ * @brief This macro clears TDES interrupt flag.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define TDES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk))\r
+\r
+/**\r
+ * @brief This macro enables TDES key protection.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define TDES_ENABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk)\r
+\r
+/**\r
+ * @brief This macro disables TDES key protection.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define TDES_DISABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL = ((crpt)->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<<CRPT_TDES_CTL_KEYUNPRT_Pos)); \\r
+ ((crpt)->TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk)\r
+\r
+/**\r
+ * @brief This macro enables SHA interrupt.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define SHA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk))\r
+\r
+/**\r
+ * @brief This macro disables SHA interrupt.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define SHA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk))\r
+\r
+/**\r
+ * @brief This macro gets SHA interrupt flag.\r
+ * @param crpt Specified cripto module\r
+ * @return SHA interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define SHA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk))\r
+\r
+/**\r
+ * @brief This macro clears SHA interrupt flag.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define SHA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk))\r
+\r
+/**\r
+ * @brief This macro enables ECC interrupt.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define ECC_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk))\r
+\r
+/**\r
+ * @brief This macro disables ECC interrupt.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define ECC_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk))\r
+\r
+/**\r
+ * @brief This macro gets ECC interrupt flag.\r
+ * @param crpt Specified cripto module\r
+ * @return ECC interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define ECC_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk))\r
+\r
+/**\r
+ * @brief This macro clears ECC interrupt flag.\r
+ * @param crpt Specified cripto module\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define ECC_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk))\r
+\r
+\r
+/*@}*/ /* end of group CRYPTO_EXPORTED_MACROS */\r
+\r
+\r
+\r
+/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+\r
+void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed);\r
+void PRNG_Start(CRPT_T *crpt);\r
+void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]);\r
+void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType);\r
+void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode);\r
+void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize);\r
+void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]);\r
+void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);\r
+void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType);\r
+void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode);\r
+void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2]);\r
+void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL);\r
+void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);\r
+void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len);\r
+void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode);\r
+void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt);\r
+void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]);\r
+void ECC_DriverISR(CRPT_T *crpt);\r
+int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]);\r
+int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]);\r
+int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]);\r
+int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S);\r
+int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S);\r
+\r
+\r
+/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group CRYPTO_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CRYPTO_H__ */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/******************************************************************************\r
+ * @file dac.h\r
+ * @version V1.00\r
+ * @brief M2351 series DAC driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#ifndef __DAC_H__\r
+#define __DAC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup DAC_Driver DAC Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* DAC_CTL Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<<DAC_CTL_LALIGN_Pos) /*!< Right alignment. */\r
+#define DAC_CTL_LALIGN_LEFT_ALIGN (1UL<<DAC_CTL_LALIGN_Pos) /*!< Left alignment */\r
+\r
+#define DAC_WRITE_DAT_TRIGGER (0UL) /*!< Write DAC_DAT trigger */\r
+#define DAC_SOFTWARE_TRIGGER (0UL|DAC_CTL_TRGEN_Msk) /*!< Software trigger */\r
+#define DAC_LOW_LEVEL_TRIGGER ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin low level trigger */\r
+#define DAC_HIGH_LEVEL_TRIGGER ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin high level trigger */\r
+#define DAC_FALLING_EDGE_TRIGGER ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin falling edge trigger */\r
+#define DAC_RISING_EDGE_TRIGGER ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin rising edge trigger */\r
+#define DAC_TIMER0_TRIGGER ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 0 trigger */\r
+#define DAC_TIMER1_TRIGGER ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 1 trigger */\r
+#define DAC_TIMER2_TRIGGER ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 2 trigger */\r
+#define DAC_TIMER3_TRIGGER ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 3 trigger */\r
+#define DAC_EPWM0_TRIGGER ((6UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM0 trigger */\r
+#define DAC_EPWM1_TRIGGER ((7UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM1 trigger */\r
+\r
+#define DAC_TRIGGER_MODE_DISABLE (0UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode disable */\r
+#define DAC_TRIGGER_MODE_ENABLE (1UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode enable */\r
+\r
+\r
+/*@}*/ /* end of group DAC_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions\r
+ @{\r
+*/\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* DAC Macro Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Start the D/A conversion.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @return None\r
+ * @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically.\r
+ */\r
+#define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk)\r
+\r
+/**\r
+ * @brief Enable DAC data left-aligned.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @return None\r
+ * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion.\r
+ */\r
+#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)\r
+\r
+/**\r
+ * @brief Enable DAC data right-aligned.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @return None\r
+ * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion.\r
+ */\r
+#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)\r
+\r
+/**\r
+ * @brief Enable output voltage buffer.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @return None\r
+ * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and\r
+ * drive external loads directly without having to add an external operational amplifier.\r
+ */\r
+#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)\r
+\r
+/**\r
+ * @brief Disable output voltage buffer.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @return None\r
+ * @details This macro is used to disable output voltage buffer.\r
+ */\r
+#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)\r
+\r
+/**\r
+ * @brief Enable the interrupt.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @param[in] u32Ch Not used in M2351 Series DAC.\r
+ * @return None\r
+ * @details This macro is used to enable DAC interrupt.\r
+ */\r
+#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)\r
+\r
+/**\r
+ * @brief Disable the interrupt.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @param[in] u32Ch Not used in M2351 Series DAC.\r
+ * @return None\r
+ * @details This macro is used to disable DAC interrupt.\r
+ */\r
+#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)\r
+\r
+/**\r
+ * @brief Enable DMA under-run interrupt.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @return None\r
+ * @details This macro is used to enable DMA under-run interrupt.\r
+ */\r
+#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)\r
+\r
+/**\r
+ * @brief Disable DMA under-run interrupt.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @return None\r
+ * @details This macro is used to disable DMA under-run interrupt.\r
+ */\r
+#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)\r
+\r
+/**\r
+ * @brief Enable PDMA mode.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @return None\r
+ * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set.\r
+ */\r
+#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)\r
+\r
+/**\r
+ * @brief Disable PDMA mode.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @return None\r
+ * @details This macro is used to disable DMA mode.\r
+ */\r
+#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)\r
+\r
+/**\r
+ * @brief Write data for conversion.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @param[in] u32Ch Not used in M2351 Series DAC.\r
+ * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.\r
+ * @return None\r
+ * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.\r
+ * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.\r
+ */\r
+#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data))\r
+\r
+/**\r
+ * @brief Read DAC 12-bit holding data.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @param[in] u32Ch Not used in M2351 Series DAC.\r
+ * @return Return DAC 12-bit holding data.\r
+ * @details This macro is used to read DAC_DAT register.\r
+ */\r
+#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT)\r
+\r
+/**\r
+ * @brief Get the busy state of DAC.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @param[in] u32Ch Not used in M2351 Series DAC.\r
+ * @retval 0 Idle state.\r
+ * @retval 1 Busy state.\r
+ * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state.\r
+ */\r
+#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos)\r
+\r
+/**\r
+ * @brief Get the interrupt flag.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @param[in] u32Ch Not used in M2351 Series DAC.\r
+ * @retval 0 DAC is in conversion state.\r
+ * @retval 1 DAC conversion finish.\r
+ * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.\r
+ */\r
+#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk)\r
+\r
+/**\r
+ * @brief Get the DMA under-run flag.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @retval 0 No DMA under-run error condition occurred.\r
+ * @retval 1 DMA under-run error condition occurred.\r
+ * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state.\r
+ */\r
+#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos)\r
+\r
+/**\r
+ * @brief This macro clear the interrupt status bit.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @param[in] u32Ch Not used in M2351 Series DAC.\r
+ * @return None\r
+ * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag.\r
+ */\r
+#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk)\r
+\r
+/**\r
+ * @brief This macro clear the DMA under-run flag.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @return None\r
+ * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag.\r
+ */\r
+#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk)\r
+\r
+\r
+/**\r
+ * @brief Enable DAC group mode\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @return None\r
+ * @note Only DAC0 has this control bit.\r
+ * \hideinitializer\r
+ */\r
+#define DAC_ENABLE_GROUP_MODE(dac) ((dac)->CTL |= DAC_CTL_GRPEN_Msk)\r
+\r
+/**\r
+ * @brief Disable DAC group mode\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @return None\r
+ * @note Only DAC0 has this control bit.\r
+ * \hideinitializer\r
+ */\r
+#define DAC_DISABLE_GROUP_MODE(dac) ((dac)->CTL &= ~DAC_CTL_GRPEN_Msk)\r
+\r
+void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);\r
+void DAC_Close(DAC_T *dac, uint32_t u32Ch);\r
+uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay);\r
+\r
+/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group DAC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __DAC_H__ */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/******************************************************************************\r
+ * @file eadc.h\r
+ * @version V0.10\r
+ * @brief M2351 series EADC driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#ifndef __EADC_H__\r
+#define __EADC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup EADC_Driver EADC Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* EADC_CTL Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define EADC_CTL_DIFFEN_SINGLE_END (0UL<<EADC_CTL_DIFFEN_Pos) /*!< Single-end input mode */\r
+#define EADC_CTL_DIFFEN_DIFFERENTIAL (1UL<<EADC_CTL_DIFFEN_Pos) /*!< Differential input mode */\r
+\r
+#define EADC_CTL_DMOF_STRAIGHT_BINARY (0UL<<EADC_CTL_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result */\r
+#define EADC_CTL_DMOF_TWOS_COMPLEMENT (1UL<<EADC_CTL_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* EADC_SCTL Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos) /*!< A/D sample module channel selection */\r
+#define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection */\r
+#define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time */\r
+\r
+#define EADC_SOFTWARE_TRIGGER (0UL<<EADC_SCTL_TRGSEL_Pos) /*!< Software trigger */\r
+#define EADC_FALLING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin falling edge trigger */\r
+#define EADC_RISING_EDGE_TRIGGER (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin rising edge trigger */\r
+#define EADC_FALLING_RISING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin both falling and rising edge trigger */\r
+#define EADC_ADINT0_TRIGGER (2UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT0 interrupt EOC pulse trigger */\r
+#define EADC_ADINT1_TRIGGER (3UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT1 interrupt EOC pulse trigger */\r
+#define EADC_TIMER0_TRIGGER (4UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer0 overflow pulse trigger */\r
+#define EADC_TIMER1_TRIGGER (5UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer1 overflow pulse trigger */\r
+#define EADC_TIMER2_TRIGGER (6UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer2 overflow pulse trigger */\r
+#define EADC_TIMER3_TRIGGER (7UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer3 overflow pulse trigger */\r
+#define EADC_PWM0TG0_TRIGGER (8UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG0 trigger */\r
+#define EADC_PWM0TG1_TRIGGER (9UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG1 trigger */\r
+#define EADC_PWM0TG2_TRIGGER (0xAUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG2 trigger */\r
+#define EADC_PWM0TG3_TRIGGER (0xBUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG3 trigger */\r
+#define EADC_PWM0TG4_TRIGGER (0xCUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG4 trigger */\r
+#define EADC_PWM0TG5_TRIGGER (0xDUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG5 trigger */\r
+#define EADC_PWM1TG0_TRIGGER (0xEUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG0 trigger */\r
+#define EADC_PWM1TG1_TRIGGER (0xFUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG1 trigger */\r
+#define EADC_PWM1TG2_TRIGGER (0x10UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG2 trigger */\r
+#define EADC_PWM1TG3_TRIGGER (0x11UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG3 trigger */\r
+#define EADC_PWM1TG4_TRIGGER (0x12UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG4 trigger */\r
+#define EADC_PWM1TG5_TRIGGER (0x13UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG5 trigger */\r
+#define EADC_BPWM0TG_TRIGGER (0x14UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM0TG trigger */\r
+#define EADC_BPWM1TG_TRIGGER (0x15UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM1TG trigger */\r
+\r
+#define EADC_SCTL_TRGDLYDIV_DIVIDER_1 (0UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/1 */\r
+#define EADC_SCTL_TRGDLYDIV_DIVIDER_2 (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/2 */\r
+#define EADC_SCTL_TRGDLYDIV_DIVIDER_4 (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/4 */\r
+#define EADC_SCTL_TRGDLYDIV_DIVIDER_16 (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/16 */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* EADC_CMP Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define EADC_CMP_CMPCOND_LESS_THAN (0UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "less than" */\r
+#define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" */\r
+#define EADC_CMP_CMPWEN_ENABLE (EADC_CMP_CMPWEN_Msk) /*!< Compare window mode enable */\r
+#define EADC_CMP_CMPWEN_DISABLE (~EADC_CMP_CMPWEN_Msk) /*!< Compare window mode disable */\r
+#define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt enable */\r
+#define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt disable */\r
+\r
+/*@}*/ /* end of group EADC_EXPORTED_CONSTANTS */\r
+\r
+/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions\r
+ @{\r
+*/\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* EADC Macro Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief A/D Converter Control Circuits Reset.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @return None\r
+ * @details ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.\r
+ */\r
+#define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk)\r
+\r
+/**\r
+ * @brief Enable PDMA transfer.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @return None\r
+ * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,\r
+ * user can enable this bit to generate a PDMA data transfer request.\r
+ * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.\r
+ */\r
+#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)\r
+\r
+/**\r
+ * @brief Disable PDMA transfer.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @return None\r
+ * @details This macro is used to disable PDMA transfer.\r
+ */\r
+#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))\r
+\r
+/**\r
+ * @brief Enable double buffer mode.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.\r
+ * @return None\r
+ * @details The ADC controller supports a double buffer mode in sample module 0~3.\r
+ * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.\r
+ */\r
+#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)\r
+\r
+/**\r
+ * @brief Disable double buffer mode.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.\r
+ * @return None\r
+ * @details Sample has one sample result register.\r
+ */\r
+#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)\r
+\r
+/**\r
+ * @brief Set ADIFn at A/D end of conversion.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.\r
+ * @return None\r
+ * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.\r
+ */\r
+#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)\r
+\r
+/**\r
+ * @brief Set ADIFn at A/D start of conversion.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.\r
+ * @return None\r
+ * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.\r
+ */\r
+#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)\r
+\r
+/**\r
+ * @brief Enable the interrupt.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.\r
+ * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.\r
+ * @return None\r
+ * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion.\r
+ * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).\r
+ */\r
+#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))\r
+\r
+/**\r
+ * @brief Disable the interrupt.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.\r
+ * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.\r
+ * @return None\r
+ * @details Specific sample module A/D ADINT0 interrupt function Disabled.\r
+ */\r
+#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))\r
+\r
+/**\r
+ * @brief Enable the sample module interrupt.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.\r
+ * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.\r
+ * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.\r
+ * @return None\r
+ * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.\r
+ */\r
+#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))\r
+\r
+/**\r
+ * @brief Disable the sample module interrupt.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.\r
+ * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.\r
+ * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.\r
+ * @return None\r
+ * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.\r
+ */\r
+#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))\r
+\r
+/**\r
+ * @brief Set the input mode output format.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32Format Decides the output format. Valid values are:\r
+ * - \ref EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result.\r
+ * - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result.\r
+ * @return None\r
+ * @details The macro is used to set A/D input mode output format.\r
+ */\r
+#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))\r
+\r
+/**\r
+ * @brief Start the A/D conversion.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.\r
+ * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF.\r
+ * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.\r
+ * @return None\r
+ * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.\r
+ */\r
+#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))\r
+\r
+/**\r
+ * @brief Cancel the conversion for sample module.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.\r
+ * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF.\r
+ * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.\r
+ * @return None\r
+ * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.\r
+ */\r
+#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))\r
+\r
+/**\r
+ * @brief Get the conversion pending flag.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @return Return the conversion pending sample module.\r
+ * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end,\r
+ * the STPFn (n=0~18) bit is automatically cleared to 0.\r
+ */\r
+#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)\r
+\r
+/**\r
+ * @brief Get the conversion data of the user-specified sample module.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.\r
+ * @return Return the conversion data of the user-specified sample module.\r
+ * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.\r
+ */\r
+#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)\r
+\r
+/**\r
+ * @brief Get the data overrun flag of the user-specified sample module.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.\r
+ * @return Return the data overrun flag of the user-specified sample module.\r
+ * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.\r
+ */\r
+#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))\r
+\r
+/**\r
+ * @brief Get the data valid flag of the user-specified sample module.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.\r
+ * @return Return the data valid flag of the user-specified sample module.\r
+ * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status.\r
+ */\r
+#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))\r
+\r
+/**\r
+ * @brief Get the double data of the user-specified sample module.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.\r
+ * @return Return the double data of the user-specified sample module.\r
+ * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.\r
+ */\r
+#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk)\r
+\r
+/**\r
+ * @brief Get the user-specified interrupt flags.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.\r
+ * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.\r
+ * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.\r
+ * @return Return the user-specified interrupt flags.\r
+ * @details This macro is used to get the user-specified interrupt flags.\r
+ */\r
+#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))\r
+\r
+/**\r
+ * @brief Get the user-specified sample module overrun flags.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.\r
+ * @return Return the user-specified sample module overrun flags.\r
+ * @details This macro is used to get the user-specified sample module overrun flags.\r
+ */\r
+#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))\r
+\r
+/**\r
+ * @brief Clear the selected interrupt status bits.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.\r
+ * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.\r
+ * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.\r
+ * @return None\r
+ * @details This macro is used to clear clear the selected interrupt status bits.\r
+ */\r
+#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))\r
+\r
+/**\r
+ * @brief Clear the selected sample module overrun status bits.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status.\r
+ * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.\r
+ * @return None\r
+ * @details This macro is used to clear the selected sample module overrun status bits.\r
+ */\r
+#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))\r
+\r
+/**\r
+ * @brief Check all sample module A/D result data register overrun flags.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @retval 0 None of sample module data register overrun flag is set to 1.\r
+ * @retval 1 Any one of sample module data register overrun flag is set to 1.\r
+ * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.\r
+ */\r
+#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)\r
+\r
+/**\r
+ * @brief Check all sample module A/D result data register valid flags.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @retval 0 None of sample module data register valid flag is set to 1.\r
+ * @retval 1 Any one of sample module data register valid flag is set to 1.\r
+ * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.\r
+ */\r
+#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)\r
+\r
+/**\r
+ * @brief Check all A/D sample module start of conversion overrun flags.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @retval 0 None of sample module event overrun flag is set to 1.\r
+ * @retval 1 Any one of sample module event overrun flag is set to 1.\r
+ * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.\r
+ */\r
+#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)\r
+\r
+/**\r
+ * @brief Check all A/D interrupt flag overrun bits.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @retval 0 None of ADINT interrupt flag is overwritten to 1.\r
+ * @retval 1 Any one of ADINT interrupt flag is overwritten to 1.\r
+ * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.\r
+ */\r
+#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)\r
+\r
+/**\r
+ * @brief Get the busy state of EADC.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @retval 0 Idle state.\r
+ * @retval 1 Busy state.\r
+ * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.\r
+ */\r
+#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)\r
+\r
+/**\r
+ * @brief Configure the comparator 0 and enable it.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.\r
+ * @param[in] u32Condition specifies the compare condition. Valid values are:\r
+ * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"\r
+ * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value\r
+ * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.\r
+ * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.\r
+ * @return None\r
+ * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);\r
+ * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or\r
+ * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.\r
+ */\r
+#define EADC_ENABLE_CMP0(eadc,\\r
+ u32ModuleNum,\\r
+ u32Condition,\\r
+ u16CMPData,\\r
+ u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\\r
+ (u32Condition) |\\r
+ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \\r
+ (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\\r
+ EADC_CMP_ADCMPEN_Msk))\r
+\r
+/**\r
+ * @brief Configure the comparator 1 and enable it.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.\r
+ * @param[in] u32Condition specifies the compare condition. Valid values are:\r
+ * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"\r
+ * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value\r
+ * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.\r
+ * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.\r
+ * @return None\r
+ * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);\r
+ * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or\r
+ * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.\r
+ */\r
+#define EADC_ENABLE_CMP1(eadc,\\r
+ u32ModuleNum,\\r
+ u32Condition,\\r
+ u16CMPData,\\r
+ u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\\r
+ (u32Condition) |\\r
+ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \\r
+ (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\\r
+ EADC_CMP_ADCMPEN_Msk))\r
+\r
+/**\r
+ * @brief Configure the comparator 2 and enable it.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.\r
+ * @param[in] u32Condition specifies the compare condition. Valid values are:\r
+ * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"\r
+ * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value\r
+ * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.\r
+ * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.\r
+ * @return None\r
+ * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);\r
+ * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or\r
+ * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.\r
+ */\r
+#define EADC_ENABLE_CMP2(eadc,\\r
+ u32ModuleNum,\\r
+ u32Condition,\\r
+ u16CMPData,\\r
+ u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\\r
+ (u32Condition) |\\r
+ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \\r
+ (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\\r
+ EADC_CMP_ADCMPEN_Msk))\r
+\r
+/**\r
+ * @brief Configure the comparator 3 and enable it.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.\r
+ * @param[in] u32Condition specifies the compare condition. Valid values are:\r
+ * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"\r
+ * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value\r
+ * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.\r
+ * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.\r
+ * @return None\r
+ * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);\r
+ * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or\r
+ * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.\r
+ */\r
+#define EADC_ENABLE_CMP3(eadc,\\r
+ u32ModuleNum,\\r
+ u32Condition,\\r
+ u16CMPData,\\r
+ u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\\r
+ (u32Condition) |\\r
+ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \\r
+ (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\\r
+ EADC_CMP_ADCMPEN_Msk))\r
+\r
+/**\r
+ * @brief Enable the compare window mode.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.\r
+ * @return None\r
+ * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.\r
+ */\r
+#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)\r
+\r
+/**\r
+ * @brief Disable the compare window mode.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.\r
+ * @return None\r
+ * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.\r
+ */\r
+#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)\r
+\r
+/**\r
+ * @brief Enable the compare interrupt.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.\r
+ * @return None\r
+ * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3)\r
+ * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile,\r
+ * if ADCMPIE is set to 1, a compare interrupt request is generated.\r
+ */\r
+#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)\r
+\r
+/**\r
+ * @brief Disable the compare interrupt.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.\r
+ * @return None\r
+ * @details This macro is used to disable the compare interrupt.\r
+ */\r
+#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)\r
+\r
+/**\r
+ * @brief Disable comparator 0.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @return None\r
+ * @details This macro is used to disable comparator 0.\r
+ */\r
+#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0UL)\r
+\r
+/**\r
+ * @brief Disable comparator 1.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @return None\r
+ * @details This macro is used to disable comparator 1.\r
+ */\r
+#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0UL)\r
+\r
+/**\r
+ * @brief Disable comparator 2.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @return None\r
+ * @details This macro is used to disable comparator 2.\r
+ */\r
+#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0UL)\r
+\r
+/**\r
+ * @brief Disable comparator 3.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @return None\r
+ * @details This macro is used to disable comparator 3.\r
+ */\r
+#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0UL)\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Define EADC functions prototype */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);\r
+void EADC_Close(EADC_T *eadc);\r
+void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel);\r
+void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);\r
+void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);\r
+\r
+/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group EADC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __EADC_H__ */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file ebi.h\r
+ * @version V3.00\r
+ * @brief External Bus Interface(EBI) driver header file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __EBI_H__\r
+#define __EBI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup EBI_Driver EBI Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants\r
+ @{\r
+*/\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Miscellaneous Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */\r
+#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */\r
+#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address \hideinitializer */\r
+#define EBI_BANK0_BASE_ADDR_NS 0x70000000UL /*!< EBI bank0 base address for Non-Secure \hideinitializer */\r
+#define EBI_BANK1_BASE_ADDR_NS 0x70100000UL /*!< EBI bank1 base address for Non-Secure \hideinitializer */\r
+#define EBI_BANK2_BASE_ADDR_NS 0x70200000UL /*!< EBI bank2 base address for Non-Secure \hideinitializer */\r
+#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Constants for EBI bank number */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */\r
+#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */\r
+#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Constants for EBI data bus width */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */\r
+#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Constants for EBI CS Active Level */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */\r
+#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Constants for EBI MCLK divider and Timing */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */\r
+#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */\r
+#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */\r
+#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */\r
+#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */\r
+#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */\r
+#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */\r
+#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */\r
+\r
+#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */\r
+#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */\r
+#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */\r
+#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */\r
+#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */\r
+#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */\r
+#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */\r
+\r
+#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */\r
+#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */\r
+#define EBI_OPMODE_ADSEPARATE (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */\r
+\r
+/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Read 8-bit data on EBI bank0\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank0.\r
+ *\r
+ * @return 8-bit Data\r
+ *\r
+ * @details This macro is used to read 8-bit data from specify address on EBI bank0.\r
+ * \hideinitializer\r
+ */\r
+#define EBI0_READ_DATA8(ebi, u32Addr) (*((volatile unsigned char *)((((ebi)==EBI)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))))\r
+\r
+/**\r
+ * @brief Write 8-bit data to EBI bank0\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank0.\r
+ * @param[in] u32Data Specify data to be written.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to write 8-bit data to specify address on EBI bank0.\r
+ * \hideinitializer\r
+ */\r
+#define EBI0_WRITE_DATA8(ebi, u32Addr, u32Data) (*((volatile unsigned char *)((((ebi)==EBI)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data))\r
+\r
+/**\r
+ * @brief Read 16-bit data on EBI bank0\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank0.\r
+ *\r
+ * @return 16-bit Data\r
+ *\r
+ * @details This macro is used to read 16-bit data from specify address on EBI bank0.\r
+ * \hideinitializer\r
+ */\r
+#define EBI0_READ_DATA16(ebi, u32Addr) (*((volatile unsigned short *)((((ebi)==EBI)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))))\r
+\r
+/**\r
+ * @brief Write 16-bit data to EBI bank0\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank0.\r
+ * @param[in] u32Data Specify data to be written.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to write 16-bit data to specify address on EBI bank0.\r
+ * \hideinitializer\r
+ */\r
+#define EBI0_WRITE_DATA16(ebi, u32Addr, u32Data) (*((volatile unsigned short *)((((ebi)==EBI)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data))\r
+\r
+/**\r
+ * @brief Read 32-bit data on EBI bank0\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank0.\r
+ *\r
+ * @return 32-bit Data\r
+ *\r
+ * @details This macro is used to read 32-bit data from specify address on EBI bank0.\r
+ * \hideinitializer\r
+ */\r
+#define EBI0_READ_DATA32(ebi, u32Addr) (*((volatile unsigned int *)((((ebi)==EBI)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))))\r
+\r
+/**\r
+ * @brief Write 32-bit data to EBI bank0\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank0.\r
+ * @param[in] u32Data Specify data to be written.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to write 32-bit data to specify address on EBI bank0.\r
+ * \hideinitializer\r
+ */\r
+#define EBI0_WRITE_DATA32(ebi, u32Addr, u32Data) (*((volatile unsigned int *)((((ebi)==EBI)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data))\r
+\r
+/**\r
+ * @brief Read 8-bit data on EBI bank1\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank1.\r
+ *\r
+ * @return 8-bit Data\r
+ *\r
+ * @details This macro is used to read 8-bit data from specify address on EBI bank1.\r
+ * \hideinitializer\r
+ */\r
+#define EBI1_READ_DATA8(ebi, u32Addr) (*((volatile unsigned char *)((((ebi)==EBI)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))))\r
+\r
+/**\r
+ * @brief Write 8-bit data to EBI bank1\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank1.\r
+ * @param[in] u32Data Specify data to be written.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to write 8-bit data to specify address on EBI bank1.\r
+ * \hideinitializer\r
+ */\r
+#define EBI1_WRITE_DATA8(ebi, u32Addr, u32Data) (*((volatile unsigned char *)((((ebi)==EBI)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data))\r
+\r
+/**\r
+ * @brief Read 16-bit data on EBI bank1\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank1.\r
+ *\r
+ * @return 16-bit Data\r
+ *\r
+ * @details This macro is used to read 16-bit data from specify address on EBI bank1.\r
+ * \hideinitializer\r
+ */\r
+#define EBI1_READ_DATA16(ebi, u32Addr) (*((volatile unsigned short *)((((ebi)==EBI)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))))\r
+\r
+/**\r
+ * @brief Write 16-bit data to EBI bank1\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank1.\r
+ * @param[in] u32Data Specify data to be written.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to write 16-bit data to specify address on EBI bank1.\r
+ * \hideinitializer\r
+ */\r
+#define EBI1_WRITE_DATA16(ebi, u32Addr, u32Data) (*((volatile unsigned short *)((((ebi)==EBI)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data))\r
+\r
+/**\r
+ * @brief Read 32-bit data on EBI bank1\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank1.\r
+ *\r
+ * @return 32-bit Data\r
+ *\r
+ * @details This macro is used to read 32-bit data from specify address on EBI bank1.\r
+ * \hideinitializer\r
+ */\r
+#define EBI1_READ_DATA32(ebi, u32Addr) (*((volatile unsigned int *)((((ebi)==EBI)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))))\r
+\r
+/**\r
+ * @brief Write 32-bit data to EBI bank1\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank1.\r
+ * @param[in] u32Data Specify data to be written.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to write 32-bit data to specify address on EBI bank1.\r
+ * \hideinitializer\r
+ */\r
+#define EBI1_WRITE_DATA32(ebi, u32Addr, u32Data) (*((volatile unsigned int *)((((ebi)==EBI)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data))\r
+\r
+/**\r
+ * @brief Read 8-bit data on EBI bank2\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank2.\r
+ *\r
+ * @return 8-bit Data\r
+ *\r
+ * @details This macro is used to read 8-bit data from specify address on EBI bank2.\r
+ * \hideinitializer\r
+ */\r
+#define EBI2_READ_DATA8(ebi, u32Addr) (*((volatile unsigned char *)((((ebi)==EBI)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))))\r
+\r
+/**\r
+ * @brief Write 8-bit data to EBI bank2\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank2.\r
+ * @param[in] u32Data Specify data to be written.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to write 8-bit data to specify address on EBI bank2.\r
+ * \hideinitializer\r
+ */\r
+#define EBI2_WRITE_DATA8(ebi, u32Addr, u32Data) (*((volatile unsigned char *)((((ebi)==EBI)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data))\r
+\r
+/**\r
+ * @brief Read 16-bit data on EBI bank2\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank2.\r
+ *\r
+ * @return 16-bit Data\r
+ *\r
+ * @details This macro is used to read 16-bit data from specify address on EBI bank2.\r
+ */\r
+#define EBI2_READ_DATA16(ebi, u32Addr) (*((volatile unsigned short *)((((ebi)==EBI)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))))\r
+\r
+/**\r
+ * @brief Write 16-bit data to EBI bank2\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank2.\r
+ * @param[in] u32Data Specify data to be written.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to write 16-bit data to specify address on EBI bank2.\r
+ * \hideinitializer\r
+ */\r
+#define EBI2_WRITE_DATA16(ebi, u32Addr, u32Data) (*((volatile unsigned short *)((((ebi)==EBI)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data))\r
+\r
+/**\r
+ * @brief Read 32-bit data on EBI bank2\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank2.\r
+ *\r
+ * @return 32-bit Data\r
+ *\r
+ * @details This macro is used to read 32-bit data from specify address on EBI bank2.\r
+ * \hideinitializer\r
+ */\r
+#define EBI2_READ_DATA32(ebi, u32Addr) (*((volatile unsigned int *)((((ebi)==EBI)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))))\r
+/**\r
+ * @brief Write 32-bit data to EBI bank2\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ * @param[in] u32Addr The data address on EBI bank2.\r
+ * @param[in] u32Data Specify data to be written.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to write 32-bit data to specify address on EBI bank2.\r
+ * \hideinitializer\r
+ */\r
+#define EBI2_WRITE_DATA32(ebi, u32Addr, u32Data) (*((volatile unsigned int *)((((ebi)==EBI)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data))\r
+\r
+/**\r
+ * @brief Enable EBI Write Buffer\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to improve EBI write operation for all EBI banks.\r
+ * \hideinitializer\r
+ */\r
+#define EBI_ENABLE_WRITE_BUFFER(ebi) ((ebi)->CTL0 |= EBI_CTL_WBUFEN_Msk);\r
+\r
+/**\r
+ * @brief Disable EBI Write Buffer\r
+ *\r
+ * @param[in] ebi The pointer of EBI module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to disable EBI write buffer function.\r
+ * \hideinitializer\r
+ */\r
+#define EBI_DISABLE_WRITE_BUFFER(ebi) ((ebi)->CTL0 &= ~EBI_CTL_WBUFEN_Msk);\r
+\r
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);\r
+void EBI_Close(uint32_t u32Bank);\r
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);\r
+\r
+/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group EBI_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __EBI_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file ecap.h\r
+ * @version V3.00\r
+\r
+ * @brief EnHanced Input Capture Timer(ECAP) driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#ifndef __ECAP_H__\r
+#define __ECAP_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup ECAP_Driver ECAP Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants\r
+ @{\r
+*/\r
+\r
+#define ECAP_IC0 (0UL) /*!< ECAP IC0 Unit \hideinitializer */\r
+#define ECAP_IC1 (1UL) /*!< ECAP IC1 Unit \hideinitializer */\r
+#define ECAP_IC2 (2UL) /*!< ECAP IC2 Unit \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* ECAP CTL0 constant definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define ECAP_NOISE_FILTER_CLKDIV_1 (0UL<<ECAP_CTL0_NFCLKSEL_Pos) /*!< Noise filter clock divide by 1 \hideinitializer */\r
+#define ECAP_NOISE_FILTER_CLKDIV_2 (1UL<<ECAP_CTL0_NFCLKSEL_Pos) /*!< Noise filter clock divide by 2 \hideinitializer */\r
+#define ECAP_NOISE_FILTER_CLKDIV_4 (2UL<<ECAP_CTL0_NFCLKSEL_Pos) /*!< Noise filter clock divide by 4 \hideinitializer */\r
+#define ECAP_NOISE_FILTER_CLKDIV_16 (3UL<<ECAP_CTL0_NFCLKSEL_Pos) /*!< Noise filter clock divide by 16 \hideinitializer */\r
+#define ECAP_NOISE_FILTER_CLKDIV_32 (4UL<<ECAP_CTL0_NFCLKSEL_Pos) /*!< Noise filter clock divide by 32 \hideinitializer */\r
+#define ECAP_NOISE_FILTER_CLKDIV_64 (5UL<<ECAP_CTL0_NFCLKSEL_Pos) /*!< Noise filter clock divide by 64 \hideinitializer */\r
+\r
+\r
+#define ECAP_CAP_INPUT_SRC_FROM_IC (0UL) /*!< CAP input source from IC \hideinitializer */\r
+#define ECAP_CAP_INPUT_SRC_FROM_CH (2UL) /*!< CAP input source from CH of QEI \hideinitializer */\r
+\r
+#define ECAP_DISABLE_COMPARE (0UL<<ECAP_CTL0_CMPEN_Pos) /*!< Input capture compare and reload function disable \hideinitializer */\r
+#define ECAP_COMPARE_FUNCTION (1UL<<ECAP_CTL0_CMPEN_Pos) /*!< Input capture compare function \hideinitializer */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* ECAP CTL1 constant definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define ECAP_RISING_EDGE (0UL<<ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP capture rising edge selection \hideinitializer */\r
+#define ECAP_FALLING_EDGE (1UL<<ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP capture falling edge selection \hideinitializer */\r
+#define ECAP_RISING_FALLING_EDGE (2UL<<ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP capture either rising or falling edge selection \hideinitializer */\r
+\r
+#define ECAP_CAPTURE_TIMER_CLKDIV_1 (0UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 1 \hideinitializer */\r
+#define ECAP_CAPTURE_TIMER_CLKDIV_4 (1UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 4 \hideinitializer */\r
+#define ECAP_CAPTURE_TIMER_CLKDIV_16 (2UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 16 \hideinitializer */\r
+#define ECAP_CAPTURE_TIMER_CLKDIV_32 (3UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 32 \hideinitializer */\r
+#define ECAP_CAPTURE_TIMER_CLKDIV_64 (4UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 64 \hideinitializer */\r
+#define ECAP_CAPTURE_TIMER_CLKDIV_96 (5UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 96 \hideinitializer */\r
+#define ECAP_CAPTURE_TIMER_CLKDIV_112 (6UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 112 \hideinitializer */\r
+#define ECAP_CAPTURE_TIMER_CLKDIV_128 (7UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 128 \hideinitializer */\r
+\r
+#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK (0UL<<ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP capture timer/clock source from CAP_CLK \hideinitializer */\r
+#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP0 (1UL<<ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP capture timer/clock source from CAP0 \hideinitializer */\r
+#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP1 (2UL<<ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP capture timer/clock source from CAP1 \hideinitializer */\r
+#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP2 (3UL<<ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP capture timer/clock source from CAP2 \hideinitializer */\r
+\r
+/*@}*/ /* end of group ECAP_EXPORTED_CONSTANTS */\r
+\r
+/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief This macro is used to select noise filter clock pre-divide number\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32ClkSel The noise filter clock divide number\r
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_1\r
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_2\r
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_4\r
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_16\r
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_32\r
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_64\r
+ * @return None\r
+ * @details This macro will set the sampling frequency of the noise filter cock.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_SET_NOISE_FILTER_CLKDIV(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel))\r
+\r
+/**\r
+ * @brief This macro is used to disable noise filter\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return None\r
+ * @details This macro will disable the noise filter of input capture.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to enable noise filter\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32ClkSel Select noise filter clock divide number\r
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_1\r
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_2\r
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_4\r
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_16\r
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_32\r
+ * - \ref ECAP_NOISE_FILTER_CLKDIV_64\r
+ * @return None\r
+ * @details This macro will enable the noise filter of input capture and set noise filter clock divide.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel))\r
+\r
+/**\r
+ * @brief This macro is used to enable input channel unit\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Mask The input channel mask\r
+ * - \ref ECAP_CTL0_IC0EN_Msk\r
+ * - \ref ECAP_CTL0_IC1EN_Msk\r
+ * - \ref ECAP_CTL0_IC2EN_Msk\r
+ * @return None\r
+ * @details This macro will enable the input channel_n to input capture.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to disable input channel unit\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Mask The input channel mask\r
+ * - \ref ECAP_CTL0_IC0EN_Msk\r
+ * - \ref ECAP_CTL0_IC1EN_Msk\r
+ * - \ref ECAP_CTL0_IC2EN_Msk\r
+ * @return None\r
+ * @details This macro will disable the input channel_n to input capture.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to select input channel source\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Index The input channel number\r
+ * - \ref ECAP_IC0\r
+ * - \ref ECAP_IC1\r
+ * - \ref ECAP_IC2\r
+ * @param[in] u32Src The input source\r
+ * - \ref ECAP_CAP_INPUT_SRC_FROM_IC\r
+ * - \ref ECAP_CAP_INPUT_SRC_FROM_CH\r
+ * @return None\r
+ * @details This macro will select the input source from ICx, CHx.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<<ECAP_CTL0_CAPSEL0_Pos)<<((u32Index)<<1)))\r
+\r
+/**\r
+ * @brief This macro is used to enable input channel interrupt\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Mask The input channel mask\r
+ * - \ref ECAP_CTL0_CAPIEN0_Msk\r
+ * - \ref ECAP_CTL0_CAPIEN1_Msk\r
+ * - \ref ECAP_CTL0_CAPIEN2_Msk\r
+ * @return None\r
+ * @details This macro will enable the input channel_n interrupt.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_ENABLE_INT(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to disable input channel interrupt\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Mask The input channel mask\r
+ * - \ref ECAP_IC0\r
+ * - \ref ECAP_IC1\r
+ * - \ref ECAP_IC2\r
+ * @return None\r
+ * @details This macro will disable the input channel_n interrupt.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to enable input channel overflow interrupt\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return None\r
+ * @details This macro will enable the input channel overflow interrupt.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable input channel overflow interrupt\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return None\r
+ * @details This macro will disable the input channel overflow interrupt.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to enable input channel compare-match interrupt\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return None\r
+ * @details This macro will enable the input channel compare-match interrupt.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable input channel compare-match interrupt\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return None\r
+ * @details This macro will disable the input channel compare-match interrupt.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to start capture counter\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return None\r
+ * @details This macro will start capture counter up-counting.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to stop capture counter\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return None\r
+ * @details This macro will stop capture counter up-counting.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to set event to clear capture counter\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Event The input channel number\r
+ * - \ref ECAP_CTL0_CMPCLREN_Msk\r
+ * - \ref ECAP_CTL1_CAP0RLDEN_Msk\r
+ * - \ref ECAP_CTL1_CAP1RLDEN_Msk\r
+ * - \ref ECAP_CTL1_CAP2RLDEN_Msk\r
+ * - \ref ECAP_CTL1_OVRLDEN_Msk\r
+\r
+ * @return None\r
+ * @details This macro will enable and select compare or capture event that can clear capture counter.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \\r
+ if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \\r
+ (ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \\r
+ else \\r
+ (ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \\r
+ (ecap)->CTL1 = ((ecap)->CTL1 &~0xF00) | ((u32Event) & 0xF00); \\r
+ }while(0);\r
+\r
+/**\r
+ * @brief This macro is used to enable compare function\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return None\r
+ * @details This macro will enable the compare function.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable compare function\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return None\r
+ * @details This macro will disable the compare function.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to enable input capture function.\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return None\r
+ * @details This macro will enable input capture timer/counter.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable input capture function.\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return None\r
+ * @details This macro will disable input capture timer/counter.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to select input channel edge detection\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Index The input channel number\r
+ * - \ref ECAP_IC0\r
+ * - \ref ECAP_IC1\r
+ * - \ref ECAP_IC2\r
+ * @param[in] u32Edge The input source\r
+ * - \ref ECAP_RISING_EDGE\r
+ * - \ref ECAP_FALLING_EDGE\r
+ * - \ref ECAP_RISING_FALLING_EDGE\r
+ * @return None\r
+ * @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1)))\r
+\r
+/**\r
+ * @brief This macro is used to select ECAP counter reload trigger source\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32TrigSrc The input source\r
+ * - \ref ECAP_CTL1_CAP0RLDEN_Msk\r
+ * - \ref ECAP_CTL1_CAP1RLDEN_Msk\r
+ * - \ref ECAP_CTL1_CAP2RLDEN_Msk\r
+ * - \ref ECAP_CTL1_OVRLDEN_Msk\r
+ * @return None\r
+ * @details This macro will select capture counter reload trigger source.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc))\r
+\r
+/**\r
+ * @brief This macro is used to select capture timer clock divide.\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Clkdiv The input source\r
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_1\r
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_4\r
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_16\r
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_32\r
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_64\r
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_96\r
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_112\r
+ * - \ref ECAP_CAPTURE_TIMER_CLKDIV_128\r
+ * @return None\r
+ * @details This macro will select capture timer clock has a pre-divider with eight divided option.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv))\r
+\r
+/**\r
+ * @brief This macro is used to select capture timer/counter clock source\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32ClkSrc The input source\r
+ * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK\r
+ * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0\r
+ * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1\r
+ * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2\r
+ * @return None\r
+ * @details This macro will select capture timer/clock clock source.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRCSEL_Msk)|(u32ClkSrc))\r
+\r
+/**\r
+ * @brief This macro is used to read input capture status\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return Input capture status flags\r
+ * @details This macro will get the input capture interrupt status.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS)\r
+\r
+/**\r
+ * @brief This macro is used to get input channel interrupt flag\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Mask The input channel mask\r
+ * - \ref ECAP_STATUS_CAPTF0_Msk\r
+ * - \ref ECAP_STATUS_CAPTF1_Msk\r
+ * - \ref ECAP_STATUS_CAPTF2_Msk\r
+ * - \ref ECAP_STATUS_CAPOVF_Msk\r
+ * - \ref ECAP_STATUS_CAPCMPF_Msk\r
+ * @return None\r
+ * @details This macro will write 1 to get the input channel_n interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0)\r
+\r
+/**\r
+ * @brief This macro is used to clear input channel interrupt flag\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Mask The input channel mask\r
+ * - \ref ECAP_STATUS_CAPTF0_Msk\r
+ * - \ref ECAP_STATUS_CAPTF1_Msk\r
+ * - \ref ECAP_STATUS_CAPTF2_Msk\r
+ * - \ref ECAP_STATUS_CAPOVF_Msk\r
+ * - \ref ECAP_STATUS_CAPCMPF_Msk\r
+ * @return None\r
+ * @details This macro will write 1 to clear the input channel_n interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to set input capture counter value\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Val Counter value\r
+ * @return None\r
+ * @details This macro will set a counter value of input capture.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val))\r
+\r
+/**\r
+ * @brief This macro is used to get input capture counter value\r
+ * @param[in] ecap Specify ECAP port\r
+ * @return Capture counter value\r
+ * @details This macro will get a counter value of input capture.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT)\r
+\r
+/**\r
+ * @brief This macro is used to get input capture counter hold value\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Index The input channel number\r
+ * - \ref ECAP_IC0\r
+ * - \ref ECAP_IC1\r
+ * - \ref ECAP_IC2\r
+ * @return Capture counter hold value\r
+ * @details This macro will get a hold value of input capture channel_n.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index)))\r
+\r
+/**\r
+ * @brief This macro is used to set input capture counter compare value\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Val Input capture compare value\r
+ * @return None\r
+ * @details This macro will set a compare value of input capture counter.\r
+ * \hideinitializer\r
+ */\r
+#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val))\r
+\r
+void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask);\r
+void ECAP_Close(ECAP_T* ecap);\r
+void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask);\r
+void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask);\r
+/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group ECAP_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__ECAP_H__*/\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**
+ * @file epwm.h
+ * @version V3.00
+ * @brief M2351 series EPWM driver header file
+ *
+ * @note
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EPWM_H__
+#define __EPWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EPWM_Driver EPWM Driver
+ @{
+*/
+
+/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants
+ @{
+*/
+#define EPWM_CHANNEL_NUM (6UL) /*!< EPWM channel number */
+#define EPWM_CH_0_MASK (0x1UL) /*!< EPWM channel 0 mask \hideinitializer */
+#define EPWM_CH_1_MASK (0x2UL) /*!< EPWM channel 1 mask \hideinitializer */
+#define EPWM_CH_2_MASK (0x4UL) /*!< EPWM channel 2 mask \hideinitializer */
+#define EPWM_CH_3_MASK (0x8UL) /*!< EPWM channel 3 mask \hideinitializer */
+#define EPWM_CH_4_MASK (0x10UL) /*!< EPWM channel 4 mask \hideinitializer */
+#define EPWM_CH_5_MASK (0x20UL) /*!< EPWM channel 5 mask \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Counter Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_UP_COUNTER (0UL) /*!< Up counter type */
+#define EPWM_DOWN_COUNTER (1UL) /*!< Down counter type */
+#define EPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Aligned Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_EDGE_ALIGNED (1UL) /*!< EPWM working in edge aligned type(down count) */
+#define EPWM_CENTER_ALIGNED (2UL) /*!< EPWM working in center aligned type */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Output Level Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_OUTPUT_NOTHING (0UL) /*!< EPWM output nothing */
+#define EPWM_OUTPUT_LOW (1UL) /*!< EPWM output low */
+#define EPWM_OUTPUT_HIGH (2UL) /*!< EPWM output high */
+#define EPWM_OUTPUT_TOGGLE (3UL) /*!< EPWM output toggle */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Synchronous Start Function Control Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_SSCTL_SSRC_EPWM0 (0UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM0 */
+#define EPWM_SSCTL_SSRC_EPWM1 (1UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM1 */
+#define EPWM_SSCTL_SSRC_BPWM0 (2UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 */
+#define EPWM_SSCTL_SSRC_BPWM1 (3UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Trigger Source Select Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_TRG_ADC_EVEN_ZERO (0UL) /*!< EPWM trigger ADC while counter of even channel matches zero point */
+#define EPWM_TRG_ADC_EVEN_PERIOD (1UL) /*!< EPWM trigger ADC while counter of even channel matches period point */
+#define EPWM_TRG_ADC_EVEN_ZERO_PERIOD (2UL) /*!< EPWM trigger ADC while counter of even channel matches zero or period point */
+#define EPWM_TRG_ADC_EVEN_COMPARE_UP (3UL) /*!< EPWM trigger ADC while counter of even channel matches up count to comparator point */
+#define EPWM_TRG_ADC_EVEN_COMPARE_DOWN (4UL) /*!< EPWM trigger ADC while counter of even channel matches down count to comparator point */
+#define EPWM_TRG_ADC_ODD_ZERO (5UL) /*!< EPWM trigger ADC while counter of odd channel matches zero point */
+#define EPWM_TRG_ADC_ODD_PERIOD (6UL) /*!< EPWM trigger ADC while counter of odd channel matches period point */
+#define EPWM_TRG_ADC_ODD_ZERO_PERIOD (7UL) /*!< EPWM trigger ADC while counter of odd channel matches zero or period point */
+#define EPWM_TRG_ADC_ODD_COMPARE_UP (8UL) /*!< EPWM trigger ADC while counter of odd channel matches up count to comparator point */
+#define EPWM_TRG_ADC_ODD_COMPARE_DOWN (9UL) /*!< EPWM trigger ADC while counter of odd channel matches down count to comparator point */
+#define EPWM_TRG_ADC_CH_0_FREE_CMP_UP (10UL) /*!< EPWM trigger ADC while counter of channel 0 matches up count to free comparator point */
+#define EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN (11UL) /*!< EPWM trigger ADC while counter of channel 0 matches down count to free comparator point */
+#define EPWM_TRG_ADC_CH_2_FREE_CMP_UP (12UL) /*!< EPWM trigger ADC while counter of channel 2 matches up count to free comparator point */
+#define EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN (13UL) /*!< EPWM trigger ADC while counter of channel 2 matches down count to free comparator point */
+#define EPWM_TRG_ADC_CH_4_FREE_CMP_UP (14UL) /*!< EPWM trigger ADC while counter of channel 4 matches up count to free comparator point */
+#define EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN (15UL) /*!< EPWM trigger ADC while counter of channel 4 matches down count to free comparator point */
+
+#define EPWM_TRIGGER_DAC_ZERO (0x1UL) /*!< EPWM trigger DAC while counter down count to 0 \hideinitializer */
+#define EPWM_TRIGGER_DAC_PERIOD (0x100UL) /*!< EPWM trigger DAC while counter matches (PERIOD + 1) \hideinitializer */
+#define EPWM_TRIGGER_DAC_COMPARE_UP (0x10000UL) /*!< EPWM trigger DAC while counter up count to CMPDAT \hideinitializer */
+#define EPWM_TRIGGER_DAC_COMPARE_DOWN (0x1000000UL) /*!< EPWM trigger DAC while counter down count to CMPDAT \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Fail brake Control Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_FB_EDGE_ACMP0 (EPWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source */
+#define EPWM_FB_EDGE_ACMP1 (EPWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source */
+#define EPWM_FB_EDGE_BKP0 (EPWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source */
+#define EPWM_FB_EDGE_BKP1 (EPWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source */
+#define EPWM_FB_EDGE_ADCRM (EPWM_BRKCTL0_1_EADCEBEN_Msk) /*!< ADC Result Monitor (ADCRM) as edge-detect fault brake source */
+#define EPWM_FB_EDGE_SYS_CSS (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source */
+#define EPWM_FB_EDGE_SYS_BOD (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source */
+#define EPWM_FB_EDGE_SYS_RAM (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source */
+#define EPWM_FB_EDGE_SYS_COR (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source */
+
+#define EPWM_FB_LEVEL_ACMP0 (EPWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source */
+#define EPWM_FB_LEVEL_ACMP1 (EPWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source */
+#define EPWM_FB_LEVEL_BKP0 (EPWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source */
+#define EPWM_FB_LEVEL_BKP1 (EPWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source */
+#define EPWM_FB_LEVEL_ADCRM (EPWM_BRKCTL0_1_EADCLBEN_Msk) /*!< ADC Result Monitor (ADCRM) as level-detect fault brake source */
+#define EPWM_FB_LEVEL_SYS_CSS (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source */
+#define EPWM_FB_LEVEL_SYS_BOD (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source */
+#define EPWM_FB_LEVEL_SYS_RAM (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source */
+#define EPWM_FB_LEVEL_SYS_COR (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source */
+
+#define EPWM_FB_EDGE (0UL) /*!< edge-detect fault brake */
+#define EPWM_FB_LEVEL (8UL) /*!< level-detect fault brake */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Leading Edge Blanking Control Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_LEBCTL_TRGTYPE_RISING (0UL<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Rising Edge \hideinitializer */
+#define EPWM_LEBCTL_TRGTYPE_FALLING (1UL<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Falling Edge \hideinitializer */
+#define EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING (2UL<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Rising or Falling Edge \hideinitializer */
+#define EPWM_LEBCTL_SRCEN0 (EPWM_LEBCTL_SRCEN0_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 Enable \hideinitializer */
+#define EPWM_LEBCTL_SRCEN2 (EPWM_LEBCTL_SRCEN2_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 Enable \hideinitializer */
+#define EPWM_LEBCTL_SRCEN4 (EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH4 Enable \hideinitializer */
+#define EPWM_LEBCTL_SRCEN0_2 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH2 Enable \hideinitializer */
+#define EPWM_LEBCTL_SRCEN0_4 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH4 Enable \hideinitializer */
+#define EPWM_LEBCTL_SRCEN2_4 (EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */
+#define EPWM_LEBCTL_SRCEN0_2_4 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0, EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Capture Control Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< EPWM capture interrupt if channel has rising transition */
+#define EPWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< EPWM capture interrupt if channel has falling transition */
+
+#define EPWM_CAPTURE_PDMA_RISING_LATCH (0x2UL) /*!< EPWM capture rising latched data transfer by PDMA */
+#define EPWM_CAPTURE_PDMA_FALLING_LATCH (0x4UL) /*!< EPWM capture falling latched data transfer by PDMA */
+#define EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6UL) /*!< EPWM capture rising and falling latched data transfer by PDMA */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Duty Interrupt Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (EPWM_INTEN0_CMPDIEN0_Msk) /*!< EPWM duty interrupt triggered if down count match comparator */
+#define EPWM_DUTY_INT_UP_COUNT_MATCH_CMP (EPWM_INTEN0_CMPUIEN0_Msk) /*!< EPWM duty interrupt triggered if up down match comparator */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Interrupt Flag Accumulator Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_IFA_ZERO_POINT (0UL) /*!< EPWM counter equal to zero */
+#define EPWM_IFA_PERIOD_POINT (1UL) /*!< EPWM counter equal to period */
+#define EPWM_IFA_COMPARE_UP_COUNT_POINT (2UL) /*!< EPWM counter up count to comparator value */
+#define EPWM_IFA_COMPARE_DOWN_COUNT_POINT (3UL) /*!< EPWM counter down count to comparator value */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Load Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_LOAD_MODE_IMMEDIATE (EPWM_CTL0_IMMLDEN0_Msk) /*!< EPWM immediately load mode \hideinitializer */
+#define EPWM_LOAD_MODE_WINDOW (EPWM_CTL0_WINLDEN0_Msk) /*!< EPWM window load mode \hideinitializer */
+#define EPWM_LOAD_MODE_CENTER (EPWM_CTL0_CTRLD0_Msk) /*!< EPWM center load mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Synchronize Control Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0UL) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */
+#define EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1UL) /*!< Synchronize source from counter equal to 0 \hideinitializer */
+#define EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2UL) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */
+#define EPWM_SYNC_OUT_DISABLE (3UL) /*!< SYNC_OUT will not be generated \hideinitializer */
+#define EPWM_PHS_DIR_DECREMENT (0UL) /*!< EPWM counter count decrement \hideinitializer */
+#define EPWM_PHS_DIR_INCREMENT (1UL) /*!< EPWM counter count increment \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Noise Filter Clock Divide Select Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_NF_CLK_DIV_1 (0UL) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */
+#define EPWM_NF_CLK_DIV_2 (1UL) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */
+#define EPWM_NF_CLK_DIV_4 (2UL) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */
+#define EPWM_NF_CLK_DIV_8 (3UL) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */
+#define EPWM_NF_CLK_DIV_16 (4UL) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */
+#define EPWM_NF_CLK_DIV_32 (5UL) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */
+#define EPWM_NF_CLK_DIV_64 (6UL) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */
+#define EPWM_NF_CLK_DIV_128 (7UL) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Clock Source Select Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_CLKSRC_EPWM_CLK (0UL) /*!< EPWM Clock source selects to EPWM0_CLK or EPWM1_CLK \hideinitializer */
+#define EPWM_CLKSRC_TIMER0 (1UL) /*!< EPWM Clock source selects to TIMER0 overflow \hideinitializer */
+#define EPWM_CLKSRC_TIMER1 (2UL) /*!< EPWM Clock source selects to TIMER1 overflow \hideinitializer */
+#define EPWM_CLKSRC_TIMER2 (3UL) /*!< EPWM Clock source selects to TIMER2 overflow \hideinitializer */
+#define EPWM_CLKSRC_TIMER3 (4UL) /*!< EPWM Clock source selects to TIMER3 overflow \hideinitializer */
+
+
+/*@}*/ /* end of group EPWM_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions
+ @{
+*/
+
+/**
+ * @brief This macro enable complementary mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to enable complementary mode of EPWM module.
+ * \hideinitializer
+ */
+#define EPWM_ENABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 | (0x7ul<<EPWM_CTL1_OUTMODE0_Pos))
+
+/**
+ * @brief This macro disable complementary mode, and enable independent mode.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to disable complementary mode of EPWM module.
+ * \hideinitializer
+ */
+#define EPWM_DISABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 & ~(0x7ul<<EPWM_CTL1_OUTMODE0_Pos))
+
+/**
+ * @brief This macro enable group mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to enable group mode of EPWM module.
+ * \hideinitializer
+ */
+#define EPWM_ENABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk)
+
+/**
+ * @brief This macro disable group mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to disable group mode of EPWM module.
+ * \hideinitializer
+ */
+#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk)
+
+/**
+ * @brief Enable timer synchronous start counting function of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32SyncSrc Synchronous start source selection, valid values are:
+ * - \ref EPWM_SSCTL_SSRC_EPWM0
+ * - \ref EPWM_SSCTL_SSRC_EPWM1
+ * - \ref EPWM_SSCTL_SSRC_BPWM0
+ * - \ref EPWM_SSCTL_SSRC_BPWM1
+ * @return None
+ * @details This macro is used to enable timer synchronous start counting function of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask))
+
+/**
+ * @brief Disable timer synchronous start counting function of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to disable timer synchronous start counting function of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \
+ do{ \
+ int i;\
+ for(i = 0; i < 6; i++) { \
+ if((u32ChannelMask) & (1UL << i)) \
+ { \
+ (epwm)->SSCTL &= ~(1UL << i); \
+ } \
+ } \
+ }while(0)
+
+/**
+ * @brief This macro enable EPWM counter synchronous start counting function.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time.
+ * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC().
+ * \hideinitializer
+ */
+#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk)
+
+/**
+ * @brief This macro enable output inverter of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to enable output inverter of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask))
+
+/**
+ * @brief This macro get captured rising data
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This macro is used to get captured rising data of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT)
+
+/**
+ * @brief This macro get captured falling data
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This macro is used to get captured falling data of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT)
+
+/**
+ * @brief This macro mask output logic to high or low
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32LevelMask Output logic to high or low
+ * @return None
+ * @details This macro is used to mask output logic to high or low of specified channel(s).
+ * @note If u32ChannelMask parameter is 0, then mask function will be disabled.
+ * \hideinitializer
+ */
+#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \
+ do{ \
+ (epwm)->MSKEN = (u32ChannelMask); \
+ (epwm)->MSK = (u32LevelMask); \
+ }while(0)
+
+/**
+ * @brief This macro set the prescaler of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
+ * @return None
+ * @details This macro is used to set the prescaler of specified channel.
+ * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
+ * The clock of EPWM counter is divided by (u32Prescaler + 1).
+ * \hideinitializer
+ */
+#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler))
+
+/**
+ * @brief This macro get the prescaler of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
+ * @details This macro is used to get the prescaler of specified channel.
+ * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
+ * The clock of EPWM counter is divided by (u32Prescaler + 1).
+ * \hideinitializer
+ */
+#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U])
+
+/**
+ * @brief This macro set the comparator of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the comparator of specified channel.
+ * @note This new setting will take effect on next EPWM period.
+ * \hideinitializer
+ */
+#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR))
+
+/**
+ * @brief This macro get the comparator of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF
+ * @details This macro is used to get the comparator of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)])
+
+/**
+ * @brief This macro set the free trigger comparator of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the free trigger comparator of specified channel.
+ * @note This new setting will take effect on next EPWM period.
+ * \hideinitializer
+ */
+#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR))
+
+/**
+ * @brief This macro set the period of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the period of specified channel.
+ * @note This new setting will take effect on next EPWM period.
+ * @note EPWM counter will stop if period length set to 0.
+ * \hideinitializer
+ */
+#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
+
+/**
+ * @brief This macro get the period of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Return the period of specified channel. Valid values are between 0~0xFFFF
+ * @details This macro is used to get the period of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)])
+
+/**
+ * @brief This macro set the EPWM aligned type
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32AlignedType EPWM aligned type, valid values are:
+ * - \ref EPWM_EDGE_ALIGNED
+ * - \ref EPWM_CENTER_ALIGNED
+ * @return None
+ * @details This macro is used to set the EPWM aligned type of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \
+ do{ \
+ uint32_t i; \
+ for(i = 0UL; i < 6UL; i++) { \
+ if((u32ChannelMask) & (1UL << i)) \
+ { \
+ (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \
+ } \
+ } \
+ }while(0)
+
+/**
+ * @brief Set load window of window loading mode for specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to set load window of window loading mode for specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask))
+
+/**
+ * @brief Trigger synchronous event from specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4
+ * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
+ * @return None
+ * @details This macro is used to trigger synchronous event from specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1U << ((u32ChannelNum) >> 1)))
+
+/**
+ * @brief Clear counter of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to clear counter of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask))
+
+/**
+ * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32ZeroLevel output level at zero point, valid values are:
+ * - \ref EPWM_OUTPUT_NOTHING
+ * - \ref EPWM_OUTPUT_LOW
+ * - \ref EPWM_OUTPUT_HIGH
+ * - \ref EPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpUpLevel output level at compare up point, valid values are:
+ * - \ref EPWM_OUTPUT_NOTHING
+ * - \ref EPWM_OUTPUT_LOW
+ * - \ref EPWM_OUTPUT_HIGH
+ * - \ref EPWM_OUTPUT_TOGGLE
+ * @param[in] u32PeriodLevel output level at period(center) point, valid values are:
+ * - \ref EPWM_OUTPUT_NOTHING
+ * - \ref EPWM_OUTPUT_LOW
+ * - \ref EPWM_OUTPUT_HIGH
+ * - \ref EPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpDownLevel output level at compare down point, valid values are:
+ * - \ref EPWM_OUTPUT_NOTHING
+ * - \ref EPWM_OUTPUT_LOW
+ * - \ref EPWM_OUTPUT_HIGH
+ * - \ref EPWM_OUTPUT_TOGGLE
+ * @return None
+ * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
+ do{ \
+ uint32_t i; \
+ for(i = 0UL; i < 6UL; i++) { \
+ if((u32ChannelMask) & (1UL << i)) { \
+ (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \
+ (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \
+ (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \
+ (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \
+ } \
+ } \
+ }while(0)
+
+/**
+ * @brief Trigger brake event from specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
+ * @param[in] u32BrakeType Type of brake trigger.
+ * - \ref EPWM_FB_EDGE
+ * - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This macro is used to trigger brake event from specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
+
+/**
+ * @brief Set Dead zone clock source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
+ * @return None
+ * @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
+ * @note The write-protection function should be disabled before using this function.
+ * \hideinitializer
+ */
+#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \
+ (((epwm)->DTCTL[(u32ChannelNum) >> 1]) = ((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \
+ ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define EPWM functions prototype */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
+uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
+void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
+void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
+void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration);
+void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
+void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource);
+void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource);
+void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource);
+uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource);
+void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
+void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc);
+void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase);
+void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
+void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm);
+void EPWM_EnableSyncPinInverse(EPWM_T *epwm);
+void EPWM_DisableSyncPinInverse(EPWM_T *epwm);
+void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
+void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
+void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum);
+void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum);
+void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum);
+void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
+void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable);
+uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+
+/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EPWM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EPWM_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
--- /dev/null
+/**************************************************************************//**\r
+ * @file fmc.h\r
+ * @version V3.0\r
+ * $Revision: 2 $\r
+ * $Date: 16/07/29 3:11p $\r
+ * @brief M2351 Series Flash Memory Controller(FMC) driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __FMC_H__\r
+#define __FMC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup FMC_Driver FMC Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Global constant definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define ISBEN 0UL\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Define Base Address */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */\r
+#define FMC_APROM_END 0x00080000UL /*!< APROM end address */\r
+#define FMC_APROM_BANK0_END (FMC_APROM_END/2UL) /*!< APROM bank0 end address */\r
+#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */\r
+#define FMC_LDROM_END 0x00101000UL /*!< LDROM end address */\r
+#define FMC_XOM_BASE 0x00200000UL /*!< XOM Base Address */\r
+#define FMC_XOMR0_BASE 0x00200000UL /*!< XOMR 0 Base Address */\r
+#define FMC_XOMR1_BASE 0x00200010UL /*!< XOMR 1 Base Address */\r
+#define FMC_XOMR2_BASE 0x00200020UL /*!< XOMR 2 Base Address */\r
+#define FMC_XOMR3_BASE 0x00200030UL /*!< XOMR 3 Base Address */\r
+#define FMC_NSCBA_BASE 0x00200800UL /*!< Non-Secure base address */\r
+#define FMC_SCRLOCK_BASE 0x00200804UL /*!< Secure Region Lock base address */\r
+#define FMC_ARLOCK_BASE 0x00210804UL /*!< All Region Lock base address */\r
+#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */\r
+#define FMC_USER_CONFIG_0 0x00300000UL /*!< CONFIG 0 Address */\r
+#define FMC_USER_CONFIG_1 0x00300004UL /*!< CONFIG 1 Address */\r
+#define FMC_USER_CONFIG_2 0x00300008UL /*!< CONFIG 2 Address */\r
+#define FMC_USER_CONFIG_3 0x0030000CUL /*!< CONFIG 3 Address */\r
+#define FMC_OTP_BASE 0x00310000UL /*!< OTP flash base address */\r
+#define FMC_KPROM_BASE 0x00311000UL /*!< Security ROM base address */\r
+\r
+#define FMC_FLASH_PAGE_SIZE 0x800UL /*!< Flash Page Size (2048 Bytes) */\r
+#define FMC_PAGE_ADDR_MASK 0xFFFFF800UL /*!< Flash page address mask */\r
+#define FMC_MULTI_WORD_PROG_LEN 512UL /*!< The maximum length of a multi-word program. */\r
+\r
+#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size */\r
+#define FMC_BANK_SIZE (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size */\r
+#define FMC_LDROM_SIZE 0x1000UL /*!< LDROM Size (4 Kbytes) */\r
+#define FMC_OTP_ENTRY_CNT 256UL /*!< OTP entry number */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* XOM region number constant definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define XOMR0 0UL /*!< XOM region 0 */\r
+#define XOMR1 1UL /*!< XOM region 1 */\r
+#define XOMR2 2UL /*!< XOM region 2 */\r
+#define XOMR3 3UL /*!< XOM region 3 */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* ISPCTL constant definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define IS_BOOT_FROM_LDROM 0x1UL /*!< ISPCTL setting to select to boot from LDROM */\r
+#define IS_BOOT_FROM_APROM 0x0UL /*!< ISPCTL setting to select to boot from APROM */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* ISPCMD constant definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read Flash */\r
+#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID */\r
+#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result */\r
+#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID */\r
+#define FMC_ISPCMD_READ_DID 0x0CUL /*!< ISP Command: Read Device ID */\r
+#define FMC_ISPCMD_READ_CKS 0x0DUL /*!< ISP Command: Read Checksum */\r
+#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: 32-bit Program Flash */\r
+#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash */\r
+#define FMC_ISPCMD_BANK_ERASE 0x23UL /*!< ISP Command: Erase Flash bank 0 or 1 */\r
+#define FMC_ISPCMD_BLOCK_ERASE 0x25UL /*!< ISP Command: Erase 4 pages alignment of APROM in bank 0 or 1 */\r
+#define FMC_ISPCMD_PROGRAM_MUL 0x27UL /*!< ISP Command: Flash Multi-Word Program */\r
+#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification*/\r
+#define FMC_ISPCMD_RUN_CKS 0x2DUL /*!< ISP Command: Run Check Calculation */\r
+#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Set vector mapping */\r
+#define FMC_ISPCMD_READ_64 0x40UL /*!< ISP Command: 64-bit read Flash */\r
+#define FMC_ISPCMD_PROGRAM_64 0x61UL /*!< ISP Command: 64-bit program Flash */\r
+\r
+#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. */\r
+#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. */\r
+#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. */\r
+\r
+/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */\r
+\r
+/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* FMC Macro Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Enable ISP Function\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will set ISPEN bit of ISPCTL control register to enable ISP function.\r
+ *\r
+ */\r
+#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP Function */\r
+\r
+/**\r
+ * @brief Disable ISP Function\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will clear ISPEN bit of ISPCTL control register to disable ISP function.\r
+ *\r
+ */\r
+#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP Function */\r
+\r
+/**\r
+ * @brief Enable LDROM Update Function\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will set LDUEN bit of ISPCTL control register to enable LDROM update function.\r
+ * User needs to set LDUEN bit before they can update LDROM.\r
+ *\r
+ */\r
+#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM Update Function */\r
+\r
+/**\r
+ * @brief Disable LDROM Update Function\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will set ISPEN bit of ISPCTL control register to disable LDROM update function.\r
+ *\r
+ */\r
+#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM Update Function */\r
+\r
+/**\r
+ * @brief Enable User Configuration Update Function\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function.\r
+ * User needs to set CFGUEN bit before they can update User Configuration area.\r
+ *\r
+ */\r
+#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function */\r
+\r
+/**\r
+ * @brief Disable User Configuration Update Function\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function.\r
+ *\r
+ */\r
+#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */\r
+\r
+\r
+/**\r
+ * @brief Enable APROM Update Function\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will set APUEN bit of ISPCTL control register to enable APROM update function.\r
+ * User needs to set APUEN bit before they can update APROM in APROM boot mode.\r
+ *\r
+ */\r
+#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM Update Function */\r
+\r
+/**\r
+ * @brief Disable APROM Update Function\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will clear APUEN bit of ISPCTL control register to disable APROM update function.\r
+ *\r
+ */\r
+#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM Update Function */\r
+\r
+/**\r
+ * @brief Set Boot from APROM\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is select booting from APROM.\r
+ *\r
+ */\r
+#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk) /*!< Select booting from APROM */\r
+\r
+/**\r
+ * @brief Set Boot from LDROM\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is select booting from LDROM.\r
+ *\r
+ */\r
+#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk) /*!< Select booting from LDROM */\r
+\r
+/**\r
+ * @brief Get ISP Fail Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to get ISP fail flag when do ISP actoin.\r
+ *\r
+ */\r
+#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag */\r
+\r
+/**\r
+ * @brief Clear ISP Fail Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to clear ISP fail flag when ISP fail flag set.\r
+ *\r
+ */\r
+#define FMC_CLR_FAIL_FLAG() (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag */\r
+\r
+/**\r
+ * @brief Enable ISP Interrupt\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will enable ISP action interrupt.\r
+ *\r
+ */\r
+#define FMC_ENABLE_ISP_INT() (FMC->ISPCTL |= FMC_ISPCTL_INTEN_Msk) /*!< Enable ISP interrupt */\r
+\r
+/**\r
+ * @brief Disable ISP Interrupt\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will disable ISP action interrupt.\r
+ *\r
+ */\r
+#define FMC_DISABLE_ISP_INT() (FMC->ISPCTL &= ~FMC_ISPCTL_INTEN_Msk) /*!< Disable ISP interrupt */\r
+\r
+\r
+/**\r
+ * @brief Get ISP Interrupt Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will get ISP action interrupt status\r
+ *\r
+ */\r
+#define FMC_GET_ISP_INT_FLAG() ((FMC->ISPSTS & FMC_ISPSTS_INTFLAG_Msk) ? 1UL : 0UL) /*!< Get ISP interrupt flag Status */\r
+\r
+\r
+/**\r
+ * @brief Clear ISP Interrupt Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will clear ISP interrupt flag\r
+ *\r
+ */\r
+#define FMC_CLEAR_ISP_INT_FLAG() (FMC->ISPSTS = FMC_ISPSTS_INTFLAG_Msk) /*!< Clear ISP interrupt flag*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* inline functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+__STATIC_INLINE uint32_t FMC_ReadCID(void);\r
+__STATIC_INLINE uint32_t FMC_ReadPID(void);\r
+__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index);\r
+__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index);\r
+__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr);\r
+__STATIC_INLINE uint32_t FMC_GetVECMAP(void);\r
+\r
+\r
+/**\r
+ * @brief Get current vector mapping address.\r
+ *\r
+ * @param None\r
+ *\r
+ * @return The current vector mapping address.\r
+ *\r
+ * @details To get VECMAP value which is the page address for remapping to vector page (0x0).\r
+ *\r
+ */\r
+__STATIC_INLINE uint32_t FMC_GetVECMAP(void)\r
+{\r
+ return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Read company ID\r
+ *\r
+ * @param None\r
+ *\r
+ * @return The company ID (32-bit)\r
+ *\r
+ * @details The company ID of Nuvoton is fixed to be 0xDA\r
+ */\r
+__STATIC_INLINE uint32_t FMC_ReadCID(void)\r
+{\r
+ FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */\r
+ FMC->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */\r
+#if ISBEN\r
+ __ISB();\r
+#endif /* To make sure ISP/CPU be Synchronized */\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */\r
+\r
+ return FMC->ISPDAT;\r
+}\r
+\r
+/**\r
+ * @brief Read product ID\r
+ *\r
+ * @param None\r
+ *\r
+ * @return The product ID (32-bit)\r
+ *\r
+ * @details This function is used to read product ID.\r
+ */\r
+__STATIC_INLINE uint32_t FMC_ReadPID(void)\r
+{\r
+ FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */\r
+ FMC->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */\r
+#if ISBEN\r
+ __ISB();\r
+#endif /* To make sure ISP/CPU be Synchronized */\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */\r
+\r
+ return FMC->ISPDAT;\r
+}\r
+\r
+/**\r
+ * @brief Read Unique ID\r
+ *\r
+ * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]\r
+ *\r
+ * @return The 32-bit unique ID data of specified UID index.\r
+ *\r
+ * @details To read out 96-bit Unique ID.\r
+ */\r
+__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index)\r
+{\r
+ FMC->ISPCMD = FMC_ISPCMD_READ_UID;\r
+ FMC->ISPADDR = ((uint32_t)u8Index << 2u);\r
+ FMC->ISPDAT = 0u;\r
+ FMC->ISPTRG = 0x1u;\r
+#if ISBEN\r
+ __ISB();\r
+#endif\r
+ while(FMC->ISPTRG) {}\r
+\r
+ return FMC->ISPDAT;\r
+}\r
+\r
+/**\r
+ * @brief To read UCID\r
+ *\r
+ * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.\r
+ *\r
+ * @return The UCID of specified index\r
+ *\r
+ * @details This function is used to read unique chip ID (UCID).\r
+ */\r
+__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)\r
+{\r
+ FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */\r
+ FMC->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */\r
+#if ISBEN\r
+ __ISB();\r
+#endif /* To make sure ISP/CPU be Synchronized */\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */\r
+\r
+ return FMC->ISPDAT;\r
+}\r
+\r
+/**\r
+ * @brief Set vector mapping address\r
+ *\r
+ * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment.\r
+ *\r
+ * @return To set VECMAP to remap specified page address to 0x0.\r
+ *\r
+ * @details This function is used to set VECMAP to map specified page to vector page (0x0).\r
+ */\r
+__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)\r
+{\r
+ FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */\r
+ FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */\r
+ FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */\r
+#if ISBEN\r
+ __ISB();\r
+#endif /* To make sure ISP/CPU be Synchronized */\r
+ while(FMC->ISPTRG) {} /* Waiting for ISP Done */\r
+}\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+\r
+extern uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count);\r
+extern void FMC_Close(void);\r
+extern int32_t FMC_ConfigXOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page);\r
+extern int32_t FMC_Erase(uint32_t u32PageAddr);\r
+extern int32_t FMC_Erase_Bank(uint32_t u32BankAddr);\r
+extern int32_t FMC_Erase_Block(uint32_t u32BlockAddr);\r
+extern int32_t FMC_EraseXOM(uint32_t xom_num);\r
+extern int32_t FMC_GetBootSource(void);\r
+extern uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count);\r
+extern int32_t FMC_Is_OTP_Locked(uint32_t otp_num);\r
+extern int32_t FMC_GetXOMState(uint32_t xom_num);\r
+extern int32_t FMC_Lock_OTP(uint32_t otp_num);\r
+extern void FMC_Open(void);\r
+extern uint32_t FMC_Read(uint32_t u32Addr);\r
+extern int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1);\r
+extern int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word);\r
+extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count);\r
+extern void FMC_SetBootSource(int32_t i32BootSrc);\r
+extern int32_t FMC_CompareSPKey(uint32_t key[3]);\r
+extern int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, const int32_t lock_CONFIG, const int32_t lock_SPROM);\r
+extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data);\r
+extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1);\r
+extern int32_t FMC_WriteConfig(uint32_t au32Config[], uint32_t u32Count);\r
+extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len);\r
+extern int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word);\r
+extern int32_t FMC_WriteMultipleA(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len);\r
+/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group FMC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __FMC_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file GPIO.h\r
+ * @version V3.0\r
+ * @brief M2351 series General Purpose I/O (GPIO) driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup GPIO_Driver GPIO Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants\r
+ @{\r
+*/\r
+\r
+#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* GPIO_MODE Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */\r
+#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */\r
+#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */\r
+#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* GPIO Interrupt Type Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */\r
+#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */\r
+#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */\r
+#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */\r
+#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* GPIO_INTTYPE Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */\r
+#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* GPIO Slew Rate Type Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode */\r
+#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode */\r
+#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* GPIO Pull-up And Pull-down Type Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode */\r
+#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode */\r
+#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* GPIO_DBCTL Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */\r
+#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */\r
+\r
+#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz */\r
+#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */\r
+\r
+#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */\r
+#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks */\r
+\r
+\r
+/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.\r
+ * Example 1:\r
+ *\r
+ * PA0 = 1;\r
+ *\r
+ * It is used to set PA.0 to high;\r
+ *\r
+ * Example 2:\r
+ *\r
+ * if (PA0)\r
+ * PA0 = 0;\r
+ *\r
+ * If PA.0 pin status is high, then set PA.0 data output to low.\r
+ */\r
+#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))\r
+#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */\r
+#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */\r
+#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */\r
+#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */\r
+#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */\r
+#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */\r
+#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */\r
+#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */\r
+#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */\r
+#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */\r
+#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */\r
+#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */\r
+#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */\r
+#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */\r
+#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */\r
+#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */\r
+#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */\r
+#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */\r
+#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */\r
+#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */\r
+#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */\r
+#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */\r
+#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */\r
+#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */\r
+#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */\r
+#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */\r
+#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */\r
+#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */\r
+#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */\r
+#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */\r
+#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */\r
+#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */\r
+#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */\r
+#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */\r
+#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */\r
+#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */\r
+#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */\r
+#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */\r
+#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */\r
+#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */\r
+#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */\r
+#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */\r
+#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */\r
+#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */\r
+#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */\r
+#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output */\r
+#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */\r
+#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */\r
+#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */\r
+#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */\r
+#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */\r
+#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */\r
+#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */\r
+#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */\r
+#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */\r
+#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */\r
+#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */\r
+#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */\r
+#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */\r
+#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */\r
+#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output */\r
+#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */\r
+#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */\r
+#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */\r
+#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */\r
+#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */\r
+#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */\r
+#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */\r
+#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */\r
+#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */\r
+#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */\r
+#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */\r
+#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */\r
+#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */\r
+#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */\r
+#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output */\r
+#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output */\r
+#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */\r
+#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */\r
+#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */\r
+#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */\r
+#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */\r
+#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */\r
+#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */\r
+#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */\r
+#define PF8 GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */\r
+#define PF9 GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */\r
+#define PF10 GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output */\r
+#define PF11 GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output */\r
+#define PG2 GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */\r
+#define PG3 GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */\r
+#define PG4 GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */\r
+#define PG9 GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */\r
+#define PG10 GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output */\r
+#define PG11 GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output */\r
+#define PG12 GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output */\r
+#define PG13 GPIO_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output */\r
+#define PG14 GPIO_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output */\r
+#define PG15 GPIO_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output */\r
+#define PH4 GPIO_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */\r
+#define PH5 GPIO_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */\r
+#define PH6 GPIO_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */\r
+#define PH7 GPIO_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */\r
+#define PH8 GPIO_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */\r
+#define PH9 GPIO_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */\r
+#define PH10 GPIO_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output */\r
+#define PH11 GPIO_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output */\r
+\r
+/* GPIO bit definitions for non-secure */\r
+#define GPIO_PIN_DATA_NS(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2))))\r
+#define PA0_NS GPIO_PIN_DATA_NS(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */\r
+#define PA1_NS GPIO_PIN_DATA_NS(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */\r
+#define PA2_NS GPIO_PIN_DATA_NS(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */\r
+#define PA3_NS GPIO_PIN_DATA_NS(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */\r
+#define PA4_NS GPIO_PIN_DATA_NS(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */\r
+#define PA5_NS GPIO_PIN_DATA_NS(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */\r
+#define PA6_NS GPIO_PIN_DATA_NS(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */\r
+#define PA7_NS GPIO_PIN_DATA_NS(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */\r
+#define PA8_NS GPIO_PIN_DATA_NS(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */\r
+#define PA9_NS GPIO_PIN_DATA_NS(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */\r
+#define PA10_NS GPIO_PIN_DATA_NS(0, 10) /*!< Specify PA.10 Pin Data Input/Output */\r
+#define PA11_NS GPIO_PIN_DATA_NS(0, 11) /*!< Specify PA.11 Pin Data Input/Output */\r
+#define PA12_NS GPIO_PIN_DATA_NS(0, 12) /*!< Specify PA.12 Pin Data Input/Output */\r
+#define PA13_NS GPIO_PIN_DATA_NS(0, 13) /*!< Specify PA.13 Pin Data Input/Output */\r
+#define PA14_NS GPIO_PIN_DATA_NS(0, 14) /*!< Specify PA.14 Pin Data Input/Output */\r
+#define PA15_NS GPIO_PIN_DATA_NS(0, 15) /*!< Specify PA.15 Pin Data Input/Output */\r
+#define PB0_NS GPIO_PIN_DATA_NS(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */\r
+#define PB1_NS GPIO_PIN_DATA_NS(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */\r
+#define PB2_NS GPIO_PIN_DATA_NS(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */\r
+#define PB3_NS GPIO_PIN_DATA_NS(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */\r
+#define PB4_NS GPIO_PIN_DATA_NS(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */\r
+#define PB5_NS GPIO_PIN_DATA_NS(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */\r
+#define PB6_NS GPIO_PIN_DATA_NS(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */\r
+#define PB7_NS GPIO_PIN_DATA_NS(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */\r
+#define PB8_NS GPIO_PIN_DATA_NS(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */\r
+#define PB9_NS GPIO_PIN_DATA_NS(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */\r
+#define PB10_NS GPIO_PIN_DATA_NS(1, 10) /*!< Specify PB.10 Pin Data Input/Output */\r
+#define PB11_NS GPIO_PIN_DATA_NS(1, 11) /*!< Specify PB.11 Pin Data Input/Output */\r
+#define PB12_NS GPIO_PIN_DATA_NS(1, 12) /*!< Specify PB.12 Pin Data Input/Output */\r
+#define PB13_NS GPIO_PIN_DATA_NS(1, 13) /*!< Specify PB.13 Pin Data Input/Output */\r
+#define PB14_NS GPIO_PIN_DATA_NS(1, 14) /*!< Specify PB.14 Pin Data Input/Output */\r
+#define PB15_NS GPIO_PIN_DATA_NS(1, 15) /*!< Specify PB.15 Pin Data Input/Output */\r
+#define PC0_NS GPIO_PIN_DATA_NS(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */\r
+#define PC1_NS GPIO_PIN_DATA_NS(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */\r
+#define PC2_NS GPIO_PIN_DATA_NS(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */\r
+#define PC3_NS GPIO_PIN_DATA_NS(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */\r
+#define PC4_NS GPIO_PIN_DATA_NS(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */\r
+#define PC5_NS GPIO_PIN_DATA_NS(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */\r
+#define PC6_NS GPIO_PIN_DATA_NS(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */\r
+#define PC7_NS GPIO_PIN_DATA_NS(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */\r
+#define PC8_NS GPIO_PIN_DATA_NS(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */\r
+#define PC9_NS GPIO_PIN_DATA_NS(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */\r
+#define PC10_NS GPIO_PIN_DATA_NS(2, 10) /*!< Specify PC.10 Pin Data Input/Output */\r
+#define PC11_NS GPIO_PIN_DATA_NS(2, 11) /*!< Specify PC.11 Pin Data Input/Output */\r
+#define PC12_NS GPIO_PIN_DATA_NS(2, 12) /*!< Specify PC.12 Pin Data Input/Output */\r
+#define PC13_NS GPIO_PIN_DATA_NS(2, 13) /*!< Specify PC.13 Pin Data Input/Output */\r
+#define PD0_NS GPIO_PIN_DATA_NS(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */\r
+#define PD1_NS GPIO_PIN_DATA_NS(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */\r
+#define PD2_NS GPIO_PIN_DATA_NS(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */\r
+#define PD3_NS GPIO_PIN_DATA_NS(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */\r
+#define PD4_NS GPIO_PIN_DATA_NS(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */\r
+#define PD5_NS GPIO_PIN_DATA_NS(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */\r
+#define PD6_NS GPIO_PIN_DATA_NS(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */\r
+#define PD7_NS GPIO_PIN_DATA_NS(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */\r
+#define PD8_NS GPIO_PIN_DATA_NS(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */\r
+#define PD9_NS GPIO_PIN_DATA_NS(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */\r
+#define PD10_NS GPIO_PIN_DATA_NS(3, 10) /*!< Specify PD.10 Pin Data Input/Output */\r
+#define PD11_NS GPIO_PIN_DATA_NS(3, 11) /*!< Specify PD.11 Pin Data Input/Output */\r
+#define PD12_NS GPIO_PIN_DATA_NS(3, 12) /*!< Specify PD.12 Pin Data Input/Output */\r
+#define PD13_NS GPIO_PIN_DATA_NS(3, 13) /*!< Specify PD.13 Pin Data Input/Output */\r
+#define PD14_NS GPIO_PIN_DATA_NS(3, 14) /*!< Specify PD.14 Pin Data Input/Output */\r
+#define PE0_NS GPIO_PIN_DATA_NS(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */\r
+#define PE1_NS GPIO_PIN_DATA_NS(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */\r
+#define PE2_NS GPIO_PIN_DATA_NS(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */\r
+#define PE3_NS GPIO_PIN_DATA_NS(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */\r
+#define PE4_NS GPIO_PIN_DATA_NS(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */\r
+#define PE5_NS GPIO_PIN_DATA_NS(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */\r
+#define PE6_NS GPIO_PIN_DATA_NS(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */\r
+#define PE7_NS GPIO_PIN_DATA_NS(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */\r
+#define PE8_NS GPIO_PIN_DATA_NS(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */\r
+#define PE9_NS GPIO_PIN_DATA_NS(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */\r
+#define PE10_NS GPIO_PIN_DATA_NS(4, 10) /*!< Specify PE.10 Pin Data Input/Output */\r
+#define PE11_NS GPIO_PIN_DATA_NS(4, 11) /*!< Specify PE.11 Pin Data Input/Output */\r
+#define PE12_NS GPIO_PIN_DATA_NS(4, 12) /*!< Specify PE.12 Pin Data Input/Output */\r
+#define PE13_NS GPIO_PIN_DATA_NS(4, 13) /*!< Specify PE.13 Pin Data Input/Output */\r
+#define PE14_NS GPIO_PIN_DATA_NS(4, 14) /*!< Specify PE.14 Pin Data Input/Output */\r
+#define PE15_NS GPIO_PIN_DATA_NS(4, 15) /*!< Specify PE.15 Pin Data Input/Output */\r
+#define PF0_NS GPIO_PIN_DATA_NS(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */\r
+#define PF1_NS GPIO_PIN_DATA_NS(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */\r
+#define PF2_NS GPIO_PIN_DATA_NS(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */\r
+#define PF3_NS GPIO_PIN_DATA_NS(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */\r
+#define PF4_NS GPIO_PIN_DATA_NS(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */\r
+#define PF5_NS GPIO_PIN_DATA_NS(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */\r
+#define PF6_NS GPIO_PIN_DATA_NS(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */\r
+#define PF7_NS GPIO_PIN_DATA_NS(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */\r
+#define PF8_NS GPIO_PIN_DATA_NS(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */\r
+#define PF9_NS GPIO_PIN_DATA_NS(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */\r
+#define PF10_NS GPIO_PIN_DATA_NS(5, 10) /*!< Specify PF.10 Pin Data Input/Output */\r
+#define PF11_NS GPIO_PIN_DATA_NS(5, 11) /*!< Specify PF.11 Pin Data Input/Output */\r
+#define PG2_NS GPIO_PIN_DATA_NS(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */\r
+#define PG3_NS GPIO_PIN_DATA_NS(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */\r
+#define PG4_NS GPIO_PIN_DATA_NS(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */\r
+#define PG9_NS GPIO_PIN_DATA_NS(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */\r
+#define PG10_NS GPIO_PIN_DATA_NS(6, 10) /*!< Specify PG.10 Pin Data Input/Output */\r
+#define PG11_NS GPIO_PIN_DATA_NS(6, 11) /*!< Specify PG.11 Pin Data Input/Output */\r
+#define PG12_NS GPIO_PIN_DATA_NS(6, 12) /*!< Specify PG.12 Pin Data Input/Output */\r
+#define PG13_NS GPIO_PIN_DATA_NS(6, 13) /*!< Specify PG.13 Pin Data Input/Output */\r
+#define PG14_NS GPIO_PIN_DATA_NS(6, 14) /*!< Specify PG.14 Pin Data Input/Output */\r
+#define PG15_NS GPIO_PIN_DATA_NS(6, 15) /*!< Specify PG.15 Pin Data Input/Output */\r
+#define PH4_NS GPIO_PIN_DATA_NS(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */\r
+#define PH5_NS GPIO_PIN_DATA_NS(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */\r
+#define PH6_NS GPIO_PIN_DATA_NS(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */\r
+#define PH7_NS GPIO_PIN_DATA_NS(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */\r
+#define PH8_NS GPIO_PIN_DATA_NS(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */\r
+#define PH9_NS GPIO_PIN_DATA_NS(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */\r
+#define PH10_NS GPIO_PIN_DATA_NS(7, 10) /*!< Specify PH.10 Pin Data Input/Output */\r
+#define PH11_NS GPIO_PIN_DATA_NS(7, 11) /*!< Specify PH.11 Pin Data Input/Output */\r
+\r
+\r
+/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Clear GPIO Pin Interrupt Flag\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n\r
+ * It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n\r
+ * It could be BIT0 ~ BIT13 for PE. \n\r
+ * It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Clear the interrupt status of specified GPIO pin.\r
+ */\r
+#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask))\r
+\r
+/**\r
+ * @brief Disable Pin De-bounce Function\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n\r
+ * It could be BIT0 ~ BIT15 for PA, PB and PE. \n\r
+ * It could be BIT0 ~ BIT13 for PC. \n\r
+ * It could be BIT0 ~ BIT14 for PD. \n\r
+ * It could be BIT0 ~ BIT11 for PF. \n\r
+ * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n\r
+ * It could be BIT4 ~ BIT11 for PH.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Disable the interrupt de-bounce function of specified GPIO pin.\r
+ */\r
+#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask))\r
+\r
+/**\r
+ * @brief Enable Pin De-bounce Function\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n\r
+ * It could be BIT0 ~ BIT15 for PA, PB and PE. \n\r
+ * It could be BIT0 ~ BIT13 for PC. \n\r
+ * It could be BIT0 ~ BIT14 for PD. \n\r
+ * It could be BIT0 ~ BIT11 for PF. \n\r
+ * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n\r
+ * It could be BIT4 ~ BIT11 for PH.\r
+ * @return None\r
+ *\r
+ * @details Enable the interrupt de-bounce function of specified GPIO pin.\r
+ */\r
+#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask))\r
+\r
+/**\r
+ * @brief Disable I/O Digital Input Path\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n\r
+ * It could be BIT0 ~ BIT15 for PA, PB and PE. \n\r
+ * It could be BIT0 ~ BIT13 for PC. \n\r
+ * It could be BIT0 ~ BIT14 for PD. \n\r
+ * It could be BIT0 ~ BIT11 for PF. \n\r
+ * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n\r
+ * It could be BIT4 ~ BIT11 for PH.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Disable I/O digital input path of specified GPIO pin.\r
+ */\r
+#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))\r
+\r
+/**\r
+ * @brief Enable I/O Digital Input Path\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n\r
+ * It could be BIT0 ~ BIT15 for PA, PB and PE. \n\r
+ * It could be BIT0 ~ BIT13 for PC. \n\r
+ * It could be BIT0 ~ BIT14 for PD. \n\r
+ * It could be BIT0 ~ BIT11 for PF. \n\r
+ * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n\r
+ * It could be BIT4 ~ BIT11 for PH.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Enable I/O digital input path of specified GPIO pin.\r
+ */\r
+#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16))\r
+\r
+/**\r
+ * @brief Disable I/O DOUT mask\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n\r
+ * It could be BIT0 ~ BIT15 for PA, PB and PE. \n\r
+ * It could be BIT0 ~ BIT13 for PC. \n\r
+ * It could be BIT0 ~ BIT14 for PD. \n\r
+ * It could be BIT0 ~ BIT11 for PF. \n\r
+ * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n\r
+ * It could be BIT4 ~ BIT11 for PH.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Disable I/O DOUT mask of specified GPIO pin.\r
+ */\r
+#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask))\r
+\r
+/**\r
+ * @brief Enable I/O DOUT mask\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n\r
+ * It could be BIT0 ~ BIT15 for PA, PB and PE. \n\r
+ * It could be BIT0 ~ BIT13 for PC. \n\r
+ * It could be BIT0 ~ BIT14 for PD. \n\r
+ * It could be BIT0 ~ BIT11 for PF. \n\r
+ * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n\r
+ * It could be BIT4 ~ BIT11 for PH.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Enable I/O DOUT mask of specified GPIO pin.\r
+ */\r
+#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))\r
+\r
+/**\r
+ * @brief Get GPIO Pin Interrupt Flag\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n\r
+ * It could be BIT0 ~ BIT15 for PA, PB and PE. \n\r
+ * It could be BIT0 ~ BIT13 for PC. \n\r
+ * It could be BIT0 ~ BIT14 for PD. \n\r
+ * It could be BIT0 ~ BIT11 for PF. \n\r
+ * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n\r
+ * It could be BIT4 ~ BIT11 for PH.\r
+ *\r
+ * @retval 0 No interrupt at specified GPIO pin\r
+ * @retval 1 The specified GPIO pin generate an interrupt\r
+ *\r
+ * @details Get the interrupt status of specified GPIO pin.\r
+ */\r
+#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask))\r
+\r
+/**\r
+ * @brief Set De-bounce Sampling Cycle Time\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC.\r
+ * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_1\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_2\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_4\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_8\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_16\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_32\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_64\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_128\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_256\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_512\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_1024\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_2048\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_4096\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_8192\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_16384\r
+ * - \ref GPIO_DBCTL_DBCLKSEL_32768\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n\r
+ * Example: _GPIO_SET_DEBOUNCE_TIME(PA, GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n\r
+ * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n\r
+ * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us,\r
+ * and system will sampling interrupt input once per 400 us.\r
+ */\r
+#define GPIO_SET_DEBOUNCE_TIME(port, u32ClkSrc, u32ClkSel) ((port)->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))\r
+\r
+/**\r
+ * @brief Get GPIO Port IN Data\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ *\r
+ * @return The specified port data\r
+ *\r
+ * @details Get the PIN register of specified GPIO port.\r
+ */\r
+#define GPIO_GET_IN_DATA(port) ((port)->PIN)\r
+\r
+/**\r
+ * @brief Set GPIO Port OUT Data\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ * @param[in] u32Data GPIO port data.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Set the Data into specified GPIO port.\r
+ */\r
+#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))\r
+\r
+/**\r
+ * @brief Toggle Specified GPIO pin\r
+ *\r
+ * @param[in] u32Pin Pxy\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Toggle the specified GPIO pint.\r
+ */\r
+#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)\r
+\r
+\r
+/**\r
+ * @brief Enable External GPIO interrupt\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ * @param[in] u32Pin The pin of specified GPIO port. \n\r
+ * It could be 0 ~ 15 for PA, PB and PE. \n\r
+ * It could be 0 ~ 13 for PC GPIO port. \n\r
+ * It could be 0 ~ 14 for PD GPIO port. \n\r
+ * It could be 0 ~ 11 for PF GPIO port. \n\r
+ * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n\r
+ * It could be 4 ~ 11 for PH GPIO port.\r
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be\r
+ * - \ref GPIO_INT_RISING\r
+ * - \ref GPIO_INT_FALLING\r
+ * - \ref GPIO_INT_BOTH_EDGE\r
+ * - \ref GPIO_INT_HIGH\r
+ * - \ref GPIO_INT_LOW\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable specified GPIO pin interrupt.\r
+ */\r
+#define GPIO_EnableEINT GPIO_EnableInt\r
+\r
+/**\r
+ * @brief Disable External GPIO interrupt\r
+ *\r
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.\r
+ * @param[in] u32Pin The pin of specified GPIO port. \n\r
+ * It could be 0 ~ 15 for PA, PB and PE. \n\r
+ * It could be 0 ~ 13 for PC GPIO port. \n\r
+ * It could be 0 ~ 14 for PD GPIO port. \n\r
+ * It could be 0 ~ 11 for PF GPIO port. \n\r
+ * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n\r
+ * It could be 4 ~ 11 for PH GPIO port.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable specified GPIO pin interrupt.\r
+ */\r
+#define GPIO_DisableEINT GPIO_DisableInt\r
+\r
+\r
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);\r
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);\r
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);\r
+void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);\r
+void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);\r
+\r
+\r
+/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group GPIO_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __GPIO_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file hdiv.h\r
+ * @version V3.0\r
+ * $Revision: 1 $\r
+ * $Date: 16/07/07 7:50p $\r
+ * @brief M0564 series Hardware Divider(HDIV) driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __HDIV_H__\r
+#define __HDIV_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup HDIV_Driver HDIV Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup HDIV_EXPORTED_FUNCTIONS HDIV Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Division function to calculate (x/y)\r
+ *\r
+ * @param[in] x the dividend of the division\r
+ * @param[in] y the divisor of the division\r
+ *\r
+ * @return The result of (x/y)\r
+ *\r
+ * @details This is a division function to calculate x/y\r
+ *\r
+ */\r
+static __INLINE int32_t HDIV_Div(int32_t x, int16_t y)\r
+{\r
+ uint32_t *p32;\r
+\r
+ p32 = (uint32_t *)HDIV_BASE;\r
+ *p32++ = (uint32_t)x;\r
+ *p32++ = (uint32_t)y;\r
+ return (int32_t) * p32;\r
+}\r
+\r
+\r
+/**\r
+ * @brief To calculate the remainder of x/y, i.e., the result of x mod y.\r
+ *\r
+ * @param[in] x the dividend of the division\r
+ * @param[in] y the divisor of the division\r
+ *\r
+ * @return The remainder of (x/y)\r
+ *\r
+ * @details This function is used to calculate the remainder of x/y.\r
+ */\r
+static __INLINE int16_t HDIV_Mod(int32_t x, int16_t y)\r
+{\r
+ uint32_t *p32;\r
+\r
+ p32 = (uint32_t *)HDIV_BASE;\r
+ *p32++ = (uint32_t)x;\r
+ *p32++ = (uint32_t)y;\r
+ return (int16_t)p32[1];\r
+}\r
+\r
+/*@}*/ /* end of group HDIV_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group HDIV_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif //__HDIV_H__\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file i2c.h\r
+ * @version V3.0\r
+ * $Revision: 1 $\r
+ * $Date: 16/07/07 7:50p $\r
+ * @brief M2351 series I2C Serial Interface Controller(I2C) driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __I2C_H__\r
+#define __I2C_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup I2C_Driver I2C Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* I2C_CTL constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define I2C_CTL_STA_SI (0x28U) /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits */\r
+#define I2C_CTL_STA_SI_AA (0x2CU) /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits */\r
+#define I2C_CTL_STO_SI (0x18U) /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits */\r
+#define I2C_CTL_STO_SI_AA (0x1CU) /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits */\r
+#define I2C_CTL_SI (0x08U) /*!< I2C_CTL setting for I2C control bits. It would set SI bit */\r
+#define I2C_CTL_SI_AA (0x0CU) /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits */\r
+#define I2C_CTL_STA (0x20U) /*!< I2C_CTL setting for I2C control bits. It would set STA bit */\r
+#define I2C_CTL_STO (0x10U) /*!< I2C_CTL setting for I2C control bits. It would set STO bit */\r
+#define I2C_CTL_AA (0x04U) /*!< I2C_CTL setting for I2C control bits. It would set AA bit */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* I2C GCMode constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define I2C_GCMODE_ENABLE (1U) /*!< Enable I2C GC Mode */\r
+#define I2C_GCMODE_DISABLE (0U) /*!< Disable I2C GC Mode */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* I2C SMBUS constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define I2C_SMBH_ENABLE (1U) /*!< Enable SMBus Host Mode enable */\r
+#define I2C_SMBD_ENABLE (0U) /*!< Enable SMBus Device Mode enable */\r
+#define I2C_PECTX_ENABLE (1U) /*!< Enable SMBus Packet Error Check Transmit function */\r
+#define I2C_PECTX_DISABLE (0U) /*!< Disable SMBus Packet Error Check Transmit function */\r
+\r
+/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */\r
+\r
+/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions\r
+ @{\r
+*/\r
+/**\r
+ * @brief The macro is used to set I2C bus condition at One Time\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u8Ctrl A byte writes to I2C control register\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.\r
+ */\r
+#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3Cu) | (u8Ctrl))\r
+\r
+/**\r
+ * @brief The macro is used to set START condition of I2C Bus\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Set the I2C bus START condition in I2C_CTL register.\r
+ */\r
+#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 | I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk)\r
+\r
+/**\r
+ * @brief The macro is used to wait I2C bus status get ready\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.\r
+ */\r
+#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk))\r
+\r
+/**\r
+ * @brief The macro is used to Read I2C Bus Data Register\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return A byte of I2C data register\r
+ *\r
+ * @details I2C controller read data from bus and save it in I2CDAT register.\r
+ */\r
+#define I2C_GET_DATA(i2c) ((i2c)->DAT)\r
+\r
+/**\r
+ * @brief Write a Data to I2C Data Register\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u8Data A byte that writes to data register\r
+ *\r
+ * @return None\r
+ *\r
+ * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.\r
+ */\r
+#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))\r
+\r
+/**\r
+ * @brief Get I2C Bus status code\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return I2C status code\r
+ *\r
+ * @details To get this status code to monitor I2C bus event.\r
+ */\r
+#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0)\r
+\r
+/**\r
+ * @brief Get Time-out flag from I2C Bus\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @retval 0 I2C Bus time-out is not happened\r
+ * @retval 1 I2C Bus time-out is happened\r
+ *\r
+ * @details When I2C bus occurs time-out event, the time-out flag will be set.\r
+ */\r
+#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1u : 0u)\r
+\r
+/**\r
+ * @brief To get wake-up flag from I2C Bus\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @retval 0 Chip is not woken-up from power-down mode\r
+ * @retval 1 Chip is woken-up from power-down mode\r
+ *\r
+ * @details I2C bus occurs wake-up event, wake-up flag will be set.\r
+ */\r
+#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1u : 0u)\r
+\r
+/**\r
+ * @brief To clear wake-up flag\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details If wake-up flag is set, use this macro to clear it.\r
+ */\r
+#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)\r
+\r
+/**\r
+ * @brief To get wake-up address frame ACK done flag from I2C Bus\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @retval 0 The ACK bit cycle of address match frame is not done\r
+ * @retval 1 The ACK bit cycle of address match frame is done in power-down\r
+ *\r
+ * @details I2C bus occurs wake-up event and address frame ACK is done, this flag will be set.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define I2C_GET_WAKEUP_DONE(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKAKDONE_Msk) == I2C_WKSTS_WKAKDONE_Msk ? 1u : 0u)\r
+\r
+/**\r
+ * @brief To clear address frame ACK done flag\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details If wake-up done is set, use this macro to clear it.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define I2C_CLEAR_WAKEUP_DONE(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKAKDONE_Msk)\r
+\r
+/**\r
+ * @brief To get read/write status bit in address wakeup frame\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @retval 0 Write command be record on the address match wakeup frame\r
+ * @retval 1 Read command be record on the address match wakeup frame.\r
+ *\r
+ * @details I2C bus occurs wake-up event and address frame is received, this bit will record read/write status.\r
+ *\r
+ * \hideinitializer\r
+*/\r
+#define I2C_GET_WAKEUP_WR_STATUS(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WRSTSWK_Msk) == I2C_WKSTS_WRSTSWK_Msk ? 1u : 0u)\r
+\r
+/**\r
+ * @brief To get SMBus Status\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return SMBus status\r
+ *\r
+ * @details To get the Bus Management status of I2C_BUSSTS register\r
+ *\r
+ */\r
+#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)\r
+\r
+/**\r
+ * @brief Get SMBus CRC value\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return Packet error check byte value\r
+ *\r
+ * @details The CRC check value after a transmission or a reception by count by using CRC8\r
+ *\r
+ */\r
+#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)\r
+\r
+/**\r
+ * @brief Set SMBus Bytes number of Transmission or reception\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u32PktSize Transmit / Receive bytes\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.\r
+ *\r
+ */\r
+#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))\r
+\r
+/**\r
+ * @brief Enable SMBus Alert function\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host\r
+ * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)\r
+ *\r
+ */\r
+#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)\r
+\r
+/**\r
+ * @brief Disable SMBus Alert pin function\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host\r
+ * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)\r
+ *\r
+ */\r
+#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)\r
+\r
+/**\r
+ * @brief Set SMBus SUSCON pin is output mode\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.\r
+ *\r
+ *\r
+ */\r
+#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)\r
+\r
+/**\r
+ * @brief Set SMBus SUSCON pin is input mode\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.\r
+ *\r
+ *\r
+ */\r
+#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)\r
+\r
+/**\r
+ * @brief Set SMBus SUSCON pin output high state\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.\r
+ *\r
+ */\r
+#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)\r
+\r
+\r
+/**\r
+ * @brief Set SMBus SUSCON pin output low state\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.\r
+ *\r
+ */\r
+#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)\r
+\r
+/**\r
+ * @brief Enable SMBus Acknowledge control by manual\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.\r
+ *\r
+ */\r
+#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)\r
+\r
+/**\r
+ * @brief Disable SMBus Acknowledge control by manual\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Disable acknowledge response control by user.\r
+ *\r
+ */\r
+#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)\r
+\r
+/**\r
+ * @brief Enable SMBus Acknowledge manual interrupt\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1\r
+ *\r
+ */\r
+#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)\r
+\r
+/**\r
+ * @brief Disable SMBus Acknowledge manual interrupt\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1\r
+ *\r
+ */\r
+#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)\r
+\r
+/**\r
+ * @brief Enable SMBus PEC clear at REPEAT START\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation.\r
+ *\r
+ */\r
+#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)\r
+\r
+/**\r
+ * @brief Disable SMBus PEC clear at Repeat START\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable the condition of Repeat START can clear the PEC calculation.\r
+ *\r
+ */\r
+#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)\r
+\r
+/**\r
+ * @brief Enable RX PDMA function.\r
+ * @param[in] i2c The pointer of the specified I2C module.\r
+ * @return None.\r
+ * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.\r
+ */\r
+#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)\r
+\r
+/**\r
+ * @brief Enable TX PDMA function.\r
+ * @param[in] i2c The pointer of the specified I2C module.\r
+ * @return None.\r
+ * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.\r
+ */\r
+#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)\r
+\r
+/**\r
+ * @brief Disable RX PDMA transfer.\r
+ * @param[in] i2c The pointer of the specified I2C module.\r
+ * @return None.\r
+ * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.\r
+ */\r
+#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)\r
+\r
+/**\r
+ * @brief Disable TX PDMA transfer.\r
+ * @param[in] i2c The pointer of the specified I2C module.\r
+ * @return None.\r
+ * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.\r
+ */\r
+#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)\r
+\r
+/**\r
+ * @brief Enable PDMA stretch function.\r
+ * @param[in] i2c The pointer of the specified I2C module.\r
+ * @return None.\r
+ * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.\r
+ */\r
+#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)\r
+\r
+/**\r
+ * @brief Disable PDMA stretch function.\r
+ * @param[in] i2c The pointer of the specified I2C module.\r
+ * @return None.\r
+ * @details I2C wil send STOP after PDMA transfers done automatically.\r
+ */\r
+#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)\r
+\r
+/**\r
+ * @brief Reset PDMA function.\r
+ * @param[in] i2c The pointer of the specified I2C module.\r
+ * @return None.\r
+ * @details I2C PDMA engine will be reset after this function is called.\r
+ */\r
+#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* inline functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+static __INLINE void I2C_STOP(I2C_T *i2c);\r
+\r
+/**\r
+ * @brief The macro is used to set STOP condition of I2C Bus\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Set the I2C bus STOP condition in I2C_CTL register.\r
+ */\r
+static __INLINE void I2C_STOP(I2C_T *i2c)\r
+{\r
+\r
+ (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk);\r
+ CLK_SysTickDelay(10000);\r
+ while(i2c->CTL0 & I2C_CTL0_STO_Msk) {}\r
+}\r
+\r
+\r
+void I2C_ClearTimeoutFlag(I2C_T *i2c);\r
+void I2C_Close(I2C_T *i2c);\r
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);\r
+void I2C_DisableInt(I2C_T *i2c);\r
+void I2C_EnableInt(I2C_T *i2c);\r
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c);\r
+uint32_t I2C_GetIntFlag(I2C_T *i2c);\r
+uint32_t I2C_GetStatus(I2C_T *i2c);\r
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);\r
+uint8_t I2C_GetData(I2C_T *i2c);\r
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);\r
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);\r
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);\r
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);\r
+void I2C_DisableTimeout(I2C_T *i2c);\r
+void I2C_EnableWakeup(I2C_T *i2c);\r
+void I2C_DisableWakeup(I2C_T *i2c);\r
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data);\r
+uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Data);\r
+uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Data[], uint32_t u32wLen);\r
+uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t u8Data);\r
+uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Data[], uint32_t u32wLen);\r
+uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t u8Data);\r
+uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Data[], uint32_t u32wLen);\r
+uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);\r
+uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Rdata[], uint32_t u32rLen);\r
+uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);\r
+uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Rdata[], uint32_t u32rLen);\r
+uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);\r
+uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Rdata[], uint32_t u32rLen);\r
+uint32_t I2C_SMBusGetStatus(I2C_T *i2c);\r
+void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag);\r
+void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);\r
+void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);\r
+void I2C_SMBusClose(I2C_T *i2c);\r
+void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);\r
+uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);\r
+void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t u32Us, uint32_t u32Hclk);\r
+void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);\r
+void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);\r
+\r
+/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group I2C_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/****************************************************************************//**\r
+ * @file i2s.h\r
+ * @version V3.00\r
+ * @brief M2351 series I2S driver header file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#ifndef __I2S_H__\r
+#define __I2S_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup I2S_Driver I2S Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants\r
+ @{\r
+*/\r
+#define I2S_DATABIT_8 (0UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */\r
+#define I2S_DATABIT_16 (1UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */\r
+#define I2S_DATABIT_24 (2UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */\r
+#define I2S_DATABIT_32 (3UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */\r
+\r
+/* Audio Format */\r
+#define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */\r
+#define I2S_DISABLE_MONO (0UL) /*!< Stereo channel \hideinitializer */\r
+#define I2S_MONO I2S_ENABLE_MONO\r
+#define I2S_STEREO I2S_DISABLE_MONO\r
+\r
+\r
+/* I2S Data Format */\r
+#define I2S_FORMAT_I2S (0UL << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */\r
+#define I2S_FORMAT_I2S_MSB (1UL << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */\r
+#define I2S_FORMAT_I2S_LSB (2UL << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */\r
+#define I2S_FORMAT_PCM (4UL << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */\r
+#define I2S_FORMAT_PCM_MSB (5UL << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */\r
+#define I2S_FORMAT_PCM_LSB (6UL << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */\r
+\r
+/* I2S Data Format */\r
+#define I2S_ORDER_AT_MSB 0UL /*!< Channel data is at MSB \hideinitializer */\r
+#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */\r
+\r
+/* I2S TDM Channel Number */\r
+#define I2S_TDM_2CH 0UL /*!< Use TDM 2 channel \hideinitializer */\r
+#define I2S_TDM_4CH 1UL /*!< Use TDM 4 channel \hideinitializer */\r
+#define I2S_TDM_6CH 2UL /*!< Use TDM 6 channel \hideinitializer */\r
+#define I2S_TDM_8CH 3UL /*!< Use TDM 8 channel \hideinitializer */\r
+\r
+/* I2S TDM Channel Width */\r
+#define I2S_TDM_WIDTH_8BIT 0UL /*!< TDM channel witch is 8-bit \hideinitializer */\r
+#define I2S_TDM_WIDTH_16BIT 1UL /*!< TDM channel witch is 16-bit \hideinitializer */\r
+#define I2S_TDM_WIDTH_24BIT 2UL /*!< TDM channel witch is 24-bit \hideinitializer */\r
+#define I2S_TDM_WIDTH_32BIT 3UL /*!< TDM channel witch is 32-bit \hideinitializer */\r
+\r
+/* I2S TDM Sync Width */\r
+#define I2S_TDM_SYNC_ONE_BCLK 0UL /*!< TDM sync widht is one BLCK period \hideinitializer */\r
+#define I2S_TDM_SYNC_ONE_CHANNEL 1UL /*!< TDM sync widht is one channel period \hideinitializer */\r
+\r
+/* I2S Operation mode */\r
+#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */\r
+#define I2S_MODE_MASTER 0UL /*!< As master mode \hideinitializer */\r
+\r
+/* I2S FIFO Threshold */\r
+#define I2S_FIFO_TX_LEVEL_WORD_0 0UL /*!< TX threshold is 0 word \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_1 (1UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_2 (2UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_3 (3UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_4 (4UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_5 (5UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_6 (6UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_7 (7UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_8 (8UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_9 (9UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_10 (10UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_11 (11UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_12 (12UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_13 (13UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_14 (14UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */\r
+#define I2S_FIFO_TX_LEVEL_WORD_15 (15UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */\r
+\r
+#define I2S_FIFO_RX_LEVEL_WORD_1 0UL /*!< RX threshold is 1 word \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_2 (1UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_3 (2UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_4 (3UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_5 (4UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_6 (5UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_7 (6UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_8 (7UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_9 (8UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_10 (9UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_11 (10UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_12 (11UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_13 (12UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_14 (13UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_15 (14UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */\r
+#define I2S_FIFO_RX_LEVEL_WORD_16 (15UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */\r
+\r
+/* I2S Record Channel */\r
+#define I2S_MONO_RIGHT 0UL /*!< Record mono right channel \hideinitializer */\r
+#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */\r
+\r
+/* I2S Channel */\r
+#define I2S_RIGHT 0UL /*!< Select right channel \hideinitializer */\r
+#define I2S_LEFT 1UL /*!< Select left channel \hideinitializer */\r
+\r
+/*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */\r
+\r
+/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions\r
+ @{\r
+*/\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* inline functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+\r
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */\r
+__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask);\r
+__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask);\r
+__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch);\r
+\r
+/**\r
+ * @brief Enable zero cross detect function.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)\r
+{\r
+ if((u32ChMask > 0UL) && (u32ChMask < 9UL))\r
+ {\r
+ i2s->CTL1 |= (1UL << (u32ChMask - 1UL));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable zero cross detect function.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)\r
+{\r
+ if((u32ChMask > 0UL) && (u32ChMask < 9UL))\r
+ {\r
+ i2s->CTL1 &= ~(1UL << (u32ChMask - 1UL));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Enable I2S Tx function .\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk )\r
+\r
+/**\r
+ * @brief Disable I2S Tx function .\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk )\r
+\r
+/**\r
+ * @brief Enable I2S Rx function .\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk )\r
+\r
+/**\r
+ * @brief Disable I2S Rx function .\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk )\r
+\r
+/**\r
+ * @brief Enable Tx Mute function .\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk )\r
+\r
+/**\r
+ * @brief Disable Tx Mute function .\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk )\r
+\r
+/**\r
+ * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk )\r
+\r
+/**\r
+ * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk )\r
+\r
+/**\r
+ * @brief This function sets the recording source channel when mono mode is used.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @param[in] u32Ch left or right channel. Valid values are:\r
+ * - \ref I2S_MONO_LEFT\r
+ * - \ref I2S_MONO_RIGHT\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)\r
+{\r
+ u32Ch == I2S_MONO_LEFT ?\r
+ (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) :\r
+ (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Write data to I2S Tx FIFO.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @param[in] u32Data: The data written to FIFO.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) )\r
+\r
+/**\r
+ * @brief Read Rx FIFO.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return Data in Rx FIFO.\r
+ * \hideinitializer\r
+ */\r
+#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )\r
+\r
+/**\r
+ * @brief This function gets the interrupt flag according to the mask parameter.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @param[in] u32Mask is the mask for the all interrupt flags.\r
+ * @return The masked bit value of interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) )\r
+\r
+/**\r
+ * @brief This function clears the interrupt flag according to the mask parameter.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @param[in] u32Mask is the mask for the all interrupt flags.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) )\r
+\r
+/**\r
+ * @brief This function gets the zero crossing interrupt flag according to the mask parameter.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @param[in] u32Mask is the mask for the all interrupt flags.\r
+ * @return The masked bit value of interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) )\r
+\r
+/**\r
+ * @brief This function clears the zero crossing interrupt flag according to the mask parameter.\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @param[in] u32Mask is the mask for the all interrupt flags.\r
+ * @return none\r
+ * \hideinitializer\r
+ */\r
+#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) )\r
+\r
+/**\r
+ * @brief Get transmit FIFO level\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return FIFO level\r
+ * \hideinitializer\r
+ */\r
+#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF )\r
+\r
+/**\r
+ * @brief Get receive FIFO level\r
+ * @param[in] i2s is the base address of I2S module.\r
+ * @return FIFO level\r
+ * \hideinitializer\r
+ */\r
+#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF )\r
+\r
+uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat);\r
+void I2S_Close(I2S_T *i2s);\r
+void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);\r
+void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);\r
+uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);\r
+void I2S_DisableMCLK(I2S_T *i2s);\r
+void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);\r
+void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth);\r
+\r
+/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */\r
+\r
+\r
+/*@}*/ /* end of group I2S_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __I2S_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/**************************************************************************//**
+ * @file MKROMLib.h
+ * @version V2.00
+ * @brief MaskROM library header file
+ *
+ * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __MKROM_LIB_H__
+#define __MKROM_LIB_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup MKROM_Driver MKROM Driver
+ @{
+*/
+
+/** @addtogroup MKROM_EXPORTED_CONSTANTS MKROM Exported Constants
+ @{
+*/
+/*--------------------------------------------------------------------------------------------------*/
+/* Status and Error Code Constant Definitions */
+/*--------------------------------------------------------------------------------------------------*/
+#define BL_ERR_TT_CHECK 0xF0F00000UL /*!< Not a Non-secure parameter */
+#define BL_ERR_PARAMETER 0xF0F00001UL /*!< Invalid parameter */
+#define BL_PARAM_ALIGN 0xF0F00002UL /*!< Parameter alignment error */
+#define BL_NOT_FLASH_ADDR 0xF0F00003UL /*!< Invalid flash address */
+#define BL_NOT_SRAM_ADDR 0xF0F00004UL /*!< Invalid sram address */
+#define BL_XOM_NOT_CONFIG 0xF0F00005UL /*!< XOM is not configure yet */
+#define BL_XOM_HAS_CONFIG 0xF0F00006UL /*!< XOM has beeen configured */
+#define BL_XOM_HAS_ACTIVE 0xF0F00007UL /*!< XOM is actived */
+#define BL_XOM_BASE_ERROR 0xF0F00008UL /*!< Invalid XOM base address */
+#define BL_KPROM_NOT_ENABLE 0xF0F00009UL /*!< KPROM is not enabled yet */
+#define BL_KPROM_KEY_FORBID 0xF0F0000AUL /*!< KPROM comparison is forbidden */
+#define BL_KPROM_KEY_UNMATCH 0xF0F0000BUL /*!< KPROM comparison is unmatched */
+#define BL_KPROM_KEY_LOCKED 0xF0F0000CUL /*!< KPROM write-protect is enabled */
+#define BL_KPROM_SET_FAIL 0xF0F0000EUL /*!< Set KPROM key fail */
+#define BL_ISP_CMD_FAIL (-1) /*!< FMC command fail */
+#define BL_FLASH_ALLONE 0xA11FFFFFUL /*!< Check-all-one result is all one */
+#define BL_FLASH_NOT_ALLONE 0xA1100000UL /*!< Check-all-one result is not all one*/
+
+/*--------------------------------------------------------------------------------------------------*/
+/* Random Number Generator Constant Definitions */
+/*--------------------------------------------------------------------------------------------------*/
+#define BL_RNG_PRNG (0UL) /*!<Use H/W random number generator */
+#define BL_RNG_SWRNG (1UL) /*!<Use S/W random number generator */
+#define BL_RNG_LIRC32K (0UL) /*!<Use LIRC32 for random number generator */
+#define BL_RNG_LXT (2UL) /*!<Use LXT for random number generator */
+#define XTRNG_PRNG (0UL) /*!<Use H/W random number generator */
+#define XTRNG_SWRNG (1UL) /*!<Use S/W random number generator */
+#define XTRNG_LIRC32K (0UL) /*!<Use LIRC32 for random number generator */
+#define XTRNG_LXT (2UL) /*!<Use LXT for random number generator */
+
+/*--------------------------------------------------------------------------------------------------*/
+/* Maximum SecureISP Mode Transmit/Receive Packet Size Constant Definitions */
+/*--------------------------------------------------------------------------------------------------*/
+#define MAX_PKT_SIZE 64
+
+/*@}*/ /* end of group MKROM_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup MKROM_EXPORTED_STRUCTS MKROM Exported Structs
+ @{
+*/
+/**
+ * @details Random number generator structure
+ */
+typedef struct
+{
+ uint32_t opt; /*!< Operation mode */
+ int32_t data_len; /*!< Internal use for random number generator */
+ uint8_t buf[32]; /*!< Internal use for random number generator */
+ uint8_t buf2[20]; /*!< Internal use for random number generator */
+} BL_RNG_T;
+
+typedef struct
+{
+ uint32_t opt; /*!< Operation mode */
+ int32_t data_len; /*!< Internal use for random number generator */
+ uint8_t buf[32]; /*!< Internal use for random number generator */
+ uint8_t buf2[20]; /*!< Internal use for random number generator */
+} XTRNG_T;
+
+
+/**
+ * @details XCRPT_T is structure for access MKROM Crypto library
+ */
+typedef struct
+{
+ CRPT_T *crpt; /*!< The pointer of the CRYPTO module */
+ ECC_CURVE *pCurve; /*!< Internal use for ECC */
+ ECC_CURVE Curve_Copy; /*!< Internal use for ECC */
+ uint32_t AES_CTL[4]; /*!< AES channel selection */
+ uint32_t TDES_CTL[4]; /*!< TDES channel selection */
+} XCRPT_T;
+
+/*---------------------------------------------------------------------------------------------------*/
+/* Define a global constant XCRPT as the access address of g_xcrpta for using MKROM Crypto library. */
+/*---------------------------------------------------------------------------------------------------*/
+extern XCRPT_T g_xcrpt;
+#define XCRPT (&g_xcrpt)
+
+
+/**
+ * @details Command packet structure for transmit/receive data in SecureISP function
+ */
+typedef struct
+{
+ /* Word-0 */
+ uint16_t u16CRC16; /* CRC16 checksum of from u8CmdID to Word-13 */
+ uint16_t u16CmdID; /* Command ID */
+
+ /* Word-1 */
+ uint16_t u16PacketID; /* Packet ID */
+ uint16_t u16Len; /* Valid data length in command data field */
+
+ /* Word-2 ~ 13 */
+ uint32_t au32Data[12]; /* Data fields */
+
+ /* Word-14 */
+ uint32_t u32CRC32; /* CRC32 from Word-0 to Word-13 for check cmd integrity */
+
+ /* Word-15 */
+ uint32_t RSVD; /* Reserved */
+
+} CMD_PACKET_T;
+
+
+/**
+ * @details ECC public key structure
+ */
+typedef struct
+{
+ uint32_t au32Key0[8]; /* 256-bits */
+ uint32_t au32Key1[8]; /* 256-bits */
+} __attribute__((packed)) ECC_PUBKEY_T;
+
+
+/**
+ * @details ECC ECDSA signature structure
+ */
+typedef struct
+{
+ uint32_t au32R[8]; /* 256-bits */
+ uint32_t au32S[8]; /* 256-bits */
+} __attribute__((packed)) ECDSA_SIGN_T;
+
+
+/**
+ * @details SecureISP operation mode enumerate
+ */
+typedef enum
+{
+ USB_MODE = 0x1,
+ UART_MODE = 0x2,
+ USB_UART_MODE = 0x3,
+ RESYNC_ISP = 0x80, /* To set SecureISP in waiting connection state */
+} E_ISP_MODE;
+
+
+/**
+ * @details Global ISP information data for perform SecureISP function
+ */
+typedef void (*ISPCallback)(uint32_t *pu32Buf, uint32_t u32Data);
+typedef void (*USBDEPFunc)(void);
+typedef struct
+{
+ uint32_t u32CmdMask; /* Disable the specify command in SecureISP */
+
+ uint32_t au32AESKey[8]; /* AES-256 keys */
+ uint32_t au32AESIV[4]; /* AES IV, 128-bits */
+
+ ECC_PUBKEY_T ClientPubKey; /* Client's ECC public key, 64-bytes (256-bits + 256-bits) */
+ ECC_PUBKEY_T ServerPubKey; /* Server's ECC public key, 64-bytes (256-bits + 256-bits) */
+
+ ECDSA_SIGN_T sign; /* 64-bytes (256-bits R + 256-bits S) */
+
+ uint32_t IsConnectOK; /* Internal use in SecureISP */
+ uint32_t timeout; /* Timeout period for connecting to SecureISP Tool */
+
+ __attribute__((aligned(4))) uint8_t rcvbuf[MAX_PKT_SIZE]; /* Internal use in SecureISP */
+ __attribute__((aligned(4))) uint8_t rspbuf[MAX_PKT_SIZE]; /* Internal use in SecureISP */
+
+ USBDEPFunc pfnUSBDEP[USBD_MAX_EP]; /* Internal use in SecureISP */
+ uint32_t IsUSBDataReady; /* Internal use in SecureISP */
+
+ uint32_t UARTClockFreq; /* UART clock frequency */
+ uint32_t UARTDataIdx; /* Internal use in SecureISP */
+ uint32_t IsUARTDataReady; /* Internal use in SecureISP */
+
+ ISPCallback pfnVendorFunc; /* Vendor function address */
+
+ uint32_t tmp0[8]; /* Internal use in SecureISP */
+ uint32_t tmp1[8]; /* Internal use in SecureISP */
+
+} ISP_INFO_T;
+
+
+/**
+ * @details Global USBD data for SecureISP USB
+ * @note This data is internal use in SecureISP operation
+ */
+typedef struct
+{
+ uint8_t g_usbd_SetupPacket[8];
+ volatile uint8_t g_usbd_RemoteWakeupEn;
+ volatile uint8_t g_usbd_u8ZeroFlag;
+
+ volatile uint8_t *g_usbd_CtrlInPointer;
+ volatile uint8_t *g_usbd_CtrlOutPointer;
+ volatile uint32_t g_usbd_CtrlInSize;
+ volatile uint32_t g_usbd_CtrlOutSize;
+ volatile uint32_t g_usbd_CtrlOutSizeLimit;
+ volatile uint32_t g_usbd_UsbAddr;
+ volatile uint32_t g_usbd_UsbConfig;
+ volatile uint32_t g_usbd_CtrlMaxPktSize;
+ volatile uint32_t g_usbd_UsbAltInterface;
+
+ S_USBD_INFO_T *g_usbd_sInfo;
+
+ VENDOR_REQ g_usbd_pfnVendorRequest;
+ CLASS_REQ g_usbd_pfnClassRequest;
+ SET_INTERFACE_REQ g_usbd_pfnSetInterface;
+ SET_CONFIG_CB g_usbd_pfnSetConfigCallback;
+ uint32_t g_u32EpStallLock;
+
+} BL_USBD_INFO_T;
+
+
+/*@}*/ /* end of group MKROM_EXPORTED_STRUCTS */
+
+
+/** @addtogroup MKROM_EXPORTED_FUNCTIONS Bootloader Exported Functions
+ @{
+*/
+/**
+ * @brief Get MKROM Version Number
+ * @param None
+ * @return Version number of MKROM
+ * @details This API will return the MKROM version number.
+ */
+uint32_t BL_GetVersion(void);
+
+
+/**
+ * @brief Enable FMC ISP Function and return maximum APROM size
+ * @param None
+ * @return Maximum APROM size
+ * @details This API will unlock register write-protect, enable relative settings for access FMC ISP commands
+ * and return maximum APROM by chip package.
+ */
+uint32_t BL_EnableFMC(void);
+
+
+/**
+ * @brief Disable FMC ISP Function
+ * @param None
+ * @return None
+ * @details This API will disable relative settings for disable FMC ISP function and lock register write-protect
+ * until last ISP operation is finished.
+ */
+void BL_DisableFMC(void);
+
+
+/**
+ * @brief Get FMC ISP Busy Status
+ * @param None
+ * @retval 0 ISP operation is finished
+ * @retval 1 ISP operation is in processing
+ * @details This API indicates ISP operation in in processing or finished.
+ */
+uint32_t BL_GetISPStatus(void);
+
+
+/**
+ * @brief Get Non-secure Boundary
+ * @param None
+ * @return Current Non-secure boundary
+ * @details This API can get current Non-secure boundary address.
+ */
+uint32_t BL_GetNSBoundary(void);
+
+
+/**
+ * @brief Set All Flash Region Lock
+ * @param None
+ * @retval -1 Set flash all lock failed
+ * @retval 0 Set flash all lock operation is success
+ * @details This API will protect all flash region read/write operate by ICE interface.
+ */
+int32_t BL_SetFlashAllLock(void);
+
+
+/**
+ * @brief Read Non-secure Flash Address Data (for Non-secure region)
+ * @param[in] u32NSAddr Non-secure flash address
+ * @retval 0xF0F00000 u32NSAddr isn't in Non-secure area
+ * @retval 0xF0F00001 u32NSAddr isn't word aligned
+ * @retval 0xF0F00003 u32NSAddr isn't valid flash address
+ * @retval -1 Flash read failed
+ * @retval The data of specified Non-secure address
+ * @details To read word data from specified Non-secure flash address.
+ */
+uint32_t BL_FlashRead(uint32_t u32NSAddr);
+
+
+/**
+ * @brief Read Multi-Word Data from Non-secure Flash Address (for Non-secure region)
+ * @param[in] u32NSAddr Starting Non-secure flash address
+ * @param[out] pu32NSRamBuf Non-secure sram address to store reading data
+ * @param[in] u32Size Total read byte counts, it should be word aligned and maximum size is one page size.
+ * @retval 0xF0F00000 u32NSAddr or pu32NSRamBuf region isn't in Non-secure area
+ * @retval 0xF0F00001 Wrong u32NSAddr, pu32NSRamBuf or u32Size parameter
+ * @retval 0xF0F00003 u32NSAddr isn't valid flash address
+ * @retval 0xF0F00004 pu32NSRamBuf isn't valid sram address
+ * @retval -1 Multi-words read failed
+ * @retval 0 Read operation is success
+ * @details To read multi-words data start from specified Non-secure flash address.
+ * And maximum read size is one page size, 2048 bytes.
+ */
+int32_t BL_FlashMultiRead(uint32_t u32NSAddr, uint32_t *pu32NSRamBuf, uint32_t u32Size);
+
+
+/**
+ * @brief Program Data into Non-secure Flash Address (for Non-secure region)
+ * @param[in] u32NSAddr Non-secure flash address
+ * @param[in] u32Data 32-bit Data to program
+ * @retval 0xF0F00000 u32NSAddr isn't in Non-secure area
+ * @retval 0xF0F00001 u32NSAddr isn't word aligned
+ * @retval 0xF0F00003 u32NSAddr isn't valid flash address
+ * @retval -1 Flash write failed
+ * @retval 0 Program command is finished
+ * @details To program word data into specified Non-secure flash address.
+ */
+int32_t BL_FlashWrite(uint32_t u32NSAddr, uint32_t u32Data);
+
+
+/**
+ * @brief Program Multi-Word Data into Non-secure Flash Address (for Non-secure region)
+ * @param[in] u32NSAddr Starting Non-secure flash address
+ * @param[in] pu32NSRamBuf Non-secure sram buffer address to store program data
+ * @param[in] u32Size Total program byte counts, it should be word aligned and maximum size is one page size.
+ * @retval 0xF0F00000 u32NSAddr or pu32NSRamBuf region isn't in Non-secure area
+ * @retval 0xF0F00001 Wrong u32NSAddr, pu32NSRamBuf or u32Size parameter
+ * @retval 0xF0F00003 u32NSAddr isn't valid flash address
+ * @retval 0xF0F00004 pu32NSRamBuf isn't valid sram address
+ * @retval -1 Multi-words write failed
+ * @retval 0 Program operation is finished
+ * @details To program multi-words data start from specified Non-secure flash address.
+ * And maximum program size is one page size, 2048 bytes.
+ */
+int32_t BL_FlashMultiWrite(uint32_t u32NSAddr, uint32_t *pu32NSRamBuf, uint32_t u32Size);
+
+
+/**
+ * @brief Non-secure Flash Page Erase (for Non-secure region)
+ * @param[in] u32NSAddr Non-secure flash region to be erased and must be a page size aligned address.
+ * @retval 0xF0F00000 u32NSAddr region isn't in Non-secure area
+ * @retval 0xF0F00001 u32NSAddr isn't page size aligned
+ * @retval 0xF0F00003 u32NSAddr isn't valid flash address
+ * @retval -1 Page erase failed
+ * @retval 0 Page erase success
+ * @details This API is used to perform page erase command on specified Non-secure flash address.
+ * And this address must be a page size aligned address.
+ */
+int32_t BL_FlashPageErase(uint32_t u32NSAddr);
+
+
+/**
+ * @brief Get Non-secure Flash Area CRC32 Checksum (for Non-secure region)
+ * @param[in] u32NSAddr Non-secure flash region to be calculated. u32NSAddr must be a page size aligned address.
+ * @param[in] u32ByteCount Byte counts of Non-secure flash area to be calculated. It must be multiple of 2048 bytes.
+ * @retval 0xF0F00000 u32NSAddr region isn't in Non-secure area
+ * @retval 0xF0F00001 Wrong u32NSAddr or u32ByteCount parameter
+ * @retval 0xF0F00003 u32NSAddr isn't valid flash address
+ * @retval -1 Execute CRC32 operation failed
+ * @retval Result of CRC32 checksum
+ * @details This API will calculate the CRC32 checksum result of specified non-secure flash area.
+ * The starting address and calculated size must be all 2048 bytes page size aligned.
+ */
+uint32_t BL_FlashChecksum(uint32_t u32NSAddr, uint32_t u32ByteCount);
+
+
+/**
+ * @brief Check Non-secure Flash Area Data are all ONE or not (for Non-secure region)
+ * @param[in] u32NSAddr Non-secure flash region to be calculated. u32NSAddr must be a page size aligned address.
+ * @param[in] u32ByteCount Byte counts of Non-secure flash area to be calculated. It must be multiple of 2048 bytes.
+ * @retval 0xF0F00000 u32NSAddr region isn't in Non-secure area
+ * @retval 0xF0F00001 Wrong u32NSAddr or u32ByteCount parameter
+ * @retval 0xF0F00003 u32NSAddr isn't valid flash address
+ * @retval -1 Execute Check Flash All One operation failed
+ * @retval 0xA11FFFFF The contents of verified Non-secure flash area are 0xFFFFFFFF
+ * @retval 0xA1100000 Some contents of verified Non-secure flash area are not 0xFFFFFFFF
+ * @details This API is used to check specified Non-secure flash area are all 0xFFFFFFFF or not.
+ */
+uint32_t BL_CheckFlashAllOne(uint32_t u32NSAddr, uint32_t u32ByteCount);
+
+
+/**
+ * @brief Read Company ID
+ * @param None
+ * @return The company ID (32-bit)
+ * @details The company ID of Nuvoton is fixed to be 0xDA.
+ */
+uint32_t BL_ReadCID(void);
+
+
+/**
+ * @brief Read Device ID
+ * @param None
+ * @return The device ID (32-bit)
+ * @details This function is used to read device ID.
+ */
+uint32_t BL_ReadDID(void);
+
+
+/**
+ * @brief Read Product ID
+ * @param None
+ * @return The product ID (32-bit)
+ * @details This function is used to read product ID.
+ */
+uint32_t BL_ReadPID(void);
+
+
+/**
+ * @brief Read UCID
+ * @param[in] u32Index Index of the UCID to read and u32Index must be 0, 1, 2, or 3.
+ * @return The UCID of specified index
+ * @details This function is used to read unique chip ID (UCID).
+ */
+uint32_t BL_ReadUCID(uint32_t u32Index);
+
+
+/**
+ * @brief Read UID
+ * @param[in] u32Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
+ * @return The 32-bit unique ID data of specified UID index
+ * @details To read out specified 32-bit unique ID.
+ */
+uint32_t BL_ReadUID(uint32_t u32Index);
+
+
+/**
+ * @brief Get XOM Active Status
+ * @param[in] u32XOM Specified XOM region, it must be between 0~3.
+ * @retval 0xF0F00001 Invalid u32XOM number
+ * @retval 0 Current XOM region isn't active yet
+ * @retval 1 Current XOM region is active
+ * @details This API will return specified XOM region active status.
+ */
+uint32_t BL_GetXOMActiveStatus(uint32_t u32XOM);
+
+
+/**
+ * @brief Read XOM Setting (for Non-secure region)
+ * @param[in] u32XOM Specified XOM region, it must be between 0~3
+ * @param[out] pu32Base Return specified XOM base address
+ * @param[out] pu32PageCnt Return specified XOM page count
+ * @retval 0xF0F00000 pu32Base, pu32PageCnt or XOM base address isn't in Non-secure area
+ * @retval 0xF0F00001 Wrong u32XOM, pu32Base or pu32PageCnt parameter
+ * @retval 0xF0F00003 XOM base address isn't valid flash address
+ * @retval 0xF0F00004 pu32Base or pu32PageCnt isn't valid sram address
+ * @retval 0xF0F00005 XOM region isn't configured
+ * @retval 0 Read specified XOM setting success
+ * @details This API will read specified XOM relative settings.
+ */
+int32_t BL_ReadXOMRegion(uint32_t u32XOM, uint32_t *pu32Base, uint32_t *pu32PageCnt);
+
+
+/**
+ * @brief Set XOM Region and Active (for Non-secure region)
+ * @param[in] u32XOM Specified XOM region, it must be between 0~3
+ * @param[in] u32Base Base address of XOM region
+ * @param[in] u32PageCnt Page count of XOM region
+ * @param[in] u32IsDebugMode 1: Enable XOM debug mode; others will disable XOM debug mode.
+ * @retval 0xF0F00000 XOM region isn't in Non-secure area
+ * @retval 0xF0F00001 Wrong u32XOM, u32Base or u32PageCnt parameter
+ * @retval 0xF0F00003 u32Base isn't valid flash address
+ * @retval 0xF0F00006 XOM region has configured
+ * @retval 0xF0F00007 XOM region has active
+ * @retval -1 Set XOM failed
+ * @retval 0 Set specified XOM success
+ * @details This API will set specified XOM active.
+ */
+int32_t BL_SetXOMRegion(uint32_t u32XOM, uint32_t u32Base, uint32_t u32PageCnt, uint32_t u32IsDebugMode);
+
+
+/**
+ * @brief Erase XOM Setting (for Non-secure region)
+ * @param[in] u32XOMBase Specified XOM region to be erase
+ * @retval 0xF0F00000 u32XOMBase or erase XOM region isn't in Non-secure area
+ * @retval 0xF0F00001 u32XOMBase isn't page size aligned
+ * @retval 0xF0F00003 u32XOMBase isn't valid flash address
+ * @retval 0xF0F00008 Invalid u32XOMBase address
+ * @retval -1 Erase XOM region failed
+ * @retval 0 Erase XOM region success
+ * @details This API will erase specified XOM region data and relative XOM setting.
+ */
+int32_t BL_EraseXOMRegion(uint32_t u32XOMBase);
+
+
+/**
+ * @brief Get XOM Erased Status
+ * @param None
+ * @retval -1 Erase XOM operation failed
+ * @retval 0 Erase XOM operation success
+ * @details This API will return the XOM erase operation is success or not.
+ */
+int32_t BL_GetXOMEraseStatus(void);
+
+
+/**
+ * @brief Read KPKEYSTS Status
+ * @param None
+ * @return KPKEYSTS register status
+ * @details This API can read KPROM KPKEYSTS register status.
+ */
+uint32_t BL_GetKPROMStatus(void);
+
+
+/**
+ * @brief Read KPKEYCNT Status
+ * @param None
+ * @return KPKEYCNT register status
+ * @details This API can read KPROM KPKEYCNT register status.
+ */
+uint32_t BL_GetKPROMCounter(void);
+
+
+/**
+ * @brief Read KPCNT Status
+ * @param None
+ * @return KPCNT register status
+ * @details This API can read KPROM KPCNT register status.
+ */
+uint32_t BL_GetKPROMPowerOnCounter(void);
+
+
+/**
+ * @brief Execute KPROM Key Comparison
+ * @param[in] key0 KPROM key0
+ * @param[in] key1 KPROM key1
+ * @param[in] key2 KPROM key2
+ * @retval 0xF0F00009 KPROM function isn't enabled
+ * @retval 0xF0F0000A Trigger KPROM key comparison is FORBID
+ * @retval 0xF0F0000B KPROM Key is mismatch
+ * @retval 0xF0F0000C KPROM key still locked
+ * @retval 0 KPROM Key are matched
+ * @details With this API, user can unlock KPROM write-protection and then execute FMC program command well.
+ */
+int32_t BL_TrgKPROMCompare(uint32_t key0, uint32_t key1, uint32_t key2);
+
+
+/**
+ * @brief Execute CHIP Reset
+ * @param None
+ * @return None
+ * @details This API will perform reset CHIP command to reset chip.
+ */
+void BL_ResetChip(void);
+
+
+/*--------------------------------------------------------------------------------------------------*/
+/* The following functions are for Secure code only */
+/*--------------------------------------------------------------------------------------------------*/
+/**
+ * @brief Check if ECC Private Key Valid
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] ecc_curve The pre-defined ECC curve.
+ * @param[in] private_k The input private key.
+ * @return 1 Is valid.
+ * @return 0 Is not valid.
+ * @return -1 Invalid curve.
+ * @details This API is used to check if the private key is placed in valid range of curve.
+ */
+int32_t XECC_IsPrivateKeyValid(XCRPT_T *xcrpt, E_ECC_CURVE ecc_curve, char private_k[]);
+
+
+/**
+ * @brief Generate ECC Public Key
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] ecc_curve The pre-defined ECC curve.
+ * @param[in] private_k The input private key.
+ * @param[out] public_k1 The output public key 1.
+ * @param[out] public_k2 The output public key 2.
+ * @return 0 Success.
+ * @return -1 "ecc_curve" value is invalid.
+ * @details This API is used to generate a public key pair by a specified ECC private key and ECC curve.
+ */
+int32_t XECC_GeneratePublicKey(XCRPT_T *xcrpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]);
+
+
+/**
+ * @brief Generate ECDSA Signature
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] ecc_curve The pre-defined ECC curve.
+ * @param[in] message The hash value of source context.
+ * @param[in] d The private key.
+ * @param[in] k The selected random integer.
+ * @param[out] R R of the (R,S) pair digital signature
+ * @param[out] S S of the (R,S) pair digital signature
+ * @return 0 Success.
+ * @return -1 "ecc_curve" value is invalid.
+ * @details This API is used to generate an ECDSA digital signature.
+ */
+int32_t XECC_GenerateSignature(XCRPT_T *xcrpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S);
+
+
+/**
+ * @brief Verify ECDSA Signature
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] ecc_curve The pre-defined ECC curve.
+ * @param[in] message The hash value of source context.
+ * @param[in] public_k1 The public key 1.
+ * @param[in] public_k2 The public key 2.
+ * @param[in] R R of the (R,S) pair digital signature
+ * @param[in] S S of the (R,S) pair digital signature
+ * @return 0 Success.
+ * @return -1 "ecc_curve" value is invalid.
+ * @return -2 Verification failed.
+ * @details This API is used to perform the ECDSA digital signature verification.
+ */
+int32_t XECC_VerifySignature(XCRPT_T *xcrpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S);
+
+
+/**
+ * @brief Generate ECDH Secret Shared Key
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] ecc_curve The pre-defined ECC curve.
+ * @param[in] private_k One's own private key.
+ * @param[in] public_k1 The other party's public key 1.
+ * @param[in] public_k2 The other party's public key 2.
+ * @param[out] secret_z The ECC CDH secret Z.
+ * @return 0 Success.
+ * @return -1 "ecc_curve" value is invalid.
+ * @details This API is used to generate an ECDH shared key.
+ */
+int32_t XECC_GenerateSecretZ(XCRPT_T *xcrpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]);
+
+
+/**
+ * @brief Convert Data to Hex Format
+ * @param[in] count Byte counts for convert.
+ * @param[in] reg The input data buffer.
+ * @param[out] output The output data buffer.
+ * @return None
+ * @details This API is used to convert the data to hex format.
+ */
+void XECC_Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]);
+
+
+/**
+ * @brief Convert Data to Register Format
+ * @param[in] input The input data buffer.
+ * @param[out] reg The output data buffer.
+ * @return None
+ * @details This API is used to convert the data in a register data format.
+ */
+void XECC_Hex2Reg(char input[], uint32_t volatile reg[]);
+
+
+/**
+ * @brief Get ID ECC R, S digital signature (for Secure code)
+ * @param[out] R R of the (R,S) pair digital signature
+ * @param[out] S S of the (R,S) pair digital signature
+ * @retval -1 Get R, S digital signature fail
+ * @retval 0 Success
+ * @details This API will return ECC R, S digital signature of chip ID, include PDID, UID0~2 and UCID0~3.
+ */
+int32_t XECC_GetIDECCSignature(uint32_t *R, uint32_t *S);
+
+
+/**
+ * @brief Open TDES Encrypt/Decrypt
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32Channel TDES channel. Must be 0~3.
+ * @param[in] u32EncDec 1: TDES encode; 0: TDES decode
+ * @param[in] Is3DES 1: TDES; 0: DES
+ * @param[in] Is3Key 1: TDES 3 key mode; 0: TDES 2 key mode
+ * @param[in] u32OpMode TDES operation mode, including:
+ * - \ref TDES_MODE_ECB
+ * - \ref TDES_MODE_CBC
+ * - \ref TDES_MODE_CFB
+ * - \ref TDES_MODE_OFB
+ * - \ref TDES_MODE_CTR
+ * @param[in] u32SwapType is TDES input/output data swap control and word swap control, including:
+ * - \ref TDES_NO_SWAP
+ * - \ref TDES_WHL_SWAP
+ * - \ref TDES_OUT_SWAP
+ * - \ref TDES_OUT_WHL_SWAP
+ * - \ref TDES_IN_SWAP
+ * - \ref TDES_IN_WHL_SWAP
+ * - \ref TDES_IN_OUT_SWAP
+ * - \ref TDES_IN_OUT_WHL_SWAP
+ * @return None
+ * @details This API is used to enable TDES encrypt/decrypt function.
+ */
+void XTDES_Open(XCRPT_T *xcrpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType);
+
+
+/**
+ * @brief Start TDES Encrypt/Decrypt
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32Channel TDES channel. Must be 0~3.
+ * @param[in] u32DMAMode TDES DMA control, including:
+ * - \ref CRYPTO_DMA_ONE_SHOT One shot TDES encrypt/decrypt.
+ * - \ref CRYPTO_DMA_CONTINUE Continuous TDES encrypt/decrypt.
+ * - \ref CRYPTO_DMA_LAST Last TDES encrypt/decrypt of a series of XTDES_Start.
+ * @return None
+ * @details This API is used to start TDES encrypt/decrypt.
+ */
+void XTDES_Start(XCRPT_T *xcrpt, int32_t u32Channel, uint32_t u32DMAMode);
+
+
+/**
+ * @brief Set TDES Keys
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32Channel TDES channel. Must be 0~3.
+ * @param[in] au32Keys The TDES keys. au32Keys[0][0] is Key0 high word and au32Keys[0][1] is key0 low word.
+ * @return None
+ * @details This API is used to set TDES keys.
+ */
+void XTDES_SetKey(XCRPT_T *xcrpt, uint32_t u32Channel, uint32_t au32Keys[3][2]);
+
+
+/**
+ * @brief Set TDES Initial Vectors
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32Channel TDES channel. Must be 0~3.
+ * @param[in] u32IVH TDES initial vector high word.
+ * @param[in] u32IVL TDES initial vector low word.
+ * @return None
+ * @details This API is used to set TDES initial vectors.
+ */
+void XTDES_SetInitVect(XCRPT_T *xcrpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL);
+
+
+/**
+ * @brief Set TDES DMA Transfer Configuration
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32Channel TDES channel. Must be 0~3.
+ * @param[in] u32SrcAddr TDES DMA source address
+ * @param[in] u32DstAddr TDES DMA destination address
+ * @param[in] u32TransCnt TDES DMA transfer byte count
+ * @return None
+ * @details This API is used to configure the TDES DMA transfer.
+ */
+void XTDES_SetDMATransfer(XCRPT_T *xcrpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
+
+
+/**
+ * @brief Open SHA Encrypt
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32OpMode SHA operation mode, including:
+ * - \ref SHA_MODE_SHA1
+ * - \ref SHA_MODE_SHA224
+ * - \ref SHA_MODE_SHA256
+ * - \ref SHA_MODE_SHA384
+ * - \ref SHA_MODE_SHA512
+ * @param[in] u32SwapType is the SHA input/output data swap control, including:
+ * - \ref SHA_NO_SWAP
+ * - \ref SHA_OUT_SWAP
+ * - \ref SHA_IN_SWAP
+ * - \ref SHA_IN_OUT_SWAP
+ * @param[in] hmac_key_len HMAC key byte count
+ * @return None
+ * @details This API is used to enable SHA encrypt function.
+ */
+void XSHA_Open(XCRPT_T *xcrpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len);
+
+
+/**
+ * @brief Start SHA Encrypt
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32DMAMode SHA DMA control, including:
+ * - \ref CRYPTO_DMA_ONE_SHOT One shot SHA encrypt.
+ * - \ref CRYPTO_DMA_CONTINUE Continuous SHA encrypt.
+ * - \ref CRYPTO_DMA_LAST Last SHA encrypt of a series of XSHA_Start.
+ * @return None
+ * @details This API is used to start SHA encrypt.
+ */
+void XSHA_Start(XCRPT_T *xcrpt, uint32_t u32DMAMode);
+
+
+/**
+ * @brief Set SHA DMA Transfer Configuration
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32SrcAddr SHA DMA source address
+ * @param[in] u32TransCnt SHA DMA transfer byte count
+ * @return None
+ * @details This API is used to configure the SHA DMA transfer.
+ */
+void XSHA_SetDMATransfer(XCRPT_T *xcrpt, uint32_t u32SrcAddr, uint32_t u32TransCnt);
+
+
+/**
+ * @brief Read SHA Digest
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[out] u32Digest The SHA encrypt output digest.
+ * @return None
+ * @details This API is used to read the SHA digest.
+ */
+void XSHA_Read(XCRPT_T *xcrpt, uint32_t u32Digest[]);
+
+
+/**
+ * @brief Open AES Encrypt/Decrypt
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32Channel AES channel. Must be 0~3.
+ * @param[in] u32EncDec 1: AES encode; 0: AES decode
+ * @param[in] u32OpMode AES operation mode, including:
+ * - \ref AES_MODE_ECB
+ * - \ref AES_MODE_CBC
+ * - \ref AES_MODE_CFB
+ * - \ref AES_MODE_OFB
+ * - \ref AES_MODE_CTR
+ * - \ref AES_MODE_CBC_CS1
+ * - \ref AES_MODE_CBC_CS2
+ * - \ref AES_MODE_CBC_CS3
+ * @param[in] u32KeySize is AES key size, including:
+ * - \ref AES_KEY_SIZE_128
+ * - \ref AES_KEY_SIZE_192
+ * - \ref AES_KEY_SIZE_256
+ * @param[in] u32SwapType is AES input/output data swap control, including:
+ * - \ref AES_NO_SWAP
+ * - \ref AES_OUT_SWAP
+ * - \ref AES_IN_SWAP
+ * - \ref AES_IN_OUT_SWAP
+ * @return None
+ * @details This API is used to enable AES encrypt/decrypt function.
+ */
+void XAES_Open(XCRPT_T *xcrpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType);
+
+
+/**
+ * @brief Start AES Encrypt/Decrypt
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32Channel AES channel. Must be 0~3.
+ * @param[in] u32DMAMode AES DMA control, including:
+ * - \ref CRYPTO_DMA_ONE_SHOT One shot AES encrypt/decrypt.
+ * - \ref CRYPTO_DMA_CONTINUE Continuous AES encrypt/decrypt.
+ * - \ref CRYPTO_DMA_LAST Last AES encrypt/decrypt of a series of XAES_Start.
+ * @return None
+ * @details This API is used to start AES encrypt/decrypt.
+ */
+void XAES_Start(XCRPT_T *xcrpt, int32_t u32Channel, uint32_t u32DMAMode);
+
+
+/**
+ * @brief Set AES Keys
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32Channel AES channel. Must be 0~3.
+ * @param[in] au32Keys An word array contains AES keys.
+ * @param[in] u32KeySize is AES key size, including:
+ * - \ref AES_KEY_SIZE_128
+ * - \ref AES_KEY_SIZE_192
+ * - \ref AES_KEY_SIZE_256
+ * @return None
+ * @details This API is used to set AES keys.
+ */
+void XAES_SetKey(XCRPT_T *xcrpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize);
+
+
+/**
+ * @brief Set AES Initial Vectors
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32Channel AES channel. Must be 0~3.
+ * @param[in] au32IV A four entry word array contains AES initial vectors.
+ * @return None
+ * @details This API is used to set AES initial vectors.
+ */
+void XAES_SetInitVect(XCRPT_T *xcrpt, uint32_t u32Channel, uint32_t au32IV[]);
+
+
+/**
+ * @brief Set AES DMA Transfer Configuration
+ * @param[in] xcrpt The pointer of the global XCRPT data
+ * @param[in] u32Channel AES channel. Must be 0~3.
+ * @param[in] u32SrcAddr AES DMA source address
+ * @param[in] u32DstAddr AES DMA destination address
+ * @param[in] u32TransCnt AES DMA transfer byte count
+ * @return None
+ * @details This API is used to configure the AES DMA transfer.
+ */
+void XAES_SetDMATransfer(XCRPT_T *xcrpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
+
+
+/**
+ * @brief Initial Random Number Generator (for Secure code)
+ *
+ * @param[in] rng The structure of random number generator
+ * @param[in] opt Operation modes. Possible options are,
+ * (XTRNG_PRNG | XTRNG_LIRC32K),
+ * (XTRNG_PRNG | XTRNG_LXT),
+ * (XTRNG_SWRNG | XTRNG_LIRC32K),
+ * (XTRNG_SWRNG | XTRNG_LXT)
+ * @retval -1 Fail
+ * @retval 0 Success
+ *
+ * @details This API is used to initial random number generator.
+ * After initial this API success, user can call XTRNG_Random API to generate the random number.
+ */
+int32_t XTRNG_RandomInit(XTRNG_T *rng, uint32_t opt);
+
+
+/**
+ * @brief Generate Random Number (for Secure code)
+ *
+ * @param[in] rng The structure of random number generator
+ * @param[out] p Starting buffer address to store random number
+ * @param[in] size Total byte counts of random number
+ * @retval -1 Fail
+ * @retval 0 Success
+ * @details This API is used to generate random number.
+ */
+int32_t XTRNG_Random(XTRNG_T *rng, uint8_t *p, uint32_t size);
+
+
+/**
+ * @brief Get ID ECC R, S Digital Signature (for Secure code)
+ * @param[out] R R of the (R,S) pair digital signature
+ * @param[out] S S of the (R,S) pair digital signature
+ * @retval -1 Get R, S digital signature fail
+ * @retval 0 Success
+ * @details This API will return ECC R, S digital signature of chip ID, include PDID, UID0~2 and UCID0~3.
+ */
+int32_t BL_GetIDECCSignature(uint32_t *R, uint32_t *S);
+
+
+/**
+ * @brief Initial Random Number Generator (for Secure code)
+ *
+ * @param[in] rng The structure of random number generator
+ * @param[in] opt Operation modes. Possible options are,
+ * (BL_RNG_PRNG | BL_RNG_LIRC32K),
+ * (BL_RNG_PRNG | BL_RNG_LXT),
+ * (BL_RNG_SWRNG | BL_RNG_LIRC32K),
+ * (BL_RNG_SWRNG | BL_RNG_LXT)
+ * @retval -1 Fail
+ * @retval 0 Success
+ *
+ * @details This API is used to initial random number generator.
+ * After initial this API success, user can perform BL_Random API to generate the random number.
+ */
+int32_t BL_RandomInit(BL_RNG_T *rng, uint32_t opt);
+
+
+/**
+ * @brief Generate Random Number (for Secure code)
+ *
+ * @param[in] rng The structure of random number generator
+ * @param[out] p Starting buffer address to store random number
+ * @param[in] size Total byte counts of random number
+ * @retval -1 Fail
+ * @retval 0 Success
+ * @details This API is used to generate random number.
+ */
+int32_t BL_Random(BL_RNG_T *rng, uint8_t *p, uint32_t size);
+
+
+/**
+ * @brief Initialize SecureISP Function (for Secure code)
+ * @param[in] pISPInfo The ISP information data buffer address
+ * @param[in] pUSBDInfo USB data buffer for SecureISP USB
+ * @param[in] mode Operation mode. Possible options are
+ * - \ref USB_MODE
+ * - \ref UART_MODE
+ * - \ref USB_UART_MODE
+ * - \ref RESYNC_ISP
+ * @return Return process status and exit SecureISP mode.
+ * @details Executing this API will initialize USB or UART1 SecureISP function.
+ * User can use SecureISP Tool to communicate with target chip.
+ * @note Configure relate USB and UART1 settings are necessary before executing this API.
+ */
+int32_t BL_SecureISPInit(ISP_INFO_T *pISPInfo, BL_USBD_INFO_T *pUSBDInfo, E_ISP_MODE mode);
+
+
+/**
+ * @brief Process USBD Interrupt (for Secure code)
+ * @param[in] pfnEPTable Starting address to store EP callback function
+ * @param[in] pInfo The ISP information data buffer address
+ * @param[in] pUSBDInfo USB data buffer for SecureISP USB
+ * @retval -1 Execute API in Non-secure code
+ * @retval 0 Process USBD interrupt event success
+ * @details This API is used to process USBD command and should be called in USBD_IRQHandler().
+ */
+int32_t BL_ProcessUSBDInterrupt(uint32_t *pfnEPTable, uint32_t *pInfo, uint32_t *pUSBDInfo);
+
+
+/**
+ * @brief Process UART1 Interrupt (for Secure code)
+ * @param[in] pInfo The ISP information data buffer address
+ * @retval -1 Execute API in Non-secure code
+ * @retval 0 Process UART1 interrupt event success
+ * @details This API is used to process UART1 command and should be called in UART1_IRQHandler().
+ */
+int32_t BL_ProcessUART1Interrupt(uint32_t *pInfo);
+
+
+/**
+ * @brief Get Vendor Data (for Secure code)
+ * @param[in] pInfo The ISP information data buffer address
+ * @param[out] pu32Data Data buffer to store vendor data. Maximum buffer size is 44 bytes.
+ * @param[in] pu32Buf Internal used data buffer address
+ * @retval 0 Success
+ * @retval -1 Invalid command packet
+ * @retval -2 Not in vendor function
+ * @details This API is used to get the vendor data and should be called in the vendor function.
+ */
+int32_t BL_GetVendorData(uint32_t *pInfo, uint32_t *pu32Data, uint32_t *pu32Buf);
+
+
+/**
+ * @brief Return Vendor Data (for Secure code)
+ * @param[in] pu32Data Data buffer to store response data
+ * @param[in] u32Len Data buffer length, maximum size is 40 bytes.
+ * @param[in] pu32Buf Internal used data buffer address
+ * @retval 0 Success
+ * @retval -1 Invalid buffer length
+ * @retval -2 Not in vendor function
+ * @details This API is used to return vendor data to server and should be called in the vendor function.
+ */
+int32_t BL_ReturnVendorData(uint32_t *pu32Data, uint32_t u32Len, uint32_t *pu32Buf);
+
+
+/**
+ * @brief Generate Command Response Data (for Secure code)
+ * @param[in] pCMD Buffer address to store command data
+ * @param[in] pISPInfo The ISP information data buffer address
+ * @retval 0 Command success
+ * @retval Other Command fail
+ * @details This API is used to generate response data to server.
+ */
+int32_t Cmd_GenRspPacket(CMD_PACKET_T *pCMD, ISP_INFO_T *pISPInfo);
+
+
+/**
+ * @brief Parse Command (for Secure code)
+ * @param[in] pCMD Buffer address to store command
+ * @param[in] pISPInfo The ISP information data buffer address
+ * @retval 0 Command success
+ * @retval Other Command fail
+ * @details This API is used to parse data from server.
+ */
+int32_t Cmd_ParseReqPacket(CMD_PACKET_T *pCMD, ISP_INFO_T *pISPInfo);
+
+
+/**
+ * @brief Parse CONNECT Command (for Secure code)
+ * @param[in] pISPInfo The ISP information data buffer address
+ * @retval 0 Success
+ * @retval Other Command fail
+ * @details This API is used for parse CONNECT command only.
+ */
+int32_t ParseCONNECT(ISP_INFO_T *pISPInfo);
+
+
+/**
+ * @brief Parse related ECDH Commands (for Secure code)
+ * @param[in] pISPInfo The ISP information data buffer address
+ * @retval 0 Success
+ * @retval Other Command fail
+ * @details This API is used for parse related ECDH commands.
+ */
+int32_t ParseECDH(ISP_INFO_T *pISPInfo);
+
+
+/**
+ * @brief Parse Commands (for Secure code)
+ * @param[in] pISPInfo The ISP information data buffer address
+ * @retval 0 Success
+ * @retval Other Command fail
+ * @details This API is used for parse all commands except CONNECT and related ECDH commands.
+ */
+int32_t ParseCommands(ISP_INFO_T *pISPInfo);
+
+
+/**
+ * @brief Initialize USBD Module (for Secure code)
+ * @param[in] param The structure of USBD information
+ * @param[in] pfnClassReq USB Class request callback function
+ * @param[in] pfnSetInterface USB Set Interface request callback function
+ * @param[in] pUSBDInfo USB data buffer for SecureISP USB mode
+ * @retval -1 Execute API in Non-secure code
+ * @retval 0 Success
+ * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus.
+ */
+int32_t BL_USBDOpen(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface, uint32_t *pUSBDInfo);
+
+
+/**
+ * @brief Install EP Callback Function (for Secure code)
+ * @param[in] ep EP number
+ * @param[in] pfnEPHandler EP callback function
+ * @param[in] pfnEPTable Starting address to store EP callback function
+ * @retval -1 Fail
+ * @retval 0 Success
+ * @details This function is used to set specific EP callback function
+ */
+int32_t BL_USBDInstallEPHandler(uint32_t ep, void *pfnEPHandler, uint32_t *pfnEPTable);
+
+
+/**
+ * @brief Start USBD Function (for Secure code)
+ * @param None
+ * @retval -1 Execute API in Non-secure code
+ * @retval 0 Success
+ * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer.
+ */
+int32_t BL_USBDStart(void);
+
+
+/*@}*/ /* end of group MKROM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group MKROM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MKROM_LIB_H__ */
+
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
--- /dev/null
+/**************************************************************************//**\r
+ * @file otg.h\r
+ * @version V3.00\r
+ * @brief M2351 series OTG driver header file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ ******************************************************************************/\r
+#ifndef __OTG_H__\r
+#define __OTG_H__\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Include related headers */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#include "M2351.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup OTG_Driver OTG Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants\r
+ @{\r
+*/\r
+\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* OTG constant definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define OTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. */\r
+#define OTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. */\r
+#define OTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. */\r
+#define OTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. */\r
+\r
+\r
+/*@}*/ /* end of group OTG_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Define Macros and functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * @brief This macro is used to enable OTG function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function.\r
+ */\r
+#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to enable OTG function Macro for Non-Secure\r
+ */\r
+#define OTG_ENABLE_NS() (OTG_NS->CTL |= OTG_CTL_OTGEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable OTG function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function.\r
+ */\r
+#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable OTG function Macro for Non-Secure\r
+ */\r
+#define OTG_DISABLE_NS() (OTG_NS->CTL &= ~OTG_CTL_OTGEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to enable USB PHY\r
+ * @param None\r
+ * @return None\r
+ * @details When the USB role is selected as OTG device, use this macro to enable USB PHY.\r
+ * This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY.\r
+ */\r
+#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to enable USB PHY Macro for Non-Secure\r
+ */\r
+#define OTG_ENABLE_PHY_NS() (OTG_NS->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable USB PHY\r
+ * @param None\r
+ * @return None\r
+ * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY.\r
+ */\r
+#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable USB PHY Macro for Non-Secure\r
+ */\r
+#define OTG_DISABLE_PHY_NS() (OTG_NS->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to enable ID detection function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function.\r
+ */\r
+#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to enable ID detection function Macro for Non-Secure\r
+ */\r
+#define OTG_ENABLE_ID_DETECT_NS() (OTG_NS->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable ID detection function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function.\r
+ */\r
+#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable ID detection function Macro for Non-Secure\r
+ */\r
+#define OTG_DISABLE_ID_DETECT_NS() (OTG_NS->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to enable OTG wake-up function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function.\r
+ */\r
+#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to enable OTG wake-up function Macro for Non-Secure\r
+ */\r
+#define OTG_ENABLE_WAKEUP_NS() (OTG_NS->CTL |= OTG_CTL_WKEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable OTG wake-up function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function.\r
+ */\r
+#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to disable OTG wake-up function Macro for Non-Secure\r
+ */\r
+#define OTG_DISABLE_WAKEUP_NS() (OTG_NS->CTL &= ~OTG_CTL_WKEN_Msk)\r
+\r
+/**\r
+ * @brief This macro is used to set the polarity of USB_VBUS_EN pin\r
+ * @param[in] u32Pol The polarity selection. Valid values are listed below.\r
+ * - \ref OTG_VBUS_EN_ACTIVE_HIGH\r
+ * - \ref OTG_VBUS_EN_ACTIVE_LOW\r
+ * @return None\r
+ * @details This macro is used to set the polarity of external USB VBUS power switch enable signal.\r
+ */\r
+#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBENPOL_Pos))\r
+\r
+/**\r
+ * @brief This macro is used to set the polarity of USB_VBUS_EN pin Macro for Non-Secure\r
+ */\r
+#define OTG_SET_VBUS_EN_POL_NS(u32Pol) (OTG_NS->PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBENPOL_Pos))\r
+\r
+/**\r
+ * @brief This macro is used to set the polarity of USB_VBUS_ST pin\r
+ * @param[in] u32Pol The polarity selection. Valid values are listed below.\r
+ * - \ref OTG_VBUS_ST_VALID_HIGH\r
+ * - \ref OTG_VBUS_ST_VALID_LOW\r
+ * @return None\r
+ * @details This macro is used to set the polarity of external USB VBUS power switch status signal.\r
+ */\r
+#define OTG_SET_VBUS_STS_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBSTSPOL_Pos))\r
+\r
+/**\r
+ * @brief This macro is used to set the polarity of USB_VBUS_ST pin Macro for Non-Secure\r
+ */\r
+#define OTG_SET_VBUS_STS_POL_NS(u32Pol) (OTG_NS->PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBSTSPOL_Pos))\r
+\r
+/**\r
+ * @brief This macro is used to enable OTG related interrupts\r
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.\r
+ * - \ref OTG_INTEN_ROLECHGIEN_Msk\r
+ * - \ref OTG_INTEN_VBEIEN_Msk\r
+ * - \ref OTG_INTEN_SRPFIEN_Msk\r
+ * - \ref OTG_INTEN_HNPFIEN_Msk\r
+ * - \ref OTG_INTEN_GOIDLEIEN_Msk\r
+ * - \ref OTG_INTEN_IDCHGIEN_Msk\r
+ * - \ref OTG_INTEN_PDEVIEN_Msk\r
+ * - \ref OTG_INTEN_HOSTIEN_Msk\r
+ * - \ref OTG_INTEN_BVLDCHGIEN_Msk\r
+ * - \ref OTG_INTEN_AVLDCHGIEN_Msk\r
+ * - \ref OTG_INTEN_VBCHGIEN_Msk\r
+ * - \ref OTG_INTEN_SECHGIEN_Msk\r
+ * - \ref OTG_INTEN_SRPDETIEN_Msk\r
+ * @return None\r
+ * @details This macro will enable OTG related interrupts specified by u32Mask parameter.\r
+ */\r
+#define OTG_ENABLE_INT(u32Mask) (OTG->INTEN |= (u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to enable OTG related interrupts Macro for Non-Secure\r
+ */\r
+#define OTG_ENABLE_INT_NS(u32Mask) (OTG_NS->INTEN |= (u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to disable OTG related interrupts\r
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.\r
+ * - \ref OTG_INTEN_ROLECHGIEN_Msk\r
+ * - \ref OTG_INTEN_VBEIEN_Msk\r
+ * - \ref OTG_INTEN_SRPFIEN_Msk\r
+ * - \ref OTG_INTEN_HNPFIEN_Msk\r
+ * - \ref OTG_INTEN_GOIDLEIEN_Msk\r
+ * - \ref OTG_INTEN_IDCHGIEN_Msk\r
+ * - \ref OTG_INTEN_PDEVIEN_Msk\r
+ * - \ref OTG_INTEN_HOSTIEN_Msk\r
+ * - \ref OTG_INTEN_BVLDCHGIEN_Msk\r
+ * - \ref OTG_INTEN_AVLDCHGIEN_Msk\r
+ * - \ref OTG_INTEN_VBCHGIEN_Msk\r
+ * - \ref OTG_INTEN_SECHGIEN_Msk\r
+ * - \ref OTG_INTEN_SRPDETIEN_Msk\r
+ * @return None\r
+ * @details This macro will disable OTG related interrupts specified by u32Mask parameter.\r
+ */\r
+#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to disable OTG related interrupts Macro for Non-Secure\r
+ */\r
+#define OTG_DISABLE_INT_NS(u32Mask) (OTG_NS->INTEN &= ~(u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to get OTG related interrupt flags\r
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.\r
+ * - \ref OTG_INTSTS_ROLECHGIF_Msk\r
+ * - \ref OTG_INTSTS_VBEIF_Msk\r
+ * - \ref OTG_INTSTS_SRPFIF_Msk\r
+ * - \ref OTG_INTSTS_HNPFIF_Msk\r
+ * - \ref OTG_INTSTS_GOIDLEIF_Msk\r
+ * - \ref OTG_INTSTS_IDCHGIF_Msk\r
+ * - \ref OTG_INTSTS_PDEVIF_Msk\r
+ * - \ref OTG_INTSTS_HOSTIF_Msk\r
+ * - \ref OTG_INTSTS_BVLDCHGIF_Msk\r
+ * - \ref OTG_INTSTS_AVLDCHGIF_Msk\r
+ * - \ref OTG_INTSTS_VBCHGIF_Msk\r
+ * - \ref OTG_INTSTS_SECHGIF_Msk\r
+ * - \ref OTG_INTSTS_SRPDETIF_Msk\r
+ * @return Interrupt flags of selected sources.\r
+ * @details This macro will return OTG related interrupt flags specified by u32Mask parameter.\r
+ */\r
+#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to get OTG related interrupt flags Macro for Non-Secure\r
+ */\r
+#define OTG_GET_INT_FLAG_NS(u32Mask) (OTG_NS->INTSTS & (u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to clear OTG related interrupt flags\r
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.\r
+ * - \ref OTG_INTSTS_ROLECHGIF_Msk\r
+ * - \ref OTG_INTSTS_VBEIF_Msk\r
+ * - \ref OTG_INTSTS_SRPFIF_Msk\r
+ * - \ref OTG_INTSTS_HNPFIF_Msk\r
+ * - \ref OTG_INTSTS_GOIDLEIF_Msk\r
+ * - \ref OTG_INTSTS_IDCHGIF_Msk\r
+ * - \ref OTG_INTSTS_PDEVIF_Msk\r
+ * - \ref OTG_INTSTS_HOSTIF_Msk\r
+ * - \ref OTG_INTSTS_BVLDCHGIF_Msk\r
+ * - \ref OTG_INTSTS_AVLDCHGIF_Msk\r
+ * - \ref OTG_INTSTS_VBCHGIF_Msk\r
+ * - \ref OTG_INTSTS_SECHGIF_Msk\r
+ * - \ref OTG_INTSTS_SRPDETIF_Msk\r
+ * @return None\r
+ * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter.\r
+ */\r
+#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to clear OTG related interrupt flags Macro for Non-Secure\r
+ */\r
+#define OTG_CLR_INT_FLAG_NS(u32Mask) (OTG_NS->INTSTS = (u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to get OTG related status\r
+ * @param[in] u32Mask The combination of user specified source. Valid values are listed below.\r
+ * - \ref OTG_STATUS_OVERCUR_Msk\r
+ * - \ref OTG_STATUS_IDSTS_Msk\r
+ * - \ref OTG_STATUS_SESSEND_Msk\r
+ * - \ref OTG_STATUS_BVLD_Msk\r
+ * - \ref OTG_STATUS_AVLD_Msk\r
+ * - \ref OTG_STATUS_VBUSVLD_Msk\r
+ * @return The user specified status.\r
+ * @details This macro will return OTG related status specified by u32Mask parameter.\r
+ */\r
+#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask))\r
+\r
+/**\r
+ * @brief This macro is used to get OTG related status Macro for Non-Secure\r
+ */\r
+#define OTG_GET_STATUS_NS(u32Mask) (OTG_NS->STATUS & (u32Mask))\r
+\r
+\r
+\r
+/*@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group OTG_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __OTG_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file pdma.h\r
+ * @version V3.00\r
+ * @brief M2351 series PDMA driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __PDMA_H__\r
+#define __PDMA_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup PDMA_Driver PDMA Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants\r
+ @{\r
+*/\r
+#define PDMA_CH_MAX 8UL /*!< Specify Maximum Channels of PDMA \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Operation Mode Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */\r
+#define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */\r
+#define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Data Width Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */\r
+#define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */\r
+#define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Address Attribute Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */\r
+#define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */\r
+#define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */\r
+#define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Burst Mode Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */\r
+#define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */\r
+\r
+#define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */\r
+#define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */\r
+#define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */\r
+#define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */\r
+#define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */\r
+#define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */\r
+#define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */\r
+#define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Table Interrupt Disable Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define PDMA_TBINTDIS_ENABLE (0x0UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Enabled \hideinitializer */\r
+#define PDMA_TBINTDIS_DISABLE (0x1UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Disabled \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Peripheral Transfer Mode Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define PDMA_MEM 0x00000000UL /*!<DMA Connect to Memory \hideinitializer */\r
+#define PDMA_USB_TX 0x00000002UL /*!<DMA Connect to USB TX \hideinitializer */\r
+#define PDMA_USB_RX 0x00000003UL /*!<DMA Connect to USB RX \hideinitializer */\r
+#define PDMA_UART0_TX 0x00000004UL /*!<DMA Connect to UART0 TX \hideinitializer */\r
+#define PDMA_UART0_RX 0x00000005UL /*!<DMA Connect to UART0 RX \hideinitializer */\r
+#define PDMA_UART1_TX 0x00000006UL /*!<DMA Connect to UART1 TX \hideinitializer */\r
+#define PDMA_UART1_RX 0x00000007UL /*!<DMA Connect to UART1 RX \hideinitializer */\r
+#define PDMA_UART2_TX 0x00000008UL /*!<DMA Connect to UART2 TX \hideinitializer */\r
+#define PDMA_UART2_RX 0x00000009UL /*!<DMA Connect to UART2 RX \hideinitializer */\r
+#define PDMA_UART3_TX 0x0000000AUL /*!<DMA Connect to UART3 TX \hideinitializer */\r
+#define PDMA_UART3_RX 0x0000000BUL /*!<DMA Connect to UART3 RX \hideinitializer */\r
+#define PDMA_UART4_TX 0x0000000CUL /*!<DMA Connect to UART4 TX \hideinitializer */\r
+#define PDMA_UART4_RX 0x0000000DUL /*!<DMA Connect to UART4 RX \hideinitializer */\r
+#define PDMA_UART5_TX 0x0000000EUL /*!<DMA Connect to UART5 TX \hideinitializer */\r
+#define PDMA_UART5_RX 0x0000000FUL /*!<DMA Connect to UART5 RX \hideinitializer */\r
+#define PDMA_USCI0_TX 0x00000010UL /*!<DMA Connect to USCI0 TX \hideinitializer */\r
+#define PDMA_USCI0_RX 0x00000011UL /*!<DMA Connect to USCI0 RX \hideinitializer */\r
+#define PDMA_USCI1_TX 0x00000012UL /*!<DMA Connect to USCI1 TX \hideinitializer */\r
+#define PDMA_USCI1_RX 0x00000013UL /*!<DMA Connect to USCI1 RX \hideinitializer */\r
+#define PDMA_QSPI0_TX 0x00000014UL /*!<DMA Connect to QSPI0 TX \hideinitializer */\r
+#define PDMA_QSPI0_RX 0x00000015UL /*!<DMA Connect to QSPI0 RX \hideinitializer */\r
+#define PDMA_SPI0_TX 0x00000016UL /*!<DMA Connect to SPI0 TX \hideinitializer */\r
+#define PDMA_SPI0_RX 0x00000017UL /*!<DMA Connect to SPI0 RX \hideinitializer */\r
+#define PDMA_SPI1_TX 0x00000018UL /*!<DMA Connect to SPI1 TX \hideinitializer */\r
+#define PDMA_SPI1_RX 0x00000019UL /*!<DMA Connect to SPI1 RX \hideinitializer */\r
+#define PDMA_SPI2_TX 0x0000001AUL /*!<DMA Connect to SPI2 TX \hideinitializer */\r
+#define PDMA_SPI2_RX 0x0000001BUL /*!<DMA Connect to SPI2 RX \hideinitializer */\r
+#define PDMA_SPI3_TX 0x0000001CUL /*!<DMA Connect to SPI3 TX \hideinitializer */\r
+#define PDMA_SPI3_RX 0x0000001DUL /*!<DMA Connect to SPI3 RX \hideinitializer */\r
+#define PDMA_EPWM0_P1_RX 0x00000020UL /*!<DMA Connect to EPWM0 P1 RX \hideinitializer */\r
+#define PDMA_EPWM0_P2_RX 0x00000021UL /*!<DMA Connect to EPWM0 P2 RX \hideinitializer */\r
+#define PDMA_EPWM0_P3_RX 0x00000022UL /*!<DMA Connect to EPWM0 P3 RX \hideinitializer */\r
+#define PDMA_EPWM1_P1_RX 0x00000023UL /*!<DMA Connect to EPWM1 P1 RX \hideinitializer */\r
+#define PDMA_EPWM1_P2_RX 0x00000024UL /*!<DMA Connect to EPWM1 P2 RX \hideinitializer */\r
+#define PDMA_EPWM1_P3_RX 0x00000025UL /*!<DMA Connect to EPWM1 P3 RX \hideinitializer */\r
+#define PDMA_I2C0_TX 0x00000026UL /*!<DMA Connect to I2C0 TX \hideinitializer */\r
+#define PDMA_I2C0_RX 0x00000027UL /*!<DMA Connect to I2C0 RX \hideinitializer */\r
+#define PDMA_I2C1_TX 0x00000028UL /*!<DMA Connect to I2C1 TX \hideinitializer */\r
+#define PDMA_I2C1_RX 0x00000029UL /*!<DMA Connect to I2C1 RX \hideinitializer */\r
+#define PDMA_I2C2_TX 0x0000002AUL /*!<DMA Connect to I2C2 TX \hideinitializer */\r
+#define PDMA_I2C2_RX 0x0000002BUL /*!<DMA Connect to I2C2 RX \hideinitializer */\r
+#define PDMA_I2S0_TX 0x0000002CUL /*!<DMA Connect to I2S0 TX \hideinitializer */\r
+#define PDMA_I2S0_RX 0x0000002DUL /*!<DMA Connect to I2S0 RX \hideinitializer */\r
+#define PDMA_TMR0 0x0000002EUL /*!<DMA Connect to TMR0 \hideinitializer */\r
+#define PDMA_TMR1 0x0000002FUL /*!<DMA Connect to TMR1 \hideinitializer */\r
+#define PDMA_TMR2 0x00000030UL /*!<DMA Connect to TMR2 \hideinitializer */\r
+#define PDMA_TMR3 0x00000031UL /*!<DMA Connect to TMR3 \hideinitializer */\r
+#define PDMA_ADC_RX 0x00000032UL /*!<DMA Connect to ADC RX \hideinitializer */\r
+#define PDMA_DAC0_TX 0x00000033UL /*!<DMA Connect to DAC0 TX \hideinitializer */\r
+#define PDMA_DAC1_TX 0x00000034UL /*!<DMA Connect to DAC1 TX \hideinitializer */\r
+#define PDMA_EPWM0_CH0_TX 0x00000035UL /*!<DMA Connect to EPWM0 CH0 TX \hideinitializer */\r
+#define PDMA_EPWM0_CH1_TX 0x00000036UL /*!<DMA Connect to EPWM0 CH1 TX \hideinitializer */\r
+#define PDMA_EPWM0_CH2_TX 0x00000037UL /*!<DMA Connect to EPWM0 CH2 TX \hideinitializer */\r
+#define PDMA_EPWM0_CH3_TX 0x00000038UL /*!<DMA Connect to EPWM0 CH3 TX \hideinitializer */\r
+#define PDMA_EPWM0_CH4_TX 0x00000039UL /*!<DMA Connect to EPWM0 CH4 TX \hideinitializer */\r
+#define PDMA_EPWM0_CH5_TX 0x0000003AUL /*!<DMA Connect to EPWM0 CH5 TX \hideinitializer */\r
+#define PDMA_EPWM1_CH0_TX 0x0000003BUL /*!<DMA Connect to EPWM1 CH0 TX \hideinitializer */\r
+#define PDMA_EPWM1_CH1_TX 0x0000003CUL /*!<DMA Connect to EPWM1 CH1 TX \hideinitializer */\r
+#define PDMA_EPWM1_CH2_TX 0x0000003DUL /*!<DMA Connect to EPWM1 CH2 TX \hideinitializer */\r
+#define PDMA_EPWM1_CH3_TX 0x0000003EUL /*!<DMA Connect to EPWM1 CH3 TX \hideinitializer */\r
+#define PDMA_EPWM1_CH4_TX 0x0000003FUL /*!<DMA Connect to EPWM1 CH4 TX \hideinitializer */\r
+#define PDMA_EPWM1_CH5_TX 0x00000040UL /*!<DMA Connect to EPWM1 CH5 TX \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Interrupt Type Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define PDMA_INT_TRANS_DONE 0x00000000UL /*!<Transfer Done Interrupt \hideinitializer */\r
+#define PDMA_INT_TABLE 0x00000001UL /*!<Table Interrupt \hideinitializer */\r
+#define PDMA_INT_TIMEOUT 0x00000002UL /*!<Timeout Interrupt \hideinitializer */\r
+#define PDMA_INT_ALIGN 0x00000003UL /*!<Transfer Alignment Interrupt \hideinitializer */\r
+\r
+\r
+/*@}*/ /* end of group PDMA_EXPORTED_CONSTANTS */\r
+\r
+/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Get PDMA Interrupt Status\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro gets the interrupt status.\r
+ */\r
+#define PDMA_GET_INT_STATUS(pdma) ((uint32_t)((pdma)->INTSTS))\r
+\r
+/**\r
+ * @brief Get Transfer Done Interrupt Status\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Get the transfer done Interrupt status.\r
+ */\r
+#define PDMA_GET_TD_STS(pdma) ((uint32_t)((pdma)->TDSTS))\r
+\r
+/**\r
+ * @brief Clear Transfer Done Interrupt Status\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Mask The channel mask\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Clear the transfer done Interrupt status.\r
+ */\r
+#define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->TDSTS = (u32Mask)))\r
+\r
+/**\r
+ * @brief Get Target Abort Interrupt Status\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Get the target abort Interrupt status.\r
+ */\r
+#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)((pdma)->ABTSTS))\r
+\r
+/**\r
+ * @brief Clear Target Abort Interrupt Status\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Mask The channel mask\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Clear the target abort Interrupt status.\r
+ */\r
+#define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ABTSTS = (u32Mask)))\r
+\r
+/**\r
+ * @brief Get PDMA Transfer Alignment Status\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Get the PDMA transfer alignment status.\r
+ */\r
+#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)((pdma)->ALIGN))\r
+\r
+/**\r
+ * @brief Clear PDMA Transfer Alignment Interrupt Status\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Mask The channel mask\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Clear the PDMA transfer alignment Interrupt status.\r
+ */\r
+#define PDMA_CLR_ALIGN_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ALIGN = (u32Mask)))\r
+\r
+/**\r
+ * @brief Clear Timeout Interrupt Status\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Clear the selected channel timeout interrupt status.\r
+ * @note This function is only supported in channel 0 and channel 1.\r
+ */\r
+#define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)((pdma)->INTSTS = (1UL << ((u32Ch) + 8UL))))\r
+\r
+/**\r
+ * @brief Check Channel Status\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ *\r
+ * @retval 0 Idle state\r
+ * @retval 1 Busy state\r
+ *\r
+ * @details Check the selected channel is busy or not.\r
+ */\r
+#define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)((pdma)->TRGSTS & (1UL << (u32Ch)))? 1 : 0)\r
+\r
+/**\r
+ * @brief Set Source Address\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ * @param[in] u32Addr The selected address\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro set the selected channel source address.\r
+ */\r
+#define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].SA = (u32Addr)))\r
+\r
+/**\r
+ * @brief Set Destination Address\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ * @param[in] u32Addr The selected address\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro set the selected channel destination address.\r
+ */\r
+#define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].DA = (u32Addr)))\r
+\r
+/**\r
+ * @brief Set Transfer Count\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ * @param[in] u32TransCount Transfer Count\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro set the selected channel transfer count.\r
+ */\r
+#define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)((pdma)->DSCT[(u32Ch)].CTL=((pdma)->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1UL) << PDMA_DSCT_CTL_TXCNT_Pos)))\r
+\r
+/**\r
+ * @brief Set Scatter-gather descriptor Address\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ * @param[in] u32Addr The descriptor address\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro set the selected channel scatter-gather descriptor address.\r
+ */\r
+#define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].NEXT = (u32Addr) - ((pdma)->SCATBA)))\r
+\r
+/**\r
+ * @brief Stop the channel\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro stop the selected channel.\r
+ */\r
+#define PDMA_STOP(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch))))\r
+\r
+/**\r
+ * @brief Pause the channel\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro pause the selected channel.\r
+ */\r
+#define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch))))\r
+\r
+/**\r
+ * @brief Reset the channel\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro reset the selected channel.\r
+ */\r
+#define PDMA_RESET(pdma, u32Ch) ((uint32_t)((pdma)->CHRST = (1UL << (u32Ch))))\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Define PWM functions prototype */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask);\r
+void PDMA_Close(PDMA_T *pdma);\r
+void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);\r
+void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount);\r
+void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);\r
+void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr);\r
+void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);\r
+void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask);\r
+void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask);\r
+void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);\r
+void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch);\r
+void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);\r
+void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);\r
+\r
+\r
+/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group PDMA_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __PDMA_H__ */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file qei.h\r
+ * @version V3.00\r
+ * @brief Quadrature Encoder Interface (QEI) driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#ifndef __QEI_H__\r
+#define __QEI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup QEI_Driver QEI Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* QEI counting mode selection constants definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define QEI_CTL_X4_FREE_COUNTING_MODE (0x0<<QEI_CTL_MODE_Pos) /*!< QEI operate in X4 free-counting mode \hideinitializer */\r
+#define QEI_CTL_X2_FREE_COUNTING_MODE (0x1<<QEI_CTL_MODE_Pos) /*!< QEI operate in X2 free-counting mode \hideinitializer */\r
+#define QEI_CTL_X4_COMPARE_COUNTING_MODE (0x2<<QEI_CTL_MODE_Pos) /*!< QEI operate in X4 compare-counting mode \hideinitializer */\r
+#define QEI_CTL_X2_COMPARE_COUNTING_MODE (0x3<<QEI_CTL_MODE_Pos) /*!< QEI operate in X2 compare-counting mode \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* QEI noise filter clock pre-divide selection constants definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define QEI_CTL_NFCLKSEL_DIV1 (0x0<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK \hideinitializer */\r
+#define QEI_CTL_NFCLKSEL_DIV2 (0x1<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/2 \hideinitializer */\r
+#define QEI_CTL_NFCLKSEL_DIV4 (0x2<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/4 \hideinitializer */\r
+#define QEI_CTL_NFCLKSEL_DIV16 (0x3<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/16 \hideinitializer */\r
+#define QEI_CTL_NFCLKSEL_DIV32 (0x4<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/32 \hideinitializer */\r
+#define QEI_CTL_NFCLKSEL_DIV64 (0x5<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/64 \hideinitializer */\r
+\r
+\r
+\r
+\r
+/*@}*/ /* end of group QEI_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Disable QEI compare function\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return None\r
+ * @details This macro disable QEI counter compare function.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_DISABLE_CNT_CMP(qei) ((qei)->CTL &= (~QEI_CTL_CMPEN_Msk))\r
+\r
+/**\r
+ * @brief Enable QEI compare function\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return None\r
+ * @details This macro enable QEI counter compare function.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk)\r
+\r
+/**\r
+ * @brief Disable QEI index latch function\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return None\r
+ * @details This macro disable QEI index trigger counter latch function.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk))\r
+\r
+/**\r
+ * @brief Enable QEI index latch function\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return None\r
+ * @details This macro enable QEI index trigger counter latch function.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk)\r
+\r
+/**\r
+ * @brief Disable QEI index reload function\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return None\r
+ * @details This macro disable QEI index trigger counter reload function.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk))\r
+\r
+/**\r
+ * @brief Enable QEI index reload function\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return None\r
+ * @details This macro enable QEI index trigger counter reload function.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk)\r
+\r
+/**\r
+ * @brief Disable QEI input\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32InputType Input signal type.\r
+ * - \ref QEI_CTL_CHAEN_Msk : QEA input\r
+ * - \ref QEI_CTL_CHAEN_Msk : QEB input\r
+ * - \ref QEI_CTL_IDXEN_Msk : IDX input\r
+ * @return None\r
+ * @details This macro disable specified QEI signal input.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType))\r
+\r
+/**\r
+ * @brief Enable QEI input\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32InputType Input signal type .\r
+ * - \ref QEI_CTL_CHAEN_Msk : QEA input\r
+ * - \ref QEI_CTL_CHBEN_Msk : QEB input\r
+ * - \ref QEI_CTL_IDXEN_Msk : IDX input\r
+ * @return None\r
+ * @details This macro enable specified QEI signal input.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType))\r
+\r
+/**\r
+ * @brief Disable inverted input polarity\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32InputType Input signal type .\r
+ * - \ref QEI_CTL_CHAINV_Msk : QEA Input\r
+ * - \ref QEI_CTL_CHBINV_Msk : QEB Input\r
+ * - \ref QEI_CTL_IDXINV_Msk : IDX Input\r
+ * @return None\r
+ * @details This macro disable specified QEI signal inverted input polarity.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType))\r
+\r
+/**\r
+ * @brief Enable inverted input polarity\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32InputType Input signal type.\r
+ * - \ref QEI_CTL_CHAINV_Msk : QEA Input\r
+ * - \ref QEI_CTL_CHBINV_Msk : QEB Input\r
+ * - \ref QEI_CTL_IDXINV_Msk : IDX Input\r
+ * @return None\r
+ * @details This macro inverse specified QEI signal input polarity.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType))\r
+\r
+/**\r
+ * @brief Disable QEI interrupt\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32IntSel Interrupt type selection.\r
+ * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt\r
+ * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt\r
+ * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt\r
+ * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt\r
+ * @return None\r
+ * @details This macro disable specified QEI interrupt.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_DISABLE_INT(qei, u32IntSel) ((qei)->CTL &= ~(u32IntSel))\r
+\r
+/**\r
+ * @brief Enable QEI interrupt\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32IntSel Interrupt type selection.\r
+ * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt\r
+ * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt\r
+ * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt\r
+ * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt\r
+ * @return None\r
+ * @details This macro enable specified QEI interrupt.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_ENABLE_INT(qei, u32IntSel) ((qei)->CTL |= (u32IntSel))\r
+\r
+/**\r
+ * @brief Disable QEI noise filter\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return None\r
+ * @details This macro disable QEI noise filter function.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_DISABLE_NOISE_FILTER(qei) ((qei)->CTL |= QEI_CTL_NFDIS_Msk)\r
+\r
+/**\r
+ * @brief Enable QEI noise filter\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32ClkSel The sampling frequency of the noise filter clock.\r
+ * - \ref QEI_CTL_NFCLKSEL_DIV1\r
+ * - \ref QEI_CTL_NFCLKSEL_DIV2\r
+ * - \ref QEI_CTL_NFCLKSEL_DIV4\r
+ * - \ref QEI_CTL_NFCLKSEL_DIV16\r
+ * - \ref QEI_CTL_NFCLKSEL_DIV32\r
+ * - \ref QEI_CTL_NFCLKSEL_DIV64\r
+ * @return None\r
+ * @details This macro enable QEI noise filter function and select noise filter clock.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel) ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel))\r
+\r
+/**\r
+ * @brief Get QEI counter value\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return QEI pulse counter register value.\r
+ * @details This macro get QEI pulse counter value.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_GET_CNT_VALUE(qei) ((qei)->CNT)\r
+\r
+/**\r
+ * @brief Get QEI counting direction\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @retval 0 QEI counter is in down-counting.\r
+ * @retval 1 QEI counter is in up-counting.\r
+ * @details This macro get QEI counting direction.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_GET_DIR(qei) (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0)\r
+\r
+/**\r
+ * @brief Get QEI counter hold value\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return QEI pulse counter hold register value.\r
+ * @details This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_GET_HOLD_VALUE(qei) ((qei)->CNTHOLD)\r
+\r
+/**\r
+ * @brief Get QEI counter index latch value\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return QEI pulse counter index latch value\r
+ * @details This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_GET_INDEX_LATCH_VALUE(qei) ((qei)->CNTLATCH)\r
+\r
+/**\r
+ * @brief Set QEI counter index latch value\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32Val The latch value.\r
+ * @return QEI pulse counter index latch value\r
+ * @details This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val) ((qei)->CNTLATCH = (u32Val))\r
+\r
+/**\r
+ * @brief Get QEI interrupt flag status\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32IntSel Interrupt type selection.\r
+* - \ref QEI_STATUS_DIRF_Msk : Counting direction flag\r
+ * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag\r
+ * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag\r
+ * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag\r
+ * - \ref QEI_STATUS_IDXF_Msk : Index detected flag\r
+ * @retval 0 QEI specified interrupt flag is not set.\r
+ * @retval 1 QEI specified interrupt flag is set.\r
+ * @details This macro get QEI specified interrupt flag status.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_GET_INT_FLAG(qei, u32IntSel) (((qei)->STATUS & (u32IntSel))?1:0)\r
+\r
+\r
+/**\r
+ * @brief Clear QEI interrupt flag\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32IntSel Interrupt type selection.\r
+ * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag\r
+ * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag\r
+ * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag\r
+ * - \ref QEI_STATUS_IDXF_Msk : Index detected flag\r
+ * @return None\r
+ * @details This macro clear QEI specified interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_CLR_INT_FLAG(qei, u32IntSel) ((qei)->STATUS = (u32IntSel))\r
+\r
+/**\r
+ * @brief Set QEI counter compare value\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32Value The counter compare value.\r
+ * @return None\r
+ * @details This macro set QEI pulse counter compare value.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_SET_CNT_CMP(qei, u32Value) ((qei)->CNTCMP = (u32Value))\r
+\r
+/**\r
+ * @brief Set QEI counter value\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32Value The counter compare value.\r
+ * @return None\r
+ * @details This macro set QEI pulse counter value.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_SET_CNT_VALUE(qei, u32Value) ((qei)->CNT = (u32Value))\r
+\r
+/**\r
+ * @brief Enable QEI counter hold mode\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32Type The triggered type.\r
+ * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control\r
+ * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0\r
+ * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1\r
+ * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2\r
+ * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3\r
+ * @return None\r
+ * @details This macro enable QEI counter hold mode.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL |= (u32Type))\r
+\r
+/**\r
+ * @brief Disable QEI counter hold mode\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32Type The triggered type.\r
+ * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control\r
+ * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0\r
+ * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1\r
+ * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2\r
+ * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3\r
+ * @return None\r
+ * @details This macro disable QEI counter hold mode.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL &= ~(u32Type))\r
+\r
+/**\r
+ * @brief Set QEI maximum count value\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32Value The counter maximum value.\r
+ * @return QEI maximum count value\r
+ * @details This macro set QEI maximum count value.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_SET_CNT_MAX(qei, u32Value) ((qei)->CNTMAX = (u32Value))\r
+\r
+/**\r
+ * @brief Set QEI counting mode\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32Mode QEI counting mode.\r
+ * - \ref QEI_CTL_X4_FREE_COUNTING_MODE\r
+ * - \ref QEI_CTL_X2_FREE_COUNTING_MODE\r
+ * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE\r
+ * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE\r
+ * @return None\r
+ * @details This macro set QEI counting mode.\r
+ * \hideinitializer\r
+ */\r
+#define QEI_SET_CNT_MODE(qei, u32Mode) ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode))\r
+\r
+\r
+void QEI_Close(QEI_T* qei);\r
+void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel);\r
+void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel);\r
+void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value);\r
+void QEI_Start(QEI_T* qei);\r
+void QEI_Stop(QEI_T* qei);\r
+\r
+\r
+/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group QEI_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__QEI_H__*/\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/******************************************************************************
+ * @file qspi.h
+ * @version V3.00
+ * @brief M2351 series QSPI driver header file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __QSPI_H__
+#define __QSPI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup QSPI_Driver QSPI Driver
+ @{
+*/
+
+/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants
+ @{
+*/
+
+#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */
+#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */
+#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */
+#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */
+
+#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave */
+#define QSPI_MASTER (0x0UL) /*!< Set as master */
+
+#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS */
+#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */
+#define QSPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low */
+
+/* QSPI Interrupt Mask */
+#define QSPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask */
+#define QSPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask */
+#define QSPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask */
+#define QSPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask */
+#define QSPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask */
+#define QSPI_SLVTO_INT_MASK (0x020UL) /*!< Slave Mode Time-out interrupt mask */
+#define QSPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask */
+#define QSPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask */
+#define QSPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask */
+#define QSPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask */
+#define QSPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask */
+
+/* QSPI Status Mask */
+#define QSPI_BUSY_MASK (0x01UL) /*!< Busy status mask */
+#define QSPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */
+#define QSPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */
+#define QSPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */
+#define QSPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */
+#define QSPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask */
+#define QSPI_SPIEN_STS_MASK (0x40UL) /*!< SPIEN status mask */
+#define QSPI_SSLINE_STS_MASK (0x80UL) /*!< QSPIx_SS line status mask */
+
+/*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear the unit transfer interrupt flag.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag.
+ */
+#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ( (qspi)->STATUS = QSPI_STATUS_UNITIF_Msk )
+
+/**
+ * @brief Disable 2-bit Transfer mode.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear TWOBIT bit of QSPI_CTL register to disable 2-bit Transfer mode.
+ */
+#define QSPI_DISABLE_2BIT_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TWOBIT_Msk )
+
+/**
+ * @brief Disable Slave 3-wire mode.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear SLV3WIRE bit of QSPI_SSCTL register to disable Slave 3-wire mode.
+ */
+#define QSPI_DISABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL &= ~QSPI_SSCTL_SLV3WIRE_Msk )
+
+/**
+ * @brief Disable Dual I/O mode.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear DUALIOEN bit of QSPI_CTL register to disable Dual I/O mode.
+ */
+#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk )
+
+/**
+ * @brief Disable Quad I/O mode.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear QUADIOEN bit of QSPI_CTL register to disable Quad I/O mode.
+ */
+#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk )
+
+/**
+ * @brief Enable 2-bit Transfer mode.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Set TWOBIT bit of QSPI_CTL register to enable 2-bit Transfer mode.
+ */
+#define QSPI_ENABLE_2BIT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TWOBIT_Msk )
+
+/**
+ * @brief Enable Slave 3-wire mode.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Set SLV3WIRE bit of QSPI_SSCTL register to enable Slave 3-wire mode.
+ */
+#define QSPI_ENABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL |= QSPI_SSCTL_SLV3WIRE_Msk )
+
+/**
+ * @brief Enable Dual input mode.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear DATDIR bit and set DUALIOEN bit of QSPI_CTL register to enable Dual input mode.
+ */
+#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_DUALIOEN_Msk )
+
+/**
+ * @brief Enable Dual output mode.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Set DATDIR bit and DUALIOEN bit of QSPI_CTL register to enable Dual output mode.
+ */
+#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk) )
+
+/**
+ * @brief Enable Quad input mode.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear DATDIR bit and set QUADIOEN bit of QSPI_CTL register to enable Quad input mode.
+ */
+#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_QUADIOEN_Msk )
+
+/**
+ * @brief Enable Quad output mode.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Set DATDIR bit and QUADIOEN bit of QSPI_CTL register to enable Quad output mode.
+ */
+#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk) )
+
+/**
+ * @brief Trigger RX PDMA function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function.
+ */
+#define QSPI_TRIGGER_RX_PDMA(qspi) ( (qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+ * @brief Trigger TX PDMA function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function.
+ */
+#define QSPI_TRIGGER_TX_PDMA(qspi) ( (qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+ * @brief Disable RX PDMA transfer.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function.
+ */
+#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+ * @brief Disable TX PDMA transfer.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function.
+ */
+#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+ * @brief Get the count of available data in RX FIFO.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return The count of available data in RX FIFO.
+ * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO.
+ */
+#define QSPI_GET_RX_FIFO_COUNT(qspi) ( ((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos )
+
+/**
+ * @brief Get the RX FIFO empty flag.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @retval 0 RX FIFO is not empty.
+ * @retval 1 RX FIFO is empty.
+ * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag.
+ */
+#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk) >> QSPI_STATUS_RXEMPTY_Pos )
+
+/**
+ * @brief Get the TX FIFO empty flag.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @retval 0 TX FIFO is not empty.
+ * @retval 1 TX FIFO is empty.
+ * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag.
+ */
+#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk) >> QSPI_STATUS_TXEMPTY_Pos )
+
+/**
+ * @brief Get the TX FIFO full flag.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @retval 0 TX FIFO is not full.
+ * @retval 1 TX FIFO is full.
+ * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag.
+ */
+#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk) >> QSPI_STATUS_TXFULL_Pos )
+
+/**
+ * @brief Get the datum read from RX register.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return Data in RX register.
+ * @details Read QSPI_RX register to get the received datum.
+ */
+#define QSPI_READ_RX(qspi) ( (qspi)->RX )
+
+/**
+ * @brief Write datum to TX register.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus.
+ * @return None.
+ * @details Write u32TxData to QSPI_TX register.
+ */
+#define QSPI_WRITE_TX(qspi, u32TxData) ( (qspi)->TX = (u32TxData) )
+
+/**
+ * @brief Set QSPIx_SS pin to high state.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set QSPIx_SS pin to high state.
+ */
+#define QSPI_SET_SS_HIGH(qspi) ( (qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk) )
+
+/**
+ * @brief Set QSPIx_SS pin to low state.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set QSPIx_SS pin to low state.
+ */
+#define QSPI_SET_SS_LOW(qspi) ( (qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk )
+
+/**
+ * @brief Enable Byte Reorder function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]).
+ */
+#define QSPI_ENABLE_BYTE_REORDER(qspi) ( (qspi)->CTL |= QSPI_CTL_REORDER_Msk )
+
+/**
+ * @brief Disable Byte Reorder function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function.
+ */
+#define QSPI_DISABLE_BYTE_REORDER(qspi) ( (qspi)->CTL &= ~QSPI_CTL_REORDER_Msk )
+
+/**
+ * @brief Set the length of suspend interval.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
+ * @return None.
+ * @details Set the length of suspend interval according to u32SuspCycle.
+ * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle).
+ */
+#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos) )
+
+/**
+ * @brief Set the QSPI transfer sequence with LSB first.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first.
+ */
+#define QSPI_SET_LSB_FIRST(qspi) ( (qspi)->CTL |= QSPI_CTL_LSB_Msk )
+
+/**
+ * @brief Set the QSPI transfer sequence with MSB first.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first.
+ */
+#define QSPI_SET_MSB_FIRST(qspi) ( (qspi)->CTL &= ~QSPI_CTL_LSB_Msk )
+
+/**
+ * @brief Set the data width of a QSPI transaction.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32Width The bit width of one transaction.
+ * @return None.
+ * @details The data width can be 8 ~ 32 bits.
+ */
+#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << QSPI_CTL_DWIDTH_Pos) )
+
+/**
+ * @brief Get the QSPI busy state.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @retval 0 QSPI controller is not busy.
+ * @retval 1 QSPI controller is busy.
+ * @details This macro will return the busy state of QSPI controller.
+ */
+#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk) >> QSPI_STATUS_BUSY_Pos )
+
+/**
+ * @brief Enable QSPI controller.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Set SPIEN (QSPI_CTL[0]) to enable QSPI controller.
+ */
+#define QSPI_ENABLE(qspi) ( (qspi)->CTL |= QSPI_CTL_SPIEN_Msk )
+
+/**
+ * @brief Disable QSPI controller.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None.
+ * @details Clear SPIEN (QSPI_CTL[0]) to disable QSPI controller.
+ */
+#define QSPI_DISABLE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_SPIEN_Msk )
+
+
+
+/* Function prototype declaration */
+uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
+void QSPI_Close(QSPI_T *qspi);
+void QSPI_ClearRxFIFO(QSPI_T *qspi);
+void QSPI_ClearTxFIFO(QSPI_T *qspi);
+void QSPI_DisableAutoSS(QSPI_T *qspi);
+void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock);
+void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+uint32_t QSPI_GetBusClock(QSPI_T *qspi);
+void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask);
+void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask);
+uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask);
+void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask);
+uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask);
+
+
+/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group QSPI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_H__ */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
--- /dev/null
+/**************************************************************************//**\r
+ * @file rtc.h\r
+ * @version V3.00\r
+ * @brief Real Time Clock(RTC) driver header file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __RTC_H__\r
+#define __RTC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup RTC_Driver RTC Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants\r
+ @{\r
+*/\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* RTC Initial Keyword Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */\r
+#define RTC_WRITE_KEY 0x0000A965UL /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* RTC Time Attribute Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */\r
+#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */\r
+#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */\r
+#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* RTC Tick Period Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */\r
+#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */\r
+#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */\r
+#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */\r
+#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */\r
+#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */\r
+#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */\r
+#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* RTC Day of Week Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */\r
+#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */\r
+#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */\r
+#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */\r
+#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */\r
+#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */\r
+#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* RTC Miscellaneous Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */\r
+\r
+#define RTC_TAMPER0_SELECT (0x1ul << 0) /*!< Select Tamper 0 \hideinitializer */\r
+#define RTC_TAMPER1_SELECT (0x1ul << 1) /*!< Select Tamper 1 \hideinitializer */\r
+#define RTC_TAMPER2_SELECT (0x1ul << 2) /*!< Select Tamper 2 \hideinitializer */\r
+#define RTC_TAMPER3_SELECT (0x1ul << 3) /*!< Select Tamper 3 \hideinitializer */\r
+#define RTC_TAMPER4_SELECT (0x1ul << 4) /*!< Select Tamper 4 \hideinitializer */\r
+#define RTC_TAMPER5_SELECT (0x1ul << 5) /*!< Select Tamper 5 \hideinitializer */\r
+#define MAX_TAMPER_PIN_NUM 6ul /*!< Tamper Pin number \hideinitializer */\r
+\r
+#define RTC_TAMPER_HIGH_LEVEL_DETECT 1ul /*!< Tamper pin detect voltage level is high \hideinitializer */\r
+#define RTC_TAMPER_LOW_LEVEL_DETECT 0ul /*!< Tamper pin detect voltage level is low \hideinitializer */\r
+\r
+#define RTC_TAMPER_DEBOUNCE_ENABLE 1ul /*!< Enable RTC tamper pin de-bounce function \hideinitializer */\r
+#define RTC_TAMPER_DEBOUNCE_DISABLE 0ul /*!< Disable RTC tamper pin de-bounce function \hideinitializer */\r
+\r
+#define RTC_PAIR0_SELECT (0x1ul << 0) /*!< Select Pair 0 \hideinitializer */\r
+#define RTC_PAIR1_SELECT (0x1ul << 1) /*!< Select Pair 1 \hideinitializer */\r
+#define RTC_PAIR2_SELECT (0x1ul << 2) /*!< Select Pair 2 \hideinitializer */\r
+#define MAX_PAIR_NUM 3ul /*!< Pair number \hideinitializer */\r
+\r
+#define RTC_2POW10_CLK (0x0ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles \hideinitializer */\r
+#define RTC_2POW11_CLK (0x1ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles \hideinitializer */\r
+#define RTC_2POW12_CLK (0x2ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles \hideinitializer */\r
+#define RTC_2POW13_CLK (0x3ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles \hideinitializer */\r
+#define RTC_2POW14_CLK (0x4ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles \hideinitializer */\r
+#define RTC_2POW15_CLK (0x5ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles \hideinitializer */\r
+#define RTC_2POW16_CLK (0x6ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles \hideinitializer */\r
+#define RTC_2POW17_CLK (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles \hideinitializer */\r
+\r
+#define REF_RANDOM_PATTERN 0x0ul /*!< The new reference pattern is generated by random number generator when the reference pattern run out \hideinitializer */\r
+#define REF_PREVIOUS_PATTERN 0x1ul /*!< The new reference pattern is repeated previous random value when the reference pattern run out \hideinitializer */\r
+#define REF_SEED 0x3ul /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out \hideinitializer */\r
+\r
+/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs\r
+ @{\r
+*/\r
+/**\r
+ * @details RTC define Time Data Struct\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t u32Year; /*!< Year value */\r
+ uint32_t u32Month; /*!< Month value */\r
+ uint32_t u32Day; /*!< Day value */\r
+ uint32_t u32DayOfWeek; /*!< Day of week value */\r
+ uint32_t u32Hour; /*!< Hour value */\r
+ uint32_t u32Minute; /*!< Minute value */\r
+ uint32_t u32Second; /*!< Second value */\r
+ uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */\r
+ uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */\r
+} S_RTC_TIME_DATA_T;\r
+\r
+/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */\r
+\r
+\r
+/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Indicate is Leap Year or not\r
+ *\r
+ * @param[in] rtc The pointer of RTC module.\r
+ *\r
+ * @retval 0 This year is not a leap year\r
+ * @retval 1 This year is a leap year\r
+ *\r
+ * @details According to current date, return this year is leap year or not.\r
+ * \hideinitializer\r
+ */\r
+#define RTC_IS_LEAP_YEAR(rtc) ((rtc)->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0)\r
+\r
+/**\r
+ * @brief Clear RTC Alarm Interrupt Flag\r
+ *\r
+ * @param[in] rtc The pointer of RTC module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to clear RTC alarm interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define RTC_CLEAR_ALARM_INT_FLAG(rtc) ((rtc)->INTSTS = RTC_INTSTS_ALMIF_Msk)\r
+\r
+/**\r
+ * @brief Clear RTC Tick Interrupt Flag\r
+ *\r
+ * @param[in] rtc The pointer of RTC module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to clear RTC tick interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define RTC_CLEAR_TICK_INT_FLAG(rtc) ((rtc)->INTSTS = RTC_INTSTS_TICKIF_Msk)\r
+\r
+/**\r
+ * @brief Clear RTC Tamper Interrupt Flag\r
+ *\r
+ * @param[in] rtc The pointer of RTC module.\r
+ * @param[in] u32TamperFlag Tamper interrupt flag. It consists of: \n\r
+ * - \ref RTC_INTSTS_TAMP0IF_Msk \n\r
+ * - \ref RTC_INTSTS_TAMP1IF_Msk \n\r
+ * - \ref RTC_INTSTS_TAMP2IF_Msk \n\r
+ * - \ref RTC_INTSTS_TAMP3IF_Msk \n\r
+ * - \ref RTC_INTSTS_TAMP4IF_Msk \n\r
+ * - \ref RTC_INTSTS_TAMP5IF_Msk\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to clear RTC tamper pin interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define RTC_CLEAR_TAMPER_INT_FLAG(rtc, u32TamperFlag) ((rtc)->INTSTS = (u32TamperFlag))\r
+\r
+/**\r
+ * @brief Get RTC Alarm Interrupt Flag\r
+ *\r
+ * @param[in] rtc The pointer of RTC module.\r
+ *\r
+ * @retval 0 RTC alarm interrupt did not occur\r
+ * @retval 1 RTC alarm interrupt occurred\r
+ *\r
+ * @details This macro indicates RTC alarm interrupt occurred or not.\r
+ * \hideinitializer\r
+ */\r
+#define RTC_GET_ALARM_INT_FLAG(rtc) (((rtc)->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)\r
+\r
+/**\r
+ * @brief Get RTC Time Tick Interrupt Flag\r
+ *\r
+ * @param[in] rtc The pointer of RTC module.\r
+ *\r
+ * @retval 0 RTC time tick interrupt did not occur\r
+ * @retval 1 RTC time tick interrupt occurred\r
+ *\r
+ * @details This macro indicates RTC time tick interrupt occurred or not.\r
+ * \hideinitializer\r
+ */\r
+#define RTC_GET_TICK_INT_FLAG(rtc) (((rtc)->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)\r
+\r
+/**\r
+ * @brief Get RTC Tamper Interrupt Flag\r
+ *\r
+ * @param[in] rtc The pointer of RTC module.\r
+ *\r
+ * @retval 0 RTC tamper event interrupt did not occur\r
+ * @retval 1 RTC tamper event interrupt occurred\r
+ *\r
+ * @details This macro indicates RTC tamper event occurred or not.\r
+ * \hideinitializer\r
+ */\r
+#define RTC_GET_TAMPER_INT_FLAG(rtc) (((rtc)->INTSTS & (0x3F00))? 1:0)\r
+\r
+/**\r
+ * @brief Get RTC Tamper Interrupt Status\r
+ *\r
+ * @param[in] rtc The pointer of RTC module.\r
+ *\r
+ * @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated\r
+ * @retval RTC_INTSTS_TAMP1IF_Msk Tamper 1 interrupt flag is generated\r
+ * @retval RTC_INTSTS_TAMP2IF_Msk Tamper 2 interrupt flag is generated\r
+ * @retval RTC_INTSTS_TAMP3IF_Msk Tamper 3 interrupt flag is generated\r
+ * @retval RTC_INTSTS_TAMP4IF_Msk Tamper 4 interrupt flag is generated\r
+ * @retval RTC_INTSTS_TAMP5IF_Msk Tamper 5 interrupt flag is generated\r
+ *\r
+ * @details This macro indicates RTC tamper interrupt status.\r
+ * \hideinitializer\r
+ */\r
+#define RTC_GET_TAMPER_INT_STATUS(rtc) (((rtc)->INTSTS & (0x3F00)))\r
+\r
+/**\r
+ * @brief Enable RTC Tick Wake-up Function\r
+ *\r
+ * @param[in] rtc The pointer of RTC module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable RTC tick interrupt wake-up function.\r
+ * \hideinitializer\r
+ */\r
+#define RTC_ENABLE_TICK_WAKEUP(rtc) ((rtc)->INTEN |= RTC_INTEN_TICKIEN_Msk);\r
+\r
+/**\r
+ * @brief Disable RTC Tick Wake-up Function\r
+ *\r
+ * @param[in] rtc The pointer of RTC module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to disable RTC tick interrupt wake-up function.\r
+ * \hideinitializer\r
+ */\r
+#define RTC_DISABLE_TICK_WAKEUP(rtc) ((rtc)->INTEN &= ~RTC_INTEN_TICKIEN_Msk);\r
+\r
+/**\r
+ * @brief Read Spare Register\r
+ *\r
+ * @param[in] rtc The pointer of RTC module.\r
+ * @param[in] u32RegNum The spare register number, 0~19.\r
+ *\r
+ * @return Spare register content\r
+ *\r
+ * @details Read the specify spare register content.\r
+ * @note The returned value is valid only when RWENF (RTC_RWEN[16]) bit is set. \n\r
+ * \hideinitializer\r
+ */\r
+#define RTC_READ_SPARE_REGISTER(rtc, u32RegNum) ((rtc)->SPR[(u32RegNum)])\r
+\r
+/**\r
+ * @brief Write Spare Register\r
+ *\r
+ * @param[in] rtc The pointer of RTC module.\r
+ * @param[in] u32RegNum The spare register number, 0~19.\r
+ * @param[in] u32RegValue The spare register value.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Write specify data to spare register.\r
+ * @note This macro is effect only when RWENF (RTC_RWEN[16]) bit is set. \n\r
+ * \hideinitializer\r
+ */\r
+#define RTC_WRITE_SPARE_REGISTER(rtc, u32RegNum, u32RegValue) ((rtc)->SPR[(u32RegNum)] = (u32RegValue))\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* static inline functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */\r
+__STATIC_INLINE void RTC_WaitAccessEnable(void);\r
+\r
+/**\r
+ * @brief Wait RTC Access Enable\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable the maximum RTC read/write accessible time.\r
+ */\r
+__STATIC_INLINE void RTC_WaitAccessEnable(void)\r
+{\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ while((RTC_NS->RWEN & RTC_RWEN_RWENF_Msk) == 0x0UL) {}\r
+ }\r
+ else\r
+ {\r
+ while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == 0x0UL) {}\r
+ }\r
+}\r
+\r
+void RTC_Open(S_RTC_TIME_DATA_T *sPt);\r
+void RTC_Close(void);\r
+void RTC_32KCalibration(int32_t i32FrequencyX10000);\r
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);\r
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);\r
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);\r
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);\r
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);\r
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);\r
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);\r
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);\r
+void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk);\r
+void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk);\r
+uint32_t RTC_GetDayOfWeek(void);\r
+void RTC_SetTickPeriod(uint32_t u32TickSelection);\r
+void RTC_EnableInt(uint32_t u32IntFlagMask);\r
+void RTC_DisableInt(uint32_t u32IntFlagMask);\r
+void RTC_EnableSpareAccess(void);\r
+void RTC_DisableSpareRegister(void);\r
+void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn);\r
+void RTC_StaticTamperDisable(uint32_t u32TamperSelect);\r
+void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source);\r
+void RTC_DynamicTamperDisable(uint32_t u32PairSel);\r
+void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed);\r
+\r
+/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group RTC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __RTC_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file sc.h\r
+ * @version V3.00\r
+ * @brief Smartcard(SC) driver header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __SC_H__\r
+#define __SC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SC_Driver SC Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants\r
+ @{\r
+*/\r
+#define SC_INTERFACE_NUM (3ul) /*!< Smartcard interface numbers \hideinitializer */\r
+#define SC_PIN_STATE_HIGH (1ul) /*!< Smartcard pin status high \hideinitializer */\r
+#define SC_PIN_STATE_LOW (0ul) /*!< Smartcard pin status low \hideinitializer */\r
+#define SC_PIN_STATE_IGNORE (0xFFFFFFFFul) /*!< Ignore pin status \hideinitializer */\r
+#define SC_CLK_ON (1ul) /*!< Smartcard clock on \hideinitializer */\r
+#define SC_CLK_OFF (0ul) /*!< Smartcard clock off \hideinitializer */\r
+\r
+#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 0, down count \hideinitializer */\r
+#define SC_TMR_MODE_1 (1ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 1, down count, start after detect start bit \hideinitializer */\r
+#define SC_TMR_MODE_2 (2ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 2, down count, start after receive start bit \hideinitializer */\r
+#define SC_TMR_MODE_3 (3ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 3, down count, use for activation, only timer 0 support this mode \hideinitializer */\r
+#define SC_TMR_MODE_4 (4ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 4, down count with reload after timeout \hideinitializer */\r
+#define SC_TMR_MODE_5 (5ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 5, down count, start after detect start bit, reload after timeout \hideinitializer */\r
+#define SC_TMR_MODE_6 (6ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 6, down count, start after receive start bit, reload after timeout \hideinitializer */\r
+#define SC_TMR_MODE_7 (7ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 7, down count, start and reload after detect start bit \hideinitializer */\r
+#define SC_TMR_MODE_8 (8ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 8, up count \hideinitializer */\r
+#define SC_TMR_MODE_F (0xF << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 15, down count, reload after detect start bit \hideinitializer */\r
+\r
+/*@}*/ /* end of group SC_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief This macro enable smartcard interrupt\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32Mask Interrupt mask to be enabled. A combination of\r
+ * - \ref SC_INTEN_ACERRIEN_Msk\r
+ * - \ref SC_INTEN_RXTOIEN_Msk\r
+ * - \ref SC_INTEN_INITIEN_Msk\r
+ * - \ref SC_INTEN_CDIEN_Msk\r
+ * - \ref SC_INTEN_BGTIEN_Msk\r
+ * - \ref SC_INTEN_TMR2IEN_Msk\r
+ * - \ref SC_INTEN_TMR1IEN_Msk\r
+ * - \ref SC_INTEN_TMR0IEN_Msk\r
+ * - \ref SC_INTEN_TERRIEN_Msk\r
+ * - \ref SC_INTEN_TBEIEN_Msk\r
+ * - \ref SC_INTEN_RDAIEN_Msk\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The macro is used to enable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,\r
+ * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,\r
+ * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.\r
+ * \hideinitializer\r
+ */\r
+#define SC_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))\r
+\r
+/**\r
+ * @brief This macro disable smartcard interrupt\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32Mask Interrupt mask to be disabled. A combination of\r
+ * - \ref SC_INTEN_ACERRIEN_Msk\r
+ * - \ref SC_INTEN_RXTOIEN_Msk\r
+ * - \ref SC_INTEN_INITIEN_Msk\r
+ * - \ref SC_INTEN_CDIEN_Msk\r
+ * - \ref SC_INTEN_BGTIEN_Msk\r
+ * - \ref SC_INTEN_TMR2IEN_Msk\r
+ * - \ref SC_INTEN_TMR1IEN_Msk\r
+ * - \ref SC_INTEN_TMR0IEN_Msk\r
+ * - \ref SC_INTEN_TERRIEN_Msk\r
+ * - \ref SC_INTEN_TBEIEN_Msk\r
+ * - \ref SC_INTEN_RDAIEN_Msk\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,\r
+ * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,\r
+ * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.\r
+ * \hideinitializer\r
+ */\r
+#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))\r
+\r
+/**\r
+ * @brief This macro set VCC pin state of smartcard interface\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details User can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11]) to decide SC_PWR pin is in high or low level.\r
+ * \hideinitializer\r
+ */\r
+#define SC_SET_VCC_PIN(sc, u32State) \\r
+ do {\\r
+ while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\\r
+ if(u32State)\\r
+ (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\\r
+ else\\r
+ (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\\r
+ }while(0)\r
+\r
+\r
+/**\r
+ * @brief This macro turns CLK output on or off\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details User can set CLKKEEP (SC_PINCTL[6]) to decide SC_CLK pin always keeps free running or not.\r
+ * \hideinitializer\r
+ */\r
+#define SC_SET_CLK_PIN(sc, u32OnOff)\\r
+ do {\\r
+ while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\\r
+ if(u32OnOff)\\r
+ (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\\r
+ else\\r
+ (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\\r
+ }while(0)\r
+\r
+/**\r
+ * @brief This macro set I/O pin state of smartcard interface\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details User can set SCDATA (SC_PINCTL[9]) to decide SC_DATA pin to high or low.\r
+ * \hideinitializer\r
+ */\r
+#define SC_SET_IO_PIN(sc, u32State)\\r
+ do {\\r
+ while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\\r
+ if(u32State)\\r
+ (sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\\r
+ else\\r
+ (sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\\r
+ }while(0)\r
+\r
+/**\r
+ * @brief This macro set RST pin state of smartcard interface\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details User can set SCRST (SC_PINCTL[1]) to decide SC_RST pin to high or low.\r
+ * \hideinitializer\r
+ */\r
+#define SC_SET_RST_PIN(sc, u32State)\\r
+ do {\\r
+ while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\\r
+ if(u32State)\\r
+ (sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\\r
+ else\\r
+ (sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\\r
+ }while(0)\r
+\r
+/**\r
+ * @brief This macro read one byte from smartcard module receive FIFO\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return One byte read from receive FIFO\r
+ *\r
+ * @details By reading DAT register, the SC will return an 8-bit received data.\r
+ * \hideinitializer\r
+ */\r
+#define SC_READ(sc) ((char)((sc)->DAT))\r
+\r
+/**\r
+ * @brief This macro write one byte to smartcard module transmit FIFO\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u8Data Data to write to transmit FIFO.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details By writing data to DAT register, the SC will send out an 8-bit data.\r
+ * \hideinitializer\r
+ */\r
+#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))\r
+\r
+/**\r
+ * @brief This macro set smartcard stop bit length\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32Len Stop bit length, ether 1 or 2.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.\r
+ * \hideinitializer\r
+ */\r
+#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | (((u32Len) == 1)? SC_CTL_NSB_Msk : 0))\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* static inline functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */\r
+__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count);\r
+__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count);\r
+\r
+\r
+/**\r
+ * @brief Enable/Disable Tx error retry, and set Tx error retry count\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable/disable transmitter retry function when parity error has occurred, and set error retry count.\r
+ */\r
+__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count)\r
+{\r
+ while((sc)->CTL & SC_CTL_SYNC_Msk) {}\r
+\r
+ /* Retry count must set while enable bit disabled, so disable it first */\r
+ (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk);\r
+\r
+ if((u32Count) != 0UL)\r
+ {\r
+ while((sc)->CTL & SC_CTL_SYNC_Msk) {}\r
+ (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable/Disable Rx error retry, and set Rx error retry count\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable/disable receiver retry function when parity error has occurred, and set error retry count.\r
+ */\r
+__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count)\r
+{\r
+ while((sc)->CTL & SC_CTL_SYNC_Msk) {}\r
+\r
+ /* Retry count must set while enable bit disabled, so disable it first */\r
+ (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk);\r
+\r
+ if((u32Count) != 0UL)\r
+ {\r
+ while((sc)->CTL & SC_CTL_SYNC_Msk) {}\r
+ (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk;\r
+ }\r
+}\r
+\r
+\r
+uint32_t SC_IsCardInserted(SC_T *sc);\r
+void SC_ClearFIFO(SC_T *sc);\r
+void SC_Close(SC_T *sc);\r
+void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR);\r
+void SC_ResetReader(SC_T *sc);\r
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT);\r
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT);\r
+void SC_StopAllTimer(SC_T *sc);\r
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);\r
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum);\r
+uint32_t SC_GetInterfaceClock(SC_T *sc);\r
+\r
+\r
+/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group SC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SC_H__ */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file scu.h\r
+ * @version V1.00\r
+ * @brief Secure Configuration Unit Driver Header\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __SCU_H__\r
+#define __SCU_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SCU_Driver SCU Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SCU_EXPORTED_CONSTANTS SCU Exported Constants\r
+ @{\r
+*/\r
+\r
+\r
+\r
+\r
+/**\r
+ * @details Non-secure Attribution Definition.\r
+ */\r
+typedef enum NSATTR\r
+{\r
+ /****** PNNSET0 **********************************************************************************/\r
+ USBH_Attr = 9,\r
+ SDH0_Attr = 13,\r
+ EBI_Attr = 16,\r
+ PDMA1_Attr = 24,\r
+\r
+ /****** PNNSET1 **********************************************************************************/\r
+ CRC_Attr = 32 + 17,\r
+ CRPT_Attr = 32 + 18,\r
+\r
+ /****** PNNSET2 **********************************************************************************/\r
+ RTC_Attr = 64 + 1,\r
+ EADC_Attr = 64 + 3,\r
+ ACMP01_Attr = 64 + 5,\r
+ DAC_Attr = 64 + 7,\r
+ I2S0_Attr = 64 + 8,\r
+ OTG_Attr = 64 + 13,\r
+ TMR23_Attr = 64 + 17,\r
+ PWM0_Attr = 64 + 24,\r
+ PWM1_Attr = 64 + 25,\r
+ BPWM0_Attr = 64 + 26,\r
+ BPWM1_Attr = 64 + 27,\r
+ /****** PNNSET3 **********************************************************************************/\r
+ QSPI0_Attr = 96 + 0,\r
+ SPI0_Attr = 96 + 1,\r
+ SPI1_Attr = 96 + 2,\r
+ SPI2_Attr = 96 + 3,\r
+ SPI3_Attr = 96 + 4,\r
+ UART0_Attr = 96 + 16,\r
+ UART1_Attr = 96 + 17,\r
+ UART2_Attr = 96 + 18,\r
+ UART3_Attr = 96 + 19,\r
+ UART4_Attr = 96 + 20,\r
+ UART5_Attr = 96 + 21,\r
+ /****** PNNSET4 **********************************************************************************/\r
+ I2C0_Attr = 128 + 0,\r
+ I2C1_Attr = 128 + 1,\r
+ I2C2_Attr = 128 + 2,\r
+ SC0_Attr = 128 + 16,\r
+ SC1_Attr = 128 + 17,\r
+ SC2_Attr = 128 + 18,\r
+\r
+\r
+ /****** PNNSET5 **********************************************************************************/\r
+ CAN0_Attr = 160 + 0,\r
+ QEI0_Attr = 160 + 16,\r
+ QEI1_Attr = 160 + 17,\r
+ ECAP0_Attr = 160 + 20,\r
+ ECAP1_Attr = 160 + 21,\r
+\r
+ /****** PNNSET6 **********************************************************************************/\r
+ USBD_Attr = 192 + 0,\r
+ USCI0_Attr = 192 + 16,\r
+ USCI1_Attr = 192 + 17\r
+\r
+\r
+} NSATTR_T;\r
+\r
+\r
+/*@}*/ /* end of group SCU_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Set peripheral non-secure attribution\r
+ *\r
+ * @param[in] nsattr The secure/non-secure attribution of specified module.\r
+ The possible value could be refer to \ref NSATTR.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to set a peripheral to be non-secure peripheral.\r
+ *\r
+ */\r
+#define SCU_SET_PNSSET(nsattr) { SCU->PNSSET[(nsattr)/32] |= (1 << ((nsattr) & 0x1ful)); }\r
+\r
+/**\r
+ * @brief Get peripheral secure/non-secure attribution\r
+ *\r
+ * @param[in] nsattr The secure/non-secure attribution of specified module.\r
+ The possible value could be refer to \ref NSATTR.\r
+ *\r
+ * @return The secure/non-secure attribution of specified peripheral.\r
+ * @retval 0 The peripheral is secure\r
+ * @retval 1 The peripheral is non-secure\r
+ *\r
+ * @details This macro gets the peripheral secure/non-secure attribution.\r
+ */\r
+#define SCU_GET_PNSSET(nsattr) ((SCU->PNSSET[(nsattr)/32] >> ((nsattr) & 0x1ful)) & 1ul)\r
+\r
+\r
+/**\r
+ * @brief Set secure/non-secure attribution of specified GPIO ports\r
+ *\r
+ * @param[in] mask The port mask of each GPIO port\r
+ * - \ref SCU_IONSSET_PA_Msk\r
+ * - \ref SCU_IONSSET_PB_Msk\r
+ * - \ref SCU_IONSSET_PC_Msk\r
+ * - \ref SCU_IONSSET_PD_Msk\r
+ * - \ref SCU_IONSSET_PE_Msk\r
+ * - \ref SCU_IONSSET_PF_Msk\r
+ * - \ref SCU_IONSSET_PG_Msk\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro gets the peripheral secure/non-secure attribution.\r
+ */\r
+#define SCU_SET_IONSSET(mask) (SCU->IONSSET |= (mask))\r
+\r
+\r
+/**\r
+ * @brief Get secure/non-secure attribution of specified GPIO ports\r
+ *\r
+ * @param[in] port The port mask of each GPIO port\r
+ * - \ref SCU_IONSSET_PA_Msk\r
+ * - \ref SCU_IONSSET_PB_Msk\r
+ * - \ref SCU_IONSSET_PC_Msk\r
+ * - \ref SCU_IONSSET_PD_Msk\r
+ * - \ref SCU_IONSSET_PE_Msk\r
+ * - \ref SCU_IONSSET_PF_Msk\r
+ * - \ref SCU_IONSSET_PG_Msk\r
+ *\r
+ * @return The secure/non-secure attribution of specified peripheral.\r
+ * @retval 0 The specified IO port is secure\r
+ * @retval 1 The specified IO port is non-secure\r
+ *\r
+ * @details This macro gets GPIO port secure/non-secure attribution.\r
+ */\r
+#define SCU_GET_IONSSET(port) ((SCU->IONSSET&(port))?1:0)\r
+\r
+\r
+/**\r
+ * @brief Enable sercure violation interrupts\r
+ *\r
+ * @param[in] mask The mask of each secure violation interrupt source\r
+ * - \ref SCU_SVIOIEN_APB0IEN_Msk\r
+ * - \ref SCU_SVIOIEN_APB1IEN_Msk\r
+ * - \ref SCU_SVIOIEN_GPIOIEN_Msk\r
+ * - \ref SCU_SVIOIEN_EBIIEN_Msk\r
+ * - \ref SCU_SVIOIEN_USBHIEN_Msk\r
+ * - \ref SCU_SVIOIEN_CRCIEN_Msk\r
+ * - \ref SCU_SVIOIEN_SDH0IEN_Msk\r
+ * - \ref SCU_SVIOIEN_PDMA0IEN_Msk\r
+ * - \ref SCU_SVIOIEN_PDMA1IEN_Msk\r
+ * - \ref SCU_SVIOIEN_SRAM0IEN_Msk\r
+ * - \ref SCU_SVIOIEN_SRAM1IEN_Msk\r
+ * - \ref SCU_SVIOIEN_FMCIEN_Msk\r
+ * - \ref SCU_SVIOIEN_FLASHIEN_Msk\r
+ * - \ref SCU_SVIOIEN_SCUIEN_Msk\r
+ * - \ref SCU_SVIOIEN_SYSIEN_Msk\r
+ * - \ref SCU_SVIOIEN_CRPTIEN_Msk\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable secure violation interrupt of SCU.\r
+ * The secure violation interrupt could be used to detect attack of secure elements.\r
+ */\r
+#define SCU_ENABLE_INT(mask) (SCU->SVIOIEN |= (mask))\r
+\r
+\r
+/**\r
+ * @brief Disable sercure violation interrupts\r
+ *\r
+ * @param[in] mask The mask of each secure violation interrupt source\r
+ * - \ref SCU_SVIOIEN_APB0IEN_Msk\r
+ * - \ref SCU_SVIOIEN_APB1IEN_Msk\r
+ * - \ref SCU_SVIOIEN_GPIOIEN_Msk\r
+ * - \ref SCU_SVIOIEN_EBIIEN_Msk\r
+ * - \ref SCU_SVIOIEN_USBHIEN_Msk\r
+ * - \ref SCU_SVIOIEN_CRCIEN_Msk\r
+ * - \ref SCU_SVIOIEN_SDH0IEN_Msk\r
+ * - \ref SCU_SVIOIEN_PDMA0IEN_Msk\r
+ * - \ref SCU_SVIOIEN_PDMA1IEN_Msk\r
+ * - \ref SCU_SVIOIEN_SRAM0IEN_Msk\r
+ * - \ref SCU_SVIOIEN_SRAM1IEN_Msk\r
+ * - \ref SCU_SVIOIEN_FMCIEN_Msk\r
+ * - \ref SCU_SVIOIEN_FLASHIEN_Msk\r
+ * - \ref SCU_SVIOIEN_SCUIEN_Msk\r
+ * - \ref SCU_SVIOIEN_SYSIEN_Msk\r
+ * - \ref SCU_SVIOIEN_CRPTIEN_Msk\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to disable secure violation interrupt of SCU.\r
+ *\r
+ */\r
+#define SCU_DISABLE_INT(mask) (SCU->SVIOIEN &= (~(mask)))\r
+\r
+\r
+/**\r
+ * @brief Get secure violation interrupt status\r
+ *\r
+ * @param mask The interrupt flag mask bit\r
+ *\r
+ * @return The value of SCU_SVINTSTS register\r
+ *\r
+ * @details Return interrupt flag of SCU_SVINTSTS register.\r
+ *\r
+ */\r
+#define SCU_GET_INT_FLAG(mask) (SCU->SVINTSTS&(mask))\r
+\r
+/**\r
+ * @brief Clear secure violation interrupt flag\r
+ *\r
+ * @param[in] flag The combination of the specified interrupt flags.\r
+ * Each bit corresponds to a interrupt source.\r
+ * This parameter decides which interrupt flags will be cleared.\r
+ * - \ref SCU_SVINTSTS_APB0IF_Msk\r
+ * - \ref SCU_SVINTSTS_APB1IF_Msk\r
+ * - \ref SCU_SVINTSTS_GPIOIF_Msk\r
+ * - \ref SCU_SVINTSTS_EBIIF_Msk\r
+ * - \ref SCU_SVINTSTS_USBHIF_Msk\r
+ * - \ref SCU_SVINTSTS_CRCIF_Msk\r
+ * - \ref SCU_SVINTSTS_SDH0IF_Msk\r
+ * - \ref SCU_SVINTSTS_PDMA0IF_Msk\r
+ * - \ref SCU_SVINTSTS_PDMA1IF_Msk\r
+ * - \ref SCU_SVINTSTS_SRAM0IF_Msk\r
+ * - \ref SCU_SVINTSTS_SRAM1IF_Msk\r
+ * - \ref SCU_SVINTSTS_FMCIF_Msk\r
+ * - \ref SCU_SVINTSTS_FLASHIF_Msk\r
+ * - \ref SCU_SVINTSTS_SCUIF_Msk\r
+ * - \ref SCU_SVINTSTS_SYSIF_Msk\r
+ * - \ref SCU_SVINTSTS_CRPTIF_Msk\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Clear SCU related interrupt flags specified by flag parameter.\r
+ *\r
+ */\r
+#define SCU_CLR_INT_FLAG(flag) (SCU->SVINTSTS = (flag))\r
+\r
+\r
+\r
+/**\r
+ * @brief Control the behavior of non-secure monitor when CPU is in idle state.\r
+ *\r
+ * @param[in] opt Option for behavior control of non-secure monitor when CPU in idle.\r
+ * - true The counter keeps counting when CPU is in idle.\r
+ - false The counter will stop when CPU is in idle.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To control non-secure monitor counter when CPU is in idle.\r
+ *\r
+ */\r
+#define SCU_NSM_IDLE_ON(opt) ((opt)?(SCU->NSMCTL |= SCU_NSMCTL_IDLEON_Msk):(SCU->NSMCTL &= ~SCU_NSMCTL_IDLEON_Msk))\r
+\r
+/**\r
+ * @brief Control the behavior of non-secure monitor when CPU is in debug state.\r
+ *\r
+ * @param[in] opt Option for behavior control of non-secure monitor when CPU in debug.\r
+ * - true The counter keeps counting when CPU is in debug.\r
+ - false The counter will stop when CPU is in debug.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To control non-secure monitor counter when CPU is in debug.\r
+ *\r
+ */\r
+#define SCU_NSM_DBG_ON(opt) ((opt)?(SCU->NSMCTL |= SCU_NSMCTL_DBGON_Msk):(SCU->NSMCTL &= ~SCU_NSMCTL_DBGON_Msk))\r
+\r
+\r
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */\r
+__STATIC_INLINE void SCU_NSMConfig(uint32_t u32Ticks, uint32_t u32Prescale);\r
+__STATIC_INLINE void SCU_TimerConfig(uint32_t u32Ticks, uint32_t u32Prescale);\r
+\r
+\r
+/**\r
+ * @brief Config non-secure monitor to detect timeout in non-secure state.\r
+ *\r
+ * @param[in] u32Ticks A specified period for timeout in non-secure state\r
+ * @param[in] u32Prescale A pre-scale divider to non-secure monitor clock\r
+\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to configure non-secure monitor. If the CPU state stay in non-secure state for\r
+ * a specified period. The non-secure monitor will timeout and assert an interrupt. Otherwise, the\r
+ * non-secure monitor will auto clear whenever returning to secure state. This could be used to avoid\r
+ * CPU state in non-secure state too long time for security purpose. User must enable SCU_IRQn if interrupt\r
+ * is necessary.\r
+ *\r
+ */\r
+__STATIC_INLINE void SCU_NSMConfig(uint32_t u32Ticks, uint32_t u32Prescale)\r
+{\r
+\r
+ SCU->NSMLOAD = u32Ticks;\r
+ SCU->NSMVAL = 0ul;\r
+ SCU->NSMCTL = SCU_NSMCTL_AUTORLD_Msk | SCU_NSMCTL_NSMIEN_Msk | (u32Prescale & 0xfful);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Config non-secure monitor to be a timer.\r
+ *\r
+ * @param[in] u32Ticks A specified period for timer interrupt.\r
+ * @param[in] u32Prescale A pre-scale divider to timer clock source.\r
+\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to configure non-secure monitor as a timer. In other words, the timer counter\r
+ * keeps counting even CPU is in secure state.\r
+ *\r
+ */\r
+__STATIC_INLINE void SCU_TimerConfig(uint32_t u32Ticks, uint32_t u32Prescale)\r
+{\r
+\r
+ SCU->NSMLOAD = u32Ticks;\r
+ SCU->NSMVAL = 0ul;\r
+ SCU->NSMCTL = SCU_NSMCTL_AUTORLD_Msk | SCU_NSMCTL_NSMIEN_Msk | SCU_NSMCTL_TMRMOD_Msk | (u32Prescale & 0xfful);\r
+}\r
+\r
+\r
+\r
+\r
+/*@}*/ /* end of group SCU_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group SCU_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SCU_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file scuart.h\r
+ * @version V3.00\r
+ * @brief Smartcard UART mode (SCUART) driver header file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __SCUART_H__\r
+#define __SCUART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SCUART_Driver SCUART Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants\r
+ @{\r
+*/\r
+#define SCUART_CHAR_LEN_5 (0x3UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */\r
+#define SCUART_CHAR_LEN_6 (0x2UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */\r
+#define SCUART_CHAR_LEN_7 (0x1UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */\r
+#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */\r
+\r
+#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */\r
+#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */\r
+#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */\r
+\r
+#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */\r
+#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */\r
+\r
+/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions\r
+ @{\r
+*/\r
+\r
+/* TX Macros */\r
+/**\r
+ * @brief Write Data to Tx data register\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u8Data Data byte to transmit.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details By writing data to DAT register, the SC will send out an 8-bit data.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))\r
+\r
+/**\r
+ * @brief Get Tx FIFO empty flag status from register\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Transmit FIFO empty status\r
+ * @retval 0 Transmit FIFO is not empty\r
+ * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty\r
+ *\r
+ * @details When the last byte of Tx buffer has been transferred to Transmitter Shift Register, hardware sets TXEMPTY (SC_STATUS[9]) high.\r
+ * It will be cleared when writing data into DAT (SC_DAT[7:0]).\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)\r
+\r
+/**\r
+ * @brief Get Tx FIFO full flag status from register\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Transmit FIFO full status\r
+ * @retval 0 Transmit FIFO is not full\r
+ * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full\r
+ *\r
+ * @details TXFULL (SC_STATUS[10]) is set when Tx buffer counts equals to 4, otherwise is cleared by hardware.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk)\r
+\r
+/**\r
+ * @brief Wait specified smartcard port transmission complete\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details TXACT (SC_STATUS[31]) is cleared automatically when Tx transfer is finished or the last byte transmission has completed.\r
+ *\r
+ * @note This macro blocks until transmit complete.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk)\r
+\r
+/**\r
+ * @brief Check specified smartcard port transmit FIFO is full or not\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Transmit FIFO full status\r
+ * @retval 0 Transmit FIFO is not full\r
+ * @retval 1 Transmit FIFO is full\r
+ *\r
+ * @details TXFULL (SC_STATUS[10]) indicates Tx buffer full or not.\r
+ * This bit is set when Tx buffer counts equals to 4, otherwise is cleared by hardware.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_IS_TX_FULL(sc) (((sc)->STATUS & SC_STATUS_TXFULL_Msk)? 1 : 0)\r
+\r
+/**\r
+ * @brief Check specified smartcard port transmission is over\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Transmit complete status\r
+ * @retval 0 Transmit is not complete\r
+ * @retval 1 Transmit complete\r
+ *\r
+ * @details TXACT (SC_STATUS[31]) indicates Tx Transmit is complete or not.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_IS_TX_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 0 : 1)\r
+\r
+/**\r
+ * @brief Check specified smartcard port transmit FIFO empty status\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Transmit FIFO empty status\r
+ * @retval 0 Transmit FIFO is not empty\r
+ * @retval 1 Transmit FIFO is empty\r
+ *\r
+ * @details TXEMPTY (SC_STATUS[9]) is set by hardware when the last byte of Tx buffer has been transferred to Transmitter Shift Register.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_IS_TX_FIFO_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)? 1 : 0)\r
+\r
+/**\r
+ * @brief Check specified Smartcard port Transmission Status\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @retval 0 Transmit is completed\r
+ * @retval 1 Transmit is active\r
+ *\r
+ * @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_IS_TX_ACTIVE(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0)\r
+\r
+\r
+/* RX Macros */\r
+/**\r
+ * @brief Read Rx data register\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return The oldest data byte in RX FIFO\r
+ *\r
+ * @details By reading DAT register, the SC will return an 8-bit received data.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_READ(sc) ((sc)->DAT)\r
+\r
+/**\r
+ * @brief Get Rx FIFO empty flag status from register\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Receive FIFO empty status\r
+ * @retval 0 Receive FIFO is not empty\r
+ * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty\r
+ *\r
+ * @details When the last byte of Rx buffer has been read by CPU, hardware sets RXEMPTY (SC_STATUS[1]) high.\r
+ * It will be cleared when SC receives any new data.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk)\r
+\r
+/**\r
+ * @brief Get Rx FIFO full flag status from register\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Receive FIFO full status\r
+ * @retval 0 Receive FIFO is not full\r
+ * @retval SC_STATUS_TXFULL_Msk Receive FIFO is full\r
+ *\r
+ * @details RXFULL (SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk)\r
+\r
+/**\r
+ * @brief Check if receive data number in FIFO reach FIFO trigger level or not\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Receive FIFO data status\r
+ * @retval 0 The number of bytes in receive FIFO is less than trigger level\r
+ * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level\r
+ *\r
+ * @details RDAIF (SC_INTSTS[0]) is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\r
+ *\r
+ * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_IS_RX_READY(sc) (((sc)->INTSTS & SC_INTSTS_RDAIF_Msk)? 1 : 0)\r
+\r
+/**\r
+ * @brief Check specified smartcard port receive FIFO is full or not\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Receive FIFO full status\r
+ * @retval 0 Receive FIFO is not full\r
+ * @retval 1 Receive FIFO is full\r
+ *\r
+ * @details RXFULLF( SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_IS_RX_FULL(sc) (((sc)->STATUS & SC_STATUS_RXFULL_Msk)? 1 : 0)\r
+\r
+\r
+/* Interrupt Macros */\r
+/**\r
+ * @brief Enable specified interrupts\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32Mask Interrupt masks to enable, a combination of following bits,\r
+ * - \ref SC_INTEN_RXTOIEN_Msk\r
+ * - \ref SC_INTEN_TERRIEN_Msk\r
+ * - \ref SC_INTEN_TBEIEN_Msk\r
+ * - \ref SC_INTEN_RDAIEN_Msk\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The macro is used to enable receiver buffer time-out interrupt, transfer error interrupt,\r
+ * transmit buffer empty interrupt or receive data reach trigger level interrupt.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))\r
+\r
+/**\r
+ * @brief Disable specified interrupts\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32Mask Interrupt masks to disable, a combination of following bits,\r
+ * - \ref SC_INTEN_RXTOIEN_Msk\r
+ * - \ref SC_INTEN_TERRIEN_Msk\r
+ * - \ref SC_INTEN_TBEIEN_Msk\r
+ * - \ref SC_INTEN_RDAIEN_Msk\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The macro is used to disable receiver buffer time-out interrupt, transfer error interrupt,\r
+ * transmit buffer empty interrupt or receive data reach trigger level interrupt.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))\r
+\r
+/**\r
+ * @brief Get specified interrupt flag/status\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32Type Interrupt flag/status to check, could be one of following value\r
+ * - \ref SC_INTSTS_RXTOIF_Msk\r
+ * - \ref SC_INTSTS_TERRIF_Msk\r
+ * - \ref SC_INTSTS_TBEIF_Msk\r
+ * - \ref SC_INTSTS_RDAIF_Msk\r
+ *\r
+ * @return The status of specified interrupt\r
+ * @retval 0 Specified interrupt does not happened\r
+ * @retval 1 Specified interrupt happened\r
+ *\r
+ * @details The macro is used to get receiver buffer time-out interrupt status, transfer error interrupt status,\r
+ * transmit buffer empty interrupt status or receive data reach interrupt status.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_GET_INT_FLAG(sc, u32Type) (((sc)->INTSTS & (u32Type))? 1 : 0)\r
+\r
+/**\r
+ * @brief Clear specified interrupt flag/status\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32Type Interrupt flag/status to clear, only \ref SC_INTSTS_TERRIF_Msk valid for this macro.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The macro is used to clear transfer error interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type))\r
+\r
+/**\r
+ * @brief Get receive error flag/status\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Current receive error status, could one of following errors:\r
+ * @retval SC_STATUS_PEF_Msk Parity error\r
+ * @retval SC_STATUS_FEF_Msk Frame error\r
+ * @retval SC_STATUS_BEF_Msk Break error\r
+ *\r
+ * @details The macro is used to get receiver parity error status, frame error status or break error status.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))\r
+\r
+/**\r
+ * @brief Clear specified receive error flag/status\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32Mask Receive error flag/status to clear, combination following values\r
+ * - \ref SC_STATUS_PEF_Msk\r
+ * - \ref SC_STATUS_FEF_Msk\r
+ * - \ref SC_STATUS_BEF_Msk\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The macro is used to clear receiver parity error flag, frame error flag or break error flag.\r
+ * \hideinitializer\r
+ */\r
+#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask))\r
+\r
+void SCUART_Close(SC_T* sc);\r
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate);\r
+uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);\r
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);\r
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);\r
+void SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);\r
+\r
+/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group SCUART_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SCUART_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file sdh.h\r
+ * @version V1.00\r
+ * @brief M2351 SDH driver header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#ifndef __SDH_H__\r
+#define __SDH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+#include <stdio.h>\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SDH_Driver SDH Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants\r
+ @{\r
+*/\r
+\r
+#define SDH_ERR_ID 0xFFFF0100UL /*!< SDH error ID \hideinitializer */\r
+\r
+#define SDH_TIMEOUT (SDH_ERR_ID|0x01UL) /*!< Timeout \hideinitializer */\r
+#define SDH_NO_MEMORY (SDH_ERR_ID|0x02UL) /*!< OOM \hideinitializer */\r
+\r
+/* -- function return value */\r
+#define Successful 0U /*!< Success \hideinitializer */\r
+#define Fail 1U /*!< Failed \hideinitializer */\r
+\r
+/* --- define type of SD card or MMC */\r
+#define SDH_TYPE_UNKNOWN 0UL /*!< Unknown card type \hideinitializer */\r
+#define SDH_TYPE_SD_HIGH 1UL /*!< SDHC card \hideinitializer */\r
+#define SDH_TYPE_SD_LOW 2UL /*!< SD card \hideinitializer */\r
+#define SDH_TYPE_MMC 3UL /*!< MMC card \hideinitializer */\r
+#define SDH_TYPE_EMMC 4UL /*!< eMMC card \hideinitializer */\r
+\r
+/* SD error */\r
+#define SDH_NO_SD_CARD (SDH_ERR_ID|0x10UL) /*!< Card removed \hideinitializer */\r
+#define SDH_ERR_DEVICE (SDH_ERR_ID|0x11UL) /*!< Device error \hideinitializer */\r
+#define SDH_INIT_TIMEOUT (SDH_ERR_ID|0x12UL) /*!< Card init timeout \hideinitializer */\r
+#define SDH_SELECT_ERROR (SDH_ERR_ID|0x13UL) /*!< Card select error \hideinitializer */\r
+#define SDH_WRITE_PROTECT (SDH_ERR_ID|0x14UL) /*!< Card write protect \hideinitializer */\r
+#define SDH_INIT_ERROR (SDH_ERR_ID|0x15UL) /*!< Card init error \hideinitializer */\r
+#define SDH_CRC7_ERROR (SDH_ERR_ID|0x16UL) /*!< CRC 7 error \hideinitializer */\r
+#define SDH_CRC16_ERROR (SDH_ERR_ID|0x17UL) /*!< CRC 16 error \hideinitializer */\r
+#define SDH_CRC_ERROR (SDH_ERR_ID|0x18UL) /*!< CRC error \hideinitializer */\r
+#define SDH_CMD8_ERROR (SDH_ERR_ID|0x19UL) /*!< Command 8 error \hideinitializer */\r
+\r
+#define MMC_FREQ 20000UL /*!< output 20MHz to MMC \hideinitializer */\r
+#define SD_FREQ 25000UL /*!< output 25MHz to SD \hideinitializer */\r
+#define SDHC_FREQ 50000UL /*!< output 50MHz to SDH \hideinitializer */\r
+\r
+#define CardDetect_From_GPIO (1UL << 8) /*!< Card detection pin is GPIO \hideinitializer */\r
+#define CardDetect_From_DAT3 (1UL << 9) /*!< Card detection pin is DAT3 \hideinitializer */\r
+\r
+/*@}*/ /* end of group SDH_EXPORTED_CONSTANTS */\r
+\r
+/** @addtogroup SDH_EXPORTED_TYPEDEF SDH Exported Type Defines\r
+ @{\r
+*/\r
+typedef struct SDH_info_t\r
+{\r
+ unsigned int CardType; /*!< SDHC, SD, or MMC */\r
+ unsigned int RCA; /*!< Relative card address */\r
+ unsigned char IsCardInsert; /*!< Card insert state */\r
+ unsigned int totalSectorN; /*!< Total sector number */\r
+ unsigned int diskSize; /*!< Disk size in K bytes */\r
+ int sectorSize; /*!< Sector size in bytes */\r
+} SDH_INFO_T; /*!< Structure holds SD card info */\r
+\r
+/*@}*/ /* end of group SDH_EXPORTED_TYPEDEF */\r
+\r
+/** @cond HIDDEN_SYMBOLS */\r
+extern SDH_INFO_T SD0;\r
+/** @endcond HIDDEN_SYMBOLS */\r
+\r
+/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Enable specified interrupt.\r
+ *\r
+ * @param[in] sdh The pointer of the specified SDH module.\r
+ * @param[in] u32IntMask Interrupt type mask:\r
+ * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk /\r
+ * \ref SDH_INTEN_CDSRC_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk /\r
+ * \ref SDH_INTEN_WKIEN_Msk\r
+ *\r
+ * @return None.\r
+ * \hideinitializer\r
+ */\r
+#define SDH_ENABLE_INT(sdh, u32IntMask) ((sdh)->INTEN |= (u32IntMask))\r
+\r
+/**\r
+ * @brief Disable specified interrupt.\r
+ *\r
+ * @param[in] sdh The pointer of the specified SDH module.\r
+ * @param[in] u32IntMask Interrupt type mask:\r
+ * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk /\r
+ * \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk /\r
+ *\r
+ * @return None.\r
+ * \hideinitializer\r
+ */\r
+#define SDH_DISABLE_INT(sdh, u32IntMask) ((sdh)->INTEN &= ~(u32IntMask))\r
+\r
+/**\r
+ * @brief Get specified interrupt flag/status.\r
+ *\r
+ * @param[in] sdh The pointer of the specified SDH module.\r
+ * @param[in] u32IntMask Interrupt type mask:\r
+ * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk /\r
+ * \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk /\r
+ * \ref SDH_INTSTS_CDIF_Msk / \ref SDH_INTSTS_RTOIF_Msk /\r
+ * \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk /\r
+ * \ref SDH_INTSTS_DAT1STS_Msk\r
+ *\r
+ *\r
+ * @return 0 = The specified interrupt is not happened.\r
+ * 1 = The specified interrupt is happened.\r
+ * \hideinitializer\r
+ */\r
+#define SDH_GET_INT_FLAG(sdh, u32IntMask) (((sdh)->INTSTS & (u32IntMask))?1:0)\r
+\r
+\r
+/**\r
+ * @brief Clear specified interrupt flag/status.\r
+ *\r
+ * @param[in] sdh The pointer of the specified SDH module.\r
+ * @param[in] u32IntMask Interrupt type mask:\r
+ * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk /\r
+ * \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk\r
+ *\r
+ *\r
+ * @return None.\r
+ * \hideinitializer\r
+ */\r
+#define SDH_CLR_INT_FLAG(sdh, u32IntMask) ((sdh)->INTSTS = (u32IntMask))\r
+\r
+\r
+/**\r
+ * @brief Check SD Card inserted or removed.\r
+ *\r
+ * @param[in] sdh The pointer of the specified SDH module.\r
+ *\r
+ * @return 1: Card inserted.\r
+ * 0: Card removed.\r
+ * \hideinitializer\r
+ */\r
+#define SDH_IS_CARD_PRESENT(sdh) ((((sdh) == SDH0)||((sdh) == SDH0_NS))? SD0.IsCardInsert : 0)\r
+\r
+/**\r
+ * @brief Get SD Card capacity.\r
+ *\r
+ * @param[in] sdh The pointer of the specified SDH module.\r
+ *\r
+ * @return SD Card capacity. (unit: KByte)\r
+ * \hideinitializer\r
+ */\r
+#define SDH_GET_CARD_CAPACITY(sdh) ((((sdh) == SDH0)||((sdh) == SDH0_NS))? SD0.diskSize : 0)\r
+\r
+\r
+void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc);\r
+uint32_t SDH_Probe(SDH_T *sdh);\r
+uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);\r
+uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);\r
+\r
+uint32_t SDH_CardDetection(SDH_T *sdh);\r
+void SDH_Open_Disk(SDH_T *sdh, uint32_t u32CardDetSrc);\r
+void SDH_Close_Disk(SDH_T *sdh);\r
+\r
+/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group SDH_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* end of __SDH_H__ */\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/******************************************************************************\r
+ * @file spi.h\r
+ * @version V3.00\r
+ * @brief M2351 series SPI driver header file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#ifndef __SPI_H__\r
+#define __SPI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SPI_Driver SPI Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants\r
+ @{\r
+*/\r
+\r
+#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */\r
+#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */\r
+#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */\r
+#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */\r
+\r
+#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */\r
+#define SPI_MASTER (0x0UL) /*!< Set as master */\r
+\r
+#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS */\r
+#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */\r
+#define SPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low */\r
+\r
+/* SPI Interrupt Mask */\r
+#define SPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask */\r
+#define SPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask */\r
+#define SPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask */\r
+#define SPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask */\r
+#define SPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask */\r
+#define SPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask */\r
+#define SPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask */\r
+#define SPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask */\r
+#define SPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask */\r
+#define SPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask */\r
+\r
+/* SPI Status Mask */\r
+#define SPI_BUSY_MASK (0x01UL) /*!< Busy status mask */\r
+#define SPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */\r
+#define SPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */\r
+#define SPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */\r
+#define SPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */\r
+#define SPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask */\r
+#define SPI_SPIEN_STS_MASK (0x40UL) /*!< SPIEN status mask */\r
+#define SPI_SSLINE_STS_MASK (0x80UL) /*!< SPIx_SS line status mask */\r
+\r
+\r
+/* I2S Data Width */\r
+#define SPII2S_DATABIT_8 (0UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit */\r
+#define SPII2S_DATABIT_16 (1UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit */\r
+#define SPII2S_DATABIT_24 (2UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit */\r
+#define SPII2S_DATABIT_32 (3UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit */\r
+\r
+/* I2S Audio Format */\r
+#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel */\r
+#define SPII2S_STEREO (0UL) /*!< Stereo channel */\r
+\r
+/* I2S Data Format */\r
+#define SPII2S_FORMAT_I2S (0UL << SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format */\r
+#define SPII2S_FORMAT_MSB (1UL << SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format */\r
+#define SPII2S_FORMAT_PCMA (2UL << SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format */\r
+#define SPII2S_FORMAT_PCMB (3UL << SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format */\r
+\r
+/* I2S Operation mode */\r
+#define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode */\r
+#define SPII2S_MODE_MASTER (0UL) /*!< As master mode */\r
+\r
+/* I2S TX FIFO Threshold */\r
+#define SPII2S_FIFO_TX_LEVEL_WORD_0 (0UL) /*!< TX threshold is 0 word */\r
+#define SPII2S_FIFO_TX_LEVEL_WORD_1 (1UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 1 word */\r
+#define SPII2S_FIFO_TX_LEVEL_WORD_2 (2UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 2 words */\r
+#define SPII2S_FIFO_TX_LEVEL_WORD_3 (3UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 3 words */\r
+/* I2S RX FIFO Threshold */\r
+#define SPII2S_FIFO_RX_LEVEL_WORD_1 (0UL) /*!< RX threshold is 1 word */\r
+#define SPII2S_FIFO_RX_LEVEL_WORD_2 (1UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 2 words */\r
+#define SPII2S_FIFO_RX_LEVEL_WORD_3 (2UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 3 words */\r
+#define SPII2S_FIFO_RX_LEVEL_WORD_4 (3UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 4 words */\r
+\r
+/* I2S Record Channel */\r
+#define SPII2S_MONO_RIGHT (0UL) /*!< Record mono right channel */\r
+#define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel */\r
+\r
+/* I2S Channel */\r
+#define SPII2S_RIGHT (0UL) /*!< Select right channel */\r
+#define SPII2S_LEFT (1UL) /*!< Select left channel */\r
+\r
+/* I2S Interrupt Mask */\r
+#define SPII2S_FIFO_TXTH_INT_MASK (0x01UL) /*!< TX FIFO threshold interrupt mask */\r
+#define SPII2S_FIFO_RXTH_INT_MASK (0x02UL) /*!< RX FIFO threshold interrupt mask */\r
+#define SPII2S_FIFO_RXOV_INT_MASK (0x04UL) /*!< RX FIFO overrun interrupt mask */\r
+#define SPII2S_FIFO_RXTO_INT_MASK (0x08UL) /*!< RX FIFO time-out interrupt mask */\r
+#define SPII2S_TXUF_INT_MASK (0x10UL) /*!< TX FIFO underflow interrupt mask */\r
+#define SPII2S_RIGHT_ZC_INT_MASK (0x20UL) /*!< Right channel zero cross interrupt mask */\r
+#define SPII2S_LEFT_ZC_INT_MASK (0x40UL) /*!< Left channel zero cross interrupt mask */\r
+\r
+/*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Clear the unit transfer interrupt flag.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.\r
+ */\r
+#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )\r
+\r
+/**\r
+ * @brief Trigger RX PDMA function.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.\r
+ */\r
+#define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Trigger TX PDMA function.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.\r
+ */\r
+#define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Disable RX PDMA transfer.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.\r
+ */\r
+#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Disable TX PDMA transfer.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.\r
+ */\r
+#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Get the count of available data in RX FIFO.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return The count of available data in RX FIFO.\r
+ * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.\r
+ */\r
+#define SPI_GET_RX_FIFO_COUNT(spi) ( ((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos )\r
+\r
+/**\r
+ * @brief Get the RX FIFO empty flag.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @retval 0 RX FIFO is not empty.\r
+ * @retval 1 RX FIFO is empty.\r
+ * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.\r
+ */\r
+#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) >> SPI_STATUS_RXEMPTY_Pos )\r
+\r
+/**\r
+ * @brief Get the TX FIFO empty flag.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @retval 0 TX FIFO is not empty.\r
+ * @retval 1 TX FIFO is empty.\r
+ * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.\r
+ */\r
+#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) >> SPI_STATUS_TXEMPTY_Pos )\r
+\r
+/**\r
+ * @brief Get the TX FIFO full flag.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @retval 0 TX FIFO is not full.\r
+ * @retval 1 TX FIFO is full.\r
+ * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.\r
+ */\r
+#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) >> SPI_STATUS_TXFULL_Pos )\r
+\r
+/**\r
+ * @brief Get the datum read from RX register.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return Data in RX register.\r
+ * @details Read SPI_RX register to get the received datum.\r
+ */\r
+#define SPI_READ_RX(spi) ( (spi)->RX )\r
+\r
+/**\r
+ * @brief Write datum to TX register.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @param[in] u32TxData The datum which user attempt to transfer through SPI bus.\r
+ * @return None.\r
+ * @details Write u32TxData to SPI_TX register.\r
+ */\r
+#define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = (u32TxData) )\r
+\r
+/**\r
+ * @brief Set SPIx_SS pin to high state.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Disable automatic slave selection function and set SPIx_SS pin to high state.\r
+ */\r
+#define SPI_SET_SS_HIGH(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk) )\r
+\r
+/**\r
+ * @brief Set SPIx_SS pin to low state.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Disable automatic slave selection function and set SPIx_SS pin to low state.\r
+ */\r
+#define SPI_SET_SS_LOW(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk )\r
+\r
+/**\r
+ * @brief Enable Byte Reorder function.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).\r
+ */\r
+#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )\r
+\r
+/**\r
+ * @brief Disable Byte Reorder function.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.\r
+ */\r
+#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )\r
+\r
+/**\r
+ * @brief Set the length of suspend interval.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.\r
+ * @return None.\r
+ * @details Set the length of suspend interval according to u32SuspCycle.\r
+ * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).\r
+ */\r
+#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos) )\r
+\r
+/**\r
+ * @brief Set the SPI transfer sequence with LSB first.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.\r
+ */\r
+#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )\r
+\r
+/**\r
+ * @brief Set the SPI transfer sequence with MSB first.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.\r
+ */\r
+#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )\r
+\r
+/**\r
+ * @brief Set the data width of a SPI transaction.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @param[in] u32Width The bit width of one transaction.\r
+ * @return None.\r
+ * @details The data width can be 8 ~ 32 bits.\r
+ */\r
+#define SPI_SET_DATA_WIDTH(spi, u32Width) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << SPI_CTL_DWIDTH_Pos) )\r
+\r
+/**\r
+ * @brief Get the SPI busy state.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @retval 0 SPI controller is not busy.\r
+ * @retval 1 SPI controller is busy.\r
+ * @details This macro will return the busy state of SPI controller.\r
+ */\r
+#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk) >> SPI_STATUS_BUSY_Pos )\r
+\r
+/**\r
+ * @brief Enable SPI controller.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.\r
+ */\r
+#define SPI_ENABLE(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )\r
+\r
+/**\r
+ * @brief Disable SPI controller.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None.\r
+ * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.\r
+ */\r
+#define SPI_DISABLE(spi) ( (spi)->CTL &= ~SPI_CTL_SPIEN_Msk )\r
+\r
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */\r
+__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);\r
+__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);\r
+__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch);\r
+\r
+/**\r
+ * @brief Enable zero cross detection function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32ChMask The mask for left or right channel. Valid values are:\r
+ * - \ref SPII2S_RIGHT\r
+ * - \ref SPII2S_LEFT\r
+ * @return None\r
+ * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.\r
+ */\r
+__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)\r
+{\r
+ if(u32ChMask == SPII2S_RIGHT)\r
+ {\r
+ i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;\r
+ }\r
+ else\r
+ {\r
+ i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable zero cross detection function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32ChMask The mask for left or right channel. Valid values are:\r
+ * - \ref SPII2S_RIGHT\r
+ * - \ref SPII2S_LEFT\r
+ * @return None\r
+ * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.\r
+ */\r
+__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)\r
+{\r
+ if(u32ChMask == SPII2S_RIGHT)\r
+ {\r
+ i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;\r
+ }\r
+ else\r
+ {\r
+ i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable I2S TX DMA function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.\r
+ */\r
+#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Disable I2S TX DMA function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.\r
+ */\r
+#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Enable I2S RX DMA function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.\r
+ */\r
+#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Disable I2S RX DMA function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.\r
+ */\r
+#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Enable I2S TX function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.\r
+ */\r
+#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )\r
+\r
+/**\r
+ * @brief Disable I2S TX function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.\r
+ */\r
+#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )\r
+\r
+/**\r
+ * @brief Enable I2S RX function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.\r
+ */\r
+#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )\r
+\r
+/**\r
+ * @brief Disable I2S RX function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.\r
+ */\r
+#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )\r
+\r
+/**\r
+ * @brief Enable TX Mute function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.\r
+ */\r
+#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )\r
+\r
+/**\r
+ * @brief Disable TX Mute function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.\r
+ */\r
+#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )\r
+\r
+/**\r
+ * @brief Clear TX FIFO.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.\r
+ */\r
+#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )\r
+\r
+/**\r
+ * @brief Clear RX FIFO.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.\r
+ */\r
+#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )\r
+\r
+/**\r
+ * @brief This function sets the recording source channel when mono mode is used.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32Ch left or right channel. Valid values are:\r
+ * - \ref SPII2S_MONO_LEFT\r
+ * - \ref SPII2S_MONO_RIGHT\r
+ * @return None\r
+ * @details This function selects the recording source channel of monaural mode.\r
+ */\r
+__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)\r
+{\r
+ u32Ch == SPII2S_MONO_LEFT ?\r
+ (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :\r
+ (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Write data to I2S TX FIFO.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32Data The value written to TX FIFO.\r
+ * @return None\r
+ * @details This macro will write a value to TX FIFO.\r
+ */\r
+#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )\r
+\r
+/**\r
+ * @brief Read RX FIFO.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return The value read from RX FIFO.\r
+ * @details This function will return a value read from RX FIFO.\r
+ */\r
+#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )\r
+\r
+/**\r
+ * @brief Get the interrupt flag.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32Mask The mask value for all interrupt flags.\r
+ * @return The interrupt flags specified by the u32mask parameter.\r
+ * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.\r
+ */\r
+#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )\r
+\r
+/**\r
+ * @brief Clear the interrupt flag.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32Mask The mask value for all interrupt flags.\r
+ * @return None\r
+ * @details This macro will clear the interrupt flags specified by the u32mask parameter.\r
+ * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.\r
+ */\r
+#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )\r
+\r
+/**\r
+ * @brief Get transmit FIFO level\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return TX FIFO level\r
+ * @details This macro will return the number of available words in TX FIFO.\r
+ */\r
+#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )\r
+\r
+/**\r
+ * @brief Get receive FIFO level\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return RX FIFO level\r
+ * @details This macro will return the number of available words in RX FIFO.\r
+ */\r
+#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )\r
+\r
+\r
+\r
+/* Function prototype declaration */\r
+uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);\r
+void SPI_Close(SPI_T *spi);\r
+void SPI_ClearRxFIFO(SPI_T *spi);\r
+void SPI_ClearTxFIFO(SPI_T *spi);\r
+void SPI_DisableAutoSS(SPI_T *spi);\r
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);\r
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);\r
+void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);\r
+uint32_t SPI_GetBusClock(SPI_T *spi);\r
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);\r
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);\r
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);\r
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);\r
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);\r
+\r
+uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);\r
+void SPII2S_Close(SPI_T *i2s);\r
+void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);\r
+void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);\r
+uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);\r
+void SPII2S_DisableMCLK(SPI_T *i2s);\r
+void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);\r
+\r
+\r
+/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group SPI_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SPI_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file SYS.h\r
+ * @version V3\r
+ * @brief M2351 series System Manager (SYS) driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __SYS_H__\r
+#define __SYS_H__\r
+\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SYS_Driver SYS Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Module Reset Control Resister constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define PDMA0_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA0RST_Pos) /*!< PDMA0 reset is one of the SYS_ResetModule parameter */\r
+#define EBI_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_EBIRST_Pos) /*!< EBI reset is one of the SYS_ResetModule parameter */\r
+#define USBH_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_USBHRST_Pos) /*!< USBH reset is one of the SYS_ResetModule parameter */\r
+#define SDH0_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_SDH0RST_Pos) /*!< SDH0 reset is one of the SYS_ResetModule parameter */\r
+#define CRC_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRCRST_Pos) /*!< CRC reset is one of the SYS_ResetModule parameter */\r
+#define CRPT_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRPTRST_Pos) /*!< CRPT reset is one of the SYS_ResetModule parameter */\r
+#define PDMA1_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA1RST_Pos) /*!< PDMA1 reset is one of the SYS_ResetModule parameter */\r
+\r
+#define GPIO_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_GPIORST_Pos) /*!< GPIO reset is one of the SYS_ResetModule parameter */\r
+#define TMR0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR0RST_Pos) /*!< TMR0 reset is one of the SYS_ResetModule parameter */\r
+#define TMR1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR1RST_Pos) /*!< TMR1 reset is one of the SYS_ResetModule parameter */\r
+#define TMR2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR2RST_Pos) /*!< TMR2 reset is one of the SYS_ResetModule parameter */\r
+#define TMR3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR3RST_Pos) /*!< TMR3 reset is one of the SYS_ResetModule parameter */\r
+#define ACMP01_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_ACMP01RST_Pos) /*!< ACMP01 reset is one of the SYS_ResetModule parameter */\r
+#define I2C0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C0RST_Pos) /*!< I2C0 reset is one of the SYS_ResetModule parameter */\r
+#define I2C1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C1RST_Pos) /*!< I2C1 reset is one of the SYS_ResetModule parameter */\r
+#define I2C2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C2RST_Pos) /*!< I2C2 reset is one of the SYS_ResetModule parameter */\r
+#define QSPI0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_QSPI0RST_Pos) /*!< QSPI0 reset is one of the SYS_ResetModule parameter */\r
+#define SPI0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI0RST_Pos) /*!< SPI0 reset is one of the SYS_ResetModule parameter */\r
+#define SPI1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI1RST_Pos) /*!< SPI1 reset is one of the SYS_ResetModule parameter */\r
+#define SPI2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI2RST_Pos) /*!< SPI2 reset is one of the SYS_ResetModule parameter */\r
+#define UART0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART0RST_Pos) /*!< UART0 reset is one of the SYS_ResetModule parameter */\r
+#define UART1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART1RST_Pos) /*!< UART1 reset is one of the SYS_ResetModule parameter */\r
+#define UART2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART2RST_Pos) /*!< UART2 reset is one of the SYS_ResetModule parameter */\r
+#define UART3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART3RST_Pos) /*!< UART3 reset is one of the SYS_ResetModule parameter */\r
+#define UART4_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART4RST_Pos) /*!< UART4 reset is one of the SYS_ResetModule parameter */\r
+#define UART5_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART5RST_Pos) /*!< UART5 reset is one of the SYS_ResetModule parameter */\r
+#define CAN0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_CAN0RST_Pos) /*!< CAN0 reset is one of the SYS_ResetModule parameter */\r
+#define OTG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_OTGRST_Pos) /*!< OTG reset is one of the SYS_ResetModule parameter */\r
+#define USBD_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_USBDRST_Pos) /*!< USBD reset is one of the SYS_ResetModule parameter */\r
+#define EADC_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_EADCRST_Pos) /*!< EADC reset is one of the SYS_ResetModule parameter */\r
+#define I2S0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2S0RST_Pos) /*!< I2S0 reset is one of the SYS_ResetModule parameter */\r
+#define TRNG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TRNGRST_Pos) /*!< TRNG reset is one of the SYS_ResetModule parameter */\r
+\r
+#define SC0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC0RST_Pos) /*!< SC0 reset is one of the SYS_ResetModule parameter */\r
+#define SC1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC1RST_Pos) /*!< SC1 reset is one of the SYS_ResetModule parameter */\r
+#define SC2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC2RST_Pos) /*!< SC2 reset is one of the SYS_ResetModule parameter */\r
+#define SPI3_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SPI3RST_Pos) /*!< SPI3 reset is one of the SYS_ResetModule parameter */\r
+#define USCI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI0RST_Pos) /*!< USCI0 reset is one of the SYS_ResetModule parameter */\r
+#define USCI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI1RST_Pos) /*!< USCI1 reset is one of the SYS_ResetModule parameter */\r
+#define USCI2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI2RST_Pos) /*!< USCI2 reset is one of the SYS_ResetModule parameter */\r
+#define DAC_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_DACRST_Pos) /*!< DAC reset is one of the SYS_ResetModule parameter */\r
+#define EPWM0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM0RST_Pos) /*!< EPWM0 reset is one of the SYS_ResetModule parameter */\r
+#define EPWM1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM1RST_Pos) /*!< EPWM1 reset is one of the SYS_ResetModule parameter */\r
+#define BPWM0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM0RST_Pos) /*!< BPWM0 reset is one of the SYS_ResetModule parameter */\r
+#define BPWM1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM1RST_Pos) /*!< BPWM1 reset is one of the SYS_ResetModule parameter */\r
+#define QEI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI0RST_Pos) /*!< QEI0 reset is one of the SYS_ResetModule parameter */\r
+#define QEI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI1RST_Pos) /*!< QEI1 reset is one of the SYS_ResetModule parameter */\r
+#define ECAP0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP0RST_Pos) /*!< ECAP0 reset is one of the SYS_ResetModule parameter */\r
+#define ECAP1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP1RST_Pos) /*!< ECAP1 reset is one of the SYS_ResetModule parameter */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Brown Out Detector Threshold Voltage Selection constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable */\r
+#define SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable */\r
+#define SYS_BODCTL_BODVL_3_0V (7UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.0V */\r
+#define SYS_BODCTL_BODVL_2_8V (6UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.8V */\r
+#define SYS_BODCTL_BODVL_2_6V (5UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.6V */\r
+#define SYS_BODCTL_BODVL_2_4V (4UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.4V */\r
+#define SYS_BODCTL_BODVL_2_2V (3UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V */\r
+#define SYS_BODCTL_BODVL_2_0V (2UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.0V */\r
+#define SYS_BODCTL_BODVL_1_8V (1UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.8V */\r
+#define SYS_BODCTL_BODVL_1_6V (0UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.6V */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* VREFCTL constant definitions. (Write-Protection Register) */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define SYS_VREFCTL_VREF_PIN (0x0UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = Vref pin */\r
+#define SYS_VREFCTL_VREF_1_6V (0x3UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 1.6V */\r
+#define SYS_VREFCTL_VREF_2_0V (0x7UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.0V */\r
+#define SYS_VREFCTL_VREF_2_5V (0xBUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.5V */\r
+#define SYS_VREFCTL_VREF_3_0V (0xFUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 3.0V */\r
+#define SYS_VREFCTL_VREF_AVDD (0x10UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = AVDD */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* USBPHY constant definitions. (Write-Protection Register) */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define SYS_USBPHY_USBROLE_STD_USBD (0x0UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device */\r
+#define SYS_USBPHY_USBROLE_STD_USBH (0x1UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host */\r
+#define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL<<SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device */\r
+#define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL<<SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* PLCTL constant definitions. (Write-Protection Register) */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define SYS_PLCTL_PLSEL_PL0 (0x0UL<<SYS_PLCTL_PLSEL_Pos) /*!< Set power level to power level 0 */\r
+#define SYS_PLCTL_PLSEL_PL1 (0x1UL<<SYS_PLCTL_PLSEL_Pos) /*!< Set power level to power level 1 */\r
+#define SYS_PLCTL_MVRS_LDO (0x0UL<<SYS_PLCTL_MVRS_Pos) /*!< Set main voltage regulator type to LDO */\r
+#define SYS_PLCTL_MVRS_DCDC (0x1UL<<SYS_PLCTL_MVRS_Pos) /*!< Set main voltage regulator type to DCDC */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* PLSTS constant definitions. (Write-Protection Register) */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define SYS_PLSTS_PLSTATUS_PL0 (0x0UL<<SYS_PLSTS_PLSTATUS_Pos) /*!< Power level is power level 0 */\r
+#define SYS_PLSTS_PLSTATUS_PL1 (0x1UL<<SYS_PLSTS_PLSTATUS_Pos) /*!< Power level is power level 1 */\r
+#define SYS_PLSTS_CURMVR_LDO (0x0UL<<SYS_PLSTS_CURMVR_Pos) /*!< Main voltage regulator type is LDO */\r
+#define SYS_PLSTS_CURMVR_DCDC (0x1UL<<SYS_PLSTS_CURMVR_Pos) /*!< Main voltage regulator type is DCDC */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* SRAMPCTL constant definitions. (Write-Protection Register) */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define SYS_SRAMPCTL_SRAM_NORMAL 0x0UL /*!< Select system SRAM power mode to normal mode */\r
+#define SYS_SRAMPCTL_SRAM_RETENTION 0x1UL /*!< Select system SRAM power mode to retention mode */\r
+#define SYS_SRAMPCTL_SRAM_POWER_SHUT_DOWN 0x2UL /*!< Select system SRAM power mode to power shut down mode */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* SRAMPPCTL constant definitions. (Write-Protection Register) */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define SYS_SRAMPPCT_SRAM_NORMAL 0x0UL /*!< Select peripheral SRAM power mode to normal mode */\r
+#define SYS_SRAMPPCT_SRAM_RETENTION 0x1UL /*!< Select peripheral SRAM power mode to retention mode */\r
+#define SYS_SRAMPPCT_SRAM_POWER_SHUT_DOWN 0x2UL /*!< Select peripheral SRAM power mode to power shut down mode */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Multi-Function constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+\r
+/* How to use below #define?\r
+\r
+Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial function,\r
+ user can issue following command to achieve it.\r
+\r
+ SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk)) | SYS_GPA_MFPL_PA0MFP_UART0_RXD;\r
+ SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA1MFP_Msk)) | SYS_GPA_MFPL_PA1MFP_UART0_TXD;\r
+*/\r
+\r
+/* PA.0 MFP */\r
+#define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for GPIO */\r
+#define SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0 (0x03UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for QSPI0_MOSI0 */\r
+#define SYS_GPA_MFPL_PA0MFP_SPI0_MOSI (0x04UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SPI0_MOSI */\r
+#define SYS_GPA_MFPL_PA0MFP_SC0_CLK (0x06UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SC0_CLK */\r
+#define SYS_GPA_MFPL_PA0MFP_UART0_RXD (0x07UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART0_RXD */\r
+#define SYS_GPA_MFPL_PA0MFP_UART1_nRTS (0x08UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART1_nRTS */\r
+#define SYS_GPA_MFPL_PA0MFP_I2C2_SDA (0x09UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for I2C2_SDA */\r
+#define SYS_GPA_MFPL_PA0MFP_BPWM0_CH0 (0x0cUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for BPWM0_CH0 */\r
+#define SYS_GPA_MFPL_PA0MFP_EPWM0_CH5 (0x0dUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for EPWM0_CH5 */\r
+#define SYS_GPA_MFPL_PA0MFP_DAC0_ST (0x0fUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for DAC0_ST */\r
+\r
+/* PA.1 MFP */\r
+#define SYS_GPA_MFPL_PA1MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for GPIO */\r
+#define SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0 (0x03UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for QSPI0_MISO0 */\r
+#define SYS_GPA_MFPL_PA1MFP_SPI0_MISO (0x04UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SPI0_MISO */\r
+#define SYS_GPA_MFPL_PA1MFP_SC0_DAT (0x06UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SC0_DAT */\r
+#define SYS_GPA_MFPL_PA1MFP_UART0_TXD (0x07UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART0_TXD */\r
+#define SYS_GPA_MFPL_PA1MFP_UART1_nCTS (0x08UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART1_nCTS */\r
+#define SYS_GPA_MFPL_PA1MFP_I2C2_SCL (0x09UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for I2C2_SCL */\r
+#define SYS_GPA_MFPL_PA1MFP_BPWM0_CH1 (0x0cUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for BPWM0_CH1 */\r
+#define SYS_GPA_MFPL_PA1MFP_EPWM0_CH4 (0x0dUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for EPWM0_CH4 */\r
+#define SYS_GPA_MFPL_PA1MFP_DAC1_ST (0x0fUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for DAC1_ST */\r
+\r
+/* PA.2 MFP */\r
+#define SYS_GPA_MFPL_PA2MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for GPIO */\r
+#define SYS_GPA_MFPL_PA2MFP_QSPI0_CLK (0x03UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for QSPI0_CLK */\r
+#define SYS_GPA_MFPL_PA2MFP_SPI0_CLK (0x04UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SPI0_CLK */\r
+#define SYS_GPA_MFPL_PA2MFP_SC0_RST (0x06UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SC0_RST */\r
+#define SYS_GPA_MFPL_PA2MFP_UART4_RXD (0x07UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART4_RXD */\r
+#define SYS_GPA_MFPL_PA2MFP_UART1_RXD (0x08UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART1_RXD */\r
+#define SYS_GPA_MFPL_PA2MFP_I2C1_SDA (0x09UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for I2C1_SDA */\r
+#define SYS_GPA_MFPL_PA2MFP_BPWM0_CH2 (0x0cUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for BPWM0_CH2 */\r
+#define SYS_GPA_MFPL_PA2MFP_EPWM0_CH3 (0x0dUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for EPWM0_CH3 */\r
+\r
+/* PA.3 MFP */\r
+#define SYS_GPA_MFPL_PA3MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for GPIO */\r
+#define SYS_GPA_MFPL_PA3MFP_QSPI0_SS (0x03UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for QSPI0_SS */\r
+#define SYS_GPA_MFPL_PA3MFP_SPI0_SS (0x04UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SPI0_SS */\r
+#define SYS_GPA_MFPL_PA3MFP_SC0_PWR (0x06UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SC0_PWR */\r
+#define SYS_GPA_MFPL_PA3MFP_UART4_TXD (0x07UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART4_TXD */\r
+#define SYS_GPA_MFPL_PA3MFP_UART1_TXD (0x08UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART1_TXD */\r
+#define SYS_GPA_MFPL_PA3MFP_I2C1_SCL (0x09UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for I2C1_SCL */\r
+#define SYS_GPA_MFPL_PA3MFP_BPWM0_CH3 (0x0cUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for BPWM0_CH3 */\r
+#define SYS_GPA_MFPL_PA3MFP_EPWM0_CH2 (0x0dUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for EPWM0_CH2 */\r
+#define SYS_GPA_MFPL_PA3MFP_QEI0_B (0x0eUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for QEI0_B */\r
+\r
+/* PA.4 MFP */\r
+#define SYS_GPA_MFPL_PA4MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for GPIO */\r
+#define SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1 (0x03UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for QSPI0_MOSI1 */\r
+#define SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SPI0_I2SMCLK*/\r
+#define SYS_GPA_MFPL_PA4MFP_SC0_nCD (0x06UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SC0_nCD */\r
+#define SYS_GPA_MFPL_PA4MFP_UART0_nRTS (0x07UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for UART0_nRTS */\r
+#define SYS_GPA_MFPL_PA4MFP_UART5_RXD (0x08UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for UART5_RXD */\r
+#define SYS_GPA_MFPL_PA4MFP_I2C0_SDA (0x09UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for I2C0_SDA */\r
+#define SYS_GPA_MFPL_PA4MFP_CAN0_RXD (0x0aUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for CAN0_RXD */\r
+#define SYS_GPA_MFPL_PA4MFP_BPWM0_CH4 (0x0cUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for BPWM0_CH4 */\r
+#define SYS_GPA_MFPL_PA4MFP_EPWM0_CH1 (0x0dUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for EPWM0_CH1 */\r
+#define SYS_GPA_MFPL_PA4MFP_QEI0_A (0x0eUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for QEI0_A */\r
+\r
+/* PA.5 MFP */\r
+#define SYS_GPA_MFPL_PA5MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for GPIO */\r
+#define SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1 (0x03UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for QSPI0_MISO1 */\r
+#define SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SPI1_I2SMCLK*/\r
+#define SYS_GPA_MFPL_PA5MFP_SC2_nCD (0x06UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SC2_nCD */\r
+#define SYS_GPA_MFPL_PA5MFP_UART0_nCTS (0x07UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for UART0_nCTS */\r
+#define SYS_GPA_MFPL_PA5MFP_UART5_TXD (0x08UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for UART5_TXD */\r
+#define SYS_GPA_MFPL_PA5MFP_I2C0_SCL (0x09UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for I2C0_SCL */\r
+#define SYS_GPA_MFPL_PA5MFP_CAN0_TXD (0x0aUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for CAN0_TXD */\r
+#define SYS_GPA_MFPL_PA5MFP_BPWM0_CH5 (0x0cUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for BPWM0_CH5 */\r
+#define SYS_GPA_MFPL_PA5MFP_EPWM0_CH0 (0x0dUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for EPWM0_CH0 */\r
+#define SYS_GPA_MFPL_PA5MFP_QEI0_INDEX (0x0eUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for QEI0_INDEX */\r
+\r
+/* PA.6 MFP */\r
+#define SYS_GPA_MFPL_PA6MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for GPIO */\r
+#define SYS_GPA_MFPL_PA6MFP_EBI_AD6 (0x02UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EBI_AD6 */\r
+#define SYS_GPA_MFPL_PA6MFP_SPI1_SS (0x04UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for SPI1_SS */\r
+#define SYS_GPA_MFPL_PA6MFP_SC2_CLK (0x06UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for SC2_CLK */\r
+#define SYS_GPA_MFPL_PA6MFP_UART0_RXD (0x07UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for UART0_RXD */\r
+#define SYS_GPA_MFPL_PA6MFP_I2C1_SDA (0x08UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for I2C1_SDA */\r
+#define SYS_GPA_MFPL_PA6MFP_EPWM1_CH5 (0x0bUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EPWM1_CH5 */\r
+#define SYS_GPA_MFPL_PA6MFP_BPWM1_CH3 (0x0cUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for BPWM1_CH3 */\r
+#define SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT (0x0dUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for ACMP1_WLAT */\r
+#define SYS_GPA_MFPL_PA6MFP_TM3 (0x0eUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for TM3 */\r
+#define SYS_GPA_MFPL_PA6MFP_INT0 (0x0fUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for INT0 */\r
+\r
+/* PA.7 MFP */\r
+#define SYS_GPA_MFPL_PA7MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for GPIO */\r
+#define SYS_GPA_MFPL_PA7MFP_EBI_AD7 (0x02UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EBI_AD7 */\r
+#define SYS_GPA_MFPL_PA7MFP_SPI1_CLK (0x04UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SPI1_CLK */\r
+#define SYS_GPA_MFPL_PA7MFP_SC2_DAT (0x06UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SC2_DAT */\r
+#define SYS_GPA_MFPL_PA7MFP_UART0_TXD (0x07UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for UART0_TXD */\r
+#define SYS_GPA_MFPL_PA7MFP_I2C1_SCL (0x08UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for I2C1_SCL */\r
+#define SYS_GPA_MFPL_PA7MFP_EPWM1_CH4 (0x0bUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EPWM1_CH4 */\r
+#define SYS_GPA_MFPL_PA7MFP_BPWM1_CH2 (0x0cUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for BPWM1_CH2 */\r
+#define SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT (0x0dUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for ACMP0_WLAT */\r
+#define SYS_GPA_MFPL_PA7MFP_TM2 (0x0eUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for TM2 */\r
+#define SYS_GPA_MFPL_PA7MFP_INT1 (0x0fUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for INT1 */\r
+\r
+/* PA.8 MFP */\r
+#define SYS_GPA_MFPH_PA8MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for GPIO */\r
+#define SYS_GPA_MFPH_PA8MFP_EBI_ALE (0x02UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for EBI_ALE */\r
+#define SYS_GPA_MFPH_PA8MFP_SC2_CLK (0x03UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for SC2_CLK */\r
+#define SYS_GPA_MFPH_PA8MFP_SPI2_MOSI (0x04UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for SPI2_MOSI */\r
+#define SYS_GPA_MFPH_PA8MFP_USCI0_CTL1 (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for USCI0_CTL1 */\r
+#define SYS_GPA_MFPH_PA8MFP_UART1_RXD (0x07UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for UART1_RXD */\r
+#define SYS_GPA_MFPH_PA8MFP_BPWM0_CH3 (0x09UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for BPWM0_CH3 */\r
+#define SYS_GPA_MFPH_PA8MFP_QEI1_B (0x0aUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for QEI1_B */\r
+#define SYS_GPA_MFPH_PA8MFP_ECAP0_IC2 (0x0bUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for ECAP0_IC2 */\r
+#define SYS_GPA_MFPH_PA8MFP_TM3_EXT (0x0dUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for TM3_EXT */\r
+#define SYS_GPA_MFPH_PA8MFP_INT4 (0x0fUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for INT4 */\r
+\r
+/* PA.9 MFP */\r
+#define SYS_GPA_MFPH_PA9MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for GPIO */\r
+#define SYS_GPA_MFPH_PA9MFP_EBI_MCLK (0x02UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for EBI_MCLK */\r
+#define SYS_GPA_MFPH_PA9MFP_SC2_DAT (0x03UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for SC2_DAT */\r
+#define SYS_GPA_MFPH_PA9MFP_SPI2_MISO (0x04UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for SPI2_MISO */\r
+#define SYS_GPA_MFPH_PA9MFP_USCI0_DAT1 (0x06UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for USCI0_DAT1 */\r
+#define SYS_GPA_MFPH_PA9MFP_UART1_TXD (0x07UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for UART1_TXD */\r
+#define SYS_GPA_MFPH_PA9MFP_BPWM0_CH2 (0x09UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for BPWM0_CH2 */\r
+#define SYS_GPA_MFPH_PA9MFP_QEI1_A (0x0aUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for QEI1_A */\r
+#define SYS_GPA_MFPH_PA9MFP_ECAP0_IC1 (0x0bUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for ECAP0_IC1 */\r
+#define SYS_GPA_MFPH_PA9MFP_TM2_EXT (0x0dUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for TM2_EXT */\r
+\r
+/* PA.10 MFP */\r
+#define SYS_GPA_MFPH_PA10MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for GPIO */\r
+#define SYS_GPA_MFPH_PA10MFP_ACMP1_P0 (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for ACMP1_P0 */\r
+#define SYS_GPA_MFPH_PA10MFP_EBI_nWR (0x02UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for EBI_nWR */\r
+#define SYS_GPA_MFPH_PA10MFP_SC2_RST (0x03UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for SC2_RST */\r
+#define SYS_GPA_MFPH_PA10MFP_SPI2_CLK (0x04UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for SPI2_CLK */\r
+#define SYS_GPA_MFPH_PA10MFP_USCI0_DAT0 (0x06UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for USCI0_DAT0 */\r
+#define SYS_GPA_MFPH_PA10MFP_I2C2_SDA (0x07UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for I2C2_SDA */\r
+#define SYS_GPA_MFPH_PA10MFP_BPWM0_CH1 (0x09UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for BPWM0_CH1 */\r
+#define SYS_GPA_MFPH_PA10MFP_QEI1_INDEX (0x0aUL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for QEI1_INDEX */\r
+#define SYS_GPA_MFPH_PA10MFP_ECAP0_IC0 (0x0bUL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for ECAP0_IC0 */\r
+#define SYS_GPA_MFPH_PA10MFP_TM1_EXT (0x0dUL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for TM1_EXT */\r
+#define SYS_GPA_MFPH_PA10MFP_DAC0_ST (0x0eUL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for DAC0_ST */\r
+\r
+/* PA.11 MFP */\r
+#define SYS_GPA_MFPH_PA11MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for GPIO */\r
+#define SYS_GPA_MFPH_PA11MFP_ACMP0_P0 (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for ACMP0_P0 */\r
+#define SYS_GPA_MFPH_PA11MFP_EBI_nRD (0x02UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for EBI_nRD */\r
+#define SYS_GPA_MFPH_PA11MFP_SC2_PWR (0x03UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for SC2_PWR */\r
+#define SYS_GPA_MFPH_PA11MFP_SPI2_SS (0x04UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for SPI2_SS */\r
+#define SYS_GPA_MFPH_PA11MFP_USCI0_CLK (0x06UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for USCI0_CLK */\r
+#define SYS_GPA_MFPH_PA11MFP_I2C2_SCL (0x07UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for I2C2_SCL */\r
+#define SYS_GPA_MFPH_PA11MFP_BPWM0_CH0 (0x09UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for BPWM0_CH0 */\r
+#define SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT (0x0aUL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for EPWM0_SYNC_OUT*/\r
+#define SYS_GPA_MFPH_PA11MFP_TM0_EXT (0x0dUL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for TM0_EXT */\r
+#define SYS_GPA_MFPH_PA11MFP_DAC1_ST (0x0eUL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for DAC1_ST */\r
+\r
+/* PA.12 MFP */\r
+#define SYS_GPA_MFPH_PA12MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for GPIO */\r
+#define SYS_GPA_MFPH_PA12MFP_I2S0_BCLK (0x02UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for I2S0_BCLK */\r
+#define SYS_GPA_MFPH_PA12MFP_UART4_TXD (0x03UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for UART4_TXD */\r
+#define SYS_GPA_MFPH_PA12MFP_I2C1_SCL (0x04UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for I2C1_SCL */\r
+#define SYS_GPA_MFPH_PA12MFP_SPI2_SS (0x05UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for SPI2_SS */\r
+#define SYS_GPA_MFPH_PA12MFP_CAN0_TXD (0x06UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for CAN0_TXD */\r
+#define SYS_GPA_MFPH_PA12MFP_SC2_PWR (0x07UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for SC2_PWR */\r
+#define SYS_GPA_MFPH_PA12MFP_BPWM1_CH2 (0x0bUL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for BPWM1_CH2 */\r
+#define SYS_GPA_MFPH_PA12MFP_QEI1_INDEX (0x0cUL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for QEI1_INDEX */\r
+#define SYS_GPA_MFPH_PA12MFP_USB_VBUS (0x0eUL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for USB_VBUS */\r
+\r
+/* PA.13 MFP */\r
+#define SYS_GPA_MFPH_PA13MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for GPIO */\r
+#define SYS_GPA_MFPH_PA13MFP_I2S0_MCLK (0x02UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for I2S0_MCLK */\r
+#define SYS_GPA_MFPH_PA13MFP_UART4_RXD (0x03UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for UART4_RXD */\r
+#define SYS_GPA_MFPH_PA13MFP_I2C1_SDA (0x04UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for I2C1_SDA */\r
+#define SYS_GPA_MFPH_PA13MFP_SPI2_CLK (0x05UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for SPI2_CLK */\r
+#define SYS_GPA_MFPH_PA13MFP_CAN0_RXD (0x06UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for CAN0_RXD */\r
+#define SYS_GPA_MFPH_PA13MFP_SC2_RST (0x07UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for SC2_RST */\r
+#define SYS_GPA_MFPH_PA13MFP_BPWM1_CH3 (0x0bUL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for BPWM1_CH3 */\r
+#define SYS_GPA_MFPH_PA13MFP_QEI1_A (0x0cUL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for QEI1_A */\r
+#define SYS_GPA_MFPH_PA13MFP_USB_D_N (0x0eUL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for USB_D_N */\r
+\r
+/* PA.14 MFP */\r
+#define SYS_GPA_MFPH_PA14MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for GPIO */\r
+#define SYS_GPA_MFPH_PA14MFP_I2S0_DI (0x02UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for I2S0_DI */\r
+#define SYS_GPA_MFPH_PA14MFP_UART0_TXD (0x03UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for UART0_TXD */\r
+#define SYS_GPA_MFPH_PA14MFP_SPI2_MISO (0x05UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for SPI2_MISO */\r
+#define SYS_GPA_MFPH_PA14MFP_I2C2_SCL (0x06UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for I2C2_SCL */\r
+#define SYS_GPA_MFPH_PA14MFP_SC2_DAT (0x07UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for SC2_DAT */\r
+#define SYS_GPA_MFPH_PA14MFP_BPWM1_CH4 (0x0bUL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for BPWM1_CH4 */\r
+#define SYS_GPA_MFPH_PA14MFP_QEI1_B (0x0cUL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for QEI1_B */\r
+#define SYS_GPA_MFPH_PA14MFP_USB_D_P (0x0eUL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for USB_D_P */\r
+\r
+/* PA.15 MFP */\r
+#define SYS_GPA_MFPH_PA15MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for GPIO */\r
+#define SYS_GPA_MFPH_PA15MFP_I2S0_DO (0x02UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for I2S0_DO */\r
+#define SYS_GPA_MFPH_PA15MFP_UART0_RXD (0x03UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for UART0_RXD */\r
+#define SYS_GPA_MFPH_PA15MFP_SPI2_MOSI (0x05UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for SPI2_MOSI */\r
+#define SYS_GPA_MFPH_PA15MFP_I2C2_SDA (0x06UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for I2C2_SDA */\r
+#define SYS_GPA_MFPH_PA15MFP_SC2_CLK (0x07UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for SC2_CLK */\r
+#define SYS_GPA_MFPH_PA15MFP_BPWM1_CH5 (0x0bUL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for BPWM1_CH5 */\r
+#define SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN (0x0cUL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for EPWM0_SYNC_IN*/\r
+#define SYS_GPA_MFPH_PA15MFP_USB_OTG_ID (0x0eUL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for USB_OTG_ID */\r
+\r
+/* PB.0 MFP */\r
+#define SYS_GPB_MFPL_PB0MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for GPIO */\r
+#define SYS_GPB_MFPL_PB0MFP_EADC0_CH0 (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EADC0_CH0 */\r
+#define SYS_GPB_MFPL_PB0MFP_EBI_ADR9 (0x02UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EBI_ADR9 */\r
+#define SYS_GPB_MFPL_PB0MFP_SD0_CMD (0x03UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SD0_CMD */\r
+#define SYS_GPB_MFPL_PB0MFP_UART2_RXD (0x07UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for UART2_RXD */\r
+#define SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK (0x08UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SPI0_I2SMCLK*/\r
+#define SYS_GPB_MFPL_PB0MFP_I2C1_SDA (0x09UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for I2C1_SDA */\r
+#define SYS_GPB_MFPL_PB0MFP_EPWM0_CH5 (0x0bUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EPWM0_CH5 */\r
+#define SYS_GPB_MFPL_PB0MFP_EPWM1_CH5 (0x0cUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EPWM1_CH5 */\r
+#define SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1 (0x0dUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EPWM0_BRAKE1*/\r
+\r
+/* PB.1 MFP */\r
+#define SYS_GPB_MFPL_PB1MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for GPIO */\r
+#define SYS_GPB_MFPL_PB1MFP_EADC0_CH1 (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EADC0_CH1 */\r
+#define SYS_GPB_MFPL_PB1MFP_EBI_ADR8 (0x02UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EBI_ADR8 */\r
+#define SYS_GPB_MFPL_PB1MFP_SD0_CLK (0x03UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SD0_CLK */\r
+#define SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK (0x05UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SPI1_I2SMCLK*/\r
+#define SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK (0x06UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SPI3_I2SMCLK*/\r
+#define SYS_GPB_MFPL_PB1MFP_UART2_TXD (0x07UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for UART2_TXD */\r
+#define SYS_GPB_MFPL_PB1MFP_USCI1_CLK (0x08UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for USCI1_CLK */\r
+#define SYS_GPB_MFPL_PB1MFP_I2C1_SCL (0x09UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for I2C1_SCL */\r
+#define SYS_GPB_MFPL_PB1MFP_I2S0_LRCK (0x0aUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for I2S0_LRCK */\r
+#define SYS_GPB_MFPL_PB1MFP_EPWM0_CH4 (0x0bUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EPWM0_CH4 */\r
+#define SYS_GPB_MFPL_PB1MFP_EPWM1_CH4 (0x0cUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EPWM1_CH4 */\r
+#define SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0 (0x0dUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EPWM0_BRAKE0*/\r
+\r
+/* PB.2 MFP */\r
+#define SYS_GPB_MFPL_PB2MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for GPIO */\r
+#define SYS_GPB_MFPL_PB2MFP_EADC0_CH2 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EADC0_CH2 */\r
+#define SYS_GPB_MFPL_PB2MFP_ACMP0_P1 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for ACMP0_P1 */\r
+#define SYS_GPB_MFPL_PB2MFP_EBI_ADR3 (0x02UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EBI_ADR3 */\r
+#define SYS_GPB_MFPL_PB2MFP_SD0_DAT0 (0x03UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SD0_DAT0 */\r
+#define SYS_GPB_MFPL_PB2MFP_SPI1_SS (0x05UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI1_SS */\r
+#define SYS_GPB_MFPL_PB2MFP_UART1_RXD (0x06UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART1_RXD */\r
+#define SYS_GPB_MFPL_PB2MFP_UART5_nCTS (0x07UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART5_nCTS */\r
+#define SYS_GPB_MFPL_PB2MFP_USCI1_DAT0 (0x08UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for USCI1_DAT0 */\r
+#define SYS_GPB_MFPL_PB2MFP_SC0_PWR (0x09UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SC0_PWR */\r
+#define SYS_GPB_MFPL_PB2MFP_I2S0_DO (0x0aUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for I2S0_DO */\r
+#define SYS_GPB_MFPL_PB2MFP_EPWM0_CH3 (0x0bUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EPWM0_CH3 */\r
+#define SYS_GPB_MFPL_PB2MFP_TM3 (0x0eUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for TM3 */\r
+#define SYS_GPB_MFPL_PB2MFP_INT3 (0x0fUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for INT3 */\r
+\r
+/* PB.3 MFP */\r
+#define SYS_GPB_MFPL_PB3MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for GPIO */\r
+#define SYS_GPB_MFPL_PB3MFP_EADC0_CH3 (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EADC0_CH3 */\r
+#define SYS_GPB_MFPL_PB3MFP_ACMP0_N (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for ACMP0_N */\r
+#define SYS_GPB_MFPL_PB3MFP_EBI_ADR2 (0x02UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EBI_ADR2 */\r
+#define SYS_GPB_MFPL_PB3MFP_SD0_DAT1 (0x03UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SD0_DAT1 */\r
+#define SYS_GPB_MFPL_PB3MFP_SPI1_CLK (0x05UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI1_CLK */\r
+#define SYS_GPB_MFPL_PB3MFP_UART1_TXD (0x06UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART1_TXD */\r
+#define SYS_GPB_MFPL_PB3MFP_UART5_nRTS (0x07UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART5_nRTS */\r
+#define SYS_GPB_MFPL_PB3MFP_USCI1_DAT1 (0x08UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for USCI1_DAT1 */\r
+#define SYS_GPB_MFPL_PB3MFP_SC0_RST (0x09UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SC0_RST */\r
+#define SYS_GPB_MFPL_PB3MFP_I2S0_DI (0x0aUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for I2S0_DI */\r
+#define SYS_GPB_MFPL_PB3MFP_EPWM0_CH2 (0x0bUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EPWM0_CH2 */\r
+#define SYS_GPB_MFPL_PB3MFP_TM2 (0x0eUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for TM2 */\r
+#define SYS_GPB_MFPL_PB3MFP_INT2 (0x0fUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for INT2 */\r
+\r
+/* PB.4 MFP */\r
+#define SYS_GPB_MFPL_PB4MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for GPIO */\r
+#define SYS_GPB_MFPL_PB4MFP_EADC0_CH4 (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EADC0_CH4 */\r
+#define SYS_GPB_MFPL_PB4MFP_ACMP1_P1 (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for ACMP1_P1 */\r
+#define SYS_GPB_MFPL_PB4MFP_EBI_ADR1 (0x02UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EBI_ADR1 */\r
+#define SYS_GPB_MFPL_PB4MFP_SD0_DAT2 (0x03UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SD0_DAT2 */\r
+#define SYS_GPB_MFPL_PB4MFP_SPI1_MOSI (0x05UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI1_MOSI */\r
+#define SYS_GPB_MFPL_PB4MFP_I2C0_SDA (0x06UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for I2C0_SDA */\r
+#define SYS_GPB_MFPL_PB4MFP_UART5_RXD (0x07UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART5_RXD */\r
+#define SYS_GPB_MFPL_PB4MFP_USCI1_CTL1 (0x08UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for USCI1_CTL1 */\r
+#define SYS_GPB_MFPL_PB4MFP_SC0_DAT (0x09UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SC0_DAT */\r
+#define SYS_GPB_MFPL_PB4MFP_I2S0_MCLK (0x0aUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for I2S0_MCLK */\r
+#define SYS_GPB_MFPL_PB4MFP_EPWM0_CH1 (0x0bUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EPWM0_CH1 */\r
+#define SYS_GPB_MFPL_PB4MFP_TM1 (0x0eUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for TM1 */\r
+#define SYS_GPB_MFPL_PB4MFP_INT1 (0x0fUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for INT1 */\r
+\r
+/* PB.5 MFP */\r
+#define SYS_GPB_MFPL_PB5MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for GPIO */\r
+#define SYS_GPB_MFPL_PB5MFP_EADC0_CH5 (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EADC0_CH5 */\r
+#define SYS_GPB_MFPL_PB5MFP_ACMP1_N (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for ACMP1_N */\r
+#define SYS_GPB_MFPL_PB5MFP_EBI_ADR0 (0x02UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EBI_ADR0 */\r
+#define SYS_GPB_MFPL_PB5MFP_SD0_DAT3 (0x03UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SD0_DAT3 */\r
+#define SYS_GPB_MFPL_PB5MFP_SPI1_MISO (0x05UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI1_MISO */\r
+#define SYS_GPB_MFPL_PB5MFP_I2C0_SCL (0x06UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for I2C0_SCL */\r
+#define SYS_GPB_MFPL_PB5MFP_UART5_TXD (0x07UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART5_TXD */\r
+#define SYS_GPB_MFPL_PB5MFP_USCI1_CTL0 (0x08UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for USCI1_CTL0 */\r
+#define SYS_GPB_MFPL_PB5MFP_SC0_CLK (0x09UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SC0_CLK */\r
+#define SYS_GPB_MFPL_PB5MFP_I2S0_BCLK (0x0aUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for I2S0_BCLK */\r
+#define SYS_GPB_MFPL_PB5MFP_EPWM0_CH0 (0x0bUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EPWM0_CH0 */\r
+#define SYS_GPB_MFPL_PB5MFP_TM0 (0x0eUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for TM0 */\r
+#define SYS_GPB_MFPL_PB5MFP_INT0 (0x0fUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for INT0 */\r
+\r
+/* PB.6 MFP */\r
+#define SYS_GPB_MFPL_PB6MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for GPIO */\r
+#define SYS_GPB_MFPL_PB6MFP_EADC0_CH6 (0x01UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EADC0_CH6 */\r
+#define SYS_GPB_MFPL_PB6MFP_EBI_nWRH (0x02UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_nWRH */\r
+#define SYS_GPB_MFPL_PB6MFP_USCI1_DAT1 (0x04UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for USCI1_DAT1 */\r
+#define SYS_GPB_MFPL_PB6MFP_UART1_RXD (0x06UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for UART1_RXD */\r
+#define SYS_GPB_MFPL_PB6MFP_EBI_nCS1 (0x08UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_nCS1 */\r
+#define SYS_GPB_MFPL_PB6MFP_BPWM1_CH5 (0x0aUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for BPWM1_CH5 */\r
+#define SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1 (0x0bUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EPWM1_BRAKE1*/\r
+#define SYS_GPB_MFPL_PB6MFP_EPWM1_CH5 (0x0cUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EPWM1_CH5 */\r
+#define SYS_GPB_MFPL_PB6MFP_INT4 (0x0dUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for INT4 */\r
+#define SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN (0x0eUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for USB_VBUS_EN */\r
+#define SYS_GPB_MFPL_PB6MFP_ACMP1_O (0x0fUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for ACMP1_O */\r
+\r
+/* PB.7 MFP */\r
+#define SYS_GPB_MFPL_PB7MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for GPIO */\r
+#define SYS_GPB_MFPL_PB7MFP_EADC0_CH7 (0x01UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EADC0_CH7 */\r
+#define SYS_GPB_MFPL_PB7MFP_EBI_nWRL (0x02UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_nWRL */\r
+#define SYS_GPB_MFPL_PB7MFP_USCI1_DAT0 (0x04UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for USCI1_DAT0 */\r
+#define SYS_GPB_MFPL_PB7MFP_UART1_TXD (0x06UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for UART1_TXD */\r
+#define SYS_GPB_MFPL_PB7MFP_EBI_nCS0 (0x08UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_nCS0 */\r
+#define SYS_GPB_MFPL_PB7MFP_BPWM1_CH4 (0x0aUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for BPWM1_CH4 */\r
+#define SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0 (0x0bUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EPWM1_BRAKE0*/\r
+#define SYS_GPB_MFPL_PB7MFP_EPWM1_CH4 (0x0cUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EPWM1_CH4 */\r
+#define SYS_GPB_MFPL_PB7MFP_INT5 (0x0dUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for INT5 */\r
+#define SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST (0x0eUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for USB_VBUS_ST */\r
+#define SYS_GPB_MFPL_PB7MFP_ACMP0_O (0x0fUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for ACMP0_O */\r
+\r
+/* PB.8 MFP */\r
+#define SYS_GPB_MFPH_PB8MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for GPIO */\r
+#define SYS_GPB_MFPH_PB8MFP_EADC0_CH8 (0x01UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EADC0_CH8 */\r
+#define SYS_GPB_MFPH_PB8MFP_EBI_ADR19 (0x02UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EBI_ADR19 */\r
+#define SYS_GPB_MFPH_PB8MFP_USCI1_CLK (0x04UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for USCI1_CLK */\r
+#define SYS_GPB_MFPH_PB8MFP_UART0_RXD (0x05UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART0_RXD */\r
+#define SYS_GPB_MFPH_PB8MFP_UART1_nRTS (0x06UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART1_nRTS */\r
+#define SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS (0x07UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for I2C1_SMBSUS */\r
+#define SYS_GPB_MFPH_PB8MFP_BPWM1_CH3 (0x0aUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for BPWM1_CH3 */\r
+#define SYS_GPB_MFPH_PB8MFP_SPI3_MOSI (0x0bUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for SPI3_MOSI */\r
+#define SYS_GPB_MFPH_PB8MFP_INT6 (0x0dUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for INT6 */\r
+\r
+/* PB.9 MFP */\r
+#define SYS_GPB_MFPH_PB9MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for GPIO */\r
+#define SYS_GPB_MFPH_PB9MFP_EADC0_CH9 (0x01UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EADC0_CH9 */\r
+#define SYS_GPB_MFPH_PB9MFP_EBI_ADR18 (0x02UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EBI_ADR18 */\r
+#define SYS_GPB_MFPH_PB9MFP_USCI1_CTL1 (0x04UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for USCI1_CTL1 */\r
+#define SYS_GPB_MFPH_PB9MFP_UART0_TXD (0x05UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for UART0_TXD */\r
+#define SYS_GPB_MFPH_PB9MFP_UART1_nCTS (0x06UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for UART1_nCTS */\r
+#define SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL (0x07UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for I2C1_SMBAL */\r
+#define SYS_GPB_MFPH_PB9MFP_BPWM1_CH2 (0x0aUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for BPWM1_CH2 */\r
+#define SYS_GPB_MFPH_PB9MFP_SPI3_MISO (0x0bUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for SPI3_MISO */\r
+#define SYS_GPB_MFPH_PB9MFP_INT7 (0x0dUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for INT7 */\r
+\r
+/* PB.10 MFP */\r
+#define SYS_GPB_MFPH_PB10MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for GPIO */\r
+#define SYS_GPB_MFPH_PB10MFP_EADC0_CH10 (0x01UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for EADC0_CH10 */\r
+#define SYS_GPB_MFPH_PB10MFP_EBI_ADR17 (0x02UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for EBI_ADR17 */\r
+#define SYS_GPB_MFPH_PB10MFP_USCI1_CTL0 (0x04UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for USCI1_CTL0 */\r
+#define SYS_GPB_MFPH_PB10MFP_UART0_nRTS (0x05UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for UART0_nRTS */\r
+#define SYS_GPB_MFPH_PB10MFP_UART4_RXD (0x06UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for UART4_RXD */\r
+#define SYS_GPB_MFPH_PB10MFP_I2C1_SDA (0x07UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for I2C1_SDA */\r
+#define SYS_GPB_MFPH_PB10MFP_CAN0_RXD (0x08UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for CAN0_RXD */\r
+#define SYS_GPB_MFPH_PB10MFP_BPWM1_CH1 (0x0aUL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for BPWM1_CH1 */\r
+#define SYS_GPB_MFPH_PB10MFP_SPI3_SS (0x0bUL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for SPI3_SS */\r
+\r
+/* PB.11 MFP */\r
+#define SYS_GPB_MFPH_PB11MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for GPIO */\r
+#define SYS_GPB_MFPH_PB11MFP_EADC0_CH11 (0x01UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for EADC0_CH11 */\r
+#define SYS_GPB_MFPH_PB11MFP_EBI_ADR16 (0x02UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for EBI_ADR16 */\r
+#define SYS_GPB_MFPH_PB11MFP_UART0_nCTS (0x05UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for UART0_nCTS */\r
+#define SYS_GPB_MFPH_PB11MFP_UART4_TXD (0x06UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for UART4_TXD */\r
+#define SYS_GPB_MFPH_PB11MFP_I2C1_SCL (0x07UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for I2C1_SCL */\r
+#define SYS_GPB_MFPH_PB11MFP_CAN0_TXD (0x08UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for CAN0_TXD */\r
+#define SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK (0x09UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for SPI0_I2SMCLK*/\r
+#define SYS_GPB_MFPH_PB11MFP_BPWM1_CH0 (0x0aUL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for BPWM1_CH0 */\r
+#define SYS_GPB_MFPH_PB11MFP_SPI3_CLK (0x0bUL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for SPI3_CLK */\r
+\r
+/* PB.12 MFP */\r
+#define SYS_GPB_MFPH_PB12MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for GPIO */\r
+#define SYS_GPB_MFPH_PB12MFP_EADC0_CH12 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for EADC0_CH12 */\r
+#define SYS_GPB_MFPH_PB12MFP_DAC0_OUT (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for DAC0_OUT */\r
+#define SYS_GPB_MFPH_PB12MFP_ACMP0_P2 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for ACMP0_P2 */\r
+#define SYS_GPB_MFPH_PB12MFP_ACMP1_P2 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for ACMP1_P2 */\r
+#define SYS_GPB_MFPH_PB12MFP_EBI_AD15 (0x02UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for EBI_AD15 */\r
+#define SYS_GPB_MFPH_PB12MFP_SC1_CLK (0x03UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for SC1_CLK */\r
+#define SYS_GPB_MFPH_PB12MFP_SPI0_MOSI (0x04UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for SPI0_MOSI */\r
+#define SYS_GPB_MFPH_PB12MFP_USCI0_CLK (0x05UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for USCI0_CLK */\r
+#define SYS_GPB_MFPH_PB12MFP_UART0_RXD (0x06UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for UART0_RXD */\r
+#define SYS_GPB_MFPH_PB12MFP_UART3_nCTS (0x07UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for UART3_nCTS */\r
+#define SYS_GPB_MFPH_PB12MFP_I2C2_SDA (0x08UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for I2C2_SDA */\r
+#define SYS_GPB_MFPH_PB12MFP_SD0_nCD (0x09UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for SD0_nCD */\r
+#define SYS_GPB_MFPH_PB12MFP_EPWM1_CH3 (0x0bUL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for EPWM1_CH3 */\r
+#define SYS_GPB_MFPH_PB12MFP_TM3_EXT (0x0dUL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for TM3_EXT */\r
+\r
+/* PB.13 MFP */\r
+#define SYS_GPB_MFPH_PB13MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for GPIO */\r
+#define SYS_GPB_MFPH_PB13MFP_EADC0_CH13 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for EADC0_CH13 */\r
+#define SYS_GPB_MFPH_PB13MFP_DAC1_OUT (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for DAC1_OUT */\r
+#define SYS_GPB_MFPH_PB13MFP_ACMP0_P3 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for ACMP0_P3 */\r
+#define SYS_GPB_MFPH_PB13MFP_ACMP1_P3 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for ACMP1_P3 */\r
+#define SYS_GPB_MFPH_PB13MFP_EBI_AD14 (0x02UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for EBI_AD14 */\r
+#define SYS_GPB_MFPH_PB13MFP_SC1_DAT (0x03UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for SC1_DAT */\r
+#define SYS_GPB_MFPH_PB13MFP_SPI0_MISO (0x04UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for SPI0_MISO */\r
+#define SYS_GPB_MFPH_PB13MFP_USCI0_DAT0 (0x05UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for USCI0_DAT0 */\r
+#define SYS_GPB_MFPH_PB13MFP_UART0_TXD (0x06UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for UART0_TXD */\r
+#define SYS_GPB_MFPH_PB13MFP_UART3_nRTS (0x07UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for UART3_nRTS */\r
+#define SYS_GPB_MFPH_PB13MFP_I2C2_SCL (0x08UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for I2C2_SCL */\r
+#define SYS_GPB_MFPH_PB13MFP_EPWM1_CH2 (0x0bUL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for EPWM1_CH2 */\r
+#define SYS_GPB_MFPH_PB13MFP_TM2_EXT (0x0dUL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for TM2_EXT */\r
+\r
+/* PB.14 MFP */\r
+#define SYS_GPB_MFPH_PB14MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for GPIO */\r
+#define SYS_GPB_MFPH_PB14MFP_EADC0_CH14 (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for EADC0_CH14 */\r
+#define SYS_GPB_MFPH_PB14MFP_EBI_AD13 (0x02UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for EBI_AD13 */\r
+#define SYS_GPB_MFPH_PB14MFP_SC1_RST (0x03UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for SC1_RST */\r
+#define SYS_GPB_MFPH_PB14MFP_SPI0_CLK (0x04UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for SPI0_CLK */\r
+#define SYS_GPB_MFPH_PB14MFP_USCI0_DAT1 (0x05UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for USCI0_DAT1 */\r
+#define SYS_GPB_MFPH_PB14MFP_UART0_nRTS (0x06UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for UART0_nRTS */\r
+#define SYS_GPB_MFPH_PB14MFP_UART3_RXD (0x07UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for UART3_RXD */\r
+#define SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS (0x08UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for I2C2_SMBSUS*/\r
+#define SYS_GPB_MFPH_PB14MFP_EPWM1_CH1 (0x0bUL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for EPWM1_CH1 */\r
+#define SYS_GPB_MFPH_PB14MFP_TM1_EXT (0x0dUL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for TM1_EXT */\r
+#define SYS_GPB_MFPH_PB14MFP_CLKO (0x0eUL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for CLKO */\r
+#define SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST (0x0fUL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for USB_VBUS_ST*/\r
+\r
+/* PB.15 MFP */\r
+#define SYS_GPB_MFPH_PB15MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for GPIO */\r
+#define SYS_GPB_MFPH_PB15MFP_EADC0_CH15 (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for EADC0_CH15 */\r
+#define SYS_GPB_MFPH_PB15MFP_EBI_AD12 (0x02UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for EBI_AD12 */\r
+#define SYS_GPB_MFPH_PB15MFP_SC1_PWR (0x03UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for SC1_PWR */\r
+#define SYS_GPB_MFPH_PB15MFP_SPI0_SS (0x04UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for SPI0_SS */\r
+#define SYS_GPB_MFPH_PB15MFP_USCI0_CTL1 (0x05UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for USCI0_CTL1 */\r
+#define SYS_GPB_MFPH_PB15MFP_UART0_nCTS (0x06UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for UART0_nCTS */\r
+#define SYS_GPB_MFPH_PB15MFP_UART3_TXD (0x07UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for UART3_TXD */\r
+#define SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL (0x08UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for I2C2_SMBAL */\r
+#define SYS_GPB_MFPH_PB15MFP_EPWM1_CH0 (0x0bUL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for EPWM1_CH0 */\r
+#define SYS_GPB_MFPH_PB15MFP_TM0_EXT (0x0dUL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for TM0_EXT */\r
+#define SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN (0x0eUL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for USB_VBUS_EN*/\r
+\r
+/* PC.0 MFP */\r
+#define SYS_GPC_MFPL_PC0MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for GPIO */\r
+#define SYS_GPC_MFPL_PC0MFP_EBI_AD0 (0x02UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EBI_AD0 */\r
+#define SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0 (0x04UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for QSPI0_MOSI0 */\r
+#define SYS_GPC_MFPL_PC0MFP_SC1_CLK (0x05UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SC1_CLK */\r
+#define SYS_GPC_MFPL_PC0MFP_I2S0_LRCK (0x06UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for I2S0_LRCK */\r
+#define SYS_GPC_MFPL_PC0MFP_SPI1_SS (0x07UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SPI1_SS */\r
+#define SYS_GPC_MFPL_PC0MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART2_RXD */\r
+#define SYS_GPC_MFPL_PC0MFP_I2C0_SDA (0x09UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for I2C0_SDA */\r
+#define SYS_GPC_MFPL_PC0MFP_EPWM1_CH5 (0x0cUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EPWM1_CH5 */\r
+#define SYS_GPC_MFPL_PC0MFP_ACMP1_O (0x0eUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for ACMP1_O */\r
+\r
+/* PC.1 MFP */\r
+#define SYS_GPC_MFPL_PC1MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for GPIO */\r
+#define SYS_GPC_MFPL_PC1MFP_EBI_AD1 (0x02UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EBI_AD1 */\r
+#define SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0 (0x04UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for QSPI0_MISO0 */\r
+#define SYS_GPC_MFPL_PC1MFP_SC1_DAT (0x05UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for SC1_DAT */\r
+#define SYS_GPC_MFPL_PC1MFP_I2S0_DO (0x06UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for I2S0_DO */\r
+#define SYS_GPC_MFPL_PC1MFP_SPI1_CLK (0x07UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for SPI1_CLK */\r
+#define SYS_GPC_MFPL_PC1MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART2_TXD */\r
+#define SYS_GPC_MFPL_PC1MFP_I2C0_SCL (0x09UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for I2C0_SCL */\r
+#define SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 (0x0cUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EPWM1_CH4 */\r
+#define SYS_GPC_MFPL_PC1MFP_ACMP0_O (0x0eUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for ACMP0_O */\r
+\r
+/* PC.2 MFP */\r
+#define SYS_GPC_MFPL_PC2MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for GPIO */\r
+#define SYS_GPC_MFPL_PC2MFP_EBI_AD2 (0x02UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EBI_AD2 */\r
+#define SYS_GPC_MFPL_PC2MFP_QSPI0_CLK (0x04UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for QSPI0_CLK */\r
+#define SYS_GPC_MFPL_PC2MFP_SC1_RST (0x05UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SC1_RST */\r
+#define SYS_GPC_MFPL_PC2MFP_I2S0_DI (0x06UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for I2S0_DI */\r
+#define SYS_GPC_MFPL_PC2MFP_SPI1_MOSI (0x07UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SPI1_MOSI */\r
+#define SYS_GPC_MFPL_PC2MFP_UART2_nCTS (0x08UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART2_nCTS */\r
+#define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS (0x09UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for I2C0_SMBSUS */\r
+#define SYS_GPC_MFPL_PC2MFP_UART3_RXD (0x0bUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART3_RXD */\r
+#define SYS_GPC_MFPL_PC2MFP_EPWM1_CH3 (0x0cUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EPWM1_CH3 */\r
+\r
+/* PC.3 MFP */\r
+#define SYS_GPC_MFPL_PC3MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for GPIO */\r
+#define SYS_GPC_MFPL_PC3MFP_EBI_AD3 (0x02UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EBI_AD3 */\r
+#define SYS_GPC_MFPL_PC3MFP_QSPI0_SS (0x04UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for QSPI0_SS */\r
+#define SYS_GPC_MFPL_PC3MFP_SC1_PWR (0x05UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SC1_PWR */\r
+#define SYS_GPC_MFPL_PC3MFP_I2S0_MCLK (0x06UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for I2S0_MCLK */\r
+#define SYS_GPC_MFPL_PC3MFP_SPI1_MISO (0x07UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SPI1_MISO */\r
+#define SYS_GPC_MFPL_PC3MFP_UART2_nRTS (0x08UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART2_nRTS */\r
+#define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL (0x09UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for I2C0_SMBAL */\r
+#define SYS_GPC_MFPL_PC3MFP_UART3_TXD (0x0bUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART3_TXD */\r
+#define SYS_GPC_MFPL_PC3MFP_EPWM1_CH2 (0x0cUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EPWM1_CH2 */\r
+\r
+/* PC.4 MFP */\r
+#define SYS_GPC_MFPL_PC4MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for GPIO */\r
+#define SYS_GPC_MFPL_PC4MFP_EBI_AD4 (0x02UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EBI_AD4 */\r
+#define SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1 (0x04UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for QSPI0_MOSI1 */\r
+#define SYS_GPC_MFPL_PC4MFP_SC1_nCD (0x05UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SC1_nCD */\r
+#define SYS_GPC_MFPL_PC4MFP_I2S0_BCLK (0x06UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2S0_BCLK */\r
+#define SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK (0x07UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SPI1_I2SMCLK*/\r
+#define SYS_GPC_MFPL_PC4MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for UART2_RXD */\r
+#define SYS_GPC_MFPL_PC4MFP_I2C1_SDA (0x09UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2C1_SDA */\r
+#define SYS_GPC_MFPL_PC4MFP_CAN0_RXD (0x0aUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for CAN0_RXD */\r
+#define SYS_GPC_MFPL_PC4MFP_UART4_RXD (0x0bUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for UART4_RXD */\r
+#define SYS_GPC_MFPL_PC4MFP_EPWM1_CH1 (0x0cUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EPWM1_CH1 */\r
+\r
+/* PC.5 MFP */\r
+#define SYS_GPC_MFPL_PC5MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for GPIO */\r
+#define SYS_GPC_MFPL_PC5MFP_EBI_AD5 (0x02UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EBI_AD5 */\r
+#define SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1 (0x04UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for QSPI0_MISO1 */\r
+#define SYS_GPC_MFPL_PC5MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for UART2_TXD */\r
+#define SYS_GPC_MFPL_PC5MFP_I2C1_SCL (0x09UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for I2C1_SCL */\r
+#define SYS_GPC_MFPL_PC5MFP_CAN0_TXD (0x0aUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for CAN0_TXD */\r
+#define SYS_GPC_MFPL_PC5MFP_UART4_TXD (0x0bUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for UART4_TXD */\r
+#define SYS_GPC_MFPL_PC5MFP_EPWM1_CH0 (0x0cUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EPWM1_CH0 */\r
+\r
+/* PC.6 MFP */\r
+#define SYS_GPC_MFPL_PC6MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for GPIO */\r
+#define SYS_GPC_MFPL_PC6MFP_EBI_AD8 (0x02UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EBI_AD8 */\r
+#define SYS_GPC_MFPL_PC6MFP_SPI1_MOSI (0x04UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for SPI1_MOSI */\r
+#define SYS_GPC_MFPL_PC6MFP_UART4_RXD (0x05UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART4_RXD */\r
+#define SYS_GPC_MFPL_PC6MFP_SC2_RST (0x06UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for SC2_RST */\r
+#define SYS_GPC_MFPL_PC6MFP_UART0_nRTS (0x07UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART0_nRTS */\r
+#define SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS (0x08UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for I2C1_SMBSUS */\r
+#define SYS_GPC_MFPL_PC6MFP_EPWM1_CH3 (0x0bUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EPWM1_CH3 */\r
+#define SYS_GPC_MFPL_PC6MFP_BPWM1_CH1 (0x0cUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for BPWM1_CH1 */\r
+#define SYS_GPC_MFPL_PC6MFP_TM1 (0x0eUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for TM1 */\r
+#define SYS_GPC_MFPL_PC6MFP_INT2 (0x0fUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for INT2 */\r
+\r
+/* PC.7 MFP */\r
+#define SYS_GPC_MFPL_PC7MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for GPIO */\r
+#define SYS_GPC_MFPL_PC7MFP_EBI_AD9 (0x02UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EBI_AD9 */\r
+#define SYS_GPC_MFPL_PC7MFP_SPI1_MISO (0x04UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for SPI1_MISO */\r
+#define SYS_GPC_MFPL_PC7MFP_UART4_TXD (0x05UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART4_TXD */\r
+#define SYS_GPC_MFPL_PC7MFP_SC2_PWR (0x06UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for SC2_PWR */\r
+#define SYS_GPC_MFPL_PC7MFP_UART0_nCTS (0x07UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART0_nCTS */\r
+#define SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL (0x08UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for I2C1_SMBAL */\r
+#define SYS_GPC_MFPL_PC7MFP_EPWM1_CH2 (0x0bUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EPWM1_CH2 */\r
+#define SYS_GPC_MFPL_PC7MFP_BPWM1_CH0 (0x0cUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for BPWM1_CH0 */\r
+#define SYS_GPC_MFPL_PC7MFP_TM0 (0x0eUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for TM0 */\r
+#define SYS_GPC_MFPL_PC7MFP_INT3 (0x0fUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for INT3 */\r
+\r
+/* PC.8 MFP */\r
+#define SYS_GPC_MFPH_PC8MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for GPIO */\r
+#define SYS_GPC_MFPH_PC8MFP_EBI_ADR16 (0x02UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for EBI_ADR16 */\r
+#define SYS_GPC_MFPH_PC8MFP_I2C0_SDA (0x04UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for I2C0_SDA */\r
+#define SYS_GPC_MFPH_PC8MFP_UART4_nCTS (0x05UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for UART4_nCTS */\r
+#define SYS_GPC_MFPH_PC8MFP_UART1_RXD (0x08UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for UART1_RXD */\r
+#define SYS_GPC_MFPH_PC8MFP_EPWM1_CH1 (0x0bUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for EPWM1_CH1 */\r
+#define SYS_GPC_MFPH_PC8MFP_BPWM1_CH4 (0x0cUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for BPWM1_CH4 */\r
+\r
+/* PC.9 MFP */\r
+#define SYS_GPC_MFPH_PC9MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for GPIO */\r
+#define SYS_GPC_MFPH_PC9MFP_EBI_ADR7 (0x02UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for EBI_ADR7 */\r
+#define SYS_GPC_MFPH_PC9MFP_SPI3_SS (0x06UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for SPI3_SS */\r
+#define SYS_GPC_MFPH_PC9MFP_UART3_RXD (0x07UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for UART3_RXD */\r
+#define SYS_GPC_MFPH_PC9MFP_EPWM1_CH3 (0x0cUL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for EPWM1_CH3 */\r
+\r
+/* PC.10 MFP */\r
+#define SYS_GPC_MFPH_PC10MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for GPIO */\r
+#define SYS_GPC_MFPH_PC10MFP_EBI_ADR6 (0x02UL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for EBI_ADR6 */\r
+#define SYS_GPC_MFPH_PC10MFP_SPI3_CLK (0x06UL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for SPI3_CLK */\r
+#define SYS_GPC_MFPH_PC10MFP_UART3_TXD (0x07UL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for UART3_TXD */\r
+#define SYS_GPC_MFPH_PC10MFP_ECAP1_IC0 (0x0bUL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for ECAP1_IC0 */\r
+#define SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 (0x0cUL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for EPWM1_CH2 */\r
+\r
+/* PC.11 MFP */\r
+#define SYS_GPC_MFPH_PC11MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for GPIO */\r
+#define SYS_GPC_MFPH_PC11MFP_EBI_ADR5 (0x02UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for EBI_ADR5 */\r
+#define SYS_GPC_MFPH_PC11MFP_UART0_RXD (0x03UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for UART0_RXD */\r
+#define SYS_GPC_MFPH_PC11MFP_I2C0_SDA (0x04UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for I2C0_SDA */\r
+#define SYS_GPC_MFPH_PC11MFP_SPI3_MOSI (0x06UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for SPI3_MOSI */\r
+#define SYS_GPC_MFPH_PC11MFP_ECAP1_IC1 (0x0bUL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for ECAP1_IC1 */\r
+#define SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 (0x0cUL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for EPWM1_CH1 */\r
+#define SYS_GPC_MFPH_PC11MFP_ACMP1_O (0x0eUL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for ACMP1_O */\r
+\r
+/* PC.12 MFP */\r
+#define SYS_GPC_MFPH_PC12MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for GPIO */\r
+#define SYS_GPC_MFPH_PC12MFP_EBI_ADR4 (0x02UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for EBI_ADR4 */\r
+#define SYS_GPC_MFPH_PC12MFP_UART0_TXD (0x03UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for UART0_TXD */\r
+#define SYS_GPC_MFPH_PC12MFP_I2C0_SCL (0x04UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for I2C0_SCL */\r
+#define SYS_GPC_MFPH_PC12MFP_SPI3_MISO (0x06UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for SPI3_MISO */\r
+#define SYS_GPC_MFPH_PC12MFP_SC0_nCD (0x09UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for SC0_nCD */\r
+#define SYS_GPC_MFPH_PC12MFP_ECAP1_IC2 (0x0bUL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for ECAP1_IC2 */\r
+#define SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 (0x0cUL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for EPWM1_CH0 */\r
+#define SYS_GPC_MFPH_PC12MFP_ACMP0_O (0x0eUL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for ACMP0_O */\r
+\r
+/* PC.13 MFP */\r
+#define SYS_GPC_MFPH_PC13MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for GPIO */\r
+#define SYS_GPC_MFPH_PC13MFP_EBI_ADR10 (0x02UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for EBI_ADR10 */\r
+#define SYS_GPC_MFPH_PC13MFP_SC2_nCD (0x03UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for SC2_nCD */\r
+#define SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK (0x04UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for SPI2_I2SMCLK*/\r
+#define SYS_GPC_MFPH_PC13MFP_USCI0_CTL0 (0x06UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for USCI0_CTL0 */\r
+#define SYS_GPC_MFPH_PC13MFP_UART2_TXD (0x07UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for UART2_TXD */\r
+#define SYS_GPC_MFPH_PC13MFP_BPWM0_CH4 (0x09UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for BPWM0_CH4 */\r
+#define SYS_GPC_MFPH_PC13MFP_CLKO (0x0dUL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for CLKO */\r
+#define SYS_GPC_MFPH_PC13MFP_EADC0_ST (0x0eUL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for EADC0_ST */\r
+\r
+/* PD.0 MFP */\r
+#define SYS_GPD_MFPL_PD0MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for GPIO */\r
+#define SYS_GPD_MFPL_PD0MFP_EBI_AD13 (0x02UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for EBI_AD13 */\r
+#define SYS_GPD_MFPL_PD0MFP_USCI0_CLK (0x03UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for USCI0_CLK */\r
+#define SYS_GPD_MFPL_PD0MFP_SPI0_MOSI (0x04UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SPI0_MOSI */\r
+#define SYS_GPD_MFPL_PD0MFP_UART3_RXD (0x05UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for UART3_RXD */\r
+#define SYS_GPD_MFPL_PD0MFP_I2C2_SDA (0x06UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for I2C2_SDA */\r
+#define SYS_GPD_MFPL_PD0MFP_SC2_CLK (0x07UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SC2_CLK */\r
+#define SYS_GPD_MFPL_PD0MFP_TM2 (0x0eUL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for TM2 */\r
+\r
+/* PD.1 MFP */\r
+#define SYS_GPD_MFPL_PD1MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for GPIO */\r
+#define SYS_GPD_MFPL_PD1MFP_EBI_AD12 (0x02UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EBI_AD12 */\r
+#define SYS_GPD_MFPL_PD1MFP_USCI0_DAT0 (0x03UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for USCI0_DAT0 */\r
+#define SYS_GPD_MFPL_PD1MFP_SPI0_MISO (0x04UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for SPI0_MISO */\r
+#define SYS_GPD_MFPL_PD1MFP_UART3_TXD (0x05UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for UART3_TXD */\r
+#define SYS_GPD_MFPL_PD1MFP_I2C2_SCL (0x06UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for I2C2_SCL */\r
+#define SYS_GPD_MFPL_PD1MFP_SC2_DAT (0x07UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for SC2_DAT */\r
+\r
+/* PD.2 MFP */\r
+#define SYS_GPD_MFPL_PD2MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for GPIO */\r
+#define SYS_GPD_MFPL_PD2MFP_EBI_AD11 (0x02UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for EBI_AD11 */\r
+#define SYS_GPD_MFPL_PD2MFP_USCI0_DAT1 (0x03UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for USCI0_DAT1 */\r
+#define SYS_GPD_MFPL_PD2MFP_SPI0_CLK (0x04UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for SPI0_CLK */\r
+#define SYS_GPD_MFPL_PD2MFP_UART3_nCTS (0x05UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for UART3_nCTS */\r
+#define SYS_GPD_MFPL_PD2MFP_SC2_RST (0x07UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for SC2_RST */\r
+#define SYS_GPD_MFPL_PD2MFP_UART0_RXD (0x09UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for UART0_RXD */\r
+\r
+/* PD.3 MFP */\r
+#define SYS_GPD_MFPL_PD3MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for GPIO */\r
+#define SYS_GPD_MFPL_PD3MFP_EBI_AD10 (0x02UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for EBI_AD10 */\r
+#define SYS_GPD_MFPL_PD3MFP_USCI0_CTL1 (0x03UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for USCI0_CTL1 */\r
+#define SYS_GPD_MFPL_PD3MFP_SPI0_SS (0x04UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SPI0_SS */\r
+#define SYS_GPD_MFPL_PD3MFP_UART3_nRTS (0x05UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for UART3_nRTS */\r
+#define SYS_GPD_MFPL_PD3MFP_USCI1_CTL0 (0x06UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for USCI1_CTL0 */\r
+#define SYS_GPD_MFPL_PD3MFP_SC2_PWR (0x07UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SC2_PWR */\r
+#define SYS_GPD_MFPL_PD3MFP_SC1_nCD (0x08UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SC1_nCD */\r
+#define SYS_GPD_MFPL_PD3MFP_UART0_TXD (0x09UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for UART0_TXD */\r
+\r
+/* PD.4 MFP */\r
+#define SYS_GPD_MFPL_PD4MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for GPIO */\r
+#define SYS_GPD_MFPL_PD4MFP_USCI0_CTL0 (0x03UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for USCI0_CTL0 */\r
+#define SYS_GPD_MFPL_PD4MFP_I2C1_SDA (0x04UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for I2C1_SDA */\r
+#define SYS_GPD_MFPL_PD4MFP_SPI1_SS (0x05UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for SPI1_SS */\r
+#define SYS_GPD_MFPL_PD4MFP_USCI1_CTL1 (0x06UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for USCI1_CTL1 */\r
+#define SYS_GPD_MFPL_PD4MFP_SC1_CLK (0x08UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for SC1_CLK */\r
+#define SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST (0x0eUL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for USB_VBUS_ST */\r
+\r
+/* PD.5 MFP */\r
+#define SYS_GPD_MFPL_PD5MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for GPIO */\r
+#define SYS_GPD_MFPL_PD5MFP_I2C1_SCL (0x04UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for I2C1_SCL */\r
+#define SYS_GPD_MFPL_PD5MFP_SPI1_CLK (0x05UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for SPI1_CLK */\r
+#define SYS_GPD_MFPL_PD5MFP_USCI1_DAT0 (0x06UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for USCI1_DAT0 */\r
+#define SYS_GPD_MFPL_PD5MFP_SC1_DAT (0x08UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for SC1_DAT */\r
+\r
+/* PD.6 MFP */\r
+#define SYS_GPD_MFPL_PD6MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for GPIO */\r
+#define SYS_GPD_MFPL_PD6MFP_UART1_RXD (0x03UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for UART1_RXD */\r
+#define SYS_GPD_MFPL_PD6MFP_I2C0_SDA (0x04UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for I2C0_SDA */\r
+#define SYS_GPD_MFPL_PD6MFP_SPI1_MOSI (0x05UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SPI1_MOSI */\r
+#define SYS_GPD_MFPL_PD6MFP_USCI1_DAT1 (0x06UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for USCI1_DAT1 */\r
+#define SYS_GPD_MFPL_PD6MFP_SC1_RST (0x08UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SC1_RST */\r
+\r
+/* PD.7 MFP */\r
+#define SYS_GPD_MFPL_PD7MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for GPIO */\r
+#define SYS_GPD_MFPL_PD7MFP_UART1_TXD (0x03UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for UART1_TXD */\r
+#define SYS_GPD_MFPL_PD7MFP_I2C0_SCL (0x04UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for I2C0_SCL */\r
+#define SYS_GPD_MFPL_PD7MFP_SPI1_MISO (0x05UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for SPI1_MISO */\r
+#define SYS_GPD_MFPL_PD7MFP_USCI1_CLK (0x06UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for USCI1_CLK */\r
+#define SYS_GPD_MFPL_PD7MFP_SC1_PWR (0x08UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for SC1_PWR */\r
+\r
+/* PD.8 MFP */\r
+#define SYS_GPD_MFPH_PD8MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for GPIO */\r
+#define SYS_GPD_MFPH_PD8MFP_EBI_AD6 (0x02UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EBI_AD6 */\r
+#define SYS_GPD_MFPH_PD8MFP_I2C2_SDA (0x03UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for I2C2_SDA */\r
+#define SYS_GPD_MFPH_PD8MFP_UART2_nRTS (0x04UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for UART2_nRTS */\r
+\r
+/* PD.9 MFP */\r
+#define SYS_GPD_MFPH_PD9MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for GPIO */\r
+#define SYS_GPD_MFPH_PD9MFP_EBI_AD7 (0x02UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for EBI_AD7 */\r
+#define SYS_GPD_MFPH_PD9MFP_I2C2_SCL (0x03UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for I2C2_SCL */\r
+#define SYS_GPD_MFPH_PD9MFP_UART2_nCTS (0x04UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for UART2_nCTS */\r
+\r
+/* PD.10 MFP */\r
+#define SYS_GPD_MFPH_PD10MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for GPIO */\r
+#define SYS_GPD_MFPH_PD10MFP_EBI_nCS2 (0x02UL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for EBI_nCS2 */\r
+#define SYS_GPD_MFPH_PD10MFP_UART1_RXD (0x03UL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for UART1_RXD */\r
+#define SYS_GPD_MFPH_PD10MFP_CAN0_RXD (0x04UL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for CAN0_RXD */\r
+#define SYS_GPD_MFPH_PD10MFP_QEI0_B (0x0aUL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for QEI0_B */\r
+#define SYS_GPD_MFPH_PD10MFP_INT7 (0x0fUL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for INT7 */\r
+\r
+/* PD.11 MFP */\r
+#define SYS_GPD_MFPH_PD11MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for GPIO */\r
+#define SYS_GPD_MFPH_PD11MFP_EBI_nCS1 (0x02UL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for EBI_nCS1 */\r
+#define SYS_GPD_MFPH_PD11MFP_UART1_TXD (0x03UL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for UART1_TXD */\r
+#define SYS_GPD_MFPH_PD11MFP_CAN0_TXD (0x04UL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for CAN0_TXD */\r
+#define SYS_GPD_MFPH_PD11MFP_QEI0_A (0x0aUL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for QEI0_A */\r
+#define SYS_GPD_MFPH_PD11MFP_INT6 (0x0fUL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for INT6 */\r
+\r
+/* PD.12 MFP */\r
+#define SYS_GPD_MFPH_PD12MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for GPIO */\r
+#define SYS_GPD_MFPH_PD12MFP_EBI_nCS0 (0x02UL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for EBI_nCS0 */\r
+#define SYS_GPD_MFPH_PD12MFP_UART2_RXD (0x07UL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for UART2_RXD */\r
+#define SYS_GPD_MFPH_PD12MFP_BPWM0_CH5 (0x09UL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for BPWM0_CH5 */\r
+#define SYS_GPD_MFPH_PD12MFP_QEI0_INDEX (0x0aUL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for QEI0_INDEX */\r
+#define SYS_GPD_MFPH_PD12MFP_CLKO (0x0dUL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for CLKO */\r
+#define SYS_GPD_MFPH_PD12MFP_EADC0_ST (0x0eUL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for EADC0_ST */\r
+#define SYS_GPD_MFPH_PD12MFP_INT5 (0x0fUL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for INT5 */\r
+\r
+/* PD.13 MFP */\r
+#define SYS_GPD_MFPH_PD13MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for GPIO */\r
+#define SYS_GPD_MFPH_PD13MFP_EBI_AD10 (0x02UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for EBI_AD10 */\r
+#define SYS_GPD_MFPH_PD13MFP_SD0_nCD (0x03UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for SD0_nCD */\r
+#define SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for SPI0_I2SMCLK*/\r
+#define SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK (0x05UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for SPI1_I2SMCLK*/\r
+#define SYS_GPD_MFPH_PD13MFP_SC2_nCD (0x07UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for SC2_nCD */\r
+\r
+/* PD.14 MFP */\r
+#define SYS_GPD_MFPH_PD14MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for GPIO */\r
+#define SYS_GPD_MFPH_PD14MFP_EBI_nCS0 (0x02UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for EBI_nCS0 */\r
+#define SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK (0x03UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for SPI3_I2SMCLK*/\r
+#define SYS_GPD_MFPH_PD14MFP_SC1_nCD (0x04UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for SC1_nCD */\r
+#define SYS_GPD_MFPH_PD14MFP_USCI0_CTL0 (0x05UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for USCI0_CTL0 */\r
+#define SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK (0x06UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for SPI0_I2SMCLK*/\r
+#define SYS_GPD_MFPH_PD14MFP_EPWM0_CH4 (0x0bUL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for EPWM0_CH4 */\r
+\r
+/* PE.0 MFP */\r
+#define SYS_GPE_MFPL_PE0MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for GPIO */\r
+#define SYS_GPE_MFPL_PE0MFP_EBI_AD11 (0x02UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for EBI_AD11 */\r
+#define SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0 (0x03UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for QSPI0_MOSI0 */\r
+#define SYS_GPE_MFPL_PE0MFP_SC2_CLK (0x04UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SC2_CLK */\r
+#define SYS_GPE_MFPL_PE0MFP_I2S0_MCLK (0x05UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for I2S0_MCLK */\r
+#define SYS_GPE_MFPL_PE0MFP_SPI1_MOSI (0x06UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SPI1_MOSI */\r
+#define SYS_GPE_MFPL_PE0MFP_UART3_RXD (0x07UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for UART3_RXD */\r
+#define SYS_GPE_MFPL_PE0MFP_I2C1_SDA (0x08UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for I2C1_SDA */\r
+#define SYS_GPE_MFPL_PE0MFP_UART4_nRTS (0x09UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for UART4_nRTS */\r
+\r
+/* PE.1 MFP */\r
+#define SYS_GPE_MFPL_PE1MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for GPIO */\r
+#define SYS_GPE_MFPL_PE1MFP_EBI_AD10 (0x02UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for EBI_AD10 */\r
+#define SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0 (0x03UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for QSPI0_MISO0 */\r
+#define SYS_GPE_MFPL_PE1MFP_SC2_DAT (0x04UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for SC2_DAT */\r
+#define SYS_GPE_MFPL_PE1MFP_I2S0_BCLK (0x05UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for I2S0_BCLK */\r
+#define SYS_GPE_MFPL_PE1MFP_SPI1_MISO (0x06UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for SPI1_MISO */\r
+#define SYS_GPE_MFPL_PE1MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for UART3_TXD */\r
+#define SYS_GPE_MFPL_PE1MFP_I2C1_SCL (0x08UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for I2C1_SCL */\r
+#define SYS_GPE_MFPL_PE1MFP_UART4_nCTS (0x09UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for UART4_nCTS */\r
+\r
+/* PE.2 MFP */\r
+#define SYS_GPE_MFPL_PE2MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for GPIO */\r
+#define SYS_GPE_MFPL_PE2MFP_EBI_ALE (0x02UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for EBI_ALE */\r
+#define SYS_GPE_MFPL_PE2MFP_SD0_DAT0 (0x03UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SD0_DAT0 */\r
+#define SYS_GPE_MFPL_PE2MFP_SPI3_MOSI (0x05UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SPI3_MOSI */\r
+#define SYS_GPE_MFPL_PE2MFP_SC0_CLK (0x06UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SC0_CLK */\r
+#define SYS_GPE_MFPL_PE2MFP_USCI0_CLK (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for USCI0_CLK */\r
+#define SYS_GPE_MFPL_PE2MFP_QEI0_B (0x0bUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for QEI0_B */\r
+#define SYS_GPE_MFPL_PE2MFP_EPWM0_CH5 (0x0cUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for EPWM0_CH5 */\r
+#define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0 (0x0dUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for BPWM0_CH0 */\r
+\r
+/* PE.3 MFP */\r
+#define SYS_GPE_MFPL_PE3MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for GPIO */\r
+#define SYS_GPE_MFPL_PE3MFP_EBI_MCLK (0x02UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for EBI_MCLK */\r
+#define SYS_GPE_MFPL_PE3MFP_SD0_DAT1 (0x03UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SD0_DAT1 */\r
+#define SYS_GPE_MFPL_PE3MFP_SPI3_MISO (0x05UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SPI3_MISO */\r
+#define SYS_GPE_MFPL_PE3MFP_SC0_DAT (0x06UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SC0_DAT */\r
+#define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0 (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for USCI0_DAT0 */\r
+#define SYS_GPE_MFPL_PE3MFP_QEI0_A (0x0bUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for QEI0_A */\r
+#define SYS_GPE_MFPL_PE3MFP_EPWM0_CH4 (0x0cUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for EPWM0_CH4 */\r
+#define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1 (0x0dUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for BPWM0_CH1 */\r
+\r
+/* PE.4 MFP */\r
+#define SYS_GPE_MFPL_PE4MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for GPIO */\r
+#define SYS_GPE_MFPL_PE4MFP_EBI_nWR (0x02UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EBI_nWR */\r
+#define SYS_GPE_MFPL_PE4MFP_SD0_DAT2 (0x03UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SD0_DAT2 */\r
+#define SYS_GPE_MFPL_PE4MFP_SPI3_CLK (0x05UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SPI3_CLK */\r
+#define SYS_GPE_MFPL_PE4MFP_SC0_RST (0x06UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SC0_RST */\r
+#define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1 (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for USCI0_DAT1 */\r
+#define SYS_GPE_MFPL_PE4MFP_QEI0_INDEX (0x0bUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for QEI0_INDEX */\r
+#define SYS_GPE_MFPL_PE4MFP_EPWM0_CH3 (0x0cUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EPWM0_CH3 */\r
+#define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2 (0x0dUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for BPWM0_CH2 */\r
+\r
+/* PE.5 MFP */\r
+#define SYS_GPE_MFPL_PE5MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for GPIO */\r
+#define SYS_GPE_MFPL_PE5MFP_EBI_nRD (0x02UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EBI_nRD */\r
+#define SYS_GPE_MFPL_PE5MFP_SD0_DAT3 (0x03UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SD0_DAT3 */\r
+#define SYS_GPE_MFPL_PE5MFP_SPI3_SS (0x05UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SPI3_SS */\r
+#define SYS_GPE_MFPL_PE5MFP_SC0_PWR (0x06UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SC0_PWR */\r
+#define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1 (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for USCI0_CTL1 */\r
+#define SYS_GPE_MFPL_PE5MFP_QEI1_B (0x0bUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for QEI1_B */\r
+#define SYS_GPE_MFPL_PE5MFP_EPWM0_CH2 (0x0cUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EPWM0_CH2 */\r
+#define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3 (0x0dUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for BPWM0_CH3 */\r
+\r
+/* PE.6 MFP */\r
+#define SYS_GPE_MFPL_PE6MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for GPIO */\r
+#define SYS_GPE_MFPL_PE6MFP_SD0_CLK (0x03UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SD0_CLK */\r
+#define SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK (0x05UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SPI3_I2SMCLK*/\r
+#define SYS_GPE_MFPL_PE6MFP_SC0_nCD (0x06UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SC0_nCD */\r
+#define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0 (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for USCI0_CTL0 */\r
+#define SYS_GPE_MFPL_PE6MFP_UART5_RXD (0x08UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for UART5_RXD */\r
+#define SYS_GPE_MFPL_PE6MFP_QEI1_A (0x0bUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for QEI1_A */\r
+#define SYS_GPE_MFPL_PE6MFP_EPWM0_CH1 (0x0cUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for EPWM0_CH1 */\r
+#define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4 (0x0dUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for BPWM0_CH4 */\r
+\r
+/* PE.7 MFP */\r
+#define SYS_GPE_MFPL_PE7MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for GPIO */\r
+#define SYS_GPE_MFPL_PE7MFP_SD0_CMD (0x03UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for SD0_CMD */\r
+#define SYS_GPE_MFPL_PE7MFP_UART5_TXD (0x08UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for UART5_TXD */\r
+#define SYS_GPE_MFPL_PE7MFP_QEI1_INDEX (0x0bUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for QEI1_INDEX */\r
+#define SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 (0x0cUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for EPWM0_CH0 */\r
+#define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5 (0x0dUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for BPWM0_CH5 */\r
+\r
+/* PE.8 MFP */\r
+#define SYS_GPE_MFPH_PE8MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for GPIO */\r
+#define SYS_GPE_MFPH_PE8MFP_EBI_ADR10 (0x02UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EBI_ADR10 */\r
+#define SYS_GPE_MFPH_PE8MFP_I2S0_BCLK (0x04UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for I2S0_BCLK */\r
+#define SYS_GPE_MFPH_PE8MFP_SPI2_CLK (0x05UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SPI2_CLK */\r
+#define SYS_GPE_MFPH_PE8MFP_USCI1_CTL1 (0x06UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for USCI1_CTL1 */\r
+#define SYS_GPE_MFPH_PE8MFP_UART2_TXD (0x07UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for UART2_TXD */\r
+#define SYS_GPE_MFPH_PE8MFP_EPWM0_CH0 (0x0aUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EPWM0_CH0 */\r
+#define SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0 (0x0bUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EPWM0_BRAKE0*/\r
+#define SYS_GPE_MFPH_PE8MFP_ECAP0_IC0 (0x0cUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for ECAP0_IC0 */\r
+#define SYS_GPE_MFPH_PE8MFP_TRACE_DATA3 (0x0eUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for TRACE_DATA3 */\r
+\r
+/* PE.9 MFP */\r
+#define SYS_GPE_MFPH_PE9MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for GPIO */\r
+#define SYS_GPE_MFPH_PE9MFP_EBI_ADR11 (0x02UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EBI_ADR11 */\r
+#define SYS_GPE_MFPH_PE9MFP_I2S0_MCLK (0x04UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for I2S0_MCLK */\r
+#define SYS_GPE_MFPH_PE9MFP_SPI2_MISO (0x05UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SPI2_MISO */\r
+#define SYS_GPE_MFPH_PE9MFP_USCI1_CTL0 (0x06UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for USCI1_CTL0 */\r
+#define SYS_GPE_MFPH_PE9MFP_UART2_RXD (0x07UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for UART2_RXD */\r
+#define SYS_GPE_MFPH_PE9MFP_EPWM0_CH1 (0x0aUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EPWM0_CH1 */\r
+#define SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1 (0x0bUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EPWM0_BRAKE1*/\r
+#define SYS_GPE_MFPH_PE9MFP_ECAP0_IC1 (0x0cUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for ECAP0_IC1 */\r
+#define SYS_GPE_MFPH_PE9MFP_TRACE_DATA2 (0x0eUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for TRACE_DATA2 */\r
+\r
+/* PE.10 MFP */\r
+#define SYS_GPE_MFPH_PE10MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for GPIO */\r
+#define SYS_GPE_MFPH_PE10MFP_EBI_ADR12 (0x02UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for EBI_ADR12 */\r
+#define SYS_GPE_MFPH_PE10MFP_I2S0_DI (0x04UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for I2S0_DI */\r
+#define SYS_GPE_MFPH_PE10MFP_SPI2_MOSI (0x05UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for SPI2_MOSI */\r
+#define SYS_GPE_MFPH_PE10MFP_USCI1_DAT0 (0x06UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for USCI1_DAT0 */\r
+#define SYS_GPE_MFPH_PE10MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for UART3_TXD */\r
+#define SYS_GPE_MFPH_PE10MFP_EPWM0_CH2 (0x0aUL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for EPWM0_CH2 */\r
+#define SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0 (0x0bUL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for EPWM1_BRAKE0*/\r
+#define SYS_GPE_MFPH_PE10MFP_ECAP0_IC2 (0x0cUL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for ECAP0_IC2 */\r
+#define SYS_GPE_MFPH_PE10MFP_TRACE_DATA1 (0x0eUL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for TRACE_DATA1*/\r
+\r
+/* PE.11 MFP */\r
+#define SYS_GPE_MFPH_PE11MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for GPIO */\r
+#define SYS_GPE_MFPH_PE11MFP_EBI_ADR13 (0x02UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for EBI_ADR13 */\r
+#define SYS_GPE_MFPH_PE11MFP_I2S0_DO (0x04UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for I2S0_DO */\r
+#define SYS_GPE_MFPH_PE11MFP_SPI2_SS (0x05UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for SPI2_SS */\r
+#define SYS_GPE_MFPH_PE11MFP_USCI1_DAT1 (0x06UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for USCI1_DAT1 */\r
+#define SYS_GPE_MFPH_PE11MFP_UART3_RXD (0x07UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for UART3_RXD */\r
+#define SYS_GPE_MFPH_PE11MFP_UART1_nCTS (0x08UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for UART1_nCTS */\r
+#define SYS_GPE_MFPH_PE11MFP_EPWM0_CH3 (0x0aUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for EPWM0_CH3 */\r
+#define SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1 (0x0bUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for EPWM1_BRAKE1*/\r
+#define SYS_GPE_MFPH_PE11MFP_ECAP1_IC2 (0x0dUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for ECAP1_IC2 */\r
+#define SYS_GPE_MFPH_PE11MFP_TRACE_DATA0 (0x0eUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for TRACE_DATA0*/\r
+\r
+/* PE.12 MFP */\r
+#define SYS_GPE_MFPH_PE12MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for GPIO */\r
+#define SYS_GPE_MFPH_PE12MFP_EBI_ADR14 (0x02UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for EBI_ADR14 */\r
+#define SYS_GPE_MFPH_PE12MFP_I2S0_LRCK (0x04UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for I2S0_LRCK */\r
+#define SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK (0x05UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for SPI2_I2SMCLK*/\r
+#define SYS_GPE_MFPH_PE12MFP_USCI1_CLK (0x06UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for USCI1_CLK */\r
+#define SYS_GPE_MFPH_PE12MFP_UART1_nRTS (0x08UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for UART1_nRTS */\r
+#define SYS_GPE_MFPH_PE12MFP_EPWM0_CH4 (0x0aUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for EPWM0_CH4 */\r
+#define SYS_GPE_MFPH_PE12MFP_ECAP1_IC1 (0x0dUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for ECAP1_IC1 */\r
+#define SYS_GPE_MFPH_PE12MFP_TRACE_CLK (0x0eUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for TRACE_CLK */\r
+\r
+/* PE.13 MFP */\r
+#define SYS_GPE_MFPH_PE13MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for GPIO */\r
+#define SYS_GPE_MFPH_PE13MFP_EBI_ADR15 (0x02UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for EBI_ADR15 */\r
+#define SYS_GPE_MFPH_PE13MFP_I2C0_SCL (0x04UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for I2C0_SCL */\r
+#define SYS_GPE_MFPH_PE13MFP_UART4_nRTS (0x05UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for UART4_nRTS */\r
+#define SYS_GPE_MFPH_PE13MFP_UART1_TXD (0x08UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for UART1_TXD */\r
+#define SYS_GPE_MFPH_PE13MFP_EPWM0_CH5 (0x0aUL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for EPWM0_CH5 */\r
+#define SYS_GPE_MFPH_PE13MFP_EPWM1_CH0 (0x0bUL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for EPWM1_CH0 */\r
+#define SYS_GPE_MFPH_PE13MFP_BPWM1_CH5 (0x0cUL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for BPWM1_CH5 */\r
+#define SYS_GPE_MFPH_PE13MFP_ECAP1_IC0 (0x0dUL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for ECAP1_IC0 */\r
+\r
+/* PE.14 MFP */\r
+#define SYS_GPE_MFPH_PE14MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE14MFP_Pos)/*!< GPE_MFPH PE14 setting for GPIO */\r
+#define SYS_GPE_MFPH_PE14MFP_EBI_AD8 (0x02UL<<SYS_GPE_MFPH_PE14MFP_Pos)/*!< GPE_MFPH PE14 setting for EBI_AD8 */\r
+#define SYS_GPE_MFPH_PE14MFP_UART2_TXD (0x03UL<<SYS_GPE_MFPH_PE14MFP_Pos)/*!< GPE_MFPH PE14 setting for UART2_TXD */\r
+#define SYS_GPE_MFPH_PE14MFP_CAN0_TXD (0x04UL<<SYS_GPE_MFPH_PE14MFP_Pos)/*!< GPE_MFPH PE14 setting for CAN0_TXD */\r
+\r
+/* PE.15 MFP */\r
+#define SYS_GPE_MFPH_PE15MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE15MFP_Pos)/*!< GPE_MFPH PE15 setting for GPIO */\r
+#define SYS_GPE_MFPH_PE15MFP_EBI_AD9 (0x02UL<<SYS_GPE_MFPH_PE15MFP_Pos)/*!< GPE_MFPH PE15 setting for EBI_AD9 */\r
+#define SYS_GPE_MFPH_PE15MFP_UART2_RXD (0x03UL<<SYS_GPE_MFPH_PE15MFP_Pos)/*!< GPE_MFPH PE15 setting for UART2_RXD */\r
+#define SYS_GPE_MFPH_PE15MFP_CAN0_RXD (0x04UL<<SYS_GPE_MFPH_PE15MFP_Pos)/*!< GPE_MFPH PE15 setting for CAN0_RXD */\r
+\r
+/* PF.0 MFP */\r
+#define SYS_GPF_MFPL_PF0MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for GPIO */\r
+#define SYS_GPF_MFPL_PF0MFP_UART1_TXD (0x02UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for UART1_TXD */\r
+#define SYS_GPF_MFPL_PF0MFP_I2C1_SCL (0x03UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for I2C1_SCL */\r
+#define SYS_GPF_MFPL_PF0MFP_BPWM1_CH0 (0x0cUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for BPWM1_CH0 */\r
+#define SYS_GPF_MFPL_PF0MFP_ICE_DAT (0x0eUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for ICE_DAT */\r
+\r
+/* PF.1 MFP */\r
+#define SYS_GPF_MFPL_PF1MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for GPIO */\r
+#define SYS_GPF_MFPL_PF1MFP_UART1_RXD (0x02UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for UART1_RXD */\r
+#define SYS_GPF_MFPL_PF1MFP_I2C1_SDA (0x03UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for I2C1_SDA */\r
+#define SYS_GPF_MFPL_PF1MFP_BPWM1_CH1 (0x0cUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for BPWM1_CH1 */\r
+#define SYS_GPF_MFPL_PF1MFP_ICE_CLK (0x0eUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for ICE_CLK */\r
+\r
+/* PF.2 MFP */\r
+#define SYS_GPF_MFPL_PF2MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for GPIO */\r
+#define SYS_GPF_MFPL_PF2MFP_EBI_nCS1 (0x02UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for EBI_nCS1 */\r
+#define SYS_GPF_MFPL_PF2MFP_UART0_RXD (0x03UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for UART0_RXD */\r
+#define SYS_GPF_MFPL_PF2MFP_I2C0_SDA (0x04UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for I2C0_SDA */\r
+#define SYS_GPF_MFPL_PF2MFP_QSPI0_CLK (0x05UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for QSPI0_CLK */\r
+#define SYS_GPF_MFPL_PF2MFP_XT1_OUT (0x0aUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for XT1_OUT */\r
+#define SYS_GPF_MFPL_PF2MFP_BPWM1_CH1 (0x0bUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for BPWM1_CH1 */\r
+\r
+/* PF.3 MFP */\r
+#define SYS_GPF_MFPL_PF3MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for GPIO */\r
+#define SYS_GPF_MFPL_PF3MFP_EBI_nCS0 (0x02UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for EBI_nCS0 */\r
+#define SYS_GPF_MFPL_PF3MFP_UART0_TXD (0x03UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for UART0_TXD */\r
+#define SYS_GPF_MFPL_PF3MFP_I2C0_SCL (0x04UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for I2C0_SCL */\r
+#define SYS_GPF_MFPL_PF3MFP_XT1_IN (0x0aUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for XT1_IN */\r
+#define SYS_GPF_MFPL_PF3MFP_BPWM1_CH0 (0x0bUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for BPWM1_CH0 */\r
+\r
+/* PF.4 MFP */\r
+#define SYS_GPF_MFPL_PF4MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for GPIO */\r
+#define SYS_GPF_MFPL_PF4MFP_UART2_TXD (0x02UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for UART2_TXD */\r
+#define SYS_GPF_MFPL_PF4MFP_UART2_nRTS (0x04UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for UART2_nRTS */\r
+#define SYS_GPF_MFPL_PF4MFP_BPWM0_CH5 (0x08UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for BPWM0_CH5 */\r
+#define SYS_GPF_MFPL_PF4MFP_X32_OUT (0x0aUL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for X32_OUT */\r
+\r
+/* PF.5 MFP */\r
+#define SYS_GPF_MFPL_PF5MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for GPIO */\r
+#define SYS_GPF_MFPL_PF5MFP_UART2_RXD (0x02UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for UART2_RXD */\r
+#define SYS_GPF_MFPL_PF5MFP_UART2_nCTS (0x04UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for UART2_nCTS */\r
+#define SYS_GPF_MFPL_PF5MFP_BPWM0_CH4 (0x08UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for BPWM0_CH4 */\r
+#define SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT (0x09UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for EPWM0_SYNC_OUT*/\r
+#define SYS_GPF_MFPL_PF5MFP_X32_IN (0x0aUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for X32_IN */\r
+#define SYS_GPF_MFPL_PF5MFP_EADC0_ST (0x0bUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for EADC0_ST */\r
+\r
+/* PF.6 MFP */\r
+#define SYS_GPF_MFPL_PF6MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for GPIO */\r
+#define SYS_GPF_MFPL_PF6MFP_EBI_ADR19 (0x02UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for EBI_ADR19 */\r
+#define SYS_GPF_MFPL_PF6MFP_SC0_CLK (0x03UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for SC0_CLK */\r
+#define SYS_GPF_MFPL_PF6MFP_I2S0_LRCK (0x04UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for I2S0_LRCK */\r
+#define SYS_GPF_MFPL_PF6MFP_SPI0_MOSI (0x05UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for SPI0_MOSI */\r
+#define SYS_GPF_MFPL_PF6MFP_UART4_RXD (0x06UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for UART4_RXD */\r
+#define SYS_GPF_MFPL_PF6MFP_EBI_nCS0 (0x07UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for EBI_nCS0 */\r
+#define SYS_GPF_MFPL_PF6MFP_TAMPER0 (0x0aUL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for TAMPER0 */\r
+\r
+/* PF.7 MFP */\r
+#define SYS_GPF_MFPL_PF7MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for GPIO */\r
+#define SYS_GPF_MFPL_PF7MFP_EBI_ADR18 (0x02UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for EBI_ADR18 */\r
+#define SYS_GPF_MFPL_PF7MFP_SC0_DAT (0x03UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for SC0_DAT */\r
+#define SYS_GPF_MFPL_PF7MFP_I2S0_DO (0x04UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for I2S0_DO */\r
+#define SYS_GPF_MFPL_PF7MFP_SPI0_MISO (0x05UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for SPI0_MISO */\r
+#define SYS_GPF_MFPL_PF7MFP_UART4_TXD (0x06UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for UART4_TXD */\r
+#define SYS_GPF_MFPL_PF7MFP_TAMPER1 (0x0aUL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for TAMPER1 */\r
+\r
+/* PF.8 MFP */\r
+#define SYS_GPF_MFPH_PF8MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for GPIO */\r
+#define SYS_GPF_MFPH_PF8MFP_EBI_ADR17 (0x02UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for EBI_ADR17 */\r
+#define SYS_GPF_MFPH_PF8MFP_SC0_RST (0x03UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for SC0_RST */\r
+#define SYS_GPF_MFPH_PF8MFP_I2S0_DI (0x04UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for I2S0_DI */\r
+#define SYS_GPF_MFPH_PF8MFP_SPI0_CLK (0x05UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for SPI0_CLK */\r
+#define SYS_GPF_MFPH_PF8MFP_TAMPER2 (0x0aUL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for TAMPER2 */\r
+\r
+/* PF.9 MFP */\r
+#define SYS_GPF_MFPH_PF9MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for GPIO */\r
+#define SYS_GPF_MFPH_PF9MFP_EBI_ADR16 (0x02UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for EBI_ADR16 */\r
+#define SYS_GPF_MFPH_PF9MFP_SC0_PWR (0x03UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for SC0_PWR */\r
+#define SYS_GPF_MFPH_PF9MFP_I2S0_MCLK (0x04UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for I2S0_MCLK */\r
+#define SYS_GPF_MFPH_PF9MFP_SPI0_SS (0x05UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for SPI0_SS */\r
+#define SYS_GPF_MFPH_PF9MFP_TAMPER3 (0x0aUL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for TAMPER3 */\r
+\r
+/* PF.10 MFP */\r
+#define SYS_GPF_MFPH_PF10MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for GPIO */\r
+#define SYS_GPF_MFPH_PF10MFP_EBI_ADR15 (0x02UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for EBI_ADR15 */\r
+#define SYS_GPF_MFPH_PF10MFP_SC0_nCD (0x03UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for SC0_nCD */\r
+#define SYS_GPF_MFPH_PF10MFP_I2S0_BCLK (0x04UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for I2S0_BCLK */\r
+#define SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK (0x05UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for SPI0_I2SMCLK*/\r
+#define SYS_GPF_MFPH_PF10MFP_TAMPER4 (0x0aUL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for TAMPER4 */\r
+\r
+/* PF.11 MFP */\r
+#define SYS_GPF_MFPH_PF11MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for GPIO */\r
+#define SYS_GPF_MFPH_PF11MFP_EBI_ADR14 (0x02UL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for EBI_ADR14 */\r
+#define SYS_GPF_MFPH_PF11MFP_SPI2_MOSI (0x03UL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for SPI2_MOSI */\r
+#define SYS_GPF_MFPH_PF11MFP_TAMPER5 (0x0aUL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for TAMPER5 */\r
+#define SYS_GPF_MFPH_PF11MFP_TM3 (0x0dUL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for TM3 */\r
+\r
+/* PG.2 MFP */\r
+#define SYS_GPG_MFPL_PG2MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for GPIO */\r
+#define SYS_GPG_MFPL_PG2MFP_EBI_ADR11 (0x02UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for EBI_ADR11 */\r
+#define SYS_GPG_MFPL_PG2MFP_SPI2_SS (0x03UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for SPI2_SS */\r
+#define SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL (0x04UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for I2C0_SMBAL */\r
+#define SYS_GPG_MFPL_PG2MFP_I2C1_SCL (0x05UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for I2C1_SCL */\r
+#define SYS_GPG_MFPL_PG2MFP_TM0 (0x0dUL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for TM0 */\r
+\r
+/* PG.3 MFP */\r
+#define SYS_GPG_MFPL_PG3MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for GPIO */\r
+#define SYS_GPG_MFPL_PG3MFP_EBI_ADR12 (0x02UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for EBI_ADR12 */\r
+#define SYS_GPG_MFPL_PG3MFP_SPI2_CLK (0x03UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for SPI2_CLK */\r
+#define SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS (0x04UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for I2C0_SMBSUS */\r
+#define SYS_GPG_MFPL_PG3MFP_I2C1_SDA (0x05UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for I2C1_SDA */\r
+#define SYS_GPG_MFPL_PG3MFP_TM1 (0x0dUL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for TM1 */\r
+\r
+/* PG.4 MFP */\r
+#define SYS_GPG_MFPL_PG4MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for GPIO */\r
+#define SYS_GPG_MFPL_PG4MFP_EBI_ADR13 (0x02UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for EBI_ADR13 */\r
+#define SYS_GPG_MFPL_PG4MFP_SPI2_MISO (0x03UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for SPI2_MISO */\r
+#define SYS_GPG_MFPL_PG4MFP_TM2 (0x0dUL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for TM2 */\r
+\r
+/* PG.9 MFP */\r
+#define SYS_GPG_MFPH_PG9MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for GPIO */\r
+#define SYS_GPG_MFPH_PG9MFP_EBI_AD0 (0x02UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for EBI_AD0 */\r
+#define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5 (0x0cUL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for BPWM0_CH5 */\r
+\r
+/* PG.10 MFP */\r
+#define SYS_GPG_MFPH_PG10MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for GPIO */\r
+#define SYS_GPG_MFPH_PG10MFP_EBI_AD1 (0x02UL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for EBI_AD1 */\r
+#define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4 (0x0cUL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for BPWM0_CH4 */\r
+\r
+/* PG.11 MFP */\r
+#define SYS_GPG_MFPH_PG11MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for GPIO */\r
+#define SYS_GPG_MFPH_PG11MFP_EBI_AD2 (0x02UL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for EBI_AD2 */\r
+#define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3 (0x0cUL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for BPWM0_CH3 */\r
+\r
+/* PG.12 MFP */\r
+#define SYS_GPG_MFPH_PG12MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for GPIO */\r
+#define SYS_GPG_MFPH_PG12MFP_EBI_AD3 (0x02UL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for EBI_AD3 */\r
+#define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2 (0x0cUL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for BPWM0_CH2 */\r
+\r
+/* PG.13 MFP */\r
+#define SYS_GPG_MFPH_PG13MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for GPIO */\r
+#define SYS_GPG_MFPH_PG13MFP_EBI_AD4 (0x02UL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for EBI_AD4 */\r
+#define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1 (0x0cUL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for BPWM0_CH1 */\r
+\r
+/* PG.14 MFP */\r
+#define SYS_GPG_MFPH_PG14MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for GPIO */\r
+#define SYS_GPG_MFPH_PG14MFP_EBI_AD5 (0x02UL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for EBI_AD5 */\r
+#define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0 (0x0cUL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for BPWM0_CH0 */\r
+\r
+/* PG.15 MFP */\r
+#define SYS_GPG_MFPH_PG15MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for GPIO */\r
+#define SYS_GPG_MFPH_PG15MFP_CLKO (0x0eUL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for CLKO */\r
+#define SYS_GPG_MFPH_PG15MFP_EADC0_ST (0x0fUL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for EADC0_ST */\r
+\r
+/* PH.4 MFP */\r
+#define SYS_GPH_MFPL_PH4MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for GPIO */\r
+#define SYS_GPH_MFPL_PH4MFP_EBI_ADR3 (0x02UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for EBI_ADR3 */\r
+#define SYS_GPH_MFPL_PH4MFP_SPI1_MISO (0x03UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for SPI1_MISO */\r
+\r
+/* PH.5 MFP */\r
+#define SYS_GPH_MFPL_PH5MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for GPIO */\r
+#define SYS_GPH_MFPL_PH5MFP_EBI_ADR2 (0x02UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for EBI_ADR2 */\r
+#define SYS_GPH_MFPL_PH5MFP_SPI1_MOSI (0x03UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for SPI1_MOSI */\r
+\r
+/* PH.6 MFP */\r
+#define SYS_GPH_MFPL_PH6MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for GPIO */\r
+#define SYS_GPH_MFPL_PH6MFP_EBI_ADR1 (0x02UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for EBI_ADR1 */\r
+#define SYS_GPH_MFPL_PH6MFP_SPI1_CLK (0x03UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for SPI1_CLK */\r
+\r
+/* PH.7 MFP */\r
+#define SYS_GPH_MFPL_PH7MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for GPIO */\r
+#define SYS_GPH_MFPL_PH7MFP_EBI_ADR0 (0x02UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for EBI_ADR0 */\r
+#define SYS_GPH_MFPL_PH7MFP_SPI1_SS (0x03UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for SPI1_SS */\r
+\r
+/* PH.8 MFP */\r
+#define SYS_GPH_MFPH_PH8MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for GPIO */\r
+#define SYS_GPH_MFPH_PH8MFP_EBI_AD12 (0x02UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for EBI_AD12 */\r
+#define SYS_GPH_MFPH_PH8MFP_QSPI0_CLK (0x03UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for QSPI0_CLK */\r
+#define SYS_GPH_MFPH_PH8MFP_SC2_PWR (0x04UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for SC2_PWR */\r
+#define SYS_GPH_MFPH_PH8MFP_I2S0_DI (0x05UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for I2S0_DI */\r
+#define SYS_GPH_MFPH_PH8MFP_SPI1_CLK (0x06UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for SPI1_CLK */\r
+#define SYS_GPH_MFPH_PH8MFP_UART3_nRTS (0x07UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for UART3_nRTS */\r
+#define SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL (0x08UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for I2C1_SMBAL */\r
+#define SYS_GPH_MFPH_PH8MFP_I2C2_SCL (0x09UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for I2C2_SCL */\r
+#define SYS_GPH_MFPH_PH8MFP_UART1_TXD (0x0aUL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for UART1_TXD */\r
+\r
+/* PH.9 MFP */\r
+#define SYS_GPH_MFPH_PH9MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for GPIO */\r
+#define SYS_GPH_MFPH_PH9MFP_EBI_AD13 (0x02UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for EBI_AD13 */\r
+#define SYS_GPH_MFPH_PH9MFP_QSPI0_SS (0x03UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for QSPI0_SS */\r
+#define SYS_GPH_MFPH_PH9MFP_SC2_RST (0x04UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for SC2_RST */\r
+#define SYS_GPH_MFPH_PH9MFP_I2S0_DO (0x05UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for I2S0_DO */\r
+#define SYS_GPH_MFPH_PH9MFP_SPI1_SS (0x06UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for SPI1_SS */\r
+#define SYS_GPH_MFPH_PH9MFP_UART3_nCTS (0x07UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for UART3_nCTS */\r
+#define SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS (0x08UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for I2C1_SMBSUS */\r
+#define SYS_GPH_MFPH_PH9MFP_I2C2_SDA (0x09UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for I2C2_SDA */\r
+#define SYS_GPH_MFPH_PH9MFP_UART1_RXD (0x0aUL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for UART1_RXD */\r
+\r
+/* PH.10 MFP */\r
+#define SYS_GPH_MFPH_PH10MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for GPIO */\r
+#define SYS_GPH_MFPH_PH10MFP_EBI_AD14 (0x02UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for EBI_AD14 */\r
+#define SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1 (0x03UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for QSPI0_MISO1*/\r
+#define SYS_GPH_MFPH_PH10MFP_SC2_nCD (0x04UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for SC2_nCD */\r
+#define SYS_GPH_MFPH_PH10MFP_I2S0_LRCK (0x05UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for I2S0_LRCK */\r
+#define SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK (0x06UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for SPI1_I2SMCLK*/\r
+#define SYS_GPH_MFPH_PH10MFP_UART4_TXD (0x07UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for UART4_TXD */\r
+#define SYS_GPH_MFPH_PH10MFP_UART0_TXD (0x08UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for UART0_TXD */\r
+\r
+/* PH.11 MFP */\r
+#define SYS_GPH_MFPH_PH11MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for GPIO */\r
+#define SYS_GPH_MFPH_PH11MFP_EBI_AD15 (0x02UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for EBI_AD15 */\r
+#define SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1 (0x03UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for QSPI0_MOSI1*/\r
+#define SYS_GPH_MFPH_PH11MFP_UART4_RXD (0x07UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for UART4_RXD */\r
+#define SYS_GPH_MFPH_PH11MFP_UART0_RXD (0x08UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for UART0_RXD */\r
+#define SYS_GPH_MFPH_PH11MFP_EPWM0_CH5 (0x0bUL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for EPWM0_CH5 */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Multi-Function setting constant definitions abbreviation. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+\r
+#define ACMP0_N_PB3 SYS_GPB_MFPL_PB3MFP_ACMP0_N /*!< GPB_MFPL PB3 setting for ACMP0_N*/\r
+#define ACMP0_O_PB7 SYS_GPB_MFPL_PB7MFP_ACMP0_O /*!< GPB_MFPL PB7 setting for ACMP0_O*/\r
+#define ACMP0_O_PC1 SYS_GPC_MFPL_PC1MFP_ACMP0_O /*!< GPC_MFPL PC1 setting for ACMP0_O*/\r
+#define ACMP0_O_PC12 SYS_GPC_MFPH_PC12MFP_ACMP0_O /*!< GPC_MFPH PC12 setting for ACMP0_O*/\r
+#define ACMP0_P0_PA11 SYS_GPA_MFPH_PA11MFP_ACMP0_P0 /*!< GPA_MFPH PA11 setting for ACMP0_P0*/\r
+#define ACMP0_P1_PB2 SYS_GPB_MFPL_PB2MFP_ACMP0_P1 /*!< GPB_MFPL PB2 setting for ACMP0_P1*/\r
+#define ACMP0_P2_PB12 SYS_GPB_MFPH_PB12MFP_ACMP0_P2 /*!< GPB_MFPH PB12 setting for ACMP0_P2*/\r
+#define ACMP0_P3_PB13 SYS_GPB_MFPH_PB13MFP_ACMP0_P3 /*!< GPB_MFPH PB13 setting for ACMP0_P3*/\r
+#define ACMP0_WLAT_PA7 SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT /*!< GPA_MFPL PA7 setting for ACMP0_WLAT*/\r
+#define ACMP1_N_PB5 SYS_GPB_MFPL_PB5MFP_ACMP1_N /*!< GPB_MFPL PB5 setting for ACMP1_N*/\r
+#define ACMP1_O_PB6 SYS_GPB_MFPL_PB6MFP_ACMP1_O /*!< GPB_MFPL PB6 setting for ACMP1_O*/\r
+#define ACMP1_O_PC11 SYS_GPC_MFPH_PC11MFP_ACMP1_O /*!< GPC_MFPH PC11 setting for ACMP1_O*/\r
+#define ACMP1_O_PC0 SYS_GPC_MFPL_PC0MFP_ACMP1_O /*!< GPC_MFPL PC0 setting for ACMP1_O*/\r
+#define ACMP1_P0_PA10 SYS_GPA_MFPH_PA10MFP_ACMP1_P0 /*!< GPA_MFPH PA10 setting for ACMP1_P0*/\r
+#define ACMP1_P1_PB4 SYS_GPB_MFPL_PB4MFP_ACMP1_P1 /*!< GPB_MFPL PB4 setting for ACMP1_P1*/\r
+#define ACMP1_P2_PB12 SYS_GPB_MFPH_PB12MFP_ACMP1_P2 /*!< GPB_MFPH PB12 setting for ACMP1_P2*/\r
+#define ACMP1_P3_PB13 SYS_GPB_MFPH_PB13MFP_ACMP1_P3 /*!< GPB_MFPH PB13 setting for ACMP1_P3*/\r
+#define ACMP1_WLAT_PA6 SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT /*!< GPA_MFPL PA6 setting for ACMP1_WLAT*/\r
+#define BPWM0_CH0_PA0 SYS_GPA_MFPL_PA0MFP_BPWM0_CH0 /*!< GPA_MFPL PA0 setting for BPWM0_CH0*/\r
+#define BPWM0_CH0_PA11 SYS_GPA_MFPH_PA11MFP_BPWM0_CH0 /*!< GPA_MFPH PA11 setting for BPWM0_CH0*/\r
+#define BPWM0_CH0_PE2 SYS_GPE_MFPL_PE2MFP_BPWM0_CH0 /*!< GPE_MFPL PE2 setting for BPWM0_CH0*/\r
+#define BPWM0_CH0_PG14 SYS_GPG_MFPH_PG14MFP_BPWM0_CH0 /*!< GPG_MFPH PG14 setting for BPWM0_CH0*/\r
+#define BPWM0_CH1_PA1 SYS_GPA_MFPL_PA1MFP_BPWM0_CH1 /*!< GPA_MFPL PA1 setting for BPWM0_CH1*/\r
+#define BPWM0_CH1_PE3 SYS_GPE_MFPL_PE3MFP_BPWM0_CH1 /*!< GPE_MFPL PE3 setting for BPWM0_CH1*/\r
+#define BPWM0_CH1_PG13 SYS_GPG_MFPH_PG13MFP_BPWM0_CH1 /*!< GPG_MFPH PG13 setting for BPWM0_CH1*/\r
+#define BPWM0_CH1_PA10 SYS_GPA_MFPH_PA10MFP_BPWM0_CH1 /*!< GPA_MFPH PA10 setting for BPWM0_CH1*/\r
+#define BPWM0_CH2_PE4 SYS_GPE_MFPL_PE4MFP_BPWM0_CH2 /*!< GPE_MFPL PE4 setting for BPWM0_CH2*/\r
+#define BPWM0_CH2_PG12 SYS_GPG_MFPH_PG12MFP_BPWM0_CH2 /*!< GPG_MFPH PG12 setting for BPWM0_CH2*/\r
+#define BPWM0_CH2_PA2 SYS_GPA_MFPL_PA2MFP_BPWM0_CH2 /*!< GPA_MFPL PA2 setting for BPWM0_CH2*/\r
+#define BPWM0_CH2_PA9 SYS_GPA_MFPH_PA9MFP_BPWM0_CH2 /*!< GPA_MFPH PA9 setting for BPWM0_CH2*/\r
+#define BPWM0_CH3_PG11 SYS_GPG_MFPH_PG11MFP_BPWM0_CH3 /*!< GPG_MFPH PG11 setting for BPWM0_CH3*/\r
+#define BPWM0_CH3_PA3 SYS_GPA_MFPL_PA3MFP_BPWM0_CH3 /*!< GPA_MFPL PA3 setting for BPWM0_CH3*/\r
+#define BPWM0_CH3_PA8 SYS_GPA_MFPH_PA8MFP_BPWM0_CH3 /*!< GPA_MFPH PA8 setting for BPWM0_CH3*/\r
+#define BPWM0_CH3_PE5 SYS_GPE_MFPL_PE5MFP_BPWM0_CH3 /*!< GPE_MFPL PE5 setting for BPWM0_CH3*/\r
+#define BPWM0_CH4_PG10 SYS_GPG_MFPH_PG10MFP_BPWM0_CH4 /*!< GPG_MFPH PG10 setting for BPWM0_CH4*/\r
+#define BPWM0_CH4_PA4 SYS_GPA_MFPL_PA4MFP_BPWM0_CH4 /*!< GPA_MFPL PA4 setting for BPWM0_CH4*/\r
+#define BPWM0_CH4_PC13 SYS_GPC_MFPH_PC13MFP_BPWM0_CH4 /*!< GPC_MFPH PC13 setting for BPWM0_CH4*/\r
+#define BPWM0_CH4_PE6 SYS_GPE_MFPL_PE6MFP_BPWM0_CH4 /*!< GPE_MFPL PE6 setting for BPWM0_CH4*/\r
+#define BPWM0_CH4_PF5 SYS_GPF_MFPL_PF5MFP_BPWM0_CH4 /*!< GPF_MFPL PF5 setting for BPWM0_CH4*/\r
+#define BPWM0_CH5_PA5 SYS_GPA_MFPL_PA5MFP_BPWM0_CH5 /*!< GPA_MFPL PA5 setting for BPWM0_CH5*/\r
+#define BPWM0_CH5_PE7 SYS_GPE_MFPL_PE7MFP_BPWM0_CH5 /*!< GPE_MFPL PE7 setting for BPWM0_CH5*/\r
+#define BPWM0_CH5_PF4 SYS_GPF_MFPL_PF4MFP_BPWM0_CH5 /*!< GPF_MFPL PF4 setting for BPWM0_CH5*/\r
+#define BPWM0_CH5_PD12 SYS_GPD_MFPH_PD12MFP_BPWM0_CH5 /*!< GPD_MFPH PD12 setting for BPWM0_CH5*/\r
+#define BPWM0_CH5_PG9 SYS_GPG_MFPH_PG9MFP_BPWM0_CH5 /*!< GPG_MFPH PG9 setting for BPWM0_CH5*/\r
+#define BPWM1_CH0_PB11 SYS_GPB_MFPH_PB11MFP_BPWM1_CH0 /*!< GPB_MFPH PB11 setting for BPWM1_CH0*/\r
+#define BPWM1_CH0_PC7 SYS_GPC_MFPL_PC7MFP_BPWM1_CH0 /*!< GPC_MFPL PC7 setting for BPWM1_CH0*/\r
+#define BPWM1_CH0_PF0 SYS_GPF_MFPL_PF0MFP_BPWM1_CH0 /*!< GPF_MFPL PF0 setting for BPWM1_CH0*/\r
+#define BPWM1_CH0_PF3 SYS_GPF_MFPL_PF3MFP_BPWM1_CH0 /*!< GPF_MFPL PF3 setting for BPWM1_CH0*/\r
+#define BPWM1_CH1_PC6 SYS_GPC_MFPL_PC6MFP_BPWM1_CH1 /*!< GPC_MFPL PC6 setting for BPWM1_CH1*/\r
+#define BPWM1_CH1_PF1 SYS_GPF_MFPL_PF1MFP_BPWM1_CH1 /*!< GPF_MFPL PF1 setting for BPWM1_CH1*/\r
+#define BPWM1_CH1_PF2 SYS_GPF_MFPL_PF2MFP_BPWM1_CH1 /*!< GPF_MFPL PF2 setting for BPWM1_CH1*/\r
+#define BPWM1_CH1_PB10 SYS_GPB_MFPH_PB10MFP_BPWM1_CH1 /*!< GPB_MFPH PB10 setting for BPWM1_CH1*/\r
+#define BPWM1_CH2_PB9 SYS_GPB_MFPH_PB9MFP_BPWM1_CH2 /*!< GPB_MFPH PB9 setting for BPWM1_CH2*/\r
+#define BPWM1_CH2_PA7 SYS_GPA_MFPL_PA7MFP_BPWM1_CH2 /*!< GPA_MFPL PA7 setting for BPWM1_CH2*/\r
+#define BPWM1_CH2_PA12 SYS_GPA_MFPH_PA12MFP_BPWM1_CH2 /*!< GPA_MFPH PA12 setting for BPWM1_CH2*/\r
+#define BPWM1_CH3_PA6 SYS_GPA_MFPL_PA6MFP_BPWM1_CH3 /*!< GPA_MFPL PA6 setting for BPWM1_CH3*/\r
+#define BPWM1_CH3_PA13 SYS_GPA_MFPH_PA13MFP_BPWM1_CH3 /*!< GPA_MFPH PA13 setting for BPWM1_CH3*/\r
+#define BPWM1_CH3_PB8 SYS_GPB_MFPH_PB8MFP_BPWM1_CH3 /*!< GPB_MFPH PB8 setting for BPWM1_CH3*/\r
+#define BPWM1_CH4_PA14 SYS_GPA_MFPH_PA14MFP_BPWM1_CH4 /*!< GPA_MFPH PA14 setting for BPWM1_CH4*/\r
+#define BPWM1_CH4_PC8 SYS_GPC_MFPH_PC8MFP_BPWM1_CH4 /*!< GPC_MFPH PC8 setting for BPWM1_CH4*/\r
+#define BPWM1_CH4_PB7 SYS_GPB_MFPL_PB7MFP_BPWM1_CH4 /*!< GPB_MFPL PB7 setting for BPWM1_CH4*/\r
+#define BPWM1_CH5_PA15 SYS_GPA_MFPH_PA15MFP_BPWM1_CH5 /*!< GPA_MFPH PA15 setting for BPWM1_CH5*/\r
+#define BPWM1_CH5_PB6 SYS_GPB_MFPL_PB6MFP_BPWM1_CH5 /*!< GPB_MFPL PB6 setting for BPWM1_CH5*/\r
+#define BPWM1_CH5_PE13 SYS_GPE_MFPH_PE13MFP_BPWM1_CH5 /*!< GPE_MFPH PE13 setting for BPWM1_CH5*/\r
+#define CAN0_RXD_PA13 SYS_GPA_MFPH_PA13MFP_CAN0_RXD /*!< GPA_MFPH PA13 setting for CAN0_RXD*/\r
+#define CAN0_RXD_PD10 SYS_GPD_MFPH_PD10MFP_CAN0_RXD /*!< GPD_MFPH PD10 setting for CAN0_RXD*/\r
+#define CAN0_RXD_PA4 SYS_GPA_MFPL_PA4MFP_CAN0_RXD /*!< GPA_MFPL PA4 setting for CAN0_RXD*/\r
+#define CAN0_RXD_PC4 SYS_GPC_MFPL_PC4MFP_CAN0_RXD /*!< GPC_MFPL PC4 setting for CAN0_RXD*/\r
+#define CAN0_RXD_PB10 SYS_GPB_MFPH_PB10MFP_CAN0_RXD /*!< GPB_MFPH PB10 setting for CAN0_RXD*/\r
+#define CAN0_RXD_PE15 SYS_GPE_MFPH_PE15MFP_CAN0_RXD /*!< GPE_MFPH PE15 setting for CAN0_RXD*/\r
+#define CAN0_TXD_PD11 SYS_GPD_MFPH_PD11MFP_CAN0_TXD /*!< GPD_MFPH PD11 setting for CAN0_TXD*/\r
+#define CAN0_TXD_PC5 SYS_GPC_MFPL_PC5MFP_CAN0_TXD /*!< GPC_MFPL PC5 setting for CAN0_TXD*/\r
+#define CAN0_TXD_PB11 SYS_GPB_MFPH_PB11MFP_CAN0_TXD /*!< GPB_MFPH PB11 setting for CAN0_TXD*/\r
+#define CAN0_TXD_PA12 SYS_GPA_MFPH_PA12MFP_CAN0_TXD /*!< GPA_MFPH PA12 setting for CAN0_TXD*/\r
+#define CAN0_TXD_PE14 SYS_GPE_MFPH_PE14MFP_CAN0_TXD /*!< GPE_MFPH PE14 setting for CAN0_TXD*/\r
+#define CAN0_TXD_PA5 SYS_GPA_MFPL_PA5MFP_CAN0_TXD /*!< GPA_MFPL PA5 setting for CAN0_TXD*/\r
+#define CLKO_PC13 SYS_GPC_MFPH_PC13MFP_CLKO /*!< GPC_MFPH PC13 setting for CLKO*/\r
+#define CLKO_PB14 SYS_GPB_MFPH_PB14MFP_CLKO /*!< GPB_MFPH PB14 setting for CLKO*/\r
+#define CLKO_PD12 SYS_GPD_MFPH_PD12MFP_CLKO /*!< GPD_MFPH PD12 setting for CLKO*/\r
+#define CLKO_PG15 SYS_GPG_MFPH_PG15MFP_CLKO /*!< GPG_MFPH PG15 setting for CLKO*/\r
+#define DAC0_OUT_PB12 SYS_GPB_MFPH_PB12MFP_DAC0_OUT /*!< GPB_MFPH PB12 setting for DAC0_OUT*/\r
+#define DAC0_ST_PA10 SYS_GPA_MFPH_PA10MFP_DAC0_ST /*!< GPA_MFPH PA10 setting for DAC0_ST*/\r
+#define DAC0_ST_PA0 SYS_GPA_MFPL_PA0MFP_DAC0_ST /*!< GPA_MFPL PA0 setting for DAC0_ST*/\r
+#define DAC1_OUT_PB13 SYS_GPB_MFPH_PB13MFP_DAC1_OUT /*!< GPB_MFPH PB13 setting for DAC1_OUT*/\r
+#define DAC1_ST_PA1 SYS_GPA_MFPL_PA1MFP_DAC1_ST /*!< GPA_MFPL PA1 setting for DAC1_ST*/\r
+#define DAC1_ST_PA11 SYS_GPA_MFPH_PA11MFP_DAC1_ST /*!< GPA_MFPH PA11 setting for DAC1_ST*/\r
+#define EADC0_CH0_PB0 SYS_GPB_MFPL_PB0MFP_EADC0_CH0 /*!< GPB_MFPL PB0 setting for EADC0_CH0*/\r
+#define EADC0_CH1_PB1 SYS_GPB_MFPL_PB1MFP_EADC0_CH1 /*!< GPB_MFPL PB1 setting for EADC0_CH1*/\r
+#define EADC0_CH10_PB10 SYS_GPB_MFPH_PB10MFP_EADC0_CH10 /*!< GPB_MFPH PB10 setting for EADC0_CH10*/\r
+#define EADC0_CH11_PB11 SYS_GPB_MFPH_PB11MFP_EADC0_CH11 /*!< GPB_MFPH PB11 setting for EADC0_CH11*/\r
+#define EADC0_CH12_PB12 SYS_GPB_MFPH_PB12MFP_EADC0_CH12 /*!< GPB_MFPH PB12 setting for EADC0_CH12*/\r
+#define EADC0_CH13_PB13 SYS_GPB_MFPH_PB13MFP_EADC0_CH13 /*!< GPB_MFPH PB13 setting for EADC0_CH13*/\r
+#define EADC0_CH14_PB14 SYS_GPB_MFPH_PB14MFP_EADC0_CH14 /*!< GPB_MFPH PB14 setting for EADC0_CH14*/\r
+#define EADC0_CH15_PB15 SYS_GPB_MFPH_PB15MFP_EADC0_CH15 /*!< GPB_MFPH PB15 setting for EADC0_CH15*/\r
+#define EADC0_CH2_PB2 SYS_GPB_MFPL_PB2MFP_EADC0_CH2 /*!< GPB_MFPL PB2 setting for EADC0_CH2*/\r
+#define EADC0_CH3_PB3 SYS_GPB_MFPL_PB3MFP_EADC0_CH3 /*!< GPB_MFPL PB3 setting for EADC0_CH3*/\r
+#define EADC0_CH4_PB4 SYS_GPB_MFPL_PB4MFP_EADC0_CH4 /*!< GPB_MFPL PB4 setting for EADC0_CH4*/\r
+#define EADC0_CH5_PB5 SYS_GPB_MFPL_PB5MFP_EADC0_CH5 /*!< GPB_MFPL PB5 setting for EADC0_CH5*/\r
+#define EADC0_CH6_PB6 SYS_GPB_MFPL_PB6MFP_EADC0_CH6 /*!< GPB_MFPL PB6 setting for EADC0_CH6*/\r
+#define EADC0_CH7_PB7 SYS_GPB_MFPL_PB7MFP_EADC0_CH7 /*!< GPB_MFPL PB7 setting for EADC0_CH7*/\r
+#define EADC0_CH8_PB8 SYS_GPB_MFPH_PB8MFP_EADC0_CH8 /*!< GPB_MFPH PB8 setting for EADC0_CH8*/\r
+#define EADC0_CH9_PB9 SYS_GPB_MFPH_PB9MFP_EADC0_CH9 /*!< GPB_MFPH PB9 setting for EADC0_CH9*/\r
+#define EADC0_ST_PD12 SYS_GPD_MFPH_PD12MFP_EADC0_ST /*!< GPD_MFPH PD12 setting for EADC0_ST*/\r
+#define EADC0_ST_PF5 SYS_GPF_MFPL_PF5MFP_EADC0_ST /*!< GPF_MFPL PF5 setting for EADC0_ST*/\r
+#define EADC0_ST_PC13 SYS_GPC_MFPH_PC13MFP_EADC0_ST /*!< GPC_MFPH PC13 setting for EADC0_ST*/\r
+#define EADC0_ST_PG15 SYS_GPG_MFPH_PG15MFP_EADC0_ST /*!< GPG_MFPH PG15 setting for EADC0_ST*/\r
+#define EBI_AD0_PG9 SYS_GPG_MFPH_PG9MFP_EBI_AD0 /*!< GPG_MFPH PG9 setting for EBI_AD0*/\r
+#define EBI_AD0_PC0 SYS_GPC_MFPL_PC0MFP_EBI_AD0 /*!< GPC_MFPL PC0 setting for EBI_AD0*/\r
+#define EBI_AD1_PC1 SYS_GPC_MFPL_PC1MFP_EBI_AD1 /*!< GPC_MFPL PC1 setting for EBI_AD1*/\r
+#define EBI_AD1_PG10 SYS_GPG_MFPH_PG10MFP_EBI_AD1 /*!< GPG_MFPH PG10 setting for EBI_AD1*/\r
+#define EBI_AD10_PE1 SYS_GPE_MFPL_PE1MFP_EBI_AD10 /*!< GPE_MFPL PE1 setting for EBI_AD10*/\r
+#define EBI_AD10_PD3 SYS_GPD_MFPL_PD3MFP_EBI_AD10 /*!< GPD_MFPL PD3 setting for EBI_AD10*/\r
+#define EBI_AD10_PD13 SYS_GPD_MFPH_PD13MFP_EBI_AD10 /*!< GPD_MFPH PD13 setting for EBI_AD10*/\r
+#define EBI_AD11_PE0 SYS_GPE_MFPL_PE0MFP_EBI_AD11 /*!< GPE_MFPL PE0 setting for EBI_AD11*/\r
+#define EBI_AD11_PD2 SYS_GPD_MFPL_PD2MFP_EBI_AD11 /*!< GPD_MFPL PD2 setting for EBI_AD11*/\r
+#define EBI_AD12_PD1 SYS_GPD_MFPL_PD1MFP_EBI_AD12 /*!< GPD_MFPL PD1 setting for EBI_AD12*/\r
+#define EBI_AD12_PB15 SYS_GPB_MFPH_PB15MFP_EBI_AD12 /*!< GPB_MFPH PB15 setting for EBI_AD12*/\r
+#define EBI_AD12_PH8 SYS_GPH_MFPH_PH8MFP_EBI_AD12 /*!< GPH_MFPH PH8 setting for EBI_AD12*/\r
+#define EBI_AD13_PD0 SYS_GPD_MFPL_PD0MFP_EBI_AD13 /*!< GPD_MFPL PD0 setting for EBI_AD13*/\r
+#define EBI_AD13_PB14 SYS_GPB_MFPH_PB14MFP_EBI_AD13 /*!< GPB_MFPH PB14 setting for EBI_AD13*/\r
+#define EBI_AD13_PH9 SYS_GPH_MFPH_PH9MFP_EBI_AD13 /*!< GPH_MFPH PH9 setting for EBI_AD13*/\r
+#define EBI_AD14_PB13 SYS_GPB_MFPH_PB13MFP_EBI_AD14 /*!< GPB_MFPH PB13 setting for EBI_AD14*/\r
+#define EBI_AD14_PH10 SYS_GPH_MFPH_PH10MFP_EBI_AD14 /*!< GPH_MFPH PH10 setting for EBI_AD14*/\r
+#define EBI_AD15_PB12 SYS_GPB_MFPH_PB12MFP_EBI_AD15 /*!< GPB_MFPH PB12 setting for EBI_AD15*/\r
+#define EBI_AD15_PH11 SYS_GPH_MFPH_PH11MFP_EBI_AD15 /*!< GPH_MFPH PH11 setting for EBI_AD15*/\r
+#define EBI_AD2_PG11 SYS_GPG_MFPH_PG11MFP_EBI_AD2 /*!< GPG_MFPH PG11 setting for EBI_AD2*/\r
+#define EBI_AD2_PC2 SYS_GPC_MFPL_PC2MFP_EBI_AD2 /*!< GPC_MFPL PC2 setting for EBI_AD2*/\r
+#define EBI_AD3_PC3 SYS_GPC_MFPL_PC3MFP_EBI_AD3 /*!< GPC_MFPL PC3 setting for EBI_AD3*/\r
+#define EBI_AD3_PG12 SYS_GPG_MFPH_PG12MFP_EBI_AD3 /*!< GPG_MFPH PG12 setting for EBI_AD3*/\r
+#define EBI_AD4_PG13 SYS_GPG_MFPH_PG13MFP_EBI_AD4 /*!< GPG_MFPH PG13 setting for EBI_AD4*/\r
+#define EBI_AD4_PC4 SYS_GPC_MFPL_PC4MFP_EBI_AD4 /*!< GPC_MFPL PC4 setting for EBI_AD4*/\r
+#define EBI_AD5_PG14 SYS_GPG_MFPH_PG14MFP_EBI_AD5 /*!< GPG_MFPH PG14 setting for EBI_AD5*/\r
+#define EBI_AD5_PC5 SYS_GPC_MFPL_PC5MFP_EBI_AD5 /*!< GPC_MFPL PC5 setting for EBI_AD5*/\r
+#define EBI_AD6_PD8 SYS_GPD_MFPH_PD8MFP_EBI_AD6 /*!< GPD_MFPH PD8 setting for EBI_AD6*/\r
+#define EBI_AD6_PA6 SYS_GPA_MFPL_PA6MFP_EBI_AD6 /*!< GPA_MFPL PA6 setting for EBI_AD6*/\r
+#define EBI_AD7_PA7 SYS_GPA_MFPL_PA7MFP_EBI_AD7 /*!< GPA_MFPL PA7 setting for EBI_AD7*/\r
+#define EBI_AD7_PD9 SYS_GPD_MFPH_PD9MFP_EBI_AD7 /*!< GPD_MFPH PD9 setting for EBI_AD7*/\r
+#define EBI_AD8_PC6 SYS_GPC_MFPL_PC6MFP_EBI_AD8 /*!< GPC_MFPL PC6 setting for EBI_AD8*/\r
+#define EBI_AD8_PE14 SYS_GPE_MFPH_PE14MFP_EBI_AD8 /*!< GPE_MFPH PE14 setting for EBI_AD8*/\r
+#define EBI_AD9_PE15 SYS_GPE_MFPH_PE15MFP_EBI_AD9 /*!< GPE_MFPH PE15 setting for EBI_AD9*/\r
+#define EBI_AD9_PC7 SYS_GPC_MFPL_PC7MFP_EBI_AD9 /*!< GPC_MFPL PC7 setting for EBI_AD9*/\r
+#define EBI_ADR0_PB5 SYS_GPB_MFPL_PB5MFP_EBI_ADR0 /*!< GPB_MFPL PB5 setting for EBI_ADR0*/\r
+#define EBI_ADR0_PH7 SYS_GPH_MFPL_PH7MFP_EBI_ADR0 /*!< GPH_MFPL PH7 setting for EBI_ADR0*/\r
+#define EBI_ADR1_PH6 SYS_GPH_MFPL_PH6MFP_EBI_ADR1 /*!< GPH_MFPL PH6 setting for EBI_ADR1*/\r
+#define EBI_ADR1_PB4 SYS_GPB_MFPL_PB4MFP_EBI_ADR1 /*!< GPB_MFPL PB4 setting for EBI_ADR1*/\r
+#define EBI_ADR10_PE8 SYS_GPE_MFPH_PE8MFP_EBI_ADR10 /*!< GPE_MFPH PE8 setting for EBI_ADR10*/\r
+#define EBI_ADR10_PC13 SYS_GPC_MFPH_PC13MFP_EBI_ADR10 /*!< GPC_MFPH PC13 setting for EBI_ADR10*/\r
+#define EBI_ADR11_PG2 SYS_GPG_MFPL_PG2MFP_EBI_ADR11 /*!< GPG_MFPL PG2 setting for EBI_ADR11*/\r
+#define EBI_ADR11_PE9 SYS_GPE_MFPH_PE9MFP_EBI_ADR11 /*!< GPE_MFPH PE9 setting for EBI_ADR11*/\r
+#define EBI_ADR12_PG3 SYS_GPG_MFPL_PG3MFP_EBI_ADR12 /*!< GPG_MFPL PG3 setting for EBI_ADR12*/\r
+#define EBI_ADR12_PE10 SYS_GPE_MFPH_PE10MFP_EBI_ADR12 /*!< GPE_MFPH PE10 setting for EBI_ADR12*/\r
+#define EBI_ADR13_PG4 SYS_GPG_MFPL_PG4MFP_EBI_ADR13 /*!< GPG_MFPL PG4 setting for EBI_ADR13*/\r
+#define EBI_ADR13_PE11 SYS_GPE_MFPH_PE11MFP_EBI_ADR13 /*!< GPE_MFPH PE11 setting for EBI_ADR13*/\r
+#define EBI_ADR14_PE12 SYS_GPE_MFPH_PE12MFP_EBI_ADR14 /*!< GPE_MFPH PE12 setting for EBI_ADR14*/\r
+#define EBI_ADR14_PF11 SYS_GPF_MFPH_PF11MFP_EBI_ADR14 /*!< GPF_MFPH PF11 setting for EBI_ADR14*/\r
+#define EBI_ADR15_PF10 SYS_GPF_MFPH_PF10MFP_EBI_ADR15 /*!< GPF_MFPH PF10 setting for EBI_ADR15*/\r
+#define EBI_ADR15_PE13 SYS_GPE_MFPH_PE13MFP_EBI_ADR15 /*!< GPE_MFPH PE13 setting for EBI_ADR15*/\r
+#define EBI_ADR16_PB11 SYS_GPB_MFPH_PB11MFP_EBI_ADR16 /*!< GPB_MFPH PB11 setting for EBI_ADR16*/\r
+#define EBI_ADR16_PF9 SYS_GPF_MFPH_PF9MFP_EBI_ADR16 /*!< GPF_MFPH PF9 setting for EBI_ADR16*/\r
+#define EBI_ADR16_PC8 SYS_GPC_MFPH_PC8MFP_EBI_ADR16 /*!< GPC_MFPH PC8 setting for EBI_ADR16*/\r
+#define EBI_ADR17_PF8 SYS_GPF_MFPH_PF8MFP_EBI_ADR17 /*!< GPF_MFPH PF8 setting for EBI_ADR17*/\r
+#define EBI_ADR17_PB10 SYS_GPB_MFPH_PB10MFP_EBI_ADR17 /*!< GPB_MFPH PB10 setting for EBI_ADR17*/\r
+#define EBI_ADR18_PB9 SYS_GPB_MFPH_PB9MFP_EBI_ADR18 /*!< GPB_MFPH PB9 setting for EBI_ADR18*/\r
+#define EBI_ADR18_PF7 SYS_GPF_MFPL_PF7MFP_EBI_ADR18 /*!< GPF_MFPL PF7 setting for EBI_ADR18*/\r
+#define EBI_ADR19_PF6 SYS_GPF_MFPL_PF6MFP_EBI_ADR19 /*!< GPF_MFPL PF6 setting for EBI_ADR19*/\r
+#define EBI_ADR19_PB8 SYS_GPB_MFPH_PB8MFP_EBI_ADR19 /*!< GPB_MFPH PB8 setting for EBI_ADR19*/\r
+#define EBI_ADR2_PB3 SYS_GPB_MFPL_PB3MFP_EBI_ADR2 /*!< GPB_MFPL PB3 setting for EBI_ADR2*/\r
+#define EBI_ADR2_PH5 SYS_GPH_MFPL_PH5MFP_EBI_ADR2 /*!< GPH_MFPL PH5 setting for EBI_ADR2*/\r
+#define EBI_ADR3_PH4 SYS_GPH_MFPL_PH4MFP_EBI_ADR3 /*!< GPH_MFPL PH4 setting for EBI_ADR3*/\r
+#define EBI_ADR3_PB2 SYS_GPB_MFPL_PB2MFP_EBI_ADR3 /*!< GPB_MFPL PB2 setting for EBI_ADR3*/\r
+#define EBI_ADR4_PC12 SYS_GPC_MFPH_PC12MFP_EBI_ADR4 /*!< GPC_MFPH PC12 setting for EBI_ADR4*/\r
+#define EBI_ADR5_PC11 SYS_GPC_MFPH_PC11MFP_EBI_ADR5 /*!< GPC_MFPH PC11 setting for EBI_ADR5*/\r
+#define EBI_ADR6_PC10 SYS_GPC_MFPH_PC10MFP_EBI_ADR6 /*!< GPC_MFPH PC10 setting for EBI_ADR6*/\r
+#define EBI_ADR7_PC9 SYS_GPC_MFPH_PC9MFP_EBI_ADR7 /*!< GPC_MFPH PC9 setting for EBI_ADR7*/\r
+#define EBI_ADR8_PB1 SYS_GPB_MFPL_PB1MFP_EBI_ADR8 /*!< GPB_MFPL PB1 setting for EBI_ADR8*/\r
+#define EBI_ADR9_PB0 SYS_GPB_MFPL_PB0MFP_EBI_ADR9 /*!< GPB_MFPL PB0 setting for EBI_ADR9*/\r
+#define EBI_ALE_PA8 SYS_GPA_MFPH_PA8MFP_EBI_ALE /*!< GPA_MFPH PA8 setting for EBI_ALE*/\r
+#define EBI_ALE_PE2 SYS_GPE_MFPL_PE2MFP_EBI_ALE /*!< GPE_MFPL PE2 setting for EBI_ALE*/\r
+#define EBI_MCLK_PE3 SYS_GPE_MFPL_PE3MFP_EBI_MCLK /*!< GPE_MFPL PE3 setting for EBI_MCLK*/\r
+#define EBI_MCLK_PA9 SYS_GPA_MFPH_PA9MFP_EBI_MCLK /*!< GPA_MFPH PA9 setting for EBI_MCLK*/\r
+#define EBI_nCS0_PB7 SYS_GPB_MFPL_PB7MFP_EBI_nCS0 /*!< GPB_MFPL PB7 setting for EBI_nCS0*/\r
+#define EBI_nCS0_PF6 SYS_GPF_MFPL_PF6MFP_EBI_nCS0 /*!< GPF_MFPL PF6 setting for EBI_nCS0*/\r
+#define EBI_nCS0_PD12 SYS_GPD_MFPH_PD12MFP_EBI_nCS0 /*!< GPD_MFPH PD12 setting for EBI_nCS0*/\r
+#define EBI_nCS0_PD14 SYS_GPD_MFPH_PD14MFP_EBI_nCS0 /*!< GPD_MFPH PD14 setting for EBI_nCS0*/\r
+#define EBI_nCS0_PF3 SYS_GPF_MFPL_PF3MFP_EBI_nCS0 /*!< GPF_MFPL PF3 setting for EBI_nCS0*/\r
+#define EBI_nCS1_PF2 SYS_GPF_MFPL_PF2MFP_EBI_nCS1 /*!< GPF_MFPL PF2 setting for EBI_nCS1*/\r
+#define EBI_nCS1_PD11 SYS_GPD_MFPH_PD11MFP_EBI_nCS1 /*!< GPD_MFPH PD11 setting for EBI_nCS1*/\r
+#define EBI_nCS1_PB6 SYS_GPB_MFPL_PB6MFP_EBI_nCS1 /*!< GPB_MFPL PB6 setting for EBI_nCS1*/\r
+#define EBI_nCS2_PD10 SYS_GPD_MFPH_PD10MFP_EBI_nCS2 /*!< GPD_MFPH PD10 setting for EBI_nCS2*/\r
+#define EBI_nRD_PA11 SYS_GPA_MFPH_PA11MFP_EBI_nRD /*!< GPA_MFPH PA11 setting for EBI_nRD*/\r
+#define EBI_nRD_PE5 SYS_GPE_MFPL_PE5MFP_EBI_nRD /*!< GPE_MFPL PE5 setting for EBI_nRD*/\r
+#define EBI_nWR_PA10 SYS_GPA_MFPH_PA10MFP_EBI_nWR /*!< GPA_MFPH PA10 setting for EBI_nWR*/\r
+#define EBI_nWR_PE4 SYS_GPE_MFPL_PE4MFP_EBI_nWR /*!< GPE_MFPL PE4 setting for EBI_nWR*/\r
+#define EBI_nWRH_PB6 SYS_GPB_MFPL_PB6MFP_EBI_nWRH /*!< GPB_MFPL PB6 setting for EBI_nWRH*/\r
+#define EBI_nWRL_PB7 SYS_GPB_MFPL_PB7MFP_EBI_nWRL /*!< GPB_MFPL PB7 setting for EBI_nWRL*/\r
+#define ECAP0_IC0_PA10 SYS_GPA_MFPH_PA10MFP_ECAP0_IC0 /*!< GPA_MFPH PA10 setting for ECAP0_IC0*/\r
+#define ECAP0_IC0_PE8 SYS_GPE_MFPH_PE8MFP_ECAP0_IC0 /*!< GPE_MFPH PE8 setting for ECAP0_IC0*/\r
+#define ECAP0_IC1_PE9 SYS_GPE_MFPH_PE9MFP_ECAP0_IC1 /*!< GPE_MFPH PE9 setting for ECAP0_IC1*/\r
+#define ECAP0_IC1_PA9 SYS_GPA_MFPH_PA9MFP_ECAP0_IC1 /*!< GPA_MFPH PA9 setting for ECAP0_IC1*/\r
+#define ECAP0_IC2_PA8 SYS_GPA_MFPH_PA8MFP_ECAP0_IC2 /*!< GPA_MFPH PA8 setting for ECAP0_IC2*/\r
+#define ECAP0_IC2_PE10 SYS_GPE_MFPH_PE10MFP_ECAP0_IC2 /*!< GPE_MFPH PE10 setting for ECAP0_IC2*/\r
+#define ECAP1_IC0_PC10 SYS_GPC_MFPH_PC10MFP_ECAP1_IC0 /*!< GPC_MFPH PC10 setting for ECAP1_IC0*/\r
+#define ECAP1_IC0_PE13 SYS_GPE_MFPH_PE13MFP_ECAP1_IC0 /*!< GPE_MFPH PE13 setting for ECAP1_IC0*/\r
+#define ECAP1_IC1_PE12 SYS_GPE_MFPH_PE12MFP_ECAP1_IC1 /*!< GPE_MFPH PE12 setting for ECAP1_IC1*/\r
+#define ECAP1_IC1_PC11 SYS_GPC_MFPH_PC11MFP_ECAP1_IC1 /*!< GPC_MFPH PC11 setting for ECAP1_IC1*/\r
+#define ECAP1_IC2_PE11 SYS_GPE_MFPH_PE11MFP_ECAP1_IC2 /*!< GPE_MFPH PE11 setting for ECAP1_IC2*/\r
+#define ECAP1_IC2_PC12 SYS_GPC_MFPH_PC12MFP_ECAP1_IC2 /*!< GPC_MFPH PC12 setting for ECAP1_IC2*/\r
+#define I2C0_SCL_PB5 SYS_GPB_MFPL_PB5MFP_I2C0_SCL /*!< GPB_MFPL PB5 setting for I2C0_SCL*/\r
+#define I2C0_SCL_PC1 SYS_GPC_MFPL_PC1MFP_I2C0_SCL /*!< GPC_MFPL PC1 setting for I2C0_SCL*/\r
+#define I2C0_SCL_PF3 SYS_GPF_MFPL_PF3MFP_I2C0_SCL /*!< GPF_MFPL PF3 setting for I2C0_SCL*/\r
+#define I2C0_SCL_PE13 SYS_GPE_MFPH_PE13MFP_I2C0_SCL /*!< GPE_MFPH PE13 setting for I2C0_SCL*/\r
+#define I2C0_SCL_PD7 SYS_GPD_MFPL_PD7MFP_I2C0_SCL /*!< GPD_MFPL PD7 setting for I2C0_SCL*/\r
+#define I2C0_SCL_PA5 SYS_GPA_MFPL_PA5MFP_I2C0_SCL /*!< GPA_MFPL PA5 setting for I2C0_SCL*/\r
+#define I2C0_SCL_PC12 SYS_GPC_MFPH_PC12MFP_I2C0_SCL /*!< GPC_MFPH PC12 setting for I2C0_SCL*/\r
+#define I2C0_SDA_PB4 SYS_GPB_MFPL_PB4MFP_I2C0_SDA /*!< GPB_MFPL PB4 setting for I2C0_SDA*/\r
+#define I2C0_SDA_PC8 SYS_GPC_MFPH_PC8MFP_I2C0_SDA /*!< GPC_MFPH PC8 setting for I2C0_SDA*/\r
+#define I2C0_SDA_PC0 SYS_GPC_MFPL_PC0MFP_I2C0_SDA /*!< GPC_MFPL PC0 setting for I2C0_SDA*/\r
+#define I2C0_SDA_PD6 SYS_GPD_MFPL_PD6MFP_I2C0_SDA /*!< GPD_MFPL PD6 setting for I2C0_SDA*/\r
+#define I2C0_SDA_PC11 SYS_GPC_MFPH_PC11MFP_I2C0_SDA /*!< GPC_MFPH PC11 setting for I2C0_SDA*/\r
+#define I2C0_SDA_PA4 SYS_GPA_MFPL_PA4MFP_I2C0_SDA /*!< GPA_MFPL PA4 setting for I2C0_SDA*/\r
+#define I2C0_SDA_PF2 SYS_GPF_MFPL_PF2MFP_I2C0_SDA /*!< GPF_MFPL PF2 setting for I2C0_SDA*/\r
+#define I2C0_SMBAL_PG2 SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL /*!< GPG_MFPL PG2 setting for I2C0_SMBAL*/\r
+#define I2C0_SMBAL_PC3 SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL /*!< GPC_MFPL PC3 setting for I2C0_SMBAL*/\r
+#define I2C0_SMBSUS_PC2 SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS /*!< GPC_MFPL PC2 setting for I2C0_SMBSUS*/\r
+#define I2C0_SMBSUS_PG3 SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS /*!< GPG_MFPL PG3 setting for I2C0_SMBSUS*/\r
+#define I2C1_SCL_PA3 SYS_GPA_MFPL_PA3MFP_I2C1_SCL /*!< GPA_MFPL PA3 setting for I2C1_SCL*/\r
+#define I2C1_SCL_PG2 SYS_GPG_MFPL_PG2MFP_I2C1_SCL /*!< GPG_MFPL PG2 setting for I2C1_SCL*/\r
+#define I2C1_SCL_PB1 SYS_GPB_MFPL_PB1MFP_I2C1_SCL /*!< GPB_MFPL PB1 setting for I2C1_SCL*/\r
+#define I2C1_SCL_PB11 SYS_GPB_MFPH_PB11MFP_I2C1_SCL /*!< GPB_MFPH PB11 setting for I2C1_SCL*/\r
+#define I2C1_SCL_PD5 SYS_GPD_MFPL_PD5MFP_I2C1_SCL /*!< GPD_MFPL PD5 setting for I2C1_SCL*/\r
+#define I2C1_SCL_PA12 SYS_GPA_MFPH_PA12MFP_I2C1_SCL /*!< GPA_MFPH PA12 setting for I2C1_SCL*/\r
+#define I2C1_SCL_PC5 SYS_GPC_MFPL_PC5MFP_I2C1_SCL /*!< GPC_MFPL PC5 setting for I2C1_SCL*/\r
+#define I2C1_SCL_PA7 SYS_GPA_MFPL_PA7MFP_I2C1_SCL /*!< GPA_MFPL PA7 setting for I2C1_SCL*/\r
+#define I2C1_SCL_PF0 SYS_GPF_MFPL_PF0MFP_I2C1_SCL /*!< GPF_MFPL PF0 setting for I2C1_SCL*/\r
+#define I2C1_SCL_PE1 SYS_GPE_MFPL_PE1MFP_I2C1_SCL /*!< GPE_MFPL PE1 setting for I2C1_SCL*/\r
+#define I2C1_SDA_PB0 SYS_GPB_MFPL_PB0MFP_I2C1_SDA /*!< GPB_MFPL PB0 setting for I2C1_SDA*/\r
+#define I2C1_SDA_PA6 SYS_GPA_MFPL_PA6MFP_I2C1_SDA /*!< GPA_MFPL PA6 setting for I2C1_SDA*/\r
+#define I2C1_SDA_PA13 SYS_GPA_MFPH_PA13MFP_I2C1_SDA /*!< GPA_MFPH PA13 setting for I2C1_SDA*/\r
+#define I2C1_SDA_PG3 SYS_GPG_MFPL_PG3MFP_I2C1_SDA /*!< GPG_MFPL PG3 setting for I2C1_SDA*/\r
+#define I2C1_SDA_PE0 SYS_GPE_MFPL_PE0MFP_I2C1_SDA /*!< GPE_MFPL PE0 setting for I2C1_SDA*/\r
+#define I2C1_SDA_PC4 SYS_GPC_MFPL_PC4MFP_I2C1_SDA /*!< GPC_MFPL PC4 setting for I2C1_SDA*/\r
+#define I2C1_SDA_PA2 SYS_GPA_MFPL_PA2MFP_I2C1_SDA /*!< GPA_MFPL PA2 setting for I2C1_SDA*/\r
+#define I2C1_SDA_PB10 SYS_GPB_MFPH_PB10MFP_I2C1_SDA /*!< GPB_MFPH PB10 setting for I2C1_SDA*/\r
+#define I2C1_SDA_PF1 SYS_GPF_MFPL_PF1MFP_I2C1_SDA /*!< GPF_MFPL PF1 setting for I2C1_SDA*/\r
+#define I2C1_SDA_PD4 SYS_GPD_MFPL_PD4MFP_I2C1_SDA /*!< GPD_MFPL PD4 setting for I2C1_SDA*/\r
+#define I2C1_SMBAL_PB9 SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL /*!< GPB_MFPH PB9 setting for I2C1_SMBAL*/\r
+#define I2C1_SMBAL_PC7 SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL /*!< GPC_MFPL PC7 setting for I2C1_SMBAL*/\r
+#define I2C1_SMBAL_PH8 SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL /*!< GPH_MFPH PH8 setting for I2C1_SMBAL*/\r
+#define I2C1_SMBSUS_PH9 SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS /*!< GPH_MFPH PH9 setting for I2C1_SMBSUS*/\r
+#define I2C1_SMBSUS_PC6 SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS /*!< GPC_MFPL PC6 setting for I2C1_SMBSUS*/\r
+#define I2C1_SMBSUS_PB8 SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS /*!< GPB_MFPH PB8 setting for I2C1_SMBSUS*/\r
+#define I2C2_SCL_PB13 SYS_GPB_MFPH_PB13MFP_I2C2_SCL /*!< GPB_MFPH PB13 setting for I2C2_SCL*/\r
+#define I2C2_SCL_PA11 SYS_GPA_MFPH_PA11MFP_I2C2_SCL /*!< GPA_MFPH PA11 setting for I2C2_SCL*/\r
+#define I2C2_SCL_PH8 SYS_GPH_MFPH_PH8MFP_I2C2_SCL /*!< GPH_MFPH PH8 setting for I2C2_SCL*/\r
+#define I2C2_SCL_PD9 SYS_GPD_MFPH_PD9MFP_I2C2_SCL /*!< GPD_MFPH PD9 setting for I2C2_SCL*/\r
+#define I2C2_SCL_PD1 SYS_GPD_MFPL_PD1MFP_I2C2_SCL /*!< GPD_MFPL PD1 setting for I2C2_SCL*/\r
+#define I2C2_SCL_PA14 SYS_GPA_MFPH_PA14MFP_I2C2_SCL /*!< GPA_MFPH PA14 setting for I2C2_SCL*/\r
+#define I2C2_SCL_PA1 SYS_GPA_MFPL_PA1MFP_I2C2_SCL /*!< GPA_MFPL PA1 setting for I2C2_SCL*/\r
+#define I2C2_SDA_PA0 SYS_GPA_MFPL_PA0MFP_I2C2_SDA /*!< GPA_MFPL PA0 setting for I2C2_SDA*/\r
+#define I2C2_SDA_PB12 SYS_GPB_MFPH_PB12MFP_I2C2_SDA /*!< GPB_MFPH PB12 setting for I2C2_SDA*/\r
+#define I2C2_SDA_PA10 SYS_GPA_MFPH_PA10MFP_I2C2_SDA /*!< GPA_MFPH PA10 setting for I2C2_SDA*/\r
+#define I2C2_SDA_PA15 SYS_GPA_MFPH_PA15MFP_I2C2_SDA /*!< GPA_MFPH PA15 setting for I2C2_SDA*/\r
+#define I2C2_SDA_PH9 SYS_GPH_MFPH_PH9MFP_I2C2_SDA /*!< GPH_MFPH PH9 setting for I2C2_SDA*/\r
+#define I2C2_SDA_PD8 SYS_GPD_MFPH_PD8MFP_I2C2_SDA /*!< GPD_MFPH PD8 setting for I2C2_SDA*/\r
+#define I2C2_SDA_PD0 SYS_GPD_MFPL_PD0MFP_I2C2_SDA /*!< GPD_MFPL PD0 setting for I2C2_SDA*/\r
+#define I2C2_SMBAL_PB15 SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL /*!< GPB_MFPH PB15 setting for I2C2_SMBAL*/\r
+#define I2C2_SMBSUS_PB14 SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS /*!< GPB_MFPH PB14 setting for I2C2_SMBSUS*/\r
+#define I2S0_BCLK_PA12 SYS_GPA_MFPH_PA12MFP_I2S0_BCLK /*!< GPA_MFPH PA12 setting for I2S0_BCLK*/\r
+#define I2S0_BCLK_PB5 SYS_GPB_MFPL_PB5MFP_I2S0_BCLK /*!< GPB_MFPL PB5 setting for I2S0_BCLK*/\r
+#define I2S0_BCLK_PE8 SYS_GPE_MFPH_PE8MFP_I2S0_BCLK /*!< GPE_MFPH PE8 setting for I2S0_BCLK*/\r
+#define I2S0_BCLK_PE1 SYS_GPE_MFPL_PE1MFP_I2S0_BCLK /*!< GPE_MFPL PE1 setting for I2S0_BCLK*/\r
+#define I2S0_BCLK_PF10 SYS_GPF_MFPH_PF10MFP_I2S0_BCLK /*!< GPF_MFPH PF10 setting for I2S0_BCLK*/\r
+#define I2S0_BCLK_PC4 SYS_GPC_MFPL_PC4MFP_I2S0_BCLK /*!< GPC_MFPL PC4 setting for I2S0_BCLK*/\r
+#define I2S0_DI_PF8 SYS_GPF_MFPH_PF8MFP_I2S0_DI /*!< GPF_MFPH PF8 setting for I2S0_DI*/\r
+#define I2S0_DI_PB3 SYS_GPB_MFPL_PB3MFP_I2S0_DI /*!< GPB_MFPL PB3 setting for I2S0_DI*/\r
+#define I2S0_DI_PE10 SYS_GPE_MFPH_PE10MFP_I2S0_DI /*!< GPE_MFPH PE10 setting for I2S0_DI*/\r
+#define I2S0_DI_PA14 SYS_GPA_MFPH_PA14MFP_I2S0_DI /*!< GPA_MFPH PA14 setting for I2S0_DI*/\r
+#define I2S0_DI_PH8 SYS_GPH_MFPH_PH8MFP_I2S0_DI /*!< GPH_MFPH PH8 setting for I2S0_DI*/\r
+#define I2S0_DI_PC2 SYS_GPC_MFPL_PC2MFP_I2S0_DI /*!< GPC_MFPL PC2 setting for I2S0_DI*/\r
+#define I2S0_DO_PB2 SYS_GPB_MFPL_PB2MFP_I2S0_DO /*!< GPB_MFPL PB2 setting for I2S0_DO*/\r
+#define I2S0_DO_PH9 SYS_GPH_MFPH_PH9MFP_I2S0_DO /*!< GPH_MFPH PH9 setting for I2S0_DO*/\r
+#define I2S0_DO_PF7 SYS_GPF_MFPL_PF7MFP_I2S0_DO /*!< GPF_MFPL PF7 setting for I2S0_DO*/\r
+#define I2S0_DO_PE11 SYS_GPE_MFPH_PE11MFP_I2S0_DO /*!< GPE_MFPH PE11 setting for I2S0_DO*/\r
+#define I2S0_DO_PC1 SYS_GPC_MFPL_PC1MFP_I2S0_DO /*!< GPC_MFPL PC1 setting for I2S0_DO*/\r
+#define I2S0_DO_PA15 SYS_GPA_MFPH_PA15MFP_I2S0_DO /*!< GPA_MFPH PA15 setting for I2S0_DO*/\r
+#define I2S0_LRCK_PF6 SYS_GPF_MFPL_PF6MFP_I2S0_LRCK /*!< GPF_MFPL PF6 setting for I2S0_LRCK*/\r
+#define I2S0_LRCK_PE12 SYS_GPE_MFPH_PE12MFP_I2S0_LRCK /*!< GPE_MFPH PE12 setting for I2S0_LRCK*/\r
+#define I2S0_LRCK_PC0 SYS_GPC_MFPL_PC0MFP_I2S0_LRCK /*!< GPC_MFPL PC0 setting for I2S0_LRCK*/\r
+#define I2S0_LRCK_PH10 SYS_GPH_MFPH_PH10MFP_I2S0_LRCK /*!< GPH_MFPH PH10 setting for I2S0_LRCK*/\r
+#define I2S0_LRCK_PB1 SYS_GPB_MFPL_PB1MFP_I2S0_LRCK /*!< GPB_MFPL PB1 setting for I2S0_LRCK*/\r
+#define I2S0_MCLK_PE9 SYS_GPE_MFPH_PE9MFP_I2S0_MCLK /*!< GPE_MFPH PE9 setting for I2S0_MCLK*/\r
+#define I2S0_MCLK_PB4 SYS_GPB_MFPL_PB4MFP_I2S0_MCLK /*!< GPB_MFPL PB4 setting for I2S0_MCLK*/\r
+#define I2S0_MCLK_PC3 SYS_GPC_MFPL_PC3MFP_I2S0_MCLK /*!< GPC_MFPL PC3 setting for I2S0_MCLK*/\r
+#define I2S0_MCLK_PE0 SYS_GPE_MFPL_PE0MFP_I2S0_MCLK /*!< GPE_MFPL PE0 setting for I2S0_MCLK*/\r
+#define I2S0_MCLK_PA13 SYS_GPA_MFPH_PA13MFP_I2S0_MCLK /*!< GPA_MFPH PA13 setting for I2S0_MCLK*/\r
+#define I2S0_MCLK_PF9 SYS_GPF_MFPH_PF9MFP_I2S0_MCLK /*!< GPF_MFPH PF9 setting for I2S0_MCLK*/\r
+#define ICE_CLK_PF1 SYS_GPF_MFPL_PF1MFP_ICE_CLK /*!< GPF_MFPL PF1 setting for ICE_CLK*/\r
+#define ICE_DAT_PF0 SYS_GPF_MFPL_PF0MFP_ICE_DAT /*!< GPF_MFPL PF0 setting for ICE_DAT*/\r
+#define INT0_PB5 SYS_GPB_MFPL_PB5MFP_INT0 /*!< GPB_MFPL PB5 setting for INT0*/\r
+#define INT0_PA6 SYS_GPA_MFPL_PA6MFP_INT0 /*!< GPA_MFPL PA6 setting for INT0*/\r
+#define INT1_PB4 SYS_GPB_MFPL_PB4MFP_INT1 /*!< GPB_MFPL PB4 setting for INT1*/\r
+#define INT1_PA7 SYS_GPA_MFPL_PA7MFP_INT1 /*!< GPA_MFPL PA7 setting for INT1*/\r
+#define INT2_PB3 SYS_GPB_MFPL_PB3MFP_INT2 /*!< GPB_MFPL PB3 setting for INT2*/\r
+#define INT2_PC6 SYS_GPC_MFPL_PC6MFP_INT2 /*!< GPC_MFPL PC6 setting for INT2*/\r
+#define INT3_PC7 SYS_GPC_MFPL_PC7MFP_INT3 /*!< GPC_MFPL PC7 setting for INT3*/\r
+#define INT3_PB2 SYS_GPB_MFPL_PB2MFP_INT3 /*!< GPB_MFPL PB2 setting for INT3*/\r
+#define INT4_PB6 SYS_GPB_MFPL_PB6MFP_INT4 /*!< GPB_MFPL PB6 setting for INT4*/\r
+#define INT4_PA8 SYS_GPA_MFPH_PA8MFP_INT4 /*!< GPA_MFPH PA8 setting for INT4*/\r
+#define INT5_PB7 SYS_GPB_MFPL_PB7MFP_INT5 /*!< GPB_MFPL PB7 setting for INT5*/\r
+#define INT5_PD12 SYS_GPD_MFPH_PD12MFP_INT5 /*!< GPD_MFPH PD12 setting for INT5*/\r
+#define INT6_PD11 SYS_GPD_MFPH_PD11MFP_INT6 /*!< GPD_MFPH PD11 setting for INT6*/\r
+#define INT6_PB8 SYS_GPB_MFPH_PB8MFP_INT6 /*!< GPB_MFPH PB8 setting for INT6*/\r
+#define INT7_PB9 SYS_GPB_MFPH_PB9MFP_INT7 /*!< GPB_MFPH PB9 setting for INT7*/\r
+#define INT7_PD10 SYS_GPD_MFPH_PD10MFP_INT7 /*!< GPD_MFPH PD10 setting for INT7*/\r
+#define EPWM0_BRAKE0_PE8 SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0 /*!< GPE_MFPH PE8 setting for EPWM0_BRAKE0*/\r
+#define EPWM0_BRAKE0_PB1 SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0 /*!< GPB_MFPL PB1 setting for EPWM0_BRAKE0*/\r
+#define EPWM0_BRAKE1_PB0 SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1 /*!< GPB_MFPL PB0 setting for EPWM0_BRAKE1*/\r
+#define EPWM0_BRAKE1_PE9 SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1 /*!< GPE_MFPH PE9 setting for EPWM0_BRAKE1*/\r
+#define EPWM0_CH0_PA5 SYS_GPA_MFPL_PA5MFP_EPWM0_CH0 /*!< GPA_MFPL PA5 setting for EPWM0_CH0*/\r
+#define EPWM0_CH0_PE7 SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 /*!< GPE_MFPL PE7 setting for EPWM0_CH0*/\r
+#define EPWM0_CH0_PE8 SYS_GPE_MFPH_PE8MFP_EPWM0_CH0 /*!< GPE_MFPH PE8 setting for EPWM0_CH0*/\r
+#define EPWM0_CH0_PB5 SYS_GPB_MFPL_PB5MFP_EPWM0_CH0 /*!< GPB_MFPL PB5 setting for EPWM0_CH0*/\r
+#define EPWM0_CH1_PA4 SYS_GPA_MFPL_PA4MFP_EPWM0_CH1 /*!< GPA_MFPL PA4 setting for EPWM0_CH1*/\r
+#define EPWM0_CH1_PB4 SYS_GPB_MFPL_PB4MFP_EPWM0_CH1 /*!< GPB_MFPL PB4 setting for EPWM0_CH1*/\r
+#define EPWM0_CH1_PE9 SYS_GPE_MFPH_PE9MFP_EPWM0_CH1 /*!< GPE_MFPH PE9 setting for EPWM0_CH1*/\r
+#define EPWM0_CH1_PE6 SYS_GPE_MFPL_PE6MFP_EPWM0_CH1 /*!< GPE_MFPL PE6 setting for EPWM0_CH1*/\r
+#define EPWM0_CH2_PE5 SYS_GPE_MFPL_PE5MFP_EPWM0_CH2 /*!< GPE_MFPL PE5 setting for EPWM0_CH2*/\r
+#define EPWM0_CH2_PB3 SYS_GPB_MFPL_PB3MFP_EPWM0_CH2 /*!< GPB_MFPL PB3 setting for EPWM0_CH2*/\r
+#define EPWM0_CH2_PE10 SYS_GPE_MFPH_PE10MFP_EPWM0_CH2 /*!< GPE_MFPH PE10 setting for EPWM0_CH2*/\r
+#define EPWM0_CH2_PA3 SYS_GPA_MFPL_PA3MFP_EPWM0_CH2 /*!< GPA_MFPL PA3 setting for EPWM0_CH2*/\r
+#define EPWM0_CH3_PA2 SYS_GPA_MFPL_PA2MFP_EPWM0_CH3 /*!< GPA_MFPL PA2 setting for EPWM0_CH3*/\r
+#define EPWM0_CH3_PE11 SYS_GPE_MFPH_PE11MFP_EPWM0_CH3 /*!< GPE_MFPH PE11 setting for EPWM0_CH3*/\r
+#define EPWM0_CH3_PE4 SYS_GPE_MFPL_PE4MFP_EPWM0_CH3 /*!< GPE_MFPL PE4 setting for EPWM0_CH3*/\r
+#define EPWM0_CH3_PB2 SYS_GPB_MFPL_PB2MFP_EPWM0_CH3 /*!< GPB_MFPL PB2 setting for EPWM0_CH3*/\r
+#define EPWM0_CH4_PD14 SYS_GPD_MFPH_PD14MFP_EPWM0_CH4 /*!< GPD_MFPH PD14 setting for EPWM0_CH4*/\r
+#define EPWM0_CH4_PB1 SYS_GPB_MFPL_PB1MFP_EPWM0_CH4 /*!< GPB_MFPL PB1 setting for EPWM0_CH4*/\r
+#define EPWM0_CH4_PE3 SYS_GPE_MFPL_PE3MFP_EPWM0_CH4 /*!< GPE_MFPL PE3 setting for EPWM0_CH4*/\r
+#define EPWM0_CH4_PA1 SYS_GPA_MFPL_PA1MFP_EPWM0_CH4 /*!< GPA_MFPL PA1 setting for EPWM0_CH4*/\r
+#define EPWM0_CH4_PE12 SYS_GPE_MFPH_PE12MFP_EPWM0_CH4 /*!< GPE_MFPH PE12 setting for EPWM0_CH4*/\r
+#define EPWM0_CH5_PB0 SYS_GPB_MFPL_PB0MFP_EPWM0_CH5 /*!< GPB_MFPL PB0 setting for EPWM0_CH5*/\r
+#define EPWM0_CH5_PE2 SYS_GPE_MFPL_PE2MFP_EPWM0_CH5 /*!< GPE_MFPL PE2 setting for EPWM0_CH5*/\r
+#define EPWM0_CH5_PA0 SYS_GPA_MFPL_PA0MFP_EPWM0_CH5 /*!< GPA_MFPL PA0 setting for EPWM0_CH5*/\r
+#define EPWM0_CH5_PE13 SYS_GPE_MFPH_PE13MFP_EPWM0_CH5 /*!< GPE_MFPH PE13 setting for EPWM0_CH5*/\r
+#define EPWM0_CH5_PH11 SYS_GPH_MFPH_PH11MFP_EPWM0_CH5 /*!< GPH_MFPH PH11 setting for EPWM0_CH5*/\r
+#define EPWM0_SYNC_IN_PA15 SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN /*!< GPA_MFPH PA15 setting for EPWM0_SYNC_IN*/\r
+#define EPWM0_SYNC_OUT_PF5 SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT /*!< GPF_MFPL PF5 setting for EPWM0_SYNC_OUT*/\r
+#define EPWM0_SYNC_OUT_PA11 SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT /*!< GPA_MFPH PA11 setting for EPWM0_SYNC_OUT*/\r
+#define EPWM1_BRAKE0_PB7 SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0 /*!< GPB_MFPL PB7 setting for EPWM1_BRAKE0*/\r
+#define EPWM1_BRAKE0_PE10 SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0 /*!< GPE_MFPH PE10 setting for EPWM1_BRAKE0*/\r
+#define EPWM1_BRAKE1_PB6 SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1 /*!< GPB_MFPL PB6 setting for EPWM1_BRAKE1*/\r
+#define EPWM1_BRAKE1_PE11 SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1 /*!< GPE_MFPH PE11 setting for EPWM1_BRAKE1*/\r
+#define EPWM1_CH0_PC5 SYS_GPC_MFPL_PC5MFP_EPWM1_CH0 /*!< GPC_MFPL PC5 setting for EPWM1_CH0*/\r
+#define EPWM1_CH0_PE13 SYS_GPE_MFPH_PE13MFP_EPWM1_CH0 /*!< GPE_MFPH PE13 setting for EPWM1_CH0*/\r
+#define EPWM1_CH0_PC12 SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 /*!< GPC_MFPH PC12 setting for EPWM1_CH0*/\r
+#define EPWM1_CH0_PB15 SYS_GPB_MFPH_PB15MFP_EPWM1_CH0 /*!< GPB_MFPH PB15 setting for EPWM1_CH0*/\r
+#define EPWM1_CH1_PB14 SYS_GPB_MFPH_PB14MFP_EPWM1_CH1 /*!< GPB_MFPH PB14 setting for EPWM1_CH1*/\r
+#define EPWM1_CH1_PC11 SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 /*!< GPC_MFPH PC11 setting for EPWM1_CH1*/\r
+#define EPWM1_CH1_PC4 SYS_GPC_MFPL_PC4MFP_EPWM1_CH1 /*!< GPC_MFPL PC4 setting for EPWM1_CH1*/\r
+#define EPWM1_CH1_PC8 SYS_GPC_MFPH_PC8MFP_EPWM1_CH1 /*!< GPC_MFPH PC8 setting for EPWM1_CH1*/\r
+#define EPWM1_CH2_PC7 SYS_GPC_MFPL_PC7MFP_EPWM1_CH2 /*!< GPC_MFPL PC7 setting for EPWM1_CH2*/\r
+#define EPWM1_CH2_PC10 SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 /*!< GPC_MFPH PC10 setting for EPWM1_CH2*/\r
+#define EPWM1_CH2_PC3 SYS_GPC_MFPL_PC3MFP_EPWM1_CH2 /*!< GPC_MFPL PC3 setting for EPWM1_CH2*/\r
+#define EPWM1_CH2_PB13 SYS_GPB_MFPH_PB13MFP_EPWM1_CH2 /*!< GPB_MFPH PB13 setting for EPWM1_CH2*/\r
+#define EPWM1_CH3_PB12 SYS_GPB_MFPH_PB12MFP_EPWM1_CH3 /*!< GPB_MFPH PB12 setting for EPWM1_CH3*/\r
+#define EPWM1_CH3_PC6 SYS_GPC_MFPL_PC6MFP_EPWM1_CH3 /*!< GPC_MFPL PC6 setting for EPWM1_CH3*/\r
+#define EPWM1_CH3_PC9 SYS_GPC_MFPH_PC9MFP_EPWM1_CH3 /*!< GPC_MFPH PC9 setting for EPWM1_CH3*/\r
+#define EPWM1_CH3_PC2 SYS_GPC_MFPL_PC2MFP_EPWM1_CH3 /*!< GPC_MFPL PC2 setting for EPWM1_CH3*/\r
+#define EPWM1_CH4_PB7 SYS_GPB_MFPL_PB7MFP_EPWM1_CH4 /*!< GPB_MFPL PB7 setting for EPWM1_CH4*/\r
+#define EPWM1_CH4_PB1 SYS_GPB_MFPL_PB1MFP_EPWM1_CH4 /*!< GPB_MFPL PB1 setting for EPWM1_CH4*/\r
+#define EPWM1_CH4_PC1 SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 /*!< GPC_MFPL PC1 setting for EPWM1_CH4*/\r
+#define EPWM1_CH4_PA7 SYS_GPA_MFPL_PA7MFP_EPWM1_CH4 /*!< GPA_MFPL PA7 setting for EPWM1_CH4*/\r
+#define EPWM1_CH5_PA6 SYS_GPA_MFPL_PA6MFP_EPWM1_CH5 /*!< GPA_MFPL PA6 setting for EPWM1_CH5*/\r
+#define EPWM1_CH5_PC0 SYS_GPC_MFPL_PC0MFP_EPWM1_CH5 /*!< GPC_MFPL PC0 setting for EPWM1_CH5*/\r
+#define EPWM1_CH5_PB6 SYS_GPB_MFPL_PB6MFP_EPWM1_CH5 /*!< GPB_MFPL PB6 setting for EPWM1_CH5*/\r
+#define EPWM1_CH5_PB0 SYS_GPB_MFPL_PB0MFP_EPWM1_CH5 /*!< GPB_MFPL PB0 setting for EPWM1_CH5*/\r
+#define QEI0_A_PE3 SYS_GPE_MFPL_PE3MFP_QEI0_A /*!< GPE_MFPL PE3 setting for QEI0_A*/\r
+#define QEI0_A_PA4 SYS_GPA_MFPL_PA4MFP_QEI0_A /*!< GPA_MFPL PA4 setting for QEI0_A*/\r
+#define QEI0_A_PD11 SYS_GPD_MFPH_PD11MFP_QEI0_A /*!< GPD_MFPH PD11 setting for QEI0_A*/\r
+#define QEI0_B_PD10 SYS_GPD_MFPH_PD10MFP_QEI0_B /*!< GPD_MFPH PD10 setting for QEI0_B*/\r
+#define QEI0_B_PA3 SYS_GPA_MFPL_PA3MFP_QEI0_B /*!< GPA_MFPL PA3 setting for QEI0_B*/\r
+#define QEI0_B_PE2 SYS_GPE_MFPL_PE2MFP_QEI0_B /*!< GPE_MFPL PE2 setting for QEI0_B*/\r
+#define QEI0_INDEX_PE4 SYS_GPE_MFPL_PE4MFP_QEI0_INDEX /*!< GPE_MFPL PE4 setting for QEI0_INDEX*/\r
+#define QEI0_INDEX_PA5 SYS_GPA_MFPL_PA5MFP_QEI0_INDEX /*!< GPA_MFPL PA5 setting for QEI0_INDEX*/\r
+#define QEI0_INDEX_PD12 SYS_GPD_MFPH_PD12MFP_QEI0_INDEX /*!< GPD_MFPH PD12 setting for QEI0_INDEX*/\r
+#define QEI1_A_PE6 SYS_GPE_MFPL_PE6MFP_QEI1_A /*!< GPE_MFPL PE6 setting for QEI1_A*/\r
+#define QEI1_A_PA13 SYS_GPA_MFPH_PA13MFP_QEI1_A /*!< GPA_MFPH PA13 setting for QEI1_A*/\r
+#define QEI1_A_PA9 SYS_GPA_MFPH_PA9MFP_QEI1_A /*!< GPA_MFPH PA9 setting for QEI1_A*/\r
+#define QEI1_B_PA14 SYS_GPA_MFPH_PA14MFP_QEI1_B /*!< GPA_MFPH PA14 setting for QEI1_B*/\r
+#define QEI1_B_PA8 SYS_GPA_MFPH_PA8MFP_QEI1_B /*!< GPA_MFPH PA8 setting for QEI1_B*/\r
+#define QEI1_B_PE5 SYS_GPE_MFPL_PE5MFP_QEI1_B /*!< GPE_MFPL PE5 setting for QEI1_B*/\r
+#define QEI1_INDEX_PE7 SYS_GPE_MFPL_PE7MFP_QEI1_INDEX /*!< GPE_MFPL PE7 setting for QEI1_INDEX*/\r
+#define QEI1_INDEX_PA10 SYS_GPA_MFPH_PA10MFP_QEI1_INDEX /*!< GPA_MFPH PA10 setting for QEI1_INDEX*/\r
+#define QEI1_INDEX_PA12 SYS_GPA_MFPH_PA12MFP_QEI1_INDEX /*!< GPA_MFPH PA12 setting for QEI1_INDEX*/\r
+#define SC0_CLK_PF6 SYS_GPF_MFPL_PF6MFP_SC0_CLK /*!< GPF_MFPL PF6 setting for SC0_CLK*/\r
+#define SC0_CLK_PE2 SYS_GPE_MFPL_PE2MFP_SC0_CLK /*!< GPE_MFPL PE2 setting for SC0_CLK*/\r
+#define SC0_CLK_PA0 SYS_GPA_MFPL_PA0MFP_SC0_CLK /*!< GPA_MFPL PA0 setting for SC0_CLK*/\r
+#define SC0_CLK_PB5 SYS_GPB_MFPL_PB5MFP_SC0_CLK /*!< GPB_MFPL PB5 setting for SC0_CLK*/\r
+#define SC0_DAT_PE3 SYS_GPE_MFPL_PE3MFP_SC0_DAT /*!< GPE_MFPL PE3 setting for SC0_DAT*/\r
+#define SC0_DAT_PB4 SYS_GPB_MFPL_PB4MFP_SC0_DAT /*!< GPB_MFPL PB4 setting for SC0_DAT*/\r
+#define SC0_DAT_PA1 SYS_GPA_MFPL_PA1MFP_SC0_DAT /*!< GPA_MFPL PA1 setting for SC0_DAT*/\r
+#define SC0_DAT_PF7 SYS_GPF_MFPL_PF7MFP_SC0_DAT /*!< GPF_MFPL PF7 setting for SC0_DAT*/\r
+#define SC0_PWR_PE5 SYS_GPE_MFPL_PE5MFP_SC0_PWR /*!< GPE_MFPL PE5 setting for SC0_PWR*/\r
+#define SC0_PWR_PA3 SYS_GPA_MFPL_PA3MFP_SC0_PWR /*!< GPA_MFPL PA3 setting for SC0_PWR*/\r
+#define SC0_PWR_PB2 SYS_GPB_MFPL_PB2MFP_SC0_PWR /*!< GPB_MFPL PB2 setting for SC0_PWR*/\r
+#define SC0_PWR_PF9 SYS_GPF_MFPH_PF9MFP_SC0_PWR /*!< GPF_MFPH PF9 setting for SC0_PWR*/\r
+#define SC0_RST_PF8 SYS_GPF_MFPH_PF8MFP_SC0_RST /*!< GPF_MFPH PF8 setting for SC0_RST*/\r
+#define SC0_RST_PE4 SYS_GPE_MFPL_PE4MFP_SC0_RST /*!< GPE_MFPL PE4 setting for SC0_RST*/\r
+#define SC0_RST_PA2 SYS_GPA_MFPL_PA2MFP_SC0_RST /*!< GPA_MFPL PA2 setting for SC0_RST*/\r
+#define SC0_RST_PB3 SYS_GPB_MFPL_PB3MFP_SC0_RST /*!< GPB_MFPL PB3 setting for SC0_RST*/\r
+#define SC0_nCD_PE6 SYS_GPE_MFPL_PE6MFP_SC0_nCD /*!< GPE_MFPL PE6 setting for SC0_nCD*/\r
+#define SC0_nCD_PF10 SYS_GPF_MFPH_PF10MFP_SC0_nCD /*!< GPF_MFPH PF10 setting for SC0_nCD*/\r
+#define SC0_nCD_PA4 SYS_GPA_MFPL_PA4MFP_SC0_nCD /*!< GPA_MFPL PA4 setting for SC0_nCD*/\r
+#define SC0_nCD_PC12 SYS_GPC_MFPH_PC12MFP_SC0_nCD /*!< GPC_MFPH PC12 setting for SC0_nCD*/\r
+#define SC1_CLK_PC0 SYS_GPC_MFPL_PC0MFP_SC1_CLK /*!< GPC_MFPL PC0 setting for SC1_CLK*/\r
+#define SC1_CLK_PB12 SYS_GPB_MFPH_PB12MFP_SC1_CLK /*!< GPB_MFPH PB12 setting for SC1_CLK*/\r
+#define SC1_CLK_PD4 SYS_GPD_MFPL_PD4MFP_SC1_CLK /*!< GPD_MFPL PD4 setting for SC1_CLK*/\r
+#define SC1_DAT_PD5 SYS_GPD_MFPL_PD5MFP_SC1_DAT /*!< GPD_MFPL PD5 setting for SC1_DAT*/\r
+#define SC1_DAT_PB13 SYS_GPB_MFPH_PB13MFP_SC1_DAT /*!< GPB_MFPH PB13 setting for SC1_DAT*/\r
+#define SC1_DAT_PC1 SYS_GPC_MFPL_PC1MFP_SC1_DAT /*!< GPC_MFPL PC1 setting for SC1_DAT*/\r
+#define SC1_PWR_PB15 SYS_GPB_MFPH_PB15MFP_SC1_PWR /*!< GPB_MFPH PB15 setting for SC1_PWR*/\r
+#define SC1_PWR_PC3 SYS_GPC_MFPL_PC3MFP_SC1_PWR /*!< GPC_MFPL PC3 setting for SC1_PWR*/\r
+#define SC1_PWR_PD7 SYS_GPD_MFPL_PD7MFP_SC1_PWR /*!< GPD_MFPL PD7 setting for SC1_PWR*/\r
+#define SC1_RST_PD6 SYS_GPD_MFPL_PD6MFP_SC1_RST /*!< GPD_MFPL PD6 setting for SC1_RST*/\r
+#define SC1_RST_PB14 SYS_GPB_MFPH_PB14MFP_SC1_RST /*!< GPB_MFPH PB14 setting for SC1_RST*/\r
+#define SC1_RST_PC2 SYS_GPC_MFPL_PC2MFP_SC1_RST /*!< GPC_MFPL PC2 setting for SC1_RST*/\r
+#define SC1_nCD_PD3 SYS_GPD_MFPL_PD3MFP_SC1_nCD /*!< GPD_MFPL PD3 setting for SC1_nCD*/\r
+#define SC1_nCD_PC4 SYS_GPC_MFPL_PC4MFP_SC1_nCD /*!< GPC_MFPL PC4 setting for SC1_nCD*/\r
+#define SC1_nCD_PD14 SYS_GPD_MFPH_PD14MFP_SC1_nCD /*!< GPD_MFPH PD14 setting for SC1_nCD*/\r
+#define SC2_CLK_PD0 SYS_GPD_MFPL_PD0MFP_SC2_CLK /*!< GPD_MFPL PD0 setting for SC2_CLK*/\r
+#define SC2_CLK_PA15 SYS_GPA_MFPH_PA15MFP_SC2_CLK /*!< GPA_MFPH PA15 setting for SC2_CLK*/\r
+#define SC2_CLK_PE0 SYS_GPE_MFPL_PE0MFP_SC2_CLK /*!< GPE_MFPL PE0 setting for SC2_CLK*/\r
+#define SC2_CLK_PA8 SYS_GPA_MFPH_PA8MFP_SC2_CLK /*!< GPA_MFPH PA8 setting for SC2_CLK*/\r
+#define SC2_CLK_PA6 SYS_GPA_MFPL_PA6MFP_SC2_CLK /*!< GPA_MFPL PA6 setting for SC2_CLK*/\r
+#define SC2_DAT_PE1 SYS_GPE_MFPL_PE1MFP_SC2_DAT /*!< GPE_MFPL PE1 setting for SC2_DAT*/\r
+#define SC2_DAT_PD1 SYS_GPD_MFPL_PD1MFP_SC2_DAT /*!< GPD_MFPL PD1 setting for SC2_DAT*/\r
+#define SC2_DAT_PA9 SYS_GPA_MFPH_PA9MFP_SC2_DAT /*!< GPA_MFPH PA9 setting for SC2_DAT*/\r
+#define SC2_DAT_PA14 SYS_GPA_MFPH_PA14MFP_SC2_DAT /*!< GPA_MFPH PA14 setting for SC2_DAT*/\r
+#define SC2_DAT_PA7 SYS_GPA_MFPL_PA7MFP_SC2_DAT /*!< GPA_MFPL PA7 setting for SC2_DAT*/\r
+#define SC2_PWR_PD3 SYS_GPD_MFPL_PD3MFP_SC2_PWR /*!< GPD_MFPL PD3 setting for SC2_PWR*/\r
+#define SC2_PWR_PA11 SYS_GPA_MFPH_PA11MFP_SC2_PWR /*!< GPA_MFPH PA11 setting for SC2_PWR*/\r
+#define SC2_PWR_PA12 SYS_GPA_MFPH_PA12MFP_SC2_PWR /*!< GPA_MFPH PA12 setting for SC2_PWR*/\r
+#define SC2_PWR_PH8 SYS_GPH_MFPH_PH8MFP_SC2_PWR /*!< GPH_MFPH PH8 setting for SC2_PWR*/\r
+#define SC2_PWR_PC7 SYS_GPC_MFPL_PC7MFP_SC2_PWR /*!< GPC_MFPL PC7 setting for SC2_PWR*/\r
+#define SC2_RST_PD2 SYS_GPD_MFPL_PD2MFP_SC2_RST /*!< GPD_MFPL PD2 setting for SC2_RST*/\r
+#define SC2_RST_PC6 SYS_GPC_MFPL_PC6MFP_SC2_RST /*!< GPC_MFPL PC6 setting for SC2_RST*/\r
+#define SC2_RST_PH9 SYS_GPH_MFPH_PH9MFP_SC2_RST /*!< GPH_MFPH PH9 setting for SC2_RST*/\r
+#define SC2_RST_PA10 SYS_GPA_MFPH_PA10MFP_SC2_RST /*!< GPA_MFPH PA10 setting for SC2_RST*/\r
+#define SC2_RST_PA13 SYS_GPA_MFPH_PA13MFP_SC2_RST /*!< GPA_MFPH PA13 setting for SC2_RST*/\r
+#define SC2_nCD_PH10 SYS_GPH_MFPH_PH10MFP_SC2_nCD /*!< GPH_MFPH PH10 setting for SC2_nCD*/\r
+#define SC2_nCD_PA5 SYS_GPA_MFPL_PA5MFP_SC2_nCD /*!< GPA_MFPL PA5 setting for SC2_nCD*/\r
+#define SC2_nCD_PC13 SYS_GPC_MFPH_PC13MFP_SC2_nCD /*!< GPC_MFPH PC13 setting for SC2_nCD*/\r
+#define SC2_nCD_PD13 SYS_GPD_MFPH_PD13MFP_SC2_nCD /*!< GPD_MFPH PD13 setting for SC2_nCD*/\r
+#define SD0_CLK_PE6 SYS_GPE_MFPL_PE6MFP_SD0_CLK /*!< GPE_MFPL PE6 setting for SD0_CLK*/\r
+#define SD0_CLK_PB1 SYS_GPB_MFPL_PB1MFP_SD0_CLK /*!< GPB_MFPL PB1 setting for SD0_CLK*/\r
+#define SD0_CMD_PB0 SYS_GPB_MFPL_PB0MFP_SD0_CMD /*!< GPB_MFPL PB0 setting for SD0_CMD*/\r
+#define SD0_CMD_PE7 SYS_GPE_MFPL_PE7MFP_SD0_CMD /*!< GPE_MFPL PE7 setting for SD0_CMD*/\r
+#define SD0_DAT0_PB2 SYS_GPB_MFPL_PB2MFP_SD0_DAT0 /*!< GPB_MFPL PB2 setting for SD0_DAT0*/\r
+#define SD0_DAT0_PE2 SYS_GPE_MFPL_PE2MFP_SD0_DAT0 /*!< GPE_MFPL PE2 setting for SD0_DAT0*/\r
+#define SD0_DAT1_PE3 SYS_GPE_MFPL_PE3MFP_SD0_DAT1 /*!< GPE_MFPL PE3 setting for SD0_DAT1*/\r
+#define SD0_DAT1_PB3 SYS_GPB_MFPL_PB3MFP_SD0_DAT1 /*!< GPB_MFPL PB3 setting for SD0_DAT1*/\r
+#define SD0_DAT2_PB4 SYS_GPB_MFPL_PB4MFP_SD0_DAT2 /*!< GPB_MFPL PB4 setting for SD0_DAT2*/\r
+#define SD0_DAT2_PE4 SYS_GPE_MFPL_PE4MFP_SD0_DAT2 /*!< GPE_MFPL PE4 setting for SD0_DAT2*/\r
+#define SD0_DAT3_PE5 SYS_GPE_MFPL_PE5MFP_SD0_DAT3 /*!< GPE_MFPL PE5 setting for SD0_DAT3*/\r
+#define SD0_DAT3_PB5 SYS_GPB_MFPL_PB5MFP_SD0_DAT3 /*!< GPB_MFPL PB5 setting for SD0_DAT3*/\r
+#define SD0_nCD_PB12 SYS_GPB_MFPH_PB12MFP_SD0_nCD /*!< GPB_MFPH PB12 setting for SD0_nCD*/\r
+#define SD0_nCD_PD13 SYS_GPD_MFPH_PD13MFP_SD0_nCD /*!< GPD_MFPH PD13 setting for SD0_nCD*/\r
+#define QSPI0_CLK_PF2 SYS_GPF_MFPL_PF2MFP_QSPI0_CLK /*!< GPF_MFPL PF2 setting for QSPI0_CLK*/\r
+#define QSPI0_CLK_PH8 SYS_GPH_MFPH_PH8MFP_QSPI0_CLK /*!< GPH_MFPH PH8 setting for QSPI0_CLK*/\r
+#define QSPI0_CLK_PA2 SYS_GPA_MFPL_PA2MFP_QSPI0_CLK /*!< GPA_MFPL PA2 setting for QSPI0_CLK*/\r
+#define QSPI0_CLK_PC2 SYS_GPC_MFPL_PC2MFP_QSPI0_CLK /*!< GPC_MFPL PC2 setting for QSPI0_CLK*/\r
+#define QSPI0_MISO0_PC1 SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0 /*!< GPC_MFPL PC1 setting for QSPI0_MISO0*/\r
+#define QSPI0_MISO0_PE1 SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0 /*!< GPE_MFPL PE1 setting for QSPI0_MISO0*/\r
+#define QSPI0_MISO0_PA1 SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0 /*!< GPA_MFPL PA1 setting for QSPI0_MISO0*/\r
+#define QSPI0_MISO1_PC5 SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1 /*!< GPC_MFPL PC5 setting for QSPI0_MISO1*/\r
+#define QSPI0_MISO1_PH10 SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1 /*!< GPH_MFPH PH10 setting for QSPI0_MISO1*/\r
+#define QSPI0_MISO1_PA5 SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1 /*!< GPA_MFPL PA5 setting for QSPI0_MISO1*/\r
+#define QSPI0_MOSI0_PC0 SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0 /*!< GPC_MFPL PC0 setting for QSPI0_MOSI0*/\r
+#define QSPI0_MOSI0_PE0 SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0 /*!< GPE_MFPL PE0 setting for QSPI0_MOSI0*/\r
+#define QSPI0_MOSI0_PA0 SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0 /*!< GPA_MFPL PA0 setting for QSPI0_MOSI0*/\r
+#define QSPI0_MOSI1_PA4 SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1 /*!< GPA_MFPL PA4 setting for QSPI0_MOSI1*/\r
+#define QSPI0_MOSI1_PH11 SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1 /*!< GPH_MFPH PH11 setting for QSPI0_MOSI1*/\r
+#define QSPI0_MOSI1_PC4 SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1 /*!< GPC_MFPL PC4 setting for QSPI0_MOSI1*/\r
+#define QSPI0_SS_PH9 SYS_GPH_MFPH_PH9MFP_QSPI0_SS /*!< GPH_MFPH PH9 setting for QSPI0_SS*/\r
+#define QSPI0_SS_PA3 SYS_GPA_MFPL_PA3MFP_QSPI0_SS /*!< GPA_MFPL PA3 setting for QSPI0_SS*/\r
+#define QSPI0_SS_PC3 SYS_GPC_MFPL_PC3MFP_QSPI0_SS /*!< GPC_MFPL PC3 setting for QSPI0_SS*/\r
+#define SPI0_CLK_PD2 SYS_GPD_MFPL_PD2MFP_SPI0_CLK /*!< GPD_MFPL PD2 setting for SPI0_CLK*/\r
+#define SPI0_CLK_PF8 SYS_GPF_MFPH_PF8MFP_SPI0_CLK /*!< GPF_MFPH PF8 setting for SPI0_CLK*/\r
+#define SPI0_CLK_PA2 SYS_GPA_MFPL_PA2MFP_SPI0_CLK /*!< GPA_MFPL PA2 setting for SPI0_CLK*/\r
+#define SPI0_CLK_PB14 SYS_GPB_MFPH_PB14MFP_SPI0_CLK /*!< GPB_MFPH PB14 setting for SPI0_CLK*/\r
+#define SPI0_I2SMCLK_PD13 SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK /*!< GPD_MFPH PD13 setting for SPI0_I2SMCLK*/\r
+#define SPI0_I2SMCLK_PA4 SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK /*!< GPA_MFPL PA4 setting for SPI0_I2SMCLK*/\r
+#define SPI0_I2SMCLK_PB11 SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK /*!< GPB_MFPH PB11 setting for SPI0_I2SMCLK*/\r
+#define SPI0_I2SMCLK_PB0 SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK /*!< GPB_MFPL PB0 setting for SPI0_I2SMCLK*/\r
+#define SPI0_I2SMCLK_PD14 SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK /*!< GPD_MFPH PD14 setting for SPI0_I2SMCLK*/\r
+#define SPI0_I2SMCLK_PF10 SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK /*!< GPF_MFPH PF10 setting for SPI0_I2SMCLK*/\r
+#define SPI0_MISO_PF7 SYS_GPF_MFPL_PF7MFP_SPI0_MISO /*!< GPF_MFPL PF7 setting for SPI0_MISO*/\r
+#define SPI0_MISO_PB13 SYS_GPB_MFPH_PB13MFP_SPI0_MISO /*!< GPB_MFPH PB13 setting for SPI0_MISO*/\r
+#define SPI0_MISO_PA1 SYS_GPA_MFPL_PA1MFP_SPI0_MISO /*!< GPA_MFPL PA1 setting for SPI0_MISO*/\r
+#define SPI0_MISO_PD1 SYS_GPD_MFPL_PD1MFP_SPI0_MISO /*!< GPD_MFPL PD1 setting for SPI0_MISO*/\r
+#define SPI0_MOSI_PA0 SYS_GPA_MFPL_PA0MFP_SPI0_MOSI /*!< GPA_MFPL PA0 setting for SPI0_MOSI*/\r
+#define SPI0_MOSI_PB12 SYS_GPB_MFPH_PB12MFP_SPI0_MOSI /*!< GPB_MFPH PB12 setting for SPI0_MOSI*/\r
+#define SPI0_MOSI_PD0 SYS_GPD_MFPL_PD0MFP_SPI0_MOSI /*!< GPD_MFPL PD0 setting for SPI0_MOSI*/\r
+#define SPI0_MOSI_PF6 SYS_GPF_MFPL_PF6MFP_SPI0_MOSI /*!< GPF_MFPL PF6 setting for SPI0_MOSI*/\r
+#define SPI0_SS_PB15 SYS_GPB_MFPH_PB15MFP_SPI0_SS /*!< GPB_MFPH PB15 setting for SPI0_SS*/\r
+#define SPI0_SS_PA3 SYS_GPA_MFPL_PA3MFP_SPI0_SS /*!< GPA_MFPL PA3 setting for SPI0_SS*/\r
+#define SPI0_SS_PD3 SYS_GPD_MFPL_PD3MFP_SPI0_SS /*!< GPD_MFPL PD3 setting for SPI0_SS*/\r
+#define SPI0_SS_PF9 SYS_GPF_MFPH_PF9MFP_SPI0_SS /*!< GPF_MFPH PF9 setting for SPI0_SS*/\r
+#define SPI1_CLK_PB3 SYS_GPB_MFPL_PB3MFP_SPI1_CLK /*!< GPB_MFPL PB3 setting for SPI1_CLK*/\r
+#define SPI1_CLK_PH6 SYS_GPH_MFPL_PH6MFP_SPI1_CLK /*!< GPH_MFPL PH6 setting for SPI1_CLK*/\r
+#define SPI1_CLK_PH8 SYS_GPH_MFPH_PH8MFP_SPI1_CLK /*!< GPH_MFPH PH8 setting for SPI1_CLK*/\r
+#define SPI1_CLK_PC1 SYS_GPC_MFPL_PC1MFP_SPI1_CLK /*!< GPC_MFPL PC1 setting for SPI1_CLK*/\r
+#define SPI1_CLK_PD5 SYS_GPD_MFPL_PD5MFP_SPI1_CLK /*!< GPD_MFPL PD5 setting for SPI1_CLK*/\r
+#define SPI1_CLK_PA7 SYS_GPA_MFPL_PA7MFP_SPI1_CLK /*!< GPA_MFPL PA7 setting for SPI1_CLK*/\r
+#define SPI1_I2SMCLK_PB1 SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK /*!< GPB_MFPL PB1 setting for SPI1_I2SMCLK*/\r
+#define SPI1_I2SMCLK_PH10 SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK /*!< GPH_MFPH PH10 setting for SPI1_I2SMCLK*/\r
+#define SPI1_I2SMCLK_PC4 SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK /*!< GPC_MFPL PC4 setting for SPI1_I2SMCLK*/\r
+#define SPI1_I2SMCLK_PD13 SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK /*!< GPD_MFPH PD13 setting for SPI1_I2SMCLK*/\r
+#define SPI1_I2SMCLK_PA5 SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK /*!< GPA_MFPL PA5 setting for SPI1_I2SMCLK*/\r
+#define SPI1_MISO_PD7 SYS_GPD_MFPL_PD7MFP_SPI1_MISO /*!< GPD_MFPL PD7 setting for SPI1_MISO*/\r
+#define SPI1_MISO_PC7 SYS_GPC_MFPL_PC7MFP_SPI1_MISO /*!< GPC_MFPL PC7 setting for SPI1_MISO*/\r
+#define SPI1_MISO_PB5 SYS_GPB_MFPL_PB5MFP_SPI1_MISO /*!< GPB_MFPL PB5 setting for SPI1_MISO*/\r
+#define SPI1_MISO_PE1 SYS_GPE_MFPL_PE1MFP_SPI1_MISO /*!< GPE_MFPL PE1 setting for SPI1_MISO*/\r
+#define SPI1_MISO_PH4 SYS_GPH_MFPL_PH4MFP_SPI1_MISO /*!< GPH_MFPL PH4 setting for SPI1_MISO*/\r
+#define SPI1_MISO_PC3 SYS_GPC_MFPL_PC3MFP_SPI1_MISO /*!< GPC_MFPL PC3 setting for SPI1_MISO*/\r
+#define SPI1_MOSI_PD6 SYS_GPD_MFPL_PD6MFP_SPI1_MOSI /*!< GPD_MFPL PD6 setting for SPI1_MOSI*/\r
+#define SPI1_MOSI_PE0 SYS_GPE_MFPL_PE0MFP_SPI1_MOSI /*!< GPE_MFPL PE0 setting for SPI1_MOSI*/\r
+#define SPI1_MOSI_PB4 SYS_GPB_MFPL_PB4MFP_SPI1_MOSI /*!< GPB_MFPL PB4 setting for SPI1_MOSI*/\r
+#define SPI1_MOSI_PC6 SYS_GPC_MFPL_PC6MFP_SPI1_MOSI /*!< GPC_MFPL PC6 setting for SPI1_MOSI*/\r
+#define SPI1_MOSI_PC2 SYS_GPC_MFPL_PC2MFP_SPI1_MOSI /*!< GPC_MFPL PC2 setting for SPI1_MOSI*/\r
+#define SPI1_MOSI_PH5 SYS_GPH_MFPL_PH5MFP_SPI1_MOSI /*!< GPH_MFPL PH5 setting for SPI1_MOSI*/\r
+#define SPI1_SS_PB2 SYS_GPB_MFPL_PB2MFP_SPI1_SS /*!< GPB_MFPL PB2 setting for SPI1_SS*/\r
+#define SPI1_SS_PH9 SYS_GPH_MFPH_PH9MFP_SPI1_SS /*!< GPH_MFPH PH9 setting for SPI1_SS*/\r
+#define SPI1_SS_PD4 SYS_GPD_MFPL_PD4MFP_SPI1_SS /*!< GPD_MFPL PD4 setting for SPI1_SS*/\r
+#define SPI1_SS_PC0 SYS_GPC_MFPL_PC0MFP_SPI1_SS /*!< GPC_MFPL PC0 setting for SPI1_SS*/\r
+#define SPI1_SS_PA6 SYS_GPA_MFPL_PA6MFP_SPI1_SS /*!< GPA_MFPL PA6 setting for SPI1_SS*/\r
+#define SPI1_SS_PH7 SYS_GPH_MFPL_PH7MFP_SPI1_SS /*!< GPH_MFPL PH7 setting for SPI1_SS*/\r
+#define SPI2_CLK_PE8 SYS_GPE_MFPH_PE8MFP_SPI2_CLK /*!< GPE_MFPH PE8 setting for SPI2_CLK*/\r
+#define SPI2_CLK_PG3 SYS_GPG_MFPL_PG3MFP_SPI2_CLK /*!< GPG_MFPL PG3 setting for SPI2_CLK*/\r
+#define SPI2_CLK_PA10 SYS_GPA_MFPH_PA10MFP_SPI2_CLK /*!< GPA_MFPH PA10 setting for SPI2_CLK*/\r
+#define SPI2_CLK_PA13 SYS_GPA_MFPH_PA13MFP_SPI2_CLK /*!< GPA_MFPH PA13 setting for SPI2_CLK*/\r
+#define SPI2_I2SMCLK_PC13 SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK /*!< GPC_MFPH PC13 setting for SPI2_I2SMCLK*/\r
+#define SPI2_I2SMCLK_PE12 SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK /*!< GPE_MFPH PE12 setting for SPI2_I2SMCLK*/\r
+#define SPI2_MISO_PG4 SYS_GPG_MFPL_PG4MFP_SPI2_MISO /*!< GPG_MFPL PG4 setting for SPI2_MISO*/\r
+#define SPI2_MISO_PA9 SYS_GPA_MFPH_PA9MFP_SPI2_MISO /*!< GPA_MFPH PA9 setting for SPI2_MISO*/\r
+#define SPI2_MISO_PA14 SYS_GPA_MFPH_PA14MFP_SPI2_MISO /*!< GPA_MFPH PA14 setting for SPI2_MISO*/\r
+#define SPI2_MISO_PE9 SYS_GPE_MFPH_PE9MFP_SPI2_MISO /*!< GPE_MFPH PE9 setting for SPI2_MISO*/\r
+#define SPI2_MOSI_PE10 SYS_GPE_MFPH_PE10MFP_SPI2_MOSI /*!< GPE_MFPH PE10 setting for SPI2_MOSI*/\r
+#define SPI2_MOSI_PA15 SYS_GPA_MFPH_PA15MFP_SPI2_MOSI /*!< GPA_MFPH PA15 setting for SPI2_MOSI*/\r
+#define SPI2_MOSI_PA8 SYS_GPA_MFPH_PA8MFP_SPI2_MOSI /*!< GPA_MFPH PA8 setting for SPI2_MOSI*/\r
+#define SPI2_MOSI_PF11 SYS_GPF_MFPH_PF11MFP_SPI2_MOSI /*!< GPF_MFPH PF11 setting for SPI2_MOSI*/\r
+#define SPI2_SS_PG2 SYS_GPG_MFPL_PG2MFP_SPI2_SS /*!< GPG_MFPL PG2 setting for SPI2_SS*/\r
+#define SPI2_SS_PE11 SYS_GPE_MFPH_PE11MFP_SPI2_SS /*!< GPE_MFPH PE11 setting for SPI2_SS*/\r
+#define SPI2_SS_PA11 SYS_GPA_MFPH_PA11MFP_SPI2_SS /*!< GPA_MFPH PA11 setting for SPI2_SS*/\r
+#define SPI2_SS_PA12 SYS_GPA_MFPH_PA12MFP_SPI2_SS /*!< GPA_MFPH PA12 setting for SPI2_SS*/\r
+#define SPI3_CLK_PB11 SYS_GPB_MFPH_PB11MFP_SPI3_CLK /*!< GPB_MFPH PB11 setting for SPI3_CLK*/\r
+#define SPI3_CLK_PE4 SYS_GPE_MFPL_PE4MFP_SPI3_CLK /*!< GPE_MFPL PE4 setting for SPI3_CLK*/\r
+#define SPI3_CLK_PC10 SYS_GPC_MFPH_PC10MFP_SPI3_CLK /*!< GPC_MFPH PC10 setting for SPI3_CLK*/\r
+#define SPI3_I2SMCLK_PE6 SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK /*!< GPE_MFPL PE6 setting for SPI3_I2SMCLK*/\r
+#define SPI3_I2SMCLK_PB1 SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK /*!< GPB_MFPL PB1 setting for SPI3_I2SMCLK*/\r
+#define SPI3_I2SMCLK_PD14 SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK /*!< GPD_MFPH PD14 setting for SPI3_I2SMCLK*/\r
+#define SPI3_MISO_PC12 SYS_GPC_MFPH_PC12MFP_SPI3_MISO /*!< GPC_MFPH PC12 setting for SPI3_MISO*/\r
+#define SPI3_MISO_PB9 SYS_GPB_MFPH_PB9MFP_SPI3_MISO /*!< GPB_MFPH PB9 setting for SPI3_MISO*/\r
+#define SPI3_MISO_PE3 SYS_GPE_MFPL_PE3MFP_SPI3_MISO /*!< GPE_MFPL PE3 setting for SPI3_MISO*/\r
+#define SPI3_MOSI_PB8 SYS_GPB_MFPH_PB8MFP_SPI3_MOSI /*!< GPB_MFPH PB8 setting for SPI3_MOSI*/\r
+#define SPI3_MOSI_PE2 SYS_GPE_MFPL_PE2MFP_SPI3_MOSI /*!< GPE_MFPL PE2 setting for SPI3_MOSI*/\r
+#define SPI3_MOSI_PC11 SYS_GPC_MFPH_PC11MFP_SPI3_MOSI /*!< GPC_MFPH PC11 setting for SPI3_MOSI*/\r
+#define SPI3_SS_PE5 SYS_GPE_MFPL_PE5MFP_SPI3_SS /*!< GPE_MFPL PE5 setting for SPI3_SS*/\r
+#define SPI3_SS_PB10 SYS_GPB_MFPH_PB10MFP_SPI3_SS /*!< GPB_MFPH PB10 setting for SPI3_SS*/\r
+#define SPI3_SS_PC9 SYS_GPC_MFPH_PC9MFP_SPI3_SS /*!< GPC_MFPH PC9 setting for SPI3_SS*/\r
+#define TAMPER0_PF6 SYS_GPF_MFPL_PF6MFP_TAMPER0 /*!< GPF_MFPL PF6 setting for TAMPER0*/\r
+#define TAMPER1_PF7 SYS_GPF_MFPL_PF7MFP_TAMPER1 /*!< GPF_MFPL PF7 setting for TAMPER1*/\r
+#define TAMPER2_PF8 SYS_GPF_MFPH_PF8MFP_TAMPER2 /*!< GPF_MFPH PF8 setting for TAMPER2*/\r
+#define TAMPER3_PF9 SYS_GPF_MFPH_PF9MFP_TAMPER3 /*!< GPF_MFPH PF9 setting for TAMPER3*/\r
+#define TAMPER4_PF10 SYS_GPF_MFPH_PF10MFP_TAMPER4 /*!< GPF_MFPH PF10 setting for TAMPER4*/\r
+#define TAMPER5_PF11 SYS_GPF_MFPH_PF11MFP_TAMPER5 /*!< GPF_MFPH PF11 setting for TAMPER5*/\r
+#define TM0_PC7 SYS_GPC_MFPL_PC7MFP_TM0 /*!< GPC_MFPL PC7 setting for TM0*/\r
+#define TM0_PB5 SYS_GPB_MFPL_PB5MFP_TM0 /*!< GPB_MFPL PB5 setting for TM0*/\r
+#define TM0_PG2 SYS_GPG_MFPL_PG2MFP_TM0 /*!< GPG_MFPL PG2 setting for TM0*/\r
+#define TM0_EXT_PA11 SYS_GPA_MFPH_PA11MFP_TM0_EXT /*!< GPA_MFPH PA11 setting for TM0_EXT*/\r
+#define TM0_EXT_PB15 SYS_GPB_MFPH_PB15MFP_TM0_EXT /*!< GPB_MFPH PB15 setting for TM0_EXT*/\r
+#define TM1_PG3 SYS_GPG_MFPL_PG3MFP_TM1 /*!< GPG_MFPL PG3 setting for TM1*/\r
+#define TM1_PB4 SYS_GPB_MFPL_PB4MFP_TM1 /*!< GPB_MFPL PB4 setting for TM1*/\r
+#define TM1_PC6 SYS_GPC_MFPL_PC6MFP_TM1 /*!< GPC_MFPL PC6 setting for TM1*/\r
+#define TM1_EXT_PA10 SYS_GPA_MFPH_PA10MFP_TM1_EXT /*!< GPA_MFPH PA10 setting for TM1_EXT*/\r
+#define TM1_EXT_PB14 SYS_GPB_MFPH_PB14MFP_TM1_EXT /*!< GPB_MFPH PB14 setting for TM1_EXT*/\r
+#define TM2_PG4 SYS_GPG_MFPL_PG4MFP_TM2 /*!< GPG_MFPL PG4 setting for TM2*/\r
+#define TM2_PD0 SYS_GPD_MFPL_PD0MFP_TM2 /*!< GPD_MFPL PD0 setting for TM2*/\r
+#define TM2_PB3 SYS_GPB_MFPL_PB3MFP_TM2 /*!< GPB_MFPL PB3 setting for TM2*/\r
+#define TM2_PA7 SYS_GPA_MFPL_PA7MFP_TM2 /*!< GPA_MFPL PA7 setting for TM2*/\r
+#define TM2_EXT_PB13 SYS_GPB_MFPH_PB13MFP_TM2_EXT /*!< GPB_MFPH PB13 setting for TM2_EXT*/\r
+#define TM2_EXT_PA9 SYS_GPA_MFPH_PA9MFP_TM2_EXT /*!< GPA_MFPH PA9 setting for TM2_EXT*/\r
+#define TM3_PA6 SYS_GPA_MFPL_PA6MFP_TM3 /*!< GPA_MFPL PA6 setting for TM3*/\r
+#define TM3_PF11 SYS_GPF_MFPH_PF11MFP_TM3 /*!< GPF_MFPH PF11 setting for TM3*/\r
+#define TM3_PB2 SYS_GPB_MFPL_PB2MFP_TM3 /*!< GPB_MFPL PB2 setting for TM3*/\r
+#define TM3_EXT_PA8 SYS_GPA_MFPH_PA8MFP_TM3_EXT /*!< GPA_MFPH PA8 setting for TM3_EXT*/\r
+#define TM3_EXT_PB12 SYS_GPB_MFPH_PB12MFP_TM3_EXT /*!< GPB_MFPH PB12 setting for TM3_EXT*/\r
+#define TRACE_CLK_PE12 SYS_GPE_MFPH_PE12MFP_TRACE_CLK /*!< GPE_MFPH PE12 setting for TRACE_CLK*/\r
+#define TRACE_DATA0_PE11 SYS_GPE_MFPH_PE11MFP_TRACE_DATA0 /*!< GPE_MFPH PE11 setting for TRACE_DATA0*/\r
+#define TRACE_DATA1_PE10 SYS_GPE_MFPH_PE10MFP_TRACE_DATA1 /*!< GPE_MFPH PE10 setting for TRACE_DATA1*/\r
+#define TRACE_DATA2_PE9 SYS_GPE_MFPH_PE9MFP_TRACE_DATA2 /*!< GPE_MFPH PE9 setting for TRACE_DATA2*/\r
+#define TRACE_DATA3_PE8 SYS_GPE_MFPH_PE8MFP_TRACE_DATA3 /*!< GPE_MFPH PE8 setting for TRACE_DATA3*/\r
+#define UART0_RXD_PD2 SYS_GPD_MFPL_PD2MFP_UART0_RXD /*!< GPD_MFPL PD2 setting for UART0_RXD*/\r
+#define UART0_RXD_PB8 SYS_GPB_MFPH_PB8MFP_UART0_RXD /*!< GPB_MFPH PB8 setting for UART0_RXD*/\r
+#define UART0_RXD_PA0 SYS_GPA_MFPL_PA0MFP_UART0_RXD /*!< GPA_MFPL PA0 setting for UART0_RXD*/\r
+#define UART0_RXD_PA6 SYS_GPA_MFPL_PA6MFP_UART0_RXD /*!< GPA_MFPL PA6 setting for UART0_RXD*/\r
+#define UART0_RXD_PB12 SYS_GPB_MFPH_PB12MFP_UART0_RXD /*!< GPB_MFPH PB12 setting for UART0_RXD*/\r
+#define UART0_RXD_PA15 SYS_GPA_MFPH_PA15MFP_UART0_RXD /*!< GPA_MFPH PA15 setting for UART0_RXD*/\r
+#define UART0_RXD_PC11 SYS_GPC_MFPH_PC11MFP_UART0_RXD /*!< GPC_MFPH PC11 setting for UART0_RXD*/\r
+#define UART0_RXD_PH11 SYS_GPH_MFPH_PH11MFP_UART0_RXD /*!< GPH_MFPH PH11 setting for UART0_RXD*/\r
+#define UART0_RXD_PF2 SYS_GPF_MFPL_PF2MFP_UART0_RXD /*!< GPF_MFPL PF2 setting for UART0_RXD*/\r
+#define UART0_TXD_PA7 SYS_GPA_MFPL_PA7MFP_UART0_TXD /*!< GPA_MFPL PA7 setting for UART0_TXD*/\r
+#define UART0_TXD_PD3 SYS_GPD_MFPL_PD3MFP_UART0_TXD /*!< GPD_MFPL PD3 setting for UART0_TXD*/\r
+#define UART0_TXD_PF3 SYS_GPF_MFPL_PF3MFP_UART0_TXD /*!< GPF_MFPL PF3 setting for UART0_TXD*/\r
+#define UART0_TXD_PC12 SYS_GPC_MFPH_PC12MFP_UART0_TXD /*!< GPC_MFPH PC12 setting for UART0_TXD*/\r
+#define UART0_TXD_PH10 SYS_GPH_MFPH_PH10MFP_UART0_TXD /*!< GPH_MFPH PH10 setting for UART0_TXD*/\r
+#define UART0_TXD_PA1 SYS_GPA_MFPL_PA1MFP_UART0_TXD /*!< GPA_MFPL PA1 setting for UART0_TXD*/\r
+#define UART0_TXD_PB9 SYS_GPB_MFPH_PB9MFP_UART0_TXD /*!< GPB_MFPH PB9 setting for UART0_TXD*/\r
+#define UART0_TXD_PB13 SYS_GPB_MFPH_PB13MFP_UART0_TXD /*!< GPB_MFPH PB13 setting for UART0_TXD*/\r
+#define UART0_TXD_PA14 SYS_GPA_MFPH_PA14MFP_UART0_TXD /*!< GPA_MFPH PA14 setting for UART0_TXD*/\r
+#define UART0_nCTS_PA5 SYS_GPA_MFPL_PA5MFP_UART0_nCTS /*!< GPA_MFPL PA5 setting for UART0_nCTS*/\r
+#define UART0_nCTS_PB11 SYS_GPB_MFPH_PB11MFP_UART0_nCTS /*!< GPB_MFPH PB11 setting for UART0_nCTS*/\r
+#define UART0_nCTS_PB15 SYS_GPB_MFPH_PB15MFP_UART0_nCTS /*!< GPB_MFPH PB15 setting for UART0_nCTS*/\r
+#define UART0_nCTS_PC7 SYS_GPC_MFPL_PC7MFP_UART0_nCTS /*!< GPC_MFPL PC7 setting for UART0_nCTS*/\r
+#define UART0_nRTS_PB14 SYS_GPB_MFPH_PB14MFP_UART0_nRTS /*!< GPB_MFPH PB14 setting for UART0_nRTS*/\r
+#define UART0_nRTS_PB10 SYS_GPB_MFPH_PB10MFP_UART0_nRTS /*!< GPB_MFPH PB10 setting for UART0_nRTS*/\r
+#define UART0_nRTS_PC6 SYS_GPC_MFPL_PC6MFP_UART0_nRTS /*!< GPC_MFPL PC6 setting for UART0_nRTS*/\r
+#define UART0_nRTS_PA4 SYS_GPA_MFPL_PA4MFP_UART0_nRTS /*!< GPA_MFPL PA4 setting for UART0_nRTS*/\r
+#define UART1_RXD_PF1 SYS_GPF_MFPL_PF1MFP_UART1_RXD /*!< GPF_MFPL PF1 setting for UART1_RXD*/\r
+#define UART1_RXD_PA8 SYS_GPA_MFPH_PA8MFP_UART1_RXD /*!< GPA_MFPH PA8 setting for UART1_RXD*/\r
+#define UART1_RXD_PA2 SYS_GPA_MFPL_PA2MFP_UART1_RXD /*!< GPA_MFPL PA2 setting for UART1_RXD*/\r
+#define UART1_RXD_PB2 SYS_GPB_MFPL_PB2MFP_UART1_RXD /*!< GPB_MFPL PB2 setting for UART1_RXD*/\r
+#define UART1_RXD_PB6 SYS_GPB_MFPL_PB6MFP_UART1_RXD /*!< GPB_MFPL PB6 setting for UART1_RXD*/\r
+#define UART1_RXD_PD6 SYS_GPD_MFPL_PD6MFP_UART1_RXD /*!< GPD_MFPL PD6 setting for UART1_RXD*/\r
+#define UART1_RXD_PD10 SYS_GPD_MFPH_PD10MFP_UART1_RXD /*!< GPD_MFPH PD10 setting for UART1_RXD*/\r
+#define UART1_RXD_PH9 SYS_GPH_MFPH_PH9MFP_UART1_RXD /*!< GPH_MFPH PH9 setting for UART1_RXD*/\r
+#define UART1_RXD_PC8 SYS_GPC_MFPH_PC8MFP_UART1_RXD /*!< GPC_MFPH PC8 setting for UART1_RXD*/\r
+#define UART1_TXD_PB3 SYS_GPB_MFPL_PB3MFP_UART1_TXD /*!< GPB_MFPL PB3 setting for UART1_TXD*/\r
+#define UART1_TXD_PA3 SYS_GPA_MFPL_PA3MFP_UART1_TXD /*!< GPA_MFPL PA3 setting for UART1_TXD*/\r
+#define UART1_TXD_PE13 SYS_GPE_MFPH_PE13MFP_UART1_TXD /*!< GPE_MFPH PE13 setting for UART1_TXD*/\r
+#define UART1_TXD_PA9 SYS_GPA_MFPH_PA9MFP_UART1_TXD /*!< GPA_MFPH PA9 setting for UART1_TXD*/\r
+#define UART1_TXD_PF0 SYS_GPF_MFPL_PF0MFP_UART1_TXD /*!< GPF_MFPL PF0 setting for UART1_TXD*/\r
+#define UART1_TXD_PD11 SYS_GPD_MFPH_PD11MFP_UART1_TXD /*!< GPD_MFPH PD11 setting for UART1_TXD*/\r
+#define UART1_TXD_PD7 SYS_GPD_MFPL_PD7MFP_UART1_TXD /*!< GPD_MFPL PD7 setting for UART1_TXD*/\r
+#define UART1_TXD_PB7 SYS_GPB_MFPL_PB7MFP_UART1_TXD /*!< GPB_MFPL PB7 setting for UART1_TXD*/\r
+#define UART1_TXD_PH8 SYS_GPH_MFPH_PH8MFP_UART1_TXD /*!< GPH_MFPH PH8 setting for UART1_TXD*/\r
+#define UART1_nCTS_PE11 SYS_GPE_MFPH_PE11MFP_UART1_nCTS /*!< GPE_MFPH PE11 setting for UART1_nCTS*/\r
+#define UART1_nCTS_PB9 SYS_GPB_MFPH_PB9MFP_UART1_nCTS /*!< GPB_MFPH PB9 setting for UART1_nCTS*/\r
+#define UART1_nCTS_PA1 SYS_GPA_MFPL_PA1MFP_UART1_nCTS /*!< GPA_MFPL PA1 setting for UART1_nCTS*/\r
+#define UART1_nRTS_PA0 SYS_GPA_MFPL_PA0MFP_UART1_nRTS /*!< GPA_MFPL PA0 setting for UART1_nRTS*/\r
+#define UART1_nRTS_PE12 SYS_GPE_MFPH_PE12MFP_UART1_nRTS /*!< GPE_MFPH PE12 setting for UART1_nRTS*/\r
+#define UART1_nRTS_PB8 SYS_GPB_MFPH_PB8MFP_UART1_nRTS /*!< GPB_MFPH PB8 setting for UART1_nRTS*/\r
+#define UART2_RXD_PB0 SYS_GPB_MFPL_PB0MFP_UART2_RXD /*!< GPB_MFPL PB0 setting for UART2_RXD*/\r
+#define UART2_RXD_PE15 SYS_GPE_MFPH_PE15MFP_UART2_RXD /*!< GPE_MFPH PE15 setting for UART2_RXD*/\r
+#define UART2_RXD_PD12 SYS_GPD_MFPH_PD12MFP_UART2_RXD /*!< GPD_MFPH PD12 setting for UART2_RXD*/\r
+#define UART2_RXD_PF5 SYS_GPF_MFPL_PF5MFP_UART2_RXD /*!< GPF_MFPL PF5 setting for UART2_RXD*/\r
+#define UART2_RXD_PC0 SYS_GPC_MFPL_PC0MFP_UART2_RXD /*!< GPC_MFPL PC0 setting for UART2_RXD*/\r
+#define UART2_RXD_PC4 SYS_GPC_MFPL_PC4MFP_UART2_RXD /*!< GPC_MFPL PC4 setting for UART2_RXD*/\r
+#define UART2_RXD_PE9 SYS_GPE_MFPH_PE9MFP_UART2_RXD /*!< GPE_MFPH PE9 setting for UART2_RXD*/\r
+#define UART2_TXD_PE8 SYS_GPE_MFPH_PE8MFP_UART2_TXD /*!< GPE_MFPH PE8 setting for UART2_TXD*/\r
+#define UART2_TXD_PF4 SYS_GPF_MFPL_PF4MFP_UART2_TXD /*!< GPF_MFPL PF4 setting for UART2_TXD*/\r
+#define UART2_TXD_PC13 SYS_GPC_MFPH_PC13MFP_UART2_TXD /*!< GPC_MFPH PC13 setting for UART2_TXD*/\r
+#define UART2_TXD_PC1 SYS_GPC_MFPL_PC1MFP_UART2_TXD /*!< GPC_MFPL PC1 setting for UART2_TXD*/\r
+#define UART2_TXD_PE14 SYS_GPE_MFPH_PE14MFP_UART2_TXD /*!< GPE_MFPH PE14 setting for UART2_TXD*/\r
+#define UART2_TXD_PC5 SYS_GPC_MFPL_PC5MFP_UART2_TXD /*!< GPC_MFPL PC5 setting for UART2_TXD*/\r
+#define UART2_TXD_PB1 SYS_GPB_MFPL_PB1MFP_UART2_TXD /*!< GPB_MFPL PB1 setting for UART2_TXD*/\r
+#define UART2_nCTS_PF5 SYS_GPF_MFPL_PF5MFP_UART2_nCTS /*!< GPF_MFPL PF5 setting for UART2_nCTS*/\r
+#define UART2_nCTS_PD9 SYS_GPD_MFPH_PD9MFP_UART2_nCTS /*!< GPD_MFPH PD9 setting for UART2_nCTS*/\r
+#define UART2_nCTS_PC2 SYS_GPC_MFPL_PC2MFP_UART2_nCTS /*!< GPC_MFPL PC2 setting for UART2_nCTS*/\r
+#define UART2_nRTS_PF4 SYS_GPF_MFPL_PF4MFP_UART2_nRTS /*!< GPF_MFPL PF4 setting for UART2_nRTS*/\r
+#define UART2_nRTS_PD8 SYS_GPD_MFPH_PD8MFP_UART2_nRTS /*!< GPD_MFPH PD8 setting for UART2_nRTS*/\r
+#define UART2_nRTS_PC3 SYS_GPC_MFPL_PC3MFP_UART2_nRTS /*!< GPC_MFPL PC3 setting for UART2_nRTS*/\r
+#define UART3_RXD_PD0 SYS_GPD_MFPL_PD0MFP_UART3_RXD /*!< GPD_MFPL PD0 setting for UART3_RXD*/\r
+#define UART3_RXD_PE11 SYS_GPE_MFPH_PE11MFP_UART3_RXD /*!< GPE_MFPH PE11 setting for UART3_RXD*/\r
+#define UART3_RXD_PC9 SYS_GPC_MFPH_PC9MFP_UART3_RXD /*!< GPC_MFPH PC9 setting for UART3_RXD*/\r
+#define UART3_RXD_PE0 SYS_GPE_MFPL_PE0MFP_UART3_RXD /*!< GPE_MFPL PE0 setting for UART3_RXD*/\r
+#define UART3_RXD_PC2 SYS_GPC_MFPL_PC2MFP_UART3_RXD /*!< GPC_MFPL PC2 setting for UART3_RXD*/\r
+#define UART3_RXD_PB14 SYS_GPB_MFPH_PB14MFP_UART3_RXD /*!< GPB_MFPH PB14 setting for UART3_RXD*/\r
+#define UART3_TXD_PD1 SYS_GPD_MFPL_PD1MFP_UART3_TXD /*!< GPD_MFPL PD1 setting for UART3_TXD*/\r
+#define UART3_TXD_PC10 SYS_GPC_MFPH_PC10MFP_UART3_TXD /*!< GPC_MFPH PC10 setting for UART3_TXD*/\r
+#define UART3_TXD_PB15 SYS_GPB_MFPH_PB15MFP_UART3_TXD /*!< GPB_MFPH PB15 setting for UART3_TXD*/\r
+#define UART3_TXD_PC3 SYS_GPC_MFPL_PC3MFP_UART3_TXD /*!< GPC_MFPL PC3 setting for UART3_TXD*/\r
+#define UART3_TXD_PE1 SYS_GPE_MFPL_PE1MFP_UART3_TXD /*!< GPE_MFPL PE1 setting for UART3_TXD*/\r
+#define UART3_TXD_PE10 SYS_GPE_MFPH_PE10MFP_UART3_TXD /*!< GPE_MFPH PE10 setting for UART3_TXD*/\r
+#define UART3_nCTS_PB12 SYS_GPB_MFPH_PB12MFP_UART3_nCTS /*!< GPB_MFPH PB12 setting for UART3_nCTS*/\r
+#define UART3_nCTS_PH9 SYS_GPH_MFPH_PH9MFP_UART3_nCTS /*!< GPH_MFPH PH9 setting for UART3_nCTS*/\r
+#define UART3_nCTS_PD2 SYS_GPD_MFPL_PD2MFP_UART3_nCTS /*!< GPD_MFPL PD2 setting for UART3_nCTS*/\r
+#define UART3_nRTS_PB13 SYS_GPB_MFPH_PB13MFP_UART3_nRTS /*!< GPB_MFPH PB13 setting for UART3_nRTS*/\r
+#define UART3_nRTS_PH8 SYS_GPH_MFPH_PH8MFP_UART3_nRTS /*!< GPH_MFPH PH8 setting for UART3_nRTS*/\r
+#define UART3_nRTS_PD3 SYS_GPD_MFPL_PD3MFP_UART3_nRTS /*!< GPD_MFPL PD3 setting for UART3_nRTS*/\r
+#define UART4_RXD_PA13 SYS_GPA_MFPH_PA13MFP_UART4_RXD /*!< GPA_MFPH PA13 setting for UART4_RXD*/\r
+#define UART4_RXD_PC6 SYS_GPC_MFPL_PC6MFP_UART4_RXD /*!< GPC_MFPL PC6 setting for UART4_RXD*/\r
+#define UART4_RXD_PC4 SYS_GPC_MFPL_PC4MFP_UART4_RXD /*!< GPC_MFPL PC4 setting for UART4_RXD*/\r
+#define UART4_RXD_PB10 SYS_GPB_MFPH_PB10MFP_UART4_RXD /*!< GPB_MFPH PB10 setting for UART4_RXD*/\r
+#define UART4_RXD_PH11 SYS_GPH_MFPH_PH11MFP_UART4_RXD /*!< GPH_MFPH PH11 setting for UART4_RXD*/\r
+#define UART4_RXD_PA2 SYS_GPA_MFPL_PA2MFP_UART4_RXD /*!< GPA_MFPL PA2 setting for UART4_RXD*/\r
+#define UART4_RXD_PF6 SYS_GPF_MFPL_PF6MFP_UART4_RXD /*!< GPF_MFPL PF6 setting for UART4_RXD*/\r
+#define UART4_TXD_PH10 SYS_GPH_MFPH_PH10MFP_UART4_TXD /*!< GPH_MFPH PH10 setting for UART4_TXD*/\r
+#define UART4_TXD_PA3 SYS_GPA_MFPL_PA3MFP_UART4_TXD /*!< GPA_MFPL PA3 setting for UART4_TXD*/\r
+#define UART4_TXD_PA12 SYS_GPA_MFPH_PA12MFP_UART4_TXD /*!< GPA_MFPH PA12 setting for UART4_TXD*/\r
+#define UART4_TXD_PC7 SYS_GPC_MFPL_PC7MFP_UART4_TXD /*!< GPC_MFPL PC7 setting for UART4_TXD*/\r
+#define UART4_TXD_PB11 SYS_GPB_MFPH_PB11MFP_UART4_TXD /*!< GPB_MFPH PB11 setting for UART4_TXD*/\r
+#define UART4_TXD_PF7 SYS_GPF_MFPL_PF7MFP_UART4_TXD /*!< GPF_MFPL PF7 setting for UART4_TXD*/\r
+#define UART4_TXD_PC5 SYS_GPC_MFPL_PC5MFP_UART4_TXD /*!< GPC_MFPL PC5 setting for UART4_TXD*/\r
+#define UART4_nCTS_PE1 SYS_GPE_MFPL_PE1MFP_UART4_nCTS /*!< GPE_MFPL PE1 setting for UART4_nCTS*/\r
+#define UART4_nCTS_PC8 SYS_GPC_MFPH_PC8MFP_UART4_nCTS /*!< GPC_MFPH PC8 setting for UART4_nCTS*/\r
+#define UART4_nRTS_PE0 SYS_GPE_MFPL_PE0MFP_UART4_nRTS /*!< GPE_MFPL PE0 setting for UART4_nRTS*/\r
+#define UART4_nRTS_PE13 SYS_GPE_MFPH_PE13MFP_UART4_nRTS /*!< GPE_MFPH PE13 setting for UART4_nRTS*/\r
+#define UART5_RXD_PB4 SYS_GPB_MFPL_PB4MFP_UART5_RXD /*!< GPB_MFPL PB4 setting for UART5_RXD*/\r
+#define UART5_RXD_PA4 SYS_GPA_MFPL_PA4MFP_UART5_RXD /*!< GPA_MFPL PA4 setting for UART5_RXD*/\r
+#define UART5_RXD_PE6 SYS_GPE_MFPL_PE6MFP_UART5_RXD /*!< GPE_MFPL PE6 setting for UART5_RXD*/\r
+#define UART5_TXD_PB5 SYS_GPB_MFPL_PB5MFP_UART5_TXD /*!< GPB_MFPL PB5 setting for UART5_TXD*/\r
+#define UART5_TXD_PE7 SYS_GPE_MFPL_PE7MFP_UART5_TXD /*!< GPE_MFPL PE7 setting for UART5_TXD*/\r
+#define UART5_TXD_PA5 SYS_GPA_MFPL_PA5MFP_UART5_TXD /*!< GPA_MFPL PA5 setting for UART5_TXD*/\r
+#define UART5_nCTS_PB2 SYS_GPB_MFPL_PB2MFP_UART5_nCTS /*!< GPB_MFPL PB2 setting for UART5_nCTS*/\r
+#define UART5_nRTS_PB3 SYS_GPB_MFPL_PB3MFP_UART5_nRTS /*!< GPB_MFPL PB3 setting for UART5_nRTS*/\r
+#define USB_D_P_PA14 SYS_GPA_MFPH_PA14MFP_USB_D_P /*!< GPA_MFPH PA14 setting for USB_D_P*/\r
+#define USB_D_N_PA13 SYS_GPA_MFPH_PA13MFP_USB_D_N /*!< GPA_MFPH PA13 setting for USB_D_N*/\r
+#define USB_OTG_ID_PA15 SYS_GPA_MFPH_PA15MFP_USB_OTG_ID /*!< GPA_MFPH PA15 setting for USB_OTG_ID*/\r
+#define USB_VBUS_PA12 SYS_GPA_MFPH_PA12MFP_USB_VBUS /*!< GPA_MFPH PA12 setting for USB_VBUS*/\r
+#define USB_VBUS_EN_PB6 SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN /*!< GPB_MFPL PB6 setting for USB_VBUS_EN*/\r
+#define USB_VBUS_EN_PB15 SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN /*!< GPB_MFPH PB15 setting for USB_VBUS_EN*/\r
+#define USB_VBUS_ST_PB14 SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST /*!< GPB_MFPH PB14 setting for USB_VBUS_ST*/\r
+#define USB_VBUS_ST_PB7 SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST /*!< GPB_MFPL PB7 setting for USB_VBUS_ST*/\r
+#define USB_VBUS_ST_PD4 SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST /*!< GPD_MFPL PD4 setting for USB_VBUS_ST*/\r
+#define USCI0_CLK_PD0 SYS_GPD_MFPL_PD0MFP_USCI0_CLK /*!< GPD_MFPL PD0 setting for USCI0_CLK*/\r
+#define USCI0_CLK_PA11 SYS_GPA_MFPH_PA11MFP_USCI0_CLK /*!< GPA_MFPH PA11 setting for USCI0_CLK*/\r
+#define USCI0_CLK_PE2 SYS_GPE_MFPL_PE2MFP_USCI0_CLK /*!< GPE_MFPL PE2 setting for USCI0_CLK*/\r
+#define USCI0_CLK_PB12 SYS_GPB_MFPH_PB12MFP_USCI0_CLK /*!< GPB_MFPH PB12 setting for USCI0_CLK*/\r
+#define USCI0_CTL0_PD4 SYS_GPD_MFPL_PD4MFP_USCI0_CTL0 /*!< GPD_MFPL PD4 setting for USCI0_CTL0*/\r
+#define USCI0_CTL0_PE6 SYS_GPE_MFPL_PE6MFP_USCI0_CTL0 /*!< GPE_MFPL PE6 setting for USCI0_CTL0*/\r
+#define USCI0_CTL0_PC13 SYS_GPC_MFPH_PC13MFP_USCI0_CTL0 /*!< GPC_MFPH PC13 setting for USCI0_CTL0*/\r
+#define USCI0_CTL0_PD14 SYS_GPD_MFPH_PD14MFP_USCI0_CTL0 /*!< GPD_MFPH PD14 setting for USCI0_CTL0*/\r
+#define USCI0_CTL1_PD3 SYS_GPD_MFPL_PD3MFP_USCI0_CTL1 /*!< GPD_MFPL PD3 setting for USCI0_CTL1*/\r
+#define USCI0_CTL1_PE5 SYS_GPE_MFPL_PE5MFP_USCI0_CTL1 /*!< GPE_MFPL PE5 setting for USCI0_CTL1*/\r
+#define USCI0_CTL1_PB15 SYS_GPB_MFPH_PB15MFP_USCI0_CTL1 /*!< GPB_MFPH PB15 setting for USCI0_CTL1*/\r
+#define USCI0_CTL1_PA8 SYS_GPA_MFPH_PA8MFP_USCI0_CTL1 /*!< GPA_MFPH PA8 setting for USCI0_CTL1*/\r
+#define USCI0_DAT0_PE3 SYS_GPE_MFPL_PE3MFP_USCI0_DAT0 /*!< GPE_MFPL PE3 setting for USCI0_DAT0*/\r
+#define USCI0_DAT0_PB13 SYS_GPB_MFPH_PB13MFP_USCI0_DAT0 /*!< GPB_MFPH PB13 setting for USCI0_DAT0*/\r
+#define USCI0_DAT0_PD1 SYS_GPD_MFPL_PD1MFP_USCI0_DAT0 /*!< GPD_MFPL PD1 setting for USCI0_DAT0*/\r
+#define USCI0_DAT0_PA10 SYS_GPA_MFPH_PA10MFP_USCI0_DAT0 /*!< GPA_MFPH PA10 setting for USCI0_DAT0*/\r
+#define USCI0_DAT1_PE4 SYS_GPE_MFPL_PE4MFP_USCI0_DAT1 /*!< GPE_MFPL PE4 setting for USCI0_DAT1*/\r
+#define USCI0_DAT1_PD2 SYS_GPD_MFPL_PD2MFP_USCI0_DAT1 /*!< GPD_MFPL PD2 setting for USCI0_DAT1*/\r
+#define USCI0_DAT1_PB14 SYS_GPB_MFPH_PB14MFP_USCI0_DAT1 /*!< GPB_MFPH PB14 setting for USCI0_DAT1*/\r
+#define USCI0_DAT1_PA9 SYS_GPA_MFPH_PA9MFP_USCI0_DAT1 /*!< GPA_MFPH PA9 setting for USCI0_DAT1*/\r
+#define USCI1_CLK_PE12 SYS_GPE_MFPH_PE12MFP_USCI1_CLK /*!< GPE_MFPH PE12 setting for USCI1_CLK*/\r
+#define USCI1_CLK_PD7 SYS_GPD_MFPL_PD7MFP_USCI1_CLK /*!< GPD_MFPL PD7 setting for USCI1_CLK*/\r
+#define USCI1_CLK_PB8 SYS_GPB_MFPH_PB8MFP_USCI1_CLK /*!< GPB_MFPH PB8 setting for USCI1_CLK*/\r
+#define USCI1_CLK_PB1 SYS_GPB_MFPL_PB1MFP_USCI1_CLK /*!< GPB_MFPL PB1 setting for USCI1_CLK*/\r
+#define USCI1_CTL0_PB10 SYS_GPB_MFPH_PB10MFP_USCI1_CTL0 /*!< GPB_MFPH PB10 setting for USCI1_CTL0*/\r
+#define USCI1_CTL0_PB5 SYS_GPB_MFPL_PB5MFP_USCI1_CTL0 /*!< GPB_MFPL PB5 setting for USCI1_CTL0*/\r
+#define USCI1_CTL0_PE9 SYS_GPE_MFPH_PE9MFP_USCI1_CTL0 /*!< GPE_MFPH PE9 setting for USCI1_CTL0*/\r
+#define USCI1_CTL0_PD3 SYS_GPD_MFPL_PD3MFP_USCI1_CTL0 /*!< GPD_MFPL PD3 setting for USCI1_CTL0*/\r
+#define USCI1_CTL1_PD4 SYS_GPD_MFPL_PD4MFP_USCI1_CTL1 /*!< GPD_MFPL PD4 setting for USCI1_CTL1*/\r
+#define USCI1_CTL1_PE8 SYS_GPE_MFPH_PE8MFP_USCI1_CTL1 /*!< GPE_MFPH PE8 setting for USCI1_CTL1*/\r
+#define USCI1_CTL1_PB9 SYS_GPB_MFPH_PB9MFP_USCI1_CTL1 /*!< GPB_MFPH PB9 setting for USCI1_CTL1*/\r
+#define USCI1_CTL1_PB4 SYS_GPB_MFPL_PB4MFP_USCI1_CTL1 /*!< GPB_MFPL PB4 setting for USCI1_CTL1*/\r
+#define USCI1_DAT0_PB2 SYS_GPB_MFPL_PB2MFP_USCI1_DAT0 /*!< GPB_MFPL PB2 setting for USCI1_DAT0*/\r
+#define USCI1_DAT0_PB7 SYS_GPB_MFPL_PB7MFP_USCI1_DAT0 /*!< GPB_MFPL PB7 setting for USCI1_DAT0*/\r
+#define USCI1_DAT0_PE10 SYS_GPE_MFPH_PE10MFP_USCI1_DAT0 /*!< GPE_MFPH PE10 setting for USCI1_DAT0*/\r
+#define USCI1_DAT0_PD5 SYS_GPD_MFPL_PD5MFP_USCI1_DAT0 /*!< GPD_MFPL PD5 setting for USCI1_DAT0*/\r
+#define USCI1_DAT1_PD6 SYS_GPD_MFPL_PD6MFP_USCI1_DAT1 /*!< GPD_MFPL PD6 setting for USCI1_DAT1*/\r
+#define USCI1_DAT1_PB3 SYS_GPB_MFPL_PB3MFP_USCI1_DAT1 /*!< GPB_MFPL PB3 setting for USCI1_DAT1*/\r
+#define USCI1_DAT1_PE11 SYS_GPE_MFPH_PE11MFP_USCI1_DAT1 /*!< GPE_MFPH PE11 setting for USCI1_DAT1*/\r
+#define USCI1_DAT1_PB6 SYS_GPB_MFPL_PB6MFP_USCI1_DAT1 /*!< GPB_MFPL PB6 setting for USCI1_DAT1*/\r
+#define X32_IN_PF5 SYS_GPF_MFPL_PF5MFP_X32_IN /*!< GPF_MFPL PF5 setting for X32_IN*/\r
+#define X32_OUT_PF4 SYS_GPF_MFPL_PF4MFP_X32_OUT /*!< GPF_MFPL PF4 setting for X32_OUT*/\r
+#define XT1_IN_PF3 SYS_GPF_MFPL_PF3MFP_XT1_IN /*!< GPF_MFPL PF3 setting for XT1_IN*/\r
+#define XT1_OUT_PF2 SYS_GPF_MFPL_PF2MFP_XT1_OUT /*!< GPF_MFPL PF2 setting for XT1_OUT*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Multi-Function setting mask constant definitions abbreviation. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+\r
+\r
+#define ACMP0_N_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! ACMP0_N PB3 MFP Mask */\r
+#define ACMP0_O_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! ACMP0_O PB7 MFP Mask */\r
+#define ACMP0_O_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! ACMP0_O PC1 MFP Mask */\r
+#define ACMP0_O_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! ACMP0_O PC12 MFP Mask */\r
+#define ACMP0_P0_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! ACMP0_P0 PA11 MFP Mask */\r
+#define ACMP0_P1_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! ACMP0_P1 PB2 MFP Mask */\r
+#define ACMP0_P2_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! ACMP0_P2 PB12 MFP Mask */\r
+#define ACMP0_P3_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! ACMP0_P3 PB13 MFP Mask */\r
+#define ACMP0_WLAT_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! ACMP0_WLAT PA7 MFP Mask */\r
+#define ACMP1_N_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! ACMP1_N PB5 MFP Mask */\r
+#define ACMP1_O_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! ACMP1_O PB6 MFP Mask */\r
+#define ACMP1_O_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! ACMP1_O PC11 MFP Mask */\r
+#define ACMP1_O_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! ACMP1_O PC0 MFP Mask */\r
+#define ACMP1_P0_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! ACMP1_P0 PA10 MFP Mask */\r
+#define ACMP1_P1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! ACMP1_P1 PB4 MFP Mask */\r
+#define ACMP1_P2_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! ACMP1_P2 PB12 MFP Mask */\r
+#define ACMP1_P3_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! ACMP1_P3 PB13 MFP Mask */\r
+#define ACMP1_WLAT_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! ACMP1_WLAT PA6 MFP Mask */\r
+#define BPWM0_CH0_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! BPWM0_CH0 PA0 MFP Mask */\r
+#define BPWM0_CH0_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! BPWM0_CH0 PA11 MFP Mask */\r
+#define BPWM0_CH0_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! BPWM0_CH0 PE2 MFP Mask */\r
+#define BPWM0_CH0_PG14_Msk SYS_GPG_MFPH_PG14MFP_Msk /*<! BPWM0_CH0 PG14 MFP Mask */\r
+#define BPWM0_CH1_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! BPWM0_CH1 PA1 MFP Mask */\r
+#define BPWM0_CH1_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! BPWM0_CH1 PE3 MFP Mask */\r
+#define BPWM0_CH1_PG13_Msk SYS_GPG_MFPH_PG13MFP_Msk /*<! BPWM0_CH1 PG13 MFP Mask */\r
+#define BPWM0_CH1_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! BPWM0_CH1 PA10 MFP Mask */\r
+#define BPWM0_CH2_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! BPWM0_CH2 PE4 MFP Mask */\r
+#define BPWM0_CH2_PG12_Msk SYS_GPG_MFPH_PG12MFP_Msk /*<! BPWM0_CH2 PG12 MFP Mask */\r
+#define BPWM0_CH2_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! BPWM0_CH2 PA2 MFP Mask */\r
+#define BPWM0_CH2_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! BPWM0_CH2 PA9 MFP Mask */\r
+#define BPWM0_CH3_PG11_Msk SYS_GPG_MFPH_PG11MFP_Msk /*<! BPWM0_CH3 PG11 MFP Mask */\r
+#define BPWM0_CH3_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! BPWM0_CH3 PA3 MFP Mask */\r
+#define BPWM0_CH3_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! BPWM0_CH3 PA8 MFP Mask */\r
+#define BPWM0_CH3_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! BPWM0_CH3 PE5 MFP Mask */\r
+#define BPWM0_CH4_PG10_Msk SYS_GPG_MFPH_PG10MFP_Msk /*<! BPWM0_CH4 PG10 MFP Mask */\r
+#define BPWM0_CH4_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! BPWM0_CH4 PA4 MFP Mask */\r
+#define BPWM0_CH4_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! BPWM0_CH4 PC13 MFP Mask */\r
+#define BPWM0_CH4_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! BPWM0_CH4 PE6 MFP Mask */\r
+#define BPWM0_CH4_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! BPWM0_CH4 PF5 MFP Mask */\r
+#define BPWM0_CH5_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! BPWM0_CH5 PA5 MFP Mask */\r
+#define BPWM0_CH5_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! BPWM0_CH5 PE7 MFP Mask */\r
+#define BPWM0_CH5_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! BPWM0_CH5 PF4 MFP Mask */\r
+#define BPWM0_CH5_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! BPWM0_CH5 PD12 MFP Mask */\r
+#define BPWM0_CH5_PG9_Msk SYS_GPG_MFPH_PG9MFP_Msk /*<! BPWM0_CH5 PG9 MFP Mask */\r
+#define BPWM1_CH0_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! BPWM1_CH0 PB11 MFP Mask */\r
+#define BPWM1_CH0_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! BPWM1_CH0 PC7 MFP Mask */\r
+#define BPWM1_CH0_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! BPWM1_CH0 PF0 MFP Mask */\r
+#define BPWM1_CH0_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! BPWM1_CH0 PF3 MFP Mask */\r
+#define BPWM1_CH1_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! BPWM1_CH1 PC6 MFP Mask */\r
+#define BPWM1_CH1_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! BPWM1_CH1 PF1 MFP Mask */\r
+#define BPWM1_CH1_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! BPWM1_CH1 PF2 MFP Mask */\r
+#define BPWM1_CH1_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! BPWM1_CH1 PB10 MFP Mask */\r
+#define BPWM1_CH2_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! BPWM1_CH2 PB9 MFP Mask */\r
+#define BPWM1_CH2_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! BPWM1_CH2 PA7 MFP Mask */\r
+#define BPWM1_CH2_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! BPWM1_CH2 PA12 MFP Mask */\r
+#define BPWM1_CH3_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! BPWM1_CH3 PA6 MFP Mask */\r
+#define BPWM1_CH3_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! BPWM1_CH3 PA13 MFP Mask */\r
+#define BPWM1_CH3_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! BPWM1_CH3 PB8 MFP Mask */\r
+#define BPWM1_CH4_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! BPWM1_CH4 PA14 MFP Mask */\r
+#define BPWM1_CH4_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! BPWM1_CH4 PC8 MFP Mask */\r
+#define BPWM1_CH4_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! BPWM1_CH4 PB7 MFP Mask */\r
+#define BPWM1_CH5_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! BPWM1_CH5 PA15 MFP Mask */\r
+#define BPWM1_CH5_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! BPWM1_CH5 PB6 MFP Mask */\r
+#define BPWM1_CH5_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! BPWM1_CH5 PE13 MFP Mask */\r
+#define CAN0_RXD_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! CAN0_RXD PA13 MFP Mask */\r
+#define CAN0_RXD_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! CAN0_RXD PD10 MFP Mask */\r
+#define CAN0_RXD_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! CAN0_RXD PA4 MFP Mask */\r
+#define CAN0_RXD_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! CAN0_RXD PC4 MFP Mask */\r
+#define CAN0_RXD_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! CAN0_RXD PB10 MFP Mask */\r
+#define CAN0_RXD_PE15_Msk SYS_GPE_MFPH_PE15MFP_Msk /*<! CAN0_RXD PE15 MFP Mask */\r
+#define CAN0_TXD_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! CAN0_TXD PD11 MFP Mask */\r
+#define CAN0_TXD_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! CAN0_TXD PC5 MFP Mask */\r
+#define CAN0_TXD_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! CAN0_TXD PB11 MFP Mask */\r
+#define CAN0_TXD_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! CAN0_TXD PA12 MFP Mask */\r
+#define CAN0_TXD_PE14_Msk SYS_GPE_MFPH_PE14MFP_Msk /*<! CAN0_TXD PE14 MFP Mask */\r
+#define CAN0_TXD_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! CAN0_TXD PA5 MFP Mask */\r
+#define CLKO_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! CLKO PC13 MFP Mask */\r
+#define CLKO_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! CLKO PB14 MFP Mask */\r
+#define CLKO_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! CLKO PD12 MFP Mask */\r
+#define CLKO_PG15_Msk SYS_GPG_MFPH_PG15MFP_Msk /*<! CLKO PG15 MFP Mask */\r
+#define DAC0_OUT_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! DAC0_OUT PB12 MFP Mask */\r
+#define DAC0_ST_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! DAC0_ST PA10 MFP Mask */\r
+#define DAC0_ST_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! DAC0_ST PA0 MFP Mask */\r
+#define DAC1_OUT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! DAC1_OUT PB13 MFP Mask */\r
+#define DAC1_ST_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! DAC1_ST PA1 MFP Mask */\r
+#define DAC1_ST_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! DAC1_ST PA11 MFP Mask */\r
+#define EADC0_CH0_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EADC0_CH0 PB0 MFP Mask */\r
+#define EADC0_CH1_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EADC0_CH1 PB1 MFP Mask */\r
+#define EADC0_CH10_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! EADC0_CH10 PB10 MFP Mask */\r
+#define EADC0_CH11_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! EADC0_CH11 PB11 MFP Mask */\r
+#define EADC0_CH12_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! EADC0_CH12 PB12 MFP Mask */\r
+#define EADC0_CH13_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! EADC0_CH13 PB13 MFP Mask */\r
+#define EADC0_CH14_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! EADC0_CH14 PB14 MFP Mask */\r
+#define EADC0_CH15_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! EADC0_CH15 PB15 MFP Mask */\r
+#define EADC0_CH2_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! EADC0_CH2 PB2 MFP Mask */\r
+#define EADC0_CH3_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! EADC0_CH3 PB3 MFP Mask */\r
+#define EADC0_CH4_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! EADC0_CH4 PB4 MFP Mask */\r
+#define EADC0_CH5_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! EADC0_CH5 PB5 MFP Mask */\r
+#define EADC0_CH6_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EADC0_CH6 PB6 MFP Mask */\r
+#define EADC0_CH7_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EADC0_CH7 PB7 MFP Mask */\r
+#define EADC0_CH8_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! EADC0_CH8 PB8 MFP Mask */\r
+#define EADC0_CH9_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! EADC0_CH9 PB9 MFP Mask */\r
+#define EADC0_ST_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! EADC0_ST PD12 MFP Mask */\r
+#define EADC0_ST_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! EADC0_ST PF5 MFP Mask */\r
+#define EADC0_ST_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! EADC0_ST PC13 MFP Mask */\r
+#define EADC0_ST_PG15_Msk SYS_GPG_MFPH_PG15MFP_Msk /*<! EADC0_ST PG15 MFP Mask */\r
+#define EBI_AD0_PG9_Msk SYS_GPG_MFPH_PG9MFP_Msk /*<! EBI_AD0 PG9 MFP Mask */\r
+#define EBI_AD0_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! EBI_AD0 PC0 MFP Mask */\r
+#define EBI_AD1_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! EBI_AD1 PC1 MFP Mask */\r
+#define EBI_AD1_PG10_Msk SYS_GPG_MFPH_PG10MFP_Msk /*<! EBI_AD1 PG10 MFP Mask */\r
+#define EBI_AD10_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! EBI_AD10 PE1 MFP Mask */\r
+#define EBI_AD10_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! EBI_AD10 PD3 MFP Mask */\r
+#define EBI_AD10_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! EBI_AD10 PD13 MFP Mask */\r
+#define EBI_AD11_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! EBI_AD11 PE0 MFP Mask */\r
+#define EBI_AD11_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! EBI_AD11 PD2 MFP Mask */\r
+#define EBI_AD12_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! EBI_AD12 PD1 MFP Mask */\r
+#define EBI_AD12_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! EBI_AD12 PB15 MFP Mask */\r
+#define EBI_AD12_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! EBI_AD12 PH8 MFP Mask */\r
+#define EBI_AD13_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! EBI_AD13 PD0 MFP Mask */\r
+#define EBI_AD13_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! EBI_AD13 PB14 MFP Mask */\r
+#define EBI_AD13_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! EBI_AD13 PH9 MFP Mask */\r
+#define EBI_AD14_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! EBI_AD14 PB13 MFP Mask */\r
+#define EBI_AD14_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! EBI_AD14 PH10 MFP Mask */\r
+#define EBI_AD15_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! EBI_AD15 PB12 MFP Mask */\r
+#define EBI_AD15_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! EBI_AD15 PH11 MFP Mask */\r
+#define EBI_AD2_PG11_Msk SYS_GPG_MFPH_PG11MFP_Msk /*<! EBI_AD2 PG11 MFP Mask */\r
+#define EBI_AD2_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! EBI_AD2 PC2 MFP Mask */\r
+#define EBI_AD3_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! EBI_AD3 PC3 MFP Mask */\r
+#define EBI_AD3_PG12_Msk SYS_GPG_MFPH_PG12MFP_Msk /*<! EBI_AD3 PG12 MFP Mask */\r
+#define EBI_AD4_PG13_Msk SYS_GPG_MFPH_PG13MFP_Msk /*<! EBI_AD4 PG13 MFP Mask */\r
+#define EBI_AD4_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! EBI_AD4 PC4 MFP Mask */\r
+#define EBI_AD5_PG14_Msk SYS_GPG_MFPH_PG14MFP_Msk /*<! EBI_AD5 PG14 MFP Mask */\r
+#define EBI_AD5_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! EBI_AD5 PC5 MFP Mask */\r
+#define EBI_AD6_PD8_Msk SYS_GPD_MFPH_PD8MFP_Msk /*<! EBI_AD6 PD8 MFP Mask */\r
+#define EBI_AD6_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! EBI_AD6 PA6 MFP Mask */\r
+#define EBI_AD7_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! EBI_AD7 PA7 MFP Mask */\r
+#define EBI_AD7_PD9_Msk SYS_GPD_MFPH_PD9MFP_Msk /*<! EBI_AD7 PD9 MFP Mask */\r
+#define EBI_AD8_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! EBI_AD8 PC6 MFP Mask */\r
+#define EBI_AD8_PE14_Msk SYS_GPE_MFPH_PE14MFP_Msk /*<! EBI_AD8 PE14 MFP Mask */\r
+#define EBI_AD9_PE15_Msk SYS_GPE_MFPH_PE15MFP_Msk /*<! EBI_AD9 PE15 MFP Mask */\r
+#define EBI_AD9_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! EBI_AD9 PC7 MFP Mask */\r
+#define EBI_ADR0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! EBI_ADR0 PB5 MFP Mask */\r
+#define EBI_ADR0_PH7_Msk SYS_GPH_MFPL_PH7MFP_Msk /*<! EBI_ADR0 PH7 MFP Mask */\r
+#define EBI_ADR1_PH6_Msk SYS_GPH_MFPL_PH6MFP_Msk /*<! EBI_ADR1 PH6 MFP Mask */\r
+#define EBI_ADR1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! EBI_ADR1 PB4 MFP Mask */\r
+#define EBI_ADR10_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! EBI_ADR10 PE8 MFP Mask */\r
+#define EBI_ADR10_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! EBI_ADR10 PC13 MFP Mask */\r
+#define EBI_ADR11_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! EBI_ADR11 PG2 MFP Mask */\r
+#define EBI_ADR11_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! EBI_ADR11 PE9 MFP Mask */\r
+#define EBI_ADR12_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! EBI_ADR12 PG3 MFP Mask */\r
+#define EBI_ADR12_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! EBI_ADR12 PE10 MFP Mask */\r
+#define EBI_ADR13_PG4_Msk SYS_GPG_MFPL_PG4MFP_Msk /*<! EBI_ADR13 PG4 MFP Mask */\r
+#define EBI_ADR13_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! EBI_ADR13 PE11 MFP Mask */\r
+#define EBI_ADR14_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! EBI_ADR14 PE12 MFP Mask */\r
+#define EBI_ADR14_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! EBI_ADR14 PF11 MFP Mask */\r
+#define EBI_ADR15_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! EBI_ADR15 PF10 MFP Mask */\r
+#define EBI_ADR15_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! EBI_ADR15 PE13 MFP Mask */\r
+#define EBI_ADR16_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! EBI_ADR16 PB11 MFP Mask */\r
+#define EBI_ADR16_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! EBI_ADR16 PF9 MFP Mask */\r
+#define EBI_ADR16_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! EBI_ADR16 PC8 MFP Mask */\r
+#define EBI_ADR17_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! EBI_ADR17 PF8 MFP Mask */\r
+#define EBI_ADR17_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! EBI_ADR17 PB10 MFP Mask */\r
+#define EBI_ADR18_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! EBI_ADR18 PB9 MFP Mask */\r
+#define EBI_ADR18_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! EBI_ADR18 PF7 MFP Mask */\r
+#define EBI_ADR19_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! EBI_ADR19 PF6 MFP Mask */\r
+#define EBI_ADR19_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! EBI_ADR19 PB8 MFP Mask */\r
+#define EBI_ADR2_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! EBI_ADR2 PB3 MFP Mask */\r
+#define EBI_ADR2_PH5_Msk SYS_GPH_MFPL_PH5MFP_Msk /*<! EBI_ADR2 PH5 MFP Mask */\r
+#define EBI_ADR3_PH4_Msk SYS_GPH_MFPL_PH4MFP_Msk /*<! EBI_ADR3 PH4 MFP Mask */\r
+#define EBI_ADR3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! EBI_ADR3 PB2 MFP Mask */\r
+#define EBI_ADR4_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! EBI_ADR4 PC12 MFP Mask */\r
+#define EBI_ADR5_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! EBI_ADR5 PC11 MFP Mask */\r
+#define EBI_ADR6_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! EBI_ADR6 PC10 MFP Mask */\r
+#define EBI_ADR7_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! EBI_ADR7 PC9 MFP Mask */\r
+#define EBI_ADR8_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EBI_ADR8 PB1 MFP Mask */\r
+#define EBI_ADR9_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EBI_ADR9 PB0 MFP Mask */\r
+#define EBI_ALE_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! EBI_ALE PA8 MFP Mask */\r
+#define EBI_ALE_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! EBI_ALE PE2 MFP Mask */\r
+#define EBI_MCLK_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! EBI_MCLK PE3 MFP Mask */\r
+#define EBI_MCLK_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! EBI_MCLK PA9 MFP Mask */\r
+#define EBI_nCS0_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EBI_nCS0 PB7 MFP Mask */\r
+#define EBI_nCS0_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! EBI_nCS0 PF6 MFP Mask */\r
+#define EBI_nCS0_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! EBI_nCS0 PD12 MFP Mask */\r
+#define EBI_nCS0_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! EBI_nCS0 PD14 MFP Mask */\r
+#define EBI_nCS0_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! EBI_nCS0 PF3 MFP Mask */\r
+#define EBI_nCS1_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! EBI_nCS1 PF2 MFP Mask */\r
+#define EBI_nCS1_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! EBI_nCS1 PD11 MFP Mask */\r
+#define EBI_nCS1_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EBI_nCS1 PB6 MFP Mask */\r
+#define EBI_nCS2_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! EBI_nCS2 PD10 MFP Mask */\r
+#define EBI_nRD_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! EBI_nRD PA11 MFP Mask */\r
+#define EBI_nRD_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! EBI_nRD PE5 MFP Mask */\r
+#define EBI_nWR_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! EBI_nWR PA10 MFP Mask */\r
+#define EBI_nWR_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! EBI_nWR PE4 MFP Mask */\r
+#define EBI_nWRH_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EBI_nWRH PB6 MFP Mask */\r
+#define EBI_nWRL_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EBI_nWRL PB7 MFP Mask */\r
+#define ECAP0_IC0_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! ECAP0_IC0 PA10 MFP Mask */\r
+#define ECAP0_IC0_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! ECAP0_IC0 PE8 MFP Mask */\r
+#define ECAP0_IC1_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! ECAP0_IC1 PE9 MFP Mask */\r
+#define ECAP0_IC1_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! ECAP0_IC1 PA9 MFP Mask */\r
+#define ECAP0_IC2_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! ECAP0_IC2 PA8 MFP Mask */\r
+#define ECAP0_IC2_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! ECAP0_IC2 PE10 MFP Mask */\r
+#define ECAP1_IC0_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! ECAP1_IC0 PC10 MFP Mask */\r
+#define ECAP1_IC0_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! ECAP1_IC0 PE13 MFP Mask */\r
+#define ECAP1_IC1_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! ECAP1_IC1 PE12 MFP Mask */\r
+#define ECAP1_IC1_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! ECAP1_IC1 PC11 MFP Mask */\r
+#define ECAP1_IC2_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! ECAP1_IC2 PE11 MFP Mask */\r
+#define ECAP1_IC2_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! ECAP1_IC2 PC12 MFP Mask */\r
+#define I2C0_SCL_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! I2C0_SCL PB5 MFP Mask */\r
+#define I2C0_SCL_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! I2C0_SCL PC1 MFP Mask */\r
+#define I2C0_SCL_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! I2C0_SCL PF3 MFP Mask */\r
+#define I2C0_SCL_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! I2C0_SCL PE13 MFP Mask */\r
+#define I2C0_SCL_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! I2C0_SCL PD7 MFP Mask */\r
+#define I2C0_SCL_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! I2C0_SCL PA5 MFP Mask */\r
+#define I2C0_SCL_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! I2C0_SCL PC12 MFP Mask */\r
+#define I2C0_SDA_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! I2C0_SDA PB4 MFP Mask */\r
+#define I2C0_SDA_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! I2C0_SDA PC8 MFP Mask */\r
+#define I2C0_SDA_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! I2C0_SDA PC0 MFP Mask */\r
+#define I2C0_SDA_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! I2C0_SDA PD6 MFP Mask */\r
+#define I2C0_SDA_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! I2C0_SDA PC11 MFP Mask */\r
+#define I2C0_SDA_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! I2C0_SDA PA4 MFP Mask */\r
+#define I2C0_SDA_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! I2C0_SDA PF2 MFP Mask */\r
+#define I2C0_SMBAL_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! I2C0_SMBAL PG2 MFP Mask */\r
+#define I2C0_SMBAL_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! I2C0_SMBAL PC3 MFP Mask */\r
+#define I2C0_SMBSUS_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! I2C0_SMBSUS PC2 MFP Mask */\r
+#define I2C0_SMBSUS_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! I2C0_SMBSUS PG3 MFP Mask */\r
+#define I2C1_SCL_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! I2C1_SCL PA3 MFP Mask */\r
+#define I2C1_SCL_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! I2C1_SCL PG2 MFP Mask */\r
+#define I2C1_SCL_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! I2C1_SCL PB1 MFP Mask */\r
+#define I2C1_SCL_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! I2C1_SCL PB11 MFP Mask */\r
+#define I2C1_SCL_PD5_Msk SYS_GPD_MFPL_PD5MFP_Msk /*<! I2C1_SCL PD5 MFP Mask */\r
+#define I2C1_SCL_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! I2C1_SCL PA12 MFP Mask */\r
+#define I2C1_SCL_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! I2C1_SCL PC5 MFP Mask */\r
+#define I2C1_SCL_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! I2C1_SCL PA7 MFP Mask */\r
+#define I2C1_SCL_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! I2C1_SCL PF0 MFP Mask */\r
+#define I2C1_SCL_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! I2C1_SCL PE1 MFP Mask */\r
+#define I2C1_SDA_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! I2C1_SDA PB0 MFP Mask */\r
+#define I2C1_SDA_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! I2C1_SDA PA6 MFP Mask */\r
+#define I2C1_SDA_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! I2C1_SDA PA13 MFP Mask */\r
+#define I2C1_SDA_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! I2C1_SDA PG3 MFP Mask */\r
+#define I2C1_SDA_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! I2C1_SDA PE0 MFP Mask */\r
+#define I2C1_SDA_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! I2C1_SDA PC4 MFP Mask */\r
+#define I2C1_SDA_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! I2C1_SDA PA2 MFP Mask */\r
+#define I2C1_SDA_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! I2C1_SDA PB10 MFP Mask */\r
+#define I2C1_SDA_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! I2C1_SDA PF1 MFP Mask */\r
+#define I2C1_SDA_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! I2C1_SDA PD4 MFP Mask */\r
+#define I2C1_SMBAL_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! I2C1_SMBAL PB9 MFP Mask */\r
+#define I2C1_SMBAL_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! I2C1_SMBAL PC7 MFP Mask */\r
+#define I2C1_SMBAL_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! I2C1_SMBAL PH8 MFP Mask */\r
+#define I2C1_SMBSUS_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! I2C1_SMBSUS PH9 MFP Mask */\r
+#define I2C1_SMBSUS_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! I2C1_SMBSUS PC6 MFP Mask */\r
+#define I2C1_SMBSUS_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! I2C1_SMBSUS PB8 MFP Mask */\r
+#define I2C2_SCL_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! I2C2_SCL PB13 MFP Mask */\r
+#define I2C2_SCL_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! I2C2_SCL PA11 MFP Mask */\r
+#define I2C2_SCL_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! I2C2_SCL PH8 MFP Mask */\r
+#define I2C2_SCL_PD9_Msk SYS_GPD_MFPH_PD9MFP_Msk /*<! I2C2_SCL PD9 MFP Mask */\r
+#define I2C2_SCL_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! I2C2_SCL PD1 MFP Mask */\r
+#define I2C2_SCL_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! I2C2_SCL PA14 MFP Mask */\r
+#define I2C2_SCL_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! I2C2_SCL PA1 MFP Mask */\r
+#define I2C2_SDA_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! I2C2_SDA PA0 MFP Mask */\r
+#define I2C2_SDA_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! I2C2_SDA PB12 MFP Mask */\r
+#define I2C2_SDA_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! I2C2_SDA PA10 MFP Mask */\r
+#define I2C2_SDA_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! I2C2_SDA PA15 MFP Mask */\r
+#define I2C2_SDA_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! I2C2_SDA PH9 MFP Mask */\r
+#define I2C2_SDA_PD8_Msk SYS_GPD_MFPH_PD8MFP_Msk /*<! I2C2_SDA PD8 MFP Mask */\r
+#define I2C2_SDA_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! I2C2_SDA PD0 MFP Mask */\r
+#define I2C2_SMBAL_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! I2C2_SMBAL PB15 MFP Mask */\r
+#define I2C2_SMBSUS_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! I2C2_SMBSUS PB14 MFP Mask */\r
+#define I2S0_BCLK_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! I2S0_BCLK PA12 MFP Mask */\r
+#define I2S0_BCLK_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! I2S0_BCLK PB5 MFP Mask */\r
+#define I2S0_BCLK_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! I2S0_BCLK PE8 MFP Mask */\r
+#define I2S0_BCLK_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! I2S0_BCLK PE1 MFP Mask */\r
+#define I2S0_BCLK_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! I2S0_BCLK PF10 MFP Mask */\r
+#define I2S0_BCLK_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! I2S0_BCLK PC4 MFP Mask */\r
+#define I2S0_DI_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! I2S0_DI PF8 MFP Mask */\r
+#define I2S0_DI_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! I2S0_DI PB3 MFP Mask */\r
+#define I2S0_DI_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! I2S0_DI PE10 MFP Mask */\r
+#define I2S0_DI_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! I2S0_DI PA14 MFP Mask */\r
+#define I2S0_DI_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! I2S0_DI PH8 MFP Mask */\r
+#define I2S0_DI_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! I2S0_DI PC2 MFP Mask */\r
+#define I2S0_DO_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! I2S0_DO PB2 MFP Mask */\r
+#define I2S0_DO_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! I2S0_DO PH9 MFP Mask */\r
+#define I2S0_DO_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! I2S0_DO PF7 MFP Mask */\r
+#define I2S0_DO_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! I2S0_DO PE11 MFP Mask */\r
+#define I2S0_DO_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! I2S0_DO PC1 MFP Mask */\r
+#define I2S0_DO_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! I2S0_DO PA15 MFP Mask */\r
+#define I2S0_LRCK_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! I2S0_LRCK PF6 MFP Mask */\r
+#define I2S0_LRCK_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! I2S0_LRCK PE12 MFP Mask */\r
+#define I2S0_LRCK_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! I2S0_LRCK PC0 MFP Mask */\r
+#define I2S0_LRCK_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! I2S0_LRCK PH10 MFP Mask */\r
+#define I2S0_LRCK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! I2S0_LRCK PB1 MFP Mask */\r
+#define I2S0_MCLK_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! I2S0_MCLK PE9 MFP Mask */\r
+#define I2S0_MCLK_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! I2S0_MCLK PB4 MFP Mask */\r
+#define I2S0_MCLK_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! I2S0_MCLK PC3 MFP Mask */\r
+#define I2S0_MCLK_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! I2S0_MCLK PE0 MFP Mask */\r
+#define I2S0_MCLK_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! I2S0_MCLK PA13 MFP Mask */\r
+#define I2S0_MCLK_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! I2S0_MCLK PF9 MFP Mask */\r
+#define ICE_CLK_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! ICE_CLK PF1 MFP Mask */\r
+#define ICE_DAT_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! ICE_DAT PF0 MFP Mask */\r
+#define INT0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! INT0 PB5 MFP Mask */\r
+#define INT0_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! INT0 PA6 MFP Mask */\r
+#define INT1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! INT1 PB4 MFP Mask */\r
+#define INT1_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! INT1 PA7 MFP Mask */\r
+#define INT2_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! INT2 PB3 MFP Mask */\r
+#define INT2_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! INT2 PC6 MFP Mask */\r
+#define INT3_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! INT3 PC7 MFP Mask */\r
+#define INT3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! INT3 PB2 MFP Mask */\r
+#define INT4_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! INT4 PB6 MFP Mask */\r
+#define INT4_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! INT4 PA8 MFP Mask */\r
+#define INT5_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! INT5 PB7 MFP Mask */\r
+#define INT5_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! INT5 PD12 MFP Mask */\r
+#define INT6_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! INT6 PD11 MFP Mask */\r
+#define INT6_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! INT6 PB8 MFP Mask */\r
+#define INT7_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! INT7 PB9 MFP Mask */\r
+#define INT7_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! INT7 PD10 MFP Mask */\r
+#define EPWM0_BRAKE0_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! EPWM0_BRAKE0 PE8 MFP Mask */\r
+#define EPWM0_BRAKE0_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EPWM0_BRAKE0 PB1 MFP Mask */\r
+#define EPWM0_BRAKE1_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EPWM0_BRAKE1 PB0 MFP Mask */\r
+#define EPWM0_BRAKE1_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! EPWM0_BRAKE1 PE9 MFP Mask */\r
+#define EPWM0_CH0_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! EPWM0_CH0 PA5 MFP Mask */\r
+#define EPWM0_CH0_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! EPWM0_CH0 PE7 MFP Mask */\r
+#define EPWM0_CH0_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! EPWM0_CH0 PE8 MFP Mask */\r
+#define EPWM0_CH0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! EPWM0_CH0 PB5 MFP Mask */\r
+#define EPWM0_CH1_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! EPWM0_CH1 PA4 MFP Mask */\r
+#define EPWM0_CH1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! EPWM0_CH1 PB4 MFP Mask */\r
+#define EPWM0_CH1_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! EPWM0_CH1 PE9 MFP Mask */\r
+#define EPWM0_CH1_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! EPWM0_CH1 PE6 MFP Mask */\r
+#define EPWM0_CH2_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! EPWM0_CH2 PE5 MFP Mask */\r
+#define EPWM0_CH2_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! EPWM0_CH2 PB3 MFP Mask */\r
+#define EPWM0_CH2_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! EPWM0_CH2 PE10 MFP Mask */\r
+#define EPWM0_CH2_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! EPWM0_CH2 PA3 MFP Mask */\r
+#define EPWM0_CH3_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! EPWM0_CH3 PA2 MFP Mask */\r
+#define EPWM0_CH3_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! EPWM0_CH3 PE11 MFP Mask */\r
+#define EPWM0_CH3_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! EPWM0_CH3 PE4 MFP Mask */\r
+#define EPWM0_CH3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! EPWM0_CH3 PB2 MFP Mask */\r
+#define EPWM0_CH4_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! EPWM0_CH4 PD14 MFP Mask */\r
+#define EPWM0_CH4_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EPWM0_CH4 PB1 MFP Mask */\r
+#define EPWM0_CH4_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! EPWM0_CH4 PE3 MFP Mask */\r
+#define EPWM0_CH4_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! EPWM0_CH4 PA1 MFP Mask */\r
+#define EPWM0_CH4_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! EPWM0_CH4 PE12 MFP Mask */\r
+#define EPWM0_CH5_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EPWM0_CH5 PB0 MFP Mask */\r
+#define EPWM0_CH5_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! EPWM0_CH5 PE2 MFP Mask */\r
+#define EPWM0_CH5_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! EPWM0_CH5 PA0 MFP Mask */\r
+#define EPWM0_CH5_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! EPWM0_CH5 PE13 MFP Mask */\r
+#define EPWM0_CH5_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! EPWM0_CH5 PH11 MFP Mask */\r
+#define EPWM0_SYNC_IN_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! EPWM0_SYNC_IN PA15 MFP Mask */\r
+#define EPWM0_SYNC_OUT_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! EPWM0_SYNC_OUT PF5 MFP Mask */\r
+#define EPWM0_SYNC_OUT_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! EPWM0_SYNC_OUT PA11 MFP Mask */\r
+#define EPWM1_BRAKE0_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EPWM1_BRAKE0 PB7 MFP Mask */\r
+#define EPWM1_BRAKE0_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! EPWM1_BRAKE0 PE10 MFP Mask */\r
+#define EPWM1_BRAKE1_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EPWM1_BRAKE1 PB6 MFP Mask */\r
+#define EPWM1_BRAKE1_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! EPWM1_BRAKE1 PE11 MFP Mask */\r
+#define EPWM1_CH0_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! EPWM1_CH0 PC5 MFP Mask */\r
+#define EPWM1_CH0_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! EPWM1_CH0 PE13 MFP Mask */\r
+#define EPWM1_CH0_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! EPWM1_CH0 PC12 MFP Mask */\r
+#define EPWM1_CH0_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! EPWM1_CH0 PB15 MFP Mask */\r
+#define EPWM1_CH1_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! EPWM1_CH1 PB14 MFP Mask */\r
+#define EPWM1_CH1_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! EPWM1_CH1 PC11 MFP Mask */\r
+#define EPWM1_CH1_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! EPWM1_CH1 PC4 MFP Mask */\r
+#define EPWM1_CH1_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! EPWM1_CH1 PC8 MFP Mask */\r
+#define EPWM1_CH2_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! EPWM1_CH2 PC7 MFP Mask */\r
+#define EPWM1_CH2_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! EPWM1_CH2 PC10 MFP Mask */\r
+#define EPWM1_CH2_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! EPWM1_CH2 PC3 MFP Mask */\r
+#define EPWM1_CH2_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! EPWM1_CH2 PB13 MFP Mask */\r
+#define EPWM1_CH3_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! EPWM1_CH3 PB12 MFP Mask */\r
+#define EPWM1_CH3_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! EPWM1_CH3 PC6 MFP Mask */\r
+#define EPWM1_CH3_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! EPWM1_CH3 PC9 MFP Mask */\r
+#define EPWM1_CH3_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! EPWM1_CH3 PC2 MFP Mask */\r
+#define EPWM1_CH4_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EPWM1_CH4 PB7 MFP Mask */\r
+#define EPWM1_CH4_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EPWM1_CH4 PB1 MFP Mask */\r
+#define EPWM1_CH4_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! EPWM1_CH4 PC1 MFP Mask */\r
+#define EPWM1_CH4_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! EPWM1_CH4 PA7 MFP Mask */\r
+#define EPWM1_CH5_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! EPWM1_CH5 PA6 MFP Mask */\r
+#define EPWM1_CH5_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! EPWM1_CH5 PC0 MFP Mask */\r
+#define EPWM1_CH5_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EPWM1_CH5 PB6 MFP Mask */\r
+#define EPWM1_CH5_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EPWM1_CH5 PB0 MFP Mask */\r
+#define QEI0_A_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! QEI0_A PE3 MFP Mask */\r
+#define QEI0_A_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! QEI0_A PA4 MFP Mask */\r
+#define QEI0_A_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! QEI0_A PD11 MFP Mask */\r
+#define QEI0_B_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! QEI0_B PD10 MFP Mask */\r
+#define QEI0_B_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! QEI0_B PA3 MFP Mask */\r
+#define QEI0_B_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! QEI0_B PE2 MFP Mask */\r
+#define QEI0_INDEX_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! QEI0_INDEX PE4 MFP Mask */\r
+#define QEI0_INDEX_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! QEI0_INDEX PA5 MFP Mask */\r
+#define QEI0_INDEX_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! QEI0_INDEX PD12 MFP Mask */\r
+#define QEI1_A_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! QEI1_A PE6 MFP Mask */\r
+#define QEI1_A_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! QEI1_A PA13 MFP Mask */\r
+#define QEI1_A_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! QEI1_A PA9 MFP Mask */\r
+#define QEI1_B_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! QEI1_B PA14 MFP Mask */\r
+#define QEI1_B_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! QEI1_B PA8 MFP Mask */\r
+#define QEI1_B_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! QEI1_B PE5 MFP Mask */\r
+#define QEI1_INDEX_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! QEI1_INDEX PE7 MFP Mask */\r
+#define QEI1_INDEX_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! QEI1_INDEX PA10 MFP Mask */\r
+#define QEI1_INDEX_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! QEI1_INDEX PA12 MFP Mask */\r
+#define SC0_CLK_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! SC0_CLK PF6 MFP Mask */\r
+#define SC0_CLK_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! SC0_CLK PE2 MFP Mask */\r
+#define SC0_CLK_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! SC0_CLK PA0 MFP Mask */\r
+#define SC0_CLK_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! SC0_CLK PB5 MFP Mask */\r
+#define SC0_DAT_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! SC0_DAT PE3 MFP Mask */\r
+#define SC0_DAT_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! SC0_DAT PB4 MFP Mask */\r
+#define SC0_DAT_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! SC0_DAT PA1 MFP Mask */\r
+#define SC0_DAT_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! SC0_DAT PF7 MFP Mask */\r
+#define SC0_PWR_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! SC0_PWR PE5 MFP Mask */\r
+#define SC0_PWR_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! SC0_PWR PA3 MFP Mask */\r
+#define SC0_PWR_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! SC0_PWR PB2 MFP Mask */\r
+#define SC0_PWR_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! SC0_PWR PF9 MFP Mask */\r
+#define SC0_RST_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! SC0_RST PF8 MFP Mask */\r
+#define SC0_RST_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! SC0_RST PE4 MFP Mask */\r
+#define SC0_RST_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! SC0_RST PA2 MFP Mask */\r
+#define SC0_RST_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! SC0_RST PB3 MFP Mask */\r
+#define SC0_nCD_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! SC0_nCD PE6 MFP Mask */\r
+#define SC0_nCD_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! SC0_nCD PF10 MFP Mask */\r
+#define SC0_nCD_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! SC0_nCD PA4 MFP Mask */\r
+#define SC0_nCD_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! SC0_nCD PC12 MFP Mask */\r
+#define SC1_CLK_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! SC1_CLK PC0 MFP Mask */\r
+#define SC1_CLK_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! SC1_CLK PB12 MFP Mask */\r
+#define SC1_CLK_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! SC1_CLK PD4 MFP Mask */\r
+#define SC1_DAT_PD5_Msk SYS_GPD_MFPL_PD5MFP_Msk /*<! SC1_DAT PD5 MFP Mask */\r
+#define SC1_DAT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! SC1_DAT PB13 MFP Mask */\r
+#define SC1_DAT_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! SC1_DAT PC1 MFP Mask */\r
+#define SC1_PWR_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! SC1_PWR PB15 MFP Mask */\r
+#define SC1_PWR_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! SC1_PWR PC3 MFP Mask */\r
+#define SC1_PWR_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! SC1_PWR PD7 MFP Mask */\r
+#define SC1_RST_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! SC1_RST PD6 MFP Mask */\r
+#define SC1_RST_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! SC1_RST PB14 MFP Mask */\r
+#define SC1_RST_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! SC1_RST PC2 MFP Mask */\r
+#define SC1_nCD_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! SC1_nCD PD3 MFP Mask */\r
+#define SC1_nCD_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! SC1_nCD PC4 MFP Mask */\r
+#define SC1_nCD_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! SC1_nCD PD14 MFP Mask */\r
+#define SC2_CLK_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! SC2_CLK PD0 MFP Mask */\r
+#define SC2_CLK_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! SC2_CLK PA15 MFP Mask */\r
+#define SC2_CLK_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! SC2_CLK PE0 MFP Mask */\r
+#define SC2_CLK_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! SC2_CLK PA8 MFP Mask */\r
+#define SC2_CLK_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! SC2_CLK PA6 MFP Mask */\r
+#define SC2_DAT_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! SC2_DAT PE1 MFP Mask */\r
+#define SC2_DAT_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! SC2_DAT PD1 MFP Mask */\r
+#define SC2_DAT_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! SC2_DAT PA9 MFP Mask */\r
+#define SC2_DAT_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! SC2_DAT PA14 MFP Mask */\r
+#define SC2_DAT_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! SC2_DAT PA7 MFP Mask */\r
+#define SC2_PWR_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! SC2_PWR PD3 MFP Mask */\r
+#define SC2_PWR_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! SC2_PWR PA11 MFP Mask */\r
+#define SC2_PWR_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! SC2_PWR PA12 MFP Mask */\r
+#define SC2_PWR_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! SC2_PWR PH8 MFP Mask */\r
+#define SC2_PWR_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! SC2_PWR PC7 MFP Mask */\r
+#define SC2_RST_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! SC2_RST PD2 MFP Mask */\r
+#define SC2_RST_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! SC2_RST PC6 MFP Mask */\r
+#define SC2_RST_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! SC2_RST PH9 MFP Mask */\r
+#define SC2_RST_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! SC2_RST PA10 MFP Mask */\r
+#define SC2_RST_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! SC2_RST PA13 MFP Mask */\r
+#define SC2_nCD_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! SC2_nCD PH10 MFP Mask */\r
+#define SC2_nCD_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! SC2_nCD PA5 MFP Mask */\r
+#define SC2_nCD_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! SC2_nCD PC13 MFP Mask */\r
+#define SC2_nCD_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! SC2_nCD PD13 MFP Mask */\r
+#define SD0_CLK_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! SD0_CLK PE6 MFP Mask */\r
+#define SD0_CLK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! SD0_CLK PB1 MFP Mask */\r
+#define SD0_CMD_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! SD0_CMD PB0 MFP Mask */\r
+#define SD0_CMD_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! SD0_CMD PE7 MFP Mask */\r
+#define SD0_DAT0_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! SD0_DAT0 PB2 MFP Mask */\r
+#define SD0_DAT0_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! SD0_DAT0 PE2 MFP Mask */\r
+#define SD0_DAT1_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! SD0_DAT1 PE3 MFP Mask */\r
+#define SD0_DAT1_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! SD0_DAT1 PB3 MFP Mask */\r
+#define SD0_DAT2_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! SD0_DAT2 PB4 MFP Mask */\r
+#define SD0_DAT2_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! SD0_DAT2 PE4 MFP Mask */\r
+#define SD0_DAT3_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! SD0_DAT3 PE5 MFP Mask */\r
+#define SD0_DAT3_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! SD0_DAT3 PB5 MFP Mask */\r
+#define SD0_nCD_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! SD0_nCD PB12 MFP Mask */\r
+#define SD0_nCD_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! SD0_nCD PD13 MFP Mask */\r
+#define QSPI0_CLK_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! QSPI0_CLK PF2 MFP Mask */\r
+#define QSPI0_CLK_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! QSPI0_CLK PH8 MFP Mask */\r
+#define QSPI0_CLK_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! QSPI0_CLK PA2 MFP Mask */\r
+#define QSPI0_CLK_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! QSPI0_CLK PC2 MFP Mask */\r
+#define QSPI0_MISO0_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! QSPI0_MISO0 PC1 MFP Mask */\r
+#define QSPI0_MISO0_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! QSPI0_MISO0 PE1 MFP Mask */\r
+#define QSPI0_MISO0_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! QSPI0_MISO0 PA1 MFP Mask */\r
+#define QSPI0_MISO1_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! QSPI0_MISO1 PC5 MFP Mask */\r
+#define QSPI0_MISO1_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! QSPI0_MISO1 PH10 MFP Mask */\r
+#define QSPI0_MISO1_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! QSPI0_MISO1 PA5 MFP Mask */\r
+#define QSPI0_MOSI0_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! QSPI0_MOSI0 PC0 MFP Mask */\r
+#define QSPI0_MOSI0_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! QSPI0_MOSI0 PE0 MFP Mask */\r
+#define QSPI0_MOSI0_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! QSPI0_MOSI0 PA0 MFP Mask */\r
+#define QSPI0_MOSI1_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! QSPI0_MOSI1 PA4 MFP Mask */\r
+#define QSPI0_MOSI1_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! QSPI0_MOSI1 PH11 MFP Mask */\r
+#define QSPI0_MOSI1_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! QSPI0_MOSI1 PC4 MFP Mask */\r
+#define QSPI0_SS_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! QSPI0_SS PH9 MFP Mask */\r
+#define QSPI0_SS_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! QSPI0_SS PA3 MFP Mask */\r
+#define QSPI0_SS_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! QSPI0_SS PC3 MFP Mask */\r
+#define SPI0_CLK_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! SPI0_CLK PD2 MFP Mask */\r
+#define SPI0_CLK_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! SPI0_CLK PF8 MFP Mask */\r
+#define SPI0_CLK_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! SPI0_CLK PA2 MFP Mask */\r
+#define SPI0_CLK_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! SPI0_CLK PB14 MFP Mask */\r
+#define SPI0_I2SMCLK_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! SPI0_I2SMCLK PD13 MFP Mask */\r
+#define SPI0_I2SMCLK_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! SPI0_I2SMCLK PA4 MFP Mask */\r
+#define SPI0_I2SMCLK_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! SPI0_I2SMCLK PB11 MFP Mask */\r
+#define SPI0_I2SMCLK_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! SPI0_I2SMCLK PB0 MFP Mask */\r
+#define SPI0_I2SMCLK_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! SPI0_I2SMCLK PD14 MFP Mask */\r
+#define SPI0_I2SMCLK_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! SPI0_I2SMCLK PF10 MFP Mask */\r
+#define SPI0_MISO_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! SPI0_MISO PF7 MFP Mask */\r
+#define SPI0_MISO_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! SPI0_MISO PB13 MFP Mask */\r
+#define SPI0_MISO_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! SPI0_MISO PA1 MFP Mask */\r
+#define SPI0_MISO_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! SPI0_MISO PD1 MFP Mask */\r
+#define SPI0_MOSI_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! SPI0_MOSI PA0 MFP Mask */\r
+#define SPI0_MOSI_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! SPI0_MOSI PB12 MFP Mask */\r
+#define SPI0_MOSI_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! SPI0_MOSI PD0 MFP Mask */\r
+#define SPI0_MOSI_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! SPI0_MOSI PF6 MFP Mask */\r
+#define SPI0_SS_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! SPI0_SS PB15 MFP Mask */\r
+#define SPI0_SS_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! SPI0_SS PA3 MFP Mask */\r
+#define SPI0_SS_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! SPI0_SS PD3 MFP Mask */\r
+#define SPI0_SS_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! SPI0_SS PF9 MFP Mask */\r
+#define SPI1_CLK_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! SPI1_CLK PB3 MFP Mask */\r
+#define SPI1_CLK_PH6_Msk SYS_GPH_MFPL_PH6MFP_Msk /*<! SPI1_CLK PH6 MFP Mask */\r
+#define SPI1_CLK_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! SPI1_CLK PH8 MFP Mask */\r
+#define SPI1_CLK_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! SPI1_CLK PC1 MFP Mask */\r
+#define SPI1_CLK_PD5_Msk SYS_GPD_MFPL_PD5MFP_Msk /*<! SPI1_CLK PD5 MFP Mask */\r
+#define SPI1_CLK_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! SPI1_CLK PA7 MFP Mask */\r
+#define SPI1_I2SMCLK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! SPI1_I2SMCLK PB1 MFP Mask */\r
+#define SPI1_I2SMCLK_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! SPI1_I2SMCLK PH10 MFP Mask */\r
+#define SPI1_I2SMCLK_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! SPI1_I2SMCLK PC4 MFP Mask */\r
+#define SPI1_I2SMCLK_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! SPI1_I2SMCLK PD13 MFP Mask */\r
+#define SPI1_I2SMCLK_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! SPI1_I2SMCLK PA5 MFP Mask */\r
+#define SPI1_MISO_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! SPI1_MISO PD7 MFP Mask */\r
+#define SPI1_MISO_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! SPI1_MISO PC7 MFP Mask */\r
+#define SPI1_MISO_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! SPI1_MISO PB5 MFP Mask */\r
+#define SPI1_MISO_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! SPI1_MISO PE1 MFP Mask */\r
+#define SPI1_MISO_PH4_Msk SYS_GPH_MFPL_PH4MFP_Msk /*<! SPI1_MISO PH4 MFP Mask */\r
+#define SPI1_MISO_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! SPI1_MISO PC3 MFP Mask */\r
+#define SPI1_MOSI_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! SPI1_MOSI PD6 MFP Mask */\r
+#define SPI1_MOSI_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! SPI1_MOSI PE0 MFP Mask */\r
+#define SPI1_MOSI_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! SPI1_MOSI PB4 MFP Mask */\r
+#define SPI1_MOSI_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! SPI1_MOSI PC6 MFP Mask */\r
+#define SPI1_MOSI_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! SPI1_MOSI PC2 MFP Mask */\r
+#define SPI1_MOSI_PH5_Msk SYS_GPH_MFPL_PH5MFP_Msk /*<! SPI1_MOSI PH5 MFP Mask */\r
+#define SPI1_SS_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! SPI1_SS PB2 MFP Mask */\r
+#define SPI1_SS_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! SPI1_SS PH9 MFP Mask */\r
+#define SPI1_SS_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! SPI1_SS PD4 MFP Mask */\r
+#define SPI1_SS_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! SPI1_SS PC0 MFP Mask */\r
+#define SPI1_SS_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! SPI1_SS PA6 MFP Mask */\r
+#define SPI1_SS_PH7_Msk SYS_GPH_MFPL_PH7MFP_Msk /*<! SPI1_SS PH7 MFP Mask */\r
+#define SPI2_CLK_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! SPI2_CLK PE8 MFP Mask */\r
+#define SPI2_CLK_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! SPI2_CLK PG3 MFP Mask */\r
+#define SPI2_CLK_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! SPI2_CLK PA10 MFP Mask */\r
+#define SPI2_CLK_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! SPI2_CLK PA13 MFP Mask */\r
+#define SPI2_I2SMCLK_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! SPI2_I2SMCLK PC13 MFP Mask */\r
+#define SPI2_I2SMCLK_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! SPI2_I2SMCLK PE12 MFP Mask */\r
+#define SPI2_MISO_PG4_Msk SYS_GPG_MFPL_PG4MFP_Msk /*<! SPI2_MISO PG4 MFP Mask */\r
+#define SPI2_MISO_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! SPI2_MISO PA9 MFP Mask */\r
+#define SPI2_MISO_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! SPI2_MISO PA14 MFP Mask */\r
+#define SPI2_MISO_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! SPI2_MISO PE9 MFP Mask */\r
+#define SPI2_MOSI_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! SPI2_MOSI PE10 MFP Mask */\r
+#define SPI2_MOSI_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! SPI2_MOSI PA15 MFP Mask */\r
+#define SPI2_MOSI_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! SPI2_MOSI PA8 MFP Mask */\r
+#define SPI2_MOSI_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! SPI2_MOSI PF11 MFP Mask */\r
+#define SPI2_SS_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! SPI2_SS PG2 MFP Mask */\r
+#define SPI2_SS_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! SPI2_SS PE11 MFP Mask */\r
+#define SPI2_SS_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! SPI2_SS PA11 MFP Mask */\r
+#define SPI2_SS_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! SPI2_SS PA12 MFP Mask */\r
+#define SPI3_CLK_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! SPI3_CLK PB11 MFP Mask */\r
+#define SPI3_CLK_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! SPI3_CLK PE4 MFP Mask */\r
+#define SPI3_CLK_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! SPI3_CLK PC10 MFP Mask */\r
+#define SPI3_I2SMCLK_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! SPI3_I2SMCLK PE6 MFP Mask */\r
+#define SPI3_I2SMCLK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! SPI3_I2SMCLK PB1 MFP Mask */\r
+#define SPI3_I2SMCLK_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! SPI3_I2SMCLK PD14 MFP Mask */\r
+#define SPI3_MISO_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! SPI3_MISO PC12 MFP Mask */\r
+#define SPI3_MISO_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! SPI3_MISO PB9 MFP Mask */\r
+#define SPI3_MISO_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! SPI3_MISO PE3 MFP Mask */\r
+#define SPI3_MOSI_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! SPI3_MOSI PB8 MFP Mask */\r
+#define SPI3_MOSI_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! SPI3_MOSI PE2 MFP Mask */\r
+#define SPI3_MOSI_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! SPI3_MOSI PC11 MFP Mask */\r
+#define SPI3_SS_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! SPI3_SS PE5 MFP Mask */\r
+#define SPI3_SS_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! SPI3_SS PB10 MFP Mask */\r
+#define SPI3_SS_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! SPI3_SS PC9 MFP Mask */\r
+#define TAMPER0_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! TAMPER0 PF6 MFP Mask */\r
+#define TAMPER1_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! TAMPER1 PF7 MFP Mask */\r
+#define TAMPER2_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! TAMPER2 PF8 MFP Mask */\r
+#define TAMPER3_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! TAMPER3 PF9 MFP Mask */\r
+#define TAMPER4_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! TAMPER4 PF10 MFP Mask */\r
+#define TAMPER5_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! TAMPER5 PF11 MFP Mask */\r
+#define TM0_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! TM0 PC7 MFP Mask */\r
+#define TM0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! TM0 PB5 MFP Mask */\r
+#define TM0_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! TM0 PG2 MFP Mask */\r
+#define TM0_EXT_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! TM0_EXT PA11 MFP Mask */\r
+#define TM0_EXT_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! TM0_EXT PB15 MFP Mask */\r
+#define TM1_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! TM1 PG3 MFP Mask */\r
+#define TM1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! TM1 PB4 MFP Mask */\r
+#define TM1_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! TM1 PC6 MFP Mask */\r
+#define TM1_EXT_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! TM1_EXT PA10 MFP Mask */\r
+#define TM1_EXT_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! TM1_EXT PB14 MFP Mask */\r
+#define TM2_PG4_Msk SYS_GPG_MFPL_PG4MFP_Msk /*<! TM2 PG4 MFP Mask */\r
+#define TM2_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! TM2 PD0 MFP Mask */\r
+#define TM2_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! TM2 PB3 MFP Mask */\r
+#define TM2_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! TM2 PA7 MFP Mask */\r
+#define TM2_EXT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! TM2_EXT PB13 MFP Mask */\r
+#define TM2_EXT_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! TM2_EXT PA9 MFP Mask */\r
+#define TM3_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! TM3 PA6 MFP Mask */\r
+#define TM3_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! TM3 PF11 MFP Mask */\r
+#define TM3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! TM3 PB2 MFP Mask */\r
+#define TM3_EXT_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! TM3_EXT PA8 MFP Mask */\r
+#define TM3_EXT_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! TM3_EXT PB12 MFP Mask */\r
+#define TRACE_CLK_PE12_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! TRACE_CLK PE12 MFP Mask */\r
+#define TRACE_DATA0_PE11_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! TRACE_DATA0 PE11 MFP Mask */\r
+#define TRACE_DATA1_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! TRACE_DATA1 PE10 MFP Mask */\r
+#define TRACE_DATA2_PE9_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! TRACE_DATA2 PE9 MFP Mask */\r
+#define TRACE_DATA3_PE8_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! TRACE_DATA3 PE8 MFP Mask */\r
+#define UART0_RXD_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! UART0_RXD PD2 MFP Mask */\r
+#define UART0_RXD_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! UART0_RXD PB8 MFP Mask */\r
+#define UART0_RXD_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! UART0_RXD PA0 MFP Mask */\r
+#define UART0_RXD_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! UART0_RXD PA6 MFP Mask */\r
+#define UART0_RXD_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! UART0_RXD PB12 MFP Mask */\r
+#define UART0_RXD_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! UART0_RXD PA15 MFP Mask */\r
+#define UART0_RXD_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! UART0_RXD PC11 MFP Mask */\r
+#define UART0_RXD_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! UART0_RXD PH11 MFP Mask */\r
+#define UART0_RXD_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! UART0_RXD PF2 MFP Mask */\r
+#define UART0_TXD_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! UART0_TXD PA7 MFP Mask */\r
+#define UART0_TXD_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! UART0_TXD PD3 MFP Mask */\r
+#define UART0_TXD_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! UART0_TXD PF3 MFP Mask */\r
+#define UART0_TXD_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! UART0_TXD PC12 MFP Mask */\r
+#define UART0_TXD_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! UART0_TXD PH10 MFP Mask */\r
+#define UART0_TXD_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! UART0_TXD PA1 MFP Mask */\r
+#define UART0_TXD_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! UART0_TXD PB9 MFP Mask */\r
+#define UART0_TXD_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! UART0_TXD PB13 MFP Mask */\r
+#define UART0_TXD_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! UART0_TXD PA14 MFP Mask */\r
+#define UART0_nCTS_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! UART0_nCTS PA5 MFP Mask */\r
+#define UART0_nCTS_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! UART0_nCTS PB11 MFP Mask */\r
+#define UART0_nCTS_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! UART0_nCTS PB15 MFP Mask */\r
+#define UART0_nCTS_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! UART0_nCTS PC7 MFP Mask */\r
+#define UART0_nRTS_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! UART0_nRTS PB14 MFP Mask */\r
+#define UART0_nRTS_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! UART0_nRTS PB10 MFP Mask */\r
+#define UART0_nRTS_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! UART0_nRTS PC6 MFP Mask */\r
+#define UART0_nRTS_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! UART0_nRTS PA4 MFP Mask */\r
+#define UART1_RXD_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! UART1_RXD PF1 MFP Mask */\r
+#define UART1_RXD_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! UART1_RXD PA8 MFP Mask */\r
+#define UART1_RXD_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! UART1_RXD PA2 MFP Mask */\r
+#define UART1_RXD_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! UART1_RXD PB2 MFP Mask */\r
+#define UART1_RXD_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! UART1_RXD PB6 MFP Mask */\r
+#define UART1_RXD_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! UART1_RXD PD6 MFP Mask */\r
+#define UART1_RXD_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! UART1_RXD PD10 MFP Mask */\r
+#define UART1_RXD_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! UART1_RXD PH9 MFP Mask */\r
+#define UART1_RXD_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! UART1_RXD PC8 MFP Mask */\r
+#define UART1_TXD_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! UART1_TXD PB3 MFP Mask */\r
+#define UART1_TXD_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! UART1_TXD PA3 MFP Mask */\r
+#define UART1_TXD_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! UART1_TXD PE13 MFP Mask */\r
+#define UART1_TXD_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! UART1_TXD PA9 MFP Mask */\r
+#define UART1_TXD_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! UART1_TXD PF0 MFP Mask */\r
+#define UART1_TXD_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! UART1_TXD PD11 MFP Mask */\r
+#define UART1_TXD_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! UART1_TXD PD7 MFP Mask */\r
+#define UART1_TXD_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! UART1_TXD PB7 MFP Mask */\r
+#define UART1_TXD_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! UART1_TXD PH8 MFP Mask */\r
+#define UART1_nCTS_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! UART1_nCTS PE11 MFP Mask */\r
+#define UART1_nCTS_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! UART1_nCTS PB9 MFP Mask */\r
+#define UART1_nCTS_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! UART1_nCTS PA1 MFP Mask */\r
+#define UART1_nRTS_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! UART1_nRTS PA0 MFP Mask */\r
+#define UART1_nRTS_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! UART1_nRTS PE12 MFP Mask */\r
+#define UART1_nRTS_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! UART1_nRTS PB8 MFP Mask */\r
+#define UART2_RXD_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! UART2_RXD PB0 MFP Mask */\r
+#define UART2_RXD_PE15_Msk SYS_GPE_MFPH_PE15MFP_Msk /*<! UART2_RXD PE15 MFP Mask */\r
+#define UART2_RXD_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! UART2_RXD PD12 MFP Mask */\r
+#define UART2_RXD_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! UART2_RXD PF5 MFP Mask */\r
+#define UART2_RXD_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! UART2_RXD PC0 MFP Mask */\r
+#define UART2_RXD_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! UART2_RXD PC4 MFP Mask */\r
+#define UART2_RXD_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! UART2_RXD PE9 MFP Mask */\r
+#define UART2_TXD_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! UART2_TXD PE8 MFP Mask */\r
+#define UART2_TXD_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! UART2_TXD PF4 MFP Mask */\r
+#define UART2_TXD_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! UART2_TXD PC13 MFP Mask */\r
+#define UART2_TXD_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! UART2_TXD PC1 MFP Mask */\r
+#define UART2_TXD_PE14_Msk SYS_GPE_MFPH_PE14MFP_Msk /*<! UART2_TXD PE14 MFP Mask */\r
+#define UART2_TXD_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! UART2_TXD PC5 MFP Mask */\r
+#define UART2_TXD_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! UART2_TXD PB1 MFP Mask */\r
+#define UART2_nCTS_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! UART2_nCTS PF5 MFP Mask */\r
+#define UART2_nCTS_PD9_Msk SYS_GPD_MFPH_PD9MFP_Msk /*<! UART2_nCTS PD9 MFP Mask */\r
+#define UART2_nCTS_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! UART2_nCTS PC2 MFP Mask */\r
+#define UART2_nRTS_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! UART2_nRTS PF4 MFP Mask */\r
+#define UART2_nRTS_PD8_Msk SYS_GPD_MFPH_PD8MFP_Msk /*<! UART2_nRTS PD8 MFP Mask */\r
+#define UART2_nRTS_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! UART2_nRTS PC3 MFP Mask */\r
+#define UART3_RXD_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! UART3_RXD PD0 MFP Mask */\r
+#define UART3_RXD_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! UART3_RXD PE11 MFP Mask */\r
+#define UART3_RXD_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! UART3_RXD PC9 MFP Mask */\r
+#define UART3_RXD_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! UART3_RXD PE0 MFP Mask */\r
+#define UART3_RXD_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! UART3_RXD PC2 MFP Mask */\r
+#define UART3_RXD_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! UART3_RXD PB14 MFP Mask */\r
+#define UART3_TXD_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! UART3_TXD PD1 MFP Mask */\r
+#define UART3_TXD_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! UART3_TXD PC10 MFP Mask */\r
+#define UART3_TXD_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! UART3_TXD PB15 MFP Mask */\r
+#define UART3_TXD_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! UART3_TXD PC3 MFP Mask */\r
+#define UART3_TXD_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! UART3_TXD PE1 MFP Mask */\r
+#define UART3_TXD_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! UART3_TXD PE10 MFP Mask */\r
+#define UART3_nCTS_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! UART3_nCTS PB12 MFP Mask */\r
+#define UART3_nCTS_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! UART3_nCTS PH9 MFP Mask */\r
+#define UART3_nCTS_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! UART3_nCTS PD2 MFP Mask */\r
+#define UART3_nRTS_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! UART3_nRTS PB13 MFP Mask */\r
+#define UART3_nRTS_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! UART3_nRTS PH8 MFP Mask */\r
+#define UART3_nRTS_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! UART3_nRTS PD3 MFP Mask */\r
+#define UART4_RXD_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! UART4_RXD PA13 MFP Mask */\r
+#define UART4_RXD_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! UART4_RXD PC6 MFP Mask */\r
+#define UART4_RXD_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! UART4_RXD PC4 MFP Mask */\r
+#define UART4_RXD_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! UART4_RXD PB10 MFP Mask */\r
+#define UART4_RXD_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! UART4_RXD PH11 MFP Mask */\r
+#define UART4_RXD_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! UART4_RXD PA2 MFP Mask */\r
+#define UART4_RXD_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! UART4_RXD PF6 MFP Mask */\r
+#define UART4_TXD_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! UART4_TXD PH10 MFP Mask */\r
+#define UART4_TXD_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! UART4_TXD PA3 MFP Mask */\r
+#define UART4_TXD_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! UART4_TXD PA12 MFP Mask */\r
+#define UART4_TXD_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! UART4_TXD PC7 MFP Mask */\r
+#define UART4_TXD_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! UART4_TXD PB11 MFP Mask */\r
+#define UART4_TXD_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! UART4_TXD PF7 MFP Mask */\r
+#define UART4_TXD_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! UART4_TXD PC5 MFP Mask */\r
+#define UART4_nCTS_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! UART4_nCTS PE1 MFP Mask */\r
+#define UART4_nCTS_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! UART4_nCTS PC8 MFP Mask */\r
+#define UART4_nRTS_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! UART4_nRTS PE0 MFP Mask */\r
+#define UART4_nRTS_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! UART4_nRTS PE13 MFP Mask */\r
+#define UART5_RXD_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! UART5_RXD PB4 MFP Mask */\r
+#define UART5_RXD_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! UART5_RXD PA4 MFP Mask */\r
+#define UART5_RXD_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! UART5_RXD PE6 MFP Mask */\r
+#define UART5_TXD_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! UART5_TXD PB5 MFP Mask */\r
+#define UART5_TXD_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! UART5_TXD PE7 MFP Mask */\r
+#define UART5_TXD_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! UART5_TXD PA5 MFP Mask */\r
+#define UART5_nCTS_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! UART5_nCTS PB2 MFP Mask */\r
+#define UART5_nRTS_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! UART5_nRTS PB3 MFP Mask */\r
+#define USB_D_P_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! USB_D_P PA14 MFP Mask */\r
+#define USB_D_N_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! USB_D_N PA13 MFP Mask */\r
+#define USB_OTG_ID_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! USB_OTG_ID PA15 MFP Mask */\r
+#define USB_VBUS_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! USB_VBUS PA12 MFP Mask */\r
+#define USB_VBUS_EN_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! USB_VBUS_EN PB6 MFP Mask */\r
+#define USB_VBUS_EN_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! USB_VBUS_EN PB15 MFP Mask */\r
+#define USB_VBUS_ST_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! USB_VBUS_ST PB14 MFP Mask */\r
+#define USB_VBUS_ST_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! USB_VBUS_ST PB7 MFP Mask */\r
+#define USB_VBUS_ST_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! USB_VBUS_ST PD4 MFP Mask */\r
+#define USCI0_CLK_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! USCI0_CLK PD0 MFP Mask */\r
+#define USCI0_CLK_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! USCI0_CLK PA11 MFP Mask */\r
+#define USCI0_CLK_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! USCI0_CLK PE2 MFP Mask */\r
+#define USCI0_CLK_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! USCI0_CLK PB12 MFP Mask */\r
+#define USCI0_CTL0_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! USCI0_CTL0 PD4 MFP Mask */\r
+#define USCI0_CTL0_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! USCI0_CTL0 PE6 MFP Mask */\r
+#define USCI0_CTL0_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! USCI0_CTL0 PC13 MFP Mask */\r
+#define USCI0_CTL0_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! USCI0_CTL0 PD14 MFP Mask */\r
+#define USCI0_CTL1_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! USCI0_CTL1 PD3 MFP Mask */\r
+#define USCI0_CTL1_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! USCI0_CTL1 PE5 MFP Mask */\r
+#define USCI0_CTL1_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! USCI0_CTL1 PB15 MFP Mask */\r
+#define USCI0_CTL1_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! USCI0_CTL1 PA8 MFP Mask */\r
+#define USCI0_DAT0_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! USCI0_DAT0 PE3 MFP Mask */\r
+#define USCI0_DAT0_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! USCI0_DAT0 PB13 MFP Mask */\r
+#define USCI0_DAT0_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! USCI0_DAT0 PD1 MFP Mask */\r
+#define USCI0_DAT0_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! USCI0_DAT0 PA10 MFP Mask */\r
+#define USCI0_DAT1_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! USCI0_DAT1 PE4 MFP Mask */\r
+#define USCI0_DAT1_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! USCI0_DAT1 PD2 MFP Mask */\r
+#define USCI0_DAT1_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! USCI0_DAT1 PB14 MFP Mask */\r
+#define USCI0_DAT1_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! USCI0_DAT1 PA9 MFP Mask */\r
+#define USCI1_CLK_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! USCI1_CLK PE12 MFP Mask */\r
+#define USCI1_CLK_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! USCI1_CLK PD7 MFP Mask */\r
+#define USCI1_CLK_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! USCI1_CLK PB8 MFP Mask */\r
+#define USCI1_CLK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! USCI1_CLK PB1 MFP Mask */\r
+#define USCI1_CTL0_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! USCI1_CTL0 PB10 MFP Mask */\r
+#define USCI1_CTL0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! USCI1_CTL0 PB5 MFP Mask */\r
+#define USCI1_CTL0_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! USCI1_CTL0 PE9 MFP Mask */\r
+#define USCI1_CTL0_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! USCI1_CTL0 PD3 MFP Mask */\r
+#define USCI1_CTL1_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! USCI1_CTL1 PD4 MFP Mask */\r
+#define USCI1_CTL1_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! USCI1_CTL1 PE8 MFP Mask */\r
+#define USCI1_CTL1_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! USCI1_CTL1 PB9 MFP Mask */\r
+#define USCI1_CTL1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! USCI1_CTL1 PB4 MFP Mask */\r
+#define USCI1_DAT0_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! USCI1_DAT0 PB2 MFP Mask */\r
+#define USCI1_DAT0_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! USCI1_DAT0 PB7 MFP Mask */\r
+#define USCI1_DAT0_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! USCI1_DAT0 PE10 MFP Mask */\r
+#define USCI1_DAT0_PD5_Msk SYS_GPD_MFPL_PD5MFP_Msk /*<! USCI1_DAT0 PD5 MFP Mask */\r
+#define USCI1_DAT1_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! USCI1_DAT1 PD6 MFP Mask */\r
+#define USCI1_DAT1_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! USCI1_DAT1 PB3 MFP Mask */\r
+#define USCI1_DAT1_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! USCI1_DAT1 PE11 MFP Mask */\r
+#define USCI1_DAT1_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! USCI1_DAT1 PB6 MFP Mask */\r
+#define X32_IN_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! X32_IN PF5 MFP Mask */\r
+#define X32_OUT_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! X32_OUT PF4 MFP Mask */\r
+#define XT1_IN_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! XT1_IN PF3 MFP Mask */\r
+#define XT1_OUT_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! XT1_OUT PF2 MFP Mask */\r
+\r
+\r
+\r
+/*@}*/ /* end of group SYS_EXPORTED_CONSTANTS */\r
+\r
+/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions\r
+ @{\r
+*/\r
+\r
+\r
+/**\r
+ * @brief Clear Brown-out detector interrupt flag\r
+ * @param None\r
+ * @return None\r
+ * @details This macro clear Brown-out detector interrupt flag.\r
+ */\r
+#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)\r
+\r
+/**\r
+ * @brief Set Brown-out detector function to normal mode\r
+ * @param None\r
+ * @return None\r
+ * @details This macro set Brown-out detector to normal mode.\r
+ * The register write-protection function should be disabled before using this macro.\r
+ */\r
+#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)\r
+\r
+/**\r
+ * @brief Disable Brown-out detector function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro disable Brown-out detector function.\r
+ * The register write-protection function should be disabled before using this macro.\r
+ */\r
+#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)\r
+\r
+/**\r
+ * @brief Enable Brown-out detector function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro enable Brown-out detector function.\r
+ * The register write-protection function should be disabled before using this macro.\r
+ */\r
+#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)\r
+\r
+/**\r
+ * @brief Get Brown-out detector interrupt flag\r
+ * @param None\r
+ * @retval 0 Brown-out detect interrupt flag is not set.\r
+ * @retval >=1 Brown-out detect interrupt flag is set.\r
+ * @details This macro get Brown-out detector interrupt flag.\r
+ */\r
+#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)\r
+\r
+/**\r
+ * @brief Get Brown-out detector status\r
+ * @param None\r
+ * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled.\r
+ * @retval >=1 System voltage is lower than BOD threshold voltage setting.\r
+ * @details This macro get Brown-out detector output status.\r
+ * If the BOD function is disabled, this function always return 0.\r
+ */\r
+#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)\r
+\r
+/**\r
+ * @brief Enable Brown-out detector interrupt function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro enable Brown-out detector interrupt function.\r
+ * The register write-protection function should be disabled before using this macro.\r
+ */\r
+#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)\r
+\r
+/**\r
+ * @brief Enable Brown-out detector reset function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro enable Brown-out detect reset function.\r
+ * The register write-protection function should be disabled before using this macro.\r
+ */\r
+#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)\r
+\r
+/**\r
+ * @brief Set Brown-out detector function low power mode\r
+ * @param None\r
+ * @return None\r
+ * @details This macro set Brown-out detector to low power mode.\r
+ * The register write-protection function should be disabled before using this macro.\r
+ */\r
+#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)\r
+\r
+/**\r
+ * @brief Set Brown-out detector voltage level\r
+ * @param[in] u32Level is Brown-out voltage level. Including :\r
+ * - \ref SYS_BODCTL_BODVL_1_6V\r
+ * - \ref SYS_BODCTL_BODVL_1_8V\r
+ * - \ref SYS_BODCTL_BODVL_2_0V\r
+ * - \ref SYS_BODCTL_BODVL_2_2V\r
+ * - \ref SYS_BODCTL_BODVL_2_4V\r
+ * - \ref SYS_BODCTL_BODVL_2_6V\r
+ * - \ref SYS_BODCTL_BODVL_2_8V\r
+ * - \ref SYS_BODCTL_BODVL_3_0V\r
+ * @return None\r
+ * @details This macro set Brown-out detector voltage level.\r
+ * The write-protection function should be disabled before using this macro.\r
+ */\r
+#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))\r
+\r
+/**\r
+ * @brief Get reset source is from Brown-out detector reset\r
+ * @param None\r
+ * @retval 0 Previous reset source is not from Brown-out detector reset\r
+ * @retval >=1 Previous reset source is from Brown-out detector reset\r
+ * @details This macro get previous reset source is from Brown-out detect reset or not.\r
+ */\r
+#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)\r
+\r
+/**\r
+ * @brief Get reset source is from CPU reset\r
+ * @param None\r
+ * @retval 0 Previous reset source is not from CPU reset\r
+ * @retval >=1 Previous reset source is from CPU reset\r
+ * @details This macro get previous reset source is from CPU reset.\r
+ */\r
+#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)\r
+\r
+/**\r
+ * @brief Get reset source is from LVR Reset\r
+ * @param None\r
+ * @retval 0 Previous reset source is not from Low-Voltage-Reset\r
+ * @retval >=1 Previous reset source is from Low-Voltage-Reset\r
+ * @details This macro get previous reset source is from Low-Voltage-Reset.\r
+ */\r
+#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)\r
+\r
+/**\r
+ * @brief Get reset source is from Power-on Reset\r
+ * @param None\r
+ * @retval 0 Previous reset source is not from Power-on Reset\r
+ * @retval >=1 Previous reset source is from Power-on Reset\r
+ * @details This macro get previous reset source is from Power-on Reset.\r
+ */\r
+#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)\r
+\r
+/**\r
+ * @brief Get reset source is from reset pin reset\r
+ * @param None\r
+ * @retval 0 Previous reset source is not from reset pin reset\r
+ * @retval >=1 Previous reset source is from reset pin reset\r
+ * @details This macro get previous reset source is from reset pin reset.\r
+ */\r
+#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)\r
+\r
+/**\r
+ * @brief Get reset source is from system reset\r
+ * @param None\r
+ * @retval 0 Previous reset source is not from system reset\r
+ * @retval >=1 Previous reset source is from system reset\r
+ * @details This macro get previous reset source is from system reset.\r
+ */\r
+#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)\r
+\r
+/**\r
+ * @brief Get reset source is from window watch dog reset\r
+ * @param None\r
+ * @retval 0 Previous reset source is not from window watch dog reset\r
+ * @retval >=1 Previous reset source is from window watch dog reset\r
+ * @details This macro get previous reset source is from window watch dog reset.\r
+ */\r
+#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)\r
+\r
+/**\r
+ * @brief Disable Low-Voltage-Reset function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro disable Low-Voltage-Reset function.\r
+ * The register write-protection function should be disabled before using this macro.\r
+ */\r
+#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)\r
+\r
+/**\r
+ * @brief Enable Low-Voltage-Reset function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro enable Low-Voltage-Reset function.\r
+ * The register write-protection function should be disabled before using this macro.\r
+ */\r
+#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)\r
+\r
+/**\r
+ * @brief Disable Power-on Reset function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro disable Power-on Reset function.\r
+ * The register write-protection function should be disabled before using this macro.\r
+ */\r
+#define SYS_DISABLE_POR() (SYS->PORCTL0 = 0x5AA5)\r
+\r
+/**\r
+ * @brief Enable Power-on Reset function\r
+ * @param None\r
+ * @return None\r
+ * @details This macro enable Power-on Reset function.\r
+ * The register write-protection function should be disabled before using this macro.\r
+ */\r
+#define SYS_ENABLE_POR() (SYS->PORCTL0 = 0)\r
+\r
+/**\r
+ * @brief Clear reset source flag\r
+ * @param[in] u32RstSrc is reset source. Including :\r
+ * - \ref SYS_RSTSTS_PORF_Msk\r
+ * - \ref SYS_RSTSTS_PINRF_Msk\r
+ * - \ref SYS_RSTSTS_WDTRF_Msk\r
+ * - \ref SYS_RSTSTS_LVRF_Msk\r
+ * - \ref SYS_RSTSTS_BODRF_Msk\r
+ * - \ref SYS_RSTSTS_SYSRF_Msk\r
+ * - \ref SYS_RSTSTS_CPURF_Msk\r
+ * - \ref SYS_RSTSTS_CPULKRF_Msk\r
+ * @return None\r
+ * @details This macro clear reset source flag.\r
+ */\r
+#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* static inline functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */\r
+__STATIC_INLINE void SYS_UnlockReg(void);\r
+__STATIC_INLINE void SYS_LockReg(void);\r
+\r
+\r
+/**\r
+ * @brief Disable register write-protection function\r
+ * @param None\r
+ * @return None\r
+ * @details This function disable register write-protection function.\r
+ * To unlock the protected register to allow write access.\r
+ */\r
+__STATIC_INLINE void SYS_UnlockReg(void)\r
+{\r
+ do\r
+ {\r
+ SYS->REGLCTL = 0x59UL;\r
+ SYS->REGLCTL = 0x16UL;\r
+ SYS->REGLCTL = 0x88UL;\r
+ }\r
+ while(SYS->REGLCTL == 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Enable register write-protection function\r
+ * @param None\r
+ * @return None\r
+ * @details This function is used to enable register write-protection function.\r
+ * To lock the protected register to forbid write access.\r
+ */\r
+__STATIC_INLINE void SYS_LockReg(void)\r
+{\r
+ SYS->REGLCTL = 0UL;\r
+}\r
+\r
+\r
+void SYS_ClearResetSrc(uint32_t u32Src);\r
+uint32_t SYS_GetBODStatus(void);\r
+uint32_t SYS_GetResetSrc(void);\r
+uint32_t SYS_IsRegLocked(void);\r
+uint32_t SYS_ReadPDID(void);\r
+void SYS_ResetChip(void);\r
+void SYS_ResetCPU(void);\r
+void SYS_ResetModule(uint32_t u32ModuleIndex);\r
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);\r
+void SYS_DisableBOD(void);\r
+void SYS_SetPowerLevel(uint32_t u32PowerLevel);\r
+uint32_t SYS_SetPowerRegulator(uint32_t u32PowerRegulator);\r
+void SYS_SetSSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode);\r
+void SYS_SetPSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode);\r
+\r
+\r
+/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group SYS_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SYS_H__ */\r
+\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file timer.h\r
+ * @version V3.00\r
+ * @brief Timer Controller(Timer) driver header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup TIMER_Driver TIMER Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants\r
+ @{\r
+*/\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode \hideinitializer */\r
+#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode \hideinitializer */\r
+#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode \hideinitializer */\r
+#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode \hideinitializer */\r
+#define TIMER_TOUT_PIN_FROM_TMX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx pin \hideinitializer */\r
+#define TIMER_TOUT_PIN_FROM_TMX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx_EXT pin \hideinitializer */\r
+\r
+#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */\r
+#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */\r
+#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */\r
+#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */\r
+\r
+#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event \hideinitializer */\r
+#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event \hideinitializer */\r
+#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge \hideinitializer */\r
+#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge \hideinitializer */\r
+#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge \hideinitializer */\r
+#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge \hideinitializer */\r
+\r
+#define TIMER_TRGSRC_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event \hideinitializer */\r
+#define TIMER_TRGSRC_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event \hideinitializer */\r
+#define TIMER_TRG_TO_EPWM (TIMER_TRGCTL_TRGEPWM_Msk) /*!< Each timer event as EPWM counter clock source \hideinitializer */\r
+#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk) /*!< Each timer event to start ADC conversion \hideinitializer */\r
+#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk) /*!< Each timer event to start DAC conversion \hideinitializer */\r
+#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk) /*!< Each timer event to trigger PDMA transfer \hideinitializer */\r
+\r
+/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Set Timer Compared Value\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to set timer compared value to adjust timer time-out interval.\r
+ * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n\r
+ * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n\r
+ * But if timer is operating at other modes, the timer up counter will restart counting and start from 0.\r
+ * \hideinitializer\r
+ */\r
+#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value))\r
+\r
+/**\r
+ * @brief Set Timer Prescale Value\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n\r
+ * before it is fed into timer.\r
+ * \hideinitializer\r
+ */\r
+#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))\r
+\r
+/**\r
+ * @brief Check specify Timer Status\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @retval 0 Timer 24-bit up counter is inactive\r
+ * @retval 1 Timer 24-bit up counter is active\r
+ *\r
+ * @details This macro is used to check if specify Timer counter is inactive or active.\r
+ * \hideinitializer\r
+ */\r
+#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0)\r
+\r
+/**\r
+ * @brief Select Toggle-output Pin\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32ToutSel Toggle-output pin selection, valid values are:\r
+ * - \ref TIMER_TOUT_PIN_FROM_TMX\r
+ * - \ref TIMER_TOUT_PIN_FROM_TMX_EXT\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin.\r
+ * \hideinitializer\r
+ */\r
+#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* static inline functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */\r
+__STATIC_INLINE void TIMER_Start(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_Stop(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer);\r
+__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer);\r
+__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer);\r
+__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer);\r
+__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer);\r
+__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer);\r
+__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer);\r
+\r
+\r
+/**\r
+ * @brief Start Timer Counting\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to start Timer counting.\r
+ */\r
+__STATIC_INLINE void TIMER_Start(TIMER_T *timer)\r
+{\r
+ timer->CTL |= TIMER_CTL_CNTEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Stop Timer Counting\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to stop/suspend Timer counting.\r
+ */\r
+__STATIC_INLINE void TIMER_Stop(TIMER_T *timer)\r
+{\r
+ timer->CTL &= ~TIMER_CTL_CNTEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable Timer Interrupt Wake-up Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n\r
+ * counter event interrupt or capture trigger interrupt.\r
+ * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC.\r
+ */\r
+__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer)\r
+{\r
+ timer->CTL |= TIMER_CTL_WKEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable Timer Wake-up Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable the timer interrupt wake-up function.\r
+ */\r
+__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer)\r
+{\r
+ timer->CTL &= ~TIMER_CTL_WKEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Start Timer Capture Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to start Timer capture function.\r
+ */\r
+__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer)\r
+{\r
+ timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Stop Timer Capture Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to stop Timer capture function.\r
+ */\r
+__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer)\r
+{\r
+ timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable Capture Pin De-bounce\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable the detect de-bounce function of capture pin.\r
+ */\r
+__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)\r
+{\r
+ timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable Capture Pin De-bounce\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable the detect de-bounce function of capture pin.\r
+ */\r
+__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)\r
+{\r
+ timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable Counter Pin De-bounce\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable the detect de-bounce function of counter pin.\r
+ */\r
+__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)\r
+{\r
+ timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable Counter Pin De-bounce\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable the detect de-bounce function of counter pin.\r
+ */\r
+__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)\r
+{\r
+ timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable Timer Time-out Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable the timer time-out interrupt function.\r
+ */\r
+__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer)\r
+{\r
+ timer->CTL |= TIMER_CTL_INTEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable Timer Time-out Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable the timer time-out interrupt function.\r
+ */\r
+__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer)\r
+{\r
+ timer->CTL &= ~TIMER_CTL_INTEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable Capture Trigger Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable the timer capture trigger interrupt function.\r
+ */\r
+__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)\r
+{\r
+ timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable Capture Trigger Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable the timer capture trigger interrupt function.\r
+ */\r
+__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)\r
+{\r
+ timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Get Timer Time-out Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @retval 0 Timer time-out interrupt did not occur\r
+ * @retval 1 Timer time-out interrupt occurred\r
+ *\r
+ * @details This function indicates timer time-out interrupt occurred or not.\r
+ */\r
+__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)\r
+{\r
+ return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Clear Timer Time-out Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function clears timer time-out interrupt flag to 0.\r
+ */\r
+__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer)\r
+{\r
+ timer->INTSTS = TIMER_INTSTS_TIF_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Get Timer Capture Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @retval 0 Timer capture interrupt did not occur\r
+ * @retval 1 Timer capture interrupt occurred\r
+ *\r
+ * @details This function indicates timer capture trigger interrupt occurred or not.\r
+ */\r
+__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)\r
+{\r
+ return timer->EINTSTS;\r
+}\r
+\r
+/**\r
+ * @brief Clear Timer Capture Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function clears timer capture trigger interrupt flag to 0.\r
+ */\r
+__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)\r
+{\r
+ timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Get Timer Wake-up Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @retval 0 Timer does not cause CPU wake-up\r
+ * @retval 1 Timer interrupt event cause CPU wake-up\r
+ *\r
+ * @details This function indicates timer interrupt event has waked up system or not.\r
+ */\r
+__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)\r
+{\r
+ return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Clear Timer Wake-up Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function clears the timer wake-up system flag to 0.\r
+ */\r
+__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)\r
+{\r
+ timer->INTSTS = TIMER_INTSTS_TWKF_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Get Capture value\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return 24-bit Capture Value\r
+ *\r
+ * @details This function reports the current 24-bit timer capture value.\r
+ */\r
+__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)\r
+{\r
+ return timer->CAP;\r
+}\r
+\r
+/**\r
+ * @brief Get Counter value\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return 24-bit Counter Value\r
+ *\r
+ * @details This function reports the current 24-bit timer counter value.\r
+ */\r
+__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)\r
+{\r
+ return timer->CNT;\r
+}\r
+\r
+/**\r
+ * @brief Reset Counter\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to reset current counter value and internal prescale counter value.\r
+ */\r
+__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer)\r
+{\r
+ timer->CNT = 0UL;\r
+ while((timer->CNT & TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk) {}\r
+}\r
+\r
+\r
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);\r
+void TIMER_Close(TIMER_T *timer);\r
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);\r
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);\r
+void TIMER_DisableCapture(TIMER_T *timer);\r
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);\r
+void TIMER_DisableEventCounter(TIMER_T *timer);\r
+uint32_t TIMER_GetModuleClock(TIMER_T *timer);\r
+void TIMER_EnableFreqCounter(TIMER_T *timer, uint32_t u32DropCount, uint32_t u32Timeout, uint32_t u32EnableInt);\r
+void TIMER_DisableFreqCounter(TIMER_T *timer);\r
+void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src);\r
+void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask);\r
+\r
+/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group TIMER_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __TIMER_H__ */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file timer.h\r
+ * @version V3.00\r
+ * @brief Timer PWM Controller(Timer PWM) driver header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __TIMER_PWM_H__\r
+#define __TIMER_PWM_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants\r
+ @{\r
+*/\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Output Channel Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 \hideinitializer */\r
+#define TPWM_CH1 (BIT1) /*!< Indicate PWMx_CH1 \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Counter Type Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define TPWM_UP_COUNT (0UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up count type \hideinitializer */\r
+#define TPWM_DOWN_COUNT (1UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Down count type \hideinitializer */\r
+#define TPWM_UP_DOWN_COUNT (2UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up-Down count type \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Counter Mode Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode \hideinitializer */\r
+#define TPWM_ONE_SHOT_MODE (TIMER_PWMCTL_CNTMODE_Msk) /*!< One-shot mode \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Output Level Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define TPWM_OUTPUT_TOGGLE (0UL) /*!< Timer PWM output toggle \hideinitializer */\r
+#define TPWM_OUTPUT_NOTHING (1UL) /*!< Timer PWM output nothing \hideinitializer */\r
+#define TPWM_OUTPUT_LOW (2UL) /*!< Timer PWM output low \hideinitializer */\r
+#define TPWM_OUTPUT_HIGH (3UL) /*!< Timer PWM output high \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Trigger ADC Source Select Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define TPWM_TRIGGER_ADC_AT_ZERO_POINT (0UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero point event occurred \hideinitializer */\r
+#define TPWM_TRIGGER_ADC_AT_PERIOD_POINT (1UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter period point event occurred \hideinitializer */\r
+#define TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT (2UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero or period point event occurred \hideinitializer */\r
+#define TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT (3UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter up count compare point event occurred \hideinitializer */\r
+#define TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT (4UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter down count compare point event occurred \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Brake Control Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define TPWM_BRAKE_SOURCE_EDGE_ACMP0 (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */\r
+#define TPWM_BRAKE_SOURCE_EDGE_ACMP1 (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */\r
+#define TPWM_BRAKE_SOURCE_EDGE_BKPIN (TIMER_PWMBRKCTL_BRKPEEN_Msk) /*!< Brake pin as edge-detect fault brake source \hideinitializer */\r
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */\r
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */\r
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */\r
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */\r
+\r
+#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0 (TIMER_PWMBRKCTL_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */\r
+#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1 (TIMER_PWMBRKCTL_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */\r
+#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN (TIMER_PWMBRKCTL_BRKPLEN_Msk) /*!< Brake pin as level-detect fault brake source \hideinitializer */\r
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */\r
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */\r
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */\r
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */\r
+\r
+#define TPWM_BRAKE_EDGE (TIMER_PWMSWBRK_BRKETRG_Msk) /*!< Edge-detect fault brake \hideinitializer */\r
+#define TPWM_BRAKE_LEVEL (TIMER_PWMSWBRK_BRKLTRG_Msk) /*!< Level-detect fault brake \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Load Mode Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define TPWM_LOAD_MODE_PERIOD (0UL) /*!< Timer PWM period load mode \hideinitializer */\r
+#define TPWM_LOAD_MODE_IMMEDIATE (TIMER_PWMCTL_IMMLDEN_Msk) /*!< Timer PWM immediately load mode \hideinitializer */\r
+#define TPWM_LOAD_MODE_CENTER (TIMER_PWMCTL_CTRLD_Msk) /*!< Timer PWM center load mode \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Brake Pin De-bounce Clock Source Select Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define TPWM_BKP_DBCLK_PCLK_DIV_1 (0UL) /*!< De-bounce clock is PCLK divide by 1 \hideinitializer */\r
+#define TPWM_BKP_DBCLK_PCLK_DIV_2 (1UL) /*!< De-bounce clock is PCLK divide by 2 \hideinitializer */\r
+#define TPWM_BKP_DBCLK_PCLK_DIV_4 (2UL) /*!< De-bounce clock is PCLK divide by 4 \hideinitializer */\r
+#define TPWM_BKP_DBCLK_PCLK_DIV_8 (3UL) /*!< De-bounce clock is PCLK divide by 8 \hideinitializer */\r
+#define TPWM_BKP_DBCLK_PCLK_DIV_16 (4UL) /*!< De-bounce clock is PCLK divide by 16 \hideinitializer */\r
+#define TPWM_BKP_DBCLK_PCLK_DIV_32 (5UL) /*!< De-bounce clock is PCLK divide by 32 \hideinitializer */\r
+#define TPWM_BKP_DBCLK_PCLK_DIV_64 (6UL) /*!< De-bounce clock is PCLK divide by 64 \hideinitializer */\r
+#define TPWM_BKP_DBCLK_PCLK_DIV_128 (7UL) /*!< De-bounce clock is PCLK divide by 128 \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Brake Pin Source Select Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define TPWM_TM_BRAKE0 (0UL) /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer */\r
+#define TPWM_TM_BRAKE1 (1UL) /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer */\r
+#define TPWM_TM_BRAKE2 (2UL) /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer */\r
+#define TPWM_TM_BRAKE3 (3UL) /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Counter Clock Source Select Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define TPWM_CNTR_CLKSRC_TMR_CLK (0UL) /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer */\r
+#define TPWM_CNTR_CLKSRC_TIMER0_INT (1UL) /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer */\r
+#define TPWM_CNTR_CLKSRC_TIMER1_INT (2UL) /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer */\r
+#define TPWM_CNTR_CLKSRC_TIMER2_INT (3UL) /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer */\r
+#define TPWM_CNTR_CLKSRC_TIMER3_INT (4UL) /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Counter Synchronous Mode Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define TPWM_CNTR_SYNC_DISABLE (0UL) /*!< Disable TIMER PWM synchronous function \hideinitializer */\r
+#define TPWM_CNTR_SYNC_START_BY_TIMER0 ((0<<TIMER_PWMSCTL_SYNCSRC_Pos) | (1<<TIMER_PWMSCTL_SYNCMODE_Pos)) /*!< PWM counter synchronous start by TIMER0 PWM \hideinitializer */\r
+#define TPWM_CNTR_SYNC_CLEAR_BY_TIMER0 ((0<<TIMER_PWMSCTL_SYNCSRC_Pos) | (3<<TIMER_PWMSCTL_SYNCMODE_Pos)) /*!< PWM counter synchronous clear by TIMER0 PWM \hideinitializer */\r
+#define TPWM_CNTR_SYNC_START_BY_TIMER2 ((1<<TIMER_PWMSCTL_SYNCSRC_Pos) | (1<<TIMER_PWMSCTL_SYNCMODE_Pos)) /*!< PWM counter synchronous start by TIMER2 PWM \hideinitializer */\r
+#define TPWM_CNTR_SYNC_CLEAR_BY_TIMER2 ((1<<TIMER_PWMSCTL_SYNCSRC_Pos) | (3<<TIMER_PWMSCTL_SYNCMODE_Pos)) /*!< PWM counter synchronous clear by TIMER2 PWM \hideinitializer */\r
+\r
+/*@}*/ /* end of group TIMER_PWM_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Enable PWM Counter Mode\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable specified Timer channel as PWM counter mode, then timer counter mode is invalid.\r
+ * @note All registers about time counter function will be cleared to 0 and timer clock source will be changed to PCLKx automatically after executing this macro.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_ENABLE_PWM_MODE(timer) ((timer)->ALTCTL = (1 << TIMER_ALTCTL_FUNCSEL_Pos))\r
+\r
+/**\r
+ * @brief Disable PWM Counter Mode\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available.\r
+ * @note All registers about PWM counter function will be cleared to 0 after executing this macro.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_DISABLE_PWM_MODE(timer) ((timer)->ALTCTL = (0 << TIMER_ALTCTL_FUNCSEL_Pos))\r
+\r
+/**\r
+ * @brief Enable Independent Mode\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_ENABLE_INDEPENDENT_MODE(timer) ((timer)->PWMCTL &= ~(1 << TIMER_PWMCTL_OUTMODE_Pos))\r
+\r
+/**\r
+ * @brief Enable Complementary Mode\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer) ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos))\r
+\r
+/**\r
+ * @brief Set Counter Type\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] type Timer PWM count type, could be one of the following type\r
+ * - \ref TPWM_UP_COUNT\r
+ * - \ref TPWM_DOWN_COUNT\r
+ * - \ref TPWM_UP_DOWN_COUNT\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to set Timer PWM counter type.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_SET_COUNTER_TYPE(timer, type) ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (type))\r
+\r
+/**\r
+ * @brief Start PWM Counter\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable PWM generator and start counter counting.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk)\r
+\r
+/**\r
+ * @brief Stop PWM Counter\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to stop PWM counter after current period is completed.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0)\r
+\r
+/**\r
+ * @brief Set Counter Clock Prescaler\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @param[in] prescaler Clock prescaler of specified channel. Valid values are between 0x0~0xFFF.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to set the prescaler of specified TIMER PWM.\r
+ * @note If prescaler is 0, then there is no scaling in counter clock source.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_SET_PRESCALER(timer, prescaler) ((timer)->PWMCLKPSC = (prescaler))\r
+\r
+/**\r
+ * @brief Get Counter Clock Prescaler\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0])\r
+ *\r
+ * @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1).\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC)\r
+\r
+/**\r
+ * @brief Set Couner Period\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @param[in] period Period of specified channel. Valid values are between 0x0~0xFFFF.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to set the period of specified TIMER PWM.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_SET_PERIOD(timer, period) ((timer)->PWMPERIOD = (period))\r
+\r
+/**\r
+ * @brief Get Couner Period\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0])\r
+ *\r
+ * @details This macro is used to get the period of specified TIMER PWM.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD)\r
+\r
+/**\r
+ * @brief Set Comparator Value\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @param[in] cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to set the comparator value of specified TIMER PWM.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_SET_CMPDAT(timer, cmp) ((timer)->PWMCMPDAT = (cmp))\r
+\r
+/**\r
+ * @brief Get Comparator Value\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0])\r
+ *\r
+ * @details This macro is used to get the comparator value of specified TIMER PWM.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT)\r
+\r
+/**\r
+ * @brief Clear Counter\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to clear counter of specified TIMER PWM.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk)\r
+\r
+/**\r
+ * @brief Software Trigger Brake Event\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @param[in] type Type of brake trigger. Valid values are:\r
+ * - \ref TPWM_BRAKE_EDGE\r
+ * - \ref TPWM_BRAKE_LEVEL\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to trigger brake event by writing PWMSWBRK register.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_SW_TRIGGER_BRAKE(timer, type) ((timer)->PWMSWBRK = (type))\r
+\r
+/**\r
+ * @brief Enable Output Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @param[in] ch Enable specified channel output function. Valid values are:\r
+ * - \ref TPWM_CH0\r
+ * - \ref TPWM_CH1\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable output function of specified output pins.\r
+ * @note If the corresponding bit in u32ChMask parameter is 0, then output function will be disabled in this channel.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_ENABLE_OUTPUT(timer, ch) ((timer)->PWMPOEN = (ch))\r
+\r
+/**\r
+ * @brief Set Output Inverse\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @param[in] ch Set specified channel output is inversed or not. Valid values are:\r
+ * - \ref TPWM_CH0\r
+ * - \ref TPWM_CH1\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable output inverse of specified output pins.\r
+ * @note If u32ChMask parameter is 0, then output inverse function will be disabled.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_SET_OUTPUT_INVERSE(timer, ch) ((timer)->PWMPOLCTL = (ch))\r
+\r
+/**\r
+ * @brief Enable Output Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @param[in] ch Enable specified channel output mask function. Valid values are:\r
+ * - \ref TPWM_CH0\r
+ * - \ref TPWM_CH1\r
+ *\r
+ * @param[in] level Output to high or low on specified mask channel.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable output function of specified output pins.\r
+ * @note If u32ChMask parameter is 0, then output mask function will be disabled.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_SET_MASK_OUTPUT(timer, ch, level) do {(timer)->PWMMSKEN = (ch); (timer)->PWMMSK = (level); }while(0)\r
+\r
+/**\r
+ * @brief Set Counter Synchronous Mode\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @param[in] mode Synchronous mode. Possible options are:\r
+ * - \ref TPWM_CNTR_SYNC_DISABLE\r
+ * - \ref TPWM_CNTR_SYNC_START_BY_TIMER0\r
+ * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0\r
+ * - \ref TPWM_CNTR_SYNC_START_BY_TIMER2\r
+ * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to set counter synchronous mode of specified Timer PWM module.\r
+ * @note Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and\r
+ * TIMER2~3 PWM counter synchronous by TIMER2 PWM.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode) ((timer)->PWMSCTL = (mode))\r
+\r
+/**\r
+ * @brief Trigger Counter Synchronous\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to trigger synchronous event by specified TIMER PWM.\r
+ * @note 1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n\r
+ * 2. STRGEN (PWMSTRG[0]) is write only and always read as 0.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_TRIGGER_COUNTER_SYNC(timer) ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk)\r
+\r
+/**\r
+ * @brief Enable Zero Event Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable the zero event interrupt function.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_ENABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk)\r
+\r
+/**\r
+ * @brief Disable Zero Event Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to disable the zero event interrupt function.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_DISABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk)\r
+\r
+/**\r
+ * @brief Get Zero Event Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @retval 0 Zero event interrupt did not occur\r
+ * @retval 1 Zero event interrupt occurred\r
+ *\r
+ * @details This macro indicates zero event occurred or not.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_GET_ZERO_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0)\r
+\r
+/**\r
+ * @brief Clear Zero Event Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro clears zero event interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_CLEAR_ZERO_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk)\r
+\r
+/**\r
+ * @brief Enable Period Event Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable the period event interrupt function.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk)\r
+\r
+/**\r
+ * @brief Disable Period Event Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to disable the period event interrupt function.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk)\r
+\r
+/**\r
+ * @brief Get Period Event Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @retval 0 Period event interrupt did not occur\r
+ * @retval 1 Period event interrupt occurred\r
+ *\r
+ * @details This macro indicates period event occurred or not.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0)\r
+\r
+/**\r
+ * @brief Clear Period Event Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro clears period event interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk)\r
+\r
+/**\r
+ * @brief Enable Compare Up Event Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable the compare up event interrupt function.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk)\r
+\r
+/**\r
+ * @brief Disable Compare Up Event Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to disable the compare up event interrupt function.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk)\r
+\r
+/**\r
+ * @brief Get Compare Up Event Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @retval 0 Compare up event interrupt did not occur\r
+ * @retval 1 Compare up event interrupt occurred\r
+ *\r
+ * @details This macro indicates compare up event occurred or not.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0)\r
+\r
+/**\r
+ * @brief Clear Compare Up Event Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro clears compare up event interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk)\r
+\r
+/**\r
+ * @brief Enable Compare Down Event Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to enable the compare down event interrupt function.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_ENABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk)\r
+\r
+/**\r
+ * @brief Disable Compare Down Event Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to disable the compare down event interrupt function.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_DISABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk)\r
+\r
+/**\r
+ * @brief Get Compare Down Event Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @retval 0 Compare down event interrupt did not occur\r
+ * @retval 1 Compare down event interrupt occurred\r
+ *\r
+ * @details This macro indicates compare down event occurred or not.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_GET_CMP_DOWN_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0)\r
+\r
+/**\r
+ * @brief Clear Compare Down Event Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro clears compare down event interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk)\r
+\r
+/**\r
+ * @brief Get Counter Reach Maximum Count Status\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @retval 0 Timer PWM counter never counts to maximum value\r
+ * @retval 1 Timer PWM counter counts to maximum value, 0xFFFF\r
+ *\r
+ * @details This macro indicates Timer PWM counter has count to 0xFFFF or not.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0)\r
+\r
+/**\r
+ * @brief Clear Counter Reach Maximum Count Status\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro clears reach maximum count status.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk)\r
+\r
+/**\r
+ * @brief Get Trigger ADC Status\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @retval 0 Trigger ADC start conversion is not occur\r
+ * @retval 1 Specified counter compare event has trigger ADC start conversion\r
+ *\r
+ * @details This macro is used to indicate PWM counter compare event has triggered ADC start conversion.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_GET_TRG_ADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0)\r
+\r
+/**\r
+ * @brief Clear Trigger ADC Status\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to clear PWM counter compare event trigger ADC status.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_CLEAR_TRG_ADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk)\r
+\r
+/**\r
+ * @brief Set Brake Event at Brake Pin High or Low-to-High\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high.\r
+ * @note The default brake pin detection is high level or from low to high.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer) ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk)\r
+\r
+/**\r
+ * @brief Set Brake Event at Brake Pin Low or High-to-Low\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to set detect brake event when external brake pin at low level or transfer from high to low.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer) ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk)\r
+\r
+/**\r
+ * @brief Set External Brake Pin Source\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] pin The external brake pin source, could be one of following source\r
+ * - \ref TPWM_TM_BRAKE0\r
+ * - \ref TPWM_TM_BRAKE1\r
+ * - \ref TPWM_TM_BRAKE2\r
+ * - \ref TPWM_TM_BRAKE3\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high.\r
+ * \hideinitializer\r
+ */\r
+#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin) ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)<<TIMER_PWMBNF_BKPINSRC_Pos))\r
+\r
+\r
+void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc);\r
+uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle);\r
+void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount);\r
+void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount);\r
+void TPWM_DisableDeadTime(TIMER_T *timer);\r
+void TPWM_EnableCounter(TIMER_T *timer);\r
+void TPWM_DisableCounter(TIMER_T *timer);\r
+void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition);\r
+void TPWM_DisableTriggerADC(TIMER_T *timer);\r
+void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource);\r
+void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource);\r
+void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource);\r
+uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource);\r
+void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource);\r
+void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode);\r
+void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel);\r
+void TPWM_DisableBrakePinDebounce(TIMER_T *timer);\r
+void TPWM_EnableBrakePinInverse(TIMER_T *timer);\r
+void TPWM_DisableBrakePinInverse(TIMER_T *timer);\r
+void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum);\r
+\r
+/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group TIMER_PWM_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __TIMER_PWM_H__ */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file UART.h\r
+ * @version V3.00\r
+ * @brief M2351 series UART Interface Controller (UART) driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup UART_Driver UART Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup UART_EXPORTED_CONSTANTS UART Exported Constants\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* UART FIFO size constants definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UART0_FIFO_SIZE 16UL /*!< UART0 supports separated receive/transmit 16/16 bytes entry FIFO */\r
+#define UART1_FIFO_SIZE 16UL /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO */\r
+#define UART2_FIFO_SIZE 16UL /*!< UART2 supports separated receive/transmit 16/16 bytes entry FIFO */\r
+#define UART3_FIFO_SIZE 16UL /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO */\r
+#define UART4_FIFO_SIZE 16UL /*!< UART4 supports separated receive/transmit 16/16 bytes entry FIFO */\r
+#define UART5_FIFO_SIZE 16UL /*!< UART5 supports separated receive/transmit 16/16 bytes entry FIFO */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* UART_FIFO constants definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UART_FIFO_RFITL_1BYTE (0x0UL << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte */\r
+#define UART_FIFO_RFITL_4BYTES (0x1UL << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes */\r
+#define UART_FIFO_RFITL_8BYTES (0x2UL << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes */\r
+#define UART_FIFO_RFITL_14BYTES (0x3UL << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes */\r
+\r
+#define UART_FIFO_RTSTRGLV_1BYTE (0x0UL << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte */\r
+#define UART_FIFO_RTSTRGLV_4BYTES (0x1UL << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes */\r
+#define UART_FIFO_RTSTRGLV_8BYTES (0x2UL << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes */\r
+#define UART_FIFO_RTSTRGLV_14BYTES (0x3UL << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* UART_LINE constants definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UART_WORD_LEN_5 (0UL) /*!< UART_LINE setting to set UART word length to 5 bits */\r
+#define UART_WORD_LEN_6 (1UL) /*!< UART_LINE setting to set UART word length to 6 bits */\r
+#define UART_WORD_LEN_7 (2UL) /*!< UART_LINE setting to set UART word length to 7 bits */\r
+#define UART_WORD_LEN_8 (3UL) /*!< UART_LINE setting to set UART word length to 8 bits */\r
+\r
+#define UART_PARITY_NONE (0x0UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity */\r
+#define UART_PARITY_ODD (0x1UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity */\r
+#define UART_PARITY_EVEN (0x3UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity */\r
+#define UART_PARITY_MARK (0x5UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' */\r
+#define UART_PARITY_SPACE (0x7UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' */\r
+\r
+#define UART_STOP_BIT_1 (0x0UL << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit */\r
+#define UART_STOP_BIT_1_5 (0x1UL << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length */\r
+#define UART_STOP_BIT_2 (0x1UL << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* UART RTS ACTIVE LEVEL constants definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UART_RTS_IS_LOW_LEV_ACTIVE (0x1UL << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Active */\r
+#define UART_RTS_IS_HIGH_LEV_ACTIVE (0x0UL << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Active */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* UART_IRDA constants definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UART_IRDA_TXEN (0x1UL << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Tx mode */\r
+#define UART_IRDA_RXEN (0x0UL << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Rx mode */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* UART_FUNCSEL constants definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UART_FUNCSEL_UART (0x0UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) */\r
+#define UART_FUNCSEL_LIN (0x1UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function */\r
+#define UART_FUNCSEL_IrDA (0x2UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function */\r
+#define UART_FUNCSEL_RS485 (0x3UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* UART_LINCTL constants definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UART_LINCTL_BRKFL(x) (((x)-1UL) << UART_LINCTL_BRKFL_Pos) /*!< UART_LINCTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 */\r
+#define UART_LINCTL_BSL(x) (((x)-1UL) << UART_LINCTL_BSL_Pos) /*!< UART_LINCTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 */\r
+#define UART_LINCTL_HSEL_BREAK (0x0UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field */\r
+#define UART_LINCTL_HSEL_BREAK_SYNC (0x1UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field and sync field */\r
+#define UART_LINCTL_HSEL_BREAK_SYNC_ID (0x2UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field, sync field and ID field*/\r
+#define UART_LINCTL_PID(x) ((x) << UART_LINCTL_PID_Pos) /*!< UART_LINCTL setting to set LIN PID value */\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* UART BAUDRATE MODE constants definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UART_BAUD_MODE0 (0UL) /*!< Set UART Baudrate Mode is Mode0 */\r
+#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 */\r
+\r
+\r
+\r
+/*@}*/ /* end of group UART_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions\r
+ @{\r
+*/\r
+\r
+\r
+/**\r
+ * @brief Calculate UART baudrate mode0 divider\r
+ *\r
+ * @param[in] u32SrcFreq UART clock frequency\r
+ * @param[in] u32BaudRate Baudrate of UART module\r
+ *\r
+ * @return UART baudrate mode0 divider\r
+ *\r
+ * @details This macro calculate UART baudrate mode0 divider.\r
+ */\r
+#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)*8ul)) / (u32BaudRate) >> 4ul)-2ul)\r
+\r
+\r
+/**\r
+ * @brief Calculate UART baudrate mode2 divider\r
+ *\r
+ * @param[in] u32SrcFreq UART clock frequency\r
+ * @param[in] u32BaudRate Baudrate of UART module\r
+ *\r
+ * @return UART baudrate mode2 divider\r
+ *\r
+ * @details This macro calculate UART baudrate mode2 divider.\r
+ */\r
+#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul)\r
+\r
+\r
+/**\r
+ * @brief Write UART data\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ * @param[in] u8Data Data byte to transmit.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro write Data to Tx data register.\r
+ */\r
+#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data))\r
+\r
+\r
+/**\r
+ * @brief Read UART data\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @return The oldest data byte in RX FIFO.\r
+ *\r
+ * @details This macro read Rx data register.\r
+ */\r
+#define UART_READ(uart) ((uart)->DAT)\r
+\r
+\r
+/**\r
+ * @brief Get Tx empty\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @retval 0 Tx FIFO is not empty\r
+ * @retval >=1 Tx FIFO is empty\r
+ *\r
+ * @details This macro get Transmitter FIFO empty register value.\r
+ */\r
+#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)\r
+\r
+\r
+/**\r
+ * @brief Get Rx empty\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @retval 0 Rx FIFO is not empty\r
+ * @retval >=1 Rx FIFO is empty\r
+ *\r
+ * @details This macro get Receiver FIFO empty register value.\r
+ */\r
+#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)\r
+\r
+\r
+/**\r
+ * @brief Check specified uart port transmission is over.\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @retval 0 Tx transmission is not over\r
+ * @retval 1 Tx transmission is over\r
+ *\r
+ * @details This macro return Transmitter Empty Flag register bit value.\r
+ * It indicates if specified uart port transmission is over nor not.\r
+ */\r
+#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)\r
+\r
+\r
+/**\r
+ * @brief Wait specified uart port transmission is over\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro wait specified uart port transmission is over.\r
+ */\r
+#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))\r
+\r
+\r
+/**\r
+ * @brief Check RX is ready or not\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @retval 0 The number of bytes in the RX FIFO is less than the RFITL\r
+ * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL\r
+ *\r
+ * @details This macro check receive data available interrupt flag is set or not.\r
+ */\r
+#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)\r
+\r
+\r
+/**\r
+ * @brief Check TX FIFO is full or not\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @retval 1 TX FIFO is full\r
+ * @retval 0 TX FIFO is not full\r
+ *\r
+ * @details This macro check TX FIFO is full or not.\r
+ */\r
+#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)\r
+\r
+\r
+/**\r
+ * @brief Check RX FIFO is full or not\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @retval 1 RX FIFO is full\r
+ * @retval 0 RX FIFO is not full\r
+ *\r
+ * @details This macro check RX FIFO is full or not.\r
+ */\r
+#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)\r
+\r
+\r
+/**\r
+ * @brief Get Tx full register value\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @retval 0 Tx FIFO is not full.\r
+ * @retval >=1 Tx FIFO is full.\r
+ *\r
+ * @details This macro get Tx full register value.\r
+ */\r
+#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)\r
+\r
+\r
+/**\r
+ * @brief Get Rx full register value\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @retval 0 Rx FIFO is not full.\r
+ * @retval >=1 Rx FIFO is full.\r
+ *\r
+ * @details This macro get Rx full register value.\r
+ */\r
+#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)\r
+\r
+\r
+/**\r
+ * @brief Enable specified UART interrupt\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ * @param[in] u32eIntSel Interrupt type select\r
+ * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter empty interrupt\r
+ * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt\r
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt\r
+ * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt\r
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt\r
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt\r
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt\r
+ * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt\r
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt\r
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro enable specified UART interrupt.\r
+ */\r
+#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel))\r
+\r
+\r
+/**\r
+ * @brief Disable specified UART interrupt\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ * @param[in] u32eIntSel Interrupt type select\r
+ * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt\r
+ * - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt\r
+ * - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt\r
+ * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt\r
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt\r
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt\r
+ * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt\r
+ * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt\r
+ * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt\r
+ * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro enable specified UART interrupt.\r
+ */\r
+#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel))\r
+\r
+\r
+/**\r
+ * @brief Get specified interrupt flag/status\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be\r
+ * - \ref UART_INTSTS_HWBUFEINT_Msk : PDMA Mode Buffer Error Interrupt Indicator\r
+ * - \ref UART_INTSTS_HWTOINT_Msk : PDMA Mode Rx Time-out Interrupt Indicator\r
+ * - \ref UART_INTSTS_HWMODINT_Msk : PDMA Mode MODEM Status Interrupt Indicator\r
+ * - \ref UART_INTSTS_HWRLSINT_Msk : PDMA Mode Receive Line Status Interrupt Indicator\r
+ * - \ref UART_INTSTS_HWBUFEIF_Msk : PDMA Mode Buffer Error Interrupt Flag\r
+ * - \ref UART_INTSTS_HWTOIF_Msk : PDMA Mode Time-out Interrupt Flag\r
+ * - \ref UART_INTSTS_HWMODIF_Msk : PDMA Mode MODEM Status Interrupt Flag\r
+ * - \ref UART_INTSTS_HWRLSIF_Msk : PDMA Mode Receive Line Status Flag\r
+ * - \ref UART_INTSTS_ABRINT_Msk : Auto-baud Rate Interrupt Indicator\r
+ * - \ref UART_INTSTS_TXENDINT_Msk : Transmitter Empty Interrupt Indicator\r
+ * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator\r
+ * - \ref UART_INTSTS_WKINT_Msk : Wake-up Interrupt Indicator\r
+ * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator\r
+ * - \ref UART_INTSTS_RXTOINT_Msk : Rx Time-out Interrupt Indicator\r
+ * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator\r
+ * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator\r
+ * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator\r
+ * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator\r
+ * - \ref UART_INTSTS_TXENDIF_Msk : Transmitter Empty Interrupt Flag\r
+ * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Interrupt Flag\r
+ * - \ref UART_INTSTS_WKIF_Msk : Wake-up Interrupt Flag\r
+ * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag\r
+ * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag\r
+ * - \ref UART_INTSTS_MODEMIF_Msk : MODEM Status Interrupt Flag\r
+ * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag\r
+ * - \ref UART_INTSTS_THREIF_Msk : Transmit Holding Register Empty Interrupt Flag\r
+ * - \ref UART_INTSTS_RDAIF_Msk : Receive Data Available Interrupt Flag\r
+ *\r
+ * @retval 0 The specified interrupt is not happened.\r
+ * 1 The specified interrupt is happened.\r
+ *\r
+ * @details This macro get specified interrupt flag or interrupt indicator status.\r
+ */\r
+#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0)\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* static inline functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */\r
+static __INLINE void UART_CLEAR_RTS(UART_T* uart);\r
+static __INLINE void UART_SET_RTS(UART_T* uart);\r
+\r
+\r
+/**\r
+ * @brief Set RTS pin to low\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro set RTS pin to low.\r
+ */\r
+__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart)\r
+{\r
+ uart->MODEM |= UART_MODEM_RTSACTLV_Msk;\r
+ uart->MODEM &= ~UART_MODEM_RTS_Msk;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set RTS pin to high\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro set RTS pin to high.\r
+ */\r
+__STATIC_INLINE void UART_SET_RTS(UART_T* uart)\r
+{\r
+ uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Clear RS-485 Address Byte Detection Flag\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro clear RS-485 address byte detection flag.\r
+ */\r
+#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk)\r
+\r
+\r
+/**\r
+ * @brief Get RS-485 Address Byte Detection Flag\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module\r
+ *\r
+ * @retval 0 Receiver detects a data that is not an address bit.\r
+ * @retval 1 Receiver detects a data that is an address bit.\r
+ *\r
+ * @details This macro get RS-485 address byte detection flag.\r
+ */\r
+#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)\r
+\r
+\r
+\r
+void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag);\r
+void UART_Close(UART_T* uart);\r
+void UART_DisableFlowCtrl(UART_T* uart);\r
+void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag);\r
+void UART_EnableFlowCtrl(UART_T* uart);\r
+void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag);\r
+void UART_Open(UART_T* uart, uint32_t u32baudrate);\r
+uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);\r
+void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);\r
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);\r
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);\r
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);\r
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength);\r
+uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);\r
+\r
+\r
+/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group UART_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __UART_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/******************************************************************************\r
+ * @file usbd.h\r
+ * @version V3.00\r
+ * @brief M2351 series USBD driver header file\r
+ *\r
+ * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.\r
+ ******************************************************************************/\r
+#ifndef __USBD_H__\r
+#define __USBD_H__\r
+\r
+//#define SUPPORT_LPM // define to support LPM\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USBD_Driver USBD Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USBD_EXPORTED_STRUCTS USBD Exported Structs\r
+ @{\r
+*/\r
+typedef struct s_usbd_info\r
+{\r
+ uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */\r
+ uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */\r
+ uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */\r
+ uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */\r
+ uint8_t *gu8BosDesc; /*!< Pointer for USB BOS Descriptor */\r
+ uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */\r
+ uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */\r
+\r
+} S_USBD_INFO_T; /*!< Device description structure */\r
+\r
+extern const S_USBD_INFO_T gsInfo;\r
+\r
+/*@}*/ /* end of group USBD_EXPORTED_STRUCTS */\r
+\r
+\r
+\r
+\r
+/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants\r
+ @{\r
+*/\r
+#define USBD_BUF_BASE (uint32_t)(((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_BASE+NS_OFFSET+0x100UL):(USBD_BASE+0x100UL)) /*!< USBD buffer base address */\r
+#define USBD_MAX_EP 12UL /*!< Total EP number */\r
+\r
+#define EP0 0UL /*!< Endpoint 0 */\r
+#define EP1 1UL /*!< Endpoint 1 */\r
+#define EP2 2UL /*!< Endpoint 2 */\r
+#define EP3 3UL /*!< Endpoint 3 */\r
+#define EP4 4UL /*!< Endpoint 4 */\r
+#define EP5 5UL /*!< Endpoint 5 */\r
+#define EP6 6UL /*!< Endpoint 6 */\r
+#define EP7 7UL /*!< Endpoint 7 */\r
+#define EP8 8UL /*!< Endpoint 8 */\r
+#define EP9 9UL /*!< Endpoint 9 */\r
+#define EP10 10UL /*!< Endpoint 10 */\r
+#define EP11 11UL /*!< Endpoint 11 */\r
+\r
+/** @cond HIDDEN_SYMBOLS */\r
+/* USB Request Type */\r
+#define REQ_STANDARD 0x00UL\r
+#define REQ_CLASS 0x20UL\r
+#define REQ_VENDOR 0x40UL\r
+\r
+/* USB Standard Request */\r
+#define GET_STATUS 0x00UL\r
+#define CLEAR_FEATURE 0x01UL\r
+#define SET_FEATURE 0x03UL\r
+#define SET_ADDRESS 0x05UL\r
+#define GET_DESCRIPTOR 0x06UL\r
+#define SET_DESCRIPTOR 0x07UL\r
+#define GET_CONFIGURATION 0x08UL\r
+#define SET_CONFIGURATION 0x09UL\r
+#define GET_INTERFACE 0x0AUL\r
+#define SET_INTERFACE 0x0BUL\r
+#define SYNC_FRAME 0x0CUL\r
+\r
+/* USB Descriptor Type */\r
+#define DESC_DEVICE 0x01UL\r
+#define DESC_CONFIG 0x02UL\r
+#define DESC_STRING 0x03UL\r
+#define DESC_INTERFACE 0x04UL\r
+#define DESC_ENDPOINT 0x05UL\r
+#define DESC_QUALIFIER 0x06UL\r
+#define DESC_OTHERSPEED 0x07UL\r
+#define DESC_IFPOWER 0x08UL\r
+#define DESC_OTG 0x09UL\r
+#define DESC_BOS 0x0FUL\r
+#define DESC_CAPABILITY 0x10UL\r
+\r
+/* USB Device Capability Type */\r
+#define CAP_WIRELESS 0x01UL\r
+#define CAP_USB20_EXT 0x02UL\r
+\r
+/*!<USB HID Descriptor Type */\r
+#define DESC_HID 0x21UL\r
+#define DESC_HID_RPT 0x22UL\r
+\r
+/* USB Descriptor Length */\r
+#define LEN_DEVICE 18UL\r
+#define LEN_QUALIFIER 10UL\r
+#define LEN_CONFIG 9UL\r
+#define LEN_INTERFACE 9UL\r
+#define LEN_ENDPOINT 7UL\r
+#define LEN_OTG 5UL\r
+#define LEN_BOS 5UL\r
+#define LEN_HID 9UL\r
+#define LEN_CCID 0x36UL\r
+#define LEN_BOSCAP 7UL\r
+\r
+/* USB Endpoint Type */\r
+#define EP_ISO 0x01\r
+#define EP_BULK 0x02\r
+#define EP_INT 0x03\r
+\r
+#define EP_INPUT 0x80\r
+#define EP_OUTPUT 0x00\r
+\r
+/* USB Feature Selector */\r
+#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01UL\r
+#define FEATURE_ENDPOINT_HALT 0x00UL\r
+/** @endcond HIDDEN_SYMBOLS */\r
+\r
+/******************************************************************************/\r
+/* USB Specific Macros */\r
+/******************************************************************************/\r
+\r
+#define USBD_WAKEUP_EN USBD_INTEN_WKEN_Msk /*!< USB Wake-up Enable */\r
+#define USBD_DRVSE0 USBD_SE0_SE0_Msk /*!< Drive SE0 */\r
+\r
+#define USBD_LPMACK USBD_ATTR_LPMACK_Msk /*!< LPM Enable */\r
+#define USBD_BYTEM USBD_ATTR_BYTEM_Msk /*!< Access Size Mode Selection */\r
+#define USBD_DPPU_EN USBD_ATTR_DPPUEN_Msk /*!< USB D+ Pull-up Enable */\r
+#define USBD_USB_EN USBD_ATTR_USBEN_Msk /*!< USB Enable */\r
+#define USBD_RWAKEUP USBD_ATTR_RWAKEUP_Msk /*!< Remote Wake-Up */\r
+#define USBD_PHY_EN USBD_ATTR_PHYEN_Msk /*!< PHY Enable */\r
+\r
+#define USBD_INT_BUS USBD_INTEN_BUSIEN_Msk /*!< USB Bus Event Interrupt */\r
+#define USBD_INT_USB USBD_INTEN_USBIEN_Msk /*!< USB Event Interrupt */\r
+#define USBD_INT_FLDET USBD_INTEN_VBDETIEN_Msk /*!< USB VBUS Detection Interrupt */\r
+#define USBD_INT_WAKEUP (USBD_INTEN_NEVWKIEN_Msk | USBD_INTEN_WKEN_Msk) /*!< USB No-Event-Wake-Up Interrupt */\r
+\r
+#define USBD_INTSTS_WAKEUP USBD_INTSTS_NEVWKIF_Msk /*!< USB No-Event-Wake-Up Interrupt Status */\r
+#define USBD_INTSTS_FLDET USBD_INTSTS_VBDETIF_Msk /*!< USB Float Detect Interrupt Status */\r
+#define USBD_INTSTS_BUS USBD_INTSTS_BUSIF_Msk /*!< USB Bus Event Interrupt Status */\r
+#define USBD_INTSTS_USB USBD_INTSTS_USBIF_Msk /*!< USB Event Interrupt Status */\r
+#define USBD_INTSTS_SETUP USBD_INTSTS_SETUP_Msk /*!< USB Setup Event */\r
+#define USBD_INTSTS_EP0 USBD_INTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event */\r
+#define USBD_INTSTS_EP1 USBD_INTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event */\r
+#define USBD_INTSTS_EP2 USBD_INTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event */\r
+#define USBD_INTSTS_EP3 USBD_INTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event */\r
+#define USBD_INTSTS_EP4 USBD_INTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event */\r
+#define USBD_INTSTS_EP5 USBD_INTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event */\r
+#define USBD_INTSTS_EP6 USBD_INTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event */\r
+#define USBD_INTSTS_EP7 USBD_INTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event */\r
+#define USBD_INTSTS_EP8 USBD_INTSTS_EPEVT8_Msk /*!< USB Endpoint 8 Event */\r
+#define USBD_INTSTS_EP9 USBD_INTSTS_EPEVT9_Msk /*!< USB Endpoint 9 Event */\r
+#define USBD_INTSTS_EP10 USBD_INTSTS_EPEVT10_Msk /*!< USB Endpoint 10 Event */\r
+#define USBD_INTSTS_EP11 USBD_INTSTS_EPEVT11_Msk /*!< USB Endpoint 11 Event */\r
+\r
+#define USBD_STATE_USBRST USBD_ATTR_USBRST_Msk /*!< USB Bus Reset */\r
+#define USBD_STATE_SUSPEND USBD_ATTR_SUSPEND_Msk /*!< USB Bus Suspend */\r
+#define USBD_STATE_RESUME USBD_ATTR_RESUME_Msk /*!< USB Bus Resume */\r
+#define USBD_STATE_TIMEOUT USBD_ATTR_TOUT_Msk /*!< USB Bus Timeout */\r
+#define USBD_STATE_L1SUSPEND USBD_ATTR_L1SUSPEND_Msk /*!< USB Bus L1SUSPEND */\r
+#define USBD_STATE_L1RESUME USBD_ATTR_L1RESUME_Msk /*!< USB Bus L1RESUME */\r
+\r
+#define USBD_CFGP_SSTALL USBD_CFGP_SSTALL_Msk /*!< Set Stall */\r
+#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall */\r
+\r
+#define USBD_CFG_EPMODE_DISABLE (0UL << USBD_CFG_STATE_Pos)/*!< Endpoint Disable */\r
+#define USBD_CFG_EPMODE_OUT (1UL << USBD_CFG_STATE_Pos)/*!< Out Endpoint */\r
+#define USBD_CFG_EPMODE_IN (2UL << USBD_CFG_STATE_Pos)/*!< In Endpoint */\r
+#define USBD_CFG_TYPE_ISO (1UL << USBD_CFG_ISOCH_Pos)/*!< Isochronous */\r
+\r
+\r
+/*@}*/ /* end of group USBD_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Compare two input numbers and return maximum one.\r
+ *\r
+ * @param[in] a First number to be compared.\r
+ * @param[in] b Second number to be compared.\r
+ *\r
+ * @return Maximum value between a and b.\r
+ *\r
+ * @details If a > b, then return a. Otherwise, return b.\r
+ */\r
+#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b))\r
+\r
+\r
+/**\r
+ * @brief Compare two input numbers and return minimum one\r
+ *\r
+ * @param[in] a First number to be compared\r
+ * @param[in] b Second number to be compared\r
+ *\r
+ * @return Minimum value between a and b\r
+ *\r
+ * @details If a < b, then return a. Otherwise, return b.\r
+ */\r
+#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b))\r
+\r
+\r
+/**\r
+ * @brief Enable USB\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To set USB ATTR control register to enable USB and PHY.\r
+ *\r
+ */\r
+#define USBD_ENABLE_USB() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR |= 0x7D0)):((uint32_t)(USBD->ATTR |= 0x7D0)))\r
+\r
+/**\r
+ * @brief Disable USB\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To set USB ATTR control register to disable USB.\r
+ *\r
+ */\r
+#define USBD_DISABLE_USB() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR &= ~USBD_USB_EN)):((uint32_t)(USBD->ATTR &= ~USBD_USB_EN)))\r
+\r
+/**\r
+ * @brief Enable USB PHY\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To set USB ATTR control register to enable USB PHY.\r
+ *\r
+ */\r
+#define USBD_ENABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR |= USBD_PHY_EN)):((uint32_t)(USBD->ATTR |= USBD_PHY_EN)))\r
+\r
+/**\r
+ * @brief Disable USB PHY\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To set USB ATTR control register to disable USB PHY.\r
+ *\r
+ */\r
+#define USBD_DISABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR &= ~USBD_PHY_EN)):((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN)))\r
+\r
+/**\r
+ * @brief Enable SE0. Force USB PHY transceiver to drive SE0.\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus.\r
+ *\r
+ */\r
+#define USBD_SET_SE0() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->SE0 |= USBD_DRVSE0)):((uint32_t)(USBD->SE0 |= USBD_DRVSE0)))\r
+\r
+/**\r
+ * @brief Disable SE0\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function.\r
+ *\r
+ */\r
+#define USBD_CLR_SE0() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->SE0 &= ~USBD_DRVSE0)):((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0)))\r
+\r
+/**\r
+ * @brief Set USB device address\r
+ *\r
+ * @param[in] addr The USB device address.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Write USB device address to USB_FADDR register.\r
+ *\r
+ */\r
+#define USBD_SET_ADDR(addr) (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->FADDR = (addr)):(USBD->FADDR = (addr)))\r
+\r
+/**\r
+ * @brief Get USB device address\r
+ *\r
+ * @param None\r
+ *\r
+ * @return USB device address\r
+ *\r
+ * @details Read USB_FADDR register to get USB device address.\r
+ *\r
+ */\r
+#define USBD_GET_ADDR() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->FADDR)):((uint32_t)(USBD->FADDR)))\r
+\r
+/**\r
+ * @brief Enable USB interrupt function\r
+ *\r
+ * @param[in] intr The combination of the specified interrupt enable bits.\r
+ * Each bit corresponds to a interrupt enable bit.\r
+ * This parameter decides which interrupts will be enabled.\r
+ * (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS)\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Enable USB related interrupt functions specified by intr parameter.\r
+ *\r
+ */\r
+#define USBD_ENABLE_INT(intr) (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->INTEN |= (intr)):(USBD->INTEN |= (intr)))\r
+\r
+/**\r
+ * @brief Get interrupt status\r
+ *\r
+ * @param None\r
+ *\r
+ * @return The value of USB_INTSTS register\r
+ *\r
+ * @details Return all interrupt flags of USB_INTSTS register.\r
+ *\r
+ */\r
+#define USBD_GET_INT_FLAG() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->INTSTS)):((uint32_t)(USBD->INTSTS)))\r
+\r
+/**\r
+ * @brief Clear USB interrupt flag\r
+ *\r
+ * @param[in] flag The combination of the specified interrupt flags.\r
+ * Each bit corresponds to a interrupt source.\r
+ * This parameter decides which interrupt flags will be cleared.\r
+ * (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB)\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Clear USB related interrupt flags specified by flag parameter.\r
+ *\r
+ */\r
+#define USBD_CLR_INT_FLAG(flag) (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->INTSTS = (flag)):(USBD->INTSTS = (flag)))\r
+\r
+/**\r
+ * @brief Get endpoint status\r
+ *\r
+ * @param None\r
+ *\r
+ * @return The value of USB_EPSTS register.\r
+ *\r
+ * @details Return all endpoint status.\r
+ *\r
+ */\r
+#define USBD_GET_EP_FLAG() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->EPSTS)):((uint32_t)(USBD->EPSTS)))\r
+\r
+/**\r
+ * @brief Get USB bus state\r
+ *\r
+ * @param None\r
+ *\r
+ * @return The value of USB_ATTR[13:12] and USB_ATTR[3:0].\r
+ * Bit 0 indicates USB bus reset status.\r
+ * Bit 1 indicates USB bus suspend status.\r
+ * Bit 2 indicates USB bus resume status.\r
+ * Bit 3 indicates USB bus time-out status.\r
+ * Bit 12 indicates USB bus LPM L1 suspend status.\r
+ * Bit 13 indicates USB bus LPM L1 resume status.\r
+ *\r
+ * @details Return USB_ATTR[13:12] and USB_ATTR[3:0] for USB bus events.\r
+ *\r
+ */\r
+#define USBD_GET_BUS_STATE() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR & 0x300F)):((uint32_t)(USBD->ATTR & 0x300F)))\r
+\r
+/**\r
+ * @brief Check cable connection state\r
+ *\r
+ * @param None\r
+ *\r
+ * @retval 0 USB cable is not attached.\r
+ * @retval 1 USB cable is attached.\r
+ *\r
+ * @details Check the connection state by FLDET bit of USB_FLDET register.\r
+ *\r
+ */\r
+#define USBD_IS_ATTACHED() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)):((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)))\r
+\r
+/**\r
+ * @brief Stop USB transaction of the specified endpoint ID\r
+ *\r
+ * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID.\r
+ *\r
+ */\r
+#define USBD_STOP_TRANSACTION(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk))\r
+\r
+/**\r
+ * @brief Set USB DATA1 PID for the specified endpoint ID\r
+ *\r
+ * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction.\r
+ * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.\r
+ *\r
+ */\r
+#define USBD_SET_DATA1(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk))\r
+\r
+/**\r
+ * @brief Set USB DATA0 PID for the specified endpoint ID\r
+ *\r
+ * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction.\r
+ * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.\r
+ *\r
+ */\r
+#define USBD_SET_DATA0(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk)))\r
+\r
+/**\r
+ * @brief Set USB payload size (IN data)\r
+ *\r
+ * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.\r
+ *\r
+ * @param[in] size The transfer length.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction.\r
+ *\r
+ */\r
+#define USBD_SET_PAYLOAD_LEN(ep, size) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)))\r
+\r
+/**\r
+ * @brief Get USB payload size (OUT data)\r
+ *\r
+ * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.\r
+ *\r
+ * @return The value of USB_MXPLDx register.\r
+ *\r
+ * @details Get the data length of OUT data transaction by reading USB_MXPLDx register.\r
+ *\r
+ */\r
+#define USBD_GET_PAYLOAD_LEN(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].MXPLD + (uint32_t)((ep) << 4)))):((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4)))))\r
+\r
+/**\r
+ * @brief Configure endpoint\r
+ *\r
+ * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.\r
+ *\r
+ * @param[in] config The USB configuration.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro will write config parameter to USB_CFGx register of specified endpoint ID.\r
+ *\r
+ */\r
+#define USBD_CONFIG_EP(ep, config) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)))\r
+\r
+/**\r
+ * @brief Set USB endpoint buffer\r
+ *\r
+ * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.\r
+ *\r
+ * @param[in] offset The SRAM offset.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro will set the SRAM offset for the specified endpoint ID.\r
+ *\r
+ */\r
+#define USBD_SET_EP_BUF_ADDR(ep, offset) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)))\r
+\r
+/**\r
+ * @brief Get the offset of the specified USB endpoint buffer\r
+ *\r
+ * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.\r
+ *\r
+ * @return The offset of the specified endpoint buffer.\r
+ *\r
+ * @details This macro will return the SRAM offset of the specified endpoint ID.\r
+ *\r
+ */\r
+#define USBD_GET_EP_BUF_ADDR(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].BUFSEG + (uint32_t)((ep) << 4)))):((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4)))))\r
+\r
+/**\r
+ * @brief Set USB endpoint stall state\r
+ *\r
+ * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.\r
+ *\r
+ */\r
+#define USBD_SET_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk))\r
+\r
+/**\r
+ * @brief Clear USB endpoint stall state\r
+ *\r
+ * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.\r
+ */\r
+#define USBD_CLR_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk))\r
+\r
+/**\r
+ * @brief Get USB endpoint stall state\r
+ *\r
+ * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.\r
+ *\r
+ * @retval 0 USB endpoint is not stalled.\r
+ * @retval Others USB endpoint is stalled.\r
+ *\r
+ * @details Get USB endpoint stall state of the specified endpoint ID.\r
+ *\r
+ */\r
+#define USBD_GET_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk))\r
+\r
+/**\r
+ * @brief To support byte access between USB SRAM and system SRAM\r
+ *\r
+ * @param[in] dest Destination pointer.\r
+ *\r
+ * @param[in] src Source pointer.\r
+ *\r
+ * @param[in] size Byte count.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter.\r
+ *\r
+ */\r
+__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size)\r
+{\r
+ uint32_t volatile i = 0UL;\r
+\r
+ while(size--)\r
+ {\r
+ dest[i] = src[i];\r
+ i++;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set USB endpoint stall state\r
+ *\r
+ * @param[in] epnum USB endpoint number\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically.\r
+ *\r
+ */\r
+__STATIC_INLINE void USBD_SetStall(uint8_t epnum)\r
+{\r
+ uint32_t u32CfgAddr;\r
+ uint32_t u32Cfg;\r
+ uint32_t i;\r
+ USBD_T *pUSBD;\r
+\r
+ if((__PC() & NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pUSBD = USBD_NS;\r
+ }\r
+ else\r
+ {\r
+ pUSBD = USBD;\r
+ }\r
+\r
+ for(i = 0UL; i < USBD_MAX_EP; i++)\r
+ {\r
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */\r
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));\r
+\r
+ if((u32Cfg & 0xFUL) == epnum)\r
+ {\r
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */\r
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));\r
+\r
+ *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL);\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Clear USB endpoint stall state\r
+ *\r
+ * @param[in] epnum USB endpoint number\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token.\r
+ */\r
+__STATIC_INLINE void USBD_ClearStall(uint8_t epnum)\r
+{\r
+ uint32_t u32CfgAddr;\r
+ uint32_t u32Cfg;\r
+ uint32_t i;\r
+ USBD_T *pUSBD;\r
+\r
+ if((__PC() & NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pUSBD = USBD_NS;\r
+ }\r
+ else\r
+ {\r
+ pUSBD = USBD;\r
+ }\r
+\r
+ for(i = 0UL; i < USBD_MAX_EP; i++)\r
+ {\r
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */\r
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));\r
+\r
+ if((u32Cfg & 0xFUL) == epnum)\r
+ {\r
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */\r
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));\r
+\r
+ *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL);\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get USB endpoint stall state\r
+ *\r
+ * @param[in] epnum USB endpoint number\r
+ *\r
+ * @retval 0 USB endpoint is not stalled.\r
+ * @retval Others USB endpoint is stalled.\r
+ *\r
+ * @details Get USB endpoint stall state.\r
+ *\r
+ */\r
+__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum)\r
+{\r
+ uint32_t u32CfgAddr;\r
+ uint32_t u32Cfg;\r
+ uint32_t i;\r
+ USBD_T *pUSBD;\r
+\r
+ if((__PC() & NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pUSBD = USBD_NS;\r
+ }\r
+ else\r
+ {\r
+ pUSBD = USBD;\r
+ }\r
+\r
+ for(i = 0UL; i < USBD_MAX_EP; i++)\r
+ {\r
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */\r
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));\r
+\r
+ if((u32Cfg & 0xFUL) == epnum)\r
+ {\r
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */\r
+ break;\r
+ }\r
+ }\r
+\r
+ return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL);\r
+}\r
+\r
+extern volatile uint8_t g_USBD_u8RemoteWakeupEn;\r
+\r
+\r
+typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */\r
+typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */\r
+typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!< Functional pointer type declaration for USB set interface request callback handler */\r
+typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */\r
+\r
+\r
+/*--------------------------------------------------------------------*/\r
+void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);\r
+void USBD_Start(void);\r
+void USBD_GetSetupPacket(uint8_t *buf);\r
+void USBD_ProcessSetupPacket(void);\r
+void USBD_StandardRequest(void);\r
+void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size);\r
+void USBD_CtrlIn(void);\r
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size);\r
+void USBD_CtrlOut(void);\r
+void USBD_SwReset(void);\r
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);\r
+void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback);\r
+void USBD_LockEpStall(uint32_t u32EpBitmap);\r
+\r
+/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group USBD_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __USBD_H__ */\r
+\r
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file USCI_I2C.h\r
+ * @version V3.0\r
+ * $Revision: 1 $\r
+ * $Date: 16/07/07 7:50p $\r
+ * @brief M2351 series USCI I2C(UI2C) driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __USCI_I2C_H__\r
+#define __USCI_I2C_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USCI_I2C_Driver USCI_I2C Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* USCI_I2C master event definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+enum UI2C_MASTER_EVENT\r
+{\r
+ MASTER_SEND_ADDRESS = 10u, /*!< Master send address to Slave */\r
+ MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */\r
+ MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */\r
+ MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */\r
+ MASTER_SEND_DATA, /*!< Master Send Data to Slave */\r
+ MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */\r
+ MASTER_READ_DATA, /*!< Master Get Data from Slave */\r
+ MASTER_STOP, /*!< Master send stop to Slave */\r
+ MASTER_SEND_START /*!< Master send start to Slave */\r
+};\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* USCI_I2C slave event definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+enum UI2C_SLAVE_EVENT\r
+{\r
+ SLAVE_ADDRESS_ACK = 100u, /*!< Slave send address ACK */\r
+ SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */\r
+ SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */\r
+ SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */\r
+ SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */\r
+ SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */\r
+ SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */\r
+};\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* USCI_CTL constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UI2C_CTL_PTRG (0x20U) /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit */\r
+#define UI2C_CTL_STA (0x08U) /*!< USCI_CTL setting for I2C control bits. It would set STA bit */\r
+#define UI2C_CTL_STO (0x04U) /*!< USCI_CTL setting for I2C control bits. It would set STO bit */\r
+#define UI2C_CTL_AA (0x02U) /*!< USCI_CTL setting for I2C control bits. It would set AA bit */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* USCI_I2C GCMode constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UI2C_GCMODE_ENABLE (1U) /*!< Enable USCI_I2C GC Mode */\r
+#define UI2C_GCMODE_DISABLE (0U) /*!< Disable USCI_I2C GC Mode */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* USCI_I2C Wakeup Mode constant definitions. */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UI2C_DATA_TOGGLE_WK (0x0U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle */\r
+#define UI2C_ADDR_MATCH_WK (0x1U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* USCI_I2C interrupt mask definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UI2C_TO_INT_MASK (0x001U) /*!< Time-out interrupt mask */\r
+#define UI2C_STAR_INT_MASK (0x002U) /*!< Start condition received interrupt mask */\r
+#define UI2C_STOR_INT_MASK (0x004U) /*!< Stop condition received interrupt mask */\r
+#define UI2C_NACK_INT_MASK (0x008U) /*!< Non-acknowledge interrupt mask */\r
+#define UI2C_ARBLO_INT_MASK (0x010U) /*!< Arbitration lost interrupt mask */\r
+#define UI2C_ERR_INT_MASK (0x020U) /*!< Error interrupt mask */\r
+#define UI2C_ACK_INT_MASK (0x040U) /*!< Acknowledge interrupt mask */\r
+\r
+/*@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief This macro sets the USCI_I2C protocol control register at one time\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8Ctrl Set the register value of USCI_I2C control register.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, PTRG, ACK.\r
+ */\r
+#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2EU) | (u8Ctrl))\r
+\r
+/**\r
+ * @brief This macro only set START bit to protocol control register of USCI_I2C module.\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register.\r
+ */\r
+#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk)\r
+\r
+/**\r
+ * @brief This macro only set STOP bit to the control register of USCI_I2C module\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register.\r
+ */\r
+#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk))\r
+\r
+/**\r
+ * @brief This macro returns the data stored in data register of USCI_I2C module\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return Data\r
+ *\r
+ * @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus\r
+ */\r
+#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT)\r
+\r
+/**\r
+ * @brief This macro writes the data to data register of USCI_I2C module\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8Data The data which will be written to data register of USCI_I2C module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus\r
+ */\r
+#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data))\r
+\r
+/**\r
+ * @brief This macro returns time-out flag\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @retval 0 USCI_I2C bus time-out is not happened\r
+ * @retval 1 USCI_I2C bus time-out is happened\r
+ *\r
+ * @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared.\r
+ */\r
+#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0)\r
+\r
+/**\r
+ * @brief This macro returns wake-up flag\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @retval 0 Chip is not woken-up from power-down mode\r
+ * @retval 1 Chip is woken-up from power-down mode\r
+ *\r
+ * @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep.\r
+ */\r
+#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0)\r
+\r
+/**\r
+ * @brief This macro is used to clear USCI_I2C wake-up flag\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details If USCI_I2C wake-up flag is set, use this macro to clear it.\r
+ */\r
+#define UI2C_CLR_WAKEUP_FLAG(ui2c) ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk)\r
+\r
+/**\r
+ * @brief This macro disables the USCI_I2C 10-bit address mode\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function.\r
+ */\r
+#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk))\r
+\r
+/**\r
+ * @brief This macro enables the 10-bit address mode\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To enable USCI_I2C 10-bit address match function.\r
+ */\r
+#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk)\r
+\r
+/**\r
+ * @brief This macro gets USCI_I2C protocol interrupt flag or bus status\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return A word data of USCI_I2C_PROTSTS register\r
+ *\r
+ * @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status.\r
+ */\r
+#define UI2C_GET_PROT_STATUS(ui2c) ((ui2c)->PROTSTS)\r
+\r
+/**\r
+ * @brief This macro clears specified protocol interrupt flag\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u32IntTypeFlag Interrupt Type Flag, should be\r
+ * - \ref UI2C_PROTSTS_ACKIF_Msk\r
+ * - \ref UI2C_PROTSTS_ERRIF_Msk\r
+ * - \ref UI2C_PROTSTS_ARBLOIF_Msk\r
+ * - \ref UI2C_PROTSTS_NACKIF_Msk\r
+ * - \ref UI2C_PROTSTS_STORIF_Msk\r
+ * - \ref UI2C_PROTSTS_STARIF_Msk\r
+ * - \ref UI2C_PROTSTS_TOIF_Msk\r
+ * @return None\r
+ *\r
+ * @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag.\r
+ */\r
+#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag) ((ui2c)->PROTSTS = (u32IntTypeFlag))\r
+\r
+/**\r
+ * @brief This macro enables specified protocol interrupt\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u32IntSel Interrupt Type, should be\r
+ * - \ref UI2C_PROTIEN_ACKIEN_Msk\r
+ * - \ref UI2C_PROTIEN_ERRIEN_Msk\r
+ * - \ref UI2C_PROTIEN_ARBLOIEN_Msk\r
+ * - \ref UI2C_PROTIEN_NACKIEN_Msk\r
+ * - \ref UI2C_PROTIEN_STORIEN_Msk\r
+ * - \ref UI2C_PROTIEN_STARIEN_Msk\r
+ * - \ref UI2C_PROTIEN_TOIEN_Msk\r
+ * @return None\r
+ *\r
+ * @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function.\r
+ */\r
+#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN |= (u32IntSel))\r
+\r
+/**\r
+ * @brief This macro disables specified protocol interrupt\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u32IntSel Interrupt Type, should be\r
+ * - \ref UI2C_PROTIEN_ACKIEN_Msk\r
+ * - \ref UI2C_PROTIEN_ERRIEN_Msk\r
+ * - \ref UI2C_PROTIEN_ARBLOIEN_Msk\r
+ * - \ref UI2C_PROTIEN_NACKIEN_Msk\r
+ * - \ref UI2C_PROTIEN_STORIEN_Msk\r
+ * - \ref UI2C_PROTIEN_STARIEN_Msk\r
+ * - \ref UI2C_PROTIEN_TOIEN_Msk\r
+ * @return None\r
+ *\r
+ * @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt funtion.\r
+ */\r
+#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN &= ~ (u32IntSel))\r
+\r
+\r
+uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock);\r
+void UI2C_Close(UI2C_T *ui2c);\r
+void UI2C_ClearTimeoutFlag(UI2C_T *ui2c);\r
+void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack);\r
+void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask);\r
+void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask);\r
+uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c);\r
+uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock);\r
+uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask);\r
+void UI2C_ClearIntFlag(UI2C_T* ui2c, uint32_t u32Mask);\r
+uint32_t UI2C_GetData(UI2C_T *ui2c);\r
+void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data);\r
+void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode);\r
+void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask);\r
+void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt);\r
+void UI2C_DisableTimeout(UI2C_T *ui2c);\r
+void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode);\r
+void UI2C_DisableWakeup(UI2C_T *ui2c);\r
+uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data);\r
+uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen);\r
+uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data);\r
+uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen);\r
+uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data);\r
+uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen);\r
+uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr);\r
+uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen);\r
+uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);\r
+uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen);\r
+uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);\r
+uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen);\r
+/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group USCI_I2C_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/****************************************************************************//**\r
+ * @file usci_spi.h\r
+ * @version V3.00\r
+ * @brief M2351 series USCI_SPI driver header file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#ifndef __USCI_SPI_H__\r
+#define __USCI_SPI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USCI_SPI_Driver USCI_SPI Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants\r
+ @{\r
+*/\r
+\r
+#define USPI_MODE_0 (0x0UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge */\r
+#define USPI_MODE_1 (0x1UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge */\r
+#define USPI_MODE_2 (0x2UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge */\r
+#define USPI_MODE_3 (0x3UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge */\r
+\r
+#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave */\r
+#define USPI_MASTER (0x0UL) /*!< Set as master */\r
+\r
+#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS */\r
+#define USPI_SS_ACTIVE_HIGH (0x0UL) /*!< SS active high */\r
+#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low */\r
+\r
+/* USCI_SPI Interrupt Mask */\r
+#define USPI_SSINACT_INT_MASK (0x001UL) /*!< Slave Slave Inactive interrupt mask */\r
+#define USPI_SSACT_INT_MASK (0x002UL) /*!< Slave Slave Active interrupt mask */\r
+#define USPI_SLVTO_INT_MASK (0x004UL) /*!< Slave Mode Time-out interrupt mask */\r
+#define USPI_SLVBE_INT_MASK (0x008UL) /*!< Slave Mode Bit Count Error interrupt mask */\r
+#define USPI_TXUDR_INT_MASK (0x010UL) /*!< Slave Transmit Under Run interrupt mask */\r
+#define USPI_RXOV_INT_MASK (0x020UL) /*!< Receive Buffer Overrun interrupt mask */\r
+#define USPI_TXST_INT_MASK (0x040UL) /*!< Transmit Start interrupt mask */\r
+#define USPI_TXEND_INT_MASK (0x080UL) /*!< Transmit End interrupt mask */\r
+#define USPI_RXST_INT_MASK (0x100UL) /*!< Receive Start interrupt mask */\r
+#define USPI_RXEND_INT_MASK (0x200UL) /*!< Receive End interrupt mask */\r
+\r
+/* USCI_SPI Status Mask */\r
+#define USPI_BUSY_MASK (0x01UL) /*!< Busy status mask */\r
+#define USPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */\r
+#define USPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */\r
+#define USPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */\r
+#define USPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */\r
+#define USPI_SSLINE_STS_MASK (0x20UL) /*!< USCI_SPI_SS line status mask */\r
+\r
+/*@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Disable slave 3-wire mode.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk )\r
+\r
+/**\r
+ * @brief Enable slave 3-wire mode.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk )\r
+\r
+/**\r
+ * @brief Get the Rx buffer empty flag.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return Rx buffer flag\r
+ * @retval 0: Rx buffer is not empty\r
+ * @retval 1: Rx buffer is empty\r
+ * \hideinitializer\r
+ */\r
+#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 )\r
+\r
+/**\r
+ * @brief Get the Tx buffer empty flag.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return Tx buffer flag\r
+ * @retval 0: Tx buffer is not empty\r
+ * @retval 1: Tx buffer is empty\r
+ * \hideinitializer\r
+ */\r
+#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 )\r
+\r
+/**\r
+ * @brief Get the Tx buffer full flag.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return Tx buffer flag\r
+ * @retval 0: Tx buffer is not full\r
+ * @retval 1: Tx buffer is full\r
+ * \hideinitializer\r
+ */\r
+#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 )\r
+\r
+/**\r
+ * @brief Get the datum read from RX register.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return data in Rx register\r
+ * \hideinitializer\r
+ */\r
+#define USPI_READ_RX(uspi) ( (uspi)->RXDAT )\r
+\r
+/**\r
+ * @brief Write datum to TX register.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus.\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = (u32TxData) )\r
+\r
+/**\r
+ * @brief Set USCI_SPI_SS pin to high state.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None.\r
+ * @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode.\r
+ * \hideinitializer\r
+ */\r
+#define USPI_SET_SS_HIGH(uspi) \\r
+ do{ \\r
+ (uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \\r
+ (uspi)->PROTCTL = ((uspi)->PROTCTL & ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk)); \\r
+ }while(0)\r
+\r
+/**\r
+ * @brief Set USCI_SPI_SS pin to low state.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None.\r
+ * @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode.\r
+ * \hideinitializer\r
+ */\r
+#define USPI_SET_SS_LOW(uspi) \\r
+ do{ \\r
+ (uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \\r
+ (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \\r
+ }while(0)\r
+\r
+/**\r
+ * @brief Set the length of suspend interval.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32SuspCycle Decide the length of suspend interval.\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) )\r
+\r
+/**\r
+ * @brief Set the USCI_SPI transfer sequence with LSB first.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk )\r
+\r
+/**\r
+ * @brief Set the USCI_SPI transfer sequence with MSB first.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk )\r
+\r
+/**\r
+ * @brief Set the data width of a USCI_SPI transaction.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32Width The data width\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_SET_DATA_WIDTH(uspi, u32Width) \\r
+ do{ \\r
+ if((u32Width) == 16ul){ \\r
+ (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \\r
+ }else { \\r
+ (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \\r
+ } \\r
+ }while(0)\r
+\r
+/**\r
+ * @brief Get the USCI_SPI busy state.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return USCI_SPI busy status\r
+ * @retval 0: USCI_SPI module is not busy\r
+ * @retval 1: USCI_SPI module is busy\r
+ * \hideinitializer\r
+ */\r
+#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 )\r
+\r
+/**\r
+ * @brief Get the USCI_SPI wakeup flag.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return Wakeup status.\r
+ * @retval 0 Flag is not set.\r
+ * @retval 1 Flag is set.\r
+ * \hideinitializer\r
+ */\r
+#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0 )\r
+\r
+/**\r
+ * @brief Clear the USCI_SPI wakeup flag.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_CLR_WAKEUP_FLAG(uspi) ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk )\r
+\r
+/**\r
+ * @brief Get protocol interrupt flag/status.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return The interrupt flag/status of protocol status register.\r
+ * \hideinitializer\r
+ */\r
+#define USPI_GET_PROT_STATUS(uspi) ( (uspi)->PROTSTS )\r
+\r
+/**\r
+ * @brief Clear specified protocol interrupt flag.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32IntTypeFlag Interrupt Type Flag, should be\r
+ * - \ref USPI_PROTSTS_SSACTIF_Msk\r
+ * - \ref USPI_PROTSTS_SSINAIF_Msk\r
+ * - \ref USPI_PROTSTS_SLVBEIF_Msk\r
+ * - \ref USPI_PROTSTS_SLVTOIF_Msk\r
+ * - \ref USPI_PROTSTS_RXENDIF_Msk\r
+ * - \ref USPI_PROTSTS_RXSTIF_Msk\r
+ * - \ref USPI_PROTSTS_TXENDIF_Msk\r
+ * - \ref USPI_PROTSTS_TXSTIF_Msk\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_CLR_PROT_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->PROTSTS = (u32IntTypeFlag) )\r
+\r
+/**\r
+ * @brief Get buffer interrupt flag/status.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return The interrupt flag/status of buffer status register.\r
+ * \hideinitializer\r
+ */\r
+#define USPI_GET_BUF_STATUS(uspi) ( (uspi)->BUFSTS )\r
+\r
+/**\r
+ * @brief Clear specified buffer interrupt flag.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32IntTypeFlag Interrupt Type Flag, should be\r
+ * - \ref USPI_BUFSTS_TXUDRIF_Msk\r
+ * - \ref USPI_BUFSTS_RXOVIF_Msk\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_CLR_BUF_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->BUFSTS = (u32IntTypeFlag) )\r
+\r
+/**\r
+ * @brief Enable specified protocol interrupt.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32IntSel Interrupt Type, should be\r
+ * - \ref USPI_PROTIEN_SLVBEIEN_Msk\r
+ * - \ref USPI_PROTIEN_SLVTOIEN_Msk\r
+ * - \ref USPI_PROTIEN_SSACTIEN_Msk\r
+ * - \ref USPI_PROTIEN_SSINAIEN_Msk\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_ENABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN |= (u32IntSel) )\r
+\r
+/**\r
+ * @brief Disable specified protocol interrupt.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32IntSel Interrupt Type, should be\r
+ * - \ref USPI_PROTIEN_SLVBEIEN_Msk\r
+ * - \ref USPI_PROTIEN_SLVTOIEN_Msk\r
+ * - \ref USPI_PROTIEN_SSACTIEN_Msk\r
+ * - \ref USPI_PROTIEN_SSINAIEN_Msk\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_DISABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN &= ~ (u32IntSel) )\r
+\r
+/**\r
+ * @brief Enable specified buffer interrupt.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32IntSel Interrupt Type, should be\r
+ * - \ref USPI_BUFCTL_RXOVIEN_Msk\r
+ * - \ref USPI_BUFCTL_TXUDRIEN_Msk\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_ENABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL |= (u32IntSel) )\r
+\r
+/**\r
+ * @brief Disable specified buffer interrupt.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32IntSel Interrupt Type, should be\r
+ * - \ref USPI_BUFCTL_RXOVIEN_Msk\r
+ * - \ref USPI_BUFCTL_TXUDRIEN_Msk\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_DISABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL &= ~ (u32IntSel) )\r
+\r
+/**\r
+ * @brief Enable specified transfer interrupt.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32IntSel Interrupt Type, should be\r
+ * - \ref USPI_INTEN_RXENDIEN_Msk\r
+ * - \ref USPI_INTEN_RXSTIEN_Msk\r
+ * - \ref USPI_INTEN_TXENDIEN_Msk\r
+ * - \ref USPI_INTEN_TXSTIEN_Msk\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN |= (u32IntSel) )\r
+\r
+/**\r
+ * @brief Disable specified transfer interrupt.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32IntSel Interrupt Type, should be\r
+ * - \ref USPI_INTEN_RXENDIEN_Msk\r
+ * - \ref USPI_INTEN_RXSTIEN_Msk\r
+ * - \ref USPI_INTEN_TXENDIEN_Msk\r
+ * - \ref USPI_INTEN_TXSTIEN_Msk\r
+ * @return None\r
+ * \hideinitializer\r
+ */\r
+#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN &= ~ (u32IntSel) )\r
+\r
+/**\r
+ * @brief Trigger RX PDMA function.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None.\r
+ * @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function.\r
+ */\r
+#define USPI_TRIGGER_RX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Trigger TX PDMA function.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None.\r
+ * @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function.\r
+ */\r
+#define USPI_TRIGGER_TX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Disable RX PDMA transfer.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None.\r
+ * @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function.\r
+ */\r
+#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk )\r
+\r
+/**\r
+ * @brief Disable TX PDMA transfer.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None.\r
+ * @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function.\r
+ */\r
+#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk )\r
+\r
+uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);\r
+void USPI_Close(USPI_T *uspi);\r
+void USPI_ClearRxBuf(USPI_T *uspi);\r
+void USPI_ClearTxBuf(USPI_T *uspi);\r
+void USPI_DisableAutoSS(USPI_T *uspi);\r
+void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);\r
+uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock);\r
+uint32_t USPI_GetBusClock(USPI_T *uspi);\r
+void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask);\r
+void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask);\r
+uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask);\r
+void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask);\r
+uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask);\r
+void USPI_EnableWakeup(USPI_T *uspi);\r
+void USPI_DisableWakeup(USPI_T *uspi);\r
+\r
+\r
+/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group USCI_SPI_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __USCI_SPI_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/******************************************************************************\r
+ * @file usci_uart.h\r
+ * @version V3.00\r
+ * @brief M2351 series USCI UART (UUART) driver header file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#ifndef __USCI_UART_H__\r
+#define __USCI_UART_H__\r
+\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USCI_UART_Driver USCI_UART Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants\r
+ @{\r
+*/\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* UUART_LINECTL constants definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UUART_WORD_LEN_6 (6UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits */\r
+#define UUART_WORD_LEN_7 (7UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits */\r
+#define UUART_WORD_LEN_8 (8UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits */\r
+#define UUART_WORD_LEN_9 (9UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* UUART_PROTCTL constants definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UUART_PARITY_NONE (0x0UL << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity */\r
+#define UUART_PARITY_ODD (0x1UL << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity */\r
+#define UUART_PARITY_EVEN (0x3UL << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity */\r
+\r
+#define UUART_STOP_BIT_1 (0x0UL) /*!< UUART_PROTCTL setting for one stop bit */\r
+#define UUART_STOP_BIT_2 (0x1UL) /*!< UUART_PROTCTL setting for two stop bit */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* USCI UART interrupt mask definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define UUART_ABR_INT_MASK (0x002UL) /*!< Auto-baud rate interrupt mask */\r
+#define UUART_RLS_INT_MASK (0x004UL) /*!< Receive line status interrupt mask */\r
+#define UUART_BUF_RXOV_INT_MASK (0x008UL) /*!< Buffer RX overrun interrupt mask */\r
+#define UUART_TXST_INT_MASK (0x010UL) /*!< TX start interrupt mask */\r
+#define UUART_TXEND_INT_MASK (0x020UL) /*!< Tx end interrupt mask */\r
+#define UUART_RXST_INT_MASK (0x040UL) /*!< RX start interrupt mask */\r
+#define UUART_RXEND_INT_MASK (0x080UL) /*!< RX end interrupt mask */\r
+\r
+\r
+/*@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions\r
+ @{\r
+*/\r
+\r
+\r
+/**\r
+ * @brief Write USCI_UART data\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ * @param[in] u8Data Data byte to transmit.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro write Data to Tx data register.\r
+ */\r
+#define UUART_WRITE(uuart, u8Data) ((uuart)->TXDAT = (u8Data))\r
+\r
+\r
+/**\r
+ * @brief Read USCI_UART data\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @return The oldest data byte in RX buffer.\r
+ *\r
+ * @details This macro read Rx data register.\r
+ */\r
+#define UUART_READ(uuart) ((uuart)->RXDAT)\r
+\r
+\r
+/**\r
+ * @brief Get Tx empty\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @retval 0 Tx buffer is not empty\r
+ * @retval >=1 Tx buffer is empty\r
+ *\r
+ * @details This macro get Transmitter buffer empty register value.\r
+ */\r
+#define UUART_GET_TX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk)\r
+\r
+\r
+/**\r
+ * @brief Get Rx empty\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @retval 0 Rx buffer is not empty\r
+ * @retval >=1 Rx buffer is empty\r
+ *\r
+ * @details This macro get Receiver buffer empty register value.\r
+ */\r
+#define UUART_GET_RX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk)\r
+\r
+\r
+/**\r
+ * @brief Check specified usci_uart port transmission is over.\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @retval 0 Tx transmission is not over\r
+ * @retval 1 Tx transmission is over\r
+ *\r
+ * @details This macro return Transmitter Empty Flag register bit value. \n\r
+ * It indicates if specified usci_uart port transmission is over nor not.\r
+ */\r
+#define UUART_IS_TX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)\r
+\r
+\r
+/**\r
+ * @brief Check specified usci_uart port receiver is empty.\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @retval 0 Rx receiver is not empty\r
+ * @retval 1 Rx receiver is empty\r
+ *\r
+ * @details This macro return Receive Empty Flag register bit value. \n\r
+ * It indicates if specified usci_uart port receiver is empty nor not.\r
+ */\r
+#define UUART_IS_RX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos)\r
+\r
+\r
+/**\r
+ * @brief Wait specified usci_uart port transmission is over\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro wait specified usci_uart port transmission is over.\r
+ */\r
+#define UUART_WAIT_TX_EMPTY(uuart) while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos))\r
+\r
+\r
+/**\r
+ * @brief Check TX buffer is full or not\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @retval 1 TX buffer is full\r
+ * @retval 0 TX buffer is not full\r
+ *\r
+ * @details This macro check TX buffer is full or not.\r
+ */\r
+#define UUART_IS_TX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos)\r
+\r
+\r
+/**\r
+ * @brief Check RX buffer is full or not\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @retval 1 RX buffer is full\r
+ * @retval 0 RX buffer is not full\r
+ *\r
+ * @details This macro check RX buffer is full or not.\r
+ */\r
+#define UUART_IS_RX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos)\r
+\r
+\r
+/**\r
+ * @brief Get Tx full register value\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @retval 0 Tx buffer is not full.\r
+ * @retval >=1 Tx buffer is full.\r
+ *\r
+ * @details This macro get Tx full register value.\r
+ */\r
+#define UUART_GET_TX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)\r
+\r
+\r
+/**\r
+ * @brief Get Rx full register value\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @retval 0 Rx buffer is not full.\r
+ * @retval >=1 Rx buffer is full.\r
+ *\r
+ * @details This macro get Rx full register value.\r
+ */\r
+#define UUART_GET_RX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)\r
+\r
+\r
+/**\r
+ * @brief Enable specified USCI_UART protocol interrupt\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ * @param[in] u32IntSel Interrupt type select\r
+ * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt\r
+ * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro enable specified USCI_UART protocol interrupt.\r
+ */\r
+#define UUART_ENABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN |= (u32IntSel))\r
+\r
+\r
+/**\r
+ * @brief Disable specified USCI_UART protocol interrupt\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ * @param[in] u32IntSel Interrupt type select\r
+ * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt\r
+ * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro disable specified USCI_UART protocol interrupt.\r
+ */\r
+#define UUART_DISABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN &= ~(u32IntSel))\r
+\r
+\r
+/**\r
+ * @brief Enable specified USCI_UART buffer interrupt\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ * @param[in] u32IntSel Interrupt type select\r
+ * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro enable specified USCI_UART buffer interrupt.\r
+ */\r
+#define UUART_ENABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL |= (u32IntSel))\r
+\r
+\r
+/**\r
+ * @brief Disable specified USCI_UART buffer interrupt\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ * @param[in] u32IntSel Interrupt type select\r
+ * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro disable specified USCI_UART buffer interrupt.\r
+ */\r
+#define UUART_DISABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL &= ~ (u32IntSel))\r
+\r
+\r
+/**\r
+ * @brief Enable specified USCI_UART transfer interrupt\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ * @param[in] u32IntSel Interrupt type select\r
+ * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt\r
+ * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt\r
+ * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt\r
+ * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro enable specified USCI_UART transfer interrupt.\r
+ */\r
+#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN |= (u32IntSel))\r
+\r
+\r
+/**\r
+ * @brief Disable specified USCI_UART transfer interrupt\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ * @param[in] u32IntSel Interrupt type select\r
+ * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt\r
+ * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt\r
+ * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt\r
+ * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro disable specified USCI_UART transfer interrupt.\r
+ */\r
+#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN &= ~(u32IntSel))\r
+\r
+\r
+/**\r
+ * @brief Get protocol interrupt flag/status\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @return The interrupt flag/status of protocol status register.\r
+ *\r
+ * @details This macro get protocol status register value.\r
+ */\r
+#define UUART_GET_PROT_STATUS(uuart) ((uuart)->PROTSTS)\r
+\r
+\r
+/**\r
+ * @brief Clear specified protocol interrupt flag\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ * @param[in] u32IntTypeFlag Interrupt Type Flag, should be\r
+ * - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator\r
+ * - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag\r
+ * - \ref UUART_PROTSTS_BREAK_Msk : Break Flag\r
+ * - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag\r
+ * - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag\r
+ * - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag\r
+ * - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag\r
+ * - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag\r
+ * - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro clear specified protocol interrupt flag.\r
+ */\r
+#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->PROTSTS = (u32IntTypeFlag))\r
+\r
+\r
+/**\r
+ * @brief Get transmit/receive buffer interrupt flag/status\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @return The interrupt flag/status of buffer status register.\r
+ *\r
+ * @details This macro get buffer status register value.\r
+ */\r
+#define UUART_GET_BUF_STATUS(uuart) ((uuart)->BUFSTS)\r
+\r
+\r
+/**\r
+ * @brief Clear specified buffer interrupt flag\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ * @param[in] u32IntTypeFlag Interrupt Type Flag, should be\r
+ * - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro clear specified buffer interrupt flag.\r
+ */\r
+#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->BUFSTS = (u32IntTypeFlag))\r
+\r
+\r
+/**\r
+ * @brief Get wakeup flag\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @retval 0 Chip did not wake up from power-down mode.\r
+ * @retval 1 Chip waked up from power-down mode.\r
+ *\r
+ * @details This macro get wakeup flag.\r
+ */\r
+#define UUART_GET_WAKEUP_FLAG(uuart) ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 )\r
+\r
+\r
+/**\r
+ * @brief Clear wakeup flag\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro clear wakeup flag.\r
+ */\r
+#define UUART_CLR_WAKEUP_FLAG(uuart) ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk)\r
+\r
+\r
+void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask);\r
+uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask);\r
+void UUART_Close(UUART_T* uuart);\r
+void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask);\r
+void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask);\r
+uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate);\r
+uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);\r
+uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);\r
+uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);\r
+void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode);\r
+void UUART_DisableWakeup(UUART_T* uuart);\r
+void UUART_EnableFlowCtrl(UUART_T* uuart);\r
+void UUART_DisableFlowCtrl(UUART_T* uuart);\r
+\r
+\r
+/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group USCI_UART_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __USCI_UART_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file wdt.h\r
+ * @version V3.00\r
+ * @brief Watchdog Timer(WDT) driver header file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __WDT_H__\r
+#define __WDT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup WDT_Driver WDT Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants\r
+ @{\r
+*/\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* WDT Time-out Interval Period Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */\r
+#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */\r
+#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */\r
+#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */\r
+#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */\r
+#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */\r
+#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */\r
+#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* WDT Reset Delay Period Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */\r
+#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */\r
+#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */\r
+#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* WDT Free Reset Counter Keyword Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define WDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter \hideinitializer */\r
+\r
+/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Clear WDT Reset System Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro clears WDT time-out reset system flag.\r
+ * \hideinitializer\r
+ */\r
+#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)\r
+\r
+/**\r
+ * @brief Clear WDT Time-out Interrupt Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro clears WDT time-out interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)\r
+\r
+/**\r
+ * @brief Clear WDT Wake-up Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro clears WDT time-out wake-up system flag.\r
+ * \hideinitializer\r
+ */\r
+#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)\r
+\r
+/**\r
+ * @brief Get WDT Time-out Reset Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @retval 0 WDT time-out reset system did not occur\r
+ * @retval 1 WDT time-out reset system occurred\r
+ *\r
+ * @details This macro indicates system has been reset by WDT time-out reset or not.\r
+ * \hideinitializer\r
+ */\r
+#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL)\r
+\r
+/**\r
+ * @brief Get WDT Time-out Interrupt Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @retval 0 WDT time-out interrupt did not occur\r
+ * @retval 1 WDT time-out interrupt occurred\r
+ *\r
+ * @details This macro indicates WDT time-out interrupt occurred or not.\r
+ * \hideinitializer\r
+ */\r
+#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL)\r
+\r
+/**\r
+ * @brief Get WDT Time-out Wake-up Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @retval 0 WDT time-out interrupt does not cause CPU wake-up\r
+ * @retval 1 WDT time-out interrupt event cause CPU wake-up\r
+ *\r
+ * @details This macro indicates WDT time-out interrupt event has waked up system or not.\r
+ * \hideinitializer\r
+ */\r
+#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL)\r
+\r
+/**\r
+ * @brief Reset WDT Counter\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to reset the internal 18-bit WDT up counter value.\r
+ * @note If WDT is activated and time-out reset system function is enabled also, user should \n\r
+ * reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n\r
+ * reset system before the WDT time-out reset delay period expires.\r
+ * \hideinitializer\r
+ */\r
+#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_RESET_COUNTER_KEYWORD)\r
+\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* static inline functions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */\r
+__STATIC_INLINE void WDT_Close(void);\r
+__STATIC_INLINE void WDT_EnableInt(void);\r
+__STATIC_INLINE void WDT_DisableInt(void);\r
+\r
+/**\r
+ * @brief Stop WDT Counting\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will stop WDT counting and disable WDT module.\r
+ */\r
+__STATIC_INLINE void WDT_Close(void)\r
+{\r
+ WDT->CTL = 0UL;\r
+ while(WDT->CTL & WDT_CTL_SYNC_Msk) {} /* Wait disable WDTEN bit completed, it needs 2 * WDT_CLK. */\r
+}\r
+\r
+/**\r
+ * @brief Enable WDT Time-out Interrupt\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will enable the WDT time-out interrupt function.\r
+ */\r
+__STATIC_INLINE void WDT_EnableInt(void)\r
+{\r
+ WDT->CTL |= WDT_CTL_INTEN_Msk;\r
+ while(WDT->CTL & WDT_CTL_SYNC_Msk) {} /* Wait enable WDTEN bit completed, it needs 2 * WDT_CLK. */\r
+}\r
+\r
+/**\r
+ * @brief Disable WDT Time-out Interrupt\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will disable the WDT time-out interrupt function.\r
+ */\r
+__STATIC_INLINE void WDT_DisableInt(void)\r
+{\r
+ /* Do not touch another write 1 clear bits */\r
+ WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk);\r
+}\r
+\r
+void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);\r
+\r
+/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group WDT_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __WDT_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file wwdt.h\r
+ * @version V3.00\r
+ * @brief Window Watchdog Timer(WWDT) driver header file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __WWDT_H__\r
+#define __WWDT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup WWDT_Driver WWDT Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants\r
+ @{\r
+*/\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* WWDT Prescale Period Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */\r
+#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* WWDT Reload Counter Keyword Constant Definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */\r
+\r
+/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */\r
+\r
+\r
+/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Clear WWDT Reset System Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to clear WWDT time-out reset system flag.\r
+ * \hideinitializer\r
+ */\r
+#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)\r
+\r
+/**\r
+ * @brief Clear WWDT Compared Match Interrupt Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to clear WWDT compared match interrupt flag.\r
+ * \hideinitializer\r
+ */\r
+#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)\r
+\r
+/**\r
+ * @brief Get WWDT Reset System Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @retval 0 WWDT time-out reset system did not occur\r
+ * @retval 1 WWDT time-out reset system occurred\r
+ *\r
+ * @details This macro is used to indicate system has been reset by WWDT time-out reset or not.\r
+ * \hideinitializer\r
+ */\r
+#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0)\r
+\r
+/**\r
+ * @brief Get WWDT Compared Match Interrupt Flag\r
+ *\r
+ * @param None\r
+ *\r
+ * @retval 0 WWDT compare match interrupt did not occur\r
+ * @retval 1 WWDT compare match interrupt occurred\r
+ *\r
+ * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not.\r
+ * \hideinitializer\r
+ */\r
+#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0)\r
+\r
+/**\r
+ * @brief Get WWDT Counter\r
+ *\r
+ * @param None\r
+ *\r
+ * @return WWDT Counter Value\r
+ *\r
+ * @details This macro reflects the current WWDT counter value.\r
+ * \hideinitializer\r
+ */\r
+#define WWDT_GET_COUNTER() (WWDT->CNT)\r
+\r
+/**\r
+ * @brief Reload WWDT Counter\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This macro is used to reload the WWDT counter value to 0x3F.\r
+ * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n\r
+ * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n\r
+ * WWDT reset signal will generate immediately to reset system.\r
+ * \hideinitializer\r
+ */\r
+#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)\r
+\r
+void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);\r
+\r
+/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group WWDT_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __WWDT_H__ */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file acmp.c\r
+ * @version V3.00\r
+ * $Revision: 1 $\r
+ * $Date: 16/07/07 7:50p $\r
+ * @brief Analog Comparator(ACMP) driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+\r
+#include "M2351.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup ACMP_Driver ACMP Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions\r
+ @{\r
+*/\r
+\r
+\r
+/**\r
+ * @brief Configure the specified ACMP module\r
+ *\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum Comparator number.\r
+ * @param[in] u32NegSrc Comparator negative input selection. Including:\r
+ * - \ref ACMP_CTL_NEGSEL_PIN\r
+ * - \ref ACMP_CTL_NEGSEL_CRV\r
+ * - \ref ACMP_CTL_NEGSEL_VBG\r
+ * - \ref ACMP_CTL_NEGSEL_DAC\r
+ * @param[in] u32HysSel The hysteresis function option. Including:\r
+ * - \ref ACMP_CTL_HYSTERESIS_30MV\r
+ * - \ref ACMP_CTL_HYSTERESIS_20MV\r
+ * - \ref ACMP_CTL_HYSTERESIS_10MV\r
+ * - \ref ACMP_CTL_HYSTERESIS_DISABLE\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Configure hysteresis function, select the source of negative input and enable analog comparator.\r
+ */\r
+void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel)\r
+{\r
+ acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Close analog comparator\r
+ *\r
+ * @param[in] acmp The pointer of the specified ACMP module\r
+ * @param[in] u32ChNum Comparator number.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.\r
+ */\r
+void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum)\r
+{\r
+ acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);\r
+}\r
+\r
+\r
+\r
+/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group ACMP_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file bpwm.c\r
+ * @version V1.00\r
+ * @brief M2351 series BPWM driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup BPWM_Driver BPWM Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Configure BPWM capture and get the nearest unit time.\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @param[in] u32UnitTimeNsec The unit time of counter\r
+ * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used\r
+ * @return The nearest unit time in nano second.\r
+ * @details This function is used to Configure BPWM capture and get the nearest unit time.\r
+ */\r
+uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)\r
+{\r
+ uint32_t u32PWMClockSrc;\r
+ uint32_t u32NearestUnitTimeNsec;\r
+ uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;\r
+ uint8_t u8BreakLoop = 0U;\r
+\r
+ /* clock source is from PCLK */\r
+ if((((uint32_t)bpwm) == BPWM0_BASE) || (((uint32_t)bpwm) == BPWM0_BASE + NS_OFFSET))\r
+ {\r
+ u32PWMClockSrc = CLK_GetPCLK0Freq();\r
+ }\r
+ else/* if((bpwm == BPWM1)||(bpwm == BPWM1_NS)) */\r
+ {\r
+ u32PWMClockSrc = CLK_GetPCLK1Freq();\r
+ }\r
+\r
+ u32PWMClockSrc /= 1000UL;\r
+ for(u32Prescale = 1U; u32Prescale <= 0x1000UL; u32Prescale++)\r
+ {\r
+ u32NearestUnitTimeNsec = (1000000UL * u32Prescale) / u32PWMClockSrc;\r
+ if(u32NearestUnitTimeNsec < u32UnitTimeNsec)\r
+ {\r
+ if(u32Prescale == 0x1000U)\r
+ {\r
+ /* limit to the maximum unit time(nano second) */\r
+ u8BreakLoop = 1U;\r
+ }\r
+ if(!((1000000UL * (u32Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))\r
+ {\r
+ u8BreakLoop = 1U;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ u8BreakLoop = 1U;\r
+ }\r
+ if(u8BreakLoop)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* convert to real register value */\r
+ u32Prescale = u32Prescale - 1U;\r
+ /* all channels share a prescaler */\r
+ BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale);\r
+\r
+ /* set BPWM to down count type(edge aligned) */\r
+ (bpwm)->CTL1 = (1UL);\r
+\r
+ BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR);\r
+\r
+ return (u32NearestUnitTimeNsec);\r
+}\r
+\r
+/**\r
+ * @brief This function Configure BPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @param[in] u32Frequency Target generator frequency\r
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...\r
+ * @return Nearest frequency clock in nano second\r
+ * @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect\r
+ * existing frequency of other channel.\r
+ * @note This function is used for initial stage.\r
+ * To change duty cycle later, it should get the configured period value and calculate the new comparator value.\r
+ */\r
+uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)\r
+{\r
+ uint32_t u32PWMClockSrc;\r
+ uint32_t i;\r
+ uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;\r
+\r
+ /* clock source is from PCLK */\r
+ if(((uint32_t)bpwm == BPWM0_BASE) || ((uint32_t)bpwm == BPWM0_BASE + NS_OFFSET))\r
+ {\r
+ u32PWMClockSrc = CLK_GetPCLK0Freq();\r
+ }\r
+ else/* if((bpwm == BPWM1)||(bpwm == BPWM1_NS)) */\r
+ {\r
+ u32PWMClockSrc = CLK_GetPCLK1Freq();\r
+ }\r
+\r
+ for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++)/* prescale could be 0~0xFFF */\r
+ {\r
+ i = (u32PWMClockSrc / u32Frequency) / u32Prescale;\r
+ /* If target value is larger than CNR, need to use a larger prescaler */\r
+ if(i <= (0x10000U))\r
+ {\r
+ u32CNR = i;\r
+ break;\r
+ }\r
+ }\r
+ /* Store return value here 'cos we're gonna change u32Prescale & u32CNR to the real value to fill into register */\r
+ i = u32PWMClockSrc / (u32Prescale * u32CNR);\r
+\r
+ /* convert to real register value */\r
+ u32Prescale = u32Prescale - 1U;\r
+ /* all channels share a prescaler */\r
+ BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale);\r
+ /* set BPWM to up counter type(edge aligned) */\r
+ (bpwm)->CTL1 = BPWM_UP_COUNTER;\r
+\r
+ u32CNR = u32CNR - 1U;\r
+ BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR);\r
+ BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL);\r
+\r
+\r
+ (bpwm)->WGCTL0 = ((bpwm)->WGCTL0 & ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \\r
+ (BPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << BPWM_WGCTL0_ZPCTL0_Pos));\r
+ (bpwm)->WGCTL1 = ((bpwm)->WGCTL1 & ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1))) | \\r
+ (BPWM_OUTPUT_LOW << (u32ChannelNum << 1UL << BPWM_WGCTL1_CMPUCTL0_Pos));\r
+\r
+ return(i);\r
+}\r
+\r
+/**\r
+ * @brief Start BPWM module\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.\r
+ * @return None\r
+ * @details This function is used to start BPWM module.\r
+ * @note All channels share one counter.\r
+ */\r
+void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask)\r
+{\r
+ (bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Stop BPWM module\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.\r
+ * @return None\r
+ * @details This function is used to stop BPWM module.\r
+ * @note All channels share one period.\r
+ */\r
+void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask)\r
+{\r
+ (bpwm)->PERIOD = 0UL;\r
+}\r
+\r
+/**\r
+ * @brief Stop BPWM generation immediately by clear channel enable bit\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.\r
+ * @return None\r
+ * @details This function is used to stop BPWM generation immediately by clear channel enable bit.\r
+ * @note All channels share one counter.\r
+ */\r
+void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask)\r
+{\r
+ (bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable selected channel to trigger ADC\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:\r
+ * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT\r
+ * - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT\r
+ * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT\r
+ * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT\r
+ * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT\r
+ * - \ref BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT\r
+ * - \ref BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT\r
+ * @return None\r
+ * @details This function is used to enable selected channel to trigger ADC\r
+ */\r
+void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)\r
+{\r
+ if(u32ChannelNum < 4UL)\r
+ {\r
+ (bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3));\r
+ (bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3));\r
+ }\r
+ else\r
+ {\r
+ (bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3));\r
+ (bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable selected channel to trigger ADC\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3\r
+ * @return None\r
+ * @details This function is used to disable selected channel to trigger ADC\r
+ */\r
+void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ if(u32ChannelNum < 4UL)\r
+ {\r
+ (bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3));\r
+ }\r
+ else\r
+ {\r
+ (bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Clear selected channel trigger ADC flag\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @param[in] u32Condition This parameter is not used\r
+ * @return None\r
+ * @details This function is used to clear selected channel trigger ADC flag\r
+ */\r
+void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)\r
+{\r
+ (bpwm)->STATUS = (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum);\r
+}\r
+\r
+/**\r
+ * @brief Get selected channel trigger ADC flag\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @retval 0 The specified channel trigger ADC to start of conversion flag is not set\r
+ * @retval 1 The specified channel trigger ADC to start of conversion flag is set\r
+ * @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel\r
+ */\r
+uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Enable capture of selected channel(s)\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.\r
+ * Bit 0 is channel 0, bit 1 is channel 1...\r
+ * @return None\r
+ * @details This function is used to enable capture of selected channel(s)\r
+ */\r
+void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)\r
+{\r
+ (bpwm)->CAPINEN |= u32ChannelMask;\r
+ (bpwm)->CAPCTL |= u32ChannelMask;\r
+}\r
+\r
+/**\r
+ * @brief Disable capture of selected channel(s)\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.\r
+ * Bit 0 is channel 0, bit 1 is channel 1...\r
+ * @return None\r
+ * @details This function is used to disable capture of selected channel(s)\r
+ */\r
+void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)\r
+{\r
+ (bpwm)->CAPINEN &= ~u32ChannelMask;\r
+ (bpwm)->CAPCTL &= ~u32ChannelMask;\r
+}\r
+\r
+/**\r
+ * @brief Enables BPWM output generation of selected channel(s)\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.\r
+ * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...\r
+ * @return None\r
+ * @details This function is used to enables BPWM output generation of selected channel(s)\r
+ */\r
+void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)\r
+{\r
+ (bpwm)->POEN |= u32ChannelMask;\r
+}\r
+\r
+/**\r
+ * @brief Disables BPWM output generation of selected channel(s)\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel\r
+ * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...\r
+ * @return None\r
+ * @details This function is used to disables BPWM output generation of selected channel(s)\r
+ */\r
+void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)\r
+{\r
+ (bpwm)->POEN &= ~u32ChannelMask;\r
+}\r
+\r
+/**\r
+ * @brief Enable capture interrupt of selected channel.\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @param[in] u32Edge Rising or falling edge to latch counter.\r
+ * - \ref BPWM_CAPTURE_INT_RISING_LATCH\r
+ * - \ref BPWM_CAPTURE_INT_FALLING_LATCH\r
+ * @return None\r
+ * @details This function is used to enable capture interrupt of selected channel.\r
+ */\r
+void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)\r
+{\r
+ (bpwm)->CAPIEN |= (u32Edge << u32ChannelNum);\r
+}\r
+\r
+/**\r
+ * @brief Disable capture interrupt of selected channel.\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @param[in] u32Edge Rising or falling edge to latch counter.\r
+ * - \ref BPWM_CAPTURE_INT_RISING_LATCH\r
+ * - \ref BPWM_CAPTURE_INT_FALLING_LATCH\r
+ * @return None\r
+ * @details This function is used to disable capture interrupt of selected channel.\r
+ */\r
+void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)\r
+{\r
+ (bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);\r
+}\r
+\r
+/**\r
+ * @brief Clear capture interrupt of selected channel.\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @param[in] u32Edge Rising or falling edge to latch counter.\r
+ * - \ref BPWM_CAPTURE_INT_RISING_LATCH\r
+ * - \ref BPWM_CAPTURE_INT_FALLING_LATCH\r
+ * @return None\r
+ * @details This function is used to clear capture interrupt of selected channel.\r
+ */\r
+void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)\r
+{\r
+ (bpwm)->CAPIF = (u32Edge << u32ChannelNum);\r
+}\r
+\r
+/**\r
+ * @brief Get capture interrupt of selected channel.\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @retval 0 No capture interrupt\r
+ * @retval 1 Rising edge latch interrupt\r
+ * @retval 2 Falling edge latch interrupt\r
+ * @retval 3 Rising and falling latch interrupt\r
+ * @details This function is used to get capture interrupt of selected channel.\r
+ */\r
+uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ uint32_t u32CapIf = 0UL;\r
+\r
+ u32CapIf = ((((bpwm)->CAPIF & (BYTE1_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1);\r
+ u32CapIf |= (((bpwm)->CAPIF & (BYTE0_Msk << u32ChannelNum)) ? 1UL : 0UL);\r
+ return u32CapIf;\r
+}\r
+/**\r
+ * @brief Enable duty interrupt of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @param[in] u32IntDutyType Duty interrupt type, could be either\r
+ * - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP\r
+ * - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP\r
+ * @return None\r
+ * @details This function is used to enable duty interrupt of selected channel.\r
+ */\r
+void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)\r
+{\r
+ (bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum);\r
+}\r
+\r
+/**\r
+ * @brief Disable duty interrupt of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @return None\r
+ * @details This function is used to disable duty interrupt of selected channel\r
+ */\r
+void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ (bpwm)->INTEN &= ~((BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);\r
+}\r
+\r
+/**\r
+ * @brief Clear duty interrupt flag of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @return None\r
+ * @details This function is used to clear duty interrupt flag of selected channel\r
+ */\r
+void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ (bpwm)->INTSTS = (BYTE2_Msk | BYTE3_Msk) << u32ChannelNum;\r
+}\r
+\r
+/**\r
+ * @brief Get duty interrupt flag of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @return Duty interrupt flag of specified channel\r
+ * @retval 0 Duty interrupt did not occur\r
+ * @retval 1 Duty interrupt occurred\r
+ * @details This function is used to get duty interrupt flag of selected channel\r
+ */\r
+uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ return ((((bpwm)->INTSTS & ((BYTE2_Msk | BYTE3_Msk) << u32ChannelNum))) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Enable period interrupt of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.\r
+ * @return None\r
+ * @details This function is used to enable period interrupt of selected channel.\r
+ * @note All channels share channel 0's setting.\r
+ */\r
+void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)\r
+{\r
+ (bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable period interrupt of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @return None\r
+ * @details This function is used to disable period interrupt of selected channel.\r
+ * @note All channels share channel 0's setting.\r
+ */\r
+void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ (bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Clear period interrupt of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @return None\r
+ * @details This function is used to clear period interrupt of selected channel\r
+ * @note All channels share channel 0's setting.\r
+ */\r
+void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ (bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Get period interrupt of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @return Period interrupt flag of specified channel\r
+ * @retval 0 Period interrupt did not occur\r
+ * @retval 1 Period interrupt occurred\r
+ * @details This function is used to get period interrupt of selected channel\r
+ * @note All channels share channel 0's setting.\r
+ */\r
+uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Enable zero interrupt of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @return None\r
+ * @details This function is used to enable zero interrupt of selected channel.\r
+ * @note All channels share channel 0's setting.\r
+ */\r
+void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ (bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable zero interrupt of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @return None\r
+ * @details This function is used to disable zero interrupt of selected channel.\r
+ * @note All channels share channel 0's setting.\r
+ */\r
+void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ (bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Clear zero interrupt of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @return None\r
+ * @details This function is used to clear zero interrupt of selected channel.\r
+ * @note All channels share channel 0's setting.\r
+ */\r
+void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ (bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Get zero interrupt of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @return zero interrupt flag of specified channel\r
+ * @retval 0 zero interrupt did not occur\r
+ * @retval 1 zero interrupt occurred\r
+ * @details This function is used to get zero interrupt of selected channel.\r
+ * @note All channels share channel 0's setting.\r
+ */\r
+uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Enable load mode of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @param[in] u32LoadMode BPWM counter loading mode.\r
+ * - \ref BPWM_LOAD_MODE_IMMEDIATE\r
+ * - \ref BPWM_LOAD_MODE_CENTER\r
+ * @return None\r
+ * @details This function is used to enable load mode of selected channel.\r
+ */\r
+void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)\r
+{\r
+ (bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum);\r
+}\r
+\r
+/**\r
+ * @brief Disable load mode of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5\r
+ * @param[in] u32LoadMode BPWM counter loading mode.\r
+ * - \ref BPWM_LOAD_MODE_IMMEDIATE\r
+ * - \ref BPWM_LOAD_MODE_CENTER\r
+ * @return None\r
+ * @details This function is used to disable load mode of selected channel.\r
+ */\r
+void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)\r
+{\r
+ (bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);\r
+}\r
+\r
+/**\r
+ * @brief Set BPWM clock source\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @param[in] u32ClkSrcSel BPWM external clock source.\r
+ * - \ref BPWM_CLKSRC_BPWM_CLK\r
+ * - \ref BPWM_CLKSRC_TIMER0\r
+ * - \ref BPWM_CLKSRC_TIMER1\r
+ * - \ref BPWM_CLKSRC_TIMER2\r
+ * - \ref BPWM_CLKSRC_TIMER3\r
+ * @return None\r
+ * @details This function is used to set BPWM clock source.\r
+ * @note All channels share channel 0's setting.\r
+ */\r
+void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)\r
+{\r
+ (bpwm)->CLKSRC = (u32ClkSrcSel);\r
+}\r
+\r
+/**\r
+ * @brief Get the time-base counter reached its maximum value flag of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @return Count to max interrupt flag of specified channel\r
+ * @retval 0 Count to max interrupt did not occur\r
+ * @retval 1 Count to max interrupt occurred\r
+ * @details This function is used to get the time-base counter reached its maximum value flag of selected channel.\r
+ * @note All channels share channel 0's setting.\r
+ */\r
+uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Clear the time-base counter reached its maximum value flag of selected channel\r
+ * @param[in] bpwm The pointer of the specified BPWM module\r
+ * - BPWM0 : BPWM Group 0\r
+ * - BPWM1 : BPWM Group 1\r
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.\r
+ * @return None\r
+ * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.\r
+ * @note All channels share channel 0's setting.\r
+ */\r
+void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)\r
+{\r
+ (bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk;\r
+}\r
+\r
+\r
+/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group BPWM_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file can.c\r
+ * @version V1.00\r
+ * @brief CAN driver source file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "M2351.h"\r
+\r
+#if defined(__ICCARM__)\r
+# pragma diag_suppress=Pm073, Pm143 /* Misra C rule 14.7 */\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CAN_Driver CAN Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions\r
+ @{\r
+*/\r
+\r
+/** @cond HIDDEN_SYMBOLS */\r
+\r
+#if defined(CAN1)\r
+static uint8_t gu8LockCanIf[2][2] = {0U}; /* The chip has two CANs. */\r
+#elif defined(CAN0) || defined(CAN)\r
+static uint8_t gu8LockCanIf[1][2] = {0U}; /* The chip only has one CAN. */\r
+#endif\r
+\r
+#define RETRY_COUNTS (0x10000000UL)\r
+\r
+#define TSEG1_MIN 2\r
+#define TSEG1_MAX 16\r
+#define TSEG2_MIN 1\r
+#define TSEG2_MAX 8\r
+#define BRP_MIN 1\r
+#define BRP_MAX 1024 /* 6-bit BRP field + 4-bit BRPE field*/\r
+#define SJW_MAX 4UL\r
+#define BRP_INC 1\r
+\r
+/* #define DEBUG_PRINTF printf */\r
+#define DEBUG_PRINTF(...)\r
+\r
+\r
+static uint32_t LockIF(CAN_T *tCAN);\r
+static uint32_t LockIF_TL(CAN_T *tCAN);\r
+static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo);\r
+static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2);\r
+\r
+/**\r
+ * @brief Check if any interface is available then lock it for usage.\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @retval 0 IF0 is free\r
+ * @retval 1 IF1 is free\r
+ * @retval 2 No IF is free\r
+ * @details Search the first free message interface, starting from 0. If a interface is\r
+ * available, set a flag to lock the interface.\r
+ */\r
+static uint32_t LockIF(CAN_T *tCAN)\r
+{\r
+ uint32_t u32CanNo;\r
+ uint32_t u32FreeIfNo;\r
+ uint32_t u32IntMask;\r
+\r
+#if defined(CAN1)\r
+ u32CanNo = (tCAN == CAN1) ? 1 : 0;\r
+#else // defined(CAN0) || defined(CAN)\r
+ u32CanNo = 0U;\r
+#endif\r
+\r
+ u32FreeIfNo = 2U;\r
+\r
+ /* Disable CAN interrupt */\r
+ u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);\r
+ tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);\r
+\r
+ /* Check interface 1 is available or not */\r
+ if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0U)\r
+ {\r
+ if(gu8LockCanIf[u32CanNo][0] == (uint8_t)FALSE)\r
+ {\r
+ gu8LockCanIf[u32CanNo][0] = (uint8_t)TRUE;\r
+ u32FreeIfNo = 0U;\r
+ }\r
+ }\r
+\r
+ /* Or check interface 2 is available or not */\r
+ if(u32FreeIfNo == 2U)\r
+ {\r
+ if((tCAN->IF[1].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0U)\r
+ {\r
+ if(gu8LockCanIf[u32CanNo][1] == (uint8_t)FALSE)\r
+ {\r
+ gu8LockCanIf[u32CanNo][1] = (uint8_t)TRUE;\r
+ u32FreeIfNo = 1U;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Enable CAN interrupt */\r
+ tCAN->CON |= u32IntMask;\r
+\r
+ return u32FreeIfNo;\r
+}\r
+\r
+/**\r
+ * @brief Check if any interface is available in a time limitation then lock it for usage.\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @retval 0 IF0 is free\r
+ * @retval 1 IF1 is free\r
+ * @retval 2 No IF is free\r
+ * @details Search the first free message interface, starting from 0. If no interface is\r
+ * it will try again until time out. If a interface is available, set a flag to\r
+ * lock the interface.\r
+ */\r
+static uint32_t LockIF_TL(CAN_T *tCAN)\r
+{\r
+ uint32_t u32Count;\r
+ uint32_t u32FreeIfNo;\r
+\r
+ for(u32Count = 0U; u32Count < (uint32_t)RETRY_COUNTS; u32Count++)\r
+ {\r
+ if((u32FreeIfNo = LockIF(tCAN)) != 2U)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ return u32FreeIfNo;\r
+}\r
+\r
+/**\r
+ * @brief Release locked interface.\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32Info The interface number, 0 or 1.\r
+ * @return none\r
+ * @details Release the locked interface.\r
+ */\r
+static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo)\r
+{\r
+ uint32_t u32IntMask;\r
+ uint32_t u32CanNo;\r
+\r
+ if(u32IfNo < 2U)\r
+ {\r
+\r
+#if defined(CAN1)\r
+ u32CanNo = (tCAN == CAN1) ? 1U : 0U;\r
+#else // defined(CAN0) || defined(CAN)\r
+ u32CanNo = 0U;\r
+#endif\r
+\r
+ /* Disable CAN interrupt */\r
+ u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);\r
+ tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);\r
+\r
+ gu8LockCanIf[u32CanNo][u32IfNo] = (uint8_t)FALSE;\r
+\r
+ /* Enable CAN interrupt */\r
+ tCAN->CON |= u32IntMask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enter initialization mode\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] Following values can be used.\r
+ * \ref CAN_CON_DAR_Msk Disable automatic retransmission.\r
+ * \ref CAN_CON_EIE_Msk Enable error interrupt.\r
+ * \ref CAN_CON_SIE_Msk Enable status interrupt.\r
+ * \ref CAN_CON_IE_Msk CAN interrupt.\r
+ * @return None\r
+ * @details This function is used to set CAN to enter initialization mode and enable access bit timing\r
+ * register. After bit timing configuration ready, user must call CAN_LeaveInitMode()\r
+ * to leave initialization mode and lock bit timing register to let new configuration\r
+ * take effect.\r
+ */\r
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask)\r
+{\r
+ tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Leave initialization mode\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @return None\r
+ * @details This function is used to set CAN to leave initialization mode to let\r
+ * bit timing configuration take effect after configuration ready.\r
+ */\r
+void CAN_LeaveInitMode(CAN_T *tCAN)\r
+{\r
+ tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));\r
+ while(tCAN->CON & CAN_CON_INIT_Msk) {} /* Check INIT bit is released */\r
+}\r
+\r
+/**\r
+ * @brief Wait message into message buffer in basic mode.\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @return None\r
+ * @details This function is used to wait message into message buffer in basic mode. Please notice the\r
+ * function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode.\r
+ */\r
+void CAN_WaitMsg(CAN_T *tCAN)\r
+{\r
+ tCAN->STATUS = 0x0U; /* clr status */\r
+\r
+ while(1)\r
+ {\r
+ if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) /* check new data */\r
+ {\r
+ /* DEBUG_PRINTF("New Data IN\n"); */\r
+ break;\r
+ }\r
+\r
+ if(tCAN->STATUS & CAN_STATUS_RXOK_Msk)\r
+ {\r
+ /* DEBUG_PRINTF("Rx OK\n"); */\r
+ }\r
+\r
+ if(tCAN->STATUS & CAN_STATUS_LEC_Msk)\r
+ {\r
+ /* DEBUG_PRINTF("Error\n"); */\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get current bit rate\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @return Current Bit-Rate (kilo bit per second)\r
+ * @details Return current CAN bit rate according to the user bit-timing parameter settings\r
+ */\r
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN)\r
+{\r
+ uint8_t u8Tseg1, u8Tseg2;\r
+ uint32_t u32Bpr;\r
+\r
+ u8Tseg1 = (uint8_t)((tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos);\r
+ u8Tseg2 = (uint8_t)((tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos);\r
+ u32Bpr = (tCAN->BTIME & CAN_BTIME_BRP_Msk);\r
+ u32Bpr |= (tCAN->BRPE << 6);\r
+\r
+\r
+ return (SystemCoreClock / (u32Bpr + 1U) / ((uint32_t)u8Tseg1 + (uint32_t)u8Tseg2 + 3U));\r
+}\r
+\r
+/**\r
+ * @brief Switch the CAN into test mode.\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u8TestMask Specifies the configuration in test modes\r
+ * \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode\r
+ * \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode\r
+ * \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode\r
+ * \ref CAN_TEST_TX0_Msk / \ref CAN_TEST_TX1_Msk Control CAN_TX pin bit field\r
+ * @return None\r
+ * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/\r
+ * LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user\r
+ * must call CAN_LeaveInitMode() to let the setting take effect.\r
+ */\r
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask)\r
+{\r
+ tCAN->CON |= CAN_CON_TEST_Msk;\r
+ tCAN->TEST = u8TestMask;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Leave the test mode\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @return None\r
+ * @details This function is used to Leave the test mode (switch into normal mode).\r
+ */\r
+void CAN_LeaveTestMode(CAN_T *tCAN)\r
+{\r
+ tCAN->CON |= CAN_CON_TEST_Msk;\r
+ tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk);\r
+ tCAN->CON &= (~CAN_CON_TEST_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Get the waiting status of a received message.\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.\r
+ * @retval non-zero The corresponding message object has a new data bit is set.\r
+ * @retval 0 No message object has new data.\r
+ * @details This function is used to get the waiting status of a received message.\r
+ */\r
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj)\r
+{\r
+ uint32_t ret;\r
+\r
+ if((uint32_t)u8MsgObj < 16U)\r
+ {\r
+ ret = tCAN->NDAT1 & (1UL << u8MsgObj);\r
+ }\r
+ else\r
+ {\r
+ ret = tCAN->NDAT2 & (1UL << (u8MsgObj - 16U));\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Send CAN message in BASIC mode of test mode\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] pCanMsg Pointer to the message structure containing data to transmit.\r
+ * @return TRUE: Transmission OK\r
+ * FALSE: Check busy flag of interface 0 is timeout\r
+ * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API,\r
+ * the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter\r
+ * basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode.\r
+ */\r
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)\r
+{\r
+ uint32_t i = 0UL;\r
+ while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) {}\r
+\r
+\r
+ tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);\r
+\r
+ if(pCanMsg->IdType == CAN_STD_ID)\r
+ {\r
+ /* standard ID*/\r
+ tCAN->IF[0].ARB1 = 0UL;\r
+ tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FFUL) << 2) ;\r
+ }\r
+ else\r
+ {\r
+ /* extended ID*/\r
+ tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFFUL;\r
+ tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x1FFF0000UL) >> 16) | CAN_IF_ARB2_XTD_Msk;\r
+\r
+ }\r
+\r
+ if(pCanMsg->FrameType)\r
+ {\r
+ tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk;\r
+ }\r
+ else\r
+ {\r
+ tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);\r
+ }\r
+\r
+ tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC;\r
+ tCAN->IF[0].DAT_A1 = ((uint32_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0];\r
+ tCAN->IF[0].DAT_A2 = ((uint32_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2];\r
+ tCAN->IF[0].DAT_B1 = ((uint32_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4];\r
+ tCAN->IF[0].DAT_B2 = ((uint32_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6];\r
+\r
+ /* request transmission*/\r
+ tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk);\r
+ if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk)\r
+ {\r
+ /* DEBUG_PRINTF("Cannot clear busy for sending ...\n"); */\r
+ return (int32_t)FALSE;\r
+ }\r
+\r
+ tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk; /* sending */\r
+\r
+ for(i = 0UL; i < 0xFFFFFUL; i++)\r
+ {\r
+ if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0UL)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(i >= 0xFFFFFUL)\r
+ {\r
+ /* DEBUG_PRINTF("Cannot send out...\n"); */\r
+ return (int32_t)FALSE;\r
+ }\r
+\r
+\r
+ return (int32_t)TRUE;\r
+}\r
+\r
+/**\r
+ * @brief Get a message information in BASIC mode.\r
+ *\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.\r
+ *\r
+ * @return FALSE No any message received.\r
+ * TRUE Receive a message success.\r
+ *\r
+ */\r
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)\r
+{\r
+\r
+ if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0UL) /* In basic mode, receive data always save in IF2 */\r
+ {\r
+ return (int32_t)FALSE;\r
+ }\r
+\r
+ tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);\r
+\r
+ tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk\r
+ | CAN_IF_CMASK_CONTROL_Msk\r
+ | CAN_IF_CMASK_DATAA_Msk\r
+ | CAN_IF_CMASK_DATAB_Msk;\r
+\r
+ if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0UL)\r
+ {\r
+ /* standard ID*/\r
+ pCanMsg->IdType = CAN_STD_ID;\r
+ pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FFUL;\r
+\r
+ }\r
+ else\r
+ {\r
+ /* extended ID*/\r
+ pCanMsg->IdType = CAN_EXT_ID;\r
+ pCanMsg->Id = (tCAN->IF[1].ARB2 & 0x1FFFUL) << 16;\r
+ pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1;\r
+ }\r
+\r
+ /*\r
+ pCanMsg->FrameType = (uint32_t)(!(uint32_t)((tCAN->IF[1].ARB2 & (uint32_t)CAN_IF_ARB2_DIR_Msk) >> (uint32_t)CAN_IF_ARB2_DIR_Pos));\r
+ */\r
+\r
+ pCanMsg->FrameType = (tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) ? 0UL : 1UL;\r
+\r
+ pCanMsg->DLC = (uint8_t)(tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk);\r
+ pCanMsg->Data[0] = (uint8_t)(tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk);\r
+ pCanMsg->Data[1] = (uint8_t)((tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos);\r
+ pCanMsg->Data[2] = (uint8_t)(tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk);\r
+ pCanMsg->Data[3] = (uint8_t)((tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos);\r
+ pCanMsg->Data[4] = (uint8_t)(tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk);\r
+ pCanMsg->Data[5] = (uint8_t)((tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos);\r
+ pCanMsg->Data[6] = (uint8_t)(tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk);\r
+ pCanMsg->Data[7] = (uint8_t)((tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos);\r
+\r
+ return (int32_t)TRUE;\r
+}\r
+\r
+/**\r
+ * @brief Set Rx message object, include ID mask.\r
+ * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.\r
+ * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted\r
+ * This parameter can be one of the following values:\r
+ * \ref CAN_STD_ID (standard ID, 11-bit)\r
+ * \ref CAN_EXT_ID (extended ID, 29-bit)\r
+ * @param[in] u32id Specifies the identifier used for acceptance filtering.\r
+ * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.\r
+ * This parameter can be one of the following values:\r
+ * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.\r
+ * FALSE: for a FIFO receive object that is not the last one.\r
+ * @retval TRUE SUCCESS\r
+ * @retval FALSE No useful interface\r
+ * @details The function is used to configure a receive message object.\r
+ */\r
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast)\r
+{\r
+ uint8_t u8MsgIfNum;\r
+\r
+ /* Get and lock a free interface */\r
+ if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U)\r
+ {\r
+ return (int32_t)FALSE;\r
+ }\r
+\r
+ /* Command Setting */\r
+ tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |\r
+ CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;\r
+\r
+ if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */\r
+ {\r
+ tCAN->IF[u8MsgIfNum].ARB1 = 0U;\r
+ tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFUL) << 2;\r
+ }\r
+ else\r
+ {\r
+ tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFFUL;\r
+ tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000UL) >> 16;\r
+ }\r
+\r
+ tCAN->IF[u8MsgIfNum].MASK1 = (u32idmask & 0xFFFFUL);\r
+ tCAN->IF[u8MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFFUL;\r
+\r
+\r
+ tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;\r
+ if(u8singleOrFifoLast)\r
+ {\r
+ tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;\r
+ }\r
+ else\r
+ {\r
+ tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);\r
+ }\r
+\r
+ tCAN->IF[u8MsgIfNum].DAT_A1 = 0U;\r
+ tCAN->IF[u8MsgIfNum].DAT_A2 = 0U;\r
+ tCAN->IF[u8MsgIfNum].DAT_B1 = 0U;\r
+ tCAN->IF[u8MsgIfNum].DAT_B2 = 0U;\r
+\r
+ tCAN->IF[u8MsgIfNum].CREQ = 1UL + u8MsgObj;\r
+ ReleaseIF(tCAN, (uint32_t)u8MsgIfNum);\r
+\r
+ return (int32_t)TRUE;\r
+}\r
+\r
+/**\r
+ * @brief Set Rx message object\r
+ * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.\r
+ * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted\r
+ * This parameter can be one of the following values:\r
+ * \ref CAN_STD_ID (standard ID, 11-bit)\r
+ * \ref CAN_EXT_ID (extended ID, 29-bit)\r
+ * @param[in] u32id Specifies the identifier used for acceptance filtering.\r
+ * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.\r
+ * This parameter can be one of the following values:\r
+ * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.\r
+ * FALSE: for a FIFO receive object that is not the last one.\r
+ * @retval TRUE SUCCESS\r
+ * @retval FALSE No useful interface\r
+ * @details The function is used to configure a receive message object.\r
+ */\r
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast)\r
+{\r
+ uint8_t u8MsgIfNum;\r
+\r
+ /* Get and lock a free interface */\r
+ if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U)\r
+ {\r
+ return (int32_t)FALSE;\r
+ }\r
+\r
+ /* Command Setting */\r
+ tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |\r
+ CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;\r
+\r
+ if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */\r
+ {\r
+ tCAN->IF[u8MsgIfNum].ARB1 = 0U;\r
+ tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFUL) << 2;\r
+ }\r
+ else\r
+ {\r
+ tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFFUL;\r
+ tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000UL) >> 16;\r
+ }\r
+\r
+\r
+ tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;\r
+ if(u8singleOrFifoLast)\r
+ {\r
+ tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;\r
+ }\r
+ else\r
+ {\r
+ tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);\r
+ }\r
+\r
+ tCAN->IF[u8MsgIfNum].DAT_A1 = 0U;\r
+ tCAN->IF[u8MsgIfNum].DAT_A2 = 0U;\r
+ tCAN->IF[u8MsgIfNum].DAT_B1 = 0U;\r
+ tCAN->IF[u8MsgIfNum].DAT_B2 = 0U;\r
+\r
+ tCAN->IF[u8MsgIfNum].CREQ = 1UL + u8MsgObj;\r
+ ReleaseIF(tCAN, (uint32_t)u8MsgIfNum);\r
+\r
+ return (int32_t)TRUE;\r
+}\r
+\r
+/**\r
+ * @brief Gets the message\r
+ * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.\r
+ * @param[in] u8Release Specifies the message release indicator.\r
+ * This parameter can be one of the following values:\r
+ * TRUE: the message object is released when getting the data.\r
+ * FALSE:the message object is not released.\r
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.\r
+ * @retval TRUE Success\r
+ * @retval FALSE No any message received\r
+ * @details Gets the message, if received.\r
+ */\r
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg)\r
+{\r
+ uint8_t u8MsgIfNum;\r
+ uint32_t u32Tmp;\r
+\r
+ if(!CAN_IsNewDataReceived(tCAN, u8MsgObj))\r
+ {\r
+ return (int32_t)FALSE;\r
+ }\r
+\r
+ /* Get and lock a free interface */\r
+ if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U)\r
+ {\r
+ return (int32_t)FALSE;\r
+ }\r
+\r
+ tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);\r
+\r
+ /* read the message contents*/\r
+ tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk\r
+ | CAN_IF_CMASK_ARB_Msk\r
+ | CAN_IF_CMASK_CONTROL_Msk\r
+ | CAN_IF_CMASK_CLRINTPND_Msk\r
+ | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0UL)\r
+ | CAN_IF_CMASK_DATAA_Msk\r
+ | CAN_IF_CMASK_DATAB_Msk;\r
+\r
+ tCAN->IF[u8MsgIfNum].CREQ = 1UL + u8MsgObj;\r
+\r
+ while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)\r
+ {\r
+ /*Wait*/\r
+ }\r
+\r
+ if((tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0U)\r
+ {\r
+ /* standard ID*/\r
+ pCanMsg->IdType = CAN_STD_ID;\r
+ pCanMsg->Id = (tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2;\r
+ }\r
+ else\r
+ {\r
+ /* extended ID*/\r
+ pCanMsg->IdType = CAN_EXT_ID;\r
+\r
+ u32Tmp = (((tCAN->IF[u8MsgIfNum].ARB2) & 0x1FFFUL) << 16);\r
+ u32Tmp |= tCAN->IF[u8MsgIfNum].ARB1;\r
+\r
+ pCanMsg->Id = u32Tmp;\r
+ }\r
+\r
+ pCanMsg->DLC = (uint8_t)(tCAN->IF[u8MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk);\r
+ pCanMsg->Data[0] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk);\r
+ pCanMsg->Data[1] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos);\r
+ pCanMsg->Data[2] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk);\r
+ pCanMsg->Data[3] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos);\r
+ pCanMsg->Data[4] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk);\r
+ pCanMsg->Data[5] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos);\r
+ pCanMsg->Data[6] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk);\r
+ pCanMsg->Data[7] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos);\r
+\r
+ ReleaseIF(tCAN, (uint32_t)u8MsgIfNum);\r
+ return (int32_t)TRUE;\r
+}\r
+\r
+static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2)\r
+{\r
+ *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000;\r
+ if(*tseg2 < TSEG2_MIN)\r
+ {\r
+ *tseg2 = TSEG2_MIN;\r
+ }\r
+ if(*tseg2 > TSEG2_MAX)\r
+ {\r
+ *tseg2 = TSEG2_MAX;\r
+ }\r
+\r
+ *tseg1 = tseg - *tseg2;\r
+\r
+ if(*tseg1 > TSEG1_MAX)\r
+ {\r
+ *tseg1 = TSEG1_MAX;\r
+ *tseg2 = tseg - *tseg1;\r
+ }\r
+ return 1000 * (tseg + 1 - *tseg2) / (tseg + 1);\r
+}\r
+\r
+/** @endcond HIDDEN_SYMBOLS */\r
+\r
+/**\r
+ * @brief Set bus baud-rate.\r
+ *\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.\r
+ *\r
+ * @return u32CurrentBitRate Real baud-rate value.\r
+ *\r
+ * @details The function is used to set bus timing parameter according current clock and target baud-rate.\r
+ */\r
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)\r
+{\r
+ long rate;\r
+ long best_error = 1000000000, error = 0;\r
+ int best_tseg = 0, best_brp = 0, brp = 0;\r
+ int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0;\r
+ int spt_error = 1000, spt = 0, sampl_pt;\r
+ int64_t clock_freq = 0;\r
+ uint32_t sjw = 1UL;\r
+\r
+ CAN_EnterInitMode(tCAN, 0U);\r
+\r
+ clock_freq = (int64_t)CLK_GetPCLK0Freq();\r
+\r
+ if(u32BaudRate >= 1000000UL)\r
+ {\r
+ u32BaudRate = 1000000UL;\r
+ }\r
+\r
+ /* Use CIA recommended sample points */\r
+ if(u32BaudRate > 800000UL)\r
+ {\r
+ sampl_pt = 750;\r
+ }\r
+ else if(u32BaudRate > 500000UL)\r
+ {\r
+ sampl_pt = 800;\r
+ }\r
+ else\r
+ {\r
+ sampl_pt = 875;\r
+ }\r
+\r
+ /* tseg even = round down, odd = round up */\r
+ for(tseg = (TSEG1_MAX + TSEG2_MAX) * 2 + 1; tseg >= (TSEG1_MIN + TSEG2_MIN) * 2; tseg--)\r
+ {\r
+ tsegall = 1 + tseg / 2;\r
+ /* Compute all possible tseg choices (tseg=tseg1+tseg2) */\r
+\r
+ /* brp = (int32_t)(clock_freq / (tsegall * u32BaudRate)) + (tseg % 2); */\r
+ brp = (int32_t)(clock_freq / ((int64_t)tsegall * (int32_t)u32BaudRate)) + (tseg % 2);\r
+\r
+\r
+ /* chose brp step which is possible in system */\r
+ brp = (brp / BRP_INC) * BRP_INC;\r
+\r
+ if((brp >= BRP_MIN) && (brp <= BRP_MAX))\r
+ {\r
+ rate = (int32_t)(clock_freq / ((int64_t)brp * tsegall));\r
+\r
+ error = (int32_t)u32BaudRate - rate;\r
+\r
+ /* tseg brp biterror */\r
+ if(error < 0)\r
+ {\r
+ error = -error;\r
+ }\r
+\r
+ if(error <= best_error)\r
+ {\r
+ best_error = error;\r
+ if(error == 0)\r
+ {\r
+ spt = can_update_spt(sampl_pt, tseg / 2, &tseg1, &tseg2);\r
+ error = sampl_pt - spt;\r
+ if(error < 0)\r
+ {\r
+ error = -error;\r
+ }\r
+ if(error <= spt_error)\r
+ {\r
+ spt_error = error;\r
+ best_tseg = tseg / 2;\r
+ best_brp = brp;\r
+ if(error == 0)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ best_tseg = tseg / 2;\r
+ best_brp = brp;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ spt = can_update_spt(sampl_pt, best_tseg, &tseg1, &tseg2);\r
+\r
+ /* check for sjw user settings */\r
+ /* bt->sjw is at least 1 -> sanitize upper bound to sjw_max */\r
+ if(sjw > SJW_MAX)\r
+ {\r
+ sjw = SJW_MAX;\r
+ }\r
+ /* bt->sjw must not be higher than tseg2 */\r
+ if(tseg2 < (int32_t)sjw)\r
+ {\r
+ sjw = (uint32_t)tseg2;\r
+ }\r
+\r
+ /* real bit-rate */\r
+ u32BaudRate = (uint32_t)(int32_t)(clock_freq / (int32_t)(best_brp * (tseg1 + tseg2 + 1)));\r
+\r
+ tCAN->BTIME = (((uint32_t)tseg2 - 1UL) << CAN_BTIME_TSEG2_Pos) | (((uint32_t)tseg1 - 1UL) << CAN_BTIME_TSEG1_Pos) |\r
+ (((uint32_t)best_brp - 1UL) & CAN_BTIME_BRP_Msk) | (sjw << CAN_BTIME_SJW_Pos);\r
+\r
+\r
+ tCAN->BRPE = (((uint32_t)best_brp - 1UL) >> 6) & 0x0FUL;\r
+\r
+ /* DEBUG_PRINTF("\n bitrate = %d \n", CAN_GetCANBitRate(tCAN)); */\r
+\r
+ CAN_LeaveInitMode(tCAN);\r
+\r
+ return u32BaudRate;\r
+}\r
+\r
+/**\r
+ * @brief The function is used to disable all CAN interrupt.\r
+ *\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details No Status Change Interrupt and Error Status Interrupt will be generated.\r
+ */\r
+\r
+\r
+void CAN_Close(CAN_T *tCAN)\r
+{\r
+ CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Set CAN operation mode and target baud-rate.\r
+ *\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.\r
+ * @param[in] u32Mode The CAN operation mode. Valid values are:\r
+ * - \ref CAN_NORMAL_MODE Normal operation.\r
+ * - \ref CAN_BASIC_MODE Basic mode.\r
+ * @return u32CurrentBitRate Real baud-rate value.\r
+ *\r
+ * @details Set bus timing parameter according current clock and target baud-rate.\r
+ * In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.\r
+ */\r
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode)\r
+{\r
+ uint32_t u32CurrentBitRate;\r
+\r
+ u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate);\r
+\r
+ if(u32Mode == CAN_BASIC_MODE)\r
+ {\r
+ CAN_EnterTestMode(tCAN, (uint8_t)CAN_TEST_BASIC_Msk);\r
+ }\r
+\r
+ return u32CurrentBitRate;\r
+}\r
+\r
+/**\r
+ * @brief The function is used to configure a transmit object.\r
+ *\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.\r
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.\r
+ *\r
+ * @retval FALSE No useful interface.\r
+ * @retval TRUE Config message object success.\r
+ *\r
+ * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM.\r
+ * They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission.\r
+ */\r
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg)\r
+{\r
+ uint8_t u8MsgIfNum;\r
+\r
+ if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U)\r
+ {\r
+ return (int32_t)FALSE;\r
+ }\r
+\r
+ /* update the contents needed for transmission*/\r
+ tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |\r
+ CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;\r
+\r
+ if(pCanMsg->IdType == CAN_STD_ID)\r
+ {\r
+ /* standard ID*/\r
+ tCAN->IF[u8MsgIfNum].ARB1 = 0UL;\r
+ tCAN->IF[u8MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FFUL) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk;\r
+ }\r
+ else\r
+ {\r
+ /* extended ID*/\r
+ tCAN->IF[u8MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFFUL;\r
+ tCAN->IF[u8MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x1FFF0000UL) >> 16) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk;\r
+ }\r
+\r
+ if(pCanMsg->FrameType)\r
+ {\r
+ tCAN->IF[u8MsgIfNum].ARB2 |= CAN_IF_ARB2_DIR_Msk;\r
+ }\r
+ else\r
+ {\r
+ tCAN->IF[u8MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);\r
+ }\r
+\r
+\r
+ tCAN->IF[u8MsgIfNum].DAT_A1 = ((uint32_t)pCanMsg->Data[1] << 8) | (uint32_t)pCanMsg->Data[0];\r
+ tCAN->IF[u8MsgIfNum].DAT_A2 = ((uint32_t)pCanMsg->Data[3] << 8) | (uint32_t)pCanMsg->Data[2];\r
+ tCAN->IF[u8MsgIfNum].DAT_B1 = ((uint32_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4];\r
+ tCAN->IF[u8MsgIfNum].DAT_B2 = ((uint32_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6];\r
+\r
+ tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk;\r
+ tCAN->IF[u8MsgIfNum].CREQ = 1UL + u32MsgNum;\r
+\r
+ ReleaseIF(tCAN, (uint32_t)u8MsgIfNum);\r
+\r
+ return (int32_t)TRUE;\r
+}\r
+\r
+/**\r
+ * @brief Set transmit request bit.\r
+ *\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.\r
+ *\r
+ * @return TRUE: Start transmit message.\r
+ *\r
+ * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored.\r
+ */\r
+int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum)\r
+{\r
+ uint8_t u8MsgIfNum;\r
+\r
+ if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U)\r
+ {\r
+ return (int32_t)FALSE;\r
+ }\r
+\r
+ tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);\r
+\r
+ /* read the message contents*/\r
+ tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk\r
+ | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;\r
+\r
+ tCAN->IF[u8MsgIfNum].CREQ = 1UL + u32MsgNum;\r
+\r
+ while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)\r
+ {\r
+ /*Wait*/\r
+ }\r
+ tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;\r
+ tCAN->IF[u8MsgIfNum].CREQ = 1UL + u32MsgNum;\r
+\r
+ ReleaseIF(tCAN, (uint32_t)u8MsgIfNum);\r
+\r
+ return (int32_t)TRUE;\r
+}\r
+\r
+/**\r
+ * @brief Enable CAN interrupt.\r
+ *\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32Mask Interrupt Mask. Valid values are:\r
+ * - \ref CAN_CON_IE_Msk Module interrupt enable.\r
+ * - \ref CAN_CON_SIE_Msk Status change interrupt enable.\r
+ * - \ref CAN_CON_EIE_Msk Error interrupt enable.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The application software has two possibilities to follow the source of a message interrupt.\r
+ * First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register.\r
+ */\r
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask)\r
+{\r
+ tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) |\r
+ (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Disable CAN interrupt.\r
+ *\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk).\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.\r
+ */\r
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask)\r
+{\r
+ tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)));\r
+}\r
+\r
+\r
+/**\r
+ * @brief The function is used to configure a receive message object.\r
+ *\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.\r
+ * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:\r
+ * - \ref CAN_STD_ID The 11-bit identifier.\r
+ * - \ref CAN_EXT_ID The 29-bit identifier.\r
+ * @param[in] u32ID Specifies the identifier used for acceptance filtering.\r
+ *\r
+ * @retval FALSE No useful interface.\r
+ * @retval TRUE Configure a receive message object success.\r
+ *\r
+ * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])\r
+ * will be set when a received Data Frame is accepted and stored in the Message Object.\r
+ */\r
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID)\r
+{\r
+ uint32_t u32TimeOutCount = 0UL;\r
+\r
+ while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)TRUE) == (int32_t)FALSE)\r
+ {\r
+ if(++u32TimeOutCount >= RETRY_COUNTS)\r
+ {\r
+ return (int32_t)FALSE;\r
+ }\r
+ }\r
+\r
+ return (int32_t)TRUE;\r
+}\r
+\r
+/**\r
+ * @brief The function is used to configure a receive message object.\r
+ *\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.\r
+ * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:\r
+ * - \ref CAN_STD_ID The 11-bit identifier.\r
+ * - \ref CAN_EXT_ID The 29-bit identifier.\r
+ * @param[in] u32ID Specifies the identifier used for acceptance filtering.\r
+ * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering.\r
+ *\r
+ * @retval FALSE No useful interface.\r
+ * @retval TRUE Configure a receive message object success.\r
+ *\r
+ * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])\r
+ * will be set when a received Data Frame is accepted and stored in the Message Object.\r
+ */\r
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask)\r
+{\r
+ uint32_t u32TimeOutCount = 0UL;\r
+\r
+ while(CAN_SetRxMsgObjAndMsk(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, u32IDMask, (uint8_t)TRUE) == (int32_t)FALSE)\r
+ {\r
+ if(++u32TimeOutCount >= RETRY_COUNTS)\r
+ {\r
+ return (int32_t)FALSE;\r
+ }\r
+ }\r
+\r
+ return (int32_t)TRUE;\r
+}\r
+\r
+/**\r
+ * @brief The function is used to configure several receive message objects.\r
+ *\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31).\r
+ * @param[in] u32MsgCount the number of MSG RAM of the FIFO.\r
+ * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:\r
+ * - \ref CAN_STD_ID The 11-bit identifier.\r
+ * - \ref CAN_EXT_ID The 29-bit identifier.\r
+ * @param[in] u32ID Specifies the identifier used for acceptance filtering.\r
+ *\r
+ * @retval FALSE No useful interface.\r
+ * @retval TRUE Configure receive message objects success.\r
+ *\r
+ * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception\r
+ * and transmission by buffering the data to be transferred.\r
+ */\r
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID)\r
+{\r
+ uint32_t i = 0UL;\r
+ uint32_t u32TimeOutCount;\r
+ uint32_t u32EOB_Flag = 0UL;\r
+\r
+ for(i = 1UL; i < u32MsgCount; i++)\r
+ {\r
+ u32TimeOutCount = 0UL;\r
+\r
+ u32MsgNum += (i - 1UL);\r
+\r
+ if(i == u32MsgCount)\r
+ {\r
+ u32EOB_Flag = 1UL;\r
+ }\r
+\r
+ while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)u32EOB_Flag) == (int32_t)FALSE)\r
+ {\r
+ if(++u32TimeOutCount >= RETRY_COUNTS)\r
+ {\r
+ return (int32_t)FALSE;\r
+ }\r
+ }\r
+ }\r
+\r
+ return (int32_t)TRUE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Send CAN message.\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.\r
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.\r
+ *\r
+ * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n\r
+ * 2. When operation in normal mode: No useful interface. \n\r
+ * @retval TRUE Transmit Message success.\r
+ *\r
+ * @details The receive/transmit priority for the Message Objects is attached to the message number.\r
+ * Message Object 1 has the highest priority, while Message Object 32 has the lowest priority.\r
+ */\r
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg)\r
+{\r
+ uint32_t cond0, cond1;\r
+\r
+ cond0 = tCAN->CON & CAN_CON_TEST_Msk;\r
+ cond1 = tCAN->TEST & CAN_TEST_BASIC_Msk;\r
+ if(cond0 && cond1)\r
+ {\r
+ return (CAN_BasicSendMsg(tCAN, pCanMsg));\r
+ }\r
+ else\r
+ {\r
+ if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == (int32_t)FALSE)\r
+ {\r
+ return (int32_t)FALSE;\r
+ }\r
+ CAN_TriggerTxMsg(tCAN, u32MsgNum);\r
+ }\r
+\r
+ return (int32_t)TRUE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Gets the message, if received.\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.\r
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.\r
+ *\r
+ * @retval FALSE No any message received.\r
+ * @retval TRUE Receive Message success.\r
+ *\r
+ * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception\r
+ * and transmission by buffering the data to be transferred.\r
+ */\r
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg)\r
+{\r
+ uint32_t cond0, cond1;\r
+\r
+ cond0 = tCAN->CON & CAN_CON_TEST_Msk;\r
+ cond1 = tCAN->TEST & CAN_TEST_BASIC_Msk;\r
+\r
+ if(cond0 && cond1)\r
+ {\r
+ return (CAN_BasicReceiveMsg(tCAN, pCanMsg));\r
+ }\r
+ else\r
+ {\r
+ return CAN_ReadMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)TRUE, pCanMsg);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Clear interrupt pending bit.\r
+ * @param[in] tCAN The pointer to CAN module base address.\r
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details An interrupt remains pending until the application software has cleared it.\r
+ */\r
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum)\r
+{\r
+ uint32_t u32MsgIfNum;\r
+\r
+ if((u32MsgIfNum = LockIF_TL(tCAN)) == 2UL)\r
+ {\r
+ u32MsgIfNum = 0UL;\r
+ }\r
+\r
+ tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;\r
+ tCAN->IF[u32MsgIfNum].CREQ = 1UL + u32MsgNum;\r
+\r
+ ReleaseIF(tCAN, u32MsgIfNum);\r
+}\r
+\r
+/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group CAN_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file clk.c\r
+ * @version V3.00\r
+ * @brief M2351 series Clock Controller (CLK) driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#include "NuMicro.h"\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CLK_Driver CLK Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions\r
+ @{\r
+*/\r
+\r
+\r
+/**\r
+ * @brief Disable frequency output function\r
+ * @param None\r
+ * @return None\r
+ * @details This function disable frequency output function.\r
+ */\r
+void CLK_DisableCKO(void)\r
+{\r
+ /* Disable CKO clock source */\r
+ CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk);\r
+}\r
+\r
+\r
+/**\r
+ * @brief This function enable frequency divider module clock.\r
+ * enable frequency divider clock function and configure frequency divider.\r
+ * @param[in] u32ClkSrc is frequency divider function clock source. Including :\r
+ * - \ref CLK_CLKSEL1_CLKOSEL_HXT\r
+ * - \ref CLK_CLKSEL1_CLKOSEL_LXT\r
+ * - \ref CLK_CLKSEL1_CLKOSEL_HCLK\r
+ * - \ref CLK_CLKSEL1_CLKOSEL_HIRC\r
+ * @param[in] u32ClkDiv is divider output frequency selection.\r
+ * @param[in] u32ClkDivBy1En is frequency divided by one enable.\r
+ * @return None\r
+ *\r
+ * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.\r
+ * The formula is:\r
+ * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)\r
+ * This function is just used to set CKO clock.\r
+ * User must enable I/O for CKO clock output pin by themselves.\r
+ */\r
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)\r
+{\r
+ /* CKO = clock source / 2^(u32ClkDiv + 1) */\r
+ CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);\r
+\r
+ /* Enable CKO clock source */\r
+ CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk;\r
+\r
+ /* Select CKO clock source */\r
+ CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | (u32ClkSrc);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enter to Power-down mode\r
+ * @param None\r
+ * @return None\r
+ * @details This function is used to let system enter to Power-down mode. \n\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void CLK_PowerDown(void)\r
+{\r
+ /* Set the processor uses deep sleep as its low power mode */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+\r
+ /* Set system Power-down enabled*/\r
+ CLK->PWRCTL |= CLK_PWRCTL_PDEN_Msk;\r
+\r
+ /* Chip enter Power-down mode after CPU run WFI instruction */\r
+ __WFI();\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Enter to Idle mode\r
+ * @param None\r
+ * @return None\r
+ * @details This function let system enter to Idle mode. \n\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void CLK_Idle(void)\r
+{\r
+ /* Set the processor uses sleep as its low power mode */\r
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;\r
+\r
+ /* Set chip in idle mode because of WFI command */\r
+ CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;\r
+\r
+ /* Chip enter idle mode after CPU run WFI instruction */\r
+ __WFI();\r
+}\r
+\r
+\r
+/**\r
+ * @brief Get external high speed crystal clock frequency\r
+ * @param None\r
+ * @return External high frequency crystal frequency\r
+ * @details This function get external high frequency crystal frequency. The frequency unit is Hz.\r
+ */\r
+__NONSECURE_ENTRY_WEAK\r
+uint32_t CLK_GetHXTFreq(void)\r
+{\r
+ uint32_t u32Freq = 0UL;\r
+ uint32_t u32HXTEN = CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk;\r
+\r
+ if(u32HXTEN)\r
+ {\r
+ u32Freq = __HXT;\r
+ }\r
+ else\r
+ {\r
+ u32Freq = 0UL;\r
+ }\r
+\r
+ return u32Freq;\r
+}\r
+\r
+/**\r
+ * @brief Get external low speed crystal clock frequency\r
+ * @param None\r
+ * @return External low speed crystal clock frequency\r
+ * @details This function get external low frequency crystal frequency. The frequency unit is Hz.\r
+ */\r
+\r
+__NONSECURE_ENTRY_WEAK\r
+uint32_t CLK_GetLXTFreq(void)\r
+{\r
+ uint32_t u32Freq = 0UL;\r
+ uint32_t u32LXTEN = CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk;\r
+\r
+ if(u32LXTEN)\r
+ {\r
+ u32Freq = __LXT;\r
+ }\r
+ else\r
+ {\r
+ u32Freq = 0UL;\r
+ }\r
+\r
+ return u32Freq;\r
+}\r
+\r
+/**\r
+ * @brief Get HCLK frequency\r
+ * @param None\r
+ * @return HCLK frequency\r
+ * @details This function get HCLK frequency. The frequency unit is Hz.\r
+ */\r
+\r
+__NONSECURE_ENTRY_WEAK\r
+uint32_t CLK_GetHCLKFreq(void)\r
+{\r
+ SystemCoreClockUpdate();\r
+ return SystemCoreClock;\r
+}\r
+\r
+/**\r
+ * @brief Get PCLK0 frequency\r
+ * @param None\r
+ * @return PCLK0 frequency\r
+ * @details This function get PCLK0 frequency. The frequency unit is Hz.\r
+ */\r
+\r
+__NONSECURE_ENTRY_WEAK\r
+uint32_t CLK_GetPCLK0Freq(void)\r
+{\r
+ SystemCoreClockUpdate();\r
+ return (SystemCoreClock >> ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) >> CLK_PCLKDIV_APB0DIV_Pos));\r
+}\r
+\r
+/**\r
+ * @brief Get PCLK1 frequency\r
+ * @param None\r
+ * @return PCLK1 frequency\r
+ * @details This function get PCLK1 frequency. The frequency unit is Hz.\r
+ */\r
+\r
+__NONSECURE_ENTRY_WEAK\r
+uint32_t CLK_GetPCLK1Freq(void)\r
+{\r
+ SystemCoreClockUpdate();\r
+ return (SystemCoreClock >> ((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) >> CLK_PCLKDIV_APB1DIV_Pos));\r
+}\r
+\r
+/**\r
+ * @brief Get CPU frequency\r
+ * @param None\r
+ * @return CPU frequency\r
+ * @details This function get CPU frequency. The frequency unit is Hz.\r
+ */\r
+\r
+__NONSECURE_ENTRY_WEAK\r
+uint32_t CLK_GetCPUFreq(void)\r
+{\r
+ uint32_t u32Freq, u32HclkSrc, u32HclkDiv;\r
+ uint32_t au32ClkTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, __HIRC48, 0UL, __HIRC};\r
+ uint32_t u32PllReg, u32FIN, u32NF, u32NR, u32NO;\r
+ uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};\r
+ uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk;\r
+\r
+ /* Update PLL Clock */\r
+ u32PllReg = CLK->PLLCTL;\r
+\r
+ if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))\r
+ {\r
+ PllClock = 0UL; /* PLL is in power down mode or fix low */\r
+ }\r
+ else /* PLL is in normal mode */\r
+ {\r
+\r
+ /* PLL source clock */\r
+ if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk)\r
+ {\r
+ u32FIN = __HIRC; /* PLL source clock from HIRC */\r
+ }\r
+ else\r
+ {\r
+ u32FIN = __HXT; /* PLL source clock from HXT */\r
+ }\r
+\r
+ /* Calculate PLL frequency */\r
+ if(u32PllReg & CLK_PLLCTL_BP_Msk)\r
+ {\r
+ PllClock = u32FIN; /* PLL is in bypass mode */\r
+ }\r
+ else\r
+ {\r
+ /* PLL is output enabled in normal work mode */\r
+ u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];\r
+ u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;\r
+ u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;\r
+\r
+ /* u32FIN is shifted 2 bits to avoid overflow */\r
+ PllClock = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2);\r
+ }\r
+ }\r
+\r
+ /* HCLK clock source */\r
+ u32HclkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;\r
+\r
+ if(u32HclkSrc == CLK_CLKSEL0_HCLKSEL_LXT)\r
+ {\r
+\r
+ if(u32RTCCKEN == 0UL)\r
+ {\r
+ CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */\r
+ }\r
+\r
+ if(RTC->LXTCTL & RTC_LXTCTL_C32KS_Msk)\r
+ {\r
+ u32Freq = __LIRC32; /* LXT clock source is LIRC32 */\r
+ }\r
+ else\r
+ {\r
+ u32Freq = __LXT; /* LXT clock source is external LXT */\r
+ }\r
+\r
+ if(u32RTCCKEN == 0UL)\r
+ {\r
+ CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */\r
+ }\r
+\r
+ }\r
+ else if(u32HclkSrc == CLK_CLKSEL0_HCLKSEL_PLL)\r
+ {\r
+ u32Freq = PllClock;/* Use PLL clock */\r
+ }\r
+ else\r
+ {\r
+ u32Freq = au32ClkTbl[u32HclkSrc]; /* Use the clock sources directly */\r
+ }\r
+\r
+ /* HCLK clock source divider */\r
+ u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;\r
+\r
+ /* Update System Core Clock */\r
+ SystemCoreClock = u32Freq / u32HclkDiv;\r
+\r
+ /* Update Cycles per micro second */\r
+ CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;\r
+\r
+ return SystemCoreClock;\r
+}\r
+\r
+/**\r
+ * @brief Set HCLK frequency\r
+ * @param[in] u32Hclk is HCLK frequency.\r
+ * The range of u32Hclk is 24 MHz ~ 64 MHz if power level is PL0.\r
+ * The range of u32Hclk is 24 MHz ~ 48 MHz if power level is PL1.\r
+ * @return HCLK frequency\r
+ * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk)\r
+{\r
+ uint32_t u32HIRCSTB, u32PLSTATUS;\r
+\r
+ /* Read HIRC clock source stable flag */\r
+ u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;\r
+\r
+ /* Read power level status */\r
+ u32PLSTATUS = SYS->PLSTS & SYS_PLSTS_PLSTATUS_Msk;\r
+\r
+ /* Check HCLK frequency range */\r
+ if((u32PLSTATUS == SYS_PLSTS_PLSTATUS_PL0) && (u32Hclk > FREQ_64MHZ))\r
+ {\r
+ u32Hclk = FREQ_64MHZ;\r
+ }\r
+ else if((u32PLSTATUS == SYS_PLSTS_PLSTATUS_PL1) && (u32Hclk > FREQ_48MHZ))\r
+ {\r
+ u32Hclk = FREQ_48MHZ;\r
+ }\r
+ else if(u32Hclk < FREQ_24MHZ)\r
+ {\r
+ u32Hclk = FREQ_24MHZ;\r
+ }\r
+\r
+ /* Switch HCLK clock source to HIRC clock for safe */\r
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;\r
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);\r
+ CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;\r
+ CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);\r
+\r
+ /* Enable Flash access cycle auto-tuning function */\r
+ FMC->CYCCTL &= (~FMC_CYCCTL_FADIS_Msk);\r
+\r
+ /* Configure PLL setting if HXT clock is stable */\r
+ if(CLK->STATUS & CLK_STATUS_HXTSTB_Msk)\r
+ {\r
+ u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk);\r
+ }\r
+ /* Configure PLL setting if HXT clock is not stable */\r
+ else\r
+ {\r
+ u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk);\r
+\r
+ /* Read HIRC clock source stable flag */\r
+ u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;\r
+ }\r
+\r
+ /* Select HCLK clock source to PLL,\r
+ Select HCLK clock source divider as 1\r
+ and update system core clock\r
+ */\r
+ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL));\r
+\r
+ /* Disable HIRC if HIRC is disabled before setting core clock */\r
+ if(u32HIRCSTB == 0UL)\r
+ {\r
+ CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;\r
+ }\r
+\r
+ /* Return actually HCLK frequency is PLL frequency divide 1 */\r
+ return u32Hclk;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set HCLK clock source and HCLK clock divider\r
+ * @param[in] u32ClkSrc is HCLK clock source. Including :\r
+ * - \ref CLK_CLKSEL0_HCLKSEL_HXT\r
+ * - \ref CLK_CLKSEL0_HCLKSEL_LXT\r
+ * - \ref CLK_CLKSEL0_HCLKSEL_PLL\r
+ * - \ref CLK_CLKSEL0_HCLKSEL_LIRC\r
+ * - \ref CLK_CLKSEL0_HCLKSEL_HIRC48\r
+ * - \ref CLK_CLKSEL0_HCLKSEL_HIRC\r
+ * @param[in] u32ClkDiv is HCLK clock divider. Including :\r
+ * - \ref CLK_CLKDIV0_HCLK(x)\r
+ * @return None\r
+ * @details This function set HCLK clock source and HCLK clock divider.\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)\r
+{\r
+ uint32_t u32HIRCSTB;\r
+\r
+ /* Read HIRC clock source stable flag */\r
+ u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;\r
+\r
+ /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */\r
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;\r
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);\r
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;\r
+\r
+ /* Enable Flash access cycle auto-tuning function */\r
+ FMC->CYCCTL &= (~FMC_CYCCTL_FADIS_Msk);\r
+\r
+ /* Apply new Divider */\r
+ CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;\r
+\r
+ /* Disable Flash access cycle auto-tuning function and set Flash access cycle if HCLK switches to HIRC48 */\r
+ if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_HIRC48)\r
+ {\r
+ FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | FMC_CYCCTL_FADIS_Msk | (3UL);\r
+ }\r
+\r
+ /* Switch HCLK to new HCLK source */\r
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;\r
+\r
+ /* Update System Core Clock */\r
+ SystemCoreClockUpdate();\r
+\r
+ /* Disable HIRC if HIRC is disabled before switching HCLK source */\r
+ if(u32HIRCSTB == 0UL)\r
+ {\r
+ CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;\r
+ }\r
+}\r
+/**\r
+ * @brief This function set selected module clock source and module clock divider\r
+ * @param[in] u32ModuleIdx is module index.\r
+ * @param[in] u32ClkSrc is module clock source.\r
+ * @param[in] u32ClkDiv is module clock divider.\r
+ * @return None\r
+ * @details Valid parameter combinations listed in following table:\r
+ *\r
+ * |Module index |Clock source |Divider |\r
+ * | :---------------- | :----------------------------------- | :----------------------- |\r
+ * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HXT |\ref CLK_CLKDIV0_SDH0(x) |\r
+ * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_PLL |\ref CLK_CLKDIV0_SDH0(x) |\r
+ * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HCLK |\ref CLK_CLKDIV0_SDH0(x) |\r
+ * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HIRC |\ref CLK_CLKDIV0_SDH0(x) |\r
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |\r
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x |\r
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |\r
+ * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) |\r
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |\r
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |\r
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x |\r
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT_TRG | x |\r
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |\r
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |\r
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x |\r
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x |\r
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x |\r
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT_TRG | x |\r
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |\r
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |\r
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x |\r
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x |\r
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x |\r
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT_TRG | x |\r
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x |\r
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x |\r
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x |\r
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x |\r
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x |\r
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT_TRG | x |\r
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x |\r
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x |\r
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) |\r
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PLL |\ref CLK_CLKDIV0_UART0(x) |\r
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) |\r
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) |\r
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) |\r
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PLL |\ref CLK_CLKDIV0_UART1(x) |\r
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) |\r
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) |\r
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) |\r
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PLL |\ref CLK_CLKDIV4_UART2(x) |\r
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) |\r
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) |\r
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) |\r
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_PLL |\ref CLK_CLKDIV4_UART3(x) |\r
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) |\r
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) |\r
+ * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) |\r
+ * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL |\ref CLK_CLKDIV4_UART4(x) |\r
+ * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) |\r
+ * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) |\r
+ * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) |\r
+ * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL |\ref CLK_CLKDIV4_UART5(x) |\r
+ * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) |\r
+ * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) |\r
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x |\r
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x |\r
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x |\r
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x |\r
+ * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x |\r
+ * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x |\r
+ * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LXT | x |\r
+ * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LIRC | x |\r
+ * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT | x |\r
+ * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL | x |\r
+ * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PCLK0 | x |\r
+ * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC | x |\r
+ * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x |\r
+ * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL | x |\r
+ * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x |\r
+ * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x |\r
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x |\r
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x |\r
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x |\r
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x |\r
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x |\r
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x |\r
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK0 | x |\r
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x |\r
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x |\r
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x |\r
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK1 | x |\r
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x |\r
+ * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HXT | x |\r
+ * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PLL | x |\r
+ * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PCLK0 | x |\r
+ * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HIRC | x |\r
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) |\r
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) |\r
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) |\r
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) |\r
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) |\r
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) |\r
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK1 |\ref CLK_CLKDIV1_SC1(x) |\r
+ * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) |\r
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) |\r
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) |\r
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) |\r
+ * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) |\r
+ * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) |\r
+ * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) |\r
+ * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) |\r
+ * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) |\r
+ * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) |\r
+ * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) |\r
+ */\r
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)\r
+{\r
+ uint32_t u32Sel = 0UL, u32Div = 0UL;\r
+ uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL};\r
+ uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL};\r
+\r
+ if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)\r
+ {\r
+ /* Get clock divider control register address */\r
+ u32Div = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);\r
+ /* Apply new divider */\r
+ M32(u32Div) = (M32(u32Div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;\r
+ }\r
+\r
+ if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)\r
+ {\r
+ /* Get clock select control register address */\r
+ u32Sel = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);\r
+ /* Set new clock selection setting */\r
+ M32(u32Sel) = (M32(u32Sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set SysTick clock source\r
+ * @param[in] u32ClkSrc is module clock source. Including:\r
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT\r
+ * - \ref CLK_CLKSEL0_STCLKSEL_LXT\r
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2\r
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2\r
+ * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2\r
+ * @return None\r
+ * @details This function set SysTick clock source. \n\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)\r
+{\r
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;\r
+}\r
+\r
+/**\r
+ * @brief Enable clock source\r
+ * @param[in] u32ClkMask is clock source mask. Including :\r
+ * - \ref CLK_PWRCTL_HXTEN_Msk\r
+ * - \ref CLK_PWRCTL_LXTEN_Msk\r
+ * - \ref CLK_PWRCTL_HIRCEN_Msk\r
+ * - \ref CLK_PWRCTL_LIRCEN_Msk\r
+ * - \ref CLK_PWRCTL_HIRC48EN_Msk\r
+ * @return None\r
+ * @details This function enable clock source. \n\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void CLK_EnableXtalRC(uint32_t u32ClkMask)\r
+{\r
+ CLK->PWRCTL |= u32ClkMask;\r
+}\r
+\r
+/**\r
+ * @brief Disable clock source\r
+ * @param[in] u32ClkMask is clock source mask. Including :\r
+ * - \ref CLK_PWRCTL_HXTEN_Msk\r
+ * - \ref CLK_PWRCTL_LXTEN_Msk\r
+ * - \ref CLK_PWRCTL_HIRCEN_Msk\r
+ * - \ref CLK_PWRCTL_LIRCEN_Msk\r
+ * - \ref CLK_PWRCTL_HIRC48EN_Msk\r
+ * @return None\r
+ * @details This function disable clock source. \n\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void CLK_DisableXtalRC(uint32_t u32ClkMask)\r
+{\r
+ CLK->PWRCTL &= ~u32ClkMask;\r
+}\r
+\r
+/**\r
+ * @brief This function enable module clock\r
+ * @param[in] u32ModuleIdx is module index. Including :\r
+ * - \ref PDMA0_MODULE\r
+ * - \ref PDMA1_MODULE\r
+ * - \ref ISP_MODULE\r
+ * - \ref EBI_MODULE\r
+ * - \ref SDH0_MODULE\r
+ * - \ref CRC_MODULE\r
+ * - \ref CRPT_MODULE\r
+ * - \ref USBH_MODULE\r
+ * - \ref WDT_MODULE\r
+ * - \ref WWDT_MODULE\r
+ * - \ref RTC_MODULE\r
+ * - \ref TMR0_MODULE\r
+ * - \ref TMR1_MODULE\r
+ * - \ref TMR2_MODULE\r
+ * - \ref TMR3_MODULE\r
+ * - \ref CLKO_MODULE\r
+ * - \ref ACMP01_MODULE\r
+ * - \ref I2C0_MODULE\r
+ * - \ref I2C1_MODULE\r
+ * - \ref I2C2_MODULE\r
+ * - \ref QSPI0_MODULE\r
+ * - \ref SPI0_MODULE\r
+ * - \ref SPI1_MODULE\r
+ * - \ref SPI2_MODULE\r
+ * - \ref SPI3_MODULE\r
+ * - \ref UART0_MODULE\r
+ * - \ref UART1_MODULE\r
+ * - \ref UART2_MODULE\r
+ * - \ref UART3_MODULE\r
+ * - \ref UART4_MODULE\r
+ * - \ref UART5_MODULE\r
+ * - \ref CAN0_MODULE\r
+ * - \ref OTG_MODULE\r
+ * - \ref USBD_MODULE\r
+ * - \ref EADC_MODULE\r
+ * - \ref I2S0_MODULE\r
+ * - \ref SC0_MODULE\r
+ * - \ref SC1_MODULE\r
+ * - \ref SC2_MODULE\r
+ * - \ref USCI0_MODULE\r
+ * - \ref USCI1_MODULE\r
+ * - \ref DAC_MODULE\r
+ * - \ref EPWM0_MODULE\r
+ * - \ref EPWM1_MODULE\r
+ * - \ref BPWM0_MODULE\r
+ * - \ref BPWM1_MODULE\r
+ * - \ref QEI0_MODULE\r
+ * - \ref QEI1_MODULE\r
+ * - \ref QEI0_MODULE\r
+ * - \ref TRNG_MODULE\r
+ * - \ref ECAP0_MODULE\r
+ * - \ref ECAP1_MODULE\r
+ * @return None\r
+ * @details This function enable module clock.\r
+ */\r
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx)\r
+{\r
+ uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;\r
+\r
+ u32TmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx));\r
+ u32TmpAddr = (uint32_t)&CLK->AHBCLK;\r
+ u32TmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));\r
+\r
+ *(volatile uint32_t *)u32TmpAddr |= u32TmpVal;\r
+}\r
+\r
+/**\r
+ * @brief This function disable module clock\r
+ * @param[in] u32ModuleIdx is module index\r
+ * - \ref PDMA0_MODULE\r
+ * - \ref PDMA1_MODULE\r
+ * - \ref ISP_MODULE\r
+ * - \ref EBI_MODULE\r
+ * - \ref SDH0_MODULE\r
+ * - \ref CRC_MODULE\r
+ * - \ref CRPT_MODULE\r
+ * - \ref USBH_MODULE\r
+ * - \ref WDT_MODULE\r
+ * - \ref WWDT_MODULE\r
+ * - \ref RTC_MODULE\r
+ * - \ref TMR0_MODULE\r
+ * - \ref TMR1_MODULE\r
+ * - \ref TMR2_MODULE\r
+ * - \ref TMR3_MODULE\r
+ * - \ref CLKO_MODULE\r
+ * - \ref ACMP01_MODULE\r
+ * - \ref I2C0_MODULE\r
+ * - \ref I2C1_MODULE\r
+ * - \ref I2C2_MODULE\r
+ * - \ref QSPI0_MODULE\r
+ * - \ref SPI0_MODULE\r
+ * - \ref SPI1_MODULE\r
+ * - \ref SPI2_MODULE\r
+ * - \ref SPI3_MODULE\r
+ * - \ref UART0_MODULE\r
+ * - \ref UART1_MODULE\r
+ * - \ref UART2_MODULE\r
+ * - \ref UART3_MODULE\r
+ * - \ref UART4_MODULE\r
+ * - \ref UART5_MODULE\r
+ * - \ref CAN0_MODULE\r
+ * - \ref OTG_MODULE\r
+ * - \ref USBD_MODULE\r
+ * - \ref EADC_MODULE\r
+ * - \ref I2S0_MODULE\r
+ * - \ref SC0_MODULE\r
+ * - \ref SC1_MODULE\r
+ * - \ref SC2_MODULE\r
+ * - \ref USCI0_MODULE\r
+ * - \ref USCI1_MODULE\r
+ * - \ref DAC_MODULE\r
+ * - \ref EPWM0_MODULE\r
+ * - \ref EPWM1_MODULE\r
+ * - \ref BPWM0_MODULE\r
+ * - \ref BPWM1_MODULE\r
+ * - \ref QEI0_MODULE\r
+ * - \ref QEI1_MODULE\r
+ * - \ref QEI0_MODULE\r
+ * - \ref TRNG_MODULE\r
+ * - \ref ECAP0_MODULE\r
+ * - \ref ECAP1_MODULE\r
+ * @return None\r
+ * @details This function disable module clock.\r
+ */\r
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx)\r
+{\r
+ uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;\r
+\r
+ u32TmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx));\r
+ u32TmpAddr = (uint32_t)&CLK->AHBCLK;\r
+ u32TmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));\r
+\r
+ *(uint32_t *)u32TmpAddr &= u32TmpVal;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set PLL frequency\r
+ * @param[in] u32PllClkSrc is PLL clock source. Including :\r
+ * - \ref CLK_PLLCTL_PLLSRC_HXT\r
+ * - \ref CLK_PLLCTL_PLLSRC_HIRC\r
+ * @param[in] u32PllFreq is PLL frequency. The range of u32PllFreq is 24 MHz ~ 144 MHz.\r
+ * @return PLL frequency\r
+ * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)\r
+{\r
+ uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32PllClk;\r
+ uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;\r
+\r
+ /* Disable PLL first to avoid unstable when setting PLL */\r
+ CLK_DisablePLL();\r
+\r
+ /* PLL source clock is from HXT */\r
+ if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)\r
+ {\r
+\r
+ /* Enable HXT clock */\r
+ CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;\r
+\r
+ /* Wait for HXT clock ready */\r
+ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);\r
+\r
+ /* Select PLL source clock from HXT */\r
+ u32PllSrcClk = __HXT;\r
+ }\r
+\r
+ /* PLL source clock is from HIRC */\r
+ else\r
+ {\r
+\r
+ /* Enable HIRC clock */\r
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;\r
+\r
+ /* Wait for HIRC clock ready */\r
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);\r
+\r
+ /* Select PLL source clock from HIRC */\r
+ u32PllSrcClk = __HIRC;\r
+ }\r
+\r
+ /* Check PLL frequency range */\r
+ if((u32PllFreq <= FREQ_144MHZ) && (u32PllFreq >= FREQ_24MHZ))\r
+ {\r
+\r
+ /* Select "NO" according to request frequency */\r
+ if((u32PllFreq < FREQ_48MHZ) && (u32PllFreq >= FREQ_24MHZ))\r
+ {\r
+ u32NO = 3UL;\r
+ u32PllFreq = u32PllFreq << 2;\r
+ }\r
+ else if((u32PllFreq < FREQ_96MHZ) && (u32PllFreq >= FREQ_48MHZ))\r
+ {\r
+ u32NO = 1UL;\r
+ u32PllFreq = u32PllFreq << 1;\r
+ }\r
+ else\r
+ {\r
+ u32NO = 0UL;\r
+ }\r
+\r
+ /* u32NR start from 3 to avoid calculation overflow */\r
+ u32NR = 3UL;\r
+\r
+ /* Find best solution */\r
+ u32Min = (uint32_t) - 1;\r
+ u32MinNR = 0UL;\r
+ u32MinNF = 0UL;\r
+\r
+ for(; u32NR <= 32UL; u32NR++)\r
+ {\r
+ u32Tmp = u32PllSrcClk / u32NR;\r
+ if((u32Tmp >= FREQ_2MHZ) && (u32Tmp <= FREQ_8MHZ))\r
+ {\r
+ for(u32NF = 2UL; u32NF <= 513UL; u32NF++)\r
+ {\r
+ u32Tmp2 = (u32Tmp * u32NF) << 1;\r
+ if((u32Tmp2 >= FREQ_96MHZ) && (u32Tmp2 <= FREQ_200MHZ))\r
+ {\r
+ u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;\r
+ if(u32Tmp3 < u32Min)\r
+ {\r
+ u32Min = u32Tmp3;\r
+ u32MinNR = u32NR;\r
+ u32MinNF = u32NF;\r
+\r
+ /* Break when get good results */\r
+ if(u32Min == 0UL)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Enable and apply new PLL setting. */\r
+ CLK->PLLCTL = u32PllClkSrc | (u32NO << 14) | ((u32MinNR - 1UL) << 9) | (u32MinNF - 2UL);\r
+\r
+ /* Actual PLL output clock frequency */\r
+ u32PllClk = u32PllSrcClk / ((u32NO + 1UL) * u32MinNR) * (u32MinNF << 1);\r
+\r
+ }\r
+ else\r
+ {\r
+\r
+ /* Wrong frequency request. Just return default setting. */\r
+ if((SYS->PLSTS & SYS_PLSTS_PLSTATUS_Msk) == SYS_PLCTL_PLSEL_PL0)\r
+ {\r
+\r
+ /* Apply default PLL setting and return */\r
+ CLK->PLLCTL = u32PllClkSrc | CLK_PLLCTL_64MHz_HXT;\r
+\r
+ /* Actual PLL output clock frequency */\r
+ u32PllClk = FREQ_64MHZ;\r
+\r
+ }\r
+ else\r
+ {\r
+\r
+ /* Apply default PLL setting and return */\r
+ CLK->PLLCTL = u32PllClkSrc | CLK_PLLCTL_48MHz_HXT;\r
+\r
+ /* Actual PLL output clock frequency */\r
+ u32PllClk = FREQ_48MHZ;\r
+ }\r
+\r
+ }\r
+\r
+ /* Wait for PLL clock stable */\r
+ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);\r
+\r
+ /* Return actual PLL output clock frequency */\r
+ return u32PllClk;\r
+}\r
+\r
+/**\r
+ * @brief Disable PLL\r
+ * @param None\r
+ * @return None\r
+ * @details This function set PLL in Power-down mode. \n\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void CLK_DisablePLL(void)\r
+{\r
+ CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;\r
+}\r
+\r
+/**\r
+ * @brief This function check selected clock source status\r
+ * @param[in] u32ClkMask is selected clock source. Including :\r
+ * - \ref CLK_STATUS_HXTSTB_Msk\r
+ * - \ref CLK_STATUS_LXTSTB_Msk\r
+ * - \ref CLK_STATUS_HIRCSTB_Msk\r
+ * - \ref CLK_STATUS_LIRCSTB_Msk\r
+ * - \ref CLK_STATUS_PLLSTB_Msk\r
+ * - \ref CLK_STATUS_HIRC48STB_Msk\r
+ * - \ref CLK_STATUS_EXTLXTSTB_Msk\r
+ * - \ref CLK_STATUS_LIRC32STB_Msk\r
+ * @retval 0 clock is not stable\r
+ * @retval 1 clock is stable\r
+ * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms)\r
+ */\r
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)\r
+{\r
+ int32_t i32TimeOutCnt = 2400000;\r
+ uint32_t u32Ret = 1U;\r
+\r
+ while((CLK->STATUS & u32ClkMask) != u32ClkMask)\r
+ {\r
+ if(i32TimeOutCnt-- <= 0)\r
+ {\r
+ u32Ret = 0U;\r
+ break;\r
+ }\r
+ }\r
+ return u32Ret;\r
+}\r
+\r
+/**\r
+ * @brief Enable System Tick counter\r
+ * @param[in] u32ClkSrc is System Tick clock source. Including:\r
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT\r
+ * - \ref CLK_CLKSEL0_STCLKSEL_LXT\r
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2\r
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2\r
+ * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2\r
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK\r
+ * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF.\r
+ * @return None\r
+ * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)\r
+{\r
+ /* Set System Tick counter disabled */\r
+ SysTick->CTRL = 0UL;\r
+\r
+ /* Set System Tick clock source */\r
+ if(u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK)\r
+ {\r
+ SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;\r
+ }\r
+ else\r
+ {\r
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;\r
+ }\r
+\r
+ /* Set System Tick reload value */\r
+ SysTick->LOAD = u32Count;\r
+\r
+ /* Clear System Tick current value and counter flag */\r
+ SysTick->VAL = 0UL;\r
+\r
+ /* Set System Tick interrupt enabled and counter enabled */\r
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable System Tick counter\r
+ * @param None\r
+ * @return None\r
+ * @details This function disable System Tick counter.\r
+ */\r
+void CLK_DisableSysTick(void)\r
+{\r
+ /* Set System Tick counter disabled */\r
+ SysTick->CTRL = 0UL;\r
+}\r
+\r
+/**\r
+ * @brief Power-down mode selected\r
+ * @param[in] u32PDMode is power down mode index. Including :\r
+ * - \ref CLK_PMUCTL_PDMSEL_PD\r
+ * - \ref CLK_PMUCTL_PDMSEL_LLPD\r
+ * - \ref CLK_PMUCTL_PDMSEL_FWPD\r
+ * - \ref CLK_PMUCTL_PDMSEL_ULLPD\r
+ * - \ref CLK_PMUCTL_PDMSEL_SPD\r
+ * - \ref CLK_PMUCTL_PDMSEL_DPD\r
+ * @return None\r
+ * @details This function is used to set power-down mode.\r
+ */\r
+void CLK_SetPowerDownMode(uint32_t u32PDMode)\r
+{\r
+ CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_PDMSEL_Msk)) | (u32PDMode);\r
+}\r
+\r
+/**\r
+ * @brief Set Wake-up pin trigger type at Deep Power down mode\r
+ * @param[in] u32TriggerType Wake-up pin trigger type\r
+ * - \ref CLK_DPDWKPIN_RISING\r
+ * - \ref CLK_DPDWKPIN_FALLING\r
+ * - \ref CLK_DPDWKPIN_BOTHEDGE\r
+ * @return None\r
+ * @details This function is used to enable Wake-up pin trigger type.\r
+ */\r
+\r
+void CLK_EnableDPDWKPin(uint32_t u32TriggerType)\r
+{\r
+ CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_WKPINEN_Msk)) | (u32TriggerType);\r
+}\r
+\r
+/**\r
+ * @brief Get power manager wake up source\r
+ * @param[in] None\r
+ * @return None\r
+ * @details This function get power manager wake up source.\r
+ */\r
+\r
+uint32_t CLK_GetPMUWKSrc(void)\r
+{\r
+ return (CLK->PMUSTS);\r
+}\r
+\r
+/**\r
+ * @brief Set specified GPIO as wake up source at Standby Power-down mode\r
+ * @param[in] u32Port GPIO port. It could be 0~3.\r
+ * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15.\r
+ * @param[in] u32TriggerType Wake-up pin trigger type\r
+ * - \ref CLK_SPDWKPIN_RISING\r
+ * - \ref CLK_SPDWKPIN_FALLING\r
+ * @param[in] u32DebounceEn Standby Power-down mode wake-up pin de-bounce function\r
+ * - \ref CLK_SPDWKPIN_DEBOUNCEEN\r
+ * - \ref CLK_SPDWKPIN_DEBOUNCEDIS\r
+ * @return None\r
+ * @details This function is used to set specified GPIO as wake up source at Standby Power-down mode.\r
+ */\r
+\r
+void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)\r
+{\r
+ uint32_t u32TmpAddr = 0UL;\r
+ uint32_t u32TmpVal = 0UL;\r
+\r
+ /* GPx Stand-by Power-down Wake-up Pin Select */\r
+ u32TmpAddr = (uint32_t)&CLK->PASWKCTL;\r
+ u32TmpAddr += (0x4UL * u32Port);\r
+\r
+ u32TmpVal = inpw((uint32_t *)u32TmpAddr);\r
+ u32TmpVal = (u32TmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) |\r
+ (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE;\r
+ outpw((uint32_t *)u32TmpAddr, u32TmpVal);\r
+}\r
+\r
+/**\r
+ * @brief Get PLL clock frequency\r
+ * @param None\r
+ * @return PLL frequency\r
+ * @details This function get PLL frequency. The frequency unit is Hz.\r
+ */\r
+\r
+__NONSECURE_ENTRY_WEAK\r
+uint32_t CLK_GetPLLClockFreq(void)\r
+{\r
+ uint32_t u32PllFreq = 0UL, u32PllReg;\r
+ uint32_t u32FIN, u32NF, u32NR, u32NO;\r
+ uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};\r
+\r
+ u32PllReg = CLK->PLLCTL;\r
+\r
+ if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))\r
+ {\r
+ u32PllFreq = 0UL; /* PLL is in power down mode or fix low */\r
+ }\r
+ else /* PLL is in normal mode */\r
+ {\r
+\r
+ /* PLL source clock */\r
+ if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk)\r
+ {\r
+ u32FIN = __HIRC; /* PLL source clock from HIRC */\r
+ }\r
+ else\r
+ {\r
+ u32FIN = __HXT; /* PLL source clock from HXT */\r
+ }\r
+\r
+ /* Calculate PLL frequency */\r
+ if(u32PllReg & CLK_PLLCTL_BP_Msk)\r
+ {\r
+ u32PllFreq = u32FIN; /* PLL is in bypass mode */\r
+ }\r
+ else\r
+ {\r
+ /* PLL is output enabled in normal work mode */\r
+ u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];\r
+ u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;\r
+ u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;\r
+\r
+ /* u32FIN is shifted 2 bits to avoid overflow */\r
+ u32PllFreq = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2);\r
+ }\r
+ }\r
+\r
+ return u32PllFreq;\r
+}\r
+\r
+/**\r
+ * @brief Get selected module clock source\r
+ * @param[in] u32ModuleIdx is module index.\r
+ * - \ref SDH0_MODULE\r
+ * - \ref USBH_MODULE\r
+ * - \ref WDT_MODULE\r
+ * - \ref WWDT_MODULE\r
+ * - \ref RTC_MODULE\r
+ * - \ref TMR0_MODULE\r
+ * - \ref TMR1_MODULE\r
+ * - \ref TMR2_MODULE\r
+ * - \ref TMR3_MODULE\r
+ * - \ref CLKO_MODULE\r
+ * - \ref QSPI0_MODULE\r
+ * - \ref SPI0_MODULE\r
+ * - \ref SPI1_MODULE\r
+ * - \ref SPI2_MODULE\r
+ * - \ref SPI3_MODULE\r
+ * - \ref UART0_MODULE\r
+ * - \ref UART1_MODULE\r
+ * - \ref UART2_MODULE\r
+ * - \ref UART3_MODULE\r
+ * - \ref UART4_MODULE\r
+ * - \ref UART5_MODULE\r
+ * - \ref OTG_MODULE\r
+ * - \ref USBD_MODULE\r
+ * - \ref I2S0_MODULE\r
+ * - \ref SC0_MODULE\r
+ * - \ref SC1_MODULE\r
+ * - \ref SC2_MODULE\r
+ * - \ref EPWM0_MODULE\r
+ * - \ref EPWM1_MODULE\r
+ * - \ref BPWM0_MODULE\r
+ * - \ref BPWM1_MODULE\r
+ * @return Selected module clock source setting\r
+ * @details This function get selected module clock source.\r
+ */\r
+\r
+__NONSECURE_ENTRY_WEAK\r
+uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)\r
+{\r
+ uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;\r
+ uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL};\r
+\r
+ /* Get clock source selection setting */\r
+ if(u32ModuleIdx == EPWM0_MODULE)\r
+ {\r
+ u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos);\r
+ }\r
+ else if(u32ModuleIdx == EPWM1_MODULE)\r
+ {\r
+ u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos);\r
+ }\r
+ else if(u32ModuleIdx == BPWM0_MODULE)\r
+ {\r
+ u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos);\r
+ }\r
+ else if(u32ModuleIdx == BPWM1_MODULE)\r
+ {\r
+ u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos);\r
+ }\r
+ else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)\r
+ {\r
+ /* Get clock select control register address */\r
+ u32TmpAddr = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);\r
+\r
+ /* Get clock source selection setting */\r
+ u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx));\r
+ }\r
+\r
+ return u32TmpVal;\r
+}\r
+\r
+/**\r
+ * @brief Get selected module clock divider number\r
+ * @param[in] u32ModuleIdx is module index.\r
+ * - \ref SDH0_MODULE\r
+ * - \ref USBH_MODULE\r
+ * - \ref UART0_MODULE\r
+ * - \ref UART1_MODULE\r
+ * - \ref UART2_MODULE\r
+ * - \ref UART3_MODULE\r
+ * - \ref UART4_MODULE\r
+ * - \ref UART5_MODULE\r
+ * - \ref OTG_MODULE\r
+ * - \ref USBD_MODULE\r
+ * - \ref SC0_MODULE\r
+ * - \ref SC1_MODULE\r
+ * - \ref SC2_MODULE\r
+ * - \ref EADC_MODULE\r
+ * @return Selected module clock divider number setting\r
+ * @details This function get selected module clock divider number.\r
+ */\r
+\r
+__NONSECURE_ENTRY_WEAK\r
+uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)\r
+{\r
+ uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;\r
+ uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL};\r
+\r
+ if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)\r
+ {\r
+ /* Get clock divider control register address */\r
+ u32TmpAddr = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);\r
+ /* Get clock divider number setting */\r
+ u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx));\r
+ }\r
+\r
+ return u32TmpVal;\r
+}\r
+\r
+\r
+/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group CLK_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file crc.c\r
+ * @version V3.00\r
+ * @brief Cyclic Redundancy Check(CRC) driver source file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CRC_Driver CRC Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief CRC Open\r
+ *\r
+ * @param[in] u32Mode CRC operation polynomial mode. Valid values are:\r
+ * - \ref CRC_CCITT\r
+ * - \ref CRC_8\r
+ * - \ref CRC_16\r
+ * - \ref CRC_32\r
+ * @param[in] u32Attribute CRC operation data attribute. Valid values are combined with:\r
+ * - \ref CRC_CHECKSUM_COM\r
+ * - \ref CRC_CHECKSUM_RVS\r
+ * - \ref CRC_WDATA_COM\r
+ * - \ref CRC_WDATA_RVS\r
+ * @param[in] u32Seed Seed value.\r
+ * @param[in] u32DataLen CPU Write Data Length. Valid values are:\r
+ * - \ref CRC_CPU_WDATA_8\r
+ * - \ref CRC_CPU_WDATA_16\r
+ * - \ref CRC_CPU_WDATA_32\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n\r
+ * After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.\r
+ */\r
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)\r
+{\r
+ CRC_T *pCRC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pCRC = CRC_NS;\r
+ }\r
+ else\r
+ {\r
+ pCRC = CRC;\r
+ }\r
+\r
+ pCRC->SEED = u32Seed;\r
+ pCRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;\r
+\r
+ /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */\r
+ pCRC->CTL |= CRC_CTL_CHKSINIT_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Get CRC Checksum\r
+ *\r
+ * @param[in] None\r
+ *\r
+ * @return Checksum Result\r
+ *\r
+ * @details This macro gets the CRC checksum result by current CRC polynomial mode.\r
+ */\r
+uint32_t CRC_GetChecksum(void)\r
+{\r
+ CRC_T *pCRC;\r
+ uint32_t u32Checksum = 0UL;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pCRC = CRC_NS;\r
+ }\r
+ else\r
+ {\r
+ pCRC = CRC;\r
+ }\r
+\r
+ switch(pCRC->CTL & CRC_CTL_CRCMODE_Msk)\r
+ {\r
+ case CRC_CCITT:\r
+ case CRC_16:\r
+ u32Checksum = (pCRC->CHECKSUM & 0xFFFFUL);\r
+ break;\r
+\r
+ case CRC_32:\r
+ u32Checksum = pCRC->CHECKSUM;\r
+ break;\r
+\r
+ case CRC_8:\r
+ u32Checksum = (pCRC->CHECKSUM & 0xFFUL);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return u32Checksum;\r
+}\r
+\r
+/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group CRC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file crypto.c\r
+ * @version V1.10\r
+ * @brief Cryptographic Accelerator driver source file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+#include "M2351.h"\r
+\r
+#define ENABLE_DEBUG 0\r
+#define XOM_SUPPORT 0\r
+\r
+#if ENABLE_DEBUG\r
+#define CRPT_DBGMSG printf\r
+#else\r
+#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */\r
+#endif\r
+\r
+#if defined(__ICCARM__)\r
+# pragma diag_suppress=Pm073, Pm143 /* Misra C rule 14.7 */\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup CRYPTO_Driver CRYPTO Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions\r
+ @{\r
+*/\r
+\r
+/* // @cond HIDDEN_SYMBOLS */\r
+\r
+static uint32_t g_AES_CTL[4];\r
+static uint32_t g_TDES_CTL[4];\r
+\r
+static char hex_char_tbl[] = "0123456789abcdef";\r
+\r
+static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count);\r
+static char get_Nth_nibble_char(uint32_t val32, uint32_t idx);\r
+static void Hex2Reg(char input[], uint32_t volatile reg[]);\r
+static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]);\r
+static char ch2hex(char ch);\r
+static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift);\r
+static int get_nibble_value(char c);\r
+\r
+/* // @endcond HIDDEN_SYMBOLS */\r
+\r
+/**\r
+ * @brief Open PRNG function\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32KeySize it is PRNG key size, including:\r
+ * - \ref PRNG_KEY_SIZE_64\r
+ * - \ref PRNG_KEY_SIZE_128\r
+ * - \ref PRNG_KEY_SIZE_192\r
+ * - \ref PRNG_KEY_SIZE_256\r
+ * @param[in] u32SeedReload is PRNG seed reload or not, including:\r
+ * - \ref PRNG_SEED_CONT\r
+ * - \ref PRNG_SEED_RELOAD\r
+ * @param[in] u32Seed The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD.\r
+ * @return None\r
+ */\r
+void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed)\r
+{\r
+ if(u32SeedReload)\r
+ {\r
+ crpt->PRNG_SEED = u32Seed;\r
+ }\r
+\r
+ crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |\r
+ (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos);\r
+}\r
+\r
+/**\r
+ * @brief Start to generate one PRNG key.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @return None\r
+ */\r
+void PRNG_Start(CRPT_T *crpt)\r
+{\r
+ crpt->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Read the PRNG key.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[out] u32RandKey The key buffer to store newly generated PRNG key.\r
+ * @return None\r
+ */\r
+void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[])\r
+{\r
+ uint32_t i, wcnt;\r
+\r
+ wcnt = (((crpt->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U;\r
+\r
+ for(i = 0U; i < wcnt; i++)\r
+ {\r
+ u32RandKey[i] = crpt->PRNG_KEY[i];\r
+ }\r
+\r
+ crpt->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Open AES encrypt/decrypt function.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32Channel AES channel. Must be 0~3.\r
+ * @param[in] u32EncDec 1: AES encode; 0: AES decode\r
+ * @param[in] u32OpMode AES operation mode, including:\r
+ * - \ref AES_MODE_ECB\r
+ * - \ref AES_MODE_CBC\r
+ * - \ref AES_MODE_CFB\r
+ * - \ref AES_MODE_OFB\r
+ * - \ref AES_MODE_CTR\r
+ * - \ref AES_MODE_CBC_CS1\r
+ * - \ref AES_MODE_CBC_CS2\r
+ * - \ref AES_MODE_CBC_CS3\r
+ * @param[in] u32KeySize is AES key size, including:\r
+ * - \ref AES_KEY_SIZE_128\r
+ * - \ref AES_KEY_SIZE_192\r
+ * - \ref AES_KEY_SIZE_256\r
+ * @param[in] u32SwapType is AES input/output data swap control, including:\r
+ * - \ref AES_NO_SWAP\r
+ * - \ref AES_OUT_SWAP\r
+ * - \ref AES_IN_SWAP\r
+ * - \ref AES_IN_OUT_SWAP\r
+ * @return None\r
+ */\r
+void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec,\r
+ uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType)\r
+{\r
+ crpt->AES_CTL = (u32Channel << CRPT_AES_CTL_CHANNEL_Pos) |\r
+ (u32EncDec << CRPT_AES_CTL_ENCRPT_Pos) |\r
+ (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) |\r
+ (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) |\r
+ (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos);\r
+ g_AES_CTL[u32Channel] = crpt->AES_CTL;\r
+}\r
+\r
+/**\r
+ * @brief Start AES encrypt/decrypt\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32Channel AES channel. Must be 0~3.\r
+ * @param[in] u32DMAMode AES DMA control, including:\r
+ * - \ref CRYPTO_DMA_ONE_SHOT One shop AES encrypt/decrypt.\r
+ * - \ref CRYPTO_DMA_CONTINUE Continuous AES encrypt/decrypt.\r
+ * - \ref CRYPTO_DMA_LAST Last AES encrypt/decrypt of a series of AES_Start.\r
+ * @return None\r
+ */\r
+void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode)\r
+{\r
+ crpt->AES_CTL = g_AES_CTL[u32Channel];\r
+ crpt->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos);\r
+}\r
+\r
+/**\r
+ * @brief Set AES keys\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32Channel AES channel. Must be 0~3.\r
+ * @param[in] au32Keys An word array contains AES keys.\r
+ * @param[in] u32KeySize is AES key size, including:\r
+ * - \ref AES_KEY_SIZE_128\r
+ * - \ref AES_KEY_SIZE_192\r
+ * - \ref AES_KEY_SIZE_256\r
+ * @return None\r
+ */\r
+void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize)\r
+{\r
+ uint32_t i, wcnt, key_reg_addr;\r
+\r
+ key_reg_addr = (uint32_t)&crpt->AES0_KEY[0] + (u32Channel * 0x3CUL);\r
+ wcnt = 4UL + u32KeySize * 2UL;\r
+\r
+ for(i = 0U; i < wcnt; i++)\r
+ {\r
+ outpw(key_reg_addr, au32Keys[i]);\r
+ key_reg_addr += 4UL;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set AES initial vectors\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32Channel AES channel. Must be 0~3.\r
+ * @param[in] au32IV A four entry word array contains AES initial vectors.\r
+ * @return None\r
+ */\r
+void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[])\r
+{\r
+ uint32_t i, key_reg_addr;\r
+\r
+ key_reg_addr = (uint32_t)&crpt->AES0_IV[0] + (u32Channel * 0x3CUL);\r
+\r
+ for(i = 0U; i < 4U; i++)\r
+ {\r
+ outpw(key_reg_addr, au32IV[i]);\r
+ key_reg_addr += 4UL;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set AES DMA transfer configuration.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32Channel AES channel. Must be 0~3.\r
+ * @param[in] u32SrcAddr AES DMA source address\r
+ * @param[in] u32DstAddr AES DMA destination address\r
+ * @param[in] u32TransCnt AES DMA transfer byte count\r
+ * @return None\r
+ */\r
+void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr,\r
+ uint32_t u32DstAddr, uint32_t u32TransCnt)\r
+{\r
+ uint32_t reg_addr;\r
+\r
+ reg_addr = (uint32_t)&crpt->AES0_SADDR + (u32Channel * 0x3CUL);\r
+ outpw(reg_addr, u32SrcAddr);\r
+\r
+ reg_addr = (uint32_t)&crpt->AES0_DADDR + (u32Channel * 0x3CUL);\r
+ outpw(reg_addr, u32DstAddr);\r
+\r
+ reg_addr = (uint32_t)&crpt->AES0_CNT + (u32Channel * 0x3CUL);\r
+ outpw(reg_addr, u32TransCnt);\r
+}\r
+\r
+/**\r
+ * @brief Open TDES encrypt/decrypt function.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32Channel TDES channel. Must be 0~3.\r
+ * @param[in] u32EncDec 1: TDES encode; 0: TDES decode\r
+ * @param[in] Is3DES 1: TDES; 0: DES\r
+ * @param[in] Is3Key 1: TDES 3 key mode; 0: TDES 2 key mode\r
+ * @param[in] u32OpMode TDES operation mode, including:\r
+ * - \ref TDES_MODE_ECB\r
+ * - \ref TDES_MODE_CBC\r
+ * - \ref TDES_MODE_CFB\r
+ * - \ref TDES_MODE_OFB\r
+ * - \ref TDES_MODE_CTR\r
+ * @param[in] u32SwapType is TDES input/output data swap control and word swap control, including:\r
+ * - \ref TDES_NO_SWAP\r
+ * - \ref TDES_WHL_SWAP\r
+ * - \ref TDES_OUT_SWAP\r
+ * - \ref TDES_OUT_WHL_SWAP\r
+ * - \ref TDES_IN_SWAP\r
+ * - \ref TDES_IN_WHL_SWAP\r
+ * - \ref TDES_IN_OUT_SWAP\r
+ * - \ref TDES_IN_OUT_WHL_SWAP\r
+ * @return None\r
+ */\r
+void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key,\r
+ uint32_t u32OpMode, uint32_t u32SwapType)\r
+{\r
+ g_TDES_CTL[u32Channel] = (u32Channel << CRPT_TDES_CTL_CHANNEL_Pos) |\r
+ (u32EncDec << CRPT_TDES_CTL_ENCRPT_Pos) |\r
+ u32OpMode | (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos);\r
+ if(Is3DES)\r
+ {\r
+ g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_TMODE_Msk;\r
+ }\r
+ if(Is3Key)\r
+ {\r
+ g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_3KEYS_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Start TDES encrypt/decrypt\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32Channel TDES channel. Must be 0~3.\r
+ * @param[in] u32DMAMode TDES DMA control, including:\r
+ * - \ref CRYPTO_DMA_ONE_SHOT One shop TDES encrypt/decrypt.\r
+ * - \ref CRYPTO_DMA_CONTINUE Continuous TDES encrypt/decrypt.\r
+ * - \ref CRYPTO_DMA_LAST Last TDES encrypt/decrypt of a series of TDES_Start.\r
+ * @return None\r
+ */\r
+void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode)\r
+{\r
+ g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_START_Msk | (u32DMAMode << CRPT_TDES_CTL_DMALAST_Pos);\r
+ crpt->TDES_CTL = g_TDES_CTL[u32Channel];\r
+}\r
+\r
+/**\r
+ * @brief Set TDES keys\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32Channel TDES channel. Must be 0~3.\r
+ * @param[in] au32Keys The TDES keys. au32Keys[0][0] is Key0 high word and au32Keys[0][1] is key0 low word.\r
+ * @return None\r
+ */\r
+void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2])\r
+{\r
+ uint32_t i, reg_addr;\r
+\r
+ reg_addr = (uint32_t)&crpt->TDES0_KEY1H + (0x40UL * u32Channel);\r
+\r
+ for(i = 0U; i < 3U; i++)\r
+ {\r
+ outpw(reg_addr, au32Keys[i][0]); /* TDESn_KEYxH */\r
+ reg_addr += 4UL;\r
+ outpw(reg_addr, au32Keys[i][1]); /* TDESn_KEYxL */\r
+ reg_addr += 4UL;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set TDES initial vectors\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32Channel TDES channel. Must be 0~3.\r
+ * @param[in] u32IVH TDES initial vector high word.\r
+ * @param[in] u32IVL TDES initial vector low word.\r
+ * @return None\r
+ */\r
+void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL)\r
+{\r
+ uint32_t reg_addr;\r
+\r
+ reg_addr = (uint32_t)&crpt->TDES0_IVH + (u32Channel * 0x40UL);\r
+ outpw(reg_addr, u32IVH);\r
+\r
+ reg_addr = (uint32_t)&crpt->TDES0_IVL + (u32Channel * 0x40UL);\r
+ outpw(reg_addr, u32IVL);\r
+}\r
+\r
+/**\r
+ * @brief Set TDES DMA transfer configuration.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32Channel TDES channel. Must be 0~3.\r
+ * @param[in] u32SrcAddr TDES DMA source address\r
+ * @param[in] u32DstAddr TDES DMA destination address\r
+ * @param[in] u32TransCnt TDES DMA transfer byte count\r
+ * @return None\r
+ */\r
+void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr,\r
+ uint32_t u32DstAddr, uint32_t u32TransCnt)\r
+{\r
+ uint32_t reg_addr;\r
+\r
+ reg_addr = (uint32_t)&crpt->TDES0_SADDR + (u32Channel * 0x40UL);\r
+ outpw(reg_addr, u32SrcAddr);\r
+\r
+ reg_addr = (uint32_t)&crpt->TDES0_DADDR + (u32Channel * 0x40UL);\r
+ outpw(reg_addr, u32DstAddr);\r
+\r
+ reg_addr = (uint32_t)&crpt->TDES0_CNT + (u32Channel * 0x40UL);\r
+ outpw(reg_addr, u32TransCnt);\r
+}\r
+\r
+/**\r
+ * @brief Open SHA encrypt function.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32OpMode SHA operation mode, including:\r
+ * - \ref SHA_MODE_SHA1\r
+ * - \ref SHA_MODE_SHA224\r
+ * - \ref SHA_MODE_SHA256\r
+ * @param[in] u32SwapType is SHA input/output data swap control, including:\r
+ * - \ref SHA_NO_SWAP\r
+ * - \ref SHA_OUT_SWAP\r
+ * - \ref SHA_IN_SWAP\r
+ * - \ref SHA_IN_OUT_SWAP\r
+ * @param[in] hmac_key_len HMAC key byte count\r
+ * @return None\r
+ */\r
+void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len)\r
+{\r
+ crpt->HMAC_CTL = (u32OpMode << CRPT_HMAC_CTL_OPMODE_Pos) |\r
+ (u32SwapType << CRPT_HMAC_CTL_OUTSWAP_Pos);\r
+\r
+ if(hmac_key_len != 0UL)\r
+ {\r
+ crpt->HMAC_KEYCNT = hmac_key_len;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Start SHA encrypt\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32DMAMode TDES DMA control, including:\r
+ * - \ref CRYPTO_DMA_ONE_SHOT One shop SHA encrypt.\r
+ * - \ref CRYPTO_DMA_CONTINUE Continuous SHA encrypt.\r
+ * - \ref CRYPTO_DMA_LAST Last SHA encrypt of a series of SHA_Start.\r
+ * @return None\r
+ */\r
+void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode)\r
+{\r
+ crpt->HMAC_CTL &= ~(0x7UL << CRPT_HMAC_CTL_DMALAST_Pos);\r
+ crpt->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk | (u32DMAMode << CRPT_HMAC_CTL_DMALAST_Pos);\r
+}\r
+\r
+/**\r
+ * @brief Set SHA DMA transfer\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] u32SrcAddr SHA DMA source address\r
+ * @param[in] u32TransCnt SHA DMA transfer byte count\r
+ * @return None\r
+ */\r
+void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt)\r
+{\r
+ crpt->HMAC_SADDR = u32SrcAddr;\r
+ crpt->HMAC_DMACNT = u32TransCnt;\r
+}\r
+\r
+/**\r
+ * @brief Read the SHA digest.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[out] u32Digest The SHA encrypt output digest.\r
+ * @return None\r
+ */\r
+void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[])\r
+{\r
+ uint32_t i, wcnt, reg_addr;\r
+\r
+ i = (crpt->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos;\r
+\r
+ if(i == SHA_MODE_SHA1)\r
+ {\r
+ wcnt = 5UL;\r
+ }\r
+ else if(i == SHA_MODE_SHA224)\r
+ {\r
+ wcnt = 7UL;\r
+ }\r
+ else if(i == SHA_MODE_SHA256)\r
+ {\r
+ wcnt = 8UL;\r
+ }\r
+ else if(i == SHA_MODE_SHA384)\r
+ {\r
+ wcnt = 12UL;\r
+ }\r
+ else\r
+ {\r
+ /* SHA_MODE_SHA512 */\r
+ wcnt = 16UL;\r
+ }\r
+\r
+ reg_addr = (uint32_t) & (crpt->HMAC_DGST[0]);\r
+ for(i = 0UL; i < wcnt; i++)\r
+ {\r
+ u32Digest[i] = inpw(reg_addr);\r
+ reg_addr += 4UL;\r
+ }\r
+}\r
+\r
+\r
+/*-----------------------------------------------------------------------------------------------*/\r
+/* */\r
+/* ECC */\r
+/* */\r
+/*-----------------------------------------------------------------------------------------------*/\r
+\r
+#define ECCOP_POINT_MUL (0x0UL << CRPT_ECC_CTL_ECCOP_Pos)\r
+#define ECCOP_MODULE (0x1UL << CRPT_ECC_CTL_ECCOP_Pos)\r
+#define ECCOP_POINT_ADD (0x2UL << CRPT_ECC_CTL_ECCOP_Pos)\r
+#define ECCOP_POINT_DOUBLE (0x0UL << CRPT_ECC_CTL_ECCOP_Pos)\r
+\r
+#define MODOP_DIV (0x0UL << CRPT_ECC_CTL_MODOP_Pos)\r
+#define MODOP_MUL (0x1UL << CRPT_ECC_CTL_MODOP_Pos)\r
+#define MODOP_ADD (0x2UL << CRPT_ECC_CTL_MODOP_Pos)\r
+#define MODOP_SUB (0x3UL << CRPT_ECC_CTL_MODOP_Pos)\r
+\r
+enum\r
+{\r
+ CURVE_GF_P,\r
+ CURVE_GF_2M,\r
+};\r
+\r
+/*-----------------------------------------------------*/\r
+/* Define elliptic curve (EC): */\r
+/*-----------------------------------------------------*/\r
+#if !XOM_SUPPORT // Replace with XOM ready curve table\r
+const ECC_CURVE _Curve[] =\r
+{\r
+ {\r
+ /* NIST: Curve P-192 : y^2=x^3-ax+b (mod p) */\r
+ CURVE_P_192,\r
+ 48, /* Echar */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFC", /* "000000000000000000000000000000000000000000000003" */\r
+ "64210519e59c80e70fa7e9ab72243049feb8deecc146b9b1",\r
+ "188da80eb03090f67cbf20eb43a18800f4ff0afd82ff1012",\r
+ "07192b95ffc8da78631011ed6b24cdd573f977a11e794811",\r
+ 58, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF", /* "6277101735386680763835789423207666416083908700390324961279" */\r
+ 58, /* Eol */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831", /* "6277101735386680763835789423176059013767194773182842284081" */\r
+ 192, /* key_len */\r
+ 7,\r
+ 2,\r
+ 1,\r
+ CURVE_GF_P\r
+ },\r
+ {\r
+ /* NIST: Curve P-224 : y^2=x^3-ax+b (mod p) */\r
+ CURVE_P_224,\r
+ 56, /* Echar */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFE", /* "00000000000000000000000000000000000000000000000000000003" */\r
+ "b4050a850c04b3abf54132565044b0b7d7bfd8ba270b39432355ffb4",\r
+ "b70e0cbd6bb4bf7f321390b94a03c1d356c21122343280d6115c1d21",\r
+ "bd376388b5f723fb4c22dfe6cd4375a05a07476444d5819985007e34",\r
+ 70, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "0026959946667150639794667015087019630673557916260026308143510066298881" */\r
+ 70, /* Eol */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D", /* "0026959946667150639794667015087019625940457807714424391721682722368061" */\r
+ 224, /* key_len */\r
+ 9,\r
+ 8,\r
+ 3,\r
+ CURVE_GF_P\r
+ },\r
+ {\r
+ /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */\r
+ CURVE_P_256,\r
+ 64, /* Echar */\r
+ "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFC", /* "0000000000000000000000000000000000000000000000000000000000000003" */\r
+ "5ac635d8aa3a93e7b3ebbd55769886bc651d06b0cc53b0f63bce3c3e27d2604b",\r
+ "6b17d1f2e12c4247f8bce6e563a440f277037d812deb33a0f4a13945d898c296",\r
+ "4fe342e2fe1a7f9b8ee7eb4a7c0f9e162bce33576b315ececbb6406837bf51f5",\r
+ 78, /* Epl */\r
+ "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF", /* "115792089210356248762697446949407573530086143415290314195533631308867097853951" */\r
+ 78, /* Eol */\r
+ "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551", /* "115792089210356248762697446949407573529996955224135760342422259061068512044369" */\r
+ 256, /* key_len */\r
+ 10,\r
+ 5,\r
+ 2,\r
+ CURVE_GF_P\r
+ },\r
+ {\r
+ /* NIST: Curve P-384 : y^2=x^3-ax+b (mod p) */\r
+ CURVE_P_384,\r
+ 96, /* Echar */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFC", /* "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */\r
+ "b3312fa7e23ee7e4988e056be3f82d19181d9c6efe8141120314088f5013875ac656398d8a2ed19d2a85c8edd3ec2aef",\r
+ "aa87ca22be8b05378eb1c71ef320ad746e1d3b628ba79b9859f741e082542a385502f25dbf55296c3a545e3872760ab7",\r
+ "3617de4a96262c6f5d9e98bf9292dc29f8f41dbd289a147ce9da3113b5f0b8c00a60b1ce1d7e819d7a431d7c90ea0e5f",\r
+ 116, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF", /* "39402006196394479212279040100143613805079739270465446667948293404245721771496870329047266088258938001861606973112319" */\r
+ 116, /* Eol */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973", /* "39402006196394479212279040100143613805079739270465446667946905279627659399113263569398956308152294913554433653942643" */\r
+ 384, /* key_len */\r
+ 12,\r
+ 3,\r
+ 2,\r
+ CURVE_GF_P\r
+ },\r
+ {\r
+ /* NIST: Curve P-521 : y^2=x^3-ax+b (mod p)*/\r
+ CURVE_P_521,\r
+ 131, /* Echar */\r
+ "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC", /* "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */\r
+ "051953eb9618e1c9a1f929a21a0b68540eea2da725b99b315f3b8b489918ef109e156193951ec7e937b1652c0bd3bb1bf073573df883d2c34f1ef451fd46b503f00",\r
+ "0c6858e06b70404e9cd9e3ecb662395b4429c648139053fb521f828af606b4d3dbaa14b5e77efe75928fe1dc127a2ffa8de3348b3c1856a429bf97e7e31c2e5bd66",\r
+ "11839296a789a3bc0045c8a5fb42c7d1bd998f54449579b446817afbd17273e662c97ee72995ef42640c550b9013fad0761353c7086a272c24088be94769fd16650",\r
+ 157, /* Epl */\r
+ "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397656052122559640661454554977296311391480858037121987999716643812574028291115057151" */\r
+ 157, /* Eol */\r
+ "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397655394245057746333217197532963996371363321113864768612440380340372808892707005449" */\r
+ 521, /* key_len */\r
+ 32,\r
+ 32,\r
+ 32,\r
+ CURVE_GF_P\r
+ },\r
+ {\r
+ /* NIST: Curve B-163 : y^2+xy=x^3+ax^2+b */\r
+ CURVE_B_163,\r
+ 41, /* Echar */\r
+ "00000000000000000000000000000000000000001",\r
+ "20a601907b8c953ca1481eb10512f78744a3205fd",\r
+ "3f0eba16286a2d57ea0991168d4994637e8343e36",\r
+ "0d51fbc6c71a0094fa2cdd545b11c5c0c797324f1",\r
+ 68, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */\r
+ 49, /* Eol */\r
+ "40000000000000000000292FE77E70C12A4234C33", /* "5846006549323611672814742442876390689256843201587" */\r
+ 163, /* key_len */\r
+ 7,\r
+ 6,\r
+ 3,\r
+ CURVE_GF_2M\r
+ },\r
+ {\r
+ /* NIST: Curve B-233 : y^2+xy=x^3+ax^2+b */\r
+ CURVE_B_233,\r
+ 59, /* Echar 59 */\r
+ "00000000000000000000000000000000000000000000000000000000001",\r
+ "066647ede6c332c7f8c0923bb58213b333b20e9ce4281fe115f7d8f90ad",\r
+ "0fac9dfcbac8313bb2139f1bb755fef65bc391f8b36f8f8eb7371fd558b",\r
+ "1006a08a41903350678e58528bebf8a0beff867a7ca36716f7e01f81052",\r
+ 68, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */\r
+ 70, /* Eol */\r
+ "1000000000000000000000000000013E974E72F8A6922031D2603CFE0D7", /* "6901746346790563787434755862277025555839812737345013555379383634485463" */\r
+ 233, /* key_len */\r
+ 74,\r
+ 74,\r
+ 74,\r
+ CURVE_GF_2M\r
+ },\r
+ {\r
+ /* NIST: Curve B-283 : y^2+xy=x^3+ax^2+b */\r
+ CURVE_B_283,\r
+ 71, /* Echar */\r
+ "00000000000000000000000000000000000000000000000000000000000000000000001",\r
+ "27b680ac8b8596da5a4af8a19a0303fca97fd7645309fa2a581485af6263e313b79a2f5",\r
+ "5f939258db7dd90e1934f8c70b0dfec2eed25b8557eac9c80e2e198f8cdbecd86b12053",\r
+ "3676854fe24141cb98fe6d4b20d02b4516ff702350eddb0826779c813f0df45be8112f4",\r
+ 68, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */\r
+ 85, /* Eol */\r
+ "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF90399660FC938A90165B042A7CEFADB307", /* "7770675568902916283677847627294075626569625924376904889109196526770044277787378692871" */\r
+ 283, /* key_len */\r
+ 12,\r
+ 7,\r
+ 5,\r
+ CURVE_GF_2M\r
+ },\r
+ {\r
+ /* NIST: Curve B-409 : y^2+xy=x^3+ax^2+b */\r
+ CURVE_B_409,\r
+ 103, /* Echar */\r
+ "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",\r
+ "021a5c2c8ee9feb5c4b9a753b7b476b7fd6422ef1f3dd674761fa99d6ac27c8a9a197b272822f6cd57a55aa4f50ae317b13545f",\r
+ "15d4860d088ddb3496b0c6064756260441cde4af1771d4db01ffe5b34e59703dc255a868a1180515603aeab60794e54bb7996a7",\r
+ "061b1cfab6be5f32bbfa78324ed106a7636b9c5a7bd198d0158aa4f5488d08f38514f1fdf4b4f40d2181b3681c364ba0273c706",\r
+ 68, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */\r
+ 123, /* Eol */\r
+ "10000000000000000000000000000000000000000000000000001E2AAD6A612F33307BE5FA47C3C9E052F838164CD37D9A21173", /* "661055968790248598951915308032771039828404682964281219284648798304157774827374805208143723762179110965979867288366567526771" */\r
+ 409, /* key_len */\r
+ 87,\r
+ 87,\r
+ 87,\r
+ CURVE_GF_2M\r
+ },\r
+ {\r
+ /* NIST: Curve B-571 : y^2+xy=x^3+ax^2+b */\r
+ CURVE_B_571,\r
+ 143, /* Echar */\r
+ "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",\r
+ "2f40e7e2221f295de297117b7f3d62f5c6a97ffcb8ceff1cd6ba8ce4a9a18ad84ffabbd8efa59332be7ad6756a66e294afd185a78ff12aa520e4de739baca0c7ffeff7f2955727a",\r
+ "303001d34b856296c16c0d40d3cd7750a93d1d2955fa80aa5f40fc8db7b2abdbde53950f4c0d293cdd711a35b67fb1499ae60038614f1394abfa3b4c850d927e1e7769c8eec2d19",\r
+ "37bf27342da639b6dccfffeb73d69d78c6c27a6009cbbca1980f8533921e8a684423e43bab08a576291af8f461bb2a8b3531d2f0485c19b16e2f1516e23dd3c1a4827af1b8ac15b",\r
+ 68, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */\r
+ 172, /* Eol */\r
+ "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE661CE18FF55987308059B186823851EC7DD9CA1161DE93D5174D66E8382E9BB2FE84E47", /* "3864537523017258344695351890931987344298927329706434998657235251451519142289560424536143999389415773083133881121926944486246872462816813070234528288303332411393191105285703" */\r
+ 571, /* key_len */\r
+ 10,\r
+ 5,\r
+ 2,\r
+ CURVE_GF_2M\r
+ },\r
+ {\r
+ /* NIST: Curve K-163 : y^2+xy=x^3+ax^2+b */\r
+ CURVE_K_163,\r
+ 41, /* Echar */\r
+ "00000000000000000000000000000000000000001",\r
+ "00000000000000000000000000000000000000001",\r
+ "2fe13c0537bbc11acaa07d793de4e6d5e5c94eee8",\r
+ "289070fb05d38ff58321f2e800536d538ccdaa3d9",\r
+ 68, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */\r
+ 49, /* Eol */\r
+ "4000000000000000000020108A2E0CC0D99F8A5EF", /* "5846006549323611672814741753598448348329118574063" */\r
+ 163, /* key_len */\r
+ 7,\r
+ 6,\r
+ 3,\r
+ CURVE_GF_2M\r
+ },\r
+ {\r
+ /* NIST: Curve K-233 : y^2+xy=x^3+ax^2+b */\r
+ CURVE_K_233,\r
+ 59, /* Echar 59 */\r
+ "00000000000000000000000000000000000000000000000000000000000",\r
+ "00000000000000000000000000000000000000000000000000000000001",\r
+ "17232ba853a7e731af129f22ff4149563a419c26bf50a4c9d6eefad6126",\r
+ "1db537dece819b7f70f555a67c427a8cd9bf18aeb9b56e0c11056fae6a3",\r
+ 68, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */\r
+ 70, /* Eol */\r
+ "8000000000000000000000000000069D5BB915BCD46EFB1AD5F173ABDF", /* "3450873173395281893717377931138512760570940988862252126328087024741343" */\r
+ 233, /* key_len */\r
+ 74,\r
+ 74,\r
+ 74,\r
+ CURVE_GF_2M\r
+ },\r
+ {\r
+ /* NIST: Curve K-283 : y^2+xy=x^3+ax^2+b */\r
+ CURVE_K_283,\r
+ 71, /* Echar */\r
+ "00000000000000000000000000000000000000000000000000000000000000000000000",\r
+ "00000000000000000000000000000000000000000000000000000000000000000000001",\r
+ "503213f78ca44883f1a3b8162f188e553cd265f23c1567a16876913b0c2ac2458492836",\r
+ "1ccda380f1c9e318d90f95d07e5426fe87e45c0e8184698e45962364e34116177dd2259",\r
+ 68, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */\r
+ 85, /* Eol */\r
+ "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9AE2ED07577265DFF7F94451E061E163C61", /* "3885337784451458141838923813647037813284811733793061324295874997529815829704422603873" */\r
+ 283, /* key_len */\r
+ 12,\r
+ 7,\r
+ 5,\r
+ CURVE_GF_2M\r
+ },\r
+ {\r
+ /* NIST: Curve K-409 : y^2+xy=x^3+ax^2+b */\r
+ CURVE_K_409,\r
+ 103, /* Echar */\r
+ "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",\r
+ "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",\r
+ "060f05f658f49c1ad3ab1890f7184210efd0987e307c84c27accfb8f9f67cc2c460189eb5aaaa62ee222eb1b35540cfe9023746",\r
+ "1e369050b7c4e42acba1dacbf04299c3460782f918ea427e6325165e9ea10e3da5f6c42e9c55215aa9ca27a5863ec48d8e0286b",\r
+ 68, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */\r
+ 123, /* Eol */\r
+ "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5F83B2D4EA20400EC4557D5ED3E3E7CA5B4B5C83B8E01E5FCF", /* "330527984395124299475957654016385519914202341482140609642324395022880711289249191050673258457777458014096366590617731358671" */\r
+ 409, /* key_len */\r
+ 87,\r
+ 87,\r
+ 87,\r
+ CURVE_GF_2M\r
+ },\r
+ {\r
+ /* NIST: Curve K-571 : y^2+xy=x^3+ax^2+b */\r
+ CURVE_K_571,\r
+ 143, /* Echar */\r
+ "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",\r
+ "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",\r
+ "26eb7a859923fbc82189631f8103fe4ac9ca2970012d5d46024804801841ca44370958493b205e647da304db4ceb08cbbd1ba39494776fb988b47174dca88c7e2945283a01c8972",\r
+ "349dc807f4fbf374f4aeade3bca95314dd58cec9f307a54ffc61efc006d8a2c9d4979c0ac44aea74fbebbb9f772aedcb620b01a7ba7af1b320430c8591984f601cd4c143ef1c7a3",\r
+ 68, /* Epl */\r
+ "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */\r
+ 172, /* Eol */\r
+ "20000000000000000000000000000000000000000000000000000000000000000000000131850E1F19A63E4B391A8DB917F4138B630D84BE5D639381E91DEB45CFE778F637C1001", /* "1932268761508629172347675945465993672149463664853217499328617625725759571144780212268133978522706711834706712800825351461273674974066617311929682421617092503555733685276673" */\r
+ 571, /* key_len */\r
+ 10,\r
+ 5,\r
+ 2,\r
+ CURVE_GF_2M\r
+ },\r
+};\r
+#endif\r
+\r
+\r
+static ECC_CURVE *pCurve;\r
+static ECC_CURVE Curve_Copy;\r
+\r
+static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve);\r
+static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve);\r
+static void run_ecc_codec(CRPT_T *crpt, uint32_t mode);\r
+\r
+static char temp_hex_str[160];\r
+\r
+volatile uint32_t g_ECC_done, g_ECCERR_done;\r
+\r
+void ECC_DriverISR(CRPT_T *crpt)\r
+{\r
+ if(crpt->INTSTS & CRPT_INTSTS_ECCIF_Msk)\r
+ {\r
+ g_ECC_done = 1UL;\r
+ crpt->INTSTS = CRPT_INTSTS_ECCIF_Msk;\r
+ /* printf("ECC done IRQ.\n"); */\r
+ }\r
+\r
+ if(crpt->INTSTS & CRPT_INTSTS_ECCEIF_Msk)\r
+ {\r
+ g_ECCERR_done = 1UL;\r
+ crpt->INTSTS = CRPT_INTSTS_ECCEIF_Msk;\r
+ /* printf("ECCERRIF is set!!\n"); */\r
+ }\r
+}\r
+\r
+\r
+#if ENABLE_DEBUG\r
+static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count)\r
+{\r
+ int32_t i;\r
+\r
+ printf("%s => ", str);\r
+ for(i = 0; i < count; i++)\r
+ {\r
+ printf("0x%08x ", regs[i]);\r
+ }\r
+ printf("\n");\r
+}\r
+#else\r
+static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) { }\r
+#endif\r
+static char ch2hex(char ch)\r
+{\r
+ if(ch <= '9')\r
+ {\r
+ return ch - '0';\r
+ }\r
+ else if((ch <= 'z') && (ch >= 'a'))\r
+ {\r
+ return ch - 'a' + 10U;\r
+ }\r
+ else\r
+ {\r
+ return ch - 'A' + 10U;\r
+ }\r
+}\r
+\r
+static void Hex2Reg(char input[], uint32_t volatile reg[])\r
+{\r
+ char hex;\r
+ int si, ri;\r
+ uint32_t i, val32;\r
+\r
+ si = (int)strlen(input) - 1;\r
+ ri = 0;\r
+\r
+ while(si >= 0)\r
+ {\r
+ val32 = 0UL;\r
+ for(i = 0UL; (i < 8UL) && (si >= 0); i++)\r
+ {\r
+ hex = ch2hex(input[si]);\r
+ val32 |= (uint32_t)hex << (i * 4UL);\r
+ si--;\r
+ }\r
+ reg[ri++] = val32;\r
+ }\r
+}\r
+\r
+static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift)\r
+{\r
+ uint32_t hex, carry;\r
+ int si, ri;\r
+ uint32_t i, val32;\r
+\r
+ si = (int)strlen(input) - 1;\r
+ ri = 0;\r
+ carry = 0U;\r
+ while(si >= 0)\r
+ {\r
+ val32 = 0UL;\r
+ for(i = 0UL; (i < 8UL) && (si >= 0); i++)\r
+ {\r
+ hex = (uint32_t)ch2hex(input[si]);\r
+ hex <<= shift;\r
+\r
+ val32 |= (uint32_t)((hex & 0xFU) | carry) << (i * 4UL);\r
+ carry = (hex >> 4) & 0xFU;\r
+ si--;\r
+ }\r
+ reg[ri++] = val32;\r
+ }\r
+ if(carry != 0U)\r
+ {\r
+ reg[ri] = carry;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Extract specified nibble from an unsigned word in character format.\r
+ * For example:\r
+ * Suppose val32 is 0x786543210, get_Nth_nibble_char(val32, 3) will return a '3'.\r
+ * @param[in] val32 The input unsigned word\r
+ * @param[in] idx The Nth nibble to be extracted.\r
+ * @return The nibble in character format.\r
+ */\r
+static char get_Nth_nibble_char(uint32_t val32, uint32_t idx)\r
+{\r
+ return hex_char_tbl[(val32 >> (idx * 4U)) & 0xfU ];\r
+}\r
+\r
+\r
+static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[])\r
+{\r
+ int32_t idx, ri;\r
+ uint32_t i;\r
+\r
+ output[count] = 0U;\r
+ idx = count - 1;\r
+\r
+ for(ri = 0; idx >= 0; ri++)\r
+ {\r
+ for(i = 0UL; (i < 8UL) && (idx >= 0); i++)\r
+ {\r
+ output[idx] = get_Nth_nibble_char(reg[ri], i);\r
+ idx--;\r
+ }\r
+ }\r
+}\r
+\r
+static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve)\r
+{\r
+ int32_t i, ret = 0;\r
+\r
+ pCurve = get_curve(ecc_curve);\r
+ if(pCurve == NULL)\r
+ {\r
+ CRPT_DBGMSG("Cannot find curve %d!!\n", ecc_curve);\r
+ ret = -1;\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_A[i] = 0UL;\r
+ crpt->ECC_B[i] = 0UL;\r
+ crpt->ECC_X1[i] = 0UL;\r
+ crpt->ECC_Y1[i] = 0UL;\r
+ crpt->ECC_N[i] = 0UL;\r
+ }\r
+\r
+ Hex2Reg(pCurve->Ea, crpt->ECC_A);\r
+ Hex2Reg(pCurve->Eb, crpt->ECC_B);\r
+ Hex2Reg(pCurve->Px, crpt->ECC_X1);\r
+ Hex2Reg(pCurve->Py, crpt->ECC_Y1);\r
+\r
+ CRPT_DBGMSG("Key length = %d\n", pCurve->key_len);\r
+ dump_ecc_reg("CRPT_ECC_CURVE_A", crpt->ECC_A, 10);\r
+ dump_ecc_reg("CRPT_ECC_CURVE_B", crpt->ECC_B, 10);\r
+ dump_ecc_reg("CRPT_ECC_POINT_X1", crpt->ECC_X1, 10);\r
+ dump_ecc_reg("CRPT_ECC_POINT_Y1", crpt->ECC_Y1, 10);\r
+\r
+ if(pCurve->GF == (int)CURVE_GF_2M)\r
+ {\r
+ crpt->ECC_N[0] = 0x1UL;\r
+ crpt->ECC_N[(pCurve->key_len) / 32] |= (1UL << ((pCurve->key_len) % 32));\r
+ crpt->ECC_N[(pCurve->irreducible_k1) / 32] |= (1UL << ((pCurve->irreducible_k1) % 32));\r
+ crpt->ECC_N[(pCurve->irreducible_k2) / 32] |= (1UL << ((pCurve->irreducible_k2) % 32));\r
+ crpt->ECC_N[(pCurve->irreducible_k3) / 32] |= (1UL << ((pCurve->irreducible_k3) % 32));\r
+ }\r
+ else\r
+ {\r
+ Hex2Reg(pCurve->Pp, crpt->ECC_N);\r
+ }\r
+ }\r
+ dump_ecc_reg("CRPT_ECC_CURVE_N", crpt->ECC_N, 10);\r
+ return ret;\r
+}\r
+\r
+\r
+static int get_nibble_value(char c)\r
+{\r
+ char ch;\r
+\r
+ if((c >= '0') && (c <= '9'))\r
+ {\r
+ ch = '0';\r
+ return ((int)c - (int)ch);\r
+ }\r
+\r
+ if((c >= 'a') && (c <= 'f'))\r
+ {\r
+ ch = 'a';\r
+ return ((int)c - (int)ch + 10);\r
+ }\r
+\r
+ if((c >= 'A') && (c <= 'F'))\r
+ {\r
+ ch = 'A';\r
+ return ((int)c - (int)ch + 10);\r
+ }\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if the private key is located in valid range of curve.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] ecc_curve The pre-defined ECC curve.\r
+ * @param[in] private_k The input private key.\r
+ * @return 1 Is valid.\r
+ * @return 0 Is not valid.\r
+ * @return -1 Invalid curve.\r
+ */\r
+int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[])\r
+{\r
+ uint32_t i;\r
+\r
+\r
+ pCurve = get_curve(ecc_curve);\r
+ if(pCurve == NULL)\r
+ {\r
+ return -1;\r
+ }\r
+\r
+ if(strlen(private_k) < strlen(pCurve->Eorder))\r
+ {\r
+ return 1;\r
+ }\r
+\r
+ if(strlen(private_k) > strlen(pCurve->Eorder))\r
+ {\r
+ return 0;\r
+ }\r
+\r
+ for(i = 0U; i < strlen(private_k); i++)\r
+ {\r
+ if(get_nibble_value(private_k[i]) < get_nibble_value(pCurve->Eorder[i]))\r
+ {\r
+ return 1;\r
+ }\r
+\r
+ if(get_nibble_value(private_k[i]) > get_nibble_value(pCurve->Eorder[i]))\r
+ {\r
+ return 0;\r
+ }\r
+ }\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Given a private key and curve to generate the public key pair.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] private_k The input private key.\r
+ * @param[in] ecc_curve The pre-defined ECC curve.\r
+ * @param[out] public_k1 The output publick key 1.\r
+ * @param[out] public_k2 The output publick key 2.\r
+ * @return 0 Success.\r
+ * @return -1 "ecc_curve" value is invalid.\r
+ */\r
+int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[])\r
+{\r
+ int32_t ret = 0, i;\r
+ uint32_t u32Tmp;\r
+\r
+ if(ecc_init_curve(crpt, ecc_curve) != 0)\r
+ {\r
+ ret = -1;\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_K[i] = 0UL;\r
+ }\r
+\r
+ Hex2Reg(private_k, crpt->ECC_K);\r
+\r
+ /* set FSEL (Field selection) */\r
+ if(pCurve->GF == (int)CURVE_GF_2M)\r
+ {\r
+ crpt->ECC_CTL = 0UL;\r
+ }\r
+ else /* CURVE_GF_P */\r
+ {\r
+ crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;\r
+ }\r
+\r
+ g_ECC_done = g_ECCERR_done = 0UL;\r
+ crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) |\r
+ ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk;\r
+\r
+ do\r
+ {\r
+ u32Tmp = g_ECC_done;\r
+ u32Tmp |= g_ECCERR_done;\r
+ }\r
+ while(u32Tmp == 0UL);\r
+\r
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, public_k1);\r
+ Reg2Hex(pCurve->Echar, crpt->ECC_Y1, public_k2);\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] ecc_curve The pre-defined ECC curve.\r
+ * @param[in] private_k One's own private key.\r
+ * @param[in] public_k1 The other party's publick key 1.\r
+ * @param[in] public_k2 The other party's publick key 2.\r
+ * @param[out] secret_z The ECC CDH secret Z.\r
+ * @return 0 Success.\r
+ * @return -1 "ecc_curve" value is invalid.\r
+ */\r
+int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[])\r
+{\r
+ int32_t i, ret = 0;\r
+ uint32_t u32Tmp;\r
+\r
+ if(ecc_init_curve(crpt, ecc_curve) != 0)\r
+ {\r
+ ret = -1;\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_K[i] = 0UL;\r
+ crpt->ECC_X1[i] = 0UL;\r
+ crpt->ECC_Y1[i] = 0UL;\r
+ }\r
+\r
+ if((ecc_curve == CURVE_B_163) || (ecc_curve == CURVE_B_233) || (ecc_curve == CURVE_B_283) ||\r
+ (ecc_curve == CURVE_B_409) || (ecc_curve == CURVE_B_571) || (ecc_curve == CURVE_K_163))\r
+ {\r
+ Hex2RegEx(private_k, crpt->ECC_K, 1);\r
+ }\r
+ else if((ecc_curve == CURVE_K_233) || (ecc_curve == CURVE_K_283) ||\r
+ (ecc_curve == CURVE_K_409) || (ecc_curve == CURVE_K_571))\r
+ {\r
+ Hex2RegEx(private_k, crpt->ECC_K, 2);\r
+ }\r
+ else\r
+ {\r
+ Hex2Reg(private_k, crpt->ECC_K);\r
+ }\r
+\r
+ Hex2Reg(public_k1, crpt->ECC_X1);\r
+ Hex2Reg(public_k2, crpt->ECC_Y1);\r
+\r
+ /* set FSEL (Field selection) */\r
+ if(pCurve->GF == (int)CURVE_GF_2M)\r
+ {\r
+ crpt->ECC_CTL = 0UL;\r
+ }\r
+ else /* CURVE_GF_P */\r
+ {\r
+ crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;\r
+ }\r
+ g_ECC_done = g_ECCERR_done = 0UL;\r
+ crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) |\r
+ ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk;\r
+\r
+ do\r
+ {\r
+ u32Tmp = g_ECC_done;\r
+ u32Tmp |= g_ECCERR_done;\r
+ }\r
+ while(u32Tmp == 0UL);\r
+\r
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, secret_z);\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+static void run_ecc_codec(CRPT_T *crpt, uint32_t mode)\r
+{\r
+ uint32_t u32Tmp;\r
+\r
+ if((mode & CRPT_ECC_CTL_ECCOP_Msk) == ECCOP_MODULE)\r
+ {\r
+ crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;\r
+ }\r
+ else\r
+ {\r
+ if(pCurve->GF == (int)CURVE_GF_2M)\r
+ {\r
+ /* point */\r
+ crpt->ECC_CTL = 0UL;\r
+ }\r
+ else\r
+ {\r
+ /* CURVE_GF_P */\r
+ crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;\r
+ }\r
+ }\r
+\r
+ g_ECC_done = g_ECCERR_done = 0UL;\r
+ crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | mode | CRPT_ECC_CTL_START_Msk;\r
+\r
+ do\r
+ {\r
+ u32Tmp = g_ECC_done;\r
+ u32Tmp |= g_ECCERR_done;\r
+ }\r
+ while(u32Tmp == 0UL);\r
+\r
+ while(crpt->ECC_STS & CRPT_ECC_STS_BUSY_Msk) { }\r
+}\r
+\r
+/**\r
+ * @brief ECDSA digital signature generation.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] ecc_curve The pre-defined ECC curve.\r
+ * @param[in] message The hash value of source context.\r
+ * @param[in] d The private key.\r
+ * @param[in] k The selected random integer.\r
+ * @param[out] R R of the (R,S) pair digital signature\r
+ * @param[out] S S of the (R,S) pair digital signature\r
+ * @return 0 Success.\r
+ * @return -1 "ecc_curve" value is invalid.\r
+ */\r
+int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,\r
+ char *d, char *k, char *R, char *S)\r
+{\r
+ uint32_t volatile temp_result1[18], temp_result2[18];\r
+ int32_t i, ret = 0;\r
+\r
+ if(ecc_init_curve(crpt, ecc_curve) != 0)\r
+ {\r
+ ret = -1;\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+\r
+ /*\r
+ * 1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1)\r
+ * (1) Use SHA to calculate e\r
+ */\r
+\r
+ /* 2. Select a random integer k form [1, n-1]\r
+ * (1) Notice that n is order, not prime modulus or irreducible polynomial function\r
+ */\r
+\r
+ /*\r
+ * 3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2\r
+ * (1) Write the curve parameter A, B, and curve length M to corresponding registers\r
+ * (2) Write the prime modulus or irreducible polynomial function to N registers according\r
+ * (3) Write the point G(x, y) to X1, Y1 registers\r
+ * (4) Write the random integer k to K register\r
+ * (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00\r
+ * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field\r
+ * (7) Set START(CRPT_ECC_CTL[0]) to 1\r
+ * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (9) Write the curve order and curve length to N ,M registers according\r
+ * (10) Write 0x0 to Y1 registers\r
+ * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01\r
+ * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10\r
+ * (13) Set START(CRPT_ECC_CTL[0]) to 1 *\r
+ * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (15) Read X1 registers to get r\r
+ */\r
+\r
+ /* 3-(4) Write the random integer k to K register */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_K[i] = 0UL;\r
+ }\r
+ Hex2Reg(k, crpt->ECC_K);\r
+\r
+ run_ecc_codec(crpt, ECCOP_POINT_MUL);\r
+\r
+ /* 3-(9) Write the curve order to N registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_N[i] = 0UL;\r
+ }\r
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);\r
+\r
+ /* 3-(10) Write 0x0 to Y1 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_Y1[i] = 0UL;\r
+ }\r
+\r
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);\r
+\r
+ /* 3-(15) Read X1 registers to get r */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ temp_result1[i] = crpt->ECC_X1[i];\r
+ }\r
+\r
+ Reg2Hex(pCurve->Echar, temp_result1, R);\r
+\r
+ /*\r
+ * 4. Compute s = k ? 1 ¡Ñ (e + d ¡Ñ r)(mod n). If s = 0, go to step 2\r
+ * (1) Write the curve order to N registers according\r
+ * (2) Write 0x1 to Y1 registers\r
+ * (3) Write the random integer k to X1 registers according\r
+ * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01\r
+ * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00\r
+ * (6) Set START(CRPT_ECC_CTL[0]) to 1\r
+ * (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (8) Read X1 registers to get k^-1\r
+ * (9) Write the curve order and curve length to N ,M registers\r
+ * (10) Write r, d to X1, Y1 registers\r
+ * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01\r
+ * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01\r
+ * (13) Set START(CRPT_ECC_CTL[0]) to 1\r
+ * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (15) Write the curve order to N registers\r
+ * (16) Write e to Y1 registers\r
+ * (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01\r
+ * (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10\r
+ * (19) Set START(CRPT_ECC_CTL[0]) to 1\r
+ * (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (21) Write the curve order and curve length to N ,M registers\r
+ * (22) Write k^-1 to Y1 registers\r
+ * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01\r
+ * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01\r
+ * (25) Set START(CRPT_ECC_CTL[0]) to 1\r
+ * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (27) Read X1 registers to get s\r
+ */\r
+\r
+ /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */\r
+\r
+ /* 4-(1) Write the curve order to N registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_N[i] = 0UL;\r
+ }\r
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);\r
+\r
+ /* 4-(2) Write 0x1 to Y1 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_Y1[i] = 0UL;\r
+ }\r
+ crpt->ECC_Y1[0] = 0x1UL;\r
+\r
+ /* 4-(3) Write the random integer k to X1 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_X1[i] = 0UL;\r
+ }\r
+ Hex2Reg(k, crpt->ECC_X1);\r
+\r
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV);\r
+\r
+#if ENABLE_DEBUG\r
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);\r
+ CRPT_DBGMSG("(7) output = %s\n", temp_hex_str);\r
+#endif\r
+\r
+ /* 4-(8) Read X1 registers to get k^-1 */\r
+\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ temp_result2[i] = crpt->ECC_X1[i];\r
+ }\r
+\r
+#if ENABLE_DEBUG\r
+ Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);\r
+ CRPT_DBGMSG("k^-1 = %s\n", temp_hex_str);\r
+#endif\r
+\r
+ /* 4-(9) Write the curve order and curve length to N ,M registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_N[i] = 0UL;\r
+ }\r
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);\r
+\r
+ /* 4-(10) Write r, d to X1, Y1 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_X1[i] = temp_result1[i];\r
+ }\r
+\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_Y1[i] = 0UL;\r
+ }\r
+ Hex2Reg(d, crpt->ECC_Y1);\r
+\r
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);\r
+\r
+#if ENABLE_DEBUG\r
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);\r
+ CRPT_DBGMSG("(14) output = %s\n", temp_hex_str);\r
+#endif\r
+\r
+ /* 4-(15) Write the curve order to N registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_N[i] = 0UL;\r
+ }\r
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);\r
+\r
+ /* 4-(16) Write e to Y1 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_Y1[i] = 0UL;\r
+ }\r
+\r
+ Hex2Reg(message, crpt->ECC_Y1);\r
+\r
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);\r
+\r
+#if ENABLE_DEBUG\r
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);\r
+ CRPT_DBGMSG("(20) output = %s\n", temp_hex_str);\r
+#endif\r
+\r
+ /* 4-(21) Write the curve order and curve length to N ,M registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_N[i] = 0UL;\r
+ }\r
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);\r
+\r
+ /* 4-(22) Write k^-1 to Y1 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_Y1[i] = temp_result2[i];\r
+ }\r
+\r
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);\r
+\r
+ /* 4-(27) Read X1 registers to get s */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ temp_result2[i] = crpt->ECC_X1[i];\r
+ }\r
+\r
+ Reg2Hex(pCurve->Echar, temp_result2, S);\r
+\r
+ } /* ret == 0 */\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief ECDSA dogotal signature verification.\r
+ * @param[in] crpt The pointer of CRYPTO module \r
+ * @param[in] ecc_curve The pre-defined ECC curve.\r
+ * @param[in] message The hash value of source context.\r
+ * @param[in] public_k1 The public key 1.\r
+ * @param[in] public_k2 The public key 2.\r
+ * @param[in] R R of the (R,S) pair digital signature\r
+ * @param[in] S S of the (R,S) pair digital signature\r
+ * @return 0 Success.\r
+ * @return -1 "ecc_curve" value is invalid.\r
+ * @return -2 Verification failed.\r
+ */\r
+int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,\r
+ char *public_k1, char *public_k2, char *R, char *S)\r
+{\r
+ uint32_t temp_result1[18], temp_result2[18];\r
+ uint32_t temp_x[18], temp_y[18];\r
+ int32_t i, ret = 0;\r
+\r
+ /*\r
+ * 1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid\r
+ * 2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation\r
+ * (1) Use SHA to calculate e\r
+ */\r
+\r
+ /*\r
+ * 3. Compute w = s^-1 (mod n)\r
+ * (1) Write the curve order to N registers\r
+ * (2) Write 0x1 to Y1 registers\r
+ * (3) Write s to X1 registers\r
+ * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01\r
+ * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00\r
+ * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field\r
+ * (7) Set START(CRPT_ECC_CTL[0]) to 1\r
+ * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (9) Read X1 registers to get w\r
+ */\r
+\r
+ if(ecc_init_curve(crpt, ecc_curve) != 0)\r
+ {\r
+ ret = -1;\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+\r
+ /* 3-(1) Write the curve order to N registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_N[i] = 0UL;\r
+ }\r
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);\r
+\r
+ /* 3-(2) Write 0x1 to Y1 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_Y1[i] = 0UL;\r
+ }\r
+ crpt->ECC_Y1[0] = 0x1UL;\r
+\r
+ /* 3-(3) Write s to X1 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ CRPT->ECC_X1[i] = 0UL;\r
+ }\r
+ Hex2Reg(S, crpt->ECC_X1);\r
+\r
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV);\r
+\r
+ /* 3-(9) Read X1 registers to get w */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ temp_result2[i] = crpt->ECC_X1[i];\r
+ }\r
+\r
+#if ENABLE_DEBUG\r
+ CRPT_DBGMSG("e = %s\n", message);\r
+ Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);\r
+ CRPT_DBGMSG("w = %s\n", temp_hex_str);\r
+ CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder);\r
+#endif\r
+\r
+ /*\r
+ * 4. Compute u1 = e ¡Ñ w (mod n) and u2 = r ¡Ñ w (mod n)\r
+ * (1) Write the curve order and curve length to N ,M registers\r
+ * (2) Write e, w to X1, Y1 registers\r
+ * (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01\r
+ * (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01\r
+ * (5) Set START(CRPT_ECC_CTL[0]) to 1\r
+ * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (7) Read X1 registers to get u1\r
+ * (8) Write the curve order and curve length to N ,M registers\r
+ * (9) Write r, w to X1, Y1 registers\r
+ * (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01\r
+ * (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01\r
+ * (12) Set START(CRPT_ECC_CTL[0]) to 1\r
+ * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (14) Read X1 registers to get u2\r
+ */\r
+\r
+ /* 4-(1) Write the curve order and curve length to N ,M registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_N[i] = 0UL;\r
+ }\r
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);\r
+\r
+ /* 4-(2) Write e, w to X1, Y1 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_X1[i] = 0UL;\r
+ }\r
+ Hex2Reg(message, crpt->ECC_X1);\r
+\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_Y1[i] = temp_result2[i];\r
+ }\r
+\r
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);\r
+\r
+ /* 4-(7) Read X1 registers to get u1 */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ temp_result1[i] = crpt->ECC_X1[i];\r
+ }\r
+\r
+#if ENABLE_DEBUG\r
+ Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str);\r
+ CRPT_DBGMSG("u1 = %s\n", temp_hex_str);\r
+#endif\r
+\r
+ /* 4-(8) Write the curve order and curve length to N ,M registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_N[i] = 0UL;\r
+ }\r
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);\r
+\r
+ /* 4-(9) Write r, w to X1, Y1 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_X1[i] = 0UL;\r
+ }\r
+ Hex2Reg(R, crpt->ECC_X1);\r
+\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_Y1[i] = temp_result2[i];\r
+ }\r
+\r
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);\r
+\r
+ /* 4-(14) Read X1 registers to get u2 */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ temp_result2[i] = crpt->ECC_X1[i];\r
+ }\r
+\r
+#if ENABLE_DEBUG\r
+ Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);\r
+ CRPT_DBGMSG("u2 = %s\n", temp_hex_str);\r
+#endif\r
+\r
+ /*\r
+ * 5. Compute X¡¦ (x1¡¦, y1¡¦) = u1 * G + u2 * Q\r
+ * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers\r
+ * (2) Write the point G(x, y) to X1, Y1 registers\r
+ * (3) Write u1 to K registers\r
+ * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00\r
+ * (5) Set START(CRPT_ECC_CTL[0]) to 1\r
+ * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (7) Read X1, Y1 registers to get u1*G\r
+ * (8) Write the curve parameter A, B, N, and curve length M to corresponding registers\r
+ * (9) Write the public key Q(x,y) to X1, Y1 registers\r
+ * (10) Write u2 to K registers\r
+ * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00\r
+ * (12) Set START(CRPT_ECC_CTL[0]) to 1\r
+ * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (14) Write the curve parameter A, B, N, and curve length M to corresponding registers\r
+ * (15) Write the result data u1*G to X2, Y2 registers\r
+ * (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10\r
+ * (17) Set START(CRPT_ECC_CTL[0]) to 1\r
+ * (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (19) Read X1, Y1 registers to get X¡¦(x1¡¦, y1¡¦)\r
+ * (20) Write the curve order and curve length to N ,M registers\r
+ * (21) Write x1¡¦ to X1 registers\r
+ * (22) Write 0x0 to Y1 registers\r
+ * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01\r
+ * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10\r
+ * (25) Set START(CRPT_ECC_CTL[0]) to 1\r
+ * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared\r
+ * (27) Read X1 registers to get x1¡¦ (mod n)\r
+ *\r
+ * 6. The signature is valid if x1¡¦ = r, otherwise it is invalid\r
+ */\r
+\r
+ /*\r
+ * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers\r
+ * (2) Write the point G(x, y) to X1, Y1 registers\r
+ */\r
+ ecc_init_curve(crpt, ecc_curve);\r
+\r
+ /* (3) Write u1 to K registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_K[i] = temp_result1[i];\r
+ }\r
+\r
+ run_ecc_codec(crpt, ECCOP_POINT_MUL);\r
+\r
+ /* (7) Read X1, Y1 registers to get u1*G */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ temp_x[i] = crpt->ECC_X1[i];\r
+ temp_y[i] = crpt->ECC_Y1[i];\r
+ }\r
+\r
+#if ENABLE_DEBUG\r
+ Reg2Hex(pCurve->Echar, temp_x, temp_hex_str);\r
+ CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str);\r
+ Reg2Hex(pCurve->Echar, temp_y, temp_hex_str);\r
+ CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str);\r
+#endif\r
+\r
+ /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */\r
+ ecc_init_curve(crpt, ecc_curve);\r
+\r
+ /* (9) Write the public key Q(x,y) to X1, Y1 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_X1[i] = 0UL;\r
+ crpt->ECC_Y1[i] = 0UL;\r
+ }\r
+\r
+ Hex2Reg(public_k1, crpt->ECC_X1);\r
+ Hex2Reg(public_k2, crpt->ECC_Y1);\r
+\r
+ /* (10) Write u2 to K registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_K[i] = temp_result2[i];\r
+ }\r
+\r
+ run_ecc_codec(crpt, ECCOP_POINT_MUL);\r
+\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ temp_result1[i] = crpt->ECC_X1[i];\r
+ temp_result2[i] = crpt->ECC_Y1[i];\r
+ }\r
+\r
+#if ENABLE_DEBUG\r
+ Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str);\r
+ CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str);\r
+ Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);\r
+ CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str);\r
+#endif\r
+\r
+ /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */\r
+ ecc_init_curve(crpt, ecc_curve);\r
+\r
+ /* Write the result data u2*Q to X1, Y1 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_X1[i] = temp_result1[i];\r
+ crpt->ECC_Y1[i] = temp_result2[i];\r
+ }\r
+\r
+ /* (15) Write the result data u1*G to X2, Y2 registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_X2[i] = temp_x[i];\r
+ crpt->ECC_Y2[i] = temp_y[i];\r
+ }\r
+\r
+ run_ecc_codec(crpt, ECCOP_POINT_ADD);\r
+\r
+ /* (19) Read X1, Y1 registers to get X¡¦(x1¡¦, y1¡¦) */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ temp_x[i] = crpt->ECC_X1[i];\r
+ temp_y[i] = crpt->ECC_Y1[i];\r
+ }\r
+\r
+#if ENABLE_DEBUG\r
+ Reg2Hex(pCurve->Echar, temp_x, temp_hex_str);\r
+ CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str);\r
+ Reg2Hex(pCurve->Echar, temp_y, temp_hex_str);\r
+ CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str);\r
+#endif\r
+\r
+ /* (20) Write the curve order and curve length to N ,M registers */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_N[i] = 0UL;\r
+ }\r
+ Hex2Reg(pCurve->Eorder, crpt->ECC_N);\r
+\r
+ /*\r
+ * (21) Write x1¡¦ to X1 registers\r
+ * (22) Write 0x0 to Y1 registers\r
+ */\r
+ for(i = 0; i < 18; i++)\r
+ {\r
+ crpt->ECC_X1[i] = temp_x[i];\r
+ crpt->ECC_Y1[i] = 0UL;\r
+ }\r
+\r
+#if ENABLE_DEBUG\r
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);\r
+ CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str);\r
+ Reg2Hex(pCurve->Echar, crpt->ECC_Y1, temp_hex_str);\r
+ CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str);\r
+#endif\r
+\r
+ run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);\r
+\r
+ /* (27) Read X1 registers to get x1¡¦ (mod n) */\r
+ Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);\r
+ CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str);\r
+\r
+ /* 6. The signature is valid if x1¡¦ = r, otherwise it is invalid */\r
+\r
+ /* Compare with test pattern to check if r is correct or not */\r
+ if(strcasecmp(temp_hex_str, R) != 0)\r
+ {\r
+ CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n");\r
+ CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R);\r
+ ret = -2;\r
+ }\r
+ } /* ret == 0 */\r
+\r
+ return ret;\r
+}\r
+\r
+#if XOM_SUPPORT // To support XOM ready curve table\r
+\r
+int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)\r
+{\r
+ int32_t i;\r
+\r
+ switch(id)\r
+ {\r
+ case CURVE_P_192:\r
+ p32[ 0] = 0x00000000;\r
+ p32[ 1] = 0x00000030;\r
+ for(i = 2; i <= 8; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[ 9] = 0x45464646;\r
+ p32[ 10] = 0x46464646;\r
+ p32[ 11] = 0x46464646;\r
+ p32[ 12] = 0x46464646;\r
+ p32[ 13] = 0x43464646;\r
+ for(i = 14; i <= 37; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 38] = 0x31323436;\r
+ p32[ 39] = 0x39313530;\r
+ p32[ 40] = 0x63393565;\r
+ p32[ 41] = 0x37653038;\r
+ p32[ 42] = 0x37616630;\r
+ p32[ 43] = 0x62613965;\r
+ p32[ 44] = 0x34323237;\r
+ p32[ 45] = 0x39343033;\r
+ p32[ 46] = 0x38626566;\r
+ p32[ 47] = 0x63656564;\r
+ p32[ 48] = 0x36343163;\r
+ p32[ 49] = 0x31623962;\r
+ for(i = 50; i <= 73; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 74] = 0x64383831;\r
+ p32[ 75] = 0x65303861;\r
+ p32[ 76] = 0x30333062;\r
+ p32[ 77] = 0x36663039;\r
+ p32[ 78] = 0x66626337;\r
+ p32[ 79] = 0x62653032;\r
+ p32[ 80] = 0x31613334;\r
+ p32[ 81] = 0x30303838;\r
+ p32[ 82] = 0x66663466;\r
+ p32[ 83] = 0x64666130;\r
+ p32[ 84] = 0x66663238;\r
+ p32[ 85] = 0x32313031;\r
+ for(i = 86; i <= 109; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[110] = 0x39313730;\r
+ p32[111] = 0x35396232;\r
+ p32[112] = 0x38636666;\r
+ p32[113] = 0x38376164;\r
+ p32[114] = 0x30313336;\r
+ p32[115] = 0x64653131;\r
+ p32[116] = 0x34326236;\r
+ p32[117] = 0x35646463;\r
+ p32[118] = 0x39663337;\r
+ p32[119] = 0x31613737;\r
+ p32[120] = 0x39376531;\r
+ p32[121] = 0x31313834;\r
+ for(i = 122; i <= 145; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[146] = 0x0000003a;\r
+ for(i = 147; i <= 153; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[154] = 0x45464646;\r
+ for(i = 155; i <= 158; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 159; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x0000003a;\r
+ for(i = 192; i <= 197; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[198] = 0x45443939;\r
+ p32[199] = 0x36333846;\r
+ p32[200] = 0x42363431;\r
+ p32[201] = 0x31423943;\r
+ p32[202] = 0x32443442;\r
+ p32[203] = 0x31333832;\r
+ for(i = 204; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x000000c0;\r
+ p32[237] = 0x00000007;\r
+ p32[238] = 0x00000002;\r
+ p32[239] = 0x00000001;\r
+ p32[240] = 0x00000000;\r
+ break;\r
+ case CURVE_P_224:\r
+ p32[ 0] = 0x00000001;\r
+ p32[ 1] = 0x00000038;\r
+ for(i = 2; i <= 8; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[ 9] = 0x45464646;\r
+ for(i = 10; i <= 14; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[ 15] = 0x45464646;\r
+ for(i = 16; i <= 37; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 38] = 0x35303462;\r
+ p32[ 39] = 0x35386130;\r
+ p32[ 40] = 0x34306330;\r
+ p32[ 41] = 0x62613362;\r
+ p32[ 42] = 0x31343566;\r
+ p32[ 43] = 0x36353233;\r
+ p32[ 44] = 0x34343035;\r
+ p32[ 45] = 0x37623062;\r
+ p32[ 46] = 0x66623764;\r
+ p32[ 47] = 0x61623864;\r
+ p32[ 48] = 0x62303732;\r
+ p32[ 49] = 0x33343933;\r
+ p32[ 50] = 0x35353332;\r
+ p32[ 51] = 0x34626666;\r
+ for(i = 52; i <= 73; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 74] = 0x65303762;\r
+ p32[ 75] = 0x64626330;\r
+ p32[ 76] = 0x34626236;\r
+ p32[ 77] = 0x66376662;\r
+ p32[ 78] = 0x33313233;\r
+ p32[ 79] = 0x39623039;\r
+ p32[ 80] = 0x33306134;\r
+ p32[ 81] = 0x33643163;\r
+ p32[ 82] = 0x32633635;\r
+ p32[ 83] = 0x32323131;\r
+ p32[ 84] = 0x32333433;\r
+ p32[ 85] = 0x36643038;\r
+ p32[ 86] = 0x63353131;\r
+ p32[ 87] = 0x31326431;\r
+ for(i = 88; i <= 109; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[110] = 0x37336462;\r
+ p32[111] = 0x38383336;\r
+ p32[112] = 0x37663562;\r
+ p32[113] = 0x62663332;\r
+ p32[114] = 0x32326334;\r
+ p32[115] = 0x36656664;\r
+ p32[116] = 0x33346463;\r
+ p32[117] = 0x30613537;\r
+ p32[118] = 0x37306135;\r
+ p32[119] = 0x34363734;\r
+ p32[120] = 0x35643434;\r
+ p32[121] = 0x39393138;\r
+ p32[122] = 0x30303538;\r
+ p32[123] = 0x34336537;\r
+ for(i = 124; i <= 145; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[146] = 0x00000046;\r
+ for(i = 147; i <= 154; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 155; i <= 159; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[160] = 0x31303030;\r
+ for(i = 161; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x00000046;\r
+ for(i = 192; i <= 198; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[199] = 0x32413631;\r
+ p32[200] = 0x38423045;\r
+ p32[201] = 0x45333046;\r
+ p32[202] = 0x44443331;\r
+ p32[203] = 0x35343932;\r
+ p32[204] = 0x43354335;\r
+ p32[205] = 0x44334132;\r
+ for(i = 206; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x000000e0;\r
+ p32[237] = 0x00000009;\r
+ p32[238] = 0x00000008;\r
+ p32[239] = 0x00000003;\r
+ p32[240] = 0x00000000;\r
+ break;\r
+ case CURVE_P_256:\r
+ p32[ 0] = 0x00000002;\r
+ p32[ 1] = 0x00000040;\r
+ p32[ 2] = 0x46464646;\r
+ p32[ 3] = 0x46464646;\r
+ p32[ 4] = 0x30303030;\r
+ p32[ 5] = 0x31303030;\r
+ for(i = 6; i <= 11; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ for(i = 12; i <= 16; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[ 17] = 0x43464646;\r
+ for(i = 18; i <= 37; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 38] = 0x36636135;\r
+ p32[ 39] = 0x38643533;\r
+ p32[ 40] = 0x61336161;\r
+ p32[ 41] = 0x37653339;\r
+ p32[ 42] = 0x62653362;\r
+ p32[ 43] = 0x35356462;\r
+ p32[ 44] = 0x38393637;\r
+ p32[ 45] = 0x63623638;\r
+ p32[ 46] = 0x64313536;\r
+ p32[ 47] = 0x30623630;\r
+ p32[ 48] = 0x33356363;\r
+ p32[ 49] = 0x36663062;\r
+ p32[ 50] = 0x65636233;\r
+ p32[ 51] = 0x65336333;\r
+ p32[ 52] = 0x32643732;\r
+ p32[ 53] = 0x62343036;\r
+ for(i = 54; i <= 73; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 74] = 0x37316236;\r
+ p32[ 75] = 0x32663164;\r
+ p32[ 76] = 0x63323165;\r
+ p32[ 77] = 0x37343234;\r
+ p32[ 78] = 0x63623866;\r
+ p32[ 79] = 0x35653665;\r
+ p32[ 80] = 0x34613336;\r
+ p32[ 81] = 0x32663034;\r
+ p32[ 82] = 0x33303737;\r
+ p32[ 83] = 0x31386437;\r
+ p32[ 84] = 0x62656432;\r
+ p32[ 85] = 0x30613333;\r
+ p32[ 86] = 0x31613466;\r
+ p32[ 87] = 0x35343933;\r
+ p32[ 88] = 0x38393864;\r
+ p32[ 89] = 0x36393263;\r
+ for(i = 90; i <= 109; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[110] = 0x33656634;\r
+ p32[111] = 0x32653234;\r
+ p32[112] = 0x61316566;\r
+ p32[113] = 0x62396637;\r
+ p32[114] = 0x37656538;\r
+ p32[115] = 0x61346265;\r
+ p32[116] = 0x66306337;\r
+ p32[117] = 0x36316539;\r
+ p32[118] = 0x65636232;\r
+ p32[119] = 0x37353333;\r
+ p32[120] = 0x31336236;\r
+ p32[121] = 0x65636535;\r
+ p32[122] = 0x36626263;\r
+ p32[123] = 0x38363034;\r
+ p32[124] = 0x66623733;\r
+ p32[125] = 0x35663135;\r
+ for(i = 126; i <= 145; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[146] = 0x0000004e;\r
+ p32[147] = 0x46464646;\r
+ p32[148] = 0x46464646;\r
+ p32[149] = 0x30303030;\r
+ p32[150] = 0x31303030;\r
+ for(i = 151; i <= 156; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ for(i = 157; i <= 162; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 163; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x0000004e;\r
+ p32[192] = 0x46464646;\r
+ p32[193] = 0x46464646;\r
+ p32[194] = 0x30303030;\r
+ p32[195] = 0x30303030;\r
+ for(i = 196; i <= 199; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[200] = 0x36454342;\r
+ p32[201] = 0x44414146;\r
+ p32[202] = 0x37313741;\r
+ p32[203] = 0x34384539;\r
+ p32[204] = 0x39423346;\r
+ p32[205] = 0x32434143;\r
+ p32[206] = 0x33364346;\r
+ p32[207] = 0x31353532;\r
+ for(i = 208; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x00000100;\r
+ p32[237] = 0x0000000a;\r
+ p32[238] = 0x00000005;\r
+ p32[239] = 0x00000002;\r
+ p32[240] = 0x00000000;\r
+ break;\r
+ case CURVE_P_384:\r
+ p32[ 0] = 0x00000003;\r
+ p32[ 1] = 0x00000060;\r
+ for(i = 2; i <= 16; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[ 17] = 0x45464646;\r
+ p32[ 18] = 0x46464646;\r
+ p32[ 19] = 0x46464646;\r
+ for(i = 20; i <= 23; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 24] = 0x46464646;\r
+ p32[ 25] = 0x43464646;\r
+ for(i = 26; i <= 37; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 38] = 0x31333362;\r
+ p32[ 39] = 0x37616632;\r
+ p32[ 40] = 0x65333265;\r
+ p32[ 41] = 0x34653765;\r
+ p32[ 42] = 0x65383839;\r
+ p32[ 43] = 0x62363530;\r
+ p32[ 44] = 0x38663365;\r
+ p32[ 45] = 0x39316432;\r
+ p32[ 46] = 0x64313831;\r
+ p32[ 47] = 0x65366339;\r
+ p32[ 48] = 0x31386566;\r
+ p32[ 49] = 0x32313134;\r
+ p32[ 50] = 0x34313330;\r
+ p32[ 51] = 0x66383830;\r
+ p32[ 52] = 0x33313035;\r
+ p32[ 53] = 0x61353738;\r
+ p32[ 54] = 0x36353663;\r
+ p32[ 55] = 0x64383933;\r
+ p32[ 56] = 0x65326138;\r
+ p32[ 57] = 0x64393164;\r
+ p32[ 58] = 0x35386132;\r
+ p32[ 59] = 0x64653863;\r
+ p32[ 60] = 0x63653364;\r
+ p32[ 61] = 0x66656132;\r
+ for(i = 62; i <= 73; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 74] = 0x37386161;\r
+ p32[ 75] = 0x32326163;\r
+ p32[ 76] = 0x62386562;\r
+ p32[ 77] = 0x37333530;\r
+ p32[ 78] = 0x31626538;\r
+ p32[ 79] = 0x65313763;\r
+ p32[ 80] = 0x30323366;\r
+ p32[ 81] = 0x34376461;\r
+ p32[ 82] = 0x64316536;\r
+ p32[ 83] = 0x32366233;\r
+ p32[ 84] = 0x37616238;\r
+ p32[ 85] = 0x38396239;\r
+ p32[ 86] = 0x37663935;\r
+ p32[ 87] = 0x30653134;\r
+ p32[ 88] = 0x34353238;\r
+ p32[ 89] = 0x38336132;\r
+ p32[ 90] = 0x32303535;\r
+ p32[ 91] = 0x64353266;\r
+ p32[ 92] = 0x35356662;\r
+ p32[ 93] = 0x63363932;\r
+ p32[ 94] = 0x34356133;\r
+ p32[ 95] = 0x38336535;\r
+ p32[ 96] = 0x36373237;\r
+ p32[ 97] = 0x37626130;\r
+ for(i = 98; i <= 109; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[110] = 0x37313633;\r
+ p32[111] = 0x61346564;\r
+ p32[112] = 0x36323639;\r
+ p32[113] = 0x66366332;\r
+ p32[114] = 0x65396435;\r
+ p32[115] = 0x66623839;\r
+ p32[116] = 0x32393239;\r
+ p32[117] = 0x39326364;\r
+ p32[118] = 0x34663866;\r
+ p32[119] = 0x64626431;\r
+ p32[120] = 0x61393832;\r
+ p32[121] = 0x63373431;\r
+ p32[122] = 0x61643965;\r
+ p32[123] = 0x33313133;\r
+ p32[124] = 0x30663562;\r
+ p32[125] = 0x30633862;\r
+ p32[126] = 0x30366130;\r
+ p32[127] = 0x65633162;\r
+ p32[128] = 0x65376431;\r
+ p32[129] = 0x64393138;\r
+ p32[130] = 0x33346137;\r
+ p32[131] = 0x63376431;\r
+ p32[132] = 0x61653039;\r
+ p32[133] = 0x66356530;\r
+ for(i = 134; i <= 145; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[146] = 0x00000074;\r
+ for(i = 147; i <= 161; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[162] = 0x45464646;\r
+ p32[163] = 0x46464646;\r
+ p32[164] = 0x46464646;\r
+ for(i = 165; i <= 168; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[169] = 0x46464646;\r
+ p32[170] = 0x46464646;\r
+ for(i = 171; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x00000074;\r
+ for(i = 192; i <= 203; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[204] = 0x33363743;\r
+ p32[205] = 0x31384434;\r
+ p32[206] = 0x37333446;\r
+ p32[207] = 0x46444432;\r
+ p32[208] = 0x41313835;\r
+ p32[209] = 0x32424430;\r
+ p32[210] = 0x30423834;\r
+ p32[211] = 0x41373741;\r
+ p32[212] = 0x43454345;\r
+ p32[213] = 0x41363931;\r
+ p32[214] = 0x35434343;\r
+ p32[215] = 0x33373932;\r
+ for(i = 216; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x00000180;\r
+ p32[237] = 0x0000000c;\r
+ p32[238] = 0x00000003;\r
+ p32[239] = 0x00000002;\r
+ p32[240] = 0x00000000;\r
+ break;\r
+ case CURVE_P_521:\r
+ p32[ 0] = 0x00000004;\r
+ p32[ 1] = 0x00000083;\r
+ p32[ 2] = 0x46464631;\r
+ for(i = 3; i <= 33; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[ 34] = 0x00434646;\r
+ p32[ 35] = 0x00000000;\r
+ p32[ 36] = 0x00000000;\r
+ p32[ 37] = 0x00000000;\r
+ p32[ 38] = 0x39313530;\r
+ p32[ 39] = 0x62653335;\r
+ p32[ 40] = 0x38313639;\r
+ p32[ 41] = 0x39633165;\r
+ p32[ 42] = 0x39663161;\r
+ p32[ 43] = 0x32613932;\r
+ p32[ 44] = 0x62306131;\r
+ p32[ 45] = 0x34353836;\r
+ p32[ 46] = 0x61656530;\r
+ p32[ 47] = 0x37616432;\r
+ p32[ 48] = 0x39623532;\r
+ p32[ 49] = 0x31336239;\r
+ p32[ 50] = 0x62336635;\r
+ p32[ 51] = 0x38346238;\r
+ p32[ 52] = 0x38313939;\r
+ p32[ 53] = 0x30316665;\r
+ p32[ 54] = 0x35316539;\r
+ p32[ 55] = 0x33393136;\r
+ p32[ 56] = 0x65313539;\r
+ p32[ 57] = 0x39653763;\r
+ p32[ 58] = 0x31623733;\r
+ p32[ 59] = 0x63323536;\r
+ p32[ 60] = 0x33646230;\r
+ p32[ 61] = 0x62316262;\r
+ p32[ 62] = 0x33373066;\r
+ p32[ 63] = 0x64333735;\r
+ p32[ 64] = 0x33383866;\r
+ p32[ 65] = 0x33633264;\r
+ p32[ 66] = 0x65316634;\r
+ p32[ 67] = 0x31353466;\r
+ p32[ 68] = 0x36346466;\r
+ p32[ 69] = 0x33303562;\r
+ p32[ 70] = 0x00303066;\r
+ p32[ 71] = 0x00000000;\r
+ p32[ 72] = 0x00000000;\r
+ p32[ 73] = 0x00000000;\r
+ p32[ 74] = 0x38366330;\r
+ p32[ 75] = 0x30653835;\r
+ p32[ 76] = 0x30376236;\r
+ p32[ 77] = 0x65343034;\r
+ p32[ 78] = 0x39646339;\r
+ p32[ 79] = 0x63653365;\r
+ p32[ 80] = 0x32363662;\r
+ p32[ 81] = 0x62353933;\r
+ p32[ 82] = 0x39323434;\r
+ p32[ 83] = 0x38343663;\r
+ p32[ 84] = 0x30393331;\r
+ p32[ 85] = 0x62663335;\r
+ p32[ 86] = 0x66313235;\r
+ p32[ 87] = 0x61383238;\r
+ p32[ 88] = 0x36303666;\r
+ p32[ 89] = 0x33643462;\r
+ p32[ 90] = 0x61616264;\r
+ p32[ 91] = 0x35623431;\r
+ p32[ 92] = 0x65373765;\r
+ p32[ 93] = 0x35376566;\r
+ p32[ 94] = 0x66383239;\r
+ p32[ 95] = 0x63643165;\r
+ p32[ 96] = 0x61373231;\r
+ p32[ 97] = 0x61666632;\r
+ p32[ 98] = 0x33656438;\r
+ p32[ 99] = 0x62383433;\r
+ p32[100] = 0x38316333;\r
+ p32[101] = 0x34613635;\r
+ p32[102] = 0x66623932;\r
+ p32[103] = 0x37653739;\r
+ p32[104] = 0x63313365;\r
+ p32[105] = 0x62356532;\r
+ p32[106] = 0x00363664;\r
+ p32[107] = 0x00000000;\r
+ p32[108] = 0x00000000;\r
+ p32[109] = 0x00000000;\r
+ p32[110] = 0x33383131;\r
+ p32[111] = 0x36393239;\r
+ p32[112] = 0x39383761;\r
+ p32[113] = 0x63623361;\r
+ p32[114] = 0x35343030;\r
+ p32[115] = 0x35613863;\r
+ p32[116] = 0x32346266;\r
+ p32[117] = 0x31643763;\r
+ p32[118] = 0x39396462;\r
+ p32[119] = 0x34356638;\r
+ p32[120] = 0x35393434;\r
+ p32[121] = 0x34623937;\r
+ p32[122] = 0x31383634;\r
+ p32[123] = 0x62666137;\r
+ p32[124] = 0x32373164;\r
+ p32[125] = 0x36653337;\r
+ p32[126] = 0x39633236;\r
+ p32[127] = 0x37656537;\r
+ p32[128] = 0x35393932;\r
+ p32[129] = 0x32346665;\r
+ p32[130] = 0x63303436;\r
+ p32[131] = 0x62303535;\r
+ p32[132] = 0x33313039;\r
+ p32[133] = 0x30646166;\r
+ p32[134] = 0x33313637;\r
+ p32[135] = 0x37633335;\r
+ p32[136] = 0x61363830;\r
+ p32[137] = 0x63323732;\r
+ p32[138] = 0x38303432;\r
+ p32[139] = 0x39656238;\r
+ p32[140] = 0x39363734;\r
+ p32[141] = 0x36316466;\r
+ p32[142] = 0x00303536;\r
+ p32[143] = 0x00000000;\r
+ p32[144] = 0x00000000;\r
+ p32[145] = 0x00000000;\r
+ p32[146] = 0x0000009d;\r
+ p32[147] = 0x46464631;\r
+ for(i = 148; i <= 178; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[179] = 0x00464646;\r
+ for(i = 180; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x0000009d;\r
+ p32[192] = 0x46464631;\r
+ for(i = 193; i <= 207; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[208] = 0x35414646;\r
+ p32[209] = 0x38363831;\r
+ p32[210] = 0x42333837;\r
+ p32[211] = 0x39463246;\r
+ p32[212] = 0x37423636;\r
+ p32[213] = 0x30434346;\r
+ p32[214] = 0x46383431;\r
+ p32[215] = 0x41393037;\r
+ p32[216] = 0x33304435;\r
+ p32[217] = 0x43354242;\r
+ p32[218] = 0x38384239;\r
+ p32[219] = 0x34433939;\r
+ p32[220] = 0x42454137;\r
+ p32[221] = 0x42463642;\r
+ p32[222] = 0x39453137;\r
+ p32[223] = 0x36383331;\r
+ p32[224] = 0x00393034;\r
+ for(i = 225; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x00000209;\r
+ p32[237] = 0x00000020;\r
+ p32[238] = 0x00000020;\r
+ p32[239] = 0x00000020;\r
+ p32[240] = 0x00000000;\r
+ break;\r
+ case CURVE_B_163:\r
+ p32[ 0] = 0x0000000a;\r
+ p32[ 1] = 0x00000029;\r
+ for(i = 2; i <= 11; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 12] = 0x00000031;\r
+ for(i = 13; i <= 37; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 38] = 0x36613032;\r
+ p32[ 39] = 0x30393130;\r
+ p32[ 40] = 0x63386237;\r
+ p32[ 41] = 0x63333539;\r
+ p32[ 42] = 0x38343161;\r
+ p32[ 43] = 0x31626531;\r
+ p32[ 44] = 0x32313530;\r
+ p32[ 45] = 0x37383766;\r
+ p32[ 46] = 0x33613434;\r
+ p32[ 47] = 0x66353032;\r
+ p32[ 48] = 0x00000064;\r
+ for(i = 49; i <= 73; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 74] = 0x65306633;\r
+ p32[ 75] = 0x36316162;\r
+ p32[ 76] = 0x61363832;\r
+ p32[ 77] = 0x37356432;\r
+ p32[ 78] = 0x39306165;\r
+ p32[ 79] = 0x36313139;\r
+ p32[ 80] = 0x39346438;\r
+ p32[ 81] = 0x33363439;\r
+ p32[ 82] = 0x33386537;\r
+ p32[ 83] = 0x33653334;\r
+ p32[ 84] = 0x00000036;\r
+ for(i = 85; i <= 109; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[110] = 0x31356430;\r
+ p32[111] = 0x36636266;\r
+ p32[112] = 0x61313763;\r
+ p32[113] = 0x34393030;\r
+ p32[114] = 0x63326166;\r
+ p32[115] = 0x34356464;\r
+ p32[116] = 0x31316235;\r
+ p32[117] = 0x30633563;\r
+ p32[118] = 0x37393763;\r
+ p32[119] = 0x66343233;\r
+ p32[120] = 0x00000031;\r
+ for(i = 121; i <= 145; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[146] = 0x00000044;\r
+ for(i = 147; i <= 154; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 155; i <= 159; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[160] = 0x31303030;\r
+ for(i = 161; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x00000031;\r
+ p32[192] = 0x30303034;\r
+ for(i = 193; i <= 196; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[197] = 0x46323932;\r
+ p32[198] = 0x45373745;\r
+ p32[199] = 0x31433037;\r
+ p32[200] = 0x32344132;\r
+ p32[201] = 0x33433433;\r
+ p32[202] = 0x00000033;\r
+ for(i = 203; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x000000a3;\r
+ p32[237] = 0x00000007;\r
+ p32[238] = 0x00000006;\r
+ p32[239] = 0x00000003;\r
+ p32[240] = 0x00000001;\r
+ break;\r
+ case CURVE_B_233:\r
+ p32[ 0] = 0x0000000b;\r
+ p32[ 1] = 0x0000003b;\r
+ for(i = 2; i <= 15; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 16] = 0x00313030;\r
+ for(i = 17; i <= 37; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 38] = 0x36363630;\r
+ p32[ 39] = 0x64653734;\r
+ p32[ 40] = 0x33633665;\r
+ p32[ 41] = 0x37633233;\r
+ p32[ 42] = 0x30633866;\r
+ p32[ 43] = 0x62333239;\r
+ p32[ 44] = 0x32383562;\r
+ p32[ 45] = 0x33623331;\r
+ p32[ 46] = 0x32623333;\r
+ p32[ 47] = 0x63396530;\r
+ p32[ 48] = 0x38323465;\r
+ p32[ 49] = 0x31656631;\r
+ p32[ 50] = 0x37663531;\r
+ p32[ 51] = 0x39663864;\r
+ p32[ 52] = 0x00646130;\r
+ for(i = 53; i <= 73; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 74] = 0x63616630;\r
+ p32[ 75] = 0x63666439;\r
+ p32[ 76] = 0x38636162;\r
+ p32[ 77] = 0x62333133;\r
+ p32[ 78] = 0x33313262;\r
+ p32[ 79] = 0x62316639;\r
+ p32[ 80] = 0x35353762;\r
+ p32[ 81] = 0x36666566;\r
+ p32[ 82] = 0x33636235;\r
+ p32[ 83] = 0x38663139;\r
+ p32[ 84] = 0x66363362;\r
+ p32[ 85] = 0x65386638;\r
+ p32[ 86] = 0x37333762;\r
+ p32[ 87] = 0x35646631;\r
+ p32[ 88] = 0x00623835;\r
+ for(i = 89; i <= 109; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[110] = 0x36303031;\r
+ p32[111] = 0x61383061;\r
+ p32[112] = 0x30393134;\r
+ p32[113] = 0x30353333;\r
+ p32[114] = 0x65383736;\r
+ p32[115] = 0x32353835;\r
+ p32[116] = 0x62656238;\r
+ p32[117] = 0x30613866;\r
+ p32[118] = 0x66666562;\r
+ p32[119] = 0x61373638;\r
+ p32[120] = 0x33616337;\r
+ p32[121] = 0x36313736;\r
+ p32[122] = 0x30653766;\r
+ p32[123] = 0x31386631;\r
+ p32[124] = 0x00323530;\r
+ for(i = 125; i <= 145; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[146] = 0x00000044;\r
+ for(i = 147; i <= 154; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 155; i <= 159; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[160] = 0x31303030;\r
+ for(i = 161; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x00000046;\r
+ p32[192] = 0x30303031;\r
+ for(i = 193; i <= 198; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[199] = 0x45333130;\r
+ p32[200] = 0x45343739;\r
+ p32[201] = 0x38463237;\r
+ p32[202] = 0x32393641;\r
+ p32[203] = 0x31333032;\r
+ p32[204] = 0x30363244;\r
+ p32[205] = 0x45464333;\r
+ p32[206] = 0x00374430;\r
+ for(i = 207; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x000000e9;\r
+ p32[237] = 0x0000004a;\r
+ p32[238] = 0x0000004a;\r
+ p32[239] = 0x0000004a;\r
+ p32[240] = 0x00000001;\r
+ break;\r
+ case CURVE_B_283:\r
+ p32[ 0] = 0x0000000c;\r
+ p32[ 1] = 0x00000047;\r
+ for(i = 2; i <= 18; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 19] = 0x00313030;\r
+ for(i = 20; i <= 37; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 38] = 0x36623732;\r
+ p32[ 39] = 0x63613038;\r
+ p32[ 40] = 0x35386238;\r
+ p32[ 41] = 0x61643639;\r
+ p32[ 42] = 0x61346135;\r
+ p32[ 43] = 0x31613866;\r
+ p32[ 44] = 0x33306139;\r
+ p32[ 45] = 0x63663330;\r
+ p32[ 46] = 0x66373961;\r
+ p32[ 47] = 0x34363764;\r
+ p32[ 48] = 0x39303335;\r
+ p32[ 49] = 0x61326166;\r
+ p32[ 50] = 0x34313835;\r
+ p32[ 51] = 0x66613538;\r
+ p32[ 52] = 0x33363236;\r
+ p32[ 53] = 0x33313365;\r
+ p32[ 54] = 0x61393762;\r
+ p32[ 55] = 0x00356632;\r
+ for(i = 56; i <= 73; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 74] = 0x33396635;\r
+ p32[ 75] = 0x38353239;\r
+ p32[ 76] = 0x64376264;\r
+ p32[ 77] = 0x65303964;\r
+ p32[ 78] = 0x34333931;\r
+ p32[ 79] = 0x37633866;\r
+ p32[ 80] = 0x64306230;\r
+ p32[ 81] = 0x32636566;\r
+ p32[ 82] = 0x32646565;\r
+ p32[ 83] = 0x35386235;\r
+ p32[ 84] = 0x61653735;\r
+ p32[ 85] = 0x38633963;\r
+ p32[ 86] = 0x65326530;\r
+ p32[ 87] = 0x66383931;\r
+ p32[ 88] = 0x62646338;\r
+ p32[ 89] = 0x38646365;\r
+ p32[ 90] = 0x32316236;\r
+ p32[ 91] = 0x00333530;\r
+ for(i = 92; i <= 109; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[110] = 0x36373633;\r
+ p32[111] = 0x66343538;\r
+ p32[112] = 0x31343265;\r
+ p32[113] = 0x62633134;\r
+ p32[114] = 0x65663839;\r
+ p32[115] = 0x62346436;\r
+ p32[116] = 0x30643032;\r
+ p32[117] = 0x35346232;\r
+ p32[118] = 0x66663631;\r
+ p32[119] = 0x33323037;\r
+ p32[120] = 0x64653035;\r
+ p32[121] = 0x38306264;\r
+ p32[122] = 0x37373632;\r
+ p32[123] = 0x31386339;\r
+ p32[124] = 0x64306633;\r
+ p32[125] = 0x62353466;\r
+ p32[126] = 0x31313865;\r
+ p32[127] = 0x00346632;\r
+ for(i = 128; i <= 145; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[146] = 0x00000044;\r
+ for(i = 147; i <= 154; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 155; i <= 159; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[160] = 0x31303030;\r
+ for(i = 161; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x00000055;\r
+ p32[192] = 0x46464633;\r
+ for(i = 193; i <= 199; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[200] = 0x45464646;\r
+ p32[201] = 0x33303946;\r
+ p32[202] = 0x36363939;\r
+ p32[203] = 0x39434630;\r
+ p32[204] = 0x39413833;\r
+ p32[205] = 0x35363130;\r
+ p32[206] = 0x32343042;\r
+ p32[207] = 0x45433741;\r
+ p32[208] = 0x42444146;\r
+ p32[209] = 0x00373033;\r
+ for(i = 210; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x0000011b;\r
+ p32[237] = 0x0000000c;\r
+ p32[238] = 0x00000007;\r
+ p32[239] = 0x00000005;\r
+ p32[240] = 0x00000001;\r
+ break;\r
+ case CURVE_B_409:\r
+ p32[ 0] = 0x0000000d;\r
+ p32[ 1] = 0x00000067;\r
+ for(i = 2; i <= 26; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 27] = 0x00313030;\r
+ for(i = 28; i <= 37; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 38] = 0x61313230;\r
+ p32[ 39] = 0x63326335;\r
+ p32[ 40] = 0x39656538;\r
+ p32[ 41] = 0x35626566;\r
+ p32[ 42] = 0x39623463;\r
+ p32[ 43] = 0x33353761;\r
+ p32[ 44] = 0x34623762;\r
+ p32[ 45] = 0x37623637;\r
+ p32[ 46] = 0x34366466;\r
+ p32[ 47] = 0x66653232;\r
+ p32[ 48] = 0x64336631;\r
+ p32[ 49] = 0x34373664;\r
+ p32[ 50] = 0x66313637;\r
+ p32[ 51] = 0x64393961;\r
+ p32[ 52] = 0x32636136;\r
+ p32[ 53] = 0x61386337;\r
+ p32[ 54] = 0x39316139;\r
+ p32[ 55] = 0x37326237;\r
+ p32[ 56] = 0x32323832;\r
+ p32[ 57] = 0x64633666;\r
+ p32[ 58] = 0x35613735;\r
+ p32[ 59] = 0x34616135;\r
+ p32[ 60] = 0x61303566;\r
+ p32[ 61] = 0x37313365;\r
+ p32[ 62] = 0x35333162;\r
+ p32[ 63] = 0x00663534;\r
+ for(i = 64; i <= 73; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 74] = 0x34643531;\r
+ p32[ 75] = 0x64303638;\r
+ p32[ 76] = 0x64383830;\r
+ p32[ 77] = 0x34336264;\r
+ p32[ 78] = 0x30623639;\r
+ p32[ 79] = 0x36303663;\r
+ p32[ 80] = 0x36353734;\r
+ p32[ 81] = 0x34303632;\r
+ p32[ 82] = 0x64633134;\r
+ p32[ 83] = 0x66613465;\r
+ p32[ 84] = 0x31373731;\r
+ p32[ 85] = 0x62643464;\r
+ p32[ 86] = 0x66663130;\r
+ p32[ 87] = 0x33623565;\r
+ p32[ 88] = 0x39356534;\r
+ p32[ 89] = 0x64333037;\r
+ p32[ 90] = 0x35353263;\r
+ p32[ 91] = 0x38363861;\r
+ p32[ 92] = 0x38313161;\r
+ p32[ 93] = 0x35313530;\r
+ p32[ 94] = 0x61333036;\r
+ p32[ 95] = 0x36626165;\r
+ p32[ 96] = 0x34393730;\r
+ p32[ 97] = 0x62343565;\r
+ p32[ 98] = 0x39393762;\r
+ p32[ 99] = 0x00376136;\r
+ for(i = 100; i <= 109; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[110] = 0x62313630;\r
+ p32[111] = 0x61666331;\r
+ p32[112] = 0x65623662;\r
+ p32[113] = 0x32336635;\r
+ p32[114] = 0x61666262;\r
+ p32[115] = 0x32333837;\r
+ p32[116] = 0x31646534;\r
+ p32[117] = 0x37613630;\r
+ p32[118] = 0x62363336;\r
+ p32[119] = 0x61356339;\r
+ p32[120] = 0x31646237;\r
+ p32[121] = 0x30643839;\r
+ p32[122] = 0x61383531;\r
+ p32[123] = 0x35663461;\r
+ p32[124] = 0x64383834;\r
+ p32[125] = 0x33663830;\r
+ p32[126] = 0x34313538;\r
+ p32[127] = 0x64663166;\r
+ p32[128] = 0x34623466;\r
+ p32[129] = 0x64303466;\r
+ p32[130] = 0x31383132;\r
+ p32[131] = 0x38363362;\r
+ p32[132] = 0x36336331;\r
+ p32[133] = 0x30616234;\r
+ p32[134] = 0x63333732;\r
+ p32[135] = 0x00363037;\r
+ for(i = 136; i <= 145; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[146] = 0x00000044;\r
+ for(i = 147; i <= 154; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 155; i <= 159; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[160] = 0x31303030;\r
+ for(i = 161; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x0000007b;\r
+ p32[192] = 0x30303031;\r
+ for(i = 193; i <= 204; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[205] = 0x41324531;\r
+ p32[206] = 0x41364441;\r
+ p32[207] = 0x46323136;\r
+ p32[208] = 0x30333333;\r
+ p32[209] = 0x35454237;\r
+ p32[210] = 0x37344146;\r
+ p32[211] = 0x39433343;\r
+ p32[212] = 0x32353045;\r
+ p32[213] = 0x38333846;\r
+ p32[214] = 0x43343631;\r
+ p32[215] = 0x44373344;\r
+ p32[216] = 0x31324139;\r
+ p32[217] = 0x00333731;\r
+ for(i = 218; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x00000199;\r
+ p32[237] = 0x00000057;\r
+ p32[238] = 0x00000057;\r
+ p32[239] = 0x00000057;\r
+ p32[240] = 0x00000001;\r
+ break;\r
+ case CURVE_B_571:\r
+ p32[ 0] = 0x0000000e;\r
+ p32[ 1] = 0x0000008f;\r
+ for(i = 2; i <= 36; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 37] = 0x00313030;\r
+ p32[ 38] = 0x30346632;\r
+ p32[ 39] = 0x32653765;\r
+ p32[ 40] = 0x66313232;\r
+ p32[ 41] = 0x64353932;\r
+ p32[ 42] = 0x37393265;\r
+ p32[ 43] = 0x62373131;\r
+ p32[ 44] = 0x64336637;\r
+ p32[ 45] = 0x35663236;\r
+ p32[ 46] = 0x39613663;\r
+ p32[ 47] = 0x63666637;\r
+ p32[ 48] = 0x65633862;\r
+ p32[ 49] = 0x63316666;\r
+ p32[ 50] = 0x61623664;\r
+ p32[ 51] = 0x34656338;\r
+ p32[ 52] = 0x31613961;\r
+ p32[ 53] = 0x38646138;\r
+ p32[ 54] = 0x61666634;\r
+ p32[ 55] = 0x38646262;\r
+ p32[ 56] = 0x35616665;\r
+ p32[ 57] = 0x32333339;\r
+ p32[ 58] = 0x61376562;\r
+ p32[ 59] = 0x35373664;\r
+ p32[ 60] = 0x36366136;\r
+ p32[ 61] = 0x34393265;\r
+ p32[ 62] = 0x31646661;\r
+ p32[ 63] = 0x37613538;\r
+ p32[ 64] = 0x31666638;\r
+ p32[ 65] = 0x35616132;\r
+ p32[ 66] = 0x34653032;\r
+ p32[ 67] = 0x33376564;\r
+ p32[ 68] = 0x63616239;\r
+ p32[ 69] = 0x37633061;\r
+ p32[ 70] = 0x66656666;\r
+ p32[ 71] = 0x32663766;\r
+ p32[ 72] = 0x37353539;\r
+ p32[ 73] = 0x00613732;\r
+ p32[ 74] = 0x30333033;\r
+ p32[ 75] = 0x33643130;\r
+ p32[ 76] = 0x35386234;\r
+ p32[ 77] = 0x36393236;\r
+ p32[ 78] = 0x63363163;\r
+ p32[ 79] = 0x30346430;\r
+ p32[ 80] = 0x64633364;\r
+ p32[ 81] = 0x30353737;\r
+ p32[ 82] = 0x64333961;\r
+ p32[ 83] = 0x39326431;\r
+ p32[ 84] = 0x61663535;\r
+ p32[ 85] = 0x61613038;\r
+ p32[ 86] = 0x30346635;\r
+ p32[ 87] = 0x64386366;\r
+ p32[ 88] = 0x32623762;\r
+ p32[ 89] = 0x62646261;\r
+ p32[ 90] = 0x33356564;\r
+ p32[ 91] = 0x66303539;\r
+ p32[ 92] = 0x64306334;\r
+ p32[ 93] = 0x63333932;\r
+ p32[ 94] = 0x31376464;\r
+ p32[ 95] = 0x35336131;\r
+ p32[ 96] = 0x66373662;\r
+ p32[ 97] = 0x39343162;\r
+ p32[ 98] = 0x36656139;\r
+ p32[ 99] = 0x38333030;\r
+ p32[100] = 0x66343136;\r
+ p32[101] = 0x34393331;\r
+ p32[102] = 0x61666261;\r
+ p32[103] = 0x63346233;\r
+ p32[104] = 0x64303538;\r
+ p32[105] = 0x65373239;\r
+ p32[106] = 0x37376531;\r
+ p32[107] = 0x38633936;\r
+ p32[108] = 0x32636565;\r
+ p32[109] = 0x00393164;\r
+ p32[110] = 0x66623733;\r
+ p32[111] = 0x34333732;\r
+ p32[112] = 0x36616432;\r
+ p32[113] = 0x36623933;\r
+ p32[114] = 0x66636364;\r
+ p32[115] = 0x62656666;\r
+ p32[116] = 0x36643337;\r
+ p32[117] = 0x38376439;\r
+ p32[118] = 0x32633663;\r
+ p32[119] = 0x30366137;\r
+ p32[120] = 0x62633930;\r
+ p32[121] = 0x31616362;\r
+ p32[122] = 0x66303839;\r
+ p32[123] = 0x33333538;\r
+ p32[124] = 0x65313239;\r
+ p32[125] = 0x38366138;\r
+ p32[126] = 0x33323434;\r
+ p32[127] = 0x62333465;\r
+ p32[128] = 0x38306261;\r
+ p32[129] = 0x36373561;\r
+ p32[130] = 0x61313932;\r
+ p32[131] = 0x34663866;\r
+ p32[132] = 0x62623136;\r
+ p32[133] = 0x62386132;\r
+ p32[134] = 0x31333533;\r
+ p32[135] = 0x30663264;\r
+ p32[136] = 0x63353834;\r
+ p32[137] = 0x31623931;\r
+ p32[138] = 0x66326536;\r
+ p32[139] = 0x36313531;\r
+ p32[140] = 0x64333265;\r
+ p32[141] = 0x31633364;\r
+ p32[142] = 0x32383461;\r
+ p32[143] = 0x31666137;\r
+ p32[144] = 0x63613862;\r
+ p32[145] = 0x00623531;\r
+ p32[146] = 0x00000044;\r
+ for(i = 147; i <= 154; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 155; i <= 159; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[160] = 0x31303030;\r
+ for(i = 161; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x000000ac;\r
+ p32[192] = 0x46464633;\r
+ for(i = 193; i <= 208; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[209] = 0x45464646;\r
+ p32[210] = 0x43313636;\r
+ p32[211] = 0x46383145;\r
+ p32[212] = 0x39353546;\r
+ p32[213] = 0x30333738;\r
+ p32[214] = 0x39353038;\r
+ p32[215] = 0x36383142;\r
+ p32[216] = 0x38333238;\r
+ p32[217] = 0x43453135;\r
+ p32[218] = 0x39444437;\r
+ p32[219] = 0x31314143;\r
+ p32[220] = 0x45443136;\r
+ p32[221] = 0x35443339;\r
+ p32[222] = 0x44343731;\r
+ p32[223] = 0x38453636;\r
+ p32[224] = 0x45323833;\r
+ p32[225] = 0x32424239;\r
+ p32[226] = 0x34384546;\r
+ p32[227] = 0x00373445;\r
+ for(i = 228; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x0000023b;\r
+ p32[237] = 0x0000000a;\r
+ p32[238] = 0x00000005;\r
+ p32[239] = 0x00000002;\r
+ p32[240] = 0x00000001;\r
+ break;\r
+ case CURVE_K_163:\r
+ p32[ 0] = 0x00000005;\r
+ p32[ 1] = 0x00000029;\r
+ for(i = 2; i <= 11; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 12] = 0x00000031;\r
+ for(i = 13; i <= 37; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ for(i = 38; i <= 47; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 48] = 0x00000031;\r
+ for(i = 49; i <= 73; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 74] = 0x31656632;\r
+ p32[ 75] = 0x35306333;\r
+ p32[ 76] = 0x62623733;\r
+ p32[ 77] = 0x61313163;\r
+ p32[ 78] = 0x30616163;\r
+ p32[ 79] = 0x39376437;\r
+ p32[ 80] = 0x34656433;\r
+ p32[ 81] = 0x35643665;\r
+ p32[ 82] = 0x39633565;\r
+ p32[ 83] = 0x65656534;\r
+ p32[ 84] = 0x00000038;\r
+ for(i = 85; i <= 109; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[110] = 0x30393832;\r
+ p32[111] = 0x62663037;\r
+ p32[112] = 0x33643530;\r
+ p32[113] = 0x35666638;\r
+ p32[114] = 0x31323338;\r
+ p32[115] = 0x38653266;\r
+ p32[116] = 0x33353030;\r
+ p32[117] = 0x33356436;\r
+ p32[118] = 0x64636338;\r
+ p32[119] = 0x64336161;\r
+ p32[120] = 0x00000039;\r
+ for(i = 121; i <= 145; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[146] = 0x00000044;\r
+ for(i = 147; i <= 154; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 155; i <= 159; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[160] = 0x31303030;\r
+ for(i = 161; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x00000031;\r
+ p32[192] = 0x30303034;\r
+ for(i = 193; i <= 196; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[197] = 0x30313032;\r
+ p32[198] = 0x45324138;\r
+ p32[199] = 0x30434330;\r
+ p32[200] = 0x46393944;\r
+ p32[201] = 0x45354138;\r
+ p32[202] = 0x00000046;\r
+ for(i = 203; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x000000a3;\r
+ p32[237] = 0x00000007;\r
+ p32[238] = 0x00000006;\r
+ p32[239] = 0x00000003;\r
+ p32[240] = 0x00000001;\r
+ break;\r
+ case CURVE_K_233:\r
+ p32[ 0] = 0x00000006;\r
+ p32[ 1] = 0x0000003b;\r
+ for(i = 2; i <= 15; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 16] = 0x00303030;\r
+ for(i = 17; i <= 37; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ for(i = 38; i <= 51; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 52] = 0x00313030;\r
+ for(i = 53; i <= 73; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 74] = 0x33323731;\r
+ p32[ 75] = 0x38616232;\r
+ p32[ 76] = 0x37613335;\r
+ p32[ 77] = 0x31333765;\r
+ p32[ 78] = 0x32316661;\r
+ p32[ 79] = 0x32326639;\r
+ p32[ 80] = 0x31346666;\r
+ p32[ 81] = 0x36353934;\r
+ p32[ 82] = 0x31346133;\r
+ p32[ 83] = 0x36326339;\r
+ p32[ 84] = 0x30356662;\r
+ p32[ 85] = 0x39633461;\r
+ p32[ 86] = 0x65653664;\r
+ p32[ 87] = 0x36646166;\r
+ p32[ 88] = 0x00363231;\r
+ for(i = 89; i <= 109; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[110] = 0x35626431;\r
+ p32[111] = 0x65643733;\r
+ p32[112] = 0x31386563;\r
+ p32[113] = 0x66376239;\r
+ p32[114] = 0x35663037;\r
+ p32[115] = 0x36613535;\r
+ p32[116] = 0x32346337;\r
+ p32[117] = 0x63386137;\r
+ p32[118] = 0x66623964;\r
+ p32[119] = 0x65613831;\r
+ p32[120] = 0x35623962;\r
+ p32[121] = 0x63306536;\r
+ p32[122] = 0x35303131;\r
+ p32[123] = 0x65616636;\r
+ p32[124] = 0x00336136;\r
+ for(i = 125; i <= 145; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[146] = 0x00000044;\r
+ for(i = 147; i <= 154; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 155; i <= 159; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[160] = 0x31303030;\r
+ for(i = 161; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x00000046;\r
+ p32[192] = 0x30303038;\r
+ for(i = 193; i <= 198; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[199] = 0x44393630;\r
+ p32[200] = 0x39424235;\r
+ p32[201] = 0x43423531;\r
+ p32[202] = 0x45363444;\r
+ p32[203] = 0x41314246;\r
+ p32[204] = 0x31463544;\r
+ p32[205] = 0x42413337;\r
+ p32[206] = 0x00004644;\r
+ for(i = 207; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x000000e9;\r
+ p32[237] = 0x0000004a;\r
+ p32[238] = 0x0000004a;\r
+ p32[239] = 0x0000004a;\r
+ p32[240] = 0x00000001;\r
+ break;\r
+ case CURVE_K_283:\r
+ p32[ 0] = 0x00000007;\r
+ p32[ 1] = 0x00000047;\r
+ for(i = 2; i <= 18; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 19] = 0x00303030;\r
+ for(i = 20; i <= 37; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ for(i = 38; i <= 54; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 55] = 0x00313030;\r
+ for(i = 56; i <= 73; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 74] = 0x32333035;\r
+ p32[ 75] = 0x37663331;\r
+ p32[ 76] = 0x34616338;\r
+ p32[ 77] = 0x33383834;\r
+ p32[ 78] = 0x33613166;\r
+ p32[ 79] = 0x36313862;\r
+ p32[ 80] = 0x38316632;\r
+ p32[ 81] = 0x35356538;\r
+ p32[ 82] = 0x32646333;\r
+ p32[ 83] = 0x32663536;\r
+ p32[ 84] = 0x35316333;\r
+ p32[ 85] = 0x31613736;\r
+ p32[ 86] = 0x36373836;\r
+ p32[ 87] = 0x62333139;\r
+ p32[ 88] = 0x61326330;\r
+ p32[ 89] = 0x35343263;\r
+ p32[ 90] = 0x32393438;\r
+ p32[ 91] = 0x00363338;\r
+ for(i = 92; i <= 109; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[110] = 0x64636331;\r
+ p32[111] = 0x30383361;\r
+ p32[112] = 0x39633166;\r
+ p32[113] = 0x38313365;\r
+ p32[114] = 0x66303964;\r
+ p32[115] = 0x30643539;\r
+ p32[116] = 0x34356537;\r
+ p32[117] = 0x65663632;\r
+ p32[118] = 0x34653738;\r
+ p32[119] = 0x65306335;\r
+ p32[120] = 0x34383138;\r
+ p32[121] = 0x65383936;\r
+ p32[122] = 0x36393534;\r
+ p32[123] = 0x34363332;\r
+ p32[124] = 0x31343365;\r
+ p32[125] = 0x37313631;\r
+ p32[126] = 0x32646437;\r
+ p32[127] = 0x00393532;\r
+ for(i = 128; i <= 145; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[146] = 0x00000044;\r
+ for(i = 147; i <= 154; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 155; i <= 159; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[160] = 0x31303030;\r
+ for(i = 161; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x00000055;\r
+ p32[192] = 0x46464631;\r
+ for(i = 193; i <= 199; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[200] = 0x45464646;\r
+ p32[201] = 0x32454139;\r
+ p32[202] = 0x37304445;\r
+ p32[203] = 0x32373735;\r
+ p32[204] = 0x46443536;\r
+ p32[205] = 0x39463746;\r
+ p32[206] = 0x31353434;\r
+ p32[207] = 0x31363045;\r
+ p32[208] = 0x33363145;\r
+ p32[209] = 0x00313643;\r
+ for(i = 210; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x0000011b;\r
+ p32[237] = 0x0000000c;\r
+ p32[238] = 0x00000007;\r
+ p32[239] = 0x00000005;\r
+ p32[240] = 0x00000001;\r
+ break;\r
+ case CURVE_K_409:\r
+ p32[ 0] = 0x00000008;\r
+ p32[ 1] = 0x00000067;\r
+ for(i = 2; i <= 26; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 27] = 0x00303030;\r
+ for(i = 28; i <= 37; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ for(i = 38; i <= 62; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 63] = 0x00313030;\r
+ for(i = 64; i <= 73; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[ 74] = 0x66303630;\r
+ p32[ 75] = 0x36663530;\r
+ p32[ 76] = 0x34663835;\r
+ p32[ 77] = 0x61316339;\r
+ p32[ 78] = 0x62613364;\r
+ p32[ 79] = 0x30393831;\r
+ p32[ 80] = 0x38313766;\r
+ p32[ 81] = 0x30313234;\r
+ p32[ 82] = 0x30646665;\r
+ p32[ 83] = 0x65373839;\r
+ p32[ 84] = 0x63373033;\r
+ p32[ 85] = 0x32633438;\r
+ p32[ 86] = 0x63636137;\r
+ p32[ 87] = 0x66386266;\r
+ p32[ 88] = 0x37366639;\r
+ p32[ 89] = 0x63326363;\r
+ p32[ 90] = 0x31303634;\r
+ p32[ 91] = 0x62653938;\r
+ p32[ 92] = 0x61616135;\r
+ p32[ 93] = 0x65323661;\r
+ p32[ 94] = 0x32323265;\r
+ p32[ 95] = 0x62316265;\r
+ p32[ 96] = 0x34353533;\r
+ p32[ 97] = 0x65666330;\r
+ p32[ 98] = 0x33323039;\r
+ p32[ 99] = 0x00363437;\r
+ for(i = 100; i <= 109; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[110] = 0x36336531;\r
+ p32[111] = 0x30353039;\r
+ p32[112] = 0x34633762;\r
+ p32[113] = 0x61323465;\r
+ p32[114] = 0x31616263;\r
+ p32[115] = 0x62636164;\r
+ p32[116] = 0x32343066;\r
+ p32[117] = 0x33633939;\r
+ p32[118] = 0x37303634;\r
+ p32[119] = 0x39663238;\r
+ p32[120] = 0x61653831;\r
+ p32[121] = 0x65373234;\r
+ p32[122] = 0x35323336;\r
+ p32[123] = 0x65353631;\r
+ p32[124] = 0x31616539;\r
+ p32[125] = 0x64336530;\r
+ p32[126] = 0x36663561;\r
+ p32[127] = 0x65323463;\r
+ p32[128] = 0x35356339;\r
+ p32[129] = 0x61353132;\r
+ p32[130] = 0x61633961;\r
+ p32[131] = 0x35613732;\r
+ p32[132] = 0x65333638;\r
+ p32[133] = 0x64383463;\r
+ p32[134] = 0x32306538;\r
+ p32[135] = 0x00623638;\r
+ for(i = 136; i <= 145; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[146] = 0x00000044;\r
+ for(i = 147; i <= 154; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 155; i <= 159; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[160] = 0x31303030;\r
+ for(i = 161; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x0000007b;\r
+ p32[192] = 0x46464637;\r
+ for(i = 193; i <= 203; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ p32[204] = 0x45464646;\r
+ p32[205] = 0x33384635;\r
+ p32[206] = 0x34443242;\r
+ p32[207] = 0x30324145;\r
+ p32[208] = 0x45303034;\r
+ p32[209] = 0x35353443;\r
+ p32[210] = 0x45354437;\r
+ p32[211] = 0x33453344;\r
+ p32[212] = 0x41433745;\r
+ p32[213] = 0x42344235;\r
+ p32[214] = 0x33384335;\r
+ p32[215] = 0x30453842;\r
+ p32[216] = 0x46354531;\r
+ p32[217] = 0x00004643;\r
+ for(i = 218; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x00000199;\r
+ p32[237] = 0x00000057;\r
+ p32[238] = 0x00000057;\r
+ p32[239] = 0x00000057;\r
+ p32[240] = 0x00000001;\r
+ break;\r
+ case CURVE_K_571:\r
+ p32[ 0] = 0x00000009;\r
+ p32[ 1] = 0x0000008f;\r
+ for(i = 2; i <= 36; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 37] = 0x00303030;\r
+ for(i = 38; i <= 72; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[ 73] = 0x00313030;\r
+ p32[ 74] = 0x62653632;\r
+ p32[ 75] = 0x35386137;\r
+ p32[ 76] = 0x33323939;\r
+ p32[ 77] = 0x38636266;\r
+ p32[ 78] = 0x39383132;\r
+ p32[ 79] = 0x66313336;\r
+ p32[ 80] = 0x33303138;\r
+ p32[ 81] = 0x61346566;\r
+ p32[ 82] = 0x61633963;\r
+ p32[ 83] = 0x30373932;\r
+ p32[ 84] = 0x64323130;\r
+ p32[ 85] = 0x36346435;\r
+ p32[ 86] = 0x38343230;\r
+ p32[ 87] = 0x30383430;\r
+ p32[ 88] = 0x31343831;\r
+ p32[ 89] = 0x34346163;\r
+ p32[ 90] = 0x39303733;\r
+ p32[ 91] = 0x39343835;\r
+ p32[ 92] = 0x30326233;\r
+ p32[ 93] = 0x34366535;\r
+ p32[ 94] = 0x33616437;\r
+ p32[ 95] = 0x62643430;\r
+ p32[ 96] = 0x62656334;\r
+ p32[ 97] = 0x62633830;\r
+ p32[ 98] = 0x62316462;\r
+ p32[ 99] = 0x34393361;\r
+ p32[100] = 0x37373439;\r
+ p32[101] = 0x39626636;\r
+ p32[102] = 0x34623838;\r
+ p32[103] = 0x34373137;\r
+ p32[104] = 0x38616364;\r
+ p32[105] = 0x65376338;\r
+ p32[106] = 0x35343932;\r
+ p32[107] = 0x61333832;\r
+ p32[108] = 0x38633130;\r
+ p32[109] = 0x00323739;\r
+ p32[110] = 0x64393433;\r
+ p32[111] = 0x37303863;\r
+ p32[112] = 0x62663466;\r
+ p32[113] = 0x34373366;\r
+ p32[114] = 0x65613466;\r
+ p32[115] = 0x33656461;\r
+ p32[116] = 0x39616362;\r
+ p32[117] = 0x34313335;\r
+ p32[118] = 0x38356464;\r
+ p32[119] = 0x39636563;\r
+ p32[120] = 0x37303366;\r
+ p32[121] = 0x66343561;\r
+ p32[122] = 0x31366366;\r
+ p32[123] = 0x30636665;\r
+ p32[124] = 0x38643630;\r
+ p32[125] = 0x39633261;\r
+ p32[126] = 0x37393464;\r
+ p32[127] = 0x61306339;\r
+ p32[128] = 0x61343463;\r
+ p32[129] = 0x34376165;\r
+ p32[130] = 0x62656266;\r
+ p32[131] = 0x66396262;\r
+ p32[132] = 0x61323737;\r
+ p32[133] = 0x62636465;\r
+ p32[134] = 0x62303236;\r
+ p32[135] = 0x37613130;\r
+ p32[136] = 0x61376162;\r
+ p32[137] = 0x33623166;\r
+ p32[138] = 0x33343032;\r
+ p32[139] = 0x35386330;\r
+ p32[140] = 0x38393139;\r
+ p32[141] = 0x30366634;\r
+ p32[142] = 0x34646331;\r
+ p32[143] = 0x33343163;\r
+ p32[144] = 0x63316665;\r
+ p32[145] = 0x00336137;\r
+ p32[146] = 0x00000044;\r
+ for(i = 147; i <= 154; i++)\r
+ p32[i] = 0x46464646;\r
+\r
+ for(i = 155; i <= 159; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[160] = 0x31303030;\r
+ for(i = 161; i <= 190; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[191] = 0x000000ac;\r
+ p32[192] = 0x30303032;\r
+ for(i = 193; i <= 208; i++)\r
+ p32[i] = 0x30303030;\r
+\r
+ p32[209] = 0x31303030;\r
+ p32[210] = 0x35383133;\r
+ p32[211] = 0x46314530;\r
+ p32[212] = 0x36413931;\r
+ p32[213] = 0x42344533;\r
+ p32[214] = 0x41313933;\r
+ p32[215] = 0x39424438;\r
+ p32[216] = 0x34463731;\r
+ p32[217] = 0x42383331;\r
+ p32[218] = 0x44303336;\r
+ p32[219] = 0x45423438;\r
+ p32[220] = 0x33364435;\r
+ p32[221] = 0x31383339;\r
+ p32[222] = 0x44313945;\r
+ p32[223] = 0x35344245;\r
+ p32[224] = 0x37454643;\r
+ p32[225] = 0x36463837;\r
+ p32[226] = 0x31433733;\r
+ p32[227] = 0x00313030;\r
+ for(i = 228; i <= 235; i++)\r
+ p32[i] = 0x00000000;\r
+\r
+ p32[236] = 0x0000023b;\r
+ p32[237] = 0x0000000a;\r
+ p32[238] = 0x00000005;\r
+ p32[239] = 0x00000002;\r
+ p32[240] = 0x00000001;\r
+ break;\r
+ default:\r
+ return -1;\r
+\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+\r
+static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve)\r
+{\r
+ uint32_t i;\r
+ ECC_CURVE *ret = NULL;\r
+\r
+ if(CurveCpy((unsigned int *)&Curve_Copy, ecc_curve))\r
+ return NULL;\r
+ else\r
+ return &Curve_Copy;\r
+\r
+}\r
+\r
+\r
+#else\r
+static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve)\r
+{\r
+ uint32_t i;\r
+ ECC_CURVE *ret = NULL;\r
+\r
+ for(i = 0UL; i < sizeof(_Curve) / sizeof(ECC_CURVE); i++)\r
+ {\r
+ if(ecc_curve == _Curve[i].curve_id)\r
+ {\r
+ memcpy((char *)&Curve_Copy, &_Curve[i], sizeof(ECC_CURVE));\r
+ ret = &Curve_Copy; /* (ECC_CURVE *)&_Curve[i]; */\r
+ }\r
+ if(ret != NULL)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ return ret;\r
+}\r
+#endif\r
+\r
+\r
+/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group CRYPTO_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file dac.c\r
+ * @version V1.00\r
+ * @brief M2351 series DAC driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup DAC_Driver DAC Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief This function make DAC module be ready to convert.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @param[in] u32Ch Not used in M2351 Series DAC.\r
+ * @param[in] u32TrgSrc Decides the trigger source. Valid values are:\r
+ * - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger\r
+ * - \ref DAC_SOFTWARE_TRIGGER :Software trigger\r
+ * - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger\r
+ * - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger\r
+ * - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger\r
+ * - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger\r
+ * - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger\r
+ * - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger\r
+ * - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger\r
+ * - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger\r
+ * - \ref DAC_EPWM0_TRIGGER :EPWM0 trigger\r
+ * - \ref DAC_EPWM1_TRIGGER :EPWM1 trigger\r
+ * @return None\r
+ * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger.\r
+ * When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register.\r
+ * When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1,\r
+ * external STDAC pin, timer event, or EPWM event.\r
+ */\r
+void DAC_Open(DAC_T *dac,\r
+ uint32_t u32Ch,\r
+ uint32_t u32TrgSrc)\r
+{\r
+ dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk);\r
+\r
+ dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Disable DAC analog power.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @param[in] u32Ch Not used in M2351 Series DAC.\r
+ * @return None\r
+ * @details Disable DAC analog power for saving power consumption.\r
+ */\r
+void DAC_Close(DAC_T *dac, uint32_t u32Ch)\r
+{\r
+ dac->CTL &= (~DAC_CTL_DACEN_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Set delay time for DAC to become stable.\r
+ * @param[in] dac The pointer of the specified DAC module.\r
+ * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds.\r
+ * @return Real DAC conversion settling time (micro second).\r
+ * @details For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0x40.\r
+ * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed.\r
+ */\r
+uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)\r
+{\r
+\r
+ dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL);\r
+\r
+ return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq());\r
+}\r
+\r
+\r
+\r
+/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group DAC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file eadc.c\r
+ * @version V2.00\r
+ * @brief M2351 series EADC driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup EADC_Driver EADC Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief This function make EADC_module be ready to convert.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32InputMode Decides the input mode.\r
+ * - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode.\r
+ * - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type.\r
+ * @return None\r
+ * @details This function is used to set analog input mode and enable A/D Converter.\r
+ * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.\r
+ * @note\r
+ */\r
+void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)\r
+{\r
+ eadc->CTL &= (~(EADC_CTL_DIFFEN_Msk));\r
+\r
+ eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk);\r
+\r
+ while(!(eadc->PWRM & EADC_PWRM_PWUPRDY_Msk)) {}\r
+}\r
+\r
+/**\r
+ * @brief Disable EADC_module.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @return None\r
+ * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.\r
+ */\r
+void EADC_Close(EADC_T *eadc)\r
+{\r
+ eadc->CTL &= ~EADC_CTL_ADCEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Configure the sample control logic module.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.\r
+ * @param[in] u32TriggerSrc Decides the trigger source. Valid values are:\r
+ * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger\r
+ * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger\r
+ * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger\r
+ * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger\r
+ * - \ref EADC_ADINT0_TRIGGER : ADC ADINT0 interrupt EOC pulse trigger\r
+ * - \ref EADC_ADINT1_TRIGGER : ADC ADINT1 interrupt EOC pulse trigger\r
+ * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger\r
+ * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger\r
+ * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger\r
+ * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger\r
+ * - \ref EADC_PWM0TG0_TRIGGER : EPWM0TG0 trigger\r
+ * - \ref EADC_PWM0TG1_TRIGGER : EPWM0TG1 trigger\r
+ * - \ref EADC_PWM0TG2_TRIGGER : EPWM0TG2 trigger\r
+ * - \ref EADC_PWM0TG3_TRIGGER : EPWM0TG3 trigger\r
+ * - \ref EADC_PWM0TG4_TRIGGER : EPWM0TG4 trigger\r
+ * - \ref EADC_PWM0TG5_TRIGGER : EPWM0TG5 trigger\r
+ * - \ref EADC_PWM1TG0_TRIGGER : EPWM1TG0 trigger\r
+ * - \ref EADC_PWM1TG1_TRIGGER : EPWM1TG1 trigger\r
+ * - \ref EADC_PWM1TG2_TRIGGER : EPWM1TG2 trigger\r
+ * - \ref EADC_PWM1TG3_TRIGGER : EPWM1TG3 trigger\r
+ * - \ref EADC_PWM1TG4_TRIGGER : EPWM1TG4 trigger\r
+ * - \ref EADC_PWM1TG5_TRIGGER : EPWM1TG5 trigger\r
+ * - \ref EADC_BPWM0TG_TRIGGER : BPWM0TG trigger\r
+ * - \ref EADC_BPWM1TG_TRIGGER : BPWM1TG trigger\r
+ * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15.\r
+ * @return None\r
+ * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source.\r
+ * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).\r
+ */\r
+void EADC_ConfigSampleModule(EADC_T *eadc, \\r
+ uint32_t u32ModuleNum, \\r
+ uint32_t u32TriggerSrc, \\r
+ uint32_t u32Channel)\r
+{\r
+ eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk);\r
+ eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set trigger delay time.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.\r
+ * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF.\r
+ * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are:\r
+ * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1\r
+ * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2\r
+ * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4\r
+ * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16\r
+ * @return None\r
+ * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15).\r
+ * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.\r
+ */\r
+void EADC_SetTriggerDelayTime(EADC_T *eadc, \\r
+ uint32_t u32ModuleNum, \\r
+ uint32_t u32TriggerDelayTime, \\r
+ uint32_t u32DelayClockDivider)\r
+{\r
+ eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk);\r
+ eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider);\r
+}\r
+\r
+/**\r
+ * @brief Set ADC extend sample time.\r
+ * @param[in] eadc The pointer of the specified EADC module.\r
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.\r
+ * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.\r
+ * @return None\r
+ * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy,\r
+ * user can extend A/D sampling time after trigger source is coming to get enough sampling time.\r
+ */\r
+void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)\r
+{\r
+ eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk;\r
+\r
+ eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos);\r
+\r
+}\r
+\r
+/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group EADC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file ebi.c\r
+ * @version V3.00\r
+ * @brief External Bus Interface(EBI) driver source file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup EBI_Driver EBI Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Initialize EBI for specify Bank\r
+ *\r
+ * @param[in] u32Bank Bank number for EBI. Valid values are:\r
+ * - \ref EBI_BANK0\r
+ * - \ref EBI_BANK1\r
+ * - \ref EBI_BANK2\r
+ * @param[in] u32DataWidth Data bus width. Valid values are:\r
+ * - \ref EBI_BUSWIDTH_8BIT\r
+ * - \ref EBI_BUSWIDTH_16BIT\r
+ * @param[in] u32TimingClass Default timing configuration. Valid values are:\r
+ * - \ref EBI_TIMING_FASTEST\r
+ * - \ref EBI_TIMING_VERYFAST\r
+ * - \ref EBI_TIMING_FAST\r
+ * - \ref EBI_TIMING_NORMAL\r
+ * - \ref EBI_TIMING_SLOW\r
+ * - \ref EBI_TIMING_VERYSLOW\r
+ * - \ref EBI_TIMING_SLOWEST\r
+ * @param[in] u32BusMode Set EBI bus operate mode. Valid values are:\r
+ * - \ref EBI_OPMODE_NORMAL\r
+ * - \ref EBI_OPMODE_CACCESS\r
+ * - \ref EBI_OPMODE_ADSEPARATE\r
+ * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are:\r
+ * - \ref EBI_CS_ACTIVE_HIGH\r
+ * - \ref EBI_CS_ACTIVE_LOW\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to open specify EBI bank with different bus width, timing setting and \n\r
+ * active level of CS pin to access EBI device.\r
+ * @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register.\r
+ */\r
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)\r
+{\r
+ uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U;\r
+ uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U;\r
+ volatile uint32_t *pu32EBICTL, *pu32EBITCTL;\r
+ uint32_t pu32Index0, pu32Index1;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pu32Index0 = (u32Index0 + NS_OFFSET);\r
+ pu32Index1 = (u32Index1 + NS_OFFSET);\r
+ }\r
+ else\r
+ {\r
+ pu32Index0 = u32Index0;\r
+ pu32Index1 = u32Index1;\r
+ }\r
+\r
+ pu32EBICTL = (uint32_t *)(pu32Index0);\r
+ pu32EBITCTL = (uint32_t *)(pu32Index1);\r
+\r
+ if(u32DataWidth == EBI_BUSWIDTH_8BIT)\r
+ {\r
+ *pu32EBICTL &= ~EBI_CTL_DW16_Msk;\r
+ }\r
+ else\r
+ {\r
+ *pu32EBICTL |= EBI_CTL_DW16_Msk;\r
+ }\r
+\r
+ *pu32EBICTL |= u32BusMode;\r
+\r
+ switch(u32TimingClass)\r
+ {\r
+ case EBI_TIMING_FASTEST:\r
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |\r
+ (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |\r
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;\r
+ *pu32EBITCTL = 0x0U;\r
+ break;\r
+\r
+ case EBI_TIMING_VERYFAST:\r
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |\r
+ (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |\r
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |\r
+ (0x3U << EBI_CTL_TALE_Pos) ;\r
+ *pu32EBITCTL = 0x03003318U;\r
+ break;\r
+\r
+ case EBI_TIMING_FAST:\r
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |\r
+ (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |\r
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;\r
+ *pu32EBITCTL = 0x0U;\r
+ break;\r
+\r
+ case EBI_TIMING_NORMAL:\r
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |\r
+ (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |\r
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |\r
+ (0x3U << EBI_CTL_TALE_Pos) ;\r
+ *pu32EBITCTL = 0x03003318U;\r
+ break;\r
+\r
+ case EBI_TIMING_SLOW:\r
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |\r
+ (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |\r
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |\r
+ (0x7U << EBI_CTL_TALE_Pos) ;\r
+ *pu32EBITCTL = 0x07007738U;\r
+ break;\r
+\r
+ case EBI_TIMING_VERYSLOW:\r
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |\r
+ (EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) |\r
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |\r
+ (0x7U << EBI_CTL_TALE_Pos) ;\r
+ *pu32EBITCTL = 0x07007738U;\r
+ break;\r
+\r
+ case EBI_TIMING_SLOWEST:\r
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |\r
+ (EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) |\r
+ (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |\r
+ (0x7U << EBI_CTL_TALE_Pos) ;\r
+ *pu32EBITCTL = 0x07007738U;\r
+ break;\r
+\r
+ default:\r
+ *pu32EBICTL &= ~EBI_CTL_EN_Msk;\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable EBI on specify Bank\r
+ *\r
+ * @param[in] u32Bank Bank number for EBI. Valid values are:\r
+ * - \ref EBI_BANK0\r
+ * - \ref EBI_BANK1\r
+ * - \ref EBI_BANK2\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to close specify EBI function.\r
+ */\r
+void EBI_Close(uint32_t u32Bank)\r
+{\r
+ uint32_t u32Index = (uint32_t)&EBI->CTL0 + u32Bank * 0x10U;\r
+ volatile uint32_t *pu32EBICTL;\r
+ uint32_t pu32Index;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pu32Index = (u32Index + NS_OFFSET);\r
+ }\r
+ else\r
+ {\r
+ pu32Index = u32Index;\r
+ }\r
+\r
+ pu32EBICTL = (uint32_t *)(pu32Index);\r
+\r
+ *pu32EBICTL &= ~EBI_CTL_EN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Set EBI Bus Timing for specify Bank\r
+ *\r
+ * @param[in] u32Bank Bank number for EBI. Valid values are:\r
+ * - \ref EBI_BANK0\r
+ * - \ref EBI_BANK1\r
+ * - \ref EBI_BANK2\r
+ * @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting.\r
+ * @param[in] u32MclkDiv Divider for MCLK. Valid values are:\r
+ * - \ref EBI_MCLKDIV_1\r
+ * - \ref EBI_MCLKDIV_2\r
+ * - \ref EBI_MCLKDIV_4\r
+ * - \ref EBI_MCLKDIV_8\r
+ * - \ref EBI_MCLKDIV_16\r
+ * - \ref EBI_MCLKDIV_32\r
+ * - \ref EBI_MCLKDIV_64\r
+ * - \ref EBI_MCLKDIV_128\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to configure specify EBI bus timing for access EBI device.\r
+ */\r
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)\r
+{\r
+ uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U;\r
+ uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U;\r
+ volatile uint32_t *pu32EBICTL, *pu32EBITCTL;\r
+ uint32_t pu32Index0, pu32Index1;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pu32Index0 = (u32Index0 + NS_OFFSET);\r
+ pu32Index1 = (u32Index1 + NS_OFFSET);\r
+ }\r
+ else\r
+ {\r
+ pu32Index0 = u32Index0;\r
+ pu32Index1 = u32Index1;\r
+ }\r
+\r
+ pu32EBICTL = (uint32_t *)(pu32Index0);\r
+ pu32EBITCTL = (uint32_t *)(pu32Index1);\r
+\r
+ *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos);\r
+ *pu32EBITCTL = u32TimingConfig;\r
+}\r
+\r
+/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group EBI_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file ecap.c\r
+ * @version V3.00\r
+\r
+ * @brief Enhanced Input Capture Timer (ECAP) driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "M2351.h"\r
+\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup ECAP_Driver ECAP Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Enable ECAP function\r
+ * @param[in] ecap The pointer of the specified ECAP module.\r
+ * @param[in] u32FuncMask Input capture function select\r
+ * - \ref ECAP_DISABLE_COMPARE\r
+ * - \ref ECAP_COMPARE_FUNCTION\r
+ * @return None\r
+ * @details This macro enable input capture function and select compare and reload function.\r
+ */\r
+void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask)\r
+{\r
+ /* Clear Input capture mode*/\r
+ ecap->CTL0 = ecap->CTL0 & ~(ECAP_CTL0_CMPEN_Msk);\r
+\r
+ /* Enable Input Capture and set mode */\r
+ ecap->CTL0 |= ECAP_CTL0_CAPEN_Msk | (u32FuncMask);\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Disable ECAP function\r
+ * @param[in] ecap The pointer of the specified ECAP module.\r
+ * @return None\r
+ * @details This macro disable input capture function.\r
+ */\r
+void ECAP_Close(ECAP_T* ecap)\r
+{\r
+ /* Disable Input Capture*/\r
+ ecap->CTL0 &= ~ECAP_CTL0_CAPEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief This macro is used to enable input channel interrupt\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Mask The input channel Mask\r
+ * - \ref ECAP_CTL0_CAPIEN0_Msk\r
+ * - \ref ECAP_CTL0_CAPIEN1_Msk\r
+ * - \ref ECAP_CTL0_CAPIEN2_Msk\r
+ * - \ref ECAP_CTL0_OVIEN_Msk\r
+ * - \ref ECAP_CTL0_CMPIEN_Msk\r
+ * @return None\r
+ * @details This macro will enable the input channel_n interrupt.\r
+ */\r
+void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask)\r
+{\r
+ /* Enable input channel interrupt */\r
+ ecap->CTL0 |= (u32Mask);\r
+\r
+ /* Enable NVIC ECAP IRQ */\r
+ if((ecap == ECAP0) || (ecap == ECAP0_NS))\r
+ {\r
+ NVIC_EnableIRQ(ECAP0_IRQn);\r
+ }\r
+ else\r
+ {\r
+ NVIC_EnableIRQ(ECAP1_IRQn);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This macro is used to disable input channel interrupt\r
+ * @param[in] ecap Specify ECAP port\r
+ * @param[in] u32Mask The input channel number\r
+ * - \ref ECAP_CTL0_CAPIEN0_Msk\r
+ * - \ref ECAP_CTL0_CAPIEN1_Msk\r
+ * - \ref ECAP_CTL0_CAPIEN2_Msk\r
+ * - \ref ECAP_CTL0_OVIEN_Msk\r
+ * - \ref ECAP_CTL0_CMPIEN_Msk\r
+ * @return None\r
+ * @details This macro will disable the input channel_n interrupt.\r
+ */\r
+void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask)\r
+{\r
+ /* Disable input channel interrupt */\r
+ (ecap->CTL0) &= ~(u32Mask);\r
+\r
+ /* Disable NVIC ECAP IRQ */\r
+ if((ecap == ECAP0) || (ecap == ECAP0_NS))\r
+ {\r
+ NVIC_DisableIRQ(ECAP0_IRQn);\r
+ }\r
+ else\r
+ {\r
+ NVIC_DisableIRQ(ECAP1_IRQn);\r
+ }\r
+}\r
+\r
+/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group ECAP_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**
+ * @file epwm.c
+ * @version V3.00
+ * @brief M2351 series EPWM driver source file
+ *
+ * @note
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EPWM_Driver EPWM Driver
+ @{
+*/
+
+
+/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions
+ @{
+*/
+
+/**
+ * @brief Configure EPWM capture and get the nearest unit time.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32UnitTimeNsec The unit time of counter
+ * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
+ * @return The nearest unit time in nano second.
+ * @details This function is used to Configure EPWM capture and get the nearest unit time.
+ */
+uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
+{
+ uint32_t u32PWMClockSrc;
+ uint32_t u32NearestUnitTimeNsec;
+ uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
+ uint8_t u8BreakLoop = 0U;
+
+ /* clock source is from PCLK */
+ if((epwm == EPWM0) || (epwm == EPWM0_NS))
+ {
+ u32PWMClockSrc = CLK_GetPCLK0Freq();
+ }
+ else /* if((epwm == EPWM1)||(epwm == EPWM1_NS)) */
+ {
+ u32PWMClockSrc = CLK_GetPCLK1Freq();
+ }
+
+ u32PWMClockSrc /= 1000UL;
+ for(u32Prescale = 1U; u32Prescale <= 0x1000U; u32Prescale++)
+ {
+ u32NearestUnitTimeNsec = (1000000UL * u32Prescale) / u32PWMClockSrc;
+ if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
+ {
+ if(u32Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */
+ {
+ u8BreakLoop = 1U;
+ }
+ if(!((1000000UL * (u32Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))
+ {
+ u8BreakLoop = 1U;
+ }
+ }
+ else
+ {
+ u8BreakLoop = 1U;
+ }
+ if(u8BreakLoop)
+ {
+ break;
+ }
+ }
+
+ /* convert to real register value */
+ u32Prescale = u32Prescale - 1U;
+ /* every two channels share a prescaler */
+ EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale);
+
+ /* set EPWM to down count type(edge aligned) */
+ (epwm)->CTL1 = ((epwm)->CTL1 & ~(EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1))) | (1UL << (u32ChannelNum << 1));
+ /* set EPWM to auto-reload mode */
+ (epwm)->CTL1 &= ~(EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
+ EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
+
+ return (u32NearestUnitTimeNsec);
+}
+
+/**
+ * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @return Nearest frequency clock in nano second
+ * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
+ * existing frequency of other channel.
+ * @note This function is used for initial stage.
+ * To change duty cycle later, it should get the configured period value and calculate the new comparator value.
+ */
+uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
+{
+ uint32_t u32PWMClockSrc;
+ uint32_t i;
+ uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
+
+ /* clock source is from PCLK */
+ if((epwm == EPWM0) || (epwm == EPWM0_NS))
+ {
+ u32PWMClockSrc = CLK_GetPCLK0Freq();
+ }
+ else /* if((epwm == EPWM1)||(epwm == EPWM1_NS)) */
+ {
+ u32PWMClockSrc = CLK_GetPCLK1Freq();
+ }
+
+ for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++)/* prescale could be 0~0xFFF */
+ {
+ i = (u32PWMClockSrc / u32Frequency) / u32Prescale;
+ /* If target value is larger than CNR, need to use a larger prescaler */
+ if(i <= (0x10000U))
+ {
+ u32CNR = i;
+ break;
+ }
+ }
+ /* Store return value here 'cos we're gonna change u32Prescale & u32CNR to the real value to fill into register */
+ i = u32PWMClockSrc / (u32Prescale * u32CNR);
+
+ /* convert to real register value */
+ u32Prescale = u32Prescale - 1U;
+ /* every two channels share a prescaler */
+ EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale);
+ /* set EPWM to up counter type(edge aligned) and auto-reload mode */
+ (epwm)->CTL1 = ((epwm)->CTL1 & ~((EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1)) | (EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum)));
+
+ u32CNR = u32CNR - 1U;
+ EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
+ EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL);
+
+ (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \
+ (EPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << EPWM_WGCTL0_ZPCTL0_Pos));
+ (epwm)->WGCTL1 = ((epwm)->WGCTL1 & ~((EPWM_WGCTL1_CMPDCTL0_Msk | EPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1))) | \
+ (EPWM_OUTPUT_LOW << (u32ChannelNum << 1UL << EPWM_WGCTL1_CMPUCTL0_Pos));
+
+ return(i);
+}
+
+/**
+ * @brief Start EPWM module
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to start EPWM module.
+ */
+void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ (epwm)->CNTEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Stop EPWM module
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop EPWM module.
+ */
+void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0UL; i < EPWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1UL << i))
+ {
+ (epwm)->PERIOD[i] = 0UL;
+ }
+ }
+}
+
+/**
+ * @brief Stop EPWM generation immediately by clear channel enable bit
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop EPWM generation immediately by clear channel enable bit.
+ */
+void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ (epwm)->CNTEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enable selected channel to trigger ADC
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
+ * - \ref EPWM_TRG_ADC_EVEN_ZERO
+ * - \ref EPWM_TRG_ADC_EVEN_PERIOD
+ * - \ref EPWM_TRG_ADC_EVEN_ZERO_PERIOD
+ * - \ref EPWM_TRG_ADC_EVEN_COMPARE_UP
+ * - \ref EPWM_TRG_ADC_EVEN_COMPARE_DOWN
+ * - \ref EPWM_TRG_ADC_ODD_ZERO
+ * - \ref EPWM_TRG_ADC_ODD_PERIOD
+ * - \ref EPWM_TRG_ADC_ODD_ZERO_PERIOD
+ * - \ref EPWM_TRG_ADC_ODD_COMPARE_UP
+ * - \ref EPWM_TRG_ADC_ODD_COMPARE_DOWN
+ * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_UP
+ * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN
+ * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_UP
+ * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN
+ * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_UP
+ * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN
+ * @return None
+ * @details This function is used to enable selected channel to trigger ADC.
+ */
+void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ if(u32ChannelNum < 4UL)
+ {
+ (epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3));
+ (epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3));
+ }
+ else
+ {
+ (epwm)->EADCTS1 &= ~((EPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3));
+ (epwm)->EADCTS1 |= ((EPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3));
+ }
+}
+
+/**
+ * @brief Disable selected channel to trigger ADC
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable selected channel to trigger ADC.
+ */
+void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ if(u32ChannelNum < 4UL)
+ {
+ (epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3));
+ }
+ else
+ {
+ (epwm)->EADCTS1 &= ~(EPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3));
+ }
+}
+
+/**
+ * @brief Clear selected channel trigger ADC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger ADC flag.
+ */
+void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ (epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get selected channel trigger ADC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @retval 0 The specified channel trigger ADC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger ADC to start of conversion flag is set
+ * @details This function is used to get EPWM trigger ADC to start of conversion flag for specified channel.
+ */
+uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable selected channel to trigger DAC
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions:
+ * - \ref EPWM_TRIGGER_DAC_ZERO
+ * - \ref EPWM_TRIGGER_DAC_PERIOD
+ * - \ref EPWM_TRIGGER_DAC_COMPARE_UP
+ * - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN
+ * @return None
+ * @details This function is used to enable selected channel to trigger DAC.
+ */
+void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ (epwm)->DACTRGEN |= (u32Condition << u32ChannelNum);
+}
+
+/**
+ * @brief Disable selected channel to trigger DAC
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable selected channel to trigger DAC.
+ */
+void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear selected channel trigger DAC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. This parameter is not used
+ * @param[in] u32Condition The condition to trigger DAC. This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger DAC flag.
+ */
+void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ (epwm)->STATUS = EPWM_STATUS_DACTRGF_Msk;
+}
+
+/**
+ * @brief Get selected channel trigger DAC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. This parameter is not used
+ * @retval 0 The specified channel trigger DAC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger DAC to start of conversion flag is set
+ * @details This function is used to get selected channel trigger DAC flag.
+ */
+uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return (((epwm)->STATUS & EPWM_STATUS_DACTRGF_Msk) ? 1UL : 0UL);
+}
+
+/**
+ * @brief This function enable fault brake of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel
+ * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32BrakeSource Fault brake source, could be one of following source
+ * - \ref EPWM_FB_EDGE_ADCRM
+ * - \ref EPWM_FB_EDGE_ACMP0
+ * - \ref EPWM_FB_EDGE_ACMP1
+ * - \ref EPWM_FB_EDGE_BKP0
+ * - \ref EPWM_FB_EDGE_BKP1
+ * - \ref EPWM_FB_EDGE_SYS_CSS
+ * - \ref EPWM_FB_EDGE_SYS_BOD
+ * - \ref EPWM_FB_EDGE_SYS_RAM
+ * - \ref EPWM_FB_EDGE_SYS_COR
+ * - \ref EPWM_FB_LEVEL_ADCRM
+ * - \ref EPWM_FB_LEVEL_ACMP0
+ * - \ref EPWM_FB_LEVEL_ACMP1
+ * - \ref EPWM_FB_LEVEL_BKP0
+ * - \ref EPWM_FB_LEVEL_BKP1
+ * - \ref EPWM_FB_LEVEL_SYS_CSS
+ * - \ref EPWM_FB_LEVEL_SYS_BOD
+ * - \ref EPWM_FB_LEVEL_SYS_RAM
+ * - \ref EPWM_FB_LEVEL_SYS_COR
+ * @return None
+ * @details This function is used to enable fault brake of selected channel(s).
+ * The write-protection function should be disabled before using this function.
+ */
+void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
+{
+ uint32_t i;
+
+ for(i = 0UL; i < EPWM_CHANNEL_NUM; i++)
+ {
+ if(u32ChannelMask & (1UL << i))
+ {
+ if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \
+ (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \
+ (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \
+ (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR))
+ {
+ (epwm)->BRKCTL[i >> 1] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_Msk));
+ (epwm)->FAILBRK |= (u32BrakeSource & 0xFUL);
+ }
+ else
+ {
+ (epwm)->BRKCTL[i >> 1] |= u32BrakeSource;
+ }
+ }
+
+ if(u32LevelMask & (1UL << i))
+ {
+ if((i & 0x1UL) == 0UL)
+ {
+ /* set brake action as high level for even channel */
+ (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;
+ (epwm)->BRKCTL[i >> 1] |= ((3UL) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);
+ }
+ else
+ {
+ /* set brake action as high level for odd channel */
+ (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;
+ (epwm)->BRKCTL[i >> 1] |= ((3UL) << EPWM_BRKCTL0_1_BRKAODD_Pos);
+ }
+ }
+ else
+ {
+ if((i & 0x1UL) == 0UL)
+ {
+ /* set brake action as low level for even channel */
+ (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;
+ (epwm)->BRKCTL[i >> 1] |= ((2UL) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);
+ }
+ else
+ {
+ /* set brake action as low level for odd channel */
+ (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;
+ (epwm)->BRKCTL[i >> 1] |= ((2UL) << EPWM_BRKCTL0_1_BRKAODD_Pos);
+ }
+ }
+ }
+}
+
+/**
+ * @brief Enable capture of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable capture of selected channel(s).
+ */
+void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ (epwm)->CAPINEN |= u32ChannelMask;
+ (epwm)->CAPCTL |= u32ChannelMask;
+}
+
+/**
+ * @brief Disable capture of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable capture of selected channel(s).
+ */
+void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ (epwm)->CAPINEN &= ~u32ChannelMask;
+ (epwm)->CAPCTL &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables EPWM output generation of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ * @details This function is used to enable EPWM output generation of selected channel(s).
+ */
+void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ (epwm)->POEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Disables EPWM output generation of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
+ * @return None
+ * @details This function is used to disable EPWM output generation of selected channel(s).
+ */
+void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ (epwm)->POEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables PDMA transfer of selected channel for EPWM capture
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number.
+ * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE.
+ * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either
+ * - \ref EPWM_CAPTURE_PDMA_RISING_LATCH
+ * - \ref EPWM_CAPTURE_PDMA_FALLING_LATCH
+ * - \ref EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture.
+ * @note This function can only selects even or odd channel of pairs to do PDMA transfer.
+ */
+void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
+{
+ uint32_t u32IsOddCh;
+ u32IsOddCh = u32ChannelNum & 0x1UL;
+ (epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1) << 3))) | \
+ (((u32IsOddCh << EPWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << EPWM_PDMACTL_CAPORD0_1_Pos) | \
+ u32Mode | EPWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1) << 3));
+}
+
+/**
+ * @brief Disables PDMA transfer of selected channel for EPWM capture
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number.
+ * @return None
+ * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture.
+ */
+void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1) << 3));
+}
+
+/**
+ * @brief Enable Dead zone of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Duration Dead zone length in EPWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone.
+ * @return None
+ * @details This function is used to enable Dead zone of selected channel.
+ * The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration)
+{
+ /* every two channels share the same setting */
+ (epwm)->DTCTL[(u32ChannelNum) >> 1] &= ~EPWM_DTCTL0_1_DTCNT_Msk;
+ (epwm)->DTCTL[(u32ChannelNum) >> 1] |= EPWM_DTCTL0_1_DTEN_Msk | u32Duration;
+}
+
+/**
+ * @brief Disable Dead zone of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable Dead zone of selected channel.
+ * The write-protection function should be disabled before using this function.
+ */
+void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ /* every two channels shares the same setting */
+ (epwm)->DTCTL[(u32ChannelNum) >> 1] &= ~EPWM_DTCTL0_1_DTEN_Msk;
+}
+
+/**
+ * @brief Enable capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref EPWM_CAPTURE_INT_RISING_LATCH
+ * - \ref EPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable capture interrupt of selected channel.
+ */
+void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ (epwm)->CAPIEN |= (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Disable capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref EPWM_CAPTURE_INT_RISING_LATCH
+ * - \ref EPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to disable capture interrupt of selected channel.
+ */
+void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ (epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Clear capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref EPWM_CAPTURE_INT_RISING_LATCH
+ * - \ref EPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to clear capture interrupt of selected channel.
+ */
+void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ (epwm)->CAPIF = (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Get capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @retval 0 No capture interrupt
+ * @retval 1 Rising edge latch interrupt
+ * @retval 2 Falling edge latch interrupt
+ * @retval 3 Rising and falling latch interrupt
+ * @details This function is used to get capture interrupt of selected channel.
+ */
+uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ uint32_t u32CapIf = 0UL;
+
+ u32CapIf = ((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1);
+ u32CapIf |= (((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL);
+ return u32CapIf;
+}
+/**
+ * @brief Enable duty interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntDutyType Duty interrupt type, could be either
+ * - \ref EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
+ * - \ref EPWM_DUTY_INT_UP_COUNT_MATCH_CMP
+ * @return None
+ * @details This function is used to enable duty interrupt of selected channel.
+ */
+void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
+{
+ (epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum);
+}
+
+/**
+ * @brief Disable duty interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable duty interrupt of selected channel.
+ */
+void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTEN0 &= ~((EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear duty interrupt flag of selected channel.
+ */
+void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum;
+}
+
+/**
+ * @brief Get duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Duty interrupt did not occur
+ * @retval 1 Duty interrupt occurred
+ * @details This function is used to get duty interrupt flag of selected channel.
+ */
+uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief This function enable fault brake interrupt
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ * - \ref EPWM_FB_EDGE
+ * - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This function is used to enable fault brake interrupt.
+ * The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+ (epwm)->INTEN1 |= (0x7UL << u32BrakeSource);
+}
+
+/**
+ * @brief This function disable fault brake interrupt
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ * - \ref EPWM_FB_EDGE
+ * - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This function is used to disable fault brake interrupt.
+ * The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+ (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource);
+}
+
+/**
+ * @brief This function clear fault brake interrupt of selected source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ * - \ref EPWM_FB_EDGE
+ * - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This function is used to clear fault brake interrupt of selected source.
+ * The write-protection function should be disabled before using this function.
+ */
+void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+ (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource);
+}
+
+/**
+ * @brief This function get fault brake interrupt flag of selected source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source, could be either
+ * - \ref EPWM_FB_EDGE
+ * - \ref EPWM_FB_LEVEL
+ * @return Fault brake interrupt flag of specified source
+ * @retval 0 Fault brake interrupt did not occurred
+ * @retval 1 Fault brake interrupt occurred
+ * @details This function is used to get fault brake interrupt flag of selected source.
+ */
+uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+ return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
+ * @return None
+ * @details This function is used to enable period interrupt of selected channel.
+ */
+void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
+{
+ (epwm)->INTEN0 |= (EPWM_INTEN0_PIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Disable period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable period interrupt of selected channel.
+ */
+void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTEN0 &= ~(EPWM_INTEN0_PIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Clear period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear period interrupt of selected channel.
+ */
+void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTSTS0 = (EPWM_INTSTS0_PIF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Period interrupt flag of specified channel
+ * @retval 0 Period interrupt did not occur
+ * @retval 1 Period interrupt occurred
+ * @details This function is used to get period interrupt of selected channel.
+ */
+uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return ((((epwm)->INTSTS0 & (EPWM_INTSTS0_PIF0_Msk << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable zero interrupt of selected channel.
+ */
+void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTEN0 |= (EPWM_INTEN0_ZIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Disable zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable zero interrupt of selected channel.
+ */
+void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTEN0 &= ~(EPWM_INTEN0_ZIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Clear zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear zero interrupt of selected channel.
+ */
+void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->INTSTS0 = (EPWM_INTSTS0_ZIF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Zero interrupt flag of specified channel
+ * @retval 0 Zero interrupt did not occur
+ * @retval 1 Zero interrupt occurred
+ * @details This function is used to get zero interrupt of selected channel.
+ */
+uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return ((((epwm)->INTSTS0 & (EPWM_INTSTS0_ZIF0_Msk << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable interrupt flag accumulator of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~65535.
+ * @param[in] u32IntAccSrc Interrupt flag accumulator source selection.
+ * - \ref EPWM_IFA_ZERO_POINT
+ * - \ref EPWM_IFA_PERIOD_POINT
+ * - \ref EPWM_IFA_COMPARE_UP_COUNT_POINT
+ * - \ref EPWM_IFA_COMPARE_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator of selected channel.
+ */
+void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc)
+{
+ (epwm)->IFA[u32ChannelNum] = (((epwm)->IFA[u32ChannelNum] & ~((EPWM_IFA0_IFACNT_Msk | EPWM_IFA0_IFASEL_Msk))) | \
+ (EPWM_IFA0_IFAEN_Msk | (u32IntAccSrc << EPWM_IFA0_IFASEL_Pos) | u32IntFlagCnt));
+}
+
+/**
+ * @brief Disable interrupt flag accumulator of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to Disable interrupt flag accumulator of selected channel.
+ */
+void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->IFA[u32ChannelNum] = ((epwm)->IFA[u32ChannelNum] & ~(EPWM_IFA0_IFAEN_Msk));
+}
+
+/**
+ * @brief Enable interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator interrupt of selected channel.
+ */
+void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->AINTEN |= (1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Disable interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable interrupt flag accumulator interrupt of selected channel.
+ */
+void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->AINTEN &= ~(1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Clear interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear interrupt flag accumulator interrupt of selected channel.
+ */
+void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->AINTSTS = (1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Get interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @retval 0 Accumulator interrupt did not occur
+ * @retval 1 Accumulator interrupt occurred
+ * @details This function is used to Get interrupt flag accumulator interrupt of selected channel.
+ */
+uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return (((epwm)->AINTSTS & (1UL << (u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable accumulator PDMA of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable accumulator interrupt trigger PDMA of selected channel.
+ */
+void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->APDMACTL |= (1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Disable accumulator PDMA of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable accumulator interrupt trigger PDMA of selected channel.
+ */
+void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->APDMACTL &= ~(1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Clear free trigger duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear free trigger duty interrupt flag of selected channel.
+ */
+void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->FTCI = ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1));
+}
+
+/**
+ * @brief Get free trigger duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Free trigger duty interrupt did not occur
+ * @retval 1 Free trigger duty interrupt occurred
+ * @details This function is used to get free trigger duty interrupt flag of selected channel.
+ */
+uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return (((epwm)->FTCI & ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable load mode of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode EPWM counter loading mode.
+ * - \ref EPWM_LOAD_MODE_IMMEDIATE
+ * - \ref EPWM_LOAD_MODE_WINDOW
+ * - \ref EPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to enable load mode of selected channel.
+ */
+void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+ (epwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Disable load mode of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode EPWM counter loading mode.
+ * - \ref EPWM_LOAD_MODE_IMMEDIATE
+ * - \ref EPWM_LOAD_MODE_WINDOW
+ * - \ref EPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to disable load mode of selected channel.
+ */
+void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+ (epwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Configure synchronization phase of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32SyncSrc EPWM synchronize source selection.
+ * - \ref EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC
+ * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO
+ * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR
+ * - \ref EPWM_SYNC_OUT_DISABLE
+ * @param[in] u32Direction Phase direction. Control EPWM counter count decrement or increment after synchronizing.
+ * - \ref EPWM_PHS_DIR_DECREMENT
+ * - \ref EPWM_PHS_DIR_INCREMENT
+ * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535.
+ * @return None
+ * @details This function is used to configure synchronization phase of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase)
+{
+ /* every two channels shares the same setting */
+ u32ChannelNum >>= 1;
+ (epwm)->SYNC = (((epwm)->SYNC & ~((EPWM_SYNC_SINSRC0_Msk << (u32ChannelNum << 1)) | (EPWM_SYNC_PHSDIR0_Msk << u32ChannelNum))) | \
+ (u32Direction << EPWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | (u32SyncSrc << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1));
+ (epwm)->PHS[(u32ChannelNum)] = u32StartPhase;
+}
+
+
+/**
+ * @brief Enable SYNC phase of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable SYNC phase of selected channel(s).
+ * @note Every two channels share the same setting.
+ */
+void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0UL; i < EPWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1UL << i))
+ {
+ (epwm)->SYNC |= (EPWM_SYNC_PHSEN0_Msk << (i >> 1));
+ }
+ }
+}
+
+/**
+ * @brief Disable SYNC phase of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable SYNC phase of selected channel(s).
+ * @note Every two channels share the same setting.
+ */
+void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0UL; i < EPWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1UL << i))
+ {
+ (epwm)->SYNC &= ~(EPWM_SYNC_PHSEN0_Msk << (i >> 1));
+ }
+ }
+}
+
+/**
+ * @brief Enable EPWM SYNC_IN noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector.
+ * The valid value is 0~7.
+ * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
+ * - \ref EPWM_NF_CLK_DIV_1
+ * - \ref EPWM_NF_CLK_DIV_2
+ * - \ref EPWM_NF_CLK_DIV_4
+ * - \ref EPWM_NF_CLK_DIV_8
+ * - \ref EPWM_NF_CLK_DIV_16
+ * - \ref EPWM_NF_CLK_DIV_32
+ * - \ref EPWM_NF_CLK_DIV_64
+ * - \ref EPWM_NF_CLK_DIV_128
+ * @return None
+ * @details This function is used to enable EPWM SYNC_IN noise filter function.
+ */
+void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
+{
+ (epwm)->SYNC = ((epwm)->SYNC & ~(EPWM_SYNC_SFLTCNT_Msk | EPWM_SYNC_SFLTCSEL_Msk)) | \
+ ((u32ClkCnt << EPWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << EPWM_SYNC_SFLTCSEL_Pos) | EPWM_SYNC_SNFLTEN_Msk);
+}
+
+/**
+ * @brief Disable EPWM SYNC_IN noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @return None
+ * @details This function is used to Disable EPWM SYNC_IN noise filter function.
+ */
+void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm)
+{
+ (epwm)->SYNC &= ~EPWM_SYNC_SNFLTEN_Msk;
+}
+
+/**
+ * @brief Enable EPWM SYNC input pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @return None
+ * @details This function is used to enable EPWM SYNC input pin inverse function.
+ */
+void EPWM_EnableSyncPinInverse(EPWM_T *epwm)
+{
+ (epwm)->SYNC |= EPWM_SYNC_SINPINV_Msk;
+}
+
+/**
+ * @brief Disable EPWM SYNC input pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @return None
+ * @details This function is used to Disable EPWM SYNC input pin inverse function.
+ */
+void EPWM_DisableSyncPinInverse(EPWM_T *epwm)
+{
+ (epwm)->SYNC &= (~EPWM_SYNC_SINPINV_Msk);
+}
+
+/**
+ * @brief Set EPWM clock source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32ClkSrcSel EPWM external clock source.
+ * - \ref EPWM_CLKSRC_EPWM_CLK
+ * - \ref EPWM_CLKSRC_TIMER0
+ * - \ref EPWM_CLKSRC_TIMER1
+ * - \ref EPWM_CLKSRC_TIMER2
+ * - \ref EPWM_CLKSRC_TIMER3
+ * @return None
+ * @details This function is used to set EPWM clock source.
+ * @note Every two channels share the same setting.
+ * @note If the clock source of EPWM counter is selected from TIMERn interrupt events, the TRGEPWM(TIMERn_TRGCTL[1], n=0,1..3) bit must be set as 1.
+ */
+void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
+{
+ (epwm)->CLKSRC = ((epwm)->CLKSRC & ~(EPWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1) << 3))) | \
+ (u32ClkSrcSel << ((u32ChannelNum >> 1) << 3));
+}
+
+/**
+ * @brief Enable EPWM brake noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector
+ * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
+ * - \ref EPWM_NF_CLK_DIV_1
+ * - \ref EPWM_NF_CLK_DIV_2
+ * - \ref EPWM_NF_CLK_DIV_4
+ * - \ref EPWM_NF_CLK_DIV_8
+ * - \ref EPWM_NF_CLK_DIV_16
+ * - \ref EPWM_NF_CLK_DIV_32
+ * - \ref EPWM_NF_CLK_DIV_64
+ * - \ref EPWM_NF_CLK_DIV_128
+ * @return None
+ * @details This function is used to enable EPWM brake noise filter function.
+ */
+void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
+{
+ (epwm)->BNF = ((epwm)->BNF & ~((EPWM_BNF_BRK0FCNT_Msk | EPWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum << 3))) | \
+ (((u32ClkCnt << EPWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << EPWM_BNF_BRK0NFSEL_Pos) | EPWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum << 3));
+}
+
+/**
+ * @brief Disable EPWM brake noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to disable EPWM brake noise filter function.
+ */
+void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum)
+{
+ (epwm)->BNF &= ~(EPWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum << 3));
+}
+
+/**
+ * @brief Enable EPWM brake pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to enable EPWM brake pin inverse function.
+ */
+void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum)
+{
+ (epwm)->BNF |= (EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum << 3));
+}
+
+/**
+ * @brief Disable EPWM brake pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to disable EPWM brake pin inverse function.
+ */
+void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum)
+{
+ (epwm)->BNF &= ~(EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * (uint32_t)EPWM_BNF_BRK1NFEN_Pos));
+}
+
+/**
+ * @brief Set EPWM brake pin source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE.
+ * @return None
+ * @details This function is used to set EPWM brake pin source.
+ */
+void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
+{
+ (epwm)->BNF = ((epwm)->BNF & ~(EPWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3))) | (u32SelAnotherModule << ((uint32_t)EPWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3)));
+}
+
+/**
+ * @brief Set EPWM leading edge blanking function
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32TrigSrcSel Leading edge blanking source selection.
+ * - \ref EPWM_LEBCTL_SRCEN0
+ * - \ref EPWM_LEBCTL_SRCEN2
+ * - \ref EPWM_LEBCTL_SRCEN4
+ * - \ref EPWM_LEBCTL_SRCEN0_2
+ * - \ref EPWM_LEBCTL_SRCEN0_4
+ * - \ref EPWM_LEBCTL_SRCEN2_4
+ * - \ref EPWM_LEBCTL_SRCEN0_2_4
+ * @param[in] u32TrigType Leading edge blanking trigger type.
+ * - \ref EPWM_LEBCTL_TRGTYPE_RISING
+ * - \ref EPWM_LEBCTL_TRGTYPE_FALLING
+ * - \ref EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING
+ * @param[in] u32BlankingCnt Leading Edge Blanking Counter. Valid values are between 1~512.
+ This counter value decides leading edge blanking window size, and this counter clock base is ECLK.
+ * @param[in] u32BlankingEnable Enable EPWM leading edge blanking function. Valid values are TRUE (ENABLE) or FALSE (DISABLE).
+ * - \ref FALSE
+ * - \ref TRUE
+ * @return None
+ * @details This function is used to configure EPWM leading edge blanking function that blank the false trigger from ACMP brake source which may cause by EPWM output transition.
+ * @note EPWM leading edge blanking function is only used for brake source from ACMP.
+ */
+void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable)
+{
+ (epwm)->LEBCTL = (u32TrigType) | (u32TrigSrcSel) | (u32BlankingEnable);
+ /* Blanking window size = LEBCNT + 1, so LEBCNT = u32BlankingCnt - 1 */
+ (epwm)->LEBCNT = (u32BlankingCnt) - 1UL;
+}
+
+/**
+ * @brief Get the time-base counter reached its maximum value flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Count to max interrupt flag of specified channel
+ * @retval 0 Count to max interrupt did not occur
+ * @retval 1 Count to max interrupt occurred
+ * @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
+ */
+uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ return (((epwm)->STATUS & (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the time-base counter reached its maximum value flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * - EPWM0 : EPWM Group 0
+ * - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
+ */
+void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+ (epwm)->STATUS = (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum);
+}
+
+
+/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EPWM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
--- /dev/null
+/**************************************************************************//**\r
+ * @file fmc.c\r
+ * @version V3.00\r
+ * $Revision: 1 $\r
+ * $Date: 16/07/07 7:50p $\r
+ * @brief M2351 Series Flash Memory Controller(FMC) driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#include <stdio.h>\r
+#include "NuMicro.h"\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup FMC_Driver FMC Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Run flash all one verification and get result.\r
+ *\r
+ * @param[in] u32addr Starting flash address. It must be a page aligned address.\r
+ * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes.\r
+ *\r
+ * @retval READ_ALLONE_YES The contents of verified flash area are 0xA11FFFFF.\r
+ * @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xA1100000.\r
+ * @retval READ_ALLONE_CMD_FAIL Unexpected error occurred.\r
+ *\r
+ * @details Run ISP check all one command to check specify area is all one or not.\r
+ */\r
+uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count)\r
+{\r
+ uint32_t ret = READ_ALLONE_CMD_FAIL;\r
+\r
+ FMC->ISPSTS = 0x80UL; /* clear check all one bit */\r
+\r
+ FMC->ISPCMD = FMC_ISPCMD_RUN_ALL1;\r
+ FMC->ISPADDR = u32addr;\r
+ FMC->ISPDAT = u32count;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }\r
+\r
+ do\r
+ {\r
+ FMC->ISPCMD = FMC_ISPCMD_READ_ALL1;\r
+ FMC->ISPADDR = u32addr;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+ while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }\r
+ }\r
+ while(FMC->ISPDAT == 0UL);\r
+\r
+ if(FMC->ISPDAT == READ_ALLONE_YES)\r
+ {\r
+ ret = FMC->ISPDAT;\r
+ }\r
+\r
+ if(FMC->ISPDAT == READ_ALLONE_NOT)\r
+ {\r
+ ret = FMC->ISPDAT;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Disable ISP Functions\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will clear ISPEN bit of ISPCON to disable ISP function\r
+ *\r
+ */\r
+void FMC_Close(void)\r
+{\r
+ FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Config XOM Region\r
+ * @param[in] u32XomNum The XOM number(0~3)\r
+ * @param[in] u32XomBase The XOM region base address.\r
+ * @param[in] u8XomPage The XOM page number of region size.\r
+ *\r
+ * @retval 0 Success\r
+ * @retval 1 XOM is has already actived.\r
+ * @retval -1 Program failed.\r
+ * @retval -2 Invalid XOM number.\r
+ *\r
+ * @details Program XOM base address and XOM size(page)\r
+ */\r
+int32_t FMC_ConfigXOM(uint32_t u32XomNum, uint32_t u32XomBase, uint8_t u8XomPage)\r
+{\r
+ int32_t ret = 0;\r
+\r
+ if(u32XomNum >= 4UL)\r
+ {\r
+ ret = -2;\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ ret = FMC_GetXOMState(u32XomNum);\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;\r
+ FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u);\r
+ FMC->ISPDAT = u32XomBase;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}\r
+\r
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)\r
+ {\r
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;\r
+ FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x04u);\r
+ FMC->ISPDAT = u8XomPage;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}\r
+\r
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)\r
+ {\r
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;\r
+ FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x08u);\r
+ FMC->ISPDAT = 0u;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}\r
+\r
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)\r
+ {\r
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Execute Flash Page erase\r
+ *\r
+ * @param[in] u32PageAddr Address of the flash page to be erased.\r
+ * It must be a 2048 bytes aligned address.\r
+ *\r
+ * @return ISP page erase success or not.\r
+ * @retval 0 Success\r
+ * @retval -1 Erase failed\r
+ *\r
+ * @details Execute FMC_ISPCMD_PAGE_ERASE command to erase a flash page. The page size is 2048 bytes.\r
+ */\r
+int32_t FMC_Erase(uint32_t u32PageAddr)\r
+{\r
+ int32_t ret = 0;\r
+\r
+ if(ret == 0)\r
+ {\r
+ FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;\r
+ FMC->ISPADDR = u32PageAddr;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }\r
+\r
+ if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)\r
+ {\r
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ }\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Execute Flash Bank erase\r
+ *\r
+ * @param[in] u32BankAddr Base address of the flash bank to be erased.\r
+ *\r
+ * @return ISP bank erase success or not.\r
+ * @retval 0 Success\r
+ * @retval -1 Erase failed\r
+ *\r
+ * @details Execute FMC_ISPCMD_BANK_ERASE command to erase a flash block.\r
+ */\r
+int32_t FMC_Erase_Bank(uint32_t u32BankAddr)\r
+{\r
+ int32_t ret = 0;\r
+\r
+ FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE;\r
+ FMC->ISPADDR = u32BankAddr;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}\r
+\r
+ if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)\r
+ {\r
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Execute Flash Block erase\r
+ *\r
+ * @param[in] u32BlockAddr Address of the flash block to be erased.\r
+ * It must be a 4 pages aligned address.\r
+ *\r
+ * @return ISP block erase success or not.\r
+ * @retval 0 Success\r
+ * @retval -1 Erase failed\r
+ *\r
+ * @details Execute FMC_ISPCMD_BLOCK_ERASE command to erase a flash block. The block size is 4 pages.\r
+ */\r
+int32_t FMC_Erase_Block(uint32_t u32BlockAddr)\r
+{\r
+ int32_t ret = 0;\r
+\r
+ FMC->ISPCMD = FMC_ISPCMD_BLOCK_ERASE;\r
+ FMC->ISPADDR = u32BlockAddr;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}\r
+\r
+ if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)\r
+ {\r
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Execute Erase XOM Region\r
+ *\r
+ * @param[in] u32XomNum The XOMRn(n=0~3)\r
+ *\r
+ * @return XOM erase success or not.\r
+ * @retval 0 Success\r
+ * @retval -1 Erase failed\r
+ * @retval -2 Invalid XOM number.\r
+ *\r
+ * @details Execute FMC_ISPCMD_PAGE_ERASE command to erase XOM.\r
+ */\r
+int32_t FMC_EraseXOM(uint32_t u32XomNum)\r
+{\r
+ uint32_t u32Addr;\r
+ int32_t i32Active, err = 0;\r
+\r
+ if(u32XomNum >= 4UL)\r
+ {\r
+ err = -2;\r
+ }\r
+\r
+ if(err == 0)\r
+ {\r
+ i32Active = FMC_GetXOMState(u32XomNum);\r
+\r
+ if(i32Active)\r
+ {\r
+ switch(u32XomNum)\r
+ {\r
+ case 0u:\r
+ u32Addr = (FMC->XOMR0STS & 0xFFFFFF00u) >> 8u;\r
+ break;\r
+ case 1u:\r
+ u32Addr = (FMC->XOMR1STS & 0xFFFFFF00u) >> 8u;\r
+ break;\r
+ case 2u:\r
+ u32Addr = (FMC->XOMR2STS & 0xFFFFFF00u) >> 8u;\r
+ break;\r
+ case 3u:\r
+ u32Addr = (FMC->XOMR3STS & 0xFFFFFF00u) >> 8u;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;\r
+ FMC->ISPADDR = u32Addr;\r
+ FMC->ISPDAT = 0x55aa03u;\r
+ FMC->ISPTRG = 0x1u;\r
+#if ISBEN\r
+ __ISB();\r
+#endif\r
+ while(FMC->ISPTRG) {}\r
+\r
+ /* Check ISPFF flag to know whether erase OK or fail. */\r
+ if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)\r
+ {\r
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;\r
+ err = -1;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ err = -1;\r
+ }\r
+ }\r
+ return err;\r
+}\r
+\r
+/**\r
+ * @brief Get the current boot source\r
+ *\r
+ * @param None\r
+ *\r
+ * @return The current boot source.\r
+ * @retval 0 This chip is currently booting from APROM\r
+ * @retval 1 This chip is currently booting from LDROM\r
+ *\r
+ * @note This function only show the boot source.\r
+ * User need to read ISPSTA register to know if IAP mode supported or not in relative boot.\r
+ */\r
+int32_t FMC_GetBootSource(void)\r
+{\r
+ int32_t ret = 0;\r
+\r
+ if(FMC->ISPCTL & FMC_ISPCTL_BS_Msk)\r
+ {\r
+ ret = 1;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Run CRC32 checksum calculation and get result.\r
+ *\r
+ * @param[in] u32addr Starting flash address. It must be a page aligned address.\r
+ * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 2048bytes.\r
+ *\r
+ * @return Success or not.\r
+ * @retval 0 Success.\r
+ * @retval 0xFFFFFFFF Invalid parameter.\r
+ *\r
+ * @details Run ISP CRC32 checksum command to calculate checksum then get and return checksum data.\r
+ */\r
+uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count)\r
+{\r
+ uint32_t ret;\r
+\r
+ if((u32addr % 2048UL) || (u32count % 2048UL))\r
+ {\r
+ ret = 0xFFFFFFFF;\r
+ }\r
+ else\r
+ {\r
+ FMC->ISPCMD = FMC_ISPCMD_RUN_CKS;\r
+ FMC->ISPADDR = u32addr;\r
+ FMC->ISPDAT = u32count;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }\r
+\r
+ FMC->ISPCMD = FMC_ISPCMD_READ_CKS;\r
+ FMC->ISPADDR = u32addr;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }\r
+\r
+ ret = FMC->ISPDAT;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Check the OTP is locked or not.\r
+ *\r
+ * @param[in] u32OtpNum The OTP number.\r
+ *\r
+ * @retval 1 OTP is locked.\r
+ * @retval 0 OTP is not locked.\r
+ * @retval -1 Failed to read OTP lock bits.\r
+ * @retval -2 Invalid OTP number.\r
+ *\r
+ * @details To get specify OTP lock status\r
+ */\r
+int32_t FMC_Is_OTP_Locked(uint32_t u32OtpNum)\r
+{\r
+ int32_t ret = 0;\r
+\r
+ if(u32OtpNum > 255UL)\r
+ {\r
+ ret = -2;\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ FMC->ISPCMD = FMC_ISPCMD_READ;\r
+ FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + u32OtpNum * 4UL;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }\r
+\r
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)\r
+ {\r
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ else\r
+ {\r
+ if(FMC->ISPDAT != 0xFFFFFFFFUL)\r
+ {\r
+ ret = 1; /* Lock work was progrmmed. OTP was locked. */\r
+ }\r
+ }\r
+ }\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Check the XOM is actived or not.\r
+ *\r
+ * @param[in] u32XomNum The xom number(0~3).\r
+ *\r
+ * @retval 1 XOM is actived.\r
+ * @retval 0 XOM is not actived.\r
+ * @retval -2 Invalid XOM number.\r
+ *\r
+ * @details To get specify XOMRn(n=0~3) active status\r
+ */\r
+int32_t FMC_GetXOMState(uint32_t u32XomNum)\r
+{\r
+ uint32_t u32act;\r
+ int32_t ret = 0;\r
+\r
+ if(u32XomNum >= 4UL)\r
+ {\r
+ ret = -2;\r
+ }\r
+\r
+ if(ret >= 0)\r
+ {\r
+ u32act = (((FMC->XOMSTS) & 0xful) & (1ul << u32XomNum)) >> u32XomNum;\r
+ ret = (int32_t)u32act;\r
+ }\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Lock the specified OTP.\r
+ *\r
+ * @param[in] u32OtpNum The OTP number.\r
+ *\r
+ * @retval 0 Success\r
+ * @retval -1 Failed to write OTP lock bits.\r
+ * @retval -2 Invalid OTP number.\r
+ *\r
+ * @details To lock specified OTP number\r
+ */\r
+int32_t FMC_Lock_OTP(uint32_t u32OtpNum)\r
+{\r
+ int32_t ret = 0;\r
+\r
+ if(u32OtpNum > 255UL)\r
+ {\r
+ ret = -2;\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;\r
+ FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + u32OtpNum * 4UL;\r
+ FMC->ISPDAT = 0UL;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }\r
+\r
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)\r
+ {\r
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ }\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Enable FMC ISP function\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details ISPEN bit of ISPCON must be set before we can use ISP commands.\r
+ * Therefore, To use all FMC function APIs, user needs to call FMC_Open() first to enable ISP functions.\r
+ *\r
+ * @note ISP functions are write-protected. user also needs to unlock it by calling SYS_UnlockReg() before using all ISP functions.\r
+ *\r
+ */\r
+void FMC_Open(void)\r
+{\r
+ FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Read a word bytes from flash\r
+ *\r
+ * @param[in] u32Addr Address of the flash location to be read.\r
+ * It must be a word aligned address.\r
+ *\r
+ * @return The word data read from specified flash address.\r
+ *\r
+ * @details Execute FMC_ISPCMD_READ command to read a word from flash.\r
+ */\r
+uint32_t FMC_Read(uint32_t u32Addr)\r
+{\r
+ FMC->ISPCMD = FMC_ISPCMD_READ;\r
+ FMC->ISPADDR = u32Addr;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }\r
+\r
+ return FMC->ISPDAT;\r
+}\r
+\r
+/**\r
+ * @brief Read a double-word bytes from flash\r
+ *\r
+ * @param[in] u32addr Address of the flash location to be read.\r
+ * It must be a double-word aligned address.\r
+ *\r
+ * @param[out] u32data0 Place holder of word 0 read from flash address u32addr.\r
+ * @param[out] u32data1 Place holder of word 0 read from flash address u32addr+4.\r
+ *\r
+ * @return 0 Success\r
+ * @return -1 Failed\r
+ *\r
+ * @details Execute FMC_ISPCMD_READ_64 command to read a double-word from flash.\r
+ */\r
+int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1)\r
+{\r
+ int32_t ret = 0;\r
+\r
+ FMC->ISPCMD = FMC_ISPCMD_READ_64;\r
+ FMC->ISPADDR = u32addr;\r
+ FMC->ISPDAT = 0x0UL;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }\r
+\r
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)\r
+ {\r
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ else\r
+ {\r
+ *u32data0 = FMC->MPDAT0;\r
+ *u32data1 = FMC->MPDAT1;\r
+ }\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Read data from OTP\r
+ *\r
+ * @param[in] u32OtpNum The OTP number(0~255).\r
+ * @param[in] u32LowWord Low word of the 64-bits data.\r
+ * @param[in] u32HighWord High word of the 64-bits data.\r
+ *\r
+ * @retval 0 Success\r
+ * @retval -1 Read failed.\r
+ * @retval -2 Invalid OTP number.\r
+ *\r
+ * @details Read the 64-bits data from the specified OTP.\r
+ */\r
+int32_t FMC_Read_OTP(uint32_t u32OtpNum, uint32_t *u32LowWord, uint32_t *u32HighWord)\r
+{\r
+ int32_t ret = 0;\r
+\r
+ if(u32OtpNum > 255UL)\r
+ {\r
+ ret = -2;\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ FMC->ISPCMD = FMC_ISPCMD_READ_64;\r
+ FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL ;\r
+ FMC->ISPDAT = 0x0UL;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) {}\r
+\r
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)\r
+ {\r
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ else\r
+ {\r
+ *u32LowWord = FMC->MPDAT0;\r
+ *u32HighWord = FMC->MPDAT1;\r
+ }\r
+ }\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Read the User Configuration words.\r
+ *\r
+ * @param[out] u32Config[] The word buffer to store the User Configuration data.\r
+ * @param[in] u32Count The word count to be read.\r
+ *\r
+ * @return Success or not.\r
+ * @retval 0 Success\r
+ * @retval -1 Failed\r
+ *\r
+ * @details This function is used to read the settings of user configuration.\r
+ * if u32Count = 1, Only CONFIG0 will be returned to the buffer specified by u32Config.\r
+ * if u32Count = 2, Both CONFIG0 and CONFIG1 will be returned.\r
+ */\r
+int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count)\r
+{\r
+ uint32_t i;\r
+\r
+ for(i = 0u; i < u32Count; i++)\r
+ {\r
+ u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4u);\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * @brief Set boot source from LDROM or APROM after next software reset\r
+ *\r
+ * @param[in] i32BootSrc\r
+ * 1: Boot from LDROM\r
+ * 0: Boot from APROM\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to switch APROM boot or LDROM boot. User need to call\r
+ * FMC_SetBootSource to select boot source first, then use CPU reset or\r
+ * System Reset Request to reset system.\r
+ *\r
+ */\r
+void FMC_SetBootSource(int32_t i32BootSrc)\r
+{\r
+ if(i32BootSrc)\r
+ {\r
+ FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */\r
+ }\r
+ else\r
+ {\r
+ FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Execute Security Key Comparison.\r
+ *\r
+ * @param[in] key Key 0~2 to be compared.\r
+ *\r
+ * @retval 0 Key matched.\r
+ * @retval -1 Forbidden. Times of key comparison mismatch reach the maximum count.\r
+ * @retval -2 Key mismatched.\r
+ * @retval -3 No KPROM key lock. Key comparison is not required.\r
+ *\r
+ * @ details Input a keys to compare with security key\r
+ */\r
+int32_t FMC_CompareSPKey(uint32_t key[3])\r
+{\r
+ uint32_t u32KeySts;\r
+ int32_t ret = 0;\r
+\r
+ if(FMC->KPKEYSTS & FMC_KPKEYSTS_FORBID_Msk)\r
+ {\r
+ /* FMC_SKey_Compare - FORBID! */\r
+ ret = -1;\r
+ }\r
+\r
+ if(!(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYLOCK_Msk))\r
+ {\r
+ /* FMC_SKey_Compare - key is not locked! */\r
+ ret = -3;\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ FMC->KPKEY0 = key[0];\r
+ FMC->KPKEY1 = key[1];\r
+ FMC->KPKEY2 = key[2];\r
+ FMC->KPKEYTRG = FMC_KPKEYTRG_KPKEYGO_Msk | FMC_KPKEYTRG_TCEN_Msk;\r
+\r
+ while(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { }\r
+\r
+ u32KeySts = FMC->KPKEYSTS;\r
+\r
+ if(!(u32KeySts & FMC_KPKEYSTS_KEYMATCH_Msk))\r
+ {\r
+ /* Key mismatched! */\r
+ ret = -2;\r
+ }\r
+ else if(u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk)\r
+ {\r
+ /* Key matched, but still be locked! */\r
+ ret = -2;\r
+ }\r
+ }\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Setup Security Key.\r
+ *\r
+ * @param[in] au32Key Key 0~2 to be setup.\r
+ * @param[in] u32Kpmax Maximum unmatched power-on counting number.\r
+ * @param[in] u32Kemax Maximum unmatched counting number.\r
+ * @param[in] i32LockCONFIG 1: Security key lock CONFIG to write-protect. 0: Don't lock CONFIG.\r
+ * @param[in] i32LockSPROM 1: Security key lock SPROM to write-protect. 0: Don't lock SPROM. (This param is not supported on M2351)\r
+ *\r
+ * @retval 0 Success.\r
+ * @retval -1 Key is locked. Cannot overwrite the current key.\r
+ * @retval -2 Failed to erase flash.\r
+ * @retval -3 Failed to program key.\r
+ * @retval -4 Key lock function failed.\r
+ * @retval -5 CONFIG lock function failed.\r
+ * @retval -6 SPROM lock function failed. (This status is not supported on M2351)\r
+ * @retval -7 KPMAX function failed.\r
+ * @retval -8 KEMAX function failed.\r
+ *\r
+ * @details Set secure keys and setup key compare count. The secure key also can protect user config.\r
+ */\r
+int32_t FMC_SetSPKey(uint32_t au32Key[3], uint32_t u32Kpmax, uint32_t u32Kemax,\r
+ const int32_t i32LockCONFIG, const int32_t i32LockSPROM)\r
+{\r
+ uint32_t lock_ctrl = 0UL;\r
+ uint32_t u32KeySts;\r
+ int32_t ret = 0;\r
+\r
+ if(FMC->KPKEYSTS != 0x200UL)\r
+ {\r
+ ret = -1;\r
+ }\r
+\r
+ if(FMC_Erase(FMC_KPROM_BASE))\r
+ {\r
+ ret = -2;\r
+ }\r
+\r
+ if(FMC_Erase(FMC_KPROM_BASE + 0x200UL))\r
+ {\r
+ ret = -3;\r
+ }\r
+\r
+ if(!i32LockCONFIG)\r
+ {\r
+ lock_ctrl |= 0x1UL;\r
+ }\r
+\r
+ if(!i32LockSPROM)\r
+ {\r
+ lock_ctrl |= 0x2UL;\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ FMC_Write(FMC_KPROM_BASE, au32Key[0]);\r
+ FMC_Write(FMC_KPROM_BASE + 0x4UL, au32Key[1]);\r
+ FMC_Write(FMC_KPROM_BASE + 0x8UL, au32Key[2]);\r
+ FMC_Write(FMC_KPROM_BASE + 0xCUL, u32Kpmax);\r
+ FMC_Write(FMC_KPROM_BASE + 0x10UL, u32Kemax);\r
+ FMC_Write(FMC_KPROM_BASE + 0x14UL, lock_ctrl);\r
+\r
+ while(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { }\r
+\r
+ u32KeySts = FMC->KPKEYSTS;\r
+\r
+ if(!(u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk))\r
+ {\r
+ /* Security key lock failed! */\r
+ ret = -4;\r
+ }\r
+ else if((i32LockCONFIG && (!(u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) ||\r
+ ((!i32LockCONFIG) && (u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk)))\r
+ {\r
+ /* CONFIG lock failed! */\r
+ ret = -5;\r
+ }\r
+ else if(((FMC->KPCNT & FMC_KPCNT_KPMAX_Msk) >> FMC_KPCNT_KPMAX_Pos) != u32Kpmax)\r
+ {\r
+ /* KPMAX failed! */\r
+ ret = -7;\r
+ }\r
+ else if(((FMC->KPKEYCNT & FMC_KPKEYCNT_KPKEMAX_Msk) >> FMC_KPKEYCNT_KPKEMAX_Pos) != u32Kemax)\r
+ {\r
+ /* KEMAX failed! */\r
+ ret = -8;\r
+ }\r
+ }\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Write a word bytes to flash.\r
+ *\r
+ * @param[in] u32Addr Address of the flash location to be programmed.\r
+ * It must be a word aligned address.\r
+ * @param[in] u32Data The word data to be programmed.\r
+ *\r
+ * @return None\r
+ *\r
+ * @ details Execute ISP FMC_ISPCMD_PROGRAM to program a word to flash.\r
+ */\r
+void FMC_Write(uint32_t u32Addr, uint32_t u32Data)\r
+{\r
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;\r
+ FMC->ISPADDR = u32Addr;\r
+ FMC->ISPDAT = u32Data;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }\r
+}\r
+\r
+/**\r
+ * @brief Write a double-word bytes to flash\r
+ *\r
+ * @param[in] u32addr Address of the flash location to be programmed.\r
+ * It must be a double-word aligned address.\r
+ * @param[in] u32data0 The word data to be programmed to flash address u32addr.\r
+ * @param[in] u32data1 The word data to be programmed to flash address u32addr+4.\r
+ *\r
+ * @return 0 Success\r
+ * @return -1 Failed\r
+ *\r
+ * @ details Execute ISP FMC_ISPCMD_PROGRAM_64 to program a double-word to flash.\r
+ */\r
+int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1)\r
+{\r
+ int32_t ret = 0;\r
+\r
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM_64;\r
+ FMC->ISPADDR = u32addr;\r
+ FMC->MPDAT0 = u32data0;\r
+ FMC->MPDAT1 = u32data1;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }\r
+\r
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)\r
+ {\r
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Write User Configuration\r
+ *\r
+ * @param[in] au32Config[] The word buffer to store the User Configuration data.\r
+ * @param[in] u32Count The word count to program to User Configuration.\r
+ *\r
+ * @retval 0 Success\r
+ * @retval -1 Failed\r
+ *\r
+ * @details User must enable User Configuration update before writing it.\r
+ * User must erase User Configuration before writing it.\r
+ * User Configuration is also be page erase. User needs to backup necessary data\r
+ * before erase User Configuration.\r
+ */\r
+int32_t FMC_WriteConfig(uint32_t au32Config[], uint32_t u32Count)\r
+{\r
+ int32_t ret = 0;\r
+ uint32_t i;\r
+\r
+ FMC_ENABLE_CFG_UPDATE();\r
+ for(i = 0u; i < u32Count; i++)\r
+ {\r
+ FMC_Write(FMC_CONFIG_BASE + i * 4u, au32Config[i]);\r
+ if(FMC_Read(FMC_CONFIG_BASE + i * 4u) != au32Config[i])\r
+ {\r
+ ret = -1;\r
+ }\r
+ }\r
+ FMC_DISABLE_CFG_UPDATE();\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Write Multi-Word bytes to flash\r
+ *\r
+ * @param[in] u32Addr Start flash address in APROM where the data chunk to be programmed into.\r
+ * This address must be 8-bytes aligned to flash address.\r
+ * @param[in] pu32Buf Buffer that carry the data chunk.\r
+ * @param[in] u32Len Length of the data chunk in bytes.\r
+ *\r
+ * @retval >=0 Number of data bytes were programmed.\r
+ * @return -1 Invalid address.\r
+ *\r
+ * @details Program Multi-Word data into specified address of flash.\r
+ */\r
+\r
+int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len)\r
+{\r
+\r
+ uint32_t i, idx, u32OnProg, retval = 0;\r
+ int32_t err;\r
+\r
+ if((u32Addr >= FMC_APROM_END) || ((u32Addr % 8) != 0))\r
+ {\r
+ return -1;\r
+ }\r
+\r
+ idx = 0u;\r
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM_MUL;\r
+ FMC->ISPADDR = u32Addr;\r
+ retval += 16;\r
+ do\r
+ {\r
+ err = 0;\r
+ u32OnProg = 1u;\r
+ FMC->MPDAT0 = pu32Buf[idx + 0u];\r
+ FMC->MPDAT1 = pu32Buf[idx + 1u];\r
+ FMC->MPDAT2 = pu32Buf[idx + 2u];\r
+ FMC->MPDAT3 = pu32Buf[idx + 3u];\r
+ FMC->ISPTRG = 0x1u;\r
+ idx += 4u;\r
+\r
+ for(i = idx; i < (FMC_MULTI_WORD_PROG_LEN / 4u); i += 4u) /* Max data length is 256 bytes (512/4 words)*/\r
+ {\r
+ __set_PRIMASK(1u); /* Mask interrupt to avoid status check coherence error*/\r
+ do\r
+ {\r
+ if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u)\r
+ {\r
+ __set_PRIMASK(0u);\r
+\r
+ FMC->ISPADDR = FMC->MPADDR & (~0xful);\r
+ idx = (FMC->ISPADDR - u32Addr) / 4u;\r
+ err = -1;\r
+ }\r
+ }\r
+ while((FMC->MPSTS & (3u << FMC_MPSTS_D0_Pos)) && (err == 0));\r
+\r
+ if(err == 0)\r
+ {\r
+ retval += 8;\r
+\r
+ /* Update new data for D0 */\r
+ FMC->MPDAT0 = pu32Buf[i];\r
+ FMC->MPDAT1 = pu32Buf[i + 1u];\r
+ do\r
+ {\r
+ if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u)\r
+ {\r
+ __set_PRIMASK(0u);\r
+ FMC->ISPADDR = FMC->MPADDR & (~0xful);\r
+ idx = (FMC->ISPADDR - u32Addr) / 4u;\r
+ err = -1;\r
+ }\r
+ }\r
+ while((FMC->MPSTS & (3u << FMC_MPSTS_D2_Pos)) && (err == 0));\r
+\r
+ if(err == 0)\r
+ {\r
+ retval += 8;\r
+\r
+ /* Update new data for D2*/\r
+ FMC->MPDAT2 = pu32Buf[i + 2u];\r
+ FMC->MPDAT3 = pu32Buf[i + 3u];\r
+ __set_PRIMASK(0u);\r
+ }\r
+ }\r
+\r
+ if(err < 0)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ if(err == 0)\r
+ {\r
+ u32OnProg = 0u;\r
+ while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) {}\r
+ }\r
+ }\r
+ while(u32OnProg);\r
+\r
+ return retval;\r
+}\r
+\r
+/**\r
+ * @brief Write data to OTP\r
+ *\r
+ * @param[in] u32OtpNum The OTP number(0~255).\r
+ * @param[in] u32LowWord Low word of the 64-bits data.\r
+ * @param[in] u32HighWord High word of the 64-bits data.\r
+ *\r
+ * @retval 0 Success\r
+ * @retval -1 Program failed.\r
+ * @retval -2 Invalid OTP number.\r
+ *\r
+ * @details Program a 64-bits data to the specified OTP.\r
+ */\r
+int32_t FMC_Write_OTP(uint32_t u32OtpNum, uint32_t u32LowWord, uint32_t u32HighWord)\r
+{\r
+ int32_t ret = 0;\r
+\r
+ if(u32OtpNum > 255UL)\r
+ {\r
+ ret = -2;\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;\r
+ FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL;\r
+ FMC->ISPDAT = u32LowWord;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }\r
+\r
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)\r
+ {\r
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ }\r
+\r
+ if(ret == 0)\r
+ {\r
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;\r
+ FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL + 4UL;\r
+ FMC->ISPDAT = u32HighWord;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+\r
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }\r
+\r
+ if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)\r
+ {\r
+ FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;\r
+ ret = -1;\r
+ }\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group FMC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
+\r
--- /dev/null
+/**************************************************************************//**
+ * @file gpio.c
+ * @version V3.00
+ * @brief M2351 series General Purpose I/O (GPIO) driver source file
+ *
+ * @note
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+ @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+ @{
+*/
+
+/**
+ * @brief Set GPIO operation mode
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
+ * It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ * It could be BIT0 ~ BIT13 for PC. \n
+ * It could be BIT0 ~ BIT14 for PD. \n
+ * It could be BIT0 ~ BIT11 for PF. \n
+ * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ * It could be BIT4 ~ BIT11 for PH.
+ * @param[in] u32Mode Operation mode. It could be
+ * - \ref GPIO_MODE_INPUT
+ * - \ref GPIO_MODE_OUTPUT
+ * - \ref GPIO_MODE_OPEN_DRAIN
+ * - \ref GPIO_MODE_QUASI
+ *
+ * @return None
+ *
+ * @details This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+ uint32_t u32Idx;
+
+ for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++)
+ {
+ if((u32PinMask & (1ul << u32Idx)) == (1ul << u32Idx))
+ {
+ port->MODE = (port->MODE & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1));
+ }
+ }
+}
+
+/**
+ * @brief Enable GPIO interrupt
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32Pin The pin of specified GPIO port. \n
+ * It could be 0 ~ 15 for PA, PB and PE. \n
+ * It could be 0 ~ 13 for PC GPIO port. \n
+ * It could be 0 ~ 14 for PD GPIO port. \n
+ * It could be 0 ~ 11 for PF GPIO port. \n
+ * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n
+ * It could be 4 ~ 11 for PH GPIO port.
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be
+ * - \ref GPIO_INT_RISING
+ * - \ref GPIO_INT_FALLING
+ * - \ref GPIO_INT_BOTH_EDGE
+ * - \ref GPIO_INT_HIGH
+ * - \ref GPIO_INT_LOW
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
+{
+ /* Configure interrupt mode of specified pin */
+ port->INTTYPE = (port->INTTYPE & ~(1ul << u32Pin)) | (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
+
+ /* Enable interrupt function of specified pin */
+ port->INTEN = (port->INTEN & ~(0x00010001ul << u32Pin)) | ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
+}
+
+
+/**
+ * @brief Disable GPIO interrupt
+ *
+
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32Pin The pin of specified GPIO port. \n
+ * It could be 0 ~ 15 for PA, PB and PE. \n
+ * It could be 0 ~ 13 for PC GPIO port. \n
+ * It could be 0 ~ 14 for PD GPIO port. \n
+ * It could be 0 ~ 11 for PF GPIO port. \n
+ * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n
+ * It could be 4 ~ 11 for PH GPIO port.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
+{
+ /* Configure interrupt mode of specified pin */
+ port->INTTYPE &= ~(1UL << u32Pin);
+
+ /* Disable interrupt function of specified pin */
+ port->INTEN &= ~((0x00010001UL) << u32Pin);
+}
+
+/**
+ * @brief Set GPIO slew rate control
+ *
+
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
+ * It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ * It could be BIT0 ~ BIT13 for PC. \n
+ * It could be BIT0 ~ BIT14 for PD. \n
+ * It could be BIT0 ~ BIT11 for PF. \n
+ * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ * It could be BIT4 ~ BIT11 for PH.
+ * @param[in] u32Mode Slew rate mode. It could be
+ * - \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V)
+ * - \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V)
+ * - \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V)
+ *
+ * @return None
+ *
+ * @details This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+ uint32_t u32Idx;
+
+ for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++)
+ {
+ if(u32PinMask & (1ul << u32Idx))
+ {
+ port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1));
+ }
+ }
+}
+
+/**
+ * @brief Set GPIO Pull-up and Pull-down control
+ *
+
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
+ * It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ * It could be BIT0 ~ BIT13 for PC. \n
+ * It could be BIT0 ~ BIT14 for PD. \n
+ * It could be BIT0 ~ BIT11 for PF. \n
+ * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ * It could be BIT4 ~ BIT11 for PH.
+ * @param[in] u32Mode The pin mode of specified GPIO pin. It could be
+ * - \ref GPIO_PUSEL_DISABLE
+ * - \ref GPIO_PUSEL_PULL_UP
+ * - \ref GPIO_PUSEL_PULL_DOWN
+ *
+ * @return None
+ *
+ * @details Set the pin mode of specified GPIO pin.
+ */
+void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+ uint32_t u32Idx;
+
+ for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++)
+ {
+ if(u32PinMask & (1ul << u32Idx))
+ {
+ port->PUSEL = (port->PUSEL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1));
+ }
+ }
+}
+
+/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group GPIO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
--- /dev/null
+/**************************************************************************//**\r
+ * @file i2c.c\r
+ * @version V3.00\r
+ * $Revision: 2 $\r
+ * $Date: 16/08/02 6:02p $\r
+ * @brief M2351 series I2C Serial Interface Controller(I2C) driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup I2C_Driver I2C Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Enable specify I2C Controller and set Clock Divider\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u32BusClock The target I2C bus clock in Hz\r
+ *\r
+ * @return Actual I2C bus clock frequency\r
+ *\r
+ * @details The function enable the specify I2C Controller and set proper Clock Divider\r
+ * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock.\r
+ * I2C Bus clock = PCLK / (4*(divider+1).\r
+ *\r
+ */\r
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)\r
+{\r
+ uint32_t u32Div;\r
+ uint32_t u32Pclk;\r
+\r
+ if((i2c == I2C1) || (i2c == I2C1_NS))\r
+ {\r
+ u32Pclk = CLK_GetPCLK1Freq();\r
+ }\r
+ else\r
+ {\r
+ u32Pclk = CLK_GetPCLK0Freq();\r
+ }\r
+\r
+ u32Div = (uint32_t)(((u32Pclk * 10u) / (u32BusClock * 4u) + 5u) / 10u - 1u); /* Compute proper divider for I2C clock */\r
+ i2c->CLKDIV = u32Div;\r
+\r
+ /* Enable I2C */\r
+ i2c->CTL0 |= I2C_CTL0_I2CEN_Msk;\r
+\r
+ return (u32Pclk / ((u32Div + 1u) << 2u));\r
+}\r
+\r
+/**\r
+ * @brief Disable specify I2C Controller\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Reset I2C Controller and disable specify I2C port.\r
+ *\r
+ */\r
+\r
+void I2C_Close(I2C_T *i2c)\r
+{\r
+ /* Reset I2C Controller */\r
+ if(i2c == I2C0)\r
+ {\r
+ SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;\r
+ SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;\r
+ }\r
+ else if(i2c == I2C1)\r
+ {\r
+ SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk;\r
+ SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk;\r
+ }\r
+ else if(i2c == I2C2)\r
+ {\r
+ SYS->IPRST1 |= SYS_IPRST1_I2C2RST_Msk;\r
+ SYS->IPRST1 &= ~SYS_IPRST1_I2C2RST_Msk;\r
+ }\r
+\r
+ /* Disable I2C */\r
+ i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Clear Time-out Counter flag\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag .\r
+ *\r
+ */\r
+void I2C_ClearTimeoutFlag(I2C_T *i2c)\r
+{\r
+ i2c->TOCTL |= I2C_TOCTL_TOIF_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Set Control bit of I2C Controller\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u8Start Set I2C START condition\r
+ * @param[in] u8Stop Set I2C STOP condition\r
+ * @param[in] u8Si Clear SI flag\r
+ * @param[in] u8Ack Set I2C ACK bit\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function set I2C Control bit of I2C Bus protocol.\r
+ *\r
+ */\r
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)\r
+{\r
+ uint32_t u32Reg = 0u;\r
+\r
+ if(u8Start)\r
+ {\r
+ u32Reg |= I2C_CTL_STA;\r
+ }\r
+ if(u8Stop)\r
+ {\r
+ u32Reg |= I2C_CTL_STO;\r
+ }\r
+ if(u8Si)\r
+ {\r
+ u32Reg |= I2C_CTL_SI;\r
+ }\r
+ if(u8Ack)\r
+ {\r
+ u32Reg |= I2C_CTL_AA;\r
+ }\r
+\r
+ i2c->CTL0 = (i2c->CTL0 & ~0x3Cu) | u32Reg;\r
+}\r
+\r
+/**\r
+ * @brief Disable Interrupt of I2C Controller\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used for disable I2C interrupt\r
+ *\r
+ */\r
+void I2C_DisableInt(I2C_T *i2c)\r
+{\r
+ i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable Interrupt of I2C Controller\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used for enable I2C interrupt\r
+ *\r
+ */\r
+void I2C_EnableInt(I2C_T *i2c)\r
+{\r
+ i2c->CTL0 |= I2C_CTL0_INTEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Get I2C Bus Clock\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return The actual I2C Bus clock in Hz\r
+ *\r
+ * @details To get the actual I2C Bus Clock frequency.\r
+ */\r
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c)\r
+{\r
+ uint32_t u32Divider = i2c->CLKDIV;\r
+ uint32_t u32Pclk;\r
+\r
+ if((i2c == I2C1) || (i2c == I2C1_NS))\r
+ {\r
+ u32Pclk = CLK_GetPCLK1Freq();\r
+ }\r
+ else\r
+ {\r
+ u32Pclk = CLK_GetPCLK0Freq();\r
+ }\r
+\r
+ return (u32Pclk / ((u32Divider + 1u) << 2u));\r
+}\r
+\r
+/**\r
+ * @brief Set I2C Bus Clock\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u32BusClock The target I2C Bus Clock in Hz\r
+ *\r
+ * @return The actual I2C Bus Clock in Hz\r
+ *\r
+ * @details To set the actual I2C Bus Clock frequency.\r
+ */\r
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)\r
+{\r
+ uint32_t u32Div;\r
+ uint32_t u32Pclk;\r
+\r
+ if((i2c == I2C1) || (i2c == I2C1_NS))\r
+ {\r
+ u32Pclk = CLK_GetPCLK1Freq();\r
+ }\r
+ else\r
+ {\r
+ u32Pclk = CLK_GetPCLK0Freq();\r
+ }\r
+\r
+ u32Div = (uint32_t)(((u32Pclk * 10u) / (u32BusClock * 4u) + 5u) / 10u - 1u); /* Compute proper divider for I2C clock */\r
+ i2c->CLKDIV = u32Div;\r
+\r
+ return (u32Pclk / ((u32Div + 1u) << 2u));\r
+}\r
+\r
+/**\r
+ * @brief Get Interrupt Flag\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return I2C interrupt flag status\r
+ *\r
+ * @details To get I2C Bus interrupt flag.\r
+ */\r
+uint32_t I2C_GetIntFlag(I2C_T *i2c)\r
+{\r
+ return ((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk ? 1ul : 0ul);\r
+}\r
+\r
+/**\r
+ * @brief Get I2C Bus Status Code\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return I2C Status Code\r
+ *\r
+ * @details To get I2C Bus Status Code.\r
+ */\r
+uint32_t I2C_GetStatus(I2C_T *i2c)\r
+{\r
+ return (i2c->STATUS0);\r
+}\r
+\r
+/**\r
+ * @brief Read a Byte from I2C Bus\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return I2C Data\r
+ *\r
+ * @details To read a bytes data from specify I2C port.\r
+ */\r
+uint8_t I2C_GetData(I2C_T *i2c)\r
+{\r
+ return (uint8_t)(i2c->DAT);\r
+}\r
+\r
+/**\r
+ * @brief Send a byte to I2C Bus\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u8Data The data to send to I2C bus\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to write a byte to specified I2C port\r
+ */\r
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data)\r
+{\r
+ i2c->DAT = u8Data;\r
+}\r
+\r
+/**\r
+ * @brief Set 7-bit Slave Address and GC Mode\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u8SlaveNo Set the number of I2C address register (0~3)\r
+ * @param[in] u8SlaveAddr 7-bit slave address\r
+ * @param[in] u8GCMode Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE)\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3)\r
+ * and enable GC Mode.\r
+ *\r
+ */\r
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)\r
+{\r
+ switch(u8SlaveNo)\r
+ {\r
+ case 1:\r
+ i2c->ADDR1 = ((uint32_t)u8SlaveAddr << 1) | u8GCMode;\r
+ break;\r
+ case 2:\r
+ i2c->ADDR2 = ((uint32_t)u8SlaveAddr << 1) | u8GCMode;\r
+ break;\r
+ case 3:\r
+ i2c->ADDR3 = ((uint32_t)u8SlaveAddr << 1) | u8GCMode;\r
+ break;\r
+ case 0:\r
+ default:\r
+ i2c->ADDR0 = ((uint32_t)u8SlaveAddr << 1) | u8GCMode;\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the mask bits of 7-bit Slave Address\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3)\r
+ * @param[in] u8SlaveAddrMask A byte for slave address mask\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to set 7-bit slave addresses.\r
+ *\r
+ */\r
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)\r
+{\r
+ switch(u8SlaveNo)\r
+ {\r
+ case 1:\r
+ i2c->ADDRMSK1 = (uint32_t)u8SlaveAddrMask << 1;\r
+ break;\r
+ case 2:\r
+ i2c->ADDRMSK2 = (uint32_t)u8SlaveAddrMask << 1;\r
+ break;\r
+ case 3:\r
+ i2c->ADDRMSK3 = (uint32_t)u8SlaveAddrMask << 1;\r
+ break;\r
+ case 0:\r
+ default:\r
+ i2c->ADDRMSK0 = (uint32_t)u8SlaveAddrMask << 1;\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable Time-out Counter Function and support Long Time-out\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1)\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function enable Time-out Counter function and configure DIV4 to support Long\r
+ * Time-out.\r
+ *\r
+ */\r
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)\r
+{\r
+ if(u8LongTimeout)\r
+ {\r
+ i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk;\r
+ }\r
+ else\r
+ {\r
+ i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk;\r
+ }\r
+\r
+ i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable Time-out Counter Function\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To disable Time-out Counter function in I2CTOC register.\r
+ *\r
+ */\r
+void I2C_DisableTimeout(I2C_T *i2c)\r
+{\r
+ i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable I2C Wake-up Function\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To enable Wake-up function of I2C Wake-up control register.\r
+ *\r
+ */\r
+void I2C_EnableWakeup(I2C_T *i2c)\r
+{\r
+ i2c->WKCTL |= I2C_WKCTL_WKEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable I2C Wake-up Function\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To disable Wake-up function of I2C Wake-up control register.\r
+ *\r
+ */\r
+void I2C_DisableWakeup(I2C_T *i2c)\r
+{\r
+ i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief To get SMBus Status\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return SMBus status\r
+ *\r
+ * @details To get the Bus Management status of I2C_BUSSTS register\r
+ *\r
+ */\r
+uint32_t I2C_SMBusGetStatus(I2C_T *i2c)\r
+{\r
+ return (i2c->BUSSTS);\r
+}\r
+\r
+/**\r
+ * @brief Clear SMBus Interrupt Flag\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u8SMBusIntFlag Specify SMBus interrupt flag\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To clear flags of I2C_BUSSTS status register if interrupt set.\r
+ *\r
+ */\r
+void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag)\r
+{\r
+ i2c->BUSSTS = u8SMBusIntFlag;\r
+}\r
+\r
+/**\r
+ * @brief Set SMBus Bytes Counts of Transmission or Reception\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u32PktSize Transmit / Receive bytes\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.\r
+ *\r
+ */\r
+void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize)\r
+{\r
+ i2c->PKTSIZE = u32PktSize;\r
+}\r
+\r
+/**\r
+ * @brief Init SMBus Host/Device Mode\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u8HostDevice Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0))\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Using SMBus communication must specify the port is a Host or a Device.\r
+ *\r
+ */\r
+void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice)\r
+{\r
+ /* Clear BMHEN, BMDEN of BUSCTL Register */\r
+ i2c->BUSCTL &= ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk);\r
+\r
+ /* Set SMBus Host/Device Mode, and enable Bus Management*/\r
+ if(u8HostDevice == (uint8_t)I2C_SMBH_ENABLE)\r
+ {\r
+ i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk);\r
+ }\r
+ else\r
+ {\r
+ i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable SMBus function\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode.\r
+ *\r
+ */\r
+void I2C_SMBusClose(I2C_T *i2c)\r
+{\r
+\r
+ i2c->BUSCTL = 0x00U;\r
+}\r
+\r
+/**\r
+ * @brief Enable SMBus PEC Transmit Function\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u8PECTxEn CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE)\r
+ *\r
+ * @return None\r
+ *\r
+ * @details When enable CRC check function, the Host or Device needs to transmit CRC byte.\r
+ *\r
+ */\r
+void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn)\r
+{\r
+ i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk;\r
+\r
+ if(u8PECTxEn)\r
+ {\r
+ i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk);\r
+ }\r
+ else\r
+ {\r
+ i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get SMBus CRC value\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ *\r
+ * @return A byte is packet error check value\r
+ *\r
+ * @details The CRC check value after a transmission or a reception by count by using CRC8\r
+ *\r
+ */\r
+uint8_t I2C_SMBusGetPECValue(I2C_T *i2c)\r
+{\r
+ return (uint8_t)i2c->PKTCRC;\r
+}\r
+\r
+/**\r
+ * @brief Calculate Time-out of SMBus idle period\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] u32Us Time-out length(us)\r
+ * @param[in] u32Hclk I2C peripheral clock frequency\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to set SMBus Time-out length when bus is in Idle state.\r
+ *\r
+ */\r
+\r
+void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t u32Us, uint32_t u32Hclk)\r
+{\r
+ uint32_t u32Div, u32HclkKHz;\r
+\r
+ i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk;\r
+ u32HclkKHz = u32Hclk / 1000U;\r
+ u32Div = (((u32Us * u32HclkKHz) / 1000U) >> 2U) - 1U;\r
+ if(u32Div > 255U)\r
+ {\r
+ i2c->BUSTOUT = 0xFFU;\r
+ }\r
+ else\r
+ {\r
+ i2c->BUSTOUT = u32Div;\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Calculate Time-out of SMBus active period\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] ms Time-out length(ms)\r
+ * @param[in] u32Pclk peripheral clock frequency\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to set SMBus Time-out length when bus is in active state.\r
+ * Time-out length is calculate the SCL line "one clock" pull low timing.\r
+ *\r
+ */\r
+\r
+void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)\r
+{\r
+ uint32_t u32Div, u32Pclk_kHz;\r
+\r
+ i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;\r
+\r
+ /* DIV4 disabled */\r
+ i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;\r
+ u32Pclk_kHz = u32Pclk / 1000U;\r
+ u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U;\r
+ if(u32Div <= 0xFFU)\r
+ {\r
+ i2c->BUSTOUT = u32Div;\r
+ }\r
+ else\r
+ {\r
+ /* DIV4 enabled */\r
+ i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;\r
+ i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Calculate Cumulative Clock low Time-out of SMBus active period\r
+ *\r
+ * @param[in] i2c Specify I2C port\r
+ * @param[in] ms Time-out length(ms)\r
+ * @param[in] u32Pclk peripheral clock frequency\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to set SMBus Time-out length when bus is in Active state.\r
+ * Time-out length is calculate the SCL line "clocks" low cumulative timing.\r
+ *\r
+ */\r
+\r
+void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)\r
+{\r
+ uint32_t u32Div, u32Pclk_kHz;\r
+\r
+ i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;\r
+\r
+ /* DIV4 disabled */\r
+ i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;\r
+ u32Pclk_kHz = u32Pclk / 1000U;\r
+ u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U;\r
+ if(u32Div <= 0xFFU)\r
+ {\r
+ i2c->CLKTOUT = u32Div;\r
+ }\r
+ else\r
+ {\r
+ /* DIV4 enabled */\r
+ i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;\r
+ i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Write a byte to Slave\r
+ *\r
+ * @param[in] *i2c Point to I2C peripheral\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u8Data Write a byte data to Slave\r
+ *\r
+ * @retval 0 Write data success\r
+ * @retval 1 Write data fail, or bus occurs error events\r
+ *\r
+ * @details The function is used for I2C Master write a byte data to Slave.\r
+ *\r
+ */\r
+\r
+uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Data)\r
+{\r
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;\r
+\r
+ I2C_START(i2c);\r
+ while(u8Xfering && (u8Err == 0u))\r
+ {\r
+ I2C_WAIT_READY(i2c) {}\r
+ switch(I2C_GET_STATUS(i2c))\r
+ {\r
+ case 0x08u:\r
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x18u: /* Slave Address ACK */\r
+ I2C_SET_DATA(i2c, u8Data); /* Write data to I2CDAT */\r
+ break;\r
+ case 0x20u: /* Slave Address NACK */\r
+ case 0x30u: /* Master transmit data NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x28u:\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Xfering = 0u;\r
+ break;\r
+ case 0x38u: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ }\r
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */\r
+ }\r
+ return (u8Err | u8Xfering); /* return (Success)/(Fail) status */\r
+}\r
+\r
+/**\r
+ * @brief Write multi bytes to Slave\r
+ *\r
+ * @param[in] *i2c Point to I2C peripheral\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] *au8Data Pointer to array to write data to Slave\r
+ * @param[in] u32wLen How many bytes need to write to Slave\r
+ *\r
+ * @return A length of how many bytes have been transmitted.\r
+ *\r
+ * @details The function is used for I2C Master write multi bytes data to Slave.\r
+ *\r
+ */\r
+\r
+uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Data[], uint32_t u32wLen)\r
+{\r
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;\r
+ uint32_t u32txLen = 0u;\r
+\r
+ I2C_START(i2c); /* Send START */\r
+ while(u8Xfering && (u8Err == 0u))\r
+ {\r
+ I2C_WAIT_READY(i2c) {}\r
+ switch(I2C_GET_STATUS(i2c))\r
+ {\r
+ case 0x08u:\r
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x18u: /* Slave Address ACK */\r
+ case 0x28u:\r
+ if(u32txLen < u32wLen)\r
+ {\r
+ I2C_SET_DATA(i2c, au8Data[u32txLen++]); /* Write Data to I2CDAT */\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Xfering = 0u;\r
+ }\r
+ break;\r
+ case 0x20u: /* Slave Address NACK */\r
+ case 0x30u: /* Master transmit data NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x38u: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ }\r
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */\r
+ }\r
+ return u32txLen; /* Return bytes length that have been transmitted */\r
+}\r
+\r
+/**\r
+ * @brief Specify a byte register address and write a byte to Slave\r
+ *\r
+ * @param[in] *i2c Point to I2C peripheral\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u8DataAddr Specify a address (1 byte) of data write to\r
+ * @param[in] u8Data A byte data to write it to Slave\r
+ *\r
+ * @retval 0 Write data success\r
+ * @retval 1 Write data fail, or bus occurs error events\r
+ *\r
+ * @details The function is used for I2C Master specify a address that data write to in Slave.\r
+ *\r
+ */\r
+\r
+uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t u8Data)\r
+{\r
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;\r
+ uint32_t u32txLen = 0u;\r
+\r
+ I2C_START(i2c); /* Send START */\r
+ while(u8Xfering && (u8Err == 0u))\r
+ {\r
+ I2C_WAIT_READY(i2c) {}\r
+ switch(I2C_GET_STATUS(i2c))\r
+ {\r
+ case 0x08u:\r
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Send Slave address with write bit */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x18u: /* Slave Address ACK */\r
+ I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */\r
+ break;\r
+ case 0x20u: /* Slave Address NACK */\r
+ case 0x30u: /* Master transmit data NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x28u:\r
+ if(u32txLen < 1u)\r
+ {\r
+ I2C_SET_DATA(i2c, u8Data);\r
+ u32txLen++;\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Xfering = 0u;\r
+ }\r
+ break;\r
+ case 0x38u: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ }\r
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */\r
+ }\r
+ return (u8Err | u8Xfering); /* return (Success)/(Fail) status */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Specify a byte register address and write multi bytes to Slave\r
+ *\r
+ * @param[in] *i2c Point to I2C peripheral\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u8DataAddr Specify a address (1 byte) of data write to\r
+ * @param[in] *au8Data Pointer to array to write data to Slave\r
+ * @param[in] u32wLen How many bytes need to write to Slave\r
+ *\r
+ * @return A length of how many bytes have been transmitted.\r
+ *\r
+ * @details The function is used for I2C Master specify a byte address that multi data bytes write to in Slave.\r
+ *\r
+ */\r
+\r
+uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Data[], uint32_t u32wLen)\r
+{\r
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;\r
+ uint32_t u32txLen = 0u;\r
+\r
+ I2C_START(i2c); /* Send START */\r
+ while(u8Xfering && (u8Err == 0u))\r
+ {\r
+ I2C_WAIT_READY(i2c) {}\r
+ switch(I2C_GET_STATUS(i2c))\r
+ {\r
+ case 0x08u:\r
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI;\r
+ break;\r
+ case 0x18u: /* Slave Address ACK */\r
+ I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */\r
+ break;\r
+ case 0x20u: /* Slave Address NACK */\r
+ case 0x30u: /* Master transmit data NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x28u:\r
+ if(u32txLen < u32wLen)\r
+ {\r
+ I2C_SET_DATA(i2c, au8Data[u32txLen++]);\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Xfering = 0u;\r
+ }\r
+ break;\r
+ case 0x38u: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ }\r
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */\r
+ }\r
+\r
+ return u32txLen; /* Return bytes length that have been transmitted */\r
+}\r
+\r
+/**\r
+ * @brief Specify two bytes register address and Write a byte to Slave\r
+ *\r
+ * @param[in] *i2c Point to I2C peripheral\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u16DataAddr Specify a address (2 byte) of data write to\r
+ * @param[in] u8Data Write a byte data to Slave\r
+ *\r
+ * @retval 0 Write data success\r
+ * @retval 1 Write data fail, or bus occurs error events\r
+ *\r
+ * @details The function is used for I2C Master specify two bytes address that data write to in Slave.\r
+ *\r
+ */\r
+\r
+uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t u8Data)\r
+{\r
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;\r
+ uint32_t u32txLen = 0u;\r
+\r
+ I2C_START(i2c); /* Send START */\r
+ while(u8Xfering && (u8Err == 0u))\r
+ {\r
+ I2C_WAIT_READY(i2c) {}\r
+ switch(I2C_GET_STATUS(i2c))\r
+ {\r
+ case 0x08u:\r
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x18u: /* Slave Address ACK */\r
+ I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */\r
+ break;\r
+ case 0x20u: /* Slave Address NACK */\r
+ case 0x30u: /* Master transmit data NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x28u:\r
+ if(u8Addr)\r
+ {\r
+ I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */\r
+ u8Addr = 0u;\r
+ }\r
+ else if((u32txLen < 1u) && (u8Addr == 0u))\r
+ {\r
+ I2C_SET_DATA(i2c, u8Data);\r
+ u32txLen++;\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Xfering = 0u;\r
+ }\r
+ break;\r
+ case 0x38u: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ }\r
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */\r
+ }\r
+ return (u8Err | u8Xfering); /* return (Success)/(Fail) status */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Specify two bytes register address and write multi bytes to Slave\r
+ *\r
+ * @param[in] *i2c Point to I2C peripheral\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u16DataAddr Specify a address (2 bytes) of data write to\r
+ * @param[in] au8Data[] A data array for write data to Slave\r
+ * @param[in] u32wLen How many bytes need to write to Slave\r
+ *\r
+ * @return A length of how many bytes have been transmitted.\r
+ *\r
+ * @details The function is used for I2C Master specify a byte address that multi data write to in Slave.\r
+ *\r
+ */\r
+\r
+uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Data[], uint32_t u32wLen)\r
+{\r
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;\r
+ uint32_t u32txLen = 0u;\r
+\r
+ I2C_START(i2c); /* Send START */\r
+ while(u8Xfering && (u8Err == 0u))\r
+ {\r
+ I2C_WAIT_READY(i2c) {}\r
+ switch(I2C_GET_STATUS(i2c))\r
+ {\r
+ case 0x08u:\r
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x18u: /* Slave Address ACK */\r
+ I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */\r
+ break;\r
+ case 0x20u: /* Slave Address NACK */\r
+ case 0x30u: /* Master transmit data NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x28u:\r
+ if(u8Addr)\r
+ {\r
+ I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */\r
+ u8Addr = 0u;\r
+ }\r
+ else if((u32txLen < u32wLen) && (u8Addr == 0u))\r
+ {\r
+ I2C_SET_DATA(i2c, au8Data[u32txLen++]); /* Write data to Register I2CDAT*/\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Xfering = 0u;\r
+ }\r
+ break;\r
+ case 0x38u: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ }\r
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */\r
+ }\r
+ return u32txLen; /* Return bytes length that have been transmitted */\r
+}\r
+\r
+/**\r
+ * @brief Read a byte from Slave\r
+ *\r
+ * @param[in] *i2c Point to I2C peripheral\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ *\r
+ * @return Read a byte data from Slave\r
+ *\r
+ * @details The function is used for I2C Master to read a byte data from Slave.\r
+ *\r
+ */\r
+uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr)\r
+{\r
+ uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u;\r
+\r
+ I2C_START(i2c); /* Send START */\r
+ while(u8Xfering && (u8Err == 0u))\r
+ {\r
+ I2C_WAIT_READY(i2c) {}\r
+ switch(I2C_GET_STATUS(i2c))\r
+ {\r
+ case 0x08u:\r
+ I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x40u: /* Slave Address ACK */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x48u: /* Slave Address NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x58u:\r
+ rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Xfering = 0u;\r
+ break;\r
+ case 0x38u: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ }\r
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */\r
+ }\r
+ if(u8Err)\r
+ {\r
+ rdata = 0u; /* If occurs error, return 0 */\r
+ }\r
+ return rdata; /* Return read data */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Read multi bytes from Slave\r
+ *\r
+ * @param[in] *i2c Point to I2C peripheral\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[out] au8Rdata[] A data array to store data from Slave\r
+ * @param[in] u32rLen How many bytes need to read from Slave\r
+ *\r
+ * @return A length of how many bytes have been received\r
+ *\r
+ * @details The function is used for I2C Master to read multi data bytes from Slave.\r
+ *\r
+ *\r
+ */\r
+uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Rdata[], uint32_t u32rLen)\r
+{\r
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;\r
+ uint32_t u32rxLen = 0u;\r
+\r
+ I2C_START(i2c); /* Send START */\r
+ while(u8Xfering && (u8Err == 0u))\r
+ {\r
+ I2C_WAIT_READY(i2c) {}\r
+ switch(I2C_GET_STATUS(i2c))\r
+ {\r
+ case 0x08u:\r
+ I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x40u: /* Slave Address ACK */\r
+ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */\r
+ break;\r
+ case 0x48u: /* Slave Address NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x50u:\r
+ au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */\r
+ if(u32rxLen < (u32rLen - 1u))\r
+ {\r
+ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ }\r
+ break;\r
+ case 0x58u:\r
+ au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Xfering = 0u;\r
+ break;\r
+ case 0x38u: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ }\r
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */\r
+ }\r
+ return u32rxLen; /* Return bytes length that have been received */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Specify a byte register address and read a byte from Slave\r
+ *\r
+ * @param[in] *i2c Point to I2C peripheral\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u8DataAddr Specify a address(1 byte) of data read from\r
+ *\r
+ * @return Read a byte data from Slave\r
+ *\r
+ * @details The function is used for I2C Master specify a byte address that a data byte read from Slave.\r
+ *\r
+ *\r
+ */\r
+uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)\r
+{\r
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Rdata = 0u, u8Ctrl = 0u;\r
+\r
+ I2C_START(i2c); /* Send START */\r
+ while(u8Xfering && (u8Err == 0u))\r
+ {\r
+ I2C_WAIT_READY(i2c) {}\r
+ switch(I2C_GET_STATUS(i2c))\r
+ {\r
+ case 0x08u:\r
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x18u: /* Slave Address ACK */\r
+ I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */\r
+ break;\r
+ case 0x20u: /* Slave Address NACK */\r
+ case 0x30u: /* Master transmit data NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x28u:\r
+ u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */\r
+ break;\r
+ case 0x10u:\r
+ I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x40u: /* Slave Address ACK */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x48u: /* Slave Address NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x58u:\r
+ u8Rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Xfering = 0u;\r
+ break;\r
+ case 0x38u: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ }\r
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */\r
+ }\r
+ if(u8Err)\r
+ {\r
+ u8Rdata = 0u; /* If occurs error, return 0 */\r
+ }\r
+ return u8Rdata; /* Return read data */\r
+}\r
+\r
+/**\r
+ * @brief Specify a byte register address and read multi bytes from Slave\r
+ *\r
+ * @param[in] *i2c Point to I2C peripheral\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u8DataAddr Specify a address (1 bytes) of data read from\r
+ * @param[out] au8Rdata[] A data array to store data from Slave\r
+ * @param[in] u32rLen How many bytes need to read from Slave\r
+ *\r
+ * @return A length of how many bytes have been received\r
+ *\r
+ * @details The function is used for I2C Master specify a byte address that multi data bytes read from Slave.\r
+ *\r
+ *\r
+ */\r
+uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Rdata[], uint32_t u32rLen)\r
+{\r
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;\r
+ uint32_t u32rxLen = 0u;\r
+\r
+ I2C_START(i2c); /* Send START */\r
+ while(u8Xfering && (u8Err == 0u))\r
+ {\r
+ I2C_WAIT_READY(i2c) {}\r
+ switch(I2C_GET_STATUS(i2c))\r
+ {\r
+ case 0x08u:\r
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x18u: /* Slave Address ACK */\r
+ I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */\r
+ break;\r
+ case 0x20u: /* Slave Address NACK */\r
+ case 0x30u: /* Master transmit data NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x28u:\r
+ u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */\r
+ break;\r
+ case 0x10u:\r
+ I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x40u: /* Slave Address ACK */\r
+ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */\r
+ break;\r
+ case 0x48u: /* Slave Address NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x50u:\r
+ au8Rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */\r
+ if(u32rxLen < (u32rLen - 1u))\r
+ {\r
+ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ }\r
+ break;\r
+ case 0x58u:\r
+ au8Rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Xfering = 0u;\r
+ break;\r
+ case 0x38u: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ }\r
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */\r
+ }\r
+ return u32rxLen; /* Return bytes length that have been received */\r
+}\r
+\r
+/**\r
+ * @brief Specify two bytes register address and read a byte from Slave\r
+ *\r
+ * @param[in] *i2c Point to I2C peripheral\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u16DataAddr Specify an address(2 bytes) of data read from\r
+ *\r
+ * @return Read a byte data from Slave\r
+ *\r
+ * @details The function is used for I2C Master specify two bytes address that a data byte read from Slave.\r
+ *\r
+ *\r
+ */\r
+uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr)\r
+{\r
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Rdata = 0u, u8Addr = 1u, u8Ctrl = 0u;\r
+\r
+ I2C_START(i2c); /* Send START */\r
+ while(u8Xfering && (u8Err == 0u))\r
+ {\r
+ I2C_WAIT_READY(i2c) {}\r
+ switch(I2C_GET_STATUS(i2c))\r
+ {\r
+ case 0x08u:\r
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x18u: /* Slave Address ACK */\r
+ I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */\r
+ break;\r
+ case 0x20u: /* Slave Address NACK */\r
+ case 0x30u: /* Master transmit data NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x28u:\r
+ if(u8Addr)\r
+ {\r
+ I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */\r
+ u8Addr = 0u;\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */\r
+ }\r
+ break;\r
+ case 0x10u:\r
+ I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x40u: /* Slave Address ACK */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x48u: /* Slave Address NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x58u:\r
+ u8Rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Xfering = 0u;\r
+ break;\r
+ case 0x38u: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ }\r
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */\r
+ }\r
+ if(u8Err)\r
+ {\r
+ u8Rdata = 0u; /* If occurs error, return 0 */\r
+ }\r
+ return u8Rdata; /* Return read data */\r
+}\r
+\r
+/**\r
+ * @brief Specify two bytes register address and read multi bytes from Slave\r
+ *\r
+ * @param[in] *i2c Point to I2C peripheral\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u16DataAddr Specify a address (2 bytes) of data read from\r
+ * @param[out] au8Rdata[] A data array to store data from Slave\r
+ * @param[in] u32rLen How many bytes need to read from Slave\r
+ *\r
+ * @return A length of how many bytes have been received\r
+ *\r
+ * @details The function is used for I2C Master specify two bytes address that multi data bytes read from Slave.\r
+ *\r
+ *\r
+ */\r
+uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Rdata[], uint32_t u32rLen)\r
+{\r
+ uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;\r
+ uint32_t u32rxLen = 0u;\r
+\r
+ I2C_START(i2c); /* Send START */\r
+ while(u8Xfering && (u8Err == 0u))\r
+ {\r
+ I2C_WAIT_READY(i2c) {}\r
+ switch(I2C_GET_STATUS(i2c))\r
+ {\r
+ case 0x08u:\r
+ I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x18u: /* Slave Address ACK */\r
+ I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */\r
+ break;\r
+ case 0x20u: /* Slave Address NACK */\r
+ case 0x30u: /* Master transmit data NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x28u:\r
+ if(u8Addr)\r
+ {\r
+ I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */\r
+ u8Addr = 0u;\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */\r
+ }\r
+ break;\r
+ case 0x10u:\r
+ I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ break;\r
+ case 0x40u: /* Slave Address ACK */\r
+ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */\r
+ break;\r
+ case 0x48u: /* Slave Address NACK */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ case 0x50u:\r
+ au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */\r
+ if(u32rxLen < (u32rLen - 1u))\r
+ {\r
+ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = I2C_CTL_SI; /* Clear SI */\r
+ }\r
+ break;\r
+ case 0x58u:\r
+ au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Xfering = 0u;\r
+ break;\r
+ case 0x38u: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */\r
+ u8Err = 1u;\r
+ break;\r
+ }\r
+ I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */\r
+ }\r
+ return u32rxLen; /* Return bytes length that have been received */\r
+}\r
+\r
+/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group I2C_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file i2s.c\r
+ * @version V3.00\r
+ * @brief M2351 series I2S driver source file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+\r
+#include <stdio.h>\r
+#include "NuMicro.h"\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup I2S_Driver I2S Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions\r
+ @{\r
+*/\r
+\r
+static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s);\r
+\r
+/**\r
+ * @brief This function is used to get I2S source clock frequency.\r
+ * @param[in] i2s The base address of I2S module.\r
+ * @return I2S source clock frequency (Hz).\r
+ * @details Return the source clock frequency according to the setting of I2S0_SEL (CLK_CLKSEL3[17:16]).\r
+ */\r
+static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s)\r
+{\r
+ uint32_t u32Freq, u32ClkSrcSel;\r
+\r
+ u32ClkSrcSel = CLK_GetModuleClockSource(I2S0_MODULE) << CLK_CLKSEL3_I2S0SEL_Pos;\r
+\r
+ switch(u32ClkSrcSel)\r
+ {\r
+ case CLK_CLKSEL3_I2S0SEL_HXT:\r
+ u32Freq = __HXT;\r
+ break;\r
+\r
+ case CLK_CLKSEL3_I2S0SEL_PLL:\r
+ u32Freq = CLK_GetPLLClockFreq();\r
+ break;\r
+\r
+ case CLK_CLKSEL3_I2S0SEL_HIRC:\r
+ u32Freq = __HIRC;\r
+ break;\r
+\r
+ case CLK_CLKSEL3_I2S0SEL_PCLK0:\r
+ u32Freq = CLK_GetPCLK0Freq();\r
+ break;\r
+\r
+ default:\r
+ u32Freq = __HXT;\r
+ break;\r
+ }\r
+\r
+ return u32Freq;\r
+}\r
+\r
+/**\r
+ * @brief This function configures some parameters of I2S interface for general purpose use.\r
+ * @param[in] i2s The base address of I2S module.\r
+ * @param[in] u32MasterSlave I2S operation mode. Valid values are:\r
+ * - \ref I2S_MODE_MASTER\r
+ * - \ref I2S_MODE_SLAVE\r
+ * @param[in] u32SampleRate Sample rate\r
+ * @param[in] u32WordWidth Data length. Valid values are:\r
+ * - \ref I2S_DATABIT_8\r
+ * - \ref I2S_DATABIT_16\r
+ * - \ref I2S_DATABIT_24\r
+ * - \ref I2S_DATABIT_32\r
+ * @param[in] u32MonoData: Set audio data to mono or not. Valid values are:\r
+ * - \ref I2S_ENABLE_MONO\r
+ * - \ref I2S_DISABLE_MONO\r
+ * @param[in] u32DataFormat Data format. This is also used to select I2S or PCM(TDM) function. Valid values are:\r
+ * - \ref I2S_FORMAT_I2S\r
+ * - \ref I2S_FORMAT_I2S_MSB\r
+ * - \ref I2S_FORMAT_I2S_LSB\r
+ * - \ref I2S_FORMAT_PCM\r
+ * - \ref I2S_FORMAT_PCM_MSB\r
+ * - \ref I2S_FORMAT_PCM_LSB\r
+ * @return Real sample rate.\r
+ * @details Set TX and RX FIFO threshold to middle value.\r
+ * The sample rate may not be used from the parameter, it depends on system's clock settings,\r
+ * but real sample rate used by system will be returned for reference.\r
+ * @note I2S will be reset in initialization only for Secure.\r
+ */\r
+uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat)\r
+{\r
+ uint16_t u16Divider;\r
+ uint32_t u32BitRate, u32SrcClk;\r
+\r
+ if(!(__PC() & (1UL << 28UL)))\r
+ {\r
+ /* Reset I2S */\r
+ SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk;\r
+ SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk;\r
+ }\r
+\r
+ /* Configure I2S controller according to input parameters. */\r
+ i2s->CTL0 = u32MasterSlave | u32WordWidth | u32MonoData | u32DataFormat | I2S_FIFO_TX_LEVEL_WORD_8 | I2S_FIFO_RX_LEVEL_WORD_8;\r
+\r
+ /* Get I2S source clock frequency */\r
+ u32SrcClk = I2S_GetSourceClockFreq(i2s);\r
+\r
+ /* Calculate bit clock rate */\r
+ u32BitRate = u32SampleRate * (((u32WordWidth >> 4UL) & 0x3UL) + 1UL) * 16UL;\r
+ u16Divider = (uint16_t)((((((u32SrcClk * 10UL) / u32BitRate) >> 1UL) + 5UL) / 10UL) - 1UL); /* Round to the nearest integer */\r
+ i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | ((uint32_t)u16Divider << 8UL);\r
+\r
+ /* Calculate real sample rate */\r
+ u32BitRate = u32SrcClk / (((uint32_t)u16Divider + 1UL) * 2UL);\r
+ u32SampleRate = u32BitRate / ((((u32WordWidth >> 4UL) & 0x3UL) + 1UL) * 16UL);\r
+\r
+ /* Enable I2S controller */\r
+ i2s->CTL0 |= I2S_CTL0_I2SEN_Msk;\r
+\r
+ return u32SampleRate;\r
+}\r
+\r
+/**\r
+ * @brief Disable I2S function.\r
+ * @param[in] i2s The base address of I2S module.\r
+ * @return None\r
+ * @details Clear I2SEN (I2S_CTL0[0]) to disable I2S function.\r
+ */\r
+void I2S_Close(I2S_T *i2s)\r
+{\r
+ i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable interrupt function.\r
+ * @param[in] i2s The base address of I2S module.\r
+ * @param[in] u32Mask The combination of all related interrupt enable bits.\r
+ * Each bit corresponds to a interrupt bit.\r
+ * @return None\r
+ * @details This function enables the interrupt according to the mask parameter.\r
+ */\r
+void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask)\r
+{\r
+ i2s->IEN |= u32Mask;\r
+}\r
+\r
+/**\r
+ * @brief Disable interrupt function.\r
+ * @param[in] i2s The base address of I2S module.\r
+ * @param[in] u32Mask The combination of all related interrupt enable bits.\r
+ * Each bit corresponds to a interrupt bit.\r
+ * @return None\r
+ * @details This function disables the interrupt according to the mask parameter.\r
+ */\r
+void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask)\r
+{\r
+ i2s->IEN &= ~u32Mask;\r
+}\r
+\r
+/**\r
+ * @brief Enable master clock (MCLK).\r
+ * @param[in] i2s The base address of I2S module.\r
+ * @param[in] u32BusClock The target MCLK clock.\r
+ * @return Actual MCLK clock\r
+ * @details Set the master clock rate according to u32BusClock parameter and enable master clock output.\r
+ * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference.\r
+ */\r
+uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock)\r
+{\r
+ uint8_t u8Divider;\r
+ uint32_t u32SrcClk, u32Reg, u32Clock;\r
+\r
+ u32SrcClk = I2S_GetSourceClockFreq(i2s);\r
+ if(u32BusClock == u32SrcClk)\r
+ {\r
+ u8Divider = (uint8_t)0UL;\r
+ }\r
+ else\r
+ {\r
+ u8Divider = (uint8_t)(u32SrcClk / u32BusClock) >> 1UL;\r
+ }\r
+\r
+ i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider;\r
+\r
+ i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk;\r
+\r
+ u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk;\r
+\r
+ if(u32Reg == 0UL)\r
+ {\r
+ u32Clock = u32SrcClk;\r
+ }\r
+ else\r
+ {\r
+ u32Clock = ((u32SrcClk >> 1UL) / u32Reg);\r
+ }\r
+\r
+ return u32Clock;\r
+}\r
+\r
+/**\r
+ * @brief Disable master clock (MCLK).\r
+ * @param[in] i2s The base address of I2S module.\r
+ * @return None\r
+ * @details Disable master clock output.\r
+ */\r
+void I2S_DisableMCLK(I2S_T *i2s)\r
+{\r
+ i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Configure FIFO threshold setting.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 15.\r
+ * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 15.\r
+ * @return None\r
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.\r
+ */\r
+void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)\r
+{\r
+ i2s->CTL1 = (i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) |\r
+ (u32TxThreshold << I2S_CTL1_TXTH_Pos) |\r
+ (u32RxThreshold << I2S_CTL1_RXTH_Pos);\r
+}\r
+\r
+/**\r
+ * @brief Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32ChannelWidth Channel width. Valid values are:\r
+ * - \ref I2S_TDM_WIDTH_8BIT\r
+ * - \ref I2S_TDM_WIDTH_16BIT\r
+ * - \ref I2S_TDM_WIDTH_24BIT\r
+ * - \ref I2S_TDM_WIDTH_32BIT\r
+ * @param[in] u32ChannelNum Channel number. Valid values are:\r
+ * - \ref I2S_TDM_2CH\r
+ * - \ref I2S_TDM_4CH\r
+ * - \ref I2S_TDM_6CH\r
+ * - \ref I2S_TDM_8CH\r
+ * @param[in] u32SyncWidth Width for sync pulse. Valid values are:\r
+ * - \ref I2S_TDM_SYNC_ONE_BCLK\r
+ * - \ref I2S_TDM_SYNC_ONE_CHANNEL\r
+ * @return None\r
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.\r
+ */\r
+void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth)\r
+{\r
+ i2s->CTL0 = (i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) |\r
+ (u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) |\r
+ (u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) |\r
+ (u32SyncWidth << I2S_CTL0_PCMSYNC_Pos);\r
+}\r
+\r
+/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group I2S_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file pdma.c\r
+ * @version V3.00\r
+ * @brief M2351 series PDMA driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+\r
+static uint8_t au8ChSelect[PDMA_CH_MAX];\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup PDMA_Driver PDMA Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief PDMA Open\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Mask Channel enable bits.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function enable the PDMA channels.\r
+ */\r
+void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask)\r
+{\r
+ uint32_t i;\r
+\r
+ for(i = 0UL; i < (int)PDMA_CH_MAX; i++)\r
+ {\r
+ if((1 << i) & u32Mask)\r
+ {\r
+ (pdma)->DSCT[i].CTL = 0UL;\r
+ au8ChSelect[i] = (uint8_t)PDMA_MEM;\r
+ }\r
+ }\r
+\r
+ (pdma)->CHCTL |= u32Mask;\r
+}\r
+\r
+/**\r
+ * @brief PDMA Close\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function disable all PDMA channels.\r
+ */\r
+void PDMA_Close(PDMA_T *pdma)\r
+{\r
+ (pdma)->CHCTL = 0UL;\r
+}\r
+\r
+/**\r
+ * @brief Set PDMA Transfer Count\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ * @param[in] u32Width Data width. Valid values are\r
+ * - \ref PDMA_WIDTH_8\r
+ * - \ref PDMA_WIDTH_16\r
+ * - \ref PDMA_WIDTH_32\r
+ * @param[in] u32TransCount Transfer count\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function set the selected channel data width and transfer count.\r
+ */\r
+void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)\r
+{\r
+ (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);\r
+ (pdma)->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos));\r
+}\r
+\r
+/**\r
+ * @brief Set PDMA Stride Mode\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ * @param[in] u32DestLen Destination stride count\r
+ * @param[in] u32SrcLen Source stride count\r
+ * @param[in] u32TransCount Transfer count\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function set the selected stride mode.\r
+ */\r
+void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount)\r
+{\r
+ (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk;\r
+ (pdma)->STRIDE[u32Ch].ASOCR = (u32DestLen << 16) | u32SrcLen;\r
+ (pdma)->STRIDE[u32Ch].STCR = u32TransCount;\r
+}\r
+\r
+/**\r
+ * @brief Set PDMA Transfer Address\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ * @param[in] u32SrcAddr Source address\r
+ * @param[in] u32SrcCtrl Source control attribute. Valid values are\r
+ * - \ref PDMA_SAR_INC\r
+ * - \ref PDMA_SAR_FIX\r
+ * @param[in] u32DstAddr destination address\r
+ * @param[in] u32DstCtrl destination control attribute. Valid values are\r
+ * - \ref PDMA_DAR_INC\r
+ * - \ref PDMA_DAR_FIX\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function set the selected channel source/destination address and attribute.\r
+ */\r
+void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)\r
+{\r
+ (pdma)->DSCT[u32Ch].SA = u32SrcAddr;\r
+ (pdma)->DSCT[u32Ch].DA = u32DstAddr;\r
+ (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);\r
+ (pdma)->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);\r
+}\r
+\r
+/**\r
+ * @brief Set PDMA Transfer Mode\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ * @param[in] u32Peripheral The selected peripheral. Valid values are\r
+ * - \ref PDMA_MEM\r
+ * - \ref PDMA_USB_TX\r
+ * - \ref PDMA_USB_RX\r
+ * - \ref PDMA_UART0_TX\r
+ * - \ref PDMA_UART0_RX\r
+ * - \ref PDMA_UART1_TX\r
+ * - \ref PDMA_UART1_RX\r
+ * - \ref PDMA_UART2_TX\r
+ * - \ref PDMA_UART2_RX\r
+ * - \ref PDMA_UART3_TX\r
+ * - \ref PDMA_UART3_RX\r
+ * - \ref PDMA_UART4_TX\r
+ * - \ref PDMA_UART4_RX\r
+ * - \ref PDMA_UART5_TX\r
+ * - \ref PDMA_UART5_RX\r
+ * - \ref PDMA_USCI0_TX\r
+ * - \ref PDMA_USCI0_RX\r
+ * - \ref PDMA_USCI1_TX\r
+ * - \ref PDMA_USCI1_RX\r
+ * - \ref PDMA_QSPI0_TX\r
+ * - \ref PDMA_QSPI0_RX\r
+ * - \ref PDMA_SPI0_TX\r
+ * - \ref PDMA_SPI0_RX\r
+ * - \ref PDMA_SPI1_TX\r
+ * - \ref PDMA_SPI1_RX\r
+ * - \ref PDMA_SPI2_TX\r
+ * - \ref PDMA_SPI2_RX\r
+ * - \ref PDMA_SPI3_TX\r
+ * - \ref PDMA_SPI3_RX\r
+ * - \ref PDMA_EPWM0_P1_RX\r
+ * - \ref PDMA_EPWM0_P2_RX\r
+ * - \ref PDMA_EPWM0_P3_RX\r
+ * - \ref PDMA_EPWM1_P1_RX\r
+ * - \ref PDMA_EPWM1_P2_RX\r
+ * - \ref PDMA_EPWM1_P3_RX\r
+ * - \ref PDMA_I2C0_TX\r
+ * - \ref PDMA_I2C0_RX\r
+ * - \ref PDMA_I2C1_TX\r
+ * - \ref PDMA_I2C1_RX\r
+ * - \ref PDMA_I2C2_TX\r
+ * - \ref PDMA_I2C2_RX\r
+ * - \ref PDMA_I2S0_TX\r
+ * - \ref PDMA_I2S0_RX\r
+ * - \ref PDMA_TMR0\r
+ * - \ref PDMA_TMR1\r
+ * - \ref PDMA_TMR2\r
+ * - \ref PDMA_TMR3\r
+ * - \ref PDMA_ADC_RX\r
+ * - \ref PDMA_DAC0_TX\r
+ * - \ref PDMA_DAC1_TX\r
+ * @param[in] u32ScatterEn Scatter-gather mode enable\r
+ * @param[in] u32DescAddr Scatter-gather descriptor address\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function set the selected channel transfer mode. Include peripheral setting.\r
+ */\r
+void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)\r
+{\r
+ au8ChSelect[u32Ch] = (uint8_t)u32Peripheral;\r
+ switch(u32Ch)\r
+ {\r
+ case 0UL:\r
+ (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;\r
+ break;\r
+ case 1UL:\r
+ (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);\r
+ break;\r
+ case 2UL:\r
+ (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);\r
+ break;\r
+ case 3UL:\r
+ (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);\r
+ break;\r
+ case 4UL:\r
+ (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;\r
+ break;\r
+ case 5UL:\r
+ (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);\r
+ break;\r
+ case 6UL:\r
+ (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);\r
+ break;\r
+ case 7UL:\r
+ (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if(u32ScatterEn)\r
+ {\r
+ (pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;\r
+ (pdma)->DSCT[u32Ch].NEXT = u32DescAddr - ((pdma)->SCATBA);\r
+ }\r
+ else\r
+ {\r
+ (pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set PDMA Burst Type and Size\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ * @param[in] u32BurstType Burst mode or single mode. Valid values are\r
+ * - \ref PDMA_REQ_SINGLE\r
+ * - \ref PDMA_REQ_BURST\r
+ * @param[in] u32BurstSize Set the size of burst mode. Valid values are\r
+ * - \ref PDMA_BURST_128\r
+ * - \ref PDMA_BURST_64\r
+ * - \ref PDMA_BURST_32\r
+ * - \ref PDMA_BURST_16\r
+ * - \ref PDMA_BURST_8\r
+ * - \ref PDMA_BURST_4\r
+ * - \ref PDMA_BURST_2\r
+ * - \ref PDMA_BURST_1\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function set the selected channel burst type and size.\r
+ */\r
+void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)\r
+{\r
+ (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);\r
+ (pdma)->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);\r
+}\r
+\r
+/**\r
+ * @brief Enable timeout function\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Mask Channel enable bits.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function enable timeout function of the selected channel(s).\r
+ * @note This function is only supported in channel 0 and channel 1.\r
+ */\r
+void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask)\r
+{\r
+ (pdma)->TOUTEN |= u32Mask;\r
+}\r
+\r
+/**\r
+ * @brief Disable timeout function\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Mask Channel enable bits.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function disable timeout function of the selected channel(s).\r
+ * @note This function is only supported in channel 0 and channel 1.\r
+ */\r
+void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask)\r
+{\r
+ (pdma)->TOUTEN &= ~u32Mask;\r
+}\r
+\r
+/**\r
+ * @brief Set PDMA Timeout Count\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ * @param[in] u32OnOff Enable/disable timeout function\r
+ * @param[in] u32TimeOutCnt Timeout count\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function set the timeout count.\r
+ * @note This function is only supported in channel 0 and channel 1.\r
+ */\r
+void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)\r
+{\r
+ switch(u32Ch)\r
+ {\r
+ case 0UL:\r
+ (pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;\r
+ break;\r
+ case 1UL:\r
+ (pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ if(u32OnOff)\r
+ {\r
+ (pdma)->TOUTEN |= (1UL << u32Ch);\r
+ }\r
+ else\r
+ {\r
+ (pdma)->TOUTEN &= ~(1UL << u32Ch);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Trigger PDMA\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function trigger the selected channel.\r
+ */\r
+void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch)\r
+{\r
+ if(au8ChSelect[u32Ch] == PDMA_MEM)\r
+ {\r
+ (pdma)->SWREQ = (1UL << u32Ch);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable Interrupt\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ * @param[in] u32Mask The Interrupt Type. Valid values are\r
+ * - \ref PDMA_INT_TRANS_DONE\r
+ * - \ref PDMA_INT_TABLE\r
+ * - \ref PDMA_INT_TIMEOUT\r
+ * - \ref PDMA_INT_ALIGN\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function enable the selected channel interrupt.\r
+ * @note PDMA_INT_TIMEOUT is only supported in channel 0 and channel 1.\r
+ */\r
+void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)\r
+{\r
+ switch(u32Mask)\r
+ {\r
+ case PDMA_INT_TRANS_DONE:\r
+ case PDMA_INT_ALIGN:\r
+ (pdma)->INTEN |= (1UL << u32Ch);\r
+ break;\r
+ case PDMA_INT_TABLE:\r
+ (pdma)->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;\r
+ break;\r
+ case PDMA_INT_TIMEOUT:\r
+ (pdma)->TOUTIEN |= (1UL << u32Ch);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable Interrupt\r
+ *\r
+ * @param[in] pdma The pointer of the specified PDMA module\r
+ * @param[in] u32Ch The selected channel\r
+ * @param[in] u32Mask The Interrupt Type. Valid values are\r
+ * - \ref PDMA_INT_TRANS_DONE\r
+ * - \ref PDMA_INT_TABLE\r
+ * - \ref PDMA_INT_TIMEOUT\r
+ * - \ref PDMA_INT_ALIGN\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function disable the selected channel interrupt.\r
+ * @note PDMA_INT_TIMEOUT is only supported in channel 0 and channel 1.\r
+ * @note The transfer done interrupt is disabled when table empty interrupt is disabled(PDMA_INT_TEMPTY).\r
+ */\r
+void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)\r
+{\r
+ switch(u32Mask)\r
+ {\r
+ case PDMA_INT_TRANS_DONE:\r
+ case PDMA_INT_ALIGN:\r
+ (pdma)->INTEN &= ~(1UL << u32Ch);\r
+ break;\r
+ case PDMA_INT_TABLE:\r
+ (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;\r
+ break;\r
+ case PDMA_INT_TIMEOUT:\r
+ (pdma)->TOUTIEN &= ~(1UL << u32Ch);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group PDMA_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file qei.c\r
+ * @version V3.00\r
+ * $Revision: 2 $\r
+ * $Date: 17/09/20 9:33a $\r
+ * @brief Quadrature Encoder Interface (QEI) driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "M2351.h"\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup QEI_Driver QEI Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Close QEI function\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return None\r
+ * @details This function reset QEI configuration and stop QEI counting.\r
+ */\r
+void QEI_Close(QEI_T* qei)\r
+{\r
+ /* Reset QEI configuration */\r
+ qei->CTL = 0UL;\r
+}\r
+\r
+/**\r
+ * @brief Disable QEI interrupt\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32IntSel Interrupt type selection.\r
+ * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt\r
+ * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt\r
+ * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt\r
+ * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt\r
+ * @return None\r
+ * @details This function disable QEI specified interrupt.\r
+ */\r
+void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel)\r
+{\r
+ /* Disable QEI specified interrupt */\r
+ QEI_DISABLE_INT(qei, u32IntSel);\r
+\r
+ /* Disable NVIC QEI IRQ */\r
+ if((qei == QEI0) || (qei == QEI0_NS))\r
+ {\r
+ NVIC_DisableIRQ(QEI0_IRQn);\r
+ }\r
+ else\r
+ {\r
+ NVIC_DisableIRQ(QEI1_IRQn);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable QEI interrupt\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32IntSel Interrupt type selection.\r
+ * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt\r
+ * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt\r
+ * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt\r
+ * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt\r
+ * @return None\r
+ * @details This function enable QEI specified interrupt.\r
+ */\r
+void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel)\r
+{\r
+ /* Enable QEI specified interrupt */\r
+ QEI_ENABLE_INT(qei, u32IntSel);\r
+\r
+ /* Enable NVIC QEI IRQ */\r
+ if((qei == QEI0) || (qei == QEI0_NS))\r
+ {\r
+ NVIC_EnableIRQ(QEI0_IRQn);\r
+ }\r
+ else\r
+ {\r
+ NVIC_EnableIRQ(QEI1_IRQn);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Open QEI in specified mode and enable input\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @param[in] u32Mode QEI counting mode.\r
+ * - \ref QEI_CTL_X4_FREE_COUNTING_MODE\r
+ * - \ref QEI_CTL_X2_FREE_COUNTING_MODE\r
+ * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE\r
+ * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE\r
+ * @param[in] u32Value The counter maximum value in compare-counting mode.\r
+ * @return None\r
+ * @details This function set QEI in specified mode and enable input.\r
+ */\r
+void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value)\r
+{\r
+ /* Set QEI function configuration */\r
+ /* Set QEI counting mode */\r
+ /* Enable IDX, QEA and QEB input to QEI controller */\r
+ qei->CTL = (qei->CTL & (~QEI_CTL_MODE_Msk)) | ((u32Mode) | QEI_CTL_CHAEN_Msk | QEI_CTL_CHBEN_Msk | QEI_CTL_IDXEN_Msk);\r
+\r
+ /* Set QEI maximum count value in in compare-counting mode */\r
+ qei->CNTMAX = u32Value;\r
+}\r
+\r
+/**\r
+ * @brief Start QEI function\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return None\r
+ * @details This function enable QEI function and start QEI counting.\r
+ */\r
+void QEI_Start(QEI_T* qei)\r
+{\r
+ /* Enable QEI controller function */\r
+ qei->CTL |= QEI_CTL_QEIEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Stop QEI function\r
+ * @param[in] qei The pointer of the specified QEI module.\r
+ * @return None\r
+ * @details This function disable QEI function and stop QEI counting.\r
+ */\r
+void QEI_Stop(QEI_T* qei)\r
+{\r
+ /* Disable QEI controller function */\r
+ qei->CTL &= (~QEI_CTL_QEIEN_Msk);\r
+}\r
+\r
+\r
+/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group QEI_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**
+ * @file qspi.c
+ * @version V3.00
+ * @brief M2351 series QSPI driver source file
+ *
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup QSPI_Driver QSPI Driver
+ @{
+*/
+
+
+/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make QSPI module be ready to transfer.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER)
+ * @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3)
+ * @param[in] u32DataWidth Decides the data width of a QSPI transaction.
+ * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz.
+ * @return Actual frequency of QSPI peripheral clock.
+ * @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
+ * slave selection function is disabled.
+ * In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0.
+ * The actual clock rate may be different from the target QSPI clock rate.
+ * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the
+ * actual QSPI clock rate will be 6MHz.
+ * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+ * @note If u32BusClock >= system clock frequency for Secure, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+ * @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of
+ * QSPI bus clock cannot be faster than the system clock rate. User should set up carefully.
+ * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0.
+ * @note In slave mode for Secure, the QSPI peripheral clock rate will equal to APB clock rate.
+ * @note In slave mode for Non-Secure, the QSPI peripheral clock rate will equal to the clock rate set in secure mode.
+ */
+uint32_t QSPI_Open(QSPI_T *qspi,
+ uint32_t u32MasterSlave,
+ uint32_t u32QSPIMode,
+ uint32_t u32DataWidth,
+ uint32_t u32BusClock)
+{
+ uint32_t u32ClkSrc = 0UL, u32Div, u32HCLKFreq, u32PCLK0Freq, u32RetValue = 0UL;
+
+ if(u32DataWidth == 32UL)
+ {
+ u32DataWidth = 0UL;
+ }
+
+ /* Get system clock frequency */
+ u32HCLKFreq = CLK_GetHCLKFreq();
+ /* Get APB0 clock frequency */
+ u32PCLK0Freq = CLK_GetPCLK0Freq();
+
+ if(u32MasterSlave == QSPI_MASTER)
+ {
+ /* Default setting: slave selection signal is active low; disable automatic slave selection function. */
+ qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
+
+ /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+ qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk;
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ if(!(__PC() & (1UL << 28UL)))
+ {
+ /* Select PCLK as the clock source of QSPI */
+ if((qspi == QSPI0) || (qspi == QSPI0_NS))
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
+ }
+ }
+ }
+
+ /* Check clock source of QSPI */
+ if((qspi == QSPI0) || (qspi == QSPI0_NS))
+ {
+ if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+ {
+ u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Set DIVIDER = 0 */
+ qspi->CLKDIV = 0UL;
+ /* Return master peripheral clock rate */
+ u32RetValue = u32ClkSrc;
+ }
+ else if(u32BusClock >= u32ClkSrc)
+ {
+ /* Set DIVIDER = 0 */
+ qspi->CLKDIV = 0UL;
+ /* Return master peripheral clock rate */
+ u32RetValue = u32ClkSrc;
+ }
+ else if(u32BusClock == 0UL)
+ {
+ /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+ qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
+ }
+ else
+ {
+ u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */
+ if(u32Div > 0x1FFUL)
+ {
+ u32Div = 0x1FFUL;
+ qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
+ }
+ else
+ {
+ qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (u32Div + 1UL));
+ }
+ }
+ }
+ else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */
+ {
+ /* Default setting: slave selection signal is low level active. */
+ qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
+
+ /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+ qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk;
+
+ /* Set DIVIDER = 0 */
+ qspi->CLKDIV = 0UL;
+
+ if(!(__PC() & (1UL << 28UL)))
+ {
+ /* Select PCLK as the clock source of QSPI */
+ if((qspi == QSPI0) || (qspi == QSPI0_NS))
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
+ /* Return slave peripheral clock rate */
+ u32RetValue = u32PCLK0Freq;
+ }
+ }
+ else
+ {
+ /* Check clock source of QSPI */
+ if((qspi == QSPI0) || (qspi == QSPI0_NS))
+ {
+ if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT)
+ {
+ u32RetValue = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL)
+ {
+ u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+ {
+ u32RetValue = u32PCLK0Freq; /* Clock source is PCLK0 */
+ }
+ else
+ {
+ u32RetValue = __HIRC; /* Clock source is HIRC */
+ }
+ }
+ }
+ }
+
+ return u32RetValue;
+}
+
+/**
+ * @brief Disable QSPI controller.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None
+ * @details Clear SPIEN bit of QSPI_CTL register to disable QSPI transfer control.
+ */
+void QSPI_Close(QSPI_T *qspi)
+{
+ qspi->CTL &= ~QSPI_CTL_SPIEN_Msk;
+}
+
+/**
+ * @brief Clear RX FIFO buffer.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None
+ * @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1.
+ */
+void QSPI_ClearRxFIFO(QSPI_T *qspi)
+{
+ qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk;
+}
+
+/**
+ * @brief Clear TX FIFO buffer.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None
+ * @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1.
+ * @note The TX shift register will not be cleared.
+ */
+void QSPI_ClearTxFIFO(QSPI_T *qspi)
+{
+ qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk;
+}
+
+/**
+ * @brief Disable the automatic slave selection function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return None
+ * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
+ */
+void QSPI_DisableAutoSS(QSPI_T *qspi)
+{
+ qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk);
+}
+
+/**
+ * @brief Enable the automatic slave selection function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS)
+ * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW)
+ * @return None
+ * @details This function will enable the automatic slave selection function. Only available in Master mode.
+ * The slave selection pin and the active level will be set in this function.
+ */
+void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+ qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk);
+}
+
+/**
+ * @brief Set the QSPI bus clock.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz.
+ * @return Actual frequency of QSPI bus clock.
+ * @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate.
+ * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock
+ * rate will be 6 MHz.
+ * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+ * @note If u32BusClock >= system clock frequency for Secure, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+ * @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of
+ * QSPI bus clock cannot be faster than the system clock rate. User should set up carefully.
+ * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0.
+ */
+uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
+{
+ uint32_t u32ClkSrc, u32HCLKFreq;
+ uint32_t u32Div, u32RetValue;
+
+ /* Get system clock frequency */
+ u32HCLKFreq = CLK_GetHCLKFreq();
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ if(!(__PC() & (1UL << 28UL)))
+ {
+ /* Select PCLK as the clock source of QSPI */
+ if((qspi == QSPI0) || (qspi == QSPI0_NS))
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
+ }
+ }
+ }
+
+ /* Check clock source of QSPI */
+ if((qspi == QSPI0) || (qspi == QSPI0_NS))
+ {
+ if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+ {
+ u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Set DIVIDER = 0 */
+ qspi->CLKDIV = 0UL;
+ /* Return master peripheral clock rate */
+ u32RetValue = u32ClkSrc;
+ }
+ else if(u32BusClock >= u32ClkSrc)
+ {
+ /* Set DIVIDER = 0 */
+ qspi->CLKDIV = 0UL;
+ /* Return master peripheral clock rate */
+ u32RetValue = u32ClkSrc;
+ }
+ else if(u32BusClock == 0UL)
+ {
+ /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+ qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
+ }
+ else
+ {
+ u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */
+ if(u32Div > 0x1FFUL)
+ {
+ u32Div = 0x1FFUL;
+ qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
+ }
+ else
+ {
+ qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ u32RetValue = (u32ClkSrc / (u32Div + 1UL));
+ }
+ }
+
+ return u32RetValue;
+}
+
+/**
+ * @brief Configure FIFO threshold setting.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7.
+ * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7.
+ * @return None
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+ */
+void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+ qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) |
+ (u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) |
+ (u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos);
+}
+
+/**
+ * @brief Get the actual frequency of QSPI bus clock. Only available in Master mode.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @return Actual QSPI bus clock frequency in Hz.
+ * @details This function will calculate the actual QSPI bus clock rate according to the QQSPISEL/QSPIxSEL and DIVIDER settings. Only available in Master mode.
+ */
+uint32_t QSPI_GetBusClock(QSPI_T *qspi)
+{
+ uint32_t u32Div;
+ uint32_t u32ClkSrc;
+
+ /* Get DIVIDER setting */
+ u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos;
+
+ /* Check clock source of QSPI */
+ if((qspi == QSPI0) || (qspi == QSPI0_NS))
+ {
+ if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT)
+ {
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ }
+ else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL)
+ {
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ }
+ else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+ {
+ u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+ }
+ else
+ {
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ }
+
+ /* Return QSPI bus clock rate */
+ return (u32ClkSrc / (u32Div + 1UL));
+}
+
+/**
+ * @brief Enable interrupt function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt enable bit.
+ * This parameter decides which interrupts will be enabled. It is combination of:
+ * - \ref QSPI_UNIT_INT_MASK
+ * - \ref QSPI_SSACT_INT_MASK
+ * - \ref QSPI_SSINACT_INT_MASK
+ * - \ref QSPI_SLVUR_INT_MASK
+ * - \ref QSPI_SLVBE_INT_MASK
+ * - \ref QSPI_SLVTO_INT_MASK
+ * - \ref QSPI_TXUF_INT_MASK
+ * - \ref QSPI_FIFO_TXTH_INT_MASK
+ * - \ref QSPI_FIFO_RXTH_INT_MASK
+ * - \ref QSPI_FIFO_RXOV_INT_MASK
+ * - \ref QSPI_FIFO_RXTO_INT_MASK
+ *
+ * @return None
+ * @details Enable QSPI related interrupts specified by u32Mask parameter.
+ */
+void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask)
+{
+ /* Enable unit transfer interrupt flag */
+ if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
+ {
+ qspi->CTL |= QSPI_CTL_UNITIEN_Msk;
+ }
+
+ /* Enable slave selection signal active interrupt flag */
+ if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
+ {
+ qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk;
+ }
+
+ /* Enable slave selection signal inactive interrupt flag */
+ if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
+ {
+ qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk;
+ }
+
+ /* Enable slave TX under run interrupt flag */
+ if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
+ {
+ qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk;
+ }
+
+ /* Enable slave bit count error interrupt flag */
+ if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
+ {
+ qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk;
+ }
+
+ /* Enable slave mode time-out interrupt flag */
+ if((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK)
+ {
+ qspi->SSCTL |= QSPI_SSCTL_SLVTOIEN_Msk;
+ }
+
+ /* Enable slave TX underflow interrupt flag */
+ if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
+ {
+ qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk;
+ }
+
+ /* Enable TX threshold interrupt flag */
+ if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
+ {
+ qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk;
+ }
+
+ /* Enable RX threshold interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
+ {
+ qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk;
+ }
+
+ /* Enable RX overrun interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
+ {
+ qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk;
+ }
+
+ /* Enable RX time-out interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
+ {
+ qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk;
+ }
+}
+
+/**
+ * @brief Disable interrupt function.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * This parameter decides which interrupts will be disabled. It is combination of:
+ * - \ref QSPI_UNIT_INT_MASK
+ * - \ref QSPI_SSACT_INT_MASK
+ * - \ref QSPI_SSINACT_INT_MASK
+ * - \ref QSPI_SLVUR_INT_MASK
+ * - \ref QSPI_SLVBE_INT_MASK
+ * - \ref QSPI_SLVTO_INT_MASK
+ * - \ref QSPI_TXUF_INT_MASK
+ * - \ref QSPI_FIFO_TXTH_INT_MASK
+ * - \ref QSPI_FIFO_RXTH_INT_MASK
+ * - \ref QSPI_FIFO_RXOV_INT_MASK
+ * - \ref QSPI_FIFO_RXTO_INT_MASK
+ *
+ * @return None
+ * @details Disable QSPI related interrupts specified by u32Mask parameter.
+ */
+void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask)
+{
+ /* Disable unit transfer interrupt flag */
+ if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
+ {
+ qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk;
+ }
+
+ /* Disable slave selection signal active interrupt flag */
+ if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
+ {
+ qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk;
+ }
+
+ /* Disable slave selection signal inactive interrupt flag */
+ if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
+ {
+ qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk;
+ }
+
+ /* Disable slave TX under run interrupt flag */
+ if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
+ {
+ qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk;
+ }
+
+ /* Disable slave bit count error interrupt flag */
+ if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
+ {
+ qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk;
+ }
+
+ /* Disable slave mode time-out interrupt flag */
+ if((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK)
+ {
+ qspi->SSCTL &= ~QSPI_SSCTL_SLVTOIEN_Msk;
+ }
+
+ /* Disable slave TX underflow interrupt flag */
+ if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
+ {
+ qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk;
+ }
+
+ /* Disable TX threshold interrupt flag */
+ if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
+ {
+ qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk;
+ }
+
+ /* Disable RX threshold interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
+ {
+ qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk;
+ }
+
+ /* Disable RX overrun interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
+ {
+ qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk;
+ }
+
+ /* Disable RX time-out interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
+ {
+ qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk;
+ }
+}
+
+/**
+ * @brief Get interrupt flag.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be read. It is combination of:
+ * - \ref QSPI_UNIT_INT_MASK
+ * - \ref QSPI_SSACT_INT_MASK
+ * - \ref QSPI_SSINACT_INT_MASK
+ * - \ref QSPI_SLVUR_INT_MASK
+ * - \ref QSPI_SLVBE_INT_MASK
+ * - \ref QSPI_SLVTO_INT_MASK
+ * - \ref QSPI_TXUF_INT_MASK
+ * - \ref QSPI_FIFO_TXTH_INT_MASK
+ * - \ref QSPI_FIFO_RXTH_INT_MASK
+ * - \ref QSPI_FIFO_RXOV_INT_MASK
+ * - \ref QSPI_FIFO_RXTO_INT_MASK
+ *
+ * @return Interrupt flags of selected sources.
+ * @details Get QSPI related interrupt flags specified by u32Mask parameter.
+ */
+uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask)
+{
+ uint32_t u32IntStatus;
+ uint32_t u32IntFlag = 0UL;
+
+ u32IntStatus = qspi->STATUS;
+
+ /* Check unit transfer interrupt flag */
+ if((u32Mask & QSPI_UNIT_INT_MASK) && (u32IntStatus & QSPI_STATUS_UNITIF_Msk))
+ {
+ u32IntFlag |= QSPI_UNIT_INT_MASK;
+ }
+
+ /* Check slave selection signal active interrupt flag */
+ if((u32Mask & QSPI_SSACT_INT_MASK) && (u32IntStatus & QSPI_STATUS_SSACTIF_Msk))
+ {
+ u32IntFlag |= QSPI_SSACT_INT_MASK;
+ }
+
+ /* Check slave selection signal inactive interrupt flag */
+ if((u32Mask & QSPI_SSINACT_INT_MASK) && (u32IntStatus & QSPI_STATUS_SSINAIF_Msk))
+ {
+ u32IntFlag |= QSPI_SSINACT_INT_MASK;
+ }
+
+ /* Check slave TX under run interrupt flag */
+ if((u32Mask & QSPI_SLVUR_INT_MASK) && (u32IntStatus & QSPI_STATUS_SLVURIF_Msk))
+ {
+ u32IntFlag |= QSPI_SLVUR_INT_MASK;
+ }
+
+ /* Check slave bit count error interrupt flag */
+ if((u32Mask & QSPI_SLVBE_INT_MASK) && (u32IntStatus & QSPI_STATUS_SLVBEIF_Msk))
+ {
+ u32IntFlag |= QSPI_SLVBE_INT_MASK;
+ }
+
+ /* Check slave mode time-out interrupt flag */
+ if((u32Mask & QSPI_SLVTO_INT_MASK) && (u32IntStatus & QSPI_STATUS_SLVTOIF_Msk))
+ {
+ u32IntFlag |= QSPI_SLVTO_INT_MASK;
+ }
+
+ /* Check slave TX underflow interrupt flag */
+ if((u32Mask & QSPI_TXUF_INT_MASK) && (u32IntStatus & QSPI_STATUS_TXUFIF_Msk))
+ {
+ u32IntFlag |= QSPI_TXUF_INT_MASK;
+ }
+
+ /* Check TX threshold interrupt flag */
+ if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32IntStatus & QSPI_STATUS_TXTHIF_Msk))
+ {
+ u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK;
+ }
+
+ /* Check RX threshold interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32IntStatus & QSPI_STATUS_RXTHIF_Msk))
+ {
+ u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK;
+ }
+
+ /* Check RX overrun interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32IntStatus & QSPI_STATUS_RXOVIF_Msk))
+ {
+ u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK;
+ }
+
+ /* Check RX time-out interrupt flag */
+ if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32IntStatus & QSPI_STATUS_RXTOIF_Msk))
+ {
+ u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK;
+ }
+
+ return u32IntFlag;
+}
+
+/**
+ * @brief Clear interrupt flag.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be cleared. It could be the combination of:
+ * - \ref QSPI_UNIT_INT_MASK
+ * - \ref QSPI_SSACT_INT_MASK
+ * - \ref QSPI_SSINACT_INT_MASK
+ * - \ref QSPI_SLVUR_INT_MASK
+ * - \ref QSPI_SLVBE_INT_MASK
+ * - \ref QSPI_SLVTO_INT_MASK
+ * - \ref QSPI_TXUF_INT_MASK
+ * - \ref QSPI_FIFO_RXOV_INT_MASK
+ * - \ref QSPI_FIFO_RXTO_INT_MASK
+ *
+ * @return None
+ * @details Clear QSPI related interrupt flags specified by u32Mask parameter.
+ */
+void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask)
+{
+ if(u32Mask & QSPI_UNIT_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
+ }
+
+ if(u32Mask & QSPI_SSACT_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
+ }
+
+ if(u32Mask & QSPI_SSINACT_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
+ }
+
+ if(u32Mask & QSPI_SLVUR_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
+ }
+
+ if(u32Mask & QSPI_SLVBE_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
+ }
+
+ if(u32Mask & QSPI_SLVTO_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_SLVTOIF_Msk; /* Clear slave mode time-out interrupt flag */
+ }
+
+ if(u32Mask & QSPI_TXUF_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
+ }
+
+ if(u32Mask & QSPI_FIFO_RXOV_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
+ }
+
+ if(u32Mask & QSPI_FIFO_RXTO_INT_MASK)
+ {
+ qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
+ }
+}
+
+/**
+ * @brief Get QSPI status.
+ * @param[in] qspi The pointer of the specified QSPI module.
+ * @param[in] u32Mask The combination of all related sources.
+ * Each bit corresponds to a source.
+ * This parameter decides which flags will be read. It is combination of:
+ * - \ref QSPI_BUSY_MASK
+ * - \ref QSPI_RX_EMPTY_MASK
+ * - \ref QSPI_RX_FULL_MASK
+ * - \ref QSPI_TX_EMPTY_MASK
+ * - \ref QSPI_TX_FULL_MASK
+ * - \ref QSPI_TXRX_RESET_MASK
+ * - \ref QSPI_SPIEN_STS_MASK
+ * - \ref QSPI_SSLINE_STS_MASK
+ *
+ * @return Flags of selected sources.
+ * @details Get QSPI related status specified by u32Mask parameter.
+ */
+uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask)
+{
+ uint32_t u32TmpStatus;
+ uint32_t u32Flag = 0UL;
+
+ u32TmpStatus = qspi->STATUS;
+
+ /* Check busy status */
+ if((u32Mask & QSPI_BUSY_MASK) && (u32TmpStatus & QSPI_STATUS_BUSY_Msk))
+ {
+ u32Flag |= QSPI_BUSY_MASK;
+ }
+
+ /* Check RX empty flag */
+ if((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpStatus & QSPI_STATUS_RXEMPTY_Msk))
+ {
+ u32Flag |= QSPI_RX_EMPTY_MASK;
+ }
+
+ /* Check RX full flag */
+ if((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpStatus & QSPI_STATUS_RXFULL_Msk))
+ {
+ u32Flag |= QSPI_RX_FULL_MASK;
+ }
+
+ /* Check TX empty flag */
+ if((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpStatus & QSPI_STATUS_TXEMPTY_Msk))
+ {
+ u32Flag |= QSPI_TX_EMPTY_MASK;
+ }
+
+ /* Check TX full flag */
+ if((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpStatus & QSPI_STATUS_TXFULL_Msk))
+ {
+ u32Flag |= QSPI_TX_FULL_MASK;
+ }
+
+ /* Check TX/RX reset flag */
+ if((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpStatus & QSPI_STATUS_TXRXRST_Msk))
+ {
+ u32Flag |= QSPI_TXRX_RESET_MASK;
+ }
+
+ /* Check SPIEN flag */
+ if((u32Mask & QSPI_SPIEN_STS_MASK) && (u32TmpStatus & QSPI_STATUS_SPIENSTS_Msk))
+ {
+ u32Flag |= QSPI_SPIEN_STS_MASK;
+ }
+
+ /* Check QSPIx_SS line status */
+ if((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpStatus & QSPI_STATUS_SSLINE_Msk))
+ {
+ u32Flag |= QSPI_SSLINE_STS_MASK;
+ }
+
+ return u32Flag;
+}
+
+/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group QSPI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
--- /dev/null
+/**************************************************************************//**\r
+ * @file retarget.c\r
+ * @version V3.00\r
+ * @brief Debug Port and Semihost Setting Source File\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#include <stdio.h>\r
+#include "NuMicro.h"\r
+\r
+#if defined (__ICCARM__)\r
+# pragma diag_suppress=Pm150\r
+#endif\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+#if (__ARMCC_VERSION < 400000)\r
+#else\r
+/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */\r
+#pragma import _printf_widthprec\r
+#endif\r
+#endif\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Global variables */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#if !(defined(__ICCARM__) && (__VER__ >= 6010000))\r
+# if (__ARMCC_VERSION < 6040000)\r
+struct __FILE\r
+{\r
+ int handle; /* Add whatever you need here */\r
+};\r
+# endif\r
+#elif(__VER__ >= 8000000)\r
+struct __FILE\r
+{\r
+ int handle; /* Add whatever you need here */\r
+};\r
+#endif\r
+FILE __stdout;\r
+FILE __stdin;\r
+\r
+\r
+#if (defined(__ARMCC_VERSION) || defined(__ICCARM__))\r
+extern int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0);\r
+\r
+#if defined( __ICCARM__ )\r
+__WEAK\r
+#else\r
+__attribute__((weak))\r
+#endif\r
+uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp);\r
+\r
+#endif \r
+\r
+int kbhit(void);\r
+int IsDebugFifoEmpty(void);\r
+void _ttywrch(int ch);\r
+int fputc(int ch, FILE *stream);\r
+\r
+#if (defined(__ARMCC_VERSION) || defined(__ICCARM__))\r
+int fgetc(FILE *stream);\r
+int ferror(FILE *stream);\r
+#endif\r
+\r
+char GetChar(void);\r
+void SendChar_ToUART(int ch);\r
+void SendChar(int ch);\r
+\r
+#if defined(DEBUG_ENABLE_SEMIHOST)\r
+#if (defined(__ARMCC_VERSION) || defined(__ICCARM__))\r
+/* The static buffer is used to speed up the semihost */\r
+static char g_buf[16];\r
+static char g_buf_len = 0;\r
+static volatile int32_t g_ICE_Conneced = 1;\r
+\r
+/**\r
+ * @brief This function is called by Hardfault handler.\r
+ * @param None\r
+ * @returns None\r
+ * @details This function is called by Hardfault handler and check if it is caused by __BKPT or not.\r
+ *\r
+ */\r
+\r
+uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp)\r
+{\r
+ uint32_t *sp;\r
+ uint32_t inst;\r
+\r
+ /* Check the used stack */\r
+ if(lr & 0x40)\r
+ {\r
+ /* Secure stack used */\r
+ if(lr & 4)\r
+ sp = (uint32_t *)psp;\r
+ else\r
+ sp = (uint32_t *)msp;\r
+ \r
+ }\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) \r
+ else\r
+ {\r
+ /* Non-secure stack used */\r
+ if(lr & 4)\r
+ sp = (uint32_t *)__TZ_get_PSP_NS();\r
+ else\r
+ sp = (uint32_t *)__TZ_get_MSP_NS();\r
+ \r
+ }\r
+#endif \r
+ \r
+ /* Get the instruction caused the hardfault */\r
+ inst = M16(sp[6]);\r
+ \r
+ \r
+ if(inst == 0xBEAB)\r
+ {\r
+ /* \r
+ If the instruction is 0xBEAB, it means it is caused by BKPT without ICE connected.\r
+ We still return for output/input message to UART.\r
+ */\r
+ g_ICE_Conneced = 0; // Set a flag for ICE offline\r
+ sp[6] += 2; // return to next instruction\r
+ return lr; // Keep lr in R0\r
+ }\r
+ \r
+ /* It is casued by hardfault (Not semihost). Just process the hard fault here. */\r
+ /* TODO: Implement your hardfault handle code here */\r
+ \r
+ /*\r
+ printf(" HardFault!\n\n");\r
+ printf("r0 = 0x%x\n", sp[0]);\r
+ printf("r1 = 0x%x\n", sp[1]);\r
+ printf("r2 = 0x%x\n", sp[2]);\r
+ printf("r3 = 0x%x\n", sp[3]);\r
+ printf("r12 = 0x%x\n", sp[4]);\r
+ printf("lr = 0x%x\n", sp[5]);\r
+ printf("pc = 0x%x\n", sp[6]);\r
+ printf("psr = 0x%x\n", sp[7]);\r
+ */\r
+ \r
+ while(1){}\r
+ \r
+}\r
+\r
+\r
+\r
+/**\r
+ *\r
+ * @brief The function to process semihosted command\r
+ * @param[in] n32In_R0 : semihost register 0\r
+ * @param[in] n32In_R1 : semihost register 1\r
+ * @param[out] pn32Out_R0: semihost register 0\r
+ * @retval 0: No ICE debug\r
+ * @retval 1: ICE debug\r
+ *\r
+ */\r
+\r
+int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)\r
+{\r
+ if(g_ICE_Conneced)\r
+ {\r
+ if(pn32Out_R0)\r
+ *pn32Out_R0 = n32In_R0;\r
+ \r
+ return 1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+\r
+\r
+#endif\r
+#else // defined(DEBUG_ENABLE_SEMIHOST)\r
+\r
+int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0);\r
+\r
+#if defined( __ICCARM__ )\r
+__WEAK\r
+#else\r
+__attribute__((weak)) \r
+#endif\r
+uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp)\r
+{\r
+ uint32_t *sp;\r
+ /* It is casued by hardfault. Just process the hard fault */\r
+ /* TODO: Implement your hardfault handle code here */\r
+ \r
+ /* Check the used stack */\r
+ if(lr & 0x40UL)\r
+ {\r
+ /* Secure stack used */\r
+ if(lr & 4UL)\r
+ {\r
+ sp = (uint32_t *)psp;\r
+ }\r
+ else\r
+ {\r
+ sp = (uint32_t *)msp;\r
+ }\r
+ \r
+ }\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) \r
+ else\r
+ {\r
+ /* Non-secure stack used */\r
+ if(lr & 4)\r
+ sp = (uint32_t *)__TZ_get_PSP_NS();\r
+ else\r
+ sp = (uint32_t *)__TZ_get_MSP_NS();\r
+ \r
+ }\r
+#endif \r
+ \r
+ /*\r
+ printf(" HardFault!\n\n");\r
+ printf("r0 = 0x%x\n", sp[0]);\r
+ printf("r1 = 0x%x\n", sp[1]);\r
+ printf("r2 = 0x%x\n", sp[2]);\r
+ printf("r3 = 0x%x\n", sp[3]);\r
+ printf("r12 = 0x%x\n", sp[4]);\r
+ printf("lr = 0x%x\n", sp[5]);\r
+ printf("pc = 0x%x\n", sp[6]);\r
+ printf("psr = 0x%x\n", sp[7]);\r
+ */\r
+ \r
+ /* Or *sp to remove compiler warning */\r
+ while(1U|*sp){}\r
+ \r
+ return lr;\r
+}\r
+\r
+\r
+int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)\r
+{\r
+ return 0;\r
+}\r
+\r
+#endif /* defined(DEBUG_ENABLE_SEMIHOST) */\r
+\r
+\r
+/**\r
+ * @brief Routine to send a char\r
+ *\r
+ * @param[in] ch A character data writes to debug port\r
+ *\r
+ * @returns Send value from UART debug port\r
+ *\r
+ * @details Send a target char to UART debug port .\r
+ */\r
+#ifndef NONBLOCK_PRINTF\r
+void SendChar_ToUART(int ch)\r
+{\r
+\r
+ while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk){}\r
+ DEBUG_PORT->DAT = (uint32_t)ch;\r
+ if((char)ch == '\n')\r
+ {\r
+ while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk){}\r
+ DEBUG_PORT->DAT = '\r';\r
+ }\r
+}\r
+\r
+#else\r
+/* Non-block implement of send char */\r
+# define BUF_SIZE 512\r
+void SendChar_ToUART(int ch)\r
+{\r
+ static uint8_t u8Buf[BUF_SIZE] = {0};\r
+ static int32_t i32Head = 0;\r
+ static int32_t i32Tail = 0;\r
+ int32_t i32Tmp;\r
+ \r
+ /* Only flush the data in buffer to UART when ch == 0 */\r
+ if(ch)\r
+ {\r
+ // Push char\r
+ i32Tmp = i32Head+1;\r
+ if(i32Tmp > BUF_SIZE) i32Tmp = 0;\r
+ if(i32Tmp != i32Tail)\r
+ {\r
+ u8Buf[i32Head] = ch;\r
+ i32Head = i32Tmp;\r
+ }\r
+ \r
+ if(ch == '\n')\r
+ {\r
+ i32Tmp = i32Head+1;\r
+ if(i32Tmp > BUF_SIZE) i32Tmp = 0;\r
+ if(i32Tmp != i32Tail)\r
+ {\r
+ u8Buf[i32Head] = '\r';\r
+ i32Head = i32Tmp;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(i32Tail == i32Head)\r
+ return;\r
+ }\r
+ \r
+ // pop char\r
+ do\r
+ {\r
+ i32Tmp = i32Tail + 1;\r
+ if(i32Tmp > BUF_SIZE) i32Tmp = 0;\r
+ \r
+ if((DEBUG_PORT->FSR & UART_FSR_TX_FULL_Msk) == 0)\r
+ {\r
+ DEBUG_PORT->DATA = u8Buf[i32Tail];\r
+ i32Tail = i32Tmp;\r
+ }\r
+ else\r
+ break; // FIFO full\r
+ }while(i32Tail != i32Head);\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Routine to send a char\r
+ *\r
+ * @param[in] ch A character data writes to debug port\r
+ *\r
+ * @returns Send value from UART debug port or semihost\r
+ *\r
+ * @details Send a target char to UART debug port or semihost.\r
+ */\r
+void SendChar(int ch)\r
+{\r
+#if defined(DEBUG_ENABLE_SEMIHOST)\r
+ \r
+ g_buf[g_buf_len++] = ch;\r
+ g_buf[g_buf_len] = '\0';\r
+ if(g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0')\r
+ {\r
+ /* Send the char */\r
+ if(g_ICE_Conneced)\r
+ {\r
+ \r
+ if(SH_DoCommand(0x04, (int)g_buf, NULL) != 0)\r
+ {\r
+ g_buf_len = 0;\r
+ \r
+ return;\r
+ }\r
+ }\r
+ else\r
+ {\r
+# if (DEBUG_ENABLE_SEMIHOST == 2) // Re-direct to UART Debug Port only when DEBUG_ENABLE_SEMIHOST=2 \r
+ int i;\r
+\r
+ for(i = 0; i < g_buf_len; i++)\r
+ SendChar_ToUART(g_buf[i]);\r
+ g_buf_len = 0;\r
+# endif \r
+ }\r
+ }\r
+#else\r
+ SendChar_ToUART(ch);\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Routine to get a char\r
+ *\r
+ * @param None\r
+ *\r
+ * @returns Get value from UART debug port or semihost\r
+ *\r
+ * @details Wait UART debug port or semihost to input a char.\r
+ */\r
+char GetChar(void)\r
+{\r
+#ifdef DEBUG_ENABLE_SEMIHOST\r
+# if defined (__ICCARM__)\r
+ int nRet;\r
+ while(SH_DoCommand(0x7, 0, &nRet) != 0)\r
+ {\r
+ if(nRet != 0)\r
+ return (char)nRet;\r
+ }\r
+# else\r
+ int nRet;\r
+ while(SH_DoCommand(0x101, 0, &nRet) != 0)\r
+ {\r
+ if(nRet != 0)\r
+ {\r
+ SH_DoCommand(0x07, 0, &nRet);\r
+ return (char)nRet;\r
+ }\r
+ }\r
+\r
+ \r
+# if (DEBUG_ENABLE_SEMIHOST == 2) // Re-direct to UART Debug Port only when DEBUG_ENABLE_SEMIHOST=2\r
+ \r
+ /* Use debug port when ICE is not connected at semihost mode */\r
+ while(!g_ICE_Conneced)\r
+ {\r
+ if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0)\r
+ {\r
+ return (DEBUG_PORT->DAT);\r
+ }\r
+ }\r
+# endif \r
+ \r
+# endif\r
+ return (0);\r
+#else\r
+\r
+ while(1)\r
+ {\r
+ if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0U)\r
+ {\r
+ return ((char)DEBUG_PORT->DAT);\r
+ }\r
+ }\r
+\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Check any char input from UART\r
+ *\r
+ * @param None\r
+ *\r
+ * @retval 1: No any char input\r
+ * @retval 0: Have some char input\r
+ *\r
+ * @details Check UART RSR RX EMPTY or not to determine if any char input from UART\r
+ */\r
+\r
+int kbhit(void)\r
+{\r
+ return !((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0U);\r
+}\r
+/**\r
+ * @brief Check if debug message finished\r
+ *\r
+ * @param None\r
+ *\r
+ * @retval 1: Message is finished\r
+ * @retval 0: Message is transmitting.\r
+ *\r
+ * @details Check if message finished (FIFO empty of debug port)\r
+ */\r
+\r
+int IsDebugFifoEmpty(void)\r
+{\r
+ return ((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) != 0U);\r
+}\r
+\r
+/**\r
+ * @brief C library retargetting\r
+ *\r
+ * @param[in] ch Write a character data\r
+ *\r
+ * @returns None\r
+ *\r
+ * @details Check if message finished (FIFO empty of debug port)\r
+ */\r
+\r
+void _ttywrch(int ch)\r
+{\r
+ SendChar(ch);\r
+ return;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Write character to stream\r
+ *\r
+ * @param[in] ch Character to be written. The character is passed as its int promotion.\r
+ * @param[in] stream Pointer to a FILE object that identifies the stream where the character is to be written.\r
+ *\r
+ * @returns If there are no errors, the same character that has been written is returned.\r
+ * If an error occurs, EOF is returned and the error indicator is set (see ferror).\r
+ *\r
+ * @details Writes a character to the stream and advances the position indicator.\n\r
+ * The character is written at the current position of the stream as indicated \n\r
+ * by the internal position indicator, which is then advanced one character.\r
+ *\r
+ * @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/fputc/.\r
+ *\r
+ *\r
+ */\r
+\r
+int fputc(int ch, FILE *stream)\r
+{\r
+ SendChar(ch);\r
+ return ch;\r
+}\r
+\r
+\r
+#if defined ( __GNUC__ )\r
+\r
+#if !defined(OS_USE_SEMIHOSTING)\r
+int _write (int fd, char *ptr, int len)\r
+{\r
+ int i = len;\r
+\r
+ while(i--) {\r
+ while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);\r
+\r
+ DEBUG_PORT->DAT = *ptr++;\r
+\r
+ if(*ptr == '\n') {\r
+ while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);\r
+ DEBUG_PORT->DAT = '\r';\r
+ }\r
+ }\r
+ return len;\r
+}\r
+\r
+int _read (int fd, char *ptr, int len)\r
+{\r
+\r
+ while((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) != 0);\r
+ *ptr = DEBUG_PORT->DAT;\r
+ return 1;\r
+\r
+\r
+}\r
+#endif\r
+\r
+#else\r
+/**\r
+ * @brief Get character from UART debug port or semihosting input\r
+ *\r
+ * @param[in] stream Pointer to a FILE object that identifies the stream on which the operation is to be performed.\r
+ *\r
+ * @returns The character read from UART debug port or semihosting\r
+ *\r
+ * @details For get message from debug port or semihosting.\r
+ *\r
+ */\r
+\r
+int fgetc(FILE *stream)\r
+{\r
+ return ((int)GetChar());\r
+}\r
+\r
+/**\r
+ * @brief Check error indicator\r
+ *\r
+ * @param[in] stream Pointer to a FILE object that identifies the stream.\r
+ *\r
+ * @returns If the error indicator associated with the stream was set, the function returns a nonzero value.\r
+ * Otherwise, it returns a zero value.\r
+ *\r
+ * @details Checks if the error indicator associated with stream is set, returning a value different\r
+ * from zero if it is. This indicator is generally set by a previous operation on the stream that failed.\r
+ *\r
+ * @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/ferror/.\r
+ *\r
+ */\r
+\r
+int ferror(FILE *stream)\r
+{\r
+ return EOF;\r
+}\r
+#endif\r
+\r
+#ifdef DEBUG_ENABLE_SEMIHOST\r
+# ifdef __ICCARM__\r
+void __exit(int return_code)\r
+{\r
+\r
+ /* Check if link with ICE */\r
+ if(SH_DoCommand(0x18, 0x20026, NULL) == 0)\r
+ {\r
+ /* Make sure all message is print out */\r
+ while(IsDebugFifoEmpty() == 0);\r
+ }\r
+label:\r
+ goto label; /* endless loop */\r
+}\r
+# else\r
+void _sys_exit(int return_code)\r
+{\r
+\r
+ /* Check if link with ICE */\r
+ if(SH_DoCommand(0x18, 0x20026, NULL) == 0)\r
+ {\r
+ /* Make sure all message is print out */\r
+ while(IsDebugFifoEmpty() == 0);\r
+ }\r
+label:\r
+ goto label; /* endless loop */\r
+}\r
+# endif\r
+#endif\r
+\r
+\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file rtc.c\r
+ * @version V3.00\r
+ * @brief Real Time Clock(RTC) driver source file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+\r
+/** @cond HIDDEN_SYMBOLS */\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Macro, type and constant definitions */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+#define RTC_GLOBALS\r
+\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+/* Global file scope (static) variables */\r
+/*---------------------------------------------------------------------------------------------------------*/\r
+static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay;\r
+static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec;\r
+\r
+/** @endcond HIDDEN_SYMBOLS */\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup RTC_Driver RTC Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Initialize RTC module and start counting\r
+ *\r
+ * @param[in] sPt Specify the time property and current date and time. It includes: \n\r
+ * u32Year: Year value, range between 2000 ~ 2099. \n\r
+ * u32Month: Month value, range between 1 ~ 12. \n\r
+ * u32Day: Day value, range between 1 ~ 31. \n\r
+ * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /\r
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /\r
+ * RTC_SATURDAY] \n\r
+ * u32Hour: Hour value, range between 0 ~ 23. \n\r
+ * u32Minute: Minute value, range between 0 ~ 59. \n\r
+ * u32Second: Second value, range between 0 ~ 59. \n\r
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n\r
+ * u8AmPm: [RTC_AM / RTC_PM] \n\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to: \n\r
+ * 1. Write initial key to let RTC start count. \n\r
+ * 2. Input parameter indicates start date/time. \n\r
+ * 3. User has to make sure that parameters of RTC date/time are reasonable. \n\r
+ * @note Null pointer for using default starting date/time.\r
+ */\r
+void RTC_Open(S_RTC_TIME_DATA_T *sPt)\r
+{\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ pRTC->INIT = RTC_INIT_KEY;\r
+\r
+ if(pRTC->INIT != RTC_INIT_ACTIVE_Msk)\r
+ {\r
+ pRTC->INIT = RTC_INIT_KEY;\r
+ while(pRTC->INIT != RTC_INIT_ACTIVE_Msk) {}\r
+ }\r
+\r
+ if(sPt == 0)\r
+ {\r
+ ; /* No RTC date/time data */\r
+ }\r
+ else\r
+ {\r
+ /* Set RTC date and time */\r
+ RTC_SetDateAndTime(sPt);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable RTC Clock\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API will disable RTC peripheral clock and stops RTC counting.\r
+ */\r
+void RTC_Close(void)\r
+{\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ ; /* Disable RTC clock in secure mode only */\r
+ }\r
+ else\r
+ {\r
+ CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set 32k Frequency Compensation Data\r
+ *\r
+ * @param[in] i32FrequencyX10000 Specify the RTC clock X10000, ex: 327736512 means 32773.6512.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to compensate the 32 kHz frequency by current LXT frequency for RTC application.\r
+ */\r
+void RTC_32KCalibration(int32_t i32FrequencyX10000)\r
+{\r
+ uint64_t u64Compensate;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ /* u64Compensate = (uint64_t)(0x64000000000); */\r
+ u64Compensate = (uint64_t)(0x2710000000000);\r
+ u64Compensate = (uint64_t)(u64Compensate / (uint64_t)i32FrequencyX10000);\r
+ /*\r
+ Formula for 32K compensation is\r
+ FREQADJ = 0x200000 * (32768 / LXT_freq)\r
+ */\r
+ if(u64Compensate >= (uint64_t)0x400000)\r
+ {\r
+ u64Compensate = (uint64_t)0x3FFFFF;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+ pRTC->FREQADJ = (uint32_t)u64Compensate;\r
+}\r
+\r
+/**\r
+ * @brief Get Current RTC Date and Time\r
+ *\r
+ * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n\r
+ * u32Year: Year value \n\r
+ * u32Month: Month value \n\r
+ * u32Day: Day value \n\r
+ * u32DayOfWeek: Day of week \n\r
+ * u32Hour: Hour value \n\r
+ * u32Minute: Minute value \n\r
+ * u32Second: Second value \n\r
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n\r
+ * u8AmPm: [RTC_AM / RTC_PM] \n\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to get the current RTC date and time value.\r
+ */\r
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt)\r
+{\r
+ uint32_t u32Tmp;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ sPt->u32TimeScale = pRTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */\r
+ sPt->u32DayOfWeek = pRTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */\r
+\r
+ /* Get [Date digit] data */\r
+ g_u32hiYear = (pRTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos;\r
+ g_u32loYear = (pRTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos;\r
+ g_u32hiMonth = (pRTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos;\r
+ g_u32loMonth = (pRTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos;\r
+ g_u32hiDay = (pRTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos;\r
+ g_u32loDay = (pRTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos;\r
+\r
+ /* Get [Time digit] data */\r
+ g_u32hiHour = (pRTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos;\r
+ g_u32loHour = (pRTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos;\r
+ g_u32hiMin = (pRTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos;\r
+ g_u32loMin = (pRTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos;\r
+ g_u32hiSec = (pRTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos;\r
+ g_u32loSec = (pRTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos;\r
+\r
+ /* Compute to 20XX year */\r
+ u32Tmp = (g_u32hiYear * 10UL);\r
+ u32Tmp += g_u32loYear;\r
+ sPt->u32Year = u32Tmp + (uint32_t)RTC_YEAR2000;\r
+\r
+ /* Compute 0~12 month */\r
+ u32Tmp = (g_u32hiMonth * 10UL);\r
+ sPt->u32Month = u32Tmp + g_u32loMonth;\r
+\r
+ /* Compute 0~31 day */\r
+ u32Tmp = (g_u32hiDay * 10UL);\r
+ sPt->u32Day = u32Tmp + g_u32loDay;\r
+\r
+ /* Compute 12/24 hour */\r
+ if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12)\r
+ {\r
+ u32Tmp = (g_u32hiHour * 10UL);\r
+ u32Tmp += g_u32loHour;\r
+ sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */\r
+\r
+ if(sPt->u32Hour >= 21UL)\r
+ {\r
+ sPt->u32AmPm = (uint32_t)RTC_PM;\r
+ sPt->u32Hour -= 20UL;\r
+ }\r
+ else\r
+ {\r
+ sPt->u32AmPm = (uint32_t)RTC_AM;\r
+ }\r
+\r
+ u32Tmp = (g_u32hiMin * 10UL);\r
+ u32Tmp += g_u32loMin;\r
+ sPt->u32Minute = u32Tmp;\r
+\r
+ u32Tmp = (g_u32hiSec * 10UL);\r
+ u32Tmp += g_u32loSec;\r
+ sPt->u32Second = u32Tmp;\r
+ }\r
+ else\r
+ {\r
+ u32Tmp = (g_u32hiHour * 10UL);\r
+ u32Tmp += g_u32loHour;\r
+ sPt->u32Hour = u32Tmp;\r
+\r
+ u32Tmp = (g_u32hiMin * 10UL);\r
+ u32Tmp += g_u32loMin;\r
+ sPt->u32Minute = u32Tmp;\r
+\r
+ u32Tmp = (g_u32hiSec * 10UL);\r
+ u32Tmp += g_u32loSec;\r
+ sPt->u32Second = u32Tmp;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get RTC Alarm Date and Time\r
+ *\r
+ * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n\r
+ * u32Year: Year value \n\r
+ * u32Month: Month value \n\r
+ * u32Day: Day value \n\r
+ * u32DayOfWeek: Day of week \n\r
+ * u32Hour: Hour value \n\r
+ * u32Minute: Minute value \n\r
+ * u32Second: Second value \n\r
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n\r
+ * u8AmPm: [RTC_AM / RTC_PM] \n\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to get the RTC alarm date and time setting.\r
+ */\r
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)\r
+{\r
+ uint32_t u32Tmp;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ sPt->u32TimeScale = pRTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */\r
+ sPt->u32DayOfWeek = pRTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */\r
+\r
+ /* Get alarm [Date digit] data */\r
+ RTC_WaitAccessEnable();\r
+ g_u32hiYear = (pRTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos;\r
+ g_u32loYear = (pRTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos;\r
+ g_u32hiMonth = (pRTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos;\r
+ g_u32loMonth = (pRTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos;\r
+ g_u32hiDay = (pRTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos;\r
+ g_u32loDay = (pRTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos;\r
+\r
+ /* Get alarm [Time digit] data */\r
+ RTC_WaitAccessEnable();\r
+ g_u32hiHour = (pRTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos;\r
+ g_u32loHour = (pRTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos;\r
+ g_u32hiMin = (pRTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos;\r
+ g_u32loMin = (pRTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos;\r
+ g_u32hiSec = (pRTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos;\r
+ g_u32loSec = (pRTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos;\r
+\r
+ /* Compute to 20XX year */\r
+ u32Tmp = (g_u32hiYear * 10UL);\r
+ u32Tmp += g_u32loYear;\r
+ sPt->u32Year = u32Tmp + (uint32_t)RTC_YEAR2000;\r
+\r
+ /* Compute 0~12 month */\r
+ u32Tmp = (g_u32hiMonth * 10UL);\r
+ sPt->u32Month = u32Tmp + g_u32loMonth;\r
+\r
+ /* Compute 0~31 day */\r
+ u32Tmp = (g_u32hiDay * 10UL);\r
+ sPt->u32Day = u32Tmp + g_u32loDay;\r
+\r
+ /* Compute 12/24 hour */\r
+ if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12)\r
+ {\r
+ u32Tmp = (g_u32hiHour * 10UL);\r
+ u32Tmp += g_u32loHour;\r
+ sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */\r
+\r
+ if(sPt->u32Hour >= 21UL)\r
+ {\r
+ sPt->u32AmPm = (uint32_t)RTC_PM;\r
+ sPt->u32Hour -= 20UL;\r
+ }\r
+ else\r
+ {\r
+ sPt->u32AmPm = (uint32_t)RTC_AM;\r
+ }\r
+\r
+ u32Tmp = (g_u32hiMin * 10UL);\r
+ u32Tmp += g_u32loMin;\r
+ sPt->u32Minute = u32Tmp;\r
+\r
+ u32Tmp = (g_u32hiSec * 10UL);\r
+ u32Tmp += g_u32loSec;\r
+ sPt->u32Second = u32Tmp;\r
+ }\r
+ else\r
+ {\r
+ u32Tmp = (g_u32hiHour * 10UL);\r
+ u32Tmp += g_u32loHour;\r
+ sPt->u32Hour = u32Tmp;\r
+\r
+ u32Tmp = (g_u32hiMin * 10UL);\r
+ u32Tmp += g_u32loMin;\r
+ sPt->u32Minute = u32Tmp;\r
+\r
+ u32Tmp = (g_u32hiSec * 10UL);\r
+ u32Tmp += g_u32loSec;\r
+ sPt->u32Second = u32Tmp;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update Current RTC Date and Time\r
+ *\r
+ * @param[in] sPt Specify the time property and current date and time. It includes: \n\r
+ * u32Year: Year value, range between 2000 ~ 2099. \n\r
+ * u32Month: Month value, range between 1 ~ 12. \n\r
+ * u32Day: Day value, range between 1 ~ 31. \n\r
+ * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /\r
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /\r
+ * RTC_SATURDAY] \n\r
+ * u32Hour: Hour value, range between 0 ~ 23. \n\r
+ * u32Minute: Minute value, range between 0 ~ 59. \n\r
+ * u32Second: Second value, range between 0 ~ 59. \n\r
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n\r
+ * u8AmPm: [RTC_AM / RTC_PM] \n\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to update current date and time to RTC.\r
+ */\r
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)\r
+{\r
+ uint32_t u32RegCAL, u32RegTIME;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ if(sPt == 0)\r
+ {\r
+ ; /* No RTC date/time data */\r
+ }\r
+ else\r
+ {\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ /* Set RTC 24/12 hour setting and Day of the Week */\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ RTC_WaitAccessEnable();\r
+ if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12)\r
+ {\r
+ pRTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;\r
+\r
+ /*-------------------------------------------------------------------------------------------------*/\r
+ /* Important, range of 12-hour PM mode is 21 up to 32 */\r
+ /*-------------------------------------------------------------------------------------------------*/\r
+ if(sPt->u32AmPm == (uint32_t)RTC_PM)\r
+ {\r
+ sPt->u32Hour += 20UL;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ pRTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;\r
+ }\r
+\r
+ /* Set Day of the Week */\r
+ pRTC->WEEKDAY = sPt->u32DayOfWeek;\r
+\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ /* Set RTC Current Date and Time */\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ u32RegCAL = ((sPt->u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20;\r
+ u32RegCAL |= (((sPt->u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16);\r
+ u32RegCAL |= ((sPt->u32Month / 10UL) << 12);\r
+ u32RegCAL |= ((sPt->u32Month % 10UL) << 8);\r
+ u32RegCAL |= ((sPt->u32Day / 10UL) << 4);\r
+ u32RegCAL |= (sPt->u32Day % 10UL);\r
+\r
+ u32RegTIME = ((sPt->u32Hour / 10UL) << 20);\r
+ u32RegTIME |= ((sPt->u32Hour % 10UL) << 16);\r
+ u32RegTIME |= ((sPt->u32Minute / 10UL) << 12);\r
+ u32RegTIME |= ((sPt->u32Minute % 10UL) << 8);\r
+ u32RegTIME |= ((sPt->u32Second / 10UL) << 4);\r
+ u32RegTIME |= (sPt->u32Second % 10UL);\r
+\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ /* Set RTC Calender and Time Loading */\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ RTC_WaitAccessEnable();\r
+ pRTC->CAL = (uint32_t)u32RegCAL;\r
+ RTC_WaitAccessEnable();\r
+ pRTC->TIME = (uint32_t)u32RegTIME;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update RTC Alarm Date and Time\r
+ *\r
+ * @param[in] sPt Specify the time property and alarm date and time. It includes: \n\r
+ * u32Year: Year value, range between 2000 ~ 2099. \n\r
+ * u32Month: Month value, range between 1 ~ 12. \n\r
+ * u32Day: Day value, range between 1 ~ 31. \n\r
+ * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /\r
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /\r
+ * RTC_SATURDAY] \n\r
+ * u32Hour: Hour value, range between 0 ~ 23. \n\r
+ * u32Minute: Minute value, range between 0 ~ 59. \n\r
+ * u32Second: Second value, range between 0 ~ 59. \n\r
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n\r
+ * u8AmPm: [RTC_AM / RTC_PM] \n\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to update alarm date and time setting to RTC.\r
+ */\r
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)\r
+{\r
+ uint32_t u32RegCALM, u32RegTALM;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ if(sPt == 0)\r
+ {\r
+ ; /* No RTC date/time data */\r
+ }\r
+ else\r
+ {\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ /* Set RTC 24/12 hour setting and Day of the Week */\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ RTC_WaitAccessEnable();\r
+ if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12)\r
+ {\r
+ pRTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;\r
+\r
+ /*-------------------------------------------------------------------------------------------------*/\r
+ /* Important, range of 12-hour PM mode is 21 up to 32 */\r
+ /*-------------------------------------------------------------------------------------------------*/\r
+ if(sPt->u32AmPm == (uint32_t)RTC_PM)\r
+ {\r
+ sPt->u32Hour += 20UL;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ pRTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;\r
+ }\r
+\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ /* Set RTC Alarm Date and Time */\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ u32RegCALM = ((sPt->u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20;\r
+ u32RegCALM |= (((sPt->u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16);\r
+ u32RegCALM |= ((sPt->u32Month / 10UL) << 12);\r
+ u32RegCALM |= ((sPt->u32Month % 10UL) << 8);\r
+ u32RegCALM |= ((sPt->u32Day / 10UL) << 4);\r
+ u32RegCALM |= (sPt->u32Day % 10UL);\r
+\r
+ u32RegTALM = ((sPt->u32Hour / 10UL) << 20);\r
+ u32RegTALM |= ((sPt->u32Hour % 10UL) << 16);\r
+ u32RegTALM |= ((sPt->u32Minute / 10UL) << 12);\r
+ u32RegTALM |= ((sPt->u32Minute % 10UL) << 8);\r
+ u32RegTALM |= ((sPt->u32Second / 10UL) << 4);\r
+ u32RegTALM |= (sPt->u32Second % 10UL);\r
+\r
+ RTC_WaitAccessEnable();\r
+ pRTC->CALM = (uint32_t)u32RegCALM;\r
+ RTC_WaitAccessEnable();\r
+ pRTC->TALM = (uint32_t)u32RegTALM;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update RTC Current Date\r
+ *\r
+ * @param[in] u32Year The year calendar digit of current RTC setting.\r
+ * @param[in] u32Month The month calendar digit of current RTC setting.\r
+ * @param[in] u32Day The day calendar digit of current RTC setting.\r
+ * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /\r
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /\r
+ * RTC_SATURDAY]\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to update current date to RTC.\r
+ */\r
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek)\r
+{\r
+ uint32_t u32RegCAL;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ u32RegCAL = ((u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20;\r
+ u32RegCAL |= (((u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16);\r
+ u32RegCAL |= ((u32Month / 10UL) << 12);\r
+ u32RegCAL |= ((u32Month % 10UL) << 8);\r
+ u32RegCAL |= ((u32Day / 10UL) << 4);\r
+ u32RegCAL |= (u32Day % 10UL);\r
+\r
+ RTC_WaitAccessEnable();\r
+\r
+ /* Set Day of the Week */\r
+ pRTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;\r
+\r
+ /* Set RTC Calender Loading */\r
+ RTC_WaitAccessEnable();\r
+ pRTC->CAL = (uint32_t)u32RegCAL;\r
+}\r
+\r
+/**\r
+ * @brief Update RTC Current Time\r
+ *\r
+ * @param[in] u32Hour The hour time digit of current RTC setting.\r
+ * @param[in] u32Minute The minute time digit of current RTC setting.\r
+ * @param[in] u32Second The second time digit of current RTC setting.\r
+ * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]\r
+ * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to update current time to RTC.\r
+ */\r
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)\r
+{\r
+ uint32_t u32RegTIME;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ /* Important, range of 12-hour PM mode is 21 up to 32 */\r
+ if((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM))\r
+ {\r
+ u32Hour += 20UL;\r
+ }\r
+\r
+ u32RegTIME = ((u32Hour / 10UL) << 20);\r
+ u32RegTIME |= ((u32Hour % 10UL) << 16);\r
+ u32RegTIME |= ((u32Minute / 10UL) << 12);\r
+ u32RegTIME |= ((u32Minute % 10UL) << 8);\r
+ u32RegTIME |= ((u32Second / 10UL) << 4);\r
+ u32RegTIME |= (u32Second % 10UL);\r
+\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ /* Set RTC 24/12 hour setting and Day of the Week */\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ RTC_WaitAccessEnable();\r
+ if(u32TimeMode == (uint32_t)RTC_CLOCK_12)\r
+ {\r
+ pRTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;\r
+ }\r
+ else\r
+ {\r
+ pRTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+ pRTC->TIME = (uint32_t)u32RegTIME;\r
+}\r
+\r
+/**\r
+ * @brief Update RTC Alarm Date\r
+ *\r
+ * @param[in] u32Year The year calendar digit of RTC alarm setting.\r
+ * @param[in] u32Month The month calendar digit of RTC alarm setting.\r
+ * @param[in] u32Day The day calendar digit of RTC alarm setting.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to update alarm date setting to RTC.\r
+ */\r
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day)\r
+{\r
+ uint32_t u32RegCALM;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ u32RegCALM = ((u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20;\r
+ u32RegCALM |= (((u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16);\r
+ u32RegCALM |= ((u32Month / 10UL) << 12);\r
+ u32RegCALM |= ((u32Month % 10UL) << 8);\r
+ u32RegCALM |= ((u32Day / 10UL) << 4);\r
+ u32RegCALM |= (u32Day % 10UL);\r
+\r
+ RTC_WaitAccessEnable();\r
+\r
+ /* Set RTC Alarm Date */\r
+ pRTC->CALM = (uint32_t)u32RegCALM;\r
+}\r
+\r
+/**\r
+ * @brief Update RTC Alarm Time\r
+ *\r
+ * @param[in] u32Hour The hour time digit of RTC alarm setting.\r
+ * @param[in] u32Minute The minute time digit of RTC alarm setting.\r
+ * @param[in] u32Second The second time digit of RTC alarm setting.\r
+ * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]\r
+ * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to update alarm time setting to RTC.\r
+ */\r
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)\r
+{\r
+ uint32_t u32RegTALM;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ /* Important, range of 12-hour PM mode is 21 up to 32 */\r
+ if((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM))\r
+ {\r
+ u32Hour += 20UL;\r
+ }\r
+\r
+ u32RegTALM = ((u32Hour / 10UL) << 20);\r
+ u32RegTALM |= ((u32Hour % 10UL) << 16);\r
+ u32RegTALM |= ((u32Minute / 10UL) << 12);\r
+ u32RegTALM |= ((u32Minute % 10UL) << 8);\r
+ u32RegTALM |= ((u32Second / 10UL) << 4);\r
+ u32RegTALM |= (u32Second % 10UL);\r
+\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ /* Set RTC 24/12 hour setting and Day of the Week */\r
+ /*-----------------------------------------------------------------------------------------------------*/\r
+ RTC_WaitAccessEnable();\r
+ if(u32TimeMode == (uint32_t)RTC_CLOCK_12)\r
+ {\r
+ pRTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;\r
+ }\r
+ else\r
+ {\r
+ pRTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;\r
+ }\r
+\r
+ /* Set RTC Alarm Time */\r
+ RTC_WaitAccessEnable();\r
+ pRTC->TALM = (uint32_t)u32RegTALM;\r
+}\r
+\r
+/**\r
+ * @brief Set RTC Alarm Date Mask Function\r
+ *\r
+ * @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled.\r
+ * @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled.\r
+ * @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled.\r
+ * @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled.\r
+ * @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled.\r
+ * @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to enable or disable RTC alarm date mask function.\r
+ */\r
+void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk)\r
+{\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+ pRTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) |\r
+ ((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) |\r
+ ((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) |\r
+ ((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) |\r
+ ((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) |\r
+ ((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos);\r
+}\r
+\r
+/**\r
+ * @brief Set RTC Alarm Time Mask Function\r
+ *\r
+ * @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled.\r
+ * @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled.\r
+ * @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled.\r
+ * @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled.\r
+ * @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled.\r
+ * @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to enable or disable RTC alarm time mask function.\r
+ */\r
+void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk)\r
+{\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+ pRTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) |\r
+ ((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) |\r
+ ((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) |\r
+ ((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) |\r
+ ((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) |\r
+ ((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos);\r
+}\r
+\r
+/**\r
+ * @brief Get Day of the Week\r
+ *\r
+ * @param None\r
+ *\r
+ * @retval 0 Sunday\r
+ * @retval 1 Monday\r
+ * @retval 2 Tuesday\r
+ * @retval 3 Wednesday\r
+ * @retval 4 Thursday\r
+ * @retval 5 Friday\r
+ * @retval 6 Saturday\r
+ *\r
+ * @details This API is used to get day of the week of current RTC date.\r
+ */\r
+uint32_t RTC_GetDayOfWeek(void)\r
+{\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ return (pRTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Set RTC Tick Period Time\r
+ *\r
+ * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n\r
+ * It consists of:\r
+ * - \ref RTC_TICK_1_SEC : Time tick is 1 second\r
+ * - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second\r
+ * - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second\r
+ * - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second\r
+ * - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second\r
+ * - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second\r
+ * - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second\r
+ * - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to set RTC tick period time for each tick interrupt.\r
+ */\r
+void RTC_SetTickPeriod(uint32_t u32TickSelection)\r
+{\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+\r
+ pRTC->TICK = (pRTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection;\r
+}\r
+\r
+/**\r
+ * @brief Enable RTC Interrupt\r
+ *\r
+ * @param[in] u32IntFlagMask Specify the interrupt source. It consists of:\r
+ * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt\r
+ * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt\r
+ * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt\r
+ * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 or Pair 0 Pin Event Detection interrupt\r
+ * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt\r
+ * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 or Pair 1 Pin Event Detection interrupt\r
+ * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt\r
+ * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 or Pair 2 Pin Event Detection interrupt\r
+ * - \ref RTC_INTEN_CLKFIEN_Msk : LXT Clock Frequency Monitor Fail interrupt\r
+ * - \ref RTC_INTEN_CLKSPIEN_Msk : LXT Clock Frequency Monitor Stop interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to enable the specify RTC interrupt function.\r
+ */\r
+void RTC_EnableInt(uint32_t u32IntFlagMask)\r
+{\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ pRTC->INTEN |= u32IntFlagMask;\r
+}\r
+\r
+/**\r
+ * @brief Disable RTC Interrupt\r
+ *\r
+ * @param[in] u32IntFlagMask Specify the interrupt source. It consists of:\r
+ * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt\r
+ * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt\r
+ * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt\r
+ * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 or Pair 0 Pin Event Detection interrupt\r
+ * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt\r
+ * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 or Pair 1 Pin Event Detection interrupt\r
+ * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt\r
+ * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 or Pair 2 Pin Event Detection interrupt\r
+ * - \ref RTC_INTEN_CLKFIEN_Msk : LXT Clock Frequency Monitor Fail interrupt\r
+ * - \ref RTC_INTEN_CLKSPIEN_Msk : LXT Clock Frequency Monitor Stop interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to disable the specify RTC interrupt function.\r
+ */\r
+void RTC_DisableInt(uint32_t u32IntFlagMask)\r
+{\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ pRTC->INTEN &= ~u32IntFlagMask;\r
+ pRTC->INTSTS = u32IntFlagMask;\r
+}\r
+\r
+/**\r
+ * @brief Enable Spare Registers Access\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to enable the spare registers 0~19 can be accessed.\r
+ */\r
+void RTC_EnableSpareAccess(void)\r
+{\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+\r
+ pRTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable Spare Register\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to disable the spare register 0~19 cannot be accessed.\r
+ */\r
+void RTC_DisableSpareRegister(void)\r
+{\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+\r
+ pRTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Static Tamper Detect\r
+ *\r
+ * @param[in] u32TamperSelect Tamper pin select. Possible options are\r
+ * - \ref RTC_TAMPER5_SELECT\r
+ * - \ref RTC_TAMPER4_SELECT\r
+ * - \ref RTC_TAMPER3_SELECT\r
+ * - \ref RTC_TAMPER2_SELECT\r
+ * - \ref RTC_TAMPER1_SELECT\r
+ * - \ref RTC_TAMPER0_SELECT\r
+ *\r
+ * @param[in] u32DetecLevel Tamper pin detection level select. Possible options are\r
+ * - \ref RTC_TAMPER_HIGH_LEVEL_DETECT\r
+ * - \ref RTC_TAMPER_LOW_LEVEL_DETECT\r
+ *\r
+ * @param[in] u32DebounceEn Tamper pin de-bounce enable\r
+ * - \ref RTC_TAMPER_DEBOUNCE_ENABLE\r
+ * - \ref RTC_TAMPER_DEBOUNCE_DISABLE\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to enable the tamper pin detect function with specify trigger condition.\r
+ * User need disable dynamic tamper function before use this API.\r
+ */\r
+void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn)\r
+{\r
+ uint32_t i;\r
+ uint32_t u32Reg;\r
+ uint32_t u32TmpReg;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+ u32Reg = pRTC->TAMPCTL;\r
+\r
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) |\r
+ (u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos));\r
+\r
+ for(i = 0UL; i < (uint32_t)MAX_TAMPER_PIN_NUM; i++)\r
+ {\r
+ if(u32TamperSelect & (0x1UL << i))\r
+ {\r
+ u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP0LV_Msk | RTC_TAMPCTL_TAMP0DBEN_Msk) << (i * 4UL));\r
+ u32Reg |= (u32TmpReg << (i * 4UL));\r
+ }\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+ pRTC->TAMPCTL = u32Reg;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Static Tamper Disable\r
+ *\r
+ * @param[in] u32TamperSelect Tamper pin select. Possible options are\r
+ * - \ref RTC_TAMPER5_SELECT\r
+ * - \ref RTC_TAMPER4_SELECT\r
+ * - \ref RTC_TAMPER3_SELECT\r
+ * - \ref RTC_TAMPER2_SELECT\r
+ * - \ref RTC_TAMPER1_SELECT\r
+ * - \ref RTC_TAMPER0_SELECT\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to disable the static tamper pin detect.\r
+ */\r
+void RTC_StaticTamperDisable(uint32_t u32TamperSelect)\r
+{\r
+ uint32_t i;\r
+ uint32_t u32Reg;\r
+ uint32_t u32TmpReg;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+ u32Reg = pRTC->TAMPCTL;\r
+\r
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk);\r
+\r
+ for(i = 0UL; i < (uint32_t)MAX_TAMPER_PIN_NUM; i++)\r
+ {\r
+ if(u32TamperSelect & (0x1UL << i))\r
+ {\r
+ u32Reg &= ~(u32TmpReg << (i * 4UL));\r
+ }\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+ pRTC->TAMPCTL = u32Reg;\r
+}\r
+\r
+/**\r
+ * @brief Dynamic Tamper Detect\r
+ *\r
+ * @param[in] u32PairSel Tamper pin detection enable. Possible options are\r
+ * - \ref RTC_PAIR0_SELECT\r
+ * - \ref RTC_PAIR1_SELECT\r
+ * - \ref RTC_PAIR2_SELECT\r
+ *\r
+ * @param[in] u32DebounceEn Tamper pin de-bounce enable\r
+ * - \ref RTC_TAMPER_DEBOUNCE_ENABLE\r
+ * - \ref RTC_TAMPER_DEBOUNCE_DISABLE\r
+ *\r
+ * @param[in] u32Pair1Source Dynamic Pair 1 Input Source Select\r
+ * 0: Pair 1 source select tamper 2\r
+ * 1: Pair 1 source select tamper 0\r
+ *\r
+ * @param[in] u32Pair2Source Dynamic Pair 2 Input Source Select\r
+ * 0: Pair 2 source select tamper 4\r
+ * 1: Pair 2 source select tamper 0\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to enable the dynamic tamper.\r
+ */\r
+void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source)\r
+{\r
+ uint32_t i;\r
+ uint32_t u32Reg;\r
+ uint32_t u32TmpReg;\r
+ uint32_t u32Tamper2Debounce, u32Tamper4Debounce;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+ u32Reg = pRTC->TAMPCTL;\r
+ u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk |\r
+ RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk);\r
+\r
+ u32Tamper2Debounce = u32Reg & RTC_TAMPCTL_TAMP2DBEN_Msk;\r
+ u32Tamper4Debounce = u32Reg & RTC_TAMPCTL_TAMP4DBEN_Msk;\r
+\r
+ u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk |\r
+ RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk);\r
+ u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk);\r
+ u32Reg |= ((u32Pair1Source & 0x1UL) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1UL) << RTC_TAMPCTL_DYN2ISS_Pos);\r
+\r
+ if(u32DebounceEn)\r
+ {\r
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk |\r
+ RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);\r
+ }\r
+ else\r
+ {\r
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);\r
+ }\r
+\r
+ for(i = 0UL; i < (uint32_t)MAX_PAIR_NUM; i++)\r
+ {\r
+ if(u32PairSel & (0x1UL << i))\r
+ {\r
+ u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i * 8UL));\r
+ u32Reg |= (u32TmpReg << (i * 8UL));\r
+ }\r
+ }\r
+\r
+ if((u32Pair1Source) && (u32PairSel & (uint32_t)RTC_PAIR1_SELECT))\r
+ {\r
+ u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk;\r
+ u32Reg |= u32Tamper2Debounce;\r
+ }\r
+\r
+ if((u32Pair2Source) && (u32PairSel & (uint32_t)RTC_PAIR2_SELECT))\r
+ {\r
+ u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk;\r
+ u32Reg |= u32Tamper4Debounce;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+ pRTC->TAMPCTL = u32Reg;\r
+}\r
+\r
+/**\r
+ * @brief Dynamic Tamper Disable\r
+ *\r
+ * @param[in] u32PairSel Tamper pin detection enable. Possible options are\r
+ * - \ref RTC_PAIR0_SELECT\r
+ * - \ref RTC_PAIR1_SELECT\r
+ * - \ref RTC_PAIR2_SELECT\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to disable the dynamic tamper.\r
+ */\r
+void RTC_DynamicTamperDisable(uint32_t u32PairSel)\r
+{\r
+ uint32_t i;\r
+ uint32_t u32Reg;\r
+ uint32_t u32TmpReg;\r
+ uint32_t u32Tamper2En = 0UL, u32Tamper4En = 0UL;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+ u32Reg = pRTC->TAMPCTL;\r
+\r
+ if((u32Reg & (uint32_t)RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & (uint32_t)RTC_PAIR1_SELECT))\r
+ {\r
+ u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk;\r
+ }\r
+\r
+ if((u32Reg & (uint32_t)RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & (uint32_t)RTC_PAIR2_SELECT))\r
+ {\r
+ u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk;\r
+ }\r
+\r
+ u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);\r
+\r
+ for(i = 0UL; i < (uint32_t)MAX_PAIR_NUM; i++)\r
+ {\r
+ if(u32PairSel & (0x1UL << i))\r
+ {\r
+ u32Reg &= ~(u32TmpReg << ((i * 8UL)));\r
+ }\r
+ }\r
+\r
+ u32Reg |= (u32Tamper2En | u32Tamper4En);\r
+\r
+ RTC_WaitAccessEnable();\r
+ pRTC->TAMPCTL = u32Reg;\r
+}\r
+\r
+/**\r
+ * @brief Config dynamic tamper\r
+ *\r
+ * @param[in] u32ChangeRate The dynamic tamper output change rate\r
+ * - \ref RTC_2POW10_CLK\r
+ * - \ref RTC_2POW11_CLK\r
+ * - \ref RTC_2POW12_CLK\r
+ * - \ref RTC_2POW13_CLK\r
+ * - \ref RTC_2POW14_CLK\r
+ * - \ref RTC_2POW15_CLK\r
+ * - \ref RTC_2POW16_CLK\r
+ * - \ref RTC_2POW17_CLK\r
+ *\r
+ * @param[in] u32SeedReload Reload new seed or not\r
+ * 0: not reload new seed\r
+ * 1: reload new seed\r
+ *\r
+ * @param[in] u32RefPattern Reference pattern\r
+ * - \ref REF_RANDOM_PATTERN\r
+ * - \ref REF_PREVIOUS_PATTERN\r
+ * - \ref REF_SEED\r
+ *\r
+ * @param[in] u32Seed Seed Value (0x0 ~ 0xFFFFFFFF)\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to config dynamic tamper setting.\r
+ */\r
+void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed)\r
+{\r
+ uint32_t u32Reg;\r
+ RTC_T *pRTC;\r
+\r
+ if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pRTC = RTC_NS;\r
+ }\r
+ else\r
+ {\r
+ pRTC = RTC;\r
+ }\r
+\r
+ RTC_WaitAccessEnable();\r
+ u32Reg = pRTC->TAMPCTL;\r
+\r
+ u32Reg &= ~(RTC_TAMPCTL_DYNSRC_Msk | RTC_TAMPCTL_SEEDRLD_Msk | RTC_TAMPCTL_DYNRATE_Msk);\r
+\r
+ u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1UL) << RTC_TAMPCTL_SEEDRLD_Pos) |\r
+ ((u32RefPattern & 0x3UL) << RTC_TAMPCTL_DYNSRC_Pos);\r
+\r
+ RTC_WaitAccessEnable();\r
+ pRTC->TAMPSEED = u32Seed; /* need set seed value before re-loade seed */\r
+ pRTC->TAMPCTL = u32Reg;\r
+}\r
+\r
+/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group RTC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file sc.c\r
+ * @version V3.00\r
+ * @brief Smartcard(SC) driver source file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */\r
+/** @cond HIDDEN_SYMBOLS */\r
+static uint32_t g_u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL, 0UL, 0UL};\r
+\r
+/** @endcond HIDDEN_SYMBOLS */\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SC_Driver SC Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Indicates specified smartcard slot status\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Card insert status\r
+ * @retval TRUE Card insert\r
+ * @retval FALSE Card remove\r
+ *\r
+ * @details This function is used to check if specified smartcard slot is presented.\r
+ */\r
+uint32_t SC_IsCardInserted(SC_T *sc)\r
+{\r
+ uint32_t u32Ret;\r
+\r
+ /* put conditions into two variable to remove IAR compilation warning */\r
+ uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos);\r
+ uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos);\r
+\r
+ if(((sc == SC0) || (sc == SC0_NS)) && (g_u32CardStateIgnore[0] == 1UL))\r
+ {\r
+ u32Ret = (uint32_t)TRUE;\r
+ }\r
+ else if(((sc == SC1) || (sc == SC1_NS)) && (g_u32CardStateIgnore[1] == 1UL))\r
+ {\r
+ u32Ret = (uint32_t)TRUE;\r
+ }\r
+ else if(((sc == SC2) || (sc == SC2_NS)) && (g_u32CardStateIgnore[2] == 1UL))\r
+ {\r
+ u32Ret = (uint32_t)TRUE;\r
+ }\r
+ else if(cond1 != cond2)\r
+ {\r
+ u32Ret = (uint32_t)FALSE;\r
+ }\r
+ else\r
+ {\r
+ u32Ret = (uint32_t)TRUE;\r
+ }\r
+\r
+ return u32Ret;\r
+}\r
+\r
+/*\r
+ * @brief Reset the Tx and Rx FIFO of smartcard module\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function reset both transmit and receive FIFO of specified smartcard module.\r
+ */\r
+void SC_ClearFIFO(SC_T *sc)\r
+{\r
+ while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk)\r
+ {\r
+ ;\r
+ }\r
+ sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Disable specified smartcard module\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function disable specified smartcard module, and force all transition to IDLE state.\r
+ */\r
+void SC_Close(SC_T *sc)\r
+{\r
+ sc->INTEN = 0UL;\r
+ while(sc->PINCTL & SC_PINCTL_SYNC_Msk)\r
+ {\r
+ ;\r
+ }\r
+ sc->PINCTL = 0UL;\r
+ sc->ALTCTL = 0UL;\r
+ while(sc->CTL & SC_CTL_SYNC_Msk)\r
+ {\r
+ ;\r
+ }\r
+ sc->CTL = 0UL;\r
+}\r
+\r
+/**\r
+ * @brief Initialized smartcard module\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32CardDet Card detect polarity, select the SC_CD pin state which indicates card absent. Could be:\r
+ * -\ref SC_PIN_STATE_HIGH\r
+ * -\ref SC_PIN_STATE_LOW\r
+ * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present.\r
+ * @param[in] u32PWR Power off polarity, select the SC_PWR pin state which could set smartcard VCC to high level. Could be:\r
+ * -\ref SC_PIN_STATE_HIGH\r
+ * -\ref SC_PIN_STATE_LOW\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function initialized smartcard module.\r
+ */\r
+void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR)\r
+{\r
+ uint32_t u32Reg = 0UL, u32Intf;\r
+\r
+ if((sc == SC0) || (sc == SC0_NS))\r
+ {\r
+ u32Intf = 0UL;\r
+ }\r
+ else if((sc == SC1) || (sc == SC1_NS))\r
+ {\r
+ u32Intf = 1UL;\r
+ }\r
+ else\r
+ {\r
+ u32Intf = 2UL;\r
+ }\r
+\r
+ if(u32CardDet != SC_PIN_STATE_IGNORE)\r
+ {\r
+ u32Reg = u32CardDet ? 0UL : SC_CTL_CDLV_Msk;\r
+ g_u32CardStateIgnore[u32Intf] = 0UL;\r
+ }\r
+ else\r
+ {\r
+ g_u32CardStateIgnore[u32Intf] = 1UL;\r
+ }\r
+ sc->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk;\r
+ while(sc->CTL & SC_CTL_SYNC_Msk)\r
+ {\r
+ ;\r
+ }\r
+ sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_TMRSEL_Msk | u32Reg;\r
+}\r
+\r
+/**\r
+ * @brief Reset specified smartcard module\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function reset specified smartcard module to its default state for activate smartcard.\r
+ */\r
+void SC_ResetReader(SC_T *sc)\r
+{\r
+ uint32_t u32Intf;\r
+\r
+ if((sc == SC0) || (sc == SC0_NS))\r
+ {\r
+ u32Intf = 0UL;\r
+ }\r
+ else if((sc == SC1) || (sc == SC1_NS))\r
+ {\r
+ u32Intf = 1UL;\r
+ }\r
+ else\r
+ {\r
+ u32Intf = 2UL;\r
+ }\r
+\r
+ /* Reset FIFO, enable auto de-activation while card removal */\r
+ sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk);\r
+ /* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */\r
+ while(sc->CTL & SC_CTL_SYNC_Msk)\r
+ {\r
+ ;\r
+ }\r
+ sc->CTL &= ~(SC_CTL_RXTRGLV_Msk |\r
+ SC_CTL_CDDBSEL_Msk |\r
+ SC_CTL_TXRTY_Msk |\r
+ SC_CTL_TXRTYEN_Msk |\r
+ SC_CTL_RXRTY_Msk |\r
+ SC_CTL_RXRTYEN_Msk);\r
+ while(sc->CTL & SC_CTL_SYNC_Msk)\r
+ {\r
+ ;\r
+ }\r
+ /* Enable auto convention, and all three smartcard internal timers */\r
+ sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk;\r
+ /* Disable Rx timeout */\r
+ sc->RXTOUT = 0UL;\r
+ /* 372 clocks per ETU by default */\r
+ sc->ETUCTL = 371UL;\r
+\r
+ /* Enable necessary interrupt for smartcard operation */\r
+ if(g_u32CardStateIgnore[u32Intf]) /* Do not enable card detect interrupt if card present state ignore */\r
+ {\r
+ sc->INTEN = (SC_INTEN_RDAIEN_Msk |\r
+ SC_INTEN_TERRIEN_Msk |\r
+ SC_INTEN_TMR0IEN_Msk |\r
+ SC_INTEN_TMR1IEN_Msk |\r
+ SC_INTEN_TMR2IEN_Msk |\r
+ SC_INTEN_BGTIEN_Msk |\r
+ SC_INTEN_ACERRIEN_Msk);\r
+ }\r
+ else\r
+ {\r
+ sc->INTEN = (SC_INTEN_RDAIEN_Msk |\r
+ SC_INTEN_TERRIEN_Msk |\r
+ SC_INTEN_TMR0IEN_Msk |\r
+ SC_INTEN_TMR1IEN_Msk |\r
+ SC_INTEN_TMR2IEN_Msk |\r
+ SC_INTEN_BGTIEN_Msk |\r
+ SC_INTEN_ACERRIEN_Msk |\r
+ SC_INTEN_CDIEN_Msk);\r
+ }\r
+\r
+ return;\r
+}\r
+\r
+/**\r
+ * @brief Set Block Guard Time (BGT)\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to configure block guard time (BGT) of specified smartcard module.\r
+ */\r
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT)\r
+{\r
+ sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos);\r
+}\r
+\r
+/**\r
+ * @brief Set Character Guard Time (CGT)\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to configure character guard time (CGT) of specified smartcard module.\r
+ * @note Before using this API, user should set the correct stop bit length first.\r
+ */\r
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT)\r
+{\r
+ /* CGT is "START bit" + "8-bits" + "Parity bit" + "STOP bit(s)" + "EGT counts" */\r
+ u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11UL : 12UL;\r
+ sc->EGT = u32CGT;\r
+}\r
+\r
+/**\r
+ * @brief Stop all smartcard timer\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @note This function stop the timers within specified smartcard module, \b not timer module.\r
+ */\r
+void SC_StopAllTimer(SC_T *sc)\r
+{\r
+ while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk)\r
+ {\r
+ ;\r
+ }\r
+ sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Configure and start smartcard timer\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32TimerNum Timer to start. Valid values are 0, 1, 2.\r
+ * @param[in] u32Mode Timer operating mode, valid values are:\r
+ * - \ref SC_TMR_MODE_0\r
+ * - \ref SC_TMR_MODE_1\r
+ * - \ref SC_TMR_MODE_2\r
+ * - \ref SC_TMR_MODE_3\r
+ * - \ref SC_TMR_MODE_4\r
+ * - \ref SC_TMR_MODE_5\r
+ * - \ref SC_TMR_MODE_6\r
+ * - \ref SC_TMR_MODE_7\r
+ * - \ref SC_TMR_MODE_8\r
+ * - \ref SC_TMR_MODE_F\r
+ * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1 ~ 0x1000000 ETUs.\r
+ * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs.\r
+ *\r
+ * @return None\r
+ *\r
+ * @note This function start the timer within specified smartcard module, \b not timer module.\r
+ * @note Depend on the timer operating mode, timer may not start counting immediately and starts when condition match.\r
+ */\r
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount)\r
+{\r
+ uint32_t u32Reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL));\r
+ while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk)\r
+ {\r
+ ;\r
+ }\r
+ if(u32TimerNum == 0UL)\r
+ {\r
+ while(sc->TMRCTL0 & SC_TMRCTL0_SYNC_Msk)\r
+ {\r
+ ;\r
+ }\r
+ sc->TMRCTL0 = u32Reg;\r
+ sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk;\r
+ }\r
+ else if(u32TimerNum == 1UL)\r
+ {\r
+ while(sc->TMRCTL1 & SC_TMRCTL1_SYNC_Msk)\r
+ {\r
+ ;\r
+ }\r
+ sc->TMRCTL1 = u32Reg;\r
+ sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk;\r
+ }\r
+ else /* timer 2 */\r
+ {\r
+ while(sc->TMRCTL2 & SC_TMRCTL2_SYNC_Msk)\r
+ {\r
+ ;\r
+ }\r
+ sc->TMRCTL2 = u32Reg;\r
+ sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Stop a smartcard timer\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32TimerNum Timer to stop. Valid values are 0, 1, 2.\r
+ *\r
+ * @return None\r
+ *\r
+ * @note This function stop the timer within specified smartcard module, \b not timer module.\r
+ */\r
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum)\r
+{\r
+ while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) {}\r
+\r
+ if(u32TimerNum == 0UL) /* timer 0 */\r
+ {\r
+ sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk;\r
+ }\r
+ else if(u32TimerNum == 1UL) /* timer 1 */\r
+ {\r
+ sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk;\r
+ }\r
+ else /* timer 2 */\r
+ {\r
+ sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get smartcard clock frequency\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Smartcard frequency in kHZ\r
+ *\r
+ * @details This function is used to get specified smartcard module clock frequency in kHz.\r
+ */\r
+uint32_t SC_GetInterfaceClock(SC_T *sc)\r
+{\r
+ uint32_t u32ClkSrc, u32Num, u32Clk = __HIRC, u32Div;\r
+\r
+ /* Get smartcard module clock source and divider */\r
+ if((sc == SC0) || (sc == SC0_NS))\r
+ {\r
+ u32Num = 0UL;\r
+ u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE);\r
+ u32Div = CLK_GetModuleClockDivider(SC0_MODULE);\r
+ }\r
+ else if((sc == SC1) || (sc == SC1_NS))\r
+ {\r
+ u32Num = 1UL;\r
+ u32ClkSrc = CLK_GetModuleClockSource(SC1_MODULE);\r
+ u32Div = CLK_GetModuleClockDivider(SC1_MODULE);\r
+ }\r
+ else if((sc == SC2) || (sc == SC2_NS))\r
+ {\r
+ u32Num = 2UL;\r
+ u32ClkSrc = CLK_GetModuleClockSource(SC2_MODULE);\r
+ u32Div = CLK_GetModuleClockDivider(SC2_MODULE);\r
+ }\r
+ else\r
+ {\r
+ u32Clk = 0UL;\r
+ }\r
+\r
+ if(u32Clk == 0UL)\r
+ {\r
+ ; /* Invalid sc port */\r
+ }\r
+ else\r
+ {\r
+ /* Get smartcard module clock */\r
+ if(u32ClkSrc == 0UL)\r
+ {\r
+ u32Clk = __HXT;\r
+ }\r
+ else if(u32ClkSrc == 1UL)\r
+ {\r
+ u32Clk = CLK_GetPLLClockFreq();\r
+ }\r
+ else if(u32ClkSrc == 2UL)\r
+ {\r
+ if(u32Num == 1UL)\r
+ {\r
+ u32Clk = CLK_GetPCLK1Freq();\r
+ }\r
+ else\r
+ {\r
+ u32Clk = CLK_GetPCLK0Freq();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ u32Clk = __HIRC;\r
+ }\r
+\r
+ u32Clk /= (u32Div + 1UL) * 1000UL;\r
+ }\r
+\r
+ return u32Clk;\r
+}\r
+\r
+/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group SC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file scuart.c\r
+ * @version V3.00\r
+ * @brief Smartcard UART mode (SCUART) driver source file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+static uint32_t SCUART_GetClock(SC_T *sc);\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SCUART_Driver SCUART Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Disable smartcard interface\r
+ *\r
+ * @param sc The pointer of smartcard module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to disable smartcard interface UART mode.\r
+ */\r
+void SCUART_Close(SC_T* sc)\r
+{\r
+ sc->INTEN = 0UL;\r
+ sc->UARTCTL = 0UL;\r
+ sc->CTL = 0UL;\r
+}\r
+\r
+/** @cond HIDDEN_SYMBOLS */\r
+/**\r
+ * @brief Returns module clock of specified SC interface\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ *\r
+ * @return Module clock of specified SC interface.\r
+ */\r
+static uint32_t SCUART_GetClock(SC_T *sc)\r
+{\r
+ uint32_t u32ClkSrc, u32Num, u32Clk = __HIRC, u32Div;\r
+\r
+ /* Get smartcard module clock source and divider */\r
+ if((sc == SC0) || (sc == SC0_NS))\r
+ {\r
+ u32Num = 0UL;\r
+ u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE);\r
+ u32Div = CLK_GetModuleClockDivider(SC0_MODULE);\r
+ }\r
+ else if((sc == SC1) || (sc == SC1_NS))\r
+ {\r
+ u32Num = 1UL;\r
+ u32ClkSrc = CLK_GetModuleClockSource(SC1_MODULE);\r
+ u32Div = CLK_GetModuleClockDivider(SC1_MODULE);\r
+ }\r
+ else if((sc == SC2) || (sc == SC2_NS))\r
+ {\r
+ u32Num = 2UL;\r
+ u32ClkSrc = CLK_GetModuleClockSource(SC2_MODULE);\r
+ u32Div = CLK_GetModuleClockDivider(SC2_MODULE);\r
+ }\r
+ else\r
+ {\r
+ u32Clk = 0UL;\r
+ }\r
+\r
+ if(u32Clk == 0UL)\r
+ {\r
+ ; /* Invalid sc port */\r
+ }\r
+ else\r
+ {\r
+ /* Get smartcard module clock */\r
+ if(u32ClkSrc == 0UL)\r
+ {\r
+ u32Clk = __HXT;\r
+ }\r
+ else if(u32ClkSrc == 1UL)\r
+ {\r
+ u32Clk = CLK_GetPLLClockFreq();\r
+ }\r
+ else if(u32ClkSrc == 2UL)\r
+ {\r
+ if(u32Num == 1UL)\r
+ {\r
+ u32Clk = CLK_GetPCLK1Freq();\r
+ }\r
+ else\r
+ {\r
+ u32Clk = CLK_GetPCLK0Freq();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ u32Clk = __HIRC;\r
+ }\r
+\r
+ u32Clk /= (u32Div + 1UL);\r
+ }\r
+\r
+ return u32Clk;\r
+}\r
+/** @endcond HIDDEN_SYMBOLS */\r
+\r
+/**\r
+ * @brief Enable smartcard module UART mode and set baudrate\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32Baudrate Target baudrate of smartcard UART module.\r
+ *\r
+ * @return Actual baudrate of smartcard UART mode\r
+ *\r
+ * @details This function use to enable smartcard module UART mode and set baudrate.\r
+ *\r
+ * @note This function configures character width to 8 bits, 1 stop bit, and no parity.\r
+ * And can use \ref SCUART_SetLineConfig function to update these settings.\r
+ * The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled\r
+ * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1\r
+ * register. Since the baudrate divider is 12-bit wide and must be larger than 4,\r
+ * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to\r
+ * 4096. Otherwise this function cannot configure SCUART to work with target baudrate.\r
+ */\r
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate)\r
+{\r
+ uint32_t u32Clk = SCUART_GetClock(sc), u32Div;\r
+\r
+ /* Calculate divider for target baudrate */\r
+ u32Div = (u32Clk + (u32Baudrate >> 1) - 1UL) / u32Baudrate - 1UL;\r
+\r
+ sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; /* Enable smartcard interface and stop bit = 1 */\r
+ sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; /* Enable UART mode, disable parity and 8 bit per character */\r
+ sc->ETUCTL = u32Div;\r
+\r
+ return(u32Clk / (u32Div + 1UL));\r
+}\r
+\r
+/**\r
+ * @brief Read Rx data from Rx FIFO\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] pu8RxBuf The buffer to store receive the data.\r
+ * @param[in] u32ReadBytes Target number of characters to receive\r
+ *\r
+ * @return Actual character number reads to buffer\r
+ *\r
+ * @details The function is used to read data from Rx FIFO.\r
+ *\r
+ * @note This function does not block and return immediately if there's no data available.\r
+ */\r
+uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)\r
+{\r
+ uint32_t u32Count;\r
+\r
+ for(u32Count = 0UL; u32Count < u32ReadBytes; u32Count++)\r
+ {\r
+ if(SCUART_GET_RX_EMPTY(sc)) /* no data available */\r
+ {\r
+ break;\r
+ }\r
+ pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc); /* get data from FIFO */\r
+ }\r
+\r
+ return u32Count;\r
+}\r
+\r
+/**\r
+ * @brief Configure smartcard UART mode line setting\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32Baudrate Target baudrate of smartcard UART mode. If this value is 0, SC UART baudrate will not change.\r
+ * @param[in] u32DataWidth The data length, could be:\r
+ * - \ref SCUART_CHAR_LEN_5\r
+ * - \ref SCUART_CHAR_LEN_6\r
+ * - \ref SCUART_CHAR_LEN_7\r
+ * - \ref SCUART_CHAR_LEN_8\r
+ * @param[in] u32Parity The parity setting, could be:\r
+ * - \ref SCUART_PARITY_NONE\r
+ * - \ref SCUART_PARITY_ODD\r
+ * - \ref SCUART_PARITY_EVEN\r
+ * @param[in] u32StopBits The stop bit length, could be:\r
+ * - \ref SCUART_STOP_BIT_1\r
+ * - \ref SCUART_STOP_BIT_2\r
+ *\r
+ * @return Actual baudrate of smartcard UART mode\r
+ *\r
+ * @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled\r
+ * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1\r
+ * register. Since the baudrate divider is 12-bit wide and must be larger than 4,\r
+ * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to\r
+ * 4096. Otherwise this function cannot configure SCUART to work with target baudrate.\r
+ */\r
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits)\r
+{\r
+ uint32_t u32Clk = SCUART_GetClock(sc), u32Div;\r
+\r
+ if(u32Baudrate == 0UL)\r
+ {\r
+ /* Keep original baudrate setting */\r
+ u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk;\r
+ }\r
+ else\r
+ {\r
+ /* Calculate divider for target baudrate */\r
+ u32Div = ((u32Clk + (u32Baudrate >> 1) - 1UL) / u32Baudrate) - 1UL;\r
+ sc->ETUCTL = u32Div;\r
+ }\r
+\r
+ sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; /* Set stop bit */\r
+ sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk; /* Set character width and parity */\r
+\r
+ return (u32Clk / (u32Div + 1UL));\r
+}\r
+\r
+/**\r
+ * @brief Set receive timeout count\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] u32TOC Rx time-out counter, using baudrate as counter unit. Valid range are 0~0x1FF,\r
+ * set this value to 0 will disable time-out counter.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The time-out counter resets and starts counting whenever the Rx buffer received a\r
+ * new data word. Once the counter decrease to 1 and no new data is received or CPU\r
+ * does not read any data from FIFO, a receiver time-out interrupt will be generated.\r
+ */\r
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC)\r
+{\r
+ sc->RXTOUT = u32TOC;\r
+}\r
+\r
+/**\r
+ * @brief Write data into transmit FIFO to send data out\r
+ *\r
+ * @param[in] sc The pointer of smartcard module.\r
+ * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO.\r
+ * @param[in] u32WriteBytes Number of data to send.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to write data into Tx FIFO to send data out.\r
+ *\r
+ * @note This function blocks until all data write into FIFO.\r
+ */\r
+void SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)\r
+{\r
+ uint32_t u32Count;\r
+\r
+ for(u32Count = 0UL; u32Count != u32WriteBytes; u32Count++)\r
+ {\r
+ /* Wait 'til FIFO not full */\r
+ while(SCUART_GET_TX_FULL(sc))\r
+ {\r
+ ;\r
+ }\r
+ /* Write 1 byte to FIFO */\r
+ sc->DAT = pu8TxBuf[u32Count]; /* Write 1 byte to FIFO */\r
+ }\r
+}\r
+\r
+\r
+/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group SCUART_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file SDH.c\r
+ * @version V1.00\r
+ * @brief M2351 SDH driver source file\r
+ *\r
+ * @note\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "NuMicro.h"\r
+\r
+#if defined (__ICCARM__)\r
+# pragma diag_suppress=Pm073, Pm143 /* Misra C 2004 rule 14.7 */\r
+#endif\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SDH_Driver SDH Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions\r
+ @{\r
+*/\r
+\r
+#define SDH_BLOCK_SIZE 512UL\r
+\r
+/* #define DEBUG_PRINTF printf */\r
+#define DEBUG_PRINTF(...)\r
+\r
+/** @cond HIDDEN_SYMBOLS */\r
+\r
+/* global variables */\r
+/* For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still */\r
+/* calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag */\r
+/* _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error */\r
+uint8_t g_u8R3Flag = 0UL;\r
+uint8_t volatile g_u8SDDataReadyFlag = (uint8_t)FALSE;\r
+\r
+static uint32_t _SDH_uR7_CMD = 0UL;\r
+static uint32_t _SDH_ReferenceClock;\r
+\r
+#if defined ( __ICCARM__ ) /*!< IAR Compiler */\r
+#pragma data_alignment = 4\r
+static uint8_t _SDH_ucSDHCBuffer[512];\r
+#else\r
+static __attribute__((aligned)) uint8_t _SDH_ucSDHCBuffer[512];\r
+#endif\r
+\r
+/* Declare these functions here to avoid MISRA C 2004 rule 8.1 error */\r
+void SDH_CheckRB(SDH_T *sdh);\r
+uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg);\r
+uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t u32TickCount);\r
+uint32_t SDH_Swap32(uint32_t u32Val);\r
+uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t pu32R2ptr[]);\r
+uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg);\r
+void SDH_Set_clock(SDH_T *sdh, uint32_t u32SDClockKhz);\r
+uint32_t SDH_CardDetection(SDH_T *sdh);\r
+uint32_t SDH_Init(SDH_T *sdh);\r
+uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD);\r
+uint32_t SDH_SelectCardType(SDH_T *sdh);\r
+void SDH_Get_SD_info(SDH_T *sdh);\r
+\r
+int SDH_ok = 0;\r
+\r
+SDH_INFO_T SD0;\r
+\r
+void SDH_CheckRB(SDH_T *sdh)\r
+{\r
+ while(1)\r
+ {\r
+ sdh->CTL |= SDH_CTL_CLK8OEN_Msk;\r
+ while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {}\r
+ if(sdh->INTSTS & SDH_INTSTS_DAT0STS_Msk)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg)\r
+{\r
+ SDH_INFO_T *pSD;\r
+ volatile uint32_t u32Status = Successful;\r
+\r
+ /* M2351 is only support SDH0 */\r
+ pSD = &SD0;\r
+\r
+ sdh->CMDARG = u32Arg;\r
+ sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (u32Cmd << 8) | (SDH_CTL_COEN_Msk);\r
+\r
+ while(sdh->CTL & SDH_CTL_COEN_Msk)\r
+ {\r
+ if(pSD->IsCardInsert == (uint32_t)FALSE)\r
+ {\r
+ u32Status = SDH_NO_SD_CARD;\r
+ }\r
+ }\r
+ return u32Status;\r
+}\r
+\r
+\r
+uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t u32TickCount)\r
+{\r
+ SDH_INFO_T *pSD;\r
+\r
+ /* M2351 is only support SDH0 */\r
+ pSD = &SD0;\r
+\r
+ sdh->CMDARG = u32Arg;\r
+ sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (u32Cmd << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk);\r
+\r
+ if(u32TickCount > 0UL)\r
+ {\r
+ while(sdh->CTL & SDH_CTL_RIEN_Msk)\r
+ {\r
+ if(u32TickCount-- == 0UL)\r
+ {\r
+ sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */\r
+ return 2UL;\r
+ }\r
+ if(pSD->IsCardInsert == (uint8_t)FALSE)\r
+ {\r
+ return SDH_NO_SD_CARD;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while(sdh->CTL & SDH_CTL_RIEN_Msk)\r
+ {\r
+ if(pSD->IsCardInsert == (uint8_t)FALSE)\r
+ {\r
+ return SDH_NO_SD_CARD;\r
+ }\r
+ }\r
+ }\r
+\r
+ if(_SDH_uR7_CMD)\r
+ {\r
+ if((sdh->RESP1 & 0xffUL) != 0x55UL)\r
+ {\r
+ if((sdh->RESP0 & 0xfUL) != 0x01UL)\r
+ {\r
+ _SDH_uR7_CMD = 0UL;\r
+ return SDH_CMD8_ERROR;\r
+ }\r
+ }\r
+ }\r
+\r
+ if(!g_u8R3Flag)\r
+ {\r
+ if(sdh->INTSTS & SDH_INTSTS_CRC7_Msk) /* check CRC7 */\r
+ {\r
+ return Successful;\r
+ }\r
+ else\r
+ {\r
+ return SDH_CRC7_ERROR;\r
+ }\r
+ }\r
+ else /* ignore CRC error for R3 case */\r
+ {\r
+ g_u8R3Flag = 0UL;\r
+ sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;\r
+ return Successful;\r
+ }\r
+}\r
+\r
+\r
+uint32_t SDH_Swap32(uint32_t u32Val)\r
+{\r
+ uint32_t u32Buf;\r
+\r
+ u32Buf = u32Val;\r
+ u32Val <<= 24;\r
+ u32Val |= (u32Buf << 8) & 0xff0000UL;\r
+ u32Val |= (u32Buf >> 8) & 0xff00UL;\r
+ u32Val |= (u32Buf >> 24) & 0xffUL;\r
+ return u32Buf;\r
+}\r
+\r
+/* Get 16 bytes CID or CSD */\r
+uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t pu32R2ptr[])\r
+{\r
+ uint32_t i;\r
+ uint32_t au32TmpBuf[5];\r
+ SDH_INFO_T *pSD;\r
+\r
+ /* M2351 is only support SDH0 */\r
+ pSD = &SD0;\r
+\r
+ sdh->CMDARG = u32Arg;\r
+ sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (u32Cmd << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk);\r
+\r
+ while(sdh->CTL & SDH_CTL_R2EN_Msk)\r
+ {\r
+ if(pSD->IsCardInsert == (uint8_t)FALSE)\r
+ {\r
+ return SDH_NO_SD_CARD;\r
+ }\r
+ }\r
+\r
+ if(sdh->INTSTS & SDH_INTSTS_CRC7_Msk)\r
+ {\r
+ for(i = 0UL; i < 5UL; i++)\r
+ {\r
+ au32TmpBuf[i] = SDH_Swap32(sdh->FB[i]);\r
+ }\r
+ for(i = 0UL; i < 4UL; i++)\r
+ {\r
+ pu32R2ptr[i] = ((au32TmpBuf[i] & 0x00ffffffUL) << 8) | ((au32TmpBuf[i + 1UL] & 0xff000000UL) >> 24);\r
+ }\r
+ return Successful;\r
+ }\r
+ else\r
+ {\r
+ return SDH_CRC7_ERROR;\r
+ }\r
+}\r
+\r
+\r
+uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg)\r
+{\r
+ SDH_INFO_T *pSD;\r
+\r
+ /* M2351 is only support SDH0 */\r
+ pSD = &SD0;\r
+\r
+ sdh->CMDARG = u32Arg;\r
+ sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | ((uint32_t)u32Cmd << 8) |\r
+ (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);\r
+\r
+ while(sdh->CTL & SDH_CTL_RIEN_Msk)\r
+ {\r
+ if(pSD->IsCardInsert == (uint32_t)FALSE)\r
+ {\r
+ return SDH_NO_SD_CARD;\r
+ }\r
+ }\r
+\r
+ while(sdh->CTL & SDH_CTL_DIEN_Msk)\r
+ {\r
+ if(pSD->IsCardInsert == (uint32_t)FALSE)\r
+ {\r
+ return SDH_NO_SD_CARD;\r
+ }\r
+ }\r
+\r
+ if(!(sdh->INTSTS & SDH_INTSTS_CRC7_Msk)) /* check CRC7 */\r
+ {\r
+ return SDH_CRC7_ERROR;\r
+ }\r
+\r
+ if(!(sdh->INTSTS & SDH_INTSTS_CRC16_Msk)) /* check CRC16 */\r
+ {\r
+ return SDH_CRC16_ERROR;\r
+ }\r
+\r
+ return Successful;\r
+}\r
+\r
+/* there are 8 bits for divider0, maximum is 256 */\r
+#define SDH_CLK_DIV0_MAX 256UL\r
+\r
+void SDH_Set_clock(SDH_T *sdh, uint32_t u32SDClockKhz)\r
+{\r
+ if(!(__PC() & (1UL << 28)))\r
+ {\r
+ uint32_t u32Rate, u32Div1;\r
+ static uint32_t u32SDClkSrc = 0UL;\r
+\r
+ /* M2351 is only support SDH0 */\r
+ u32SDClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH0SEL_Msk);\r
+ if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_HXT)\r
+ {\r
+ _SDH_ReferenceClock = (CLK_GetHXTFreq() / 1000UL);\r
+ }\r
+ else if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_HIRC)\r
+ {\r
+ _SDH_ReferenceClock = (__HIRC / 1000UL);\r
+ }\r
+ else if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_PLL)\r
+ {\r
+ _SDH_ReferenceClock = (CLK_GetPLLClockFreq() / 1000UL);\r
+ }\r
+ else if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_HCLK)\r
+ {\r
+ _SDH_ReferenceClock = (CLK_GetHCLKFreq() / 1000UL);\r
+ }\r
+\r
+ if(u32SDClockKhz >= 50000UL)\r
+ {\r
+ u32SDClockKhz = 50000UL;\r
+ }\r
+ u32Rate = _SDH_ReferenceClock / u32SDClockKhz;\r
+\r
+ /* choose slower clock if system clock cannot divisible by wanted clock */\r
+ if(_SDH_ReferenceClock % u32SDClockKhz != 0UL)\r
+ {\r
+ u32Rate++;\r
+ }\r
+\r
+ if(u32Rate >= SDH_CLK_DIV0_MAX)\r
+ {\r
+ u32Rate = SDH_CLK_DIV0_MAX;\r
+ }\r
+\r
+ /* --- calculate the second divider CLKDIV0[SDHOST_N] */\r
+ if(u32Rate == 0UL)\r
+ {\r
+ u32Div1 = 0UL;\r
+ }\r
+ else\r
+ {\r
+ u32Div1 = ((u32Rate - 1UL) & 0xFFUL);\r
+ }\r
+\r
+ /* --- setup register */\r
+ /* M2351 is only support SDH0 */\r
+ CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk;\r
+ CLK->CLKDIV0 |= (u32Div1 << CLK_CLKDIV0_SDH0DIV_Pos);\r
+ }\r
+}\r
+\r
+uint32_t SDH_CardDetection(SDH_T *sdh)\r
+{\r
+ uint32_t i, u32Status = (uint32_t)TRUE;\r
+ SDH_INFO_T *pSD;\r
+\r
+ /* M2351 is only support SDH0 */\r
+ pSD = &SD0;\r
+\r
+ if(sdh->INTEN & SDH_INTEN_CDSRC_Msk) /* Card detect pin from GPIO */\r
+ {\r
+ if(sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) /* Card remove */\r
+ {\r
+ pSD->IsCardInsert = (uint8_t)FALSE;\r
+ u32Status = (uint32_t)FALSE;\r
+ }\r
+ else\r
+ {\r
+ pSD->IsCardInsert = (uint8_t)TRUE;\r
+ }\r
+ }\r
+ else if(!(sdh->INTEN & SDH_INTEN_CDSRC_Msk))\r
+ {\r
+ sdh->CTL |= SDH_CTL_CLKKEEP_Msk;\r
+ for(i = 0UL; i < 5000UL; i++) {}\r
+\r
+ if(sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) /* Card insert */\r
+ {\r
+ pSD->IsCardInsert = (uint8_t)TRUE;\r
+ }\r
+ else\r
+ {\r
+ pSD->IsCardInsert = (uint8_t)FALSE;\r
+ u32Status = (uint32_t)FALSE;\r
+ }\r
+\r
+ sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk;\r
+ }\r
+\r
+ return u32Status;\r
+}\r
+\r
+\r
+/* Initial */\r
+uint32_t SDH_Init(SDH_T *sdh)\r
+{\r
+ uint32_t volatile i, u32Status;\r
+ uint32_t u32Resp;\r
+ uint32_t au32CIDBuffer[4];\r
+ uint32_t volatile u32CmdTimeOut;\r
+ SDH_INFO_T *pSD;\r
+\r
+ /* M2351 is only support SDH0 */\r
+ pSD = &SD0;\r
+\r
+ /* set the clock to 300KHz */\r
+ SDH_Set_clock(sdh, 300UL);\r
+\r
+ /* power ON 74 clock */\r
+ sdh->CTL |= SDH_CTL_CLK74OEN_Msk;\r
+\r
+ while(sdh->CTL & SDH_CTL_CLK74OEN_Msk)\r
+ {\r
+ if(pSD->IsCardInsert == (uint8_t)FALSE)\r
+ {\r
+ return SDH_NO_SD_CARD;\r
+ }\r
+ }\r
+\r
+ SDH_SDCommand(sdh, 0UL, 0UL); /* reset all cards */\r
+ for(i = 0x1000UL; i > 0UL; i--) {}\r
+\r
+ /* initial SDHC */\r
+ _SDH_uR7_CMD = 1UL;\r
+ u32CmdTimeOut = 0xFFFFFUL;\r
+\r
+ i = SDH_SDCmdAndRsp(sdh, 8UL, 0x00000155UL, u32CmdTimeOut);\r
+ if(i == Successful)\r
+ {\r
+ /* SD 2.0 */\r
+ SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut);\r
+ g_u8R3Flag = 1UL;\r
+ SDH_SDCmdAndRsp(sdh, 41UL, 0x40ff8000UL, u32CmdTimeOut); /* 2.7v-3.6v */\r
+ u32Resp = sdh->RESP0;\r
+\r
+ while(!(u32Resp & 0x00800000UL)) /* check if card is ready */\r
+ {\r
+ SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut);\r
+ g_u8R3Flag = 1UL;\r
+ SDH_SDCmdAndRsp(sdh, 41UL, 0x40ff8000UL, u32CmdTimeOut); /* 3.0v-3.4v */\r
+ u32Resp = sdh->RESP0;\r
+ }\r
+ if(u32Resp & 0x00400000UL)\r
+ {\r
+ pSD->CardType = SDH_TYPE_SD_HIGH;\r
+ }\r
+ else\r
+ {\r
+ pSD->CardType = SDH_TYPE_SD_LOW;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* SD 1.1 */\r
+ SDH_SDCommand(sdh, 0UL, 0UL); /* reset all cards */\r
+ for(i = 0x100UL; i > 0UL; i--) {}\r
+\r
+ i = SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut);\r
+ if(i == 2UL) /* MMC memory */\r
+ {\r
+ SDH_SDCommand(sdh, 0UL, 0UL); /* reset */\r
+ for(i = 0x100UL; i > 0UL; i--) {}\r
+\r
+ g_u8R3Flag = 1UL;\r
+\r
+ if(SDH_SDCmdAndRsp(sdh, 1UL, 0x40ff8000UL, u32CmdTimeOut) != 2UL) /* eMMC memory */\r
+ {\r
+ u32Resp = sdh->RESP0;\r
+ while(!(u32Resp & 0x00800000UL)) /* check if card is ready */\r
+ {\r
+ g_u8R3Flag = 1UL;\r
+\r
+ SDH_SDCmdAndRsp(sdh, 1UL, 0x40ff8000UL, u32CmdTimeOut); /* high voltage */\r
+ u32Resp = sdh->RESP0;\r
+ }\r
+\r
+ if(u32Resp & 0x00400000UL)\r
+ {\r
+ pSD->CardType = SDH_TYPE_EMMC;\r
+ }\r
+ else\r
+ {\r
+ pSD->CardType = SDH_TYPE_MMC;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ pSD->CardType = SDH_TYPE_UNKNOWN;\r
+ return SDH_ERR_DEVICE;\r
+ }\r
+ }\r
+ else if(i == 0UL) /* SD Memory */\r
+ {\r
+ g_u8R3Flag = 1UL;\r
+ SDH_SDCmdAndRsp(sdh, 41UL, 0x00ff8000UL, u32CmdTimeOut); /* 3.0v-3.4v */\r
+ u32Resp = sdh->RESP0;\r
+ while(!(u32Resp & 0x00800000UL)) /* check if card is ready */\r
+ {\r
+ SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut);\r
+ g_u8R3Flag = 1UL;\r
+ SDH_SDCmdAndRsp(sdh, 41UL, 0x00ff8000UL, u32CmdTimeOut); /* 3.0v-3.4v */\r
+ u32Resp = sdh->RESP0;\r
+ }\r
+ pSD->CardType = SDH_TYPE_SD_LOW;\r
+ }\r
+ else\r
+ {\r
+ pSD->CardType = SDH_TYPE_UNKNOWN;\r
+ return SDH_INIT_ERROR;\r
+ }\r
+ }\r
+\r
+ /* CMD2, CMD3 */\r
+ if(pSD->CardType != SDH_TYPE_UNKNOWN)\r
+ {\r
+ SDH_SDCmdAndRsp2(sdh, 2UL, 0x00UL, au32CIDBuffer);\r
+ if((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))\r
+ {\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 3UL, 0x10000UL, 0UL)) != Successful) /* set RCA */\r
+ {\r
+ return u32Status;\r
+ }\r
+ pSD->RCA = 0x10000UL;\r
+ }\r
+ else\r
+ {\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 3UL, 0x00UL, 0UL)) != Successful) /* get RCA */\r
+ {\r
+ return u32Status;\r
+ }\r
+ else\r
+ {\r
+ pSD->RCA = (sdh->RESP0 << 8) & 0xffff0000UL;\r
+ }\r
+ }\r
+ }\r
+\r
+ return Successful;\r
+}\r
+\r
+\r
+uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD)\r
+{\r
+ uint32_t volatile u32Status = 0UL;\r
+ uint16_t u16CurrentComsumption, u16BusyStatus0;\r
+\r
+ sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; /* set DMA transfer starting address */\r
+ sdh->BLEN = 63UL; /* 512 bit */\r
+\r
+ if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 6UL, 0x00ffff01UL)) != Successful)\r
+ {\r
+ return Fail;\r
+ }\r
+\r
+ u16CurrentComsumption = (uint16_t)_SDH_ucSDHCBuffer[0] << 8;\r
+ u16CurrentComsumption |= (uint16_t)_SDH_ucSDHCBuffer[1];\r
+ if(!u16CurrentComsumption)\r
+ {\r
+ return Fail;\r
+ }\r
+\r
+ u16BusyStatus0 = (uint16_t)_SDH_ucSDHCBuffer[28] << 8;\r
+ u16BusyStatus0 |= (uint16_t)_SDH_ucSDHCBuffer[29];\r
+\r
+ if(!u16BusyStatus0) /* function ready */\r
+ {\r
+ sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; /* set DMA transfer starting address */\r
+ sdh->BLEN = 63UL; /* 512 bit */\r
+\r
+ if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 6UL, 0x80ffff01UL)) != Successful)\r
+ {\r
+ return Fail;\r
+ }\r
+\r
+ /* function change timing: 8 clocks */\r
+ sdh->CTL |= SDH_CTL_CLK8OEN_Msk;\r
+ while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {}\r
+\r
+ u16CurrentComsumption = (uint16_t)_SDH_ucSDHCBuffer[0] << 8;\r
+ u16CurrentComsumption |= (uint16_t)_SDH_ucSDHCBuffer[1];\r
+ if(!u16CurrentComsumption)\r
+ {\r
+ return Fail;\r
+ }\r
+\r
+ return Successful;\r
+ }\r
+ else\r
+ {\r
+ return Fail;\r
+ }\r
+}\r
+\r
+\r
+uint32_t SDH_SelectCardType(SDH_T *sdh)\r
+{\r
+ uint32_t volatile u32Status = 0UL;\r
+ uint32_t u32Param;\r
+ SDH_INFO_T *pSD;\r
+\r
+ /* M2351 is only support SDH0 */\r
+ pSD = &SD0;\r
+\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL)) != Successful)\r
+ {\r
+ return u32Status;\r
+ }\r
+\r
+ SDH_CheckRB(sdh);\r
+\r
+ /* if SD card set 4bit */\r
+ if(pSD->CardType == SDH_TYPE_SD_HIGH)\r
+ {\r
+ sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; /* set DMA transfer starting address */\r
+ sdh->BLEN = 0x07UL; /* 64 bit */\r
+\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful)\r
+ {\r
+ return u32Status;\r
+ }\r
+\r
+ sdh->DMACTL |= 0x2;\r
+ while(sdh->DMACTL & 0x2) {};\r
+\r
+ if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 51UL, 0x00UL)) != Successful)\r
+ {\r
+ return u32Status;\r
+ }\r
+\r
+ if((_SDH_ucSDHCBuffer[0] & 0xfUL) == 0xfUL)\r
+ {\r
+ u32Status = SDH_SwitchToHighSpeed(sdh, pSD);\r
+ if(u32Status == Successful)\r
+ {\r
+ /* divider */\r
+ SDH_Set_clock(sdh, SDHC_FREQ);\r
+ }\r
+ }\r
+\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful)\r
+ {\r
+ return u32Status;\r
+ }\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 6UL, 0x02UL, 0UL)) != Successful) /* set bus width */\r
+ {\r
+ return u32Status;\r
+ }\r
+\r
+ sdh->CTL |= SDH_CTL_DBW_Msk;\r
+ }\r
+ else if(pSD->CardType == SDH_TYPE_SD_LOW)\r
+ {\r
+ sdh->DMASA = (uint32_t) _SDH_ucSDHCBuffer; /* set DMA transfer starting address */\r
+ sdh->BLEN = 0x07UL; /* 64 bit */\r
+\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful)\r
+ {\r
+ return u32Status;\r
+ }\r
+ if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 51UL, 0x00UL)) != Successful)\r
+ {\r
+ return u32Status;\r
+ }\r
+\r
+ /* set data bus width. ACMD6 for SD card, SDCR_DBW for host. */\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful)\r
+ {\r
+ return u32Status;\r
+ }\r
+\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 6UL, 0x02UL, 0UL)) != Successful) /* set bus width */\r
+ {\r
+ return u32Status;\r
+ }\r
+\r
+ sdh->CTL |= SDH_CTL_DBW_Msk;\r
+ }\r
+ else if((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))\r
+ {\r
+\r
+ if(pSD->CardType == SDH_TYPE_MMC)\r
+ {\r
+ sdh->CTL &= ~SDH_CTL_DBW_Msk;\r
+ }\r
+\r
+ /* --- sent CMD6 to MMC card to set bus width to 4 bits mode */\r
+ /* set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode) */\r
+ u32Param = (3UL << 24) | (183UL << 16) | (1UL << 8);\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 6UL, u32Param, 0UL)) != Successful)\r
+ {\r
+ return u32Status;\r
+ }\r
+ SDH_CheckRB(sdh);\r
+\r
+ sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */\r
+ }\r
+\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 16UL, SDH_BLOCK_SIZE, 0UL)) != Successful) /* set block length */\r
+ {\r
+ return u32Status;\r
+ }\r
+ sdh->BLEN = SDH_BLOCK_SIZE - 1UL; /* set the block size */\r
+\r
+ SDH_SDCommand(sdh, 7UL, 0UL);\r
+ sdh->CTL |= SDH_CTL_CLK8OEN_Msk;\r
+ while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {}\r
+\r
+ sdh->INTEN |= SDH_INTEN_BLKDIEN_Msk;\r
+\r
+ return Successful;\r
+}\r
+\r
+void SDH_Get_SD_info(SDH_T *sdh)\r
+{\r
+ uint32_t u32RLen, u32CSize, u32Mult, u32Size;\r
+ uint32_t au32Buffer[4];\r
+ SDH_INFO_T *pSD;\r
+\r
+ /* M2351 is only support SDH0 */\r
+ pSD = &SD0;\r
+\r
+ SDH_SDCmdAndRsp2(sdh, 9UL, pSD->RCA, au32Buffer);\r
+\r
+ if((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))\r
+ {\r
+ /* for MMC/eMMC card */\r
+ if((au32Buffer[0] & 0xc0000000UL) == 0xc0000000UL)\r
+ {\r
+ /* CSD_STRUCTURE [127:126] is 3 */\r
+ /* CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB */\r
+ SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL);\r
+\r
+ sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; /* set DMA transfer starting address */\r
+ sdh->BLEN = 511UL; /* read 512 bytes for EXT_CSD */\r
+\r
+ if(SDH_SDCmdAndRspDataIn(sdh, 8UL, 0x00UL) != Successful)\r
+ {\r
+ return;\r
+ }\r
+\r
+ SDH_SDCommand(sdh, 7UL, 0UL);\r
+ sdh->CTL |= SDH_CTL_CLK8OEN_Msk;\r
+ while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {}\r
+\r
+ pSD->totalSectorN = (uint32_t)_SDH_ucSDHCBuffer[215] << 24;\r
+ pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[214] << 16;\r
+ pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[213] << 8;\r
+ pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[212];\r
+ pSD->diskSize = pSD->totalSectorN / 2UL;\r
+ }\r
+ else\r
+ {\r
+ /* CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB */\r
+ u32RLen = (au32Buffer[1] & 0x000f0000UL) >> 16;\r
+ u32CSize = ((au32Buffer[1] & 0x000003ffUL) << 2) | ((au32Buffer[2] & 0xc0000000UL) >> 30);\r
+ u32Mult = (au32Buffer[2] & 0x00038000UL) >> 15;\r
+ u32Size = (u32CSize + 1UL) * (1UL << (u32Mult + 2UL)) * (1UL << u32RLen);\r
+\r
+ pSD->diskSize = u32Size / 1024UL;\r
+ pSD->totalSectorN = u32Size / 512UL;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(au32Buffer[0] & 0xc0000000UL)\r
+ {\r
+ u32CSize = ((au32Buffer[1] & 0x0000003fUL) << 16) | ((au32Buffer[2] & 0xffff0000UL) >> 16);\r
+ u32Size = (u32CSize + 1UL) * 512UL; /* Kbytes */\r
+\r
+ pSD->diskSize = u32Size;\r
+ pSD->totalSectorN = u32Size << 1;\r
+ }\r
+ else\r
+ {\r
+ u32RLen = (au32Buffer[1] & 0x000f0000UL) >> 16;\r
+ u32CSize = ((au32Buffer[1] & 0x000003ffUL) << 2) | ((au32Buffer[2] & 0xc0000000UL) >> 30);\r
+ u32Mult = (au32Buffer[2] & 0x00038000UL) >> 15;\r
+ u32Size = (u32CSize + 1UL) * (1UL << (u32Mult + 2UL)) * (1UL << u32RLen);\r
+\r
+ pSD->diskSize = u32Size / 1024UL;\r
+ pSD->totalSectorN = u32Size / 512UL;\r
+ }\r
+ }\r
+ pSD->sectorSize = (int)512UL;\r
+}\r
+\r
+/** @endcond HIDDEN_SYMBOLS */\r
+\r
+\r
+/**\r
+ * @brief This function use to reset SD function and select card detection source and pin.\r
+ *\r
+ * @param[in] sdh The pointer of the specified SDH module.\r
+ * @param[in] u32CardDetSrc Select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3)\r
+ *\r
+ * @return None\r
+ */\r
+void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc)\r
+{\r
+ /* enable DMAC */\r
+ sdh->DMACTL = SDH_DMACTL_DMARST_Msk;\r
+ while(sdh->DMACTL & SDH_DMACTL_DMARST_Msk) {}\r
+\r
+ sdh->DMACTL = SDH_DMACTL_DMAEN_Msk;\r
+\r
+ /* Reset FMI */\r
+ sdh->GCTL = SDH_GCTL_GCTLRST_Msk | SDH_GCTL_SDEN_Msk; /* Start reset FMI controller. */\r
+ while(sdh->GCTL & SDH_GCTL_GCTLRST_Msk) {}\r
+\r
+ memset(&SD0, 0, sizeof(SDH_INFO_T));\r
+\r
+ /* enable SD */\r
+ sdh->GCTL = SDH_GCTL_SDEN_Msk;\r
+\r
+ if(u32CardDetSrc & CardDetect_From_DAT3)\r
+ {\r
+ sdh->INTEN &= ~SDH_INTEN_CDSRC_Msk;\r
+ }\r
+ else\r
+ {\r
+ sdh->INTEN |= SDH_INTEN_CDSRC_Msk;\r
+ }\r
+ sdh->INTEN |= SDH_INTEN_CDIEN_Msk;\r
+\r
+ sdh->CTL |= SDH_CTL_CTLRST_Msk; /* SD software reset */\r
+ while(sdh->CTL & SDH_CTL_CTLRST_Msk) {}\r
+\r
+}\r
+\r
+/**\r
+ * @brief This function use to initial SD card.\r
+ *\r
+ * @param[in] sdh The pointer of the specified SDH module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to initial SD card.\r
+ * SD initial state needs 400KHz clock output, driver will use HIRC for SD initial clock source.\r
+ * And then switch back to the user's setting.\r
+ */\r
+uint32_t SDH_Probe(SDH_T *sdh)\r
+{\r
+ uint32_t u32Val;\r
+\r
+ /* Disable FMI/SD host interrupt */\r
+ sdh->GINTEN = 0UL;\r
+\r
+ sdh->CTL &= ~SDH_CTL_SDNWR_Msk;\r
+ sdh->CTL |= 0x09UL << SDH_CTL_SDNWR_Pos; /* set SDNWR = 9 */\r
+ sdh->CTL &= ~SDH_CTL_BLKCNT_Msk;\r
+ sdh->CTL |= 0x01UL << SDH_CTL_BLKCNT_Pos; /* set BLKCNT = 1 */\r
+ sdh->CTL &= ~SDH_CTL_DBW_Msk; /* SD 1-bit data bus */\r
+\r
+ if(!(SDH_CardDetection(sdh)))\r
+ {\r
+ return SDH_NO_SD_CARD;\r
+ }\r
+\r
+ if((u32Val = SDH_Init(sdh)) != 0UL)\r
+ {\r
+ return u32Val;\r
+ }\r
+\r
+ /* divider */\r
+ if(SD0.CardType == SDH_TYPE_MMC)\r
+ {\r
+ SDH_Set_clock(sdh, MMC_FREQ);\r
+ }\r
+ else\r
+ {\r
+ SDH_Set_clock(sdh, SD_FREQ);\r
+ }\r
+ SDH_Get_SD_info(sdh);\r
+\r
+ if((u32Val = SDH_SelectCardType(sdh)) != 0UL)\r
+ {\r
+ return u32Val;\r
+ }\r
+\r
+ SDH_ok = 1;\r
+ return 0UL;\r
+}\r
+\r
+/**\r
+ * @brief This function use to read data from SD card.\r
+ *\r
+ * @param[in] sdh The pointer of the specified SDH module.\r
+ * @param[out] pu8BufAddr The buffer to receive the data from SD card.\r
+ * @param[in] u32StartSec The start read sector address.\r
+ * @param[in] u32SecCount The the read sector number of data\r
+ *\r
+ * @return None\r
+ */\r
+uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)\r
+{\r
+ uint32_t volatile u32IsSendCmd = (uint32_t)FALSE, u32Buf;\r
+ uint32_t volatile u32Reg;\r
+ uint32_t volatile i, u32Loop, u32Status;\r
+ uint32_t u32BlkSize = SDH_BLOCK_SIZE;\r
+\r
+ SDH_INFO_T *pSD;\r
+\r
+ /* M2351 is only support SDH0 */\r
+ pSD = &SD0;\r
+\r
+ /* --- check input parameters */\r
+ if(u32SecCount == 0UL)\r
+ {\r
+ return SDH_SELECT_ERROR;\r
+ }\r
+\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL)) != Successful)\r
+ {\r
+ return u32Status;\r
+ }\r
+ SDH_CheckRB(sdh);\r
+\r
+ sdh->BLEN = u32BlkSize - 1UL; /* the actual byte count is equal to (SDBLEN+1) */\r
+\r
+ if((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC))\r
+ {\r
+ sdh->CMDARG = u32StartSec;\r
+ }\r
+ else\r
+ {\r
+ sdh->CMDARG = u32StartSec * u32BlkSize;\r
+ }\r
+\r
+ sdh->DMASA = (uint32_t)pu8BufAddr;\r
+\r
+ u32Loop = u32SecCount / 255UL;\r
+ while(u32Loop > 0UL)\r
+ {\r
+ g_u8SDDataReadyFlag = (uint8_t)FALSE;\r
+ u32Reg = sdh->CTL & ~SDH_CTL_CMDCODE_Msk;\r
+ u32Reg = u32Reg | 0xff0000UL; /* set BLK_CNT to 255 */\r
+ if(u32IsSendCmd == (uint32_t)FALSE)\r
+ {\r
+ sdh->CTL = u32Reg | (18UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);\r
+ u32IsSendCmd = (uint32_t)TRUE;\r
+ }\r
+ else\r
+ {\r
+ sdh->CTL = u32Reg | SDH_CTL_DIEN_Msk;\r
+ }\r
+\r
+ while(!g_u8SDDataReadyFlag)\r
+ {\r
+ if(g_u8SDDataReadyFlag)\r
+ {\r
+ break;\r
+ }\r
+ if(pSD->IsCardInsert == (uint8_t)FALSE)\r
+ {\r
+ return SDH_NO_SD_CARD;\r
+ }\r
+ }\r
+\r
+ if(!(sdh->INTSTS & SDH_INTSTS_CRC7_Msk)) /* check CRC7 */\r
+ {\r
+ return SDH_CRC7_ERROR;\r
+ }\r
+\r
+ if(!(sdh->INTSTS & SDH_INTSTS_CRC16_Msk)) /* check CRC16 */\r
+ {\r
+ return SDH_CRC16_ERROR;\r
+ }\r
+ u32Loop--;\r
+ }\r
+\r
+ u32Loop = u32SecCount % 255UL;\r
+ if(u32Loop != 0UL)\r
+ {\r
+ uint32_t u32RegTmp;\r
+ g_u8SDDataReadyFlag = (uint8_t)FALSE;\r
+ u32Reg = sdh->CTL & (~SDH_CTL_CMDCODE_Msk);\r
+ u32Reg = u32Reg & (~SDH_CTL_BLKCNT_Msk);\r
+ u32RegTmp = (u32Loop << 16);\r
+ u32Reg |= u32RegTmp; /* setup SDCR_BLKCNT */\r
+\r
+ if(u32IsSendCmd == (uint32_t)FALSE)\r
+ {\r
+ sdh->CTL = u32Reg | (18UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);\r
+ u32IsSendCmd = (uint32_t)TRUE;\r
+ }\r
+ else\r
+ {\r
+ sdh->CTL = u32Reg | SDH_CTL_DIEN_Msk;\r
+ }\r
+\r
+ while(!g_u8SDDataReadyFlag)\r
+ {\r
+ if(pSD->IsCardInsert == (uint8_t)FALSE)\r
+ {\r
+ return SDH_NO_SD_CARD;\r
+ }\r
+ }\r
+\r
+ if(!(sdh->INTSTS & SDH_INTSTS_CRC7_Msk)) /* check CRC7 */\r
+ {\r
+ return SDH_CRC7_ERROR;\r
+ }\r
+\r
+ if(!(sdh->INTSTS & SDH_INTSTS_CRC16_Msk)) /* check CRC16 */\r
+ {\r
+ return SDH_CRC16_ERROR;\r
+ }\r
+ }\r
+\r
+ if(SDH_SDCmdAndRsp(sdh, 12UL, 0UL, 0UL)) /* stop command */\r
+ {\r
+ return SDH_CRC7_ERROR;\r
+ }\r
+ SDH_CheckRB(sdh);\r
+\r
+ SDH_SDCommand(sdh, 7UL, 0UL);\r
+ sdh->CTL |= SDH_CTL_CLK8OEN_Msk;\r
+ while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {}\r
+\r
+ return Successful;\r
+}\r
+\r
+/**\r
+ * @brief This function use to write data to SD card.\r
+ *\r
+ * @param[in] sdh The pointer of the specified SDH module.\r
+ * @param[in] pu8BufAddr The buffer to send the data to SD card.\r
+ * @param[in] u32StartSec The start write sector address.\r
+ * @param[in] u32SecCount The the write sector number of data.\r
+ *\r
+ * @return \ref SDH_SELECT_ERROR : u32SecCount is zero. \n\r
+ * \ref SDH_NO_SD_CARD : SD card be removed. \n\r
+ * \ref SDH_CRC_ERROR : CRC error happen. \n\r
+ * \ref SDH_CRC7_ERROR : CRC7 error happen. \n\r
+ * \ref Successful : Write data to SD card success.\r
+ */\r
+uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)\r
+{\r
+ uint32_t volatile u32IsSendCmd = (uint32_t)FALSE;\r
+ uint32_t volatile u32Reg;\r
+ uint32_t volatile i, u32Loop, u32Status;\r
+\r
+ SDH_INFO_T *pSD;\r
+\r
+ /* M2351 is only support SDH0 */\r
+ pSD = &SD0;\r
+\r
+ /* --- check input parameters */\r
+ if(u32SecCount == 0UL)\r
+ {\r
+ return SDH_SELECT_ERROR;\r
+ }\r
+\r
+ if((u32Status = SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL)) != Successful)\r
+ {\r
+ return u32Status;\r
+ }\r
+\r
+ SDH_CheckRB(sdh);\r
+\r
+ /* According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n. */\r
+ sdh->BLEN = SDH_BLOCK_SIZE - 1UL; /* set the block size */\r
+\r
+ if((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC))\r
+ {\r
+ sdh->CMDARG = u32StartSec;\r
+ }\r
+ else\r
+ {\r
+ sdh->CMDARG = u32StartSec * SDH_BLOCK_SIZE; /* set start address for SD CMD */\r
+ }\r
+\r
+ sdh->DMASA = (uint32_t)pu8BufAddr;\r
+ u32Loop = u32SecCount / 255UL; /* the maximum block count is 0xFF=255 for register SDCR[BLK_CNT] */\r
+ while(u32Loop > 0UL)\r
+ {\r
+ g_u8SDDataReadyFlag = (uint8_t)FALSE;\r
+ u32Reg = sdh->CTL & 0xff00c080UL;\r
+ u32Reg = u32Reg | 0xff0000UL; /* set BLK_CNT to 0xFF=255 */\r
+ if(!u32IsSendCmd)\r
+ {\r
+ sdh->CTL = u32Reg | (25UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);\r
+ u32IsSendCmd = (uint32_t)TRUE;\r
+ }\r
+ else\r
+ {\r
+ sdh->CTL = u32Reg | SDH_CTL_DOEN_Msk;\r
+ }\r
+\r
+ while(!g_u8SDDataReadyFlag)\r
+ {\r
+ if(pSD->IsCardInsert == (uint8_t)FALSE)\r
+ {\r
+ return SDH_NO_SD_CARD;\r
+ }\r
+ }\r
+\r
+ if((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0UL) /* check CRC */\r
+ {\r
+ sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;\r
+ return SDH_CRC_ERROR;\r
+ }\r
+ u32Loop--;\r
+ }\r
+\r
+ u32Loop = u32SecCount % 255UL;\r
+ if(u32Loop != 0UL)\r
+ {\r
+ uint32_t u32RegTmp;\r
+ g_u8SDDataReadyFlag = (uint8_t)FALSE;\r
+ u32RegTmp = (u32Loop << 16);\r
+ u32Reg = (sdh->CTL & 0xff00c080UL) | u32RegTmp;\r
+ if(!u32IsSendCmd)\r
+ {\r
+ sdh->CTL = u32Reg | (25UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);\r
+ u32IsSendCmd = (uint32_t)TRUE;\r
+ }\r
+ else\r
+ {\r
+ sdh->CTL = u32Reg | SDH_CTL_DOEN_Msk;\r
+ }\r
+\r
+ while(!g_u8SDDataReadyFlag)\r
+ {\r
+ if(pSD->IsCardInsert == (uint8_t)FALSE)\r
+ {\r
+ return SDH_NO_SD_CARD;\r
+ }\r
+ }\r
+\r
+ if((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0UL) /* check CRC */\r
+ {\r
+ sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;\r
+ return SDH_CRC_ERROR;\r
+ }\r
+ }\r
+ sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;\r
+\r
+ if(SDH_SDCmdAndRsp(sdh, 12UL, 0UL, 0UL)) /* stop command */\r
+ {\r
+ return SDH_CRC7_ERROR;\r
+ }\r
+ SDH_CheckRB(sdh);\r
+\r
+ SDH_SDCommand(sdh, 7UL, 0UL);\r
+ sdh->CTL |= SDH_CTL_CLK8OEN_Msk;\r
+ while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {}\r
+\r
+ return Successful;\r
+}\r
+\r
+\r
+/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group SDH_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file spi.c\r
+ * @version V3.00\r
+ * @brief M2351 series SPI driver source file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SPI_Driver SPI Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions\r
+ @{\r
+*/\r
+\r
+static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s);\r
+\r
+/**\r
+ * @brief This function make SPI module be ready to transfer.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER)\r
+ * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3)\r
+ * @param[in] u32DataWidth Decides the data width of a SPI transaction.\r
+ * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz.\r
+ * @return Actual frequency of SPI peripheral clock.\r
+ * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic\r
+ * slave selection function is disabled.\r
+ * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0.\r
+ * The actual clock rate may be different from the target SPI clock rate.\r
+ * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the\r
+ * actual SPI clock rate will be 6MHz.\r
+ * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.\r
+ * @note If u32BusClock >= system clock frequency for Secure, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.\r
+ * @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of\r
+ * SPI bus clock cannot be faster than the system clock rate. User should set up carefully.\r
+ * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.\r
+ * @note In slave mode for Secure, the SPI peripheral clock rate will equal to APB clock rate.\r
+ * @note In slave mode for Non-Secure, the SPI peripheral clock rate will equal to the clock rate set in secure mode.\r
+ */\r
+uint32_t SPI_Open(SPI_T *spi,\r
+ uint32_t u32MasterSlave,\r
+ uint32_t u32SPIMode,\r
+ uint32_t u32DataWidth,\r
+ uint32_t u32BusClock)\r
+{\r
+ uint32_t u32ClkSrc = 0UL, u32Div, u32HCLKFreq, u32PCLK0Freq, u32PCLK1Freq, u32RetValue = 0UL;\r
+\r
+ /* Disable I2S mode */\r
+ spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;\r
+\r
+ if(u32DataWidth == 32UL)\r
+ {\r
+ u32DataWidth = 0UL;\r
+ }\r
+\r
+ /* Get system clock frequency */\r
+ u32HCLKFreq = CLK_GetHCLKFreq();\r
+ /* Get APB0 clock frequency */\r
+ u32PCLK0Freq = CLK_GetPCLK0Freq();\r
+ /* Get APB1 clock frequency */\r
+ u32PCLK1Freq = CLK_GetPCLK1Freq();\r
+\r
+ if(u32MasterSlave == SPI_MASTER)\r
+ {\r
+ /* Default setting: slave selection signal is active low; disable automatic slave selection function. */\r
+ spi->SSCTL = SPI_SS_ACTIVE_LOW;\r
+\r
+ /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */\r
+ spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;\r
+\r
+ if(u32BusClock >= u32HCLKFreq)\r
+ {\r
+ if(!(__PC() & (1UL << 28UL)))\r
+ {\r
+ /* Select PCLK as the clock source of SPI */\r
+ if((spi == SPI0) || (spi == SPI0_NS))\r
+ {\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;\r
+ }\r
+ else if((spi == SPI1) || (spi == SPI1_NS))\r
+ {\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0;\r
+ }\r
+ else if((spi == SPI2) || (spi == SPI2_NS))\r
+ {\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1;\r
+ }\r
+ else\r
+ {\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Check clock source of SPI */\r
+ if((spi == SPI0) || (spi == SPI0_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT)\r
+ {\r
+ u32ClkSrc = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL)\r
+ {\r
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1)\r
+ {\r
+ u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */\r
+ }\r
+ else\r
+ {\r
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else if((spi == SPI1) || (spi == SPI1_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT)\r
+ {\r
+ u32ClkSrc = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL)\r
+ {\r
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0)\r
+ {\r
+ u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */\r
+ }\r
+ else\r
+ {\r
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else if((spi == SPI2) || (spi == SPI2_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT)\r
+ {\r
+ u32ClkSrc = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL)\r
+ {\r
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1)\r
+ {\r
+ u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */\r
+ }\r
+ else\r
+ {\r
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT)\r
+ {\r
+ u32ClkSrc = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL)\r
+ {\r
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0)\r
+ {\r
+ u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */\r
+ }\r
+ else\r
+ {\r
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+\r
+ if(u32BusClock >= u32HCLKFreq)\r
+ {\r
+ /* Set DIVIDER = 0 */\r
+ spi->CLKDIV = 0UL;\r
+ /* Return master peripheral clock rate */\r
+ u32RetValue = u32ClkSrc;\r
+ }\r
+ else if(u32BusClock >= u32ClkSrc)\r
+ {\r
+ /* Set DIVIDER = 0 */\r
+ spi->CLKDIV = 0UL;\r
+ /* Return master peripheral clock rate */\r
+ u32RetValue = u32ClkSrc;\r
+ }\r
+ else if(u32BusClock == 0UL)\r
+ {\r
+ /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */\r
+ spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;\r
+ /* Return master peripheral clock rate */\r
+ u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));\r
+ }\r
+ else\r
+ {\r
+ u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */\r
+ if(u32Div > 0x1FFUL)\r
+ {\r
+ u32Div = 0x1FFUL;\r
+ spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;\r
+ /* Return master peripheral clock rate */\r
+ u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));\r
+ }\r
+ else\r
+ {\r
+ spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);\r
+ /* Return master peripheral clock rate */\r
+ u32RetValue = (u32ClkSrc / (u32Div + 1UL));\r
+ }\r
+ }\r
+ }\r
+ else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */\r
+ {\r
+ /* Default setting: slave selection signal is low level active. */\r
+ spi->SSCTL = SPI_SS_ACTIVE_LOW;\r
+\r
+ /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */\r
+ spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;\r
+\r
+ /* Set DIVIDER = 0 */\r
+ spi->CLKDIV = 0UL;\r
+\r
+ if(!(__PC() & (1UL << 28UL)))\r
+ {\r
+ /* Select PCLK as the clock source of SPI */\r
+ if((spi == SPI0) || (spi == SPI0_NS))\r
+ {\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;\r
+ /* Return slave peripheral clock rate */\r
+ u32RetValue = u32PCLK1Freq;\r
+ }\r
+ else if((spi == SPI1) || (spi == SPI1_NS))\r
+ {\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0;\r
+ /* Return slave peripheral clock rate */\r
+ u32RetValue = u32PCLK0Freq;\r
+ }\r
+ else if((spi == SPI2) || (spi == SPI2_NS))\r
+ {\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1;\r
+ /* Return slave peripheral clock rate */\r
+ u32RetValue = u32PCLK1Freq;\r
+ }\r
+ else\r
+ {\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0;\r
+ /* Return slave peripheral clock rate */\r
+ u32RetValue = u32PCLK0Freq;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check clock source of SPI */\r
+ if((spi == SPI0) || (spi == SPI0_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT)\r
+ {\r
+ u32RetValue = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL)\r
+ {\r
+ u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1)\r
+ {\r
+ u32RetValue = u32PCLK1Freq; /* Clock source is PCLK1 */\r
+ }\r
+ else\r
+ {\r
+ u32RetValue = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else if((spi == SPI1) || (spi == SPI1_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT)\r
+ {\r
+ u32RetValue = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL)\r
+ {\r
+ u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0)\r
+ {\r
+ u32RetValue = u32PCLK0Freq; /* Clock source is PCLK0 */\r
+ }\r
+ else\r
+ {\r
+ u32RetValue = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else if((spi == SPI2) || (spi == SPI2_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT)\r
+ {\r
+ u32RetValue = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL)\r
+ {\r
+ u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1)\r
+ {\r
+ u32RetValue = u32PCLK1Freq; /* Clock source is PCLK1 */\r
+ }\r
+ else\r
+ {\r
+ u32RetValue = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT)\r
+ {\r
+ u32RetValue = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL)\r
+ {\r
+ u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0)\r
+ {\r
+ u32RetValue = u32PCLK0Freq; /* Clock source is PCLK0 */\r
+ }\r
+ else\r
+ {\r
+ u32RetValue = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ return u32RetValue;\r
+}\r
+\r
+/**\r
+ * @brief Disable SPI controller.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None\r
+ * @details Clear SPIEN bit of SPI_CTL register to disable SPI transfer control.\r
+ */\r
+void SPI_Close(SPI_T *spi)\r
+{\r
+ spi->CTL &= ~SPI_CTL_SPIEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Clear RX FIFO buffer.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None\r
+ * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1.\r
+ */\r
+void SPI_ClearRxFIFO(SPI_T *spi)\r
+{\r
+ spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Clear TX FIFO buffer.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None\r
+ * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1.\r
+ * @note The TX shift register will not be cleared.\r
+ */\r
+void SPI_ClearTxFIFO(SPI_T *spi)\r
+{\r
+ spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable the automatic slave selection function.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return None\r
+ * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.\r
+ */\r
+void SPI_DisableAutoSS(SPI_T *spi)\r
+{\r
+ spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Enable the automatic slave selection function.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS)\r
+ * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW)\r
+ * @return None\r
+ * @details This function will enable the automatic slave selection function. Only available in Master mode.\r
+ * The slave selection pin and the active level will be set in this function.\r
+ */\r
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)\r
+{\r
+ spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Set the SPI bus clock.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz.\r
+ * @return Actual frequency of SPI bus clock.\r
+ * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate.\r
+ * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock\r
+ * rate will be 6 MHz.\r
+ * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.\r
+ * @note If u32BusClock >= system clock frequency for Secure, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.\r
+ * @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of\r
+ * SPI bus clock cannot be faster than the system clock rate. User should set up carefully.\r
+ * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.\r
+ */\r
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)\r
+{\r
+ uint32_t u32ClkSrc, u32HCLKFreq;\r
+ uint32_t u32Div, u32RetValue;\r
+\r
+ /* Get system clock frequency */\r
+ u32HCLKFreq = CLK_GetHCLKFreq();\r
+\r
+ if(u32BusClock >= u32HCLKFreq)\r
+ {\r
+ if(!(__PC() & (1UL << 28UL)))\r
+ {\r
+ /* Select PCLK as the clock source of SPI */\r
+ if((spi == SPI0) || (spi == SPI0_NS))\r
+ {\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;\r
+ }\r
+ else if((spi == SPI1) || (spi == SPI1_NS))\r
+ {\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0;\r
+ }\r
+ else if((spi == SPI2) || (spi == SPI2_NS))\r
+ {\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1;\r
+ }\r
+ else\r
+ {\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Check clock source of SPI */\r
+ if((spi == SPI0) || (spi == SPI0_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT)\r
+ {\r
+ u32ClkSrc = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL)\r
+ {\r
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1)\r
+ {\r
+ u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */\r
+ }\r
+ else\r
+ {\r
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else if((spi == SPI1) || (spi == SPI1_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT)\r
+ {\r
+ u32ClkSrc = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL)\r
+ {\r
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0)\r
+ {\r
+ u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */\r
+ }\r
+ else\r
+ {\r
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else if((spi == SPI2) || (spi == SPI2_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT)\r
+ {\r
+ u32ClkSrc = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL)\r
+ {\r
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1)\r
+ {\r
+ u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */\r
+ }\r
+ else\r
+ {\r
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT)\r
+ {\r
+ u32ClkSrc = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL)\r
+ {\r
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0)\r
+ {\r
+ u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */\r
+ }\r
+ else\r
+ {\r
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+\r
+ if(u32BusClock >= u32HCLKFreq)\r
+ {\r
+ /* Set DIVIDER = 0 */\r
+ spi->CLKDIV = 0UL;\r
+ /* Return master peripheral clock rate */\r
+ u32RetValue = u32ClkSrc;\r
+ }\r
+ else if(u32BusClock >= u32ClkSrc)\r
+ {\r
+ /* Set DIVIDER = 0 */\r
+ spi->CLKDIV = 0UL;\r
+ /* Return master peripheral clock rate */\r
+ u32RetValue = u32ClkSrc;\r
+ }\r
+ else if(u32BusClock == 0UL)\r
+ {\r
+ /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */\r
+ spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;\r
+ /* Return master peripheral clock rate */\r
+ u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));\r
+ }\r
+ else\r
+ {\r
+ u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */\r
+ if(u32Div > 0x1FFUL)\r
+ {\r
+ u32Div = 0x1FFUL;\r
+ spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;\r
+ /* Return master peripheral clock rate */\r
+ u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));\r
+ }\r
+ else\r
+ {\r
+ spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);\r
+ /* Return master peripheral clock rate */\r
+ u32RetValue = (u32ClkSrc / (u32Div + 1UL));\r
+ }\r
+ }\r
+\r
+ return u32RetValue;\r
+}\r
+\r
+/**\r
+ * @brief Configure FIFO threshold setting.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7.\r
+ * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7.\r
+ * @return None\r
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.\r
+ */\r
+void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)\r
+{\r
+ spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) |\r
+ (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |\r
+ (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos);\r
+}\r
+\r
+/**\r
+ * @brief Get the actual frequency of SPI bus clock. Only available in Master mode.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @return Actual SPI bus clock frequency in Hz.\r
+ * @details This function will calculate the actual SPI bus clock rate according to the SPIxSEL and DIVIDER settings. Only available in Master mode.\r
+ */\r
+uint32_t SPI_GetBusClock(SPI_T *spi)\r
+{\r
+ uint32_t u32Div;\r
+ uint32_t u32ClkSrc;\r
+\r
+ /* Get DIVIDER setting */\r
+ u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos;\r
+\r
+ /* Check clock source of SPI */\r
+ if((spi == SPI0) || (spi == SPI0_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT)\r
+ {\r
+ u32ClkSrc = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL)\r
+ {\r
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1)\r
+ {\r
+ u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */\r
+ }\r
+ else\r
+ {\r
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else if((spi == SPI1) || (spi == SPI1_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT)\r
+ {\r
+ u32ClkSrc = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL)\r
+ {\r
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0)\r
+ {\r
+ u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */\r
+ }\r
+ else\r
+ {\r
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else if((spi == SPI2) || (spi == SPI2_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT)\r
+ {\r
+ u32ClkSrc = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL)\r
+ {\r
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1)\r
+ {\r
+ u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */\r
+ }\r
+ else\r
+ {\r
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT)\r
+ {\r
+ u32ClkSrc = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL)\r
+ {\r
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0)\r
+ {\r
+ u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */\r
+ }\r
+ else\r
+ {\r
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+\r
+ /* Return SPI bus clock rate */\r
+ return (u32ClkSrc / (u32Div + 1UL));\r
+}\r
+\r
+/**\r
+ * @brief Enable interrupt function.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @param[in] u32Mask The combination of all related interrupt enable bits.\r
+ * Each bit corresponds to a interrupt enable bit.\r
+ * This parameter decides which interrupts will be enabled. It is combination of:\r
+ * - \ref SPI_UNIT_INT_MASK\r
+ * - \ref SPI_SSACT_INT_MASK\r
+ * - \ref SPI_SSINACT_INT_MASK\r
+ * - \ref SPI_SLVUR_INT_MASK\r
+ * - \ref SPI_SLVBE_INT_MASK\r
+ * - \ref SPI_TXUF_INT_MASK\r
+ * - \ref SPI_FIFO_TXTH_INT_MASK\r
+ * - \ref SPI_FIFO_RXTH_INT_MASK\r
+ * - \ref SPI_FIFO_RXOV_INT_MASK\r
+ * - \ref SPI_FIFO_RXTO_INT_MASK\r
+ *\r
+ * @return None\r
+ * @details Enable SPI related interrupts specified by u32Mask parameter.\r
+ */\r
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)\r
+{\r
+ /* Enable unit transfer interrupt flag */\r
+ if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)\r
+ {\r
+ spi->CTL |= SPI_CTL_UNITIEN_Msk;\r
+ }\r
+\r
+ /* Enable slave selection signal active interrupt flag */\r
+ if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)\r
+ {\r
+ spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk;\r
+ }\r
+\r
+ /* Enable slave selection signal inactive interrupt flag */\r
+ if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)\r
+ {\r
+ spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk;\r
+ }\r
+\r
+ /* Enable slave TX under run interrupt flag */\r
+ if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)\r
+ {\r
+ spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk;\r
+ }\r
+\r
+ /* Enable slave bit count error interrupt flag */\r
+ if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)\r
+ {\r
+ spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk;\r
+ }\r
+\r
+ /* Enable slave TX underflow interrupt flag */\r
+ if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)\r
+ {\r
+ spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;\r
+ }\r
+\r
+ /* Enable TX threshold interrupt flag */\r
+ if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)\r
+ {\r
+ spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;\r
+ }\r
+\r
+ /* Enable RX threshold interrupt flag */\r
+ if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)\r
+ {\r
+ spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;\r
+ }\r
+\r
+ /* Enable RX overrun interrupt flag */\r
+ if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)\r
+ {\r
+ spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;\r
+ }\r
+\r
+ /* Enable RX time-out interrupt flag */\r
+ if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)\r
+ {\r
+ spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable interrupt function.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @param[in] u32Mask The combination of all related interrupt enable bits.\r
+ * Each bit corresponds to a interrupt bit.\r
+ * This parameter decides which interrupts will be disabled. It is combination of:\r
+ * - \ref SPI_UNIT_INT_MASK\r
+ * - \ref SPI_SSACT_INT_MASK\r
+ * - \ref SPI_SSINACT_INT_MASK\r
+ * - \ref SPI_SLVUR_INT_MASK\r
+ * - \ref SPI_SLVBE_INT_MASK\r
+ * - \ref SPI_TXUF_INT_MASK\r
+ * - \ref SPI_FIFO_TXTH_INT_MASK\r
+ * - \ref SPI_FIFO_RXTH_INT_MASK\r
+ * - \ref SPI_FIFO_RXOV_INT_MASK\r
+ * - \ref SPI_FIFO_RXTO_INT_MASK\r
+ *\r
+ * @return None\r
+ * @details Disable SPI related interrupts specified by u32Mask parameter.\r
+ */\r
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)\r
+{\r
+ /* Disable unit transfer interrupt flag */\r
+ if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)\r
+ {\r
+ spi->CTL &= ~SPI_CTL_UNITIEN_Msk;\r
+ }\r
+\r
+ /* Disable slave selection signal active interrupt flag */\r
+ if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)\r
+ {\r
+ spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;\r
+ }\r
+\r
+ /* Disable slave selection signal inactive interrupt flag */\r
+ if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)\r
+ {\r
+ spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;\r
+ }\r
+\r
+ /* Disable slave TX under run interrupt flag */\r
+ if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)\r
+ {\r
+ spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;\r
+ }\r
+\r
+ /* Disable slave bit count error interrupt flag */\r
+ if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)\r
+ {\r
+ spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;\r
+ }\r
+\r
+ /* Disable slave TX underflow interrupt flag */\r
+ if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)\r
+ {\r
+ spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;\r
+ }\r
+\r
+ /* Disable TX threshold interrupt flag */\r
+ if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)\r
+ {\r
+ spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;\r
+ }\r
+\r
+ /* Disable RX threshold interrupt flag */\r
+ if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)\r
+ {\r
+ spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;\r
+ }\r
+\r
+ /* Disable RX overrun interrupt flag */\r
+ if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)\r
+ {\r
+ spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;\r
+ }\r
+\r
+ /* Disable RX time-out interrupt flag */\r
+ if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)\r
+ {\r
+ spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get interrupt flag.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @param[in] u32Mask The combination of all related interrupt sources.\r
+ * Each bit corresponds to a interrupt source.\r
+ * This parameter decides which interrupt flags will be read. It is combination of:\r
+ * - \ref SPI_UNIT_INT_MASK\r
+ * - \ref SPI_SSACT_INT_MASK\r
+ * - \ref SPI_SSINACT_INT_MASK\r
+ * - \ref SPI_SLVUR_INT_MASK\r
+ * - \ref SPI_SLVBE_INT_MASK\r
+ * - \ref SPI_TXUF_INT_MASK\r
+ * - \ref SPI_FIFO_TXTH_INT_MASK\r
+ * - \ref SPI_FIFO_RXTH_INT_MASK\r
+ * - \ref SPI_FIFO_RXOV_INT_MASK\r
+ * - \ref SPI_FIFO_RXTO_INT_MASK\r
+ *\r
+ * @return Interrupt flags of selected sources.\r
+ * @details Get SPI related interrupt flags specified by u32Mask parameter.\r
+ */\r
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)\r
+{\r
+ uint32_t u32IntStatus;\r
+ uint32_t u32IntFlag = 0UL;\r
+\r
+ u32IntStatus = spi->STATUS;\r
+\r
+ /* Check unit transfer interrupt flag */\r
+ if((u32Mask & SPI_UNIT_INT_MASK) && (u32IntStatus & SPI_STATUS_UNITIF_Msk))\r
+ {\r
+ u32IntFlag |= SPI_UNIT_INT_MASK;\r
+ }\r
+\r
+ /* Check slave selection signal active interrupt flag */\r
+ if((u32Mask & SPI_SSACT_INT_MASK) && (u32IntStatus & SPI_STATUS_SSACTIF_Msk))\r
+ {\r
+ u32IntFlag |= SPI_SSACT_INT_MASK;\r
+ }\r
+\r
+ /* Check slave selection signal inactive interrupt flag */\r
+ if((u32Mask & SPI_SSINACT_INT_MASK) && (u32IntStatus & SPI_STATUS_SSINAIF_Msk))\r
+ {\r
+ u32IntFlag |= SPI_SSINACT_INT_MASK;\r
+ }\r
+\r
+ /* Check slave TX under run interrupt flag */\r
+ if((u32Mask & SPI_SLVUR_INT_MASK) && (u32IntStatus & SPI_STATUS_SLVURIF_Msk))\r
+ {\r
+ u32IntFlag |= SPI_SLVUR_INT_MASK;\r
+ }\r
+\r
+ /* Check slave bit count error interrupt flag */\r
+ if((u32Mask & SPI_SLVBE_INT_MASK) && (u32IntStatus & SPI_STATUS_SLVBEIF_Msk))\r
+ {\r
+ u32IntFlag |= SPI_SLVBE_INT_MASK;\r
+ }\r
+\r
+ /* Check slave TX underflow interrupt flag */\r
+ if((u32Mask & SPI_TXUF_INT_MASK) && (u32IntStatus & SPI_STATUS_TXUFIF_Msk))\r
+ {\r
+ u32IntFlag |= SPI_TXUF_INT_MASK;\r
+ }\r
+\r
+ /* Check TX threshold interrupt flag */\r
+ if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (u32IntStatus & SPI_STATUS_TXTHIF_Msk))\r
+ {\r
+ u32IntFlag |= SPI_FIFO_TXTH_INT_MASK;\r
+ }\r
+\r
+ /* Check RX threshold interrupt flag */\r
+ if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (u32IntStatus & SPI_STATUS_RXTHIF_Msk))\r
+ {\r
+ u32IntFlag |= SPI_FIFO_RXTH_INT_MASK;\r
+ }\r
+\r
+ /* Check RX overrun interrupt flag */\r
+ if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (u32IntStatus & SPI_STATUS_RXOVIF_Msk))\r
+ {\r
+ u32IntFlag |= SPI_FIFO_RXOV_INT_MASK;\r
+ }\r
+\r
+ /* Check RX time-out interrupt flag */\r
+ if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32IntStatus & SPI_STATUS_RXTOIF_Msk))\r
+ {\r
+ u32IntFlag |= SPI_FIFO_RXTO_INT_MASK;\r
+ }\r
+\r
+ return u32IntFlag;\r
+}\r
+\r
+/**\r
+ * @brief Clear interrupt flag.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @param[in] u32Mask The combination of all related interrupt sources.\r
+ * Each bit corresponds to a interrupt source.\r
+ * This parameter decides which interrupt flags will be cleared. It could be the combination of:\r
+ * - \ref SPI_UNIT_INT_MASK\r
+ * - \ref SPI_SSACT_INT_MASK\r
+ * - \ref SPI_SSINACT_INT_MASK\r
+ * - \ref SPI_SLVUR_INT_MASK\r
+ * - \ref SPI_SLVBE_INT_MASK\r
+ * - \ref SPI_TXUF_INT_MASK\r
+ * - \ref SPI_FIFO_RXOV_INT_MASK\r
+ * - \ref SPI_FIFO_RXTO_INT_MASK\r
+ *\r
+ * @return None\r
+ * @details Clear SPI related interrupt flags specified by u32Mask parameter.\r
+ */\r
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)\r
+{\r
+ if(u32Mask & SPI_UNIT_INT_MASK)\r
+ {\r
+ spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */\r
+ }\r
+\r
+ if(u32Mask & SPI_SSACT_INT_MASK)\r
+ {\r
+ spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */\r
+ }\r
+\r
+ if(u32Mask & SPI_SSINACT_INT_MASK)\r
+ {\r
+ spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */\r
+ }\r
+\r
+ if(u32Mask & SPI_SLVUR_INT_MASK)\r
+ {\r
+ spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */\r
+ }\r
+\r
+ if(u32Mask & SPI_SLVBE_INT_MASK)\r
+ {\r
+ spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */\r
+ }\r
+\r
+ if(u32Mask & SPI_TXUF_INT_MASK)\r
+ {\r
+ spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */\r
+ }\r
+\r
+ if(u32Mask & SPI_FIFO_RXOV_INT_MASK)\r
+ {\r
+ spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */\r
+ }\r
+\r
+ if(u32Mask & SPI_FIFO_RXTO_INT_MASK)\r
+ {\r
+ spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get SPI status.\r
+ * @param[in] spi The pointer of the specified SPI module.\r
+ * @param[in] u32Mask The combination of all related sources.\r
+ * Each bit corresponds to a source.\r
+ * This parameter decides which flags will be read. It is combination of:\r
+ * - \ref SPI_BUSY_MASK\r
+ * - \ref SPI_RX_EMPTY_MASK\r
+ * - \ref SPI_RX_FULL_MASK\r
+ * - \ref SPI_TX_EMPTY_MASK\r
+ * - \ref SPI_TX_FULL_MASK\r
+ * - \ref SPI_TXRX_RESET_MASK\r
+ * - \ref SPI_SPIEN_STS_MASK\r
+ * - \ref SPI_SSLINE_STS_MASK\r
+ *\r
+ * @return Flags of selected sources.\r
+ * @details Get SPI related status specified by u32Mask parameter.\r
+ */\r
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)\r
+{\r
+ uint32_t u32TmpStatus;\r
+ uint32_t u32Flag = 0UL;\r
+\r
+ u32TmpStatus = spi->STATUS;\r
+\r
+ /* Check busy status */\r
+ if((u32Mask & SPI_BUSY_MASK) && (u32TmpStatus & SPI_STATUS_BUSY_Msk))\r
+ {\r
+ u32Flag |= SPI_BUSY_MASK;\r
+ }\r
+\r
+ /* Check RX empty flag */\r
+ if((u32Mask & SPI_RX_EMPTY_MASK) && (u32TmpStatus & SPI_STATUS_RXEMPTY_Msk))\r
+ {\r
+ u32Flag |= SPI_RX_EMPTY_MASK;\r
+ }\r
+\r
+ /* Check RX full flag */\r
+ if((u32Mask & SPI_RX_FULL_MASK) && (u32TmpStatus & SPI_STATUS_RXFULL_Msk))\r
+ {\r
+ u32Flag |= SPI_RX_FULL_MASK;\r
+ }\r
+\r
+ /* Check TX empty flag */\r
+ if((u32Mask & SPI_TX_EMPTY_MASK) && (u32TmpStatus & SPI_STATUS_TXEMPTY_Msk))\r
+ {\r
+ u32Flag |= SPI_TX_EMPTY_MASK;\r
+ }\r
+\r
+ /* Check TX full flag */\r
+ if((u32Mask & SPI_TX_FULL_MASK) && (u32TmpStatus & SPI_STATUS_TXFULL_Msk))\r
+ {\r
+ u32Flag |= SPI_TX_FULL_MASK;\r
+ }\r
+\r
+ /* Check TX/RX reset flag */\r
+ if((u32Mask & SPI_TXRX_RESET_MASK) && (u32TmpStatus & SPI_STATUS_TXRXRST_Msk))\r
+ {\r
+ u32Flag |= SPI_TXRX_RESET_MASK;\r
+ }\r
+\r
+ /* Check SPIEN flag */\r
+ if((u32Mask & SPI_SPIEN_STS_MASK) && (u32TmpStatus & SPI_STATUS_SPIENSTS_Msk))\r
+ {\r
+ u32Flag |= SPI_SPIEN_STS_MASK;\r
+ }\r
+\r
+ /* Check SPIx_SS line status */\r
+ if((u32Mask & SPI_SSLINE_STS_MASK) && (u32TmpStatus & SPI_STATUS_SSLINE_Msk))\r
+ {\r
+ u32Flag |= SPI_SSLINE_STS_MASK;\r
+ }\r
+\r
+ return u32Flag;\r
+}\r
+\r
+\r
+/**\r
+ * @brief This function is used to get I2S source clock frequency.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return I2S source clock frequency (Hz).\r
+ * @details Return the source clock frequency according to the setting of SPI0SEL (CLK_CLKSEL2[5:4]) or SPI1SEL (CLK_CLKSEL2[7:6]) or SPI2SEL (CLK_CLKSEL2[11:10]) or SPI3SEL (CLK_CLKSEL2[13:12]).\r
+ */\r
+static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s)\r
+{\r
+ uint32_t u32Freq;\r
+\r
+ if((i2s == SPI0) || (i2s == SPI0_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT)\r
+ {\r
+ u32Freq = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL)\r
+ {\r
+ u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1)\r
+ {\r
+ u32Freq = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */\r
+ }\r
+ else\r
+ {\r
+ u32Freq = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else if((i2s == SPI1) || (i2s == SPI1_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT)\r
+ {\r
+ u32Freq = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL)\r
+ {\r
+ u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0)\r
+ {\r
+ u32Freq = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */\r
+ }\r
+ else\r
+ {\r
+ u32Freq = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else if((i2s == SPI2) || (i2s == SPI2_NS))\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT)\r
+ {\r
+ u32Freq = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL)\r
+ {\r
+ u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1)\r
+ {\r
+ u32Freq = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */\r
+ }\r
+ else\r
+ {\r
+ u32Freq = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT)\r
+ {\r
+ u32Freq = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL)\r
+ {\r
+ u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0)\r
+ {\r
+ u32Freq = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */\r
+ }\r
+ else\r
+ {\r
+ u32Freq = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+\r
+ return u32Freq;\r
+}\r
+\r
+/**\r
+ * @brief This function configures some parameters of I2S interface for general purpose use.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below.\r
+ * - \ref SPII2S_MODE_MASTER\r
+ * - \ref SPII2S_MODE_SLAVE\r
+ * @param[in] u32SampleRate Sample rate\r
+ * @param[in] u32WordWidth Data length. Valid values are listed below.\r
+ * - \ref SPII2S_DATABIT_8\r
+ * - \ref SPII2S_DATABIT_16\r
+ * - \ref SPII2S_DATABIT_24\r
+ * - \ref SPII2S_DATABIT_32\r
+ * @param[in] u32Channels Audio format. Valid values are listed below.\r
+ * - \ref SPII2S_MONO\r
+ * - \ref SPII2S_STEREO\r
+ * @param[in] u32DataFormat Data format. Valid values are listed below.\r
+ * - \ref SPII2S_FORMAT_I2S\r
+ * - \ref SPII2S_FORMAT_MSB\r
+ * - \ref SPII2S_FORMAT_PCMA\r
+ * - \ref SPII2S_FORMAT_PCMB\r
+ * @return Real sample rate of master mode or peripheral clock rate of slave mode.\r
+ * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters.\r
+ * Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled.\r
+ * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference.\r
+ * @note In slave mode for Secure, the SPI peripheral clock rate will equal to APB clock rate.\r
+ * @note In slave mode for Non-Secure, the SPI peripheral clock rate will equal to the clock rate set in secure mode.\r
+ */\r
+uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat)\r
+{\r
+ uint32_t u32Divider;\r
+ uint32_t u32BitRate, u32SrcClk, u32RetValue;\r
+ uint32_t u32PCLK0Freq, u32PCLK1Freq;\r
+\r
+ if(!(__PC() & (1UL << 28UL)))\r
+ {\r
+ /* Reset SPI/I2S */\r
+ if((i2s == SPI0) || (i2s == SPI0_NS))\r
+ {\r
+ SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;\r
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;\r
+ }\r
+ else if((i2s == SPI1) || (i2s == SPI1_NS))\r
+ {\r
+ SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;\r
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;\r
+ }\r
+ else if((i2s == SPI2) || (i2s == SPI2_NS))\r
+ {\r
+ SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;\r
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;\r
+ }\r
+ else\r
+ {\r
+ SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk;\r
+ SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk;\r
+ }\r
+ }\r
+\r
+ /* Configure I2S controller */\r
+ i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat;\r
+ /* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */\r
+ i2s->FIFOCTL = SPII2S_FIFO_TX_LEVEL_WORD_2 | SPII2S_FIFO_RX_LEVEL_WORD_2;\r
+\r
+ if(u32MasterSlave == SPI_MASTER)\r
+ {\r
+ /* Get the source clock rate */\r
+ u32SrcClk = SPII2S_GetSourceClockFreq(i2s);\r
+\r
+ /* Calculate the bit clock rate */\r
+ u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1UL) * 16UL;\r
+ u32Divider = (((((u32SrcClk * 10UL) / u32BitRate) >> 1UL) + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */\r
+ /* Set BCLKDIV setting */\r
+ i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos);\r
+\r
+ /* Calculate bit clock rate */\r
+ u32BitRate = u32SrcClk / ((u32Divider + 1UL) * 2UL);\r
+ /* Calculate real sample rate */\r
+ u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1UL) * 16UL);\r
+\r
+ /* Enable TX function, RX function and I2S mode. */\r
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);\r
+\r
+ /* Return the real sample rate */\r
+ u32RetValue = u32SampleRate;\r
+ }\r
+ else\r
+ {\r
+ /* Set BCLKDIV = 0 */\r
+ i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk;\r
+ /* Get APB0 clock frequency */\r
+ u32PCLK0Freq = CLK_GetPCLK0Freq();\r
+ /* Get APB1 clock frequency */\r
+ u32PCLK1Freq = CLK_GetPCLK1Freq();\r
+\r
+ if((i2s == SPI0) || (i2s == SPI0_NS))\r
+ {\r
+ if(!(__PC() & (1UL << 28UL)))\r
+ {\r
+ /* Set the peripheral clock rate to equal APB clock rate */\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;\r
+ /* Return slave peripheral clock rate */\r
+ u32RetValue = u32PCLK1Freq;\r
+ }\r
+ else\r
+ {\r
+ /* Check clock source of I2S */\r
+ if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT)\r
+ {\r
+ u32RetValue = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL)\r
+ {\r
+ u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1)\r
+ {\r
+ u32RetValue = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */\r
+ }\r
+ else\r
+ {\r
+ u32RetValue = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ /* Enable TX function, RX function and I2S mode. */\r
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);\r
+ }\r
+ else if((i2s == SPI1) || (i2s == SPI1_NS))\r
+ {\r
+ if(!(__PC() & (1UL << 28UL)))\r
+ {\r
+ /* Set the peripheral clock rate to equal APB clock rate */\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0;\r
+ /* Return slave peripheral clock rate */\r
+ u32RetValue = u32PCLK0Freq;\r
+ }\r
+ else\r
+ {\r
+ /* Check clock source of I2S */\r
+ if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT)\r
+ {\r
+ u32RetValue = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL)\r
+ {\r
+ u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0)\r
+ {\r
+ u32RetValue = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */\r
+ }\r
+ else\r
+ {\r
+ u32RetValue = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ /* Enable TX function, RX function and I2S mode. */\r
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);\r
+ }\r
+ else if((i2s == SPI2) || (i2s == SPI2_NS))\r
+ {\r
+ if(!(__PC() & (1UL << 28UL)))\r
+ {\r
+ /* Set the peripheral clock rate to equal APB clock rate */\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1;\r
+ /* Return slave peripheral clock rate */\r
+ u32RetValue = u32PCLK1Freq;\r
+ }\r
+ else\r
+ {\r
+ /* Check clock source of I2S */\r
+ if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT)\r
+ {\r
+ u32RetValue = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL)\r
+ {\r
+ u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1)\r
+ {\r
+ u32RetValue = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */\r
+ }\r
+ else\r
+ {\r
+ u32RetValue = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ /* Enable TX function, RX function and I2S mode. */\r
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);\r
+ }\r
+ else\r
+ {\r
+ if(!(__PC() & (1UL << 28UL)))\r
+ {\r
+ /* Set the peripheral clock rate to equal APB clock rate */\r
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0;\r
+ /* Return slave peripheral clock rate */\r
+ u32RetValue = u32PCLK0Freq;\r
+ }\r
+ else\r
+ {\r
+ /* Check clock source of I2S */\r
+ if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT)\r
+ {\r
+ u32RetValue = __HXT; /* Clock source is HXT */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL)\r
+ {\r
+ u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */\r
+ }\r
+ else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0)\r
+ {\r
+ u32RetValue = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */\r
+ }\r
+ else\r
+ {\r
+ u32RetValue = __HIRC; /* Clock source is HIRC */\r
+ }\r
+ }\r
+ /* Enable TX function, RX function and I2S mode. */\r
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);\r
+ }\r
+ }\r
+\r
+ return u32RetValue;\r
+}\r
+\r
+/**\r
+ * @brief Disable I2S function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details Disable I2S function.\r
+ */\r
+void SPII2S_Close(SPI_T *i2s)\r
+{\r
+ i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable interrupt function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32Mask The combination of all related interrupt enable bits.\r
+ * Each bit corresponds to a interrupt source. Valid values are listed below.\r
+ * - \ref SPII2S_FIFO_TXTH_INT_MASK\r
+ * - \ref SPII2S_FIFO_RXTH_INT_MASK\r
+ * - \ref SPII2S_FIFO_RXOV_INT_MASK\r
+ * - \ref SPII2S_FIFO_RXTO_INT_MASK\r
+ * - \ref SPII2S_TXUF_INT_MASK\r
+ * - \ref SPII2S_RIGHT_ZC_INT_MASK\r
+ * - \ref SPII2S_LEFT_ZC_INT_MASK\r
+ * @return None\r
+ * @details This function enables the interrupt according to the u32Mask parameter.\r
+ */\r
+void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask)\r
+{\r
+ /* Enable TX threshold interrupt flag */\r
+ if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK)\r
+ {\r
+ i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;\r
+ }\r
+\r
+ /* Enable RX threshold interrupt flag */\r
+ if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK)\r
+ {\r
+ i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;\r
+ }\r
+\r
+ /* Enable RX overrun interrupt flag */\r
+ if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK)\r
+ {\r
+ i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;\r
+ }\r
+\r
+ /* Enable RX time-out interrupt flag */\r
+ if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK)\r
+ {\r
+ i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;\r
+ }\r
+\r
+ /* Enable TX underflow interrupt flag */\r
+ if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK)\r
+ {\r
+ i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;\r
+ }\r
+\r
+ /* Enable right channel zero cross interrupt flag */\r
+ if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK)\r
+ {\r
+ i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk;\r
+ }\r
+\r
+ /* Enable left channel zero cross interrupt flag */\r
+ if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK)\r
+ {\r
+ i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable interrupt function.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32Mask The combination of all related interrupt enable bits.\r
+ * Each bit corresponds to a interrupt source. Valid values are listed below.\r
+ * - \ref SPII2S_FIFO_TXTH_INT_MASK\r
+ * - \ref SPII2S_FIFO_RXTH_INT_MASK\r
+ * - \ref SPII2S_FIFO_RXOV_INT_MASK\r
+ * - \ref SPII2S_FIFO_RXTO_INT_MASK\r
+ * - \ref SPII2S_TXUF_INT_MASK\r
+ * - \ref SPII2S_RIGHT_ZC_INT_MASK\r
+ * - \ref SPII2S_LEFT_ZC_INT_MASK\r
+ * @return None\r
+ * @details This function disables the interrupt according to the u32Mask parameter.\r
+ */\r
+void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask)\r
+{\r
+ /* Disable TX threshold interrupt flag */\r
+ if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK)\r
+ {\r
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;\r
+ }\r
+\r
+ /* Disable RX threshold interrupt flag */\r
+ if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK)\r
+ {\r
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;\r
+ }\r
+\r
+ /* Disable RX overrun interrupt flag */\r
+ if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK)\r
+ {\r
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;\r
+ }\r
+\r
+ /* Disable RX time-out interrupt flag */\r
+ if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK)\r
+ {\r
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;\r
+ }\r
+\r
+ /* Disable TX underflow interrupt flag */\r
+ if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK)\r
+ {\r
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;\r
+ }\r
+\r
+ /* Disable right channel zero cross interrupt flag */\r
+ if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK)\r
+ {\r
+ i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk;\r
+ }\r
+\r
+ /* Disable left channel zero cross interrupt flag */\r
+ if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK)\r
+ {\r
+ i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable master clock (MCLK).\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32BusClock The target MCLK clock rate.\r
+ * @return Actual MCLK clock rate\r
+ * @details Set the master clock rate according to u32BusClock parameter and enable master clock output.\r
+ * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference.\r
+ */\r
+uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock)\r
+{\r
+ uint32_t u32Divider;\r
+ uint32_t u32SrcClk, u32RetValue;\r
+\r
+ u32SrcClk = SPII2S_GetSourceClockFreq(i2s);\r
+ if(u32BusClock == u32SrcClk)\r
+ {\r
+ u32Divider = 0UL;\r
+ }\r
+ else\r
+ {\r
+ u32Divider = (u32SrcClk / u32BusClock) >> 1UL;\r
+ /* MCLKDIV is a 7-bit width configuration. The maximum value is 0x7F. */\r
+ if(u32Divider > 0x7FUL)\r
+ {\r
+ u32Divider = 0x7FUL;\r
+ }\r
+ }\r
+\r
+ /* Write u32Divider to MCLKDIV (SPI_I2SCLK[6:0]) */\r
+ i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos);\r
+\r
+ /* Enable MCLK output */\r
+ i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk;\r
+\r
+ if(u32Divider == 0UL)\r
+ {\r
+ u32RetValue = u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */\r
+ }\r
+ else\r
+ {\r
+ u32RetValue = ((u32SrcClk >> 1UL) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */\r
+ }\r
+\r
+ return u32RetValue;\r
+}\r
+\r
+/**\r
+ * @brief Disable master clock (MCLK).\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @return None\r
+ * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output.\r
+ */\r
+void SPII2S_DisableMCLK(SPI_T *i2s)\r
+{\r
+ i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Configure FIFO threshold setting.\r
+ * @param[in] i2s The pointer of the specified I2S module.\r
+ * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7.\r
+ * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7.\r
+ * @return None\r
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.\r
+ */\r
+void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)\r
+{\r
+ i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) |\r
+ (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |\r
+ (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos);\r
+}\r
+\r
+/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group SPI_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file sys.c\r
+ * @version V3.00\r
+ * @brief M2351 series System Manager (SYS) driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup SYS_Driver SYS Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Clear reset source\r
+ * @param[in] u32Src is system reset source. Including :\r
+ * - \ref SYS_RSTSTS_CPULKRF_Msk\r
+ * - \ref SYS_RSTSTS_CPURF_Msk\r
+ * - \ref SYS_RSTSTS_SYSRF_Msk\r
+ * - \ref SYS_RSTSTS_BODRF_Msk\r
+ * - \ref SYS_RSTSTS_LVRF_Msk\r
+ * - \ref SYS_RSTSTS_WDTRF_Msk\r
+ * - \ref SYS_RSTSTS_PINRF_Msk\r
+ * - \ref SYS_RSTSTS_PORF_Msk\r
+ * @return None\r
+ * @details This function clear the selected system reset source.\r
+ */\r
+void SYS_ClearResetSrc(uint32_t u32Src)\r
+{\r
+ SYS->RSTSTS = u32Src;\r
+}\r
+\r
+/**\r
+ * @brief Get Brown-out detector output status\r
+ * @param None\r
+ * @retval 0 System voltage is higher than BODVL setting or BODEN is 0.\r
+ * @retval 1 System voltage is lower than BODVL setting.\r
+ * @details This function get Brown-out detector output status.\r
+ */\r
+uint32_t SYS_GetBODStatus(void)\r
+{\r
+ return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos);\r
+}\r
+\r
+/**\r
+ * @brief Get reset status register value\r
+ * @param None\r
+ * @return Reset source\r
+ * @details This function get the system reset status register value.\r
+ */\r
+uint32_t SYS_GetResetSrc(void)\r
+{\r
+ return (SYS->RSTSTS);\r
+}\r
+\r
+/**\r
+ * @brief Check if register is locked nor not\r
+ * @param None\r
+ * @retval 0 Write-protection function is disabled.\r
+ * 1 Write-protection function is enabled.\r
+ * @details This function check register write-protection bit setting.\r
+ */\r
+uint32_t SYS_IsRegLocked(void)\r
+{\r
+ return SYS->REGLCTL & 1UL ? 0UL : 1UL;\r
+}\r
+\r
+/**\r
+ * @brief Get product ID\r
+ * @param None\r
+ * @return Product ID\r
+ * @details This function get product ID.\r
+ */\r
+uint32_t SYS_ReadPDID(void)\r
+{\r
+ return SYS->PDID;\r
+}\r
+\r
+/**\r
+ * @brief Reset chip with chip reset\r
+ * @param None\r
+ * @return None\r
+ * @details This function reset chip with chip reset.\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void SYS_ResetChip(void)\r
+{\r
+ SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Reset chip with CPU reset\r
+ * @param None\r
+ * @return None\r
+ * @details This function reset CPU with CPU reset.\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void SYS_ResetCPU(void)\r
+{\r
+ SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Reset selected module\r
+ * @param[in] u32ModuleIndex is module index. Including :\r
+ * - \ref PDMA0_RST\r
+ * - \ref PDMA1_RST\r
+ * - \ref EBI_RST\r
+ * - \ref USBH_RST\r
+ * - \ref SDH0_RST\r
+ * - \ref CRC_RST\r
+ * - \ref CRPT_RST\r
+ * - \ref GPIO_RST\r
+ * - \ref TMR0_RST\r
+ * - \ref TMR1_RST\r
+ * - \ref TMR2_RST\r
+ * - \ref TMR3_RST\r
+ * - \ref ACMP01_RST\r
+ * - \ref I2C0_RST\r
+ * - \ref I2C1_RST\r
+ * - \ref I2C2_RST\r
+ * - \ref QSPI0_RST\r
+ * - \ref SPI0_RST\r
+ * - \ref SPI1_RST\r
+ * - \ref SPI2_RST\r
+ * - \ref SPI3_RST\r
+ * - \ref UART0_RST\r
+ * - \ref UART1_RST\r
+ * - \ref UART2_RST\r
+ * - \ref UART3_RST\r
+ * - \ref UART4_RST\r
+ * - \ref UART5_RST\r
+ * - \ref CAN0_RST\r
+ * - \ref OTG_RST\r
+ * - \ref USBD_RST\r
+ * - \ref EADC_RST\r
+ * - \ref I2S0_RST\r
+ * - \ref TRNG_RST\r
+ * - \ref SC0_RST\r
+ * - \ref SC1_RST\r
+ * - \ref SC2_RST\r
+ * - \ref USCI0_RST\r
+ * - \ref USCI1_RST\r
+ * - \ref DAC_RST\r
+ * - \ref EPWM0_RST\r
+ * - \ref EPWM1_RST\r
+ * - \ref BPWM0_RST\r
+ * - \ref BPWM1_RST\r
+ * - \ref QEI0_RST\r
+ * - \ref QEI1_RST\r
+ * - \ref ECAP0_RST\r
+ * - \ref ECAP1_RST\r
+ * @return None\r
+ * @details This function reset selected module.\r
+ */\r
+void SYS_ResetModule(uint32_t u32ModuleIndex)\r
+{\r
+ uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;\r
+\r
+ /* Generate reset signal to the corresponding module */\r
+ u32TmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL));\r
+ u32TmpAddr = (uint32_t)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL));\r
+ *(uint32_t *)u32TmpAddr |= u32TmpVal;\r
+\r
+ /* Release corresponding module from reset state */\r
+ u32TmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL));\r
+ *(uint32_t *)u32TmpAddr &= u32TmpVal;\r
+}\r
+\r
+/**\r
+ * @brief Enable and configure Brown-out detector function\r
+ * @param[in] i32Mode is reset or interrupt mode. Including :\r
+ * - \ref SYS_BODCTL_BOD_RST_EN\r
+ * - \ref SYS_BODCTL_BOD_INTERRUPT_EN\r
+ * @param[in] u32BODLevel is Brown-out voltage level. Including :\r
+ * - \ref SYS_BODCTL_BODVL_1_6V\r
+ * - \ref SYS_BODCTL_BODVL_1_8V\r
+ * - \ref SYS_BODCTL_BODVL_2_0V\r
+ * - \ref SYS_BODCTL_BODVL_2_2V\r
+ * - \ref SYS_BODCTL_BODVL_2_4V\r
+ * - \ref SYS_BODCTL_BODVL_2_6V\r
+ * - \ref SYS_BODCTL_BODVL_2_8V\r
+ * - \ref SYS_BODCTL_BODVL_3_0V\r
+ * @return None\r
+ * @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level.\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)\r
+{\r
+ /* Enable Brown-out Detector function */\r
+ SYS->BODCTL |= SYS_BODCTL_BODEN_Msk;\r
+\r
+ /* Enable Brown-out interrupt or reset function */\r
+ SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | (uint32_t)i32Mode;\r
+\r
+ /* Select Brown-out Detector threshold voltage */\r
+ SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel;\r
+}\r
+\r
+/**\r
+ * @brief Disable Brown-out detector function\r
+ * @param None\r
+ * @return None\r
+ * @details This function disable Brown-out detector function.\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void SYS_DisableBOD(void)\r
+{\r
+ SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set Power Level\r
+ * @param[in] u32PowerLevel is power level setting. Including :\r
+ * - \ref SYS_PLCTL_PLSEL_PL0\r
+ * - \ref SYS_PLCTL_PLSEL_PL1\r
+ * @return None\r
+ * @details This function select power level.\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void SYS_SetPowerLevel(uint32_t u32PowerLevel)\r
+{\r
+ /* Set power voltage level */\r
+ SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set Main Voltage Regulator Type\r
+ * @param[in] u32PowerRegulator is main voltage regulator type. Including :\r
+ * - \ref SYS_PLCTL_MVRS_LDO\r
+ * - \ref SYS_PLCTL_MVRS_DCDC\r
+ * @retval 0 main voltage regulator type setting is not finished\r
+ * @retval 1 main voltage regulator type setting is finished\r
+ * @details This function set main voltage regulator type.\r
+ * The main voltage regulator type setting to DCDC cannot finished if the inductor is not detected.\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+uint32_t SYS_SetPowerRegulator(uint32_t u32PowerRegulator)\r
+{\r
+ int32_t i32TimeOutCnt = 400;\r
+ uint32_t u32Ret = 1U;\r
+ uint32_t u32PowerRegStatus;\r
+\r
+ /* Get main voltage regulator type status */\r
+ u32PowerRegStatus = SYS->PLSTS & SYS_PLSTS_CURMVR_Msk;\r
+\r
+ /* Set main voltage regulator type */\r
+ if((u32PowerRegulator == SYS_PLCTL_MVRS_DCDC) && (u32PowerRegStatus == SYS_PLSTS_CURMVR_LDO))\r
+ {\r
+\r
+ /* Set main voltage regulator type to DCDC if status is LDO */\r
+ SYS->PLCTL |= SYS_PLCTL_MVRS_Msk;\r
+\r
+ /* Wait induction detection and main voltage regulator type change ready */\r
+ while((SYS->PLSTS & SYS_PLSTS_CURMVR_Msk) != SYS_PLSTS_CURMVR_DCDC)\r
+ {\r
+ if(i32TimeOutCnt-- <= 0)\r
+ {\r
+ u32Ret = 0U; /* Main voltage regulator type change time-out */\r
+ break;\r
+ }\r
+ }\r
+\r
+ }\r
+ else if(u32PowerRegulator == SYS_PLCTL_MVRS_LDO)\r
+ {\r
+\r
+ /* Set main voltage regulator type to LDO if status is DCDC */\r
+ SYS->PLCTL &= (~SYS_PLCTL_MVRS_Msk);\r
+\r
+ /* Wait main voltage regulator type change ready */\r
+ while((SYS->PLSTS & SYS_PLSTS_CURMVR_Msk) != SYS_PLSTS_CURMVR_LDO)\r
+ {\r
+ if(i32TimeOutCnt-- <= 0)\r
+ {\r
+ u32Ret = 0U; /* Main voltage regulator type change time-out */\r
+ break;\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+ /* Clear main voltage regulator type change error flag */\r
+ if(SYS->PLSTS & SYS_PLSTS_MVRCERR_Msk)\r
+ {\r
+ SYS->PLSTS = SYS_PLSTS_MVRCERR_Msk;\r
+ u32Ret = 0U;\r
+ }\r
+\r
+ return u32Ret;\r
+}\r
+\r
+/**\r
+ * @brief Set System SRAM Power Mode\r
+ * @param[in] u32SRAMSel is SRAM region selection. Including :\r
+ * - \ref SYS_SRAMPCTL_SRAM0PM0_Msk\r
+ * - \ref SYS_SRAMPCTL_SRAM0PM1_Msk\r
+ * - \ref SYS_SRAMPCTL_SRAM0PM2_Msk\r
+ * - \ref SYS_SRAMPCTL_SRAM0PM3_Msk\r
+ * - \ref SYS_SRAMPCTL_SRAM1PM0_Msk\r
+ * - \ref SYS_SRAMPCTL_SRAM1PM1_Msk\r
+ * - \ref SYS_SRAMPCTL_SRAM1PM2_Msk\r
+ * - \ref SYS_SRAMPCTL_SRAM1PM3_Msk\r
+ * @param[in] u32PowerMode is SRAM power mode. Including :\r
+ * - \ref SYS_SRAMPCTL_SRAM_NORMAL\r
+ * - \ref SYS_SRAMPCTL_SRAM_RETENTION\r
+ * - \ref SYS_SRAMPCTL_SRAM_POWER_SHUT_DOWN\r
+ * @return None\r
+ * @details This function set system SRAM power mode.\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void SYS_SetSSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode)\r
+{\r
+ uint32_t u32SRAMSelPos = 8UL;\r
+\r
+ /* Get system SRAM power mode setting position */\r
+ while(u32SRAMSelPos < 24UL)\r
+ {\r
+ if(u32SRAMSel & (1 << u32SRAMSelPos))\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ u32SRAMSelPos++;\r
+ }\r
+ }\r
+\r
+ /* Set system SRAM power mode setting */\r
+ SYS->SRAMPCTL = (SYS->SRAMPCTL & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos);\r
+}\r
+\r
+/**\r
+ * @brief Set Peripheral SRAM Power Mode\r
+ * @param[in] u32SRAMSel is SRAM region selection. Including :\r
+ * - \ref SYS_SRAMPPCT_CAN_Msk\r
+ * - \ref SYS_SRAMPPCT_USBD_Msk\r
+ * - \ref SYS_SRAMPPCT_PDMA0_Msk\r
+ * - \ref SYS_SRAMPPCT_PDMA1_Msk\r
+ * - \ref SYS_SRAMPPCT_FMC_Msk\r
+ * @param[in] u32PowerMode is SRAM power mode. Including :\r
+ * - \ref SYS_SRAMPPCT_SRAM_NORMAL\r
+ * - \ref SYS_SRAMPPCT_SRAM_RETENTION\r
+ * - \ref SYS_SRAMPPCT_SRAM_POWER_SHUT_DOWN\r
+ * @return None\r
+ * @details This function set peripheral SRAM power mode.\r
+ * The register write-protection function should be disabled before using this function.\r
+ */\r
+void SYS_SetPSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode)\r
+{\r
+ uint32_t u32SRAMSelPos = 0UL;\r
+\r
+ /* Get peripheral SRAM power mode setting position */\r
+ while(u32SRAMSelPos < 10UL)\r
+ {\r
+ if(u32SRAMSel & (1 << u32SRAMSelPos))\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ u32SRAMSelPos++;\r
+ }\r
+ }\r
+\r
+ /* Set peripheral SRAM power mode setting */\r
+ SYS->SRAMPPCT = (SYS->SRAMPPCT & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos);\r
+}\r
+\r
+\r
+/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group SYS_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file timer.c\r
+ * @version V3.00\r
+ * @brief Timer Controller(Timer) driver source file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup TIMER_Driver TIMER Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Open Timer with Operate Mode and Frequency\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32Mode Operation mode. Possible options are\r
+ * - \ref TIMER_ONESHOT_MODE\r
+ * - \ref TIMER_PERIODIC_MODE\r
+ * - \ref TIMER_TOGGLE_MODE\r
+ * - \ref TIMER_CONTINUOUS_MODE\r
+ * @param[in] u32Freq Target working frequency\r
+ *\r
+ * @return Real timer working frequency\r
+ *\r
+ * @details This API is used to configure timer to operate in specified mode and frequency.\r
+ * If timer cannot work in target frequency, a closest frequency will be chose and returned.\r
+ * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling\r
+ * \ref TIMER_Start macro or program registers directly.\r
+ */\r
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)\r
+{\r
+ uint32_t u32Clk = TIMER_GetModuleClock(timer);\r
+ uint32_t u32Cmpr = 0UL, u32Prescale = 0UL;\r
+\r
+ /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */\r
+ if(u32Freq > (u32Clk / 2UL))\r
+ {\r
+ u32Cmpr = 2UL;\r
+ }\r
+ else\r
+ {\r
+ u32Cmpr = u32Clk / u32Freq;\r
+ u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */\r
+ if (u32Prescale > 0UL)\r
+ u32Cmpr = u32Cmpr / (u32Prescale + 1UL);\r
+ }\r
+\r
+ timer->CTL = u32Mode | u32Prescale;\r
+ timer->CMP = u32Cmpr;\r
+\r
+ return(u32Clk / (u32Cmpr * (u32Prescale + 1UL)));\r
+}\r
+\r
+/**\r
+ * @brief Stop Timer Counting\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API stops timer counting and disable all timer interrupt function.\r
+ */\r
+void TIMER_Close(TIMER_T *timer)\r
+{\r
+ timer->CTL = 0UL;\r
+ timer->EXTCTL = 0UL;\r
+}\r
+\r
+/**\r
+ * @brief Create a specify Delay Time\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second).\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode.\r
+ * @note This API overwrites the register setting of the timer used to count the delay time.\r
+ * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay.\r
+ */\r
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)\r
+{\r
+ uint32_t u32Clk = TIMER_GetModuleClock(timer);\r
+ uint32_t u32Prescale = 0UL, u32Delay = (SystemCoreClock / u32Clk) + 1UL;\r
+ uint32_t u32Cmpr, u32NsecPerTick;\r
+\r
+ /* Clear current timer configuration */\r
+ timer->CTL = 0UL;\r
+ timer->EXTCTL = 0UL;\r
+\r
+ if(u32Clk <= 1000000UL) /* min delay is 1000 us if timer clock source is <= 1 MHz */\r
+ {\r
+ if(u32Usec < 1000UL)\r
+ {\r
+ u32Usec = 1000UL;\r
+ }\r
+ if(u32Usec > 1000000UL)\r
+ {\r
+ u32Usec = 1000000UL;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(u32Usec < 100UL)\r
+ {\r
+ u32Usec = 100UL;\r
+ }\r
+ if(u32Usec > 1000000UL)\r
+ {\r
+ u32Usec = 1000000UL;\r
+ }\r
+ }\r
+\r
+ if(u32Clk <= 1000000UL)\r
+ {\r
+ u32Prescale = 0UL;\r
+ u32NsecPerTick = 1000000000UL / u32Clk;\r
+ u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick;\r
+ }\r
+ else\r
+ {\r
+ u32Cmpr = u32Usec * (u32Clk / 1000000UL);\r
+ u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */\r
+ if (u32Prescale > 0UL)\r
+ u32Cmpr = u32Cmpr / (u32Prescale + 1UL);\r
+ }\r
+\r
+ timer->CMP = u32Cmpr;\r
+ timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale;\r
+\r
+ /*\r
+ When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.\r
+ And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.\r
+ */\r
+ for(; u32Delay > 0UL; u32Delay--)\r
+ {\r
+ __NOP();\r
+ }\r
+\r
+ while(timer->CTL & TIMER_CTL_ACTSTS_Msk) {}\r
+}\r
+\r
+/**\r
+ * @brief Enable Timer Capture Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32CapMode Timer capture mode. Could be\r
+ * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE\r
+ * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE\r
+ * @param[in] u32Edge Timer capture trigger edge. Possible values are\r
+ * - \ref TIMER_CAPTURE_EVENT_FALLING\r
+ * - \ref TIMER_CAPTURE_EVENT_RISING\r
+ * - \ref TIMER_CAPTURE_EVENT_FALLING_RISING\r
+ * - \ref TIMER_CAPTURE_EVENT_RISING_FALLING\r
+ * - \ref TIMER_CAPTURE_EVENT_GET_LOW_PERIOD\r
+ * - \ref TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to enable timer capture function with specify capture trigger edge \n\r
+ * to get current counter value or reset counter value to 0.\r
+ * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly.\r
+ */\r
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)\r
+{\r
+ timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) |\r
+ u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable Timer Capture Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to disable the timer capture function.\r
+ */\r
+void TIMER_DisableCapture(TIMER_T *timer)\r
+{\r
+ timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable Timer Counter Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32Edge Detection edge of counter pin. Could be ether\r
+ * - \ref TIMER_COUNTER_EVENT_FALLING, or\r
+ * - \ref TIMER_COUNTER_EVENT_RISING\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable the timer counter function with specify detection edge.\r
+ * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.\r
+ * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.\r
+ */\r
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)\r
+{\r
+ timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;\r
+ timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable Timer Counter Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This API is used to disable the timer event counter function.\r
+ */\r
+void TIMER_DisableEventCounter(TIMER_T *timer)\r
+{\r
+ timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Get Timer Clock Frequency\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return Timer clock frequency\r
+ *\r
+ * @details This API is used to get the timer clock frequency.\r
+ * @note This API cannot return correct clock rate if timer source is from external clock input.\r
+ */\r
+uint32_t TIMER_GetModuleClock(TIMER_T *timer)\r
+{\r
+ uint32_t u32Src, u32Clk = __HIRC;\r
+ const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC};\r
+\r
+ if(timer == TIMER0)\r
+ {\r
+ u32Src = CLK_GetModuleClockSource(TMR0_MODULE);\r
+ }\r
+ else if(timer == TIMER1)\r
+ {\r
+ u32Src = CLK_GetModuleClockSource(TMR1_MODULE);\r
+ }\r
+ else if((timer == TIMER2) || (timer == TIMER2_NS))\r
+ {\r
+ u32Src = CLK_GetModuleClockSource(TMR2_MODULE);\r
+ }\r
+ else if((timer == TIMER3) || (timer == TIMER3_NS))\r
+ {\r
+ u32Src = CLK_GetModuleClockSource(TMR3_MODULE);\r
+ }\r
+ else\r
+ {\r
+ u32Clk = 0UL;\r
+ }\r
+\r
+ if(u32Clk == 0UL)\r
+ {\r
+ ; /* Invalid timer channel */\r
+ }\r
+ else\r
+ {\r
+ if(u32Src == 2UL)\r
+ {\r
+ if((timer == TIMER0) || (timer == TIMER1))\r
+ {\r
+ u32Clk = CLK_GetPCLK0Freq();\r
+ }\r
+ else\r
+ {\r
+ u32Clk = CLK_GetPCLK1Freq();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ u32Clk = au32Clk[u32Src];\r
+ }\r
+ }\r
+\r
+ return u32Clk;\r
+}\r
+\r
+/**\r
+ * @brief Enable Timer Frequency Counter Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32DropCount This parameter has no effect in this BSP\r
+ * @param[in] u32Timeout This parameter has no effect in this BSP\r
+ * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to calculate input event frequency. After enable\r
+ * this function, a pair of timers, TIMER0 and TIMER1, or TIMER2 and TIMER3\r
+ * will be configured for this function. The mode used to calculate input\r
+ * event frequency is mentioned as "Inter Timer Trigger Mode" in Technical\r
+ * Reference Manual.\r
+ */\r
+void TIMER_EnableFreqCounter(TIMER_T *timer,\r
+ uint32_t u32DropCount,\r
+ uint32_t u32Timeout,\r
+ uint32_t u32EnableInt)\r
+{\r
+ TIMER_T *t; /* store the timer base to configure compare value */\r
+\r
+ if(timer == TIMER0)\r
+ {\r
+ t = TIMER1;\r
+ }\r
+ else if(timer == TIMER2)\r
+ {\r
+ t = TIMER3;\r
+ }\r
+ else if(timer == TIMER2_NS)\r
+ {\r
+ t = TIMER3_NS;\r
+ }\r
+ else\r
+ {\r
+ t = 0UL ;\r
+ }\r
+\r
+ if(t != 0UL)\r
+ {\r
+ t->CMP = 0xFFFFFFUL;\r
+ t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL;\r
+ timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable Timer Frequency Counter Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @brief This function is used to disable the Timer frequency counter function.\r
+ */\r
+void TIMER_DisableFreqCounter(TIMER_T *timer)\r
+{\r
+ timer->CTL &= ~TIMER_CTL_INTRGEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Select Interrupt Source to Trigger others Module\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be:\r
+ * - \ref TIMER_TRGSRC_TIMEOUT_EVENT\r
+ * - \ref TIMER_TRGSRC_CAPTURE_EVENT\r
+ *\r
+ * @return None\r
+ *\r
+ * @brief This function is used to select the interrupt source used to trigger other modules.\r
+ */\r
+void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src)\r
+{\r
+ timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src;\r
+}\r
+\r
+/**\r
+ * @brief Set Modules Trigger by Timer Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32Mask The mask of modules (EPWM, EADC, DAC and PDMA) trigger by timer. Is the combination of\r
+ * - \ref TIMER_TRG_TO_EPWM,\r
+ * - \ref TIMER_TRG_TO_EADC,\r
+ * - \ref TIMER_TRG_TO_DAC and\r
+ * - \ref TIMER_TRG_TO_PDMA\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to set EPWM, EADC, DAC and PDMA module triggered by timer interrupt event.\r
+ */\r
+void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask)\r
+{\r
+ timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGEPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask;\r
+}\r
+\r
+/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group TIMER_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file timer.c\r
+ * @version V3.00\r
+ * @brief Timer PWM Controller(Timer PWM) driver source file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Set PWM Counter Clock Source\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32CntClkSrc PWM counter clock source, could be one of following source\r
+ * - \ref TPWM_CNTR_CLKSRC_TMR_CLK\r
+ * - \ref TPWM_CNTR_CLKSRC_TIMER0_INT\r
+ * - \ref TPWM_CNTR_CLKSRC_TIMER1_INT\r
+ * - \ref TPWM_CNTR_CLKSRC_TIMER2_INT\r
+ * - \ref TPWM_CNTR_CLKSRC_TIMER3_INT\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to set PWM counter clock source.\r
+ */\r
+void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc)\r
+{\r
+ (timer)->PWMCLKSRC = ((timer)->PWMCLKSRC & ~TIMER_PWMCLKSRC_CLKSRC_Msk) | u32CntClkSrc;\r
+}\r
+\r
+/**\r
+ * @brief Configure PWM Output Frequency and Duty Cycle\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32Frequency Target generator frequency.\r
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%...\r
+ *\r
+ * @return Nearest frequency clock in nano second\r
+ *\r
+ * @details This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode.\r
+ * @note This API is only available if Timer PWM counter clock source is from TMRx_CLK.\r
+ */\r
+uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle)\r
+{\r
+ uint32_t u32PWMClockFreq, u32TargetFreq;\r
+ uint32_t u32Prescaler = 0x1000UL, u32Period, u32CMP;\r
+\r
+ if((timer == TIMER0) || (timer == TIMER1))\r
+ {\r
+ u32PWMClockFreq = CLK_GetPCLK0Freq();\r
+ }\r
+ else\r
+ {\r
+ u32PWMClockFreq = CLK_GetPCLK1Freq();\r
+ }\r
+\r
+ /* Calculate u16PERIOD and u16PSC */\r
+ for(u32Prescaler = 1UL; u32Prescaler <= 0x1000UL; u32Prescaler++)\r
+ {\r
+ u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency;\r
+\r
+ /* If target u32Period is larger than 0x10000, need to use a larger prescaler */\r
+ if(u32Period <= 0x10000UL)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ /* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */\r
+ u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period;\r
+\r
+ /* Set PWM to up count type */\r
+ timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (TPWM_UP_COUNT << TIMER_PWMCTL_CNTTYPE_Pos);\r
+\r
+ /* Set PWM to auto-reload mode */\r
+ timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | (TPWM_AUTO_RELOAD_MODE << TIMER_PWMCTL_CNTMODE_Pos);\r
+\r
+ /* Convert to real register value */\r
+ TPWM_SET_PERIOD(timer, (u32Period - 1UL));\r
+ if(u32DutyCycle)\r
+ {\r
+ u32CMP = (u32DutyCycle * u32Period) / 100UL;\r
+ }\r
+ else\r
+ {\r
+ u32CMP = 0UL;\r
+ }\r
+\r
+ TPWM_SET_CMPDAT(timer, u32CMP);\r
+\r
+ TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL));\r
+\r
+ return (u32TargetFreq);\r
+}\r
+\r
+/**\r
+ * @brief Enable Dead-Time Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable Dead-Time function and counter source is the same as Timer PWM clock source.\r
+ * @note The register write-protection function should be disabled before using this function.\r
+ */\r
+void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount)\r
+{\r
+ timer->PWMDTCTL = TIMER_PWMDTCTL_DTEN_Msk | u32DTCount;\r
+}\r
+\r
+/**\r
+ * @brief Enable Dead-Time Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable Dead-Time function and counter source is the Timer PWM clock source with prescale.\r
+ * @note The register write-protection function should be disabled before using this function.\r
+ */\r
+void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount)\r
+{\r
+ timer->PWMDTCTL = TIMER_PWMDTCTL_DTCKSEL_Msk | TIMER_PWMDTCTL_DTEN_Msk | u32DTCount;\r
+}\r
+\r
+/**\r
+ * @brief Disable Dead-Time Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable Dead-time of selected channel.\r
+ * @note The register write-protection function should be disabled before using this function.\r
+ */\r
+void TPWM_DisableDeadTime(TIMER_T *timer)\r
+{\r
+ timer->PWMDTCTL = 0x0UL;\r
+}\r
+\r
+/**\r
+ * @brief Enable PWM Counter\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable PWM generator and start counter counting.\r
+ */\r
+void TPWM_EnableCounter(TIMER_T *timer)\r
+{\r
+ timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable PWM Generator\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit.\r
+ */\r
+void TPWM_DisableCounter(TIMER_T *timer)\r
+{\r
+ timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable Trigger ADC\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32Condition The condition to trigger ADC. It could be one of following conditions:\r
+ * - \ref TPWM_TRIGGER_ADC_AT_ZERO_POINT\r
+ * - \ref TPWM_TRIGGER_ADC_AT_PERIOD_POINT\r
+ * - \ref TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT\r
+ * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT\r
+ * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable specified counter compare event to trigger ADC.\r
+ */\r
+void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition)\r
+{\r
+ timer->PWMEADCTS = TIMER_PWMEADCTS_TRGEN_Msk | u32Condition;\r
+}\r
+\r
+/**\r
+ * @brief Disable Trigger ADC\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable counter compare event to trigger ADC.\r
+ */\r
+void TPWM_DisableTriggerADC(TIMER_T *timer)\r
+{\r
+ timer->PWMEADCTS = 0x0UL;\r
+}\r
+\r
+/**\r
+ * @brief Enable Fault Brake Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32CH0Level PWMx_CH0 output level while fault brake event occurs. Valid value is one of following setting\r
+ * - \ref TPWM_OUTPUT_TOGGLE\r
+ * - \ref TPWM_OUTPUT_NOTHING\r
+ * - \ref TPWM_OUTPUT_LOW\r
+ * - \ref TPWM_OUTPUT_HIGH\r
+ * @param[in] u32CH1Level PWMx_CH1 output level while fault brake event occurs. Valid value is one of following setting\r
+ * - \ref TPWM_OUTPUT_TOGGLE\r
+ * - \ref TPWM_OUTPUT_NOTHING\r
+ * - \ref TPWM_OUTPUT_LOW\r
+ * - \ref TPWM_OUTPUT_HIGH\r
+ * @param[in] u32BrakeSource Fault brake source, combination of following source\r
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP0\r
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP1\r
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_BKPIN\r
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_CSS\r
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_BOD\r
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_COR\r
+ * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_RAM\r
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP0\r
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP1\r
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_BKPIN\r
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS\r
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD\r
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_COR\r
+ * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable fault brake function.\r
+ * @note The register write-protection function should be disabled before using this function.\r
+ */\r
+void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource)\r
+{\r
+ timer->PWMFAILBRK |= ((u32BrakeSource >> 16) & 0xFUL);\r
+ timer->PWMBRKCTL = (timer->PWMBRKCTL & ~(TIMER_PWMBRKCTL_BRKAEVEN_Msk | TIMER_PWMBRKCTL_BRKAODD_Msk)) |\r
+ (u32BrakeSource & 0xFFFFUL) | (u32CH0Level << TIMER_PWMBRKCTL_BRKAEVEN_Pos) | (u32CH1Level << TIMER_PWMBRKCTL_BRKAODD_Pos);\r
+}\r
+\r
+/**\r
+ * @brief Enable Fault Brake Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32IntSource Interrupt source, could be one of following source\r
+ * - \ref TPWM_BRAKE_EDGE\r
+ * - \ref TPWM_BRAKE_LEVEL\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable fault brake interrupt.\r
+ * @note The register write-protection function should be disabled before using this function.\r
+ */\r
+void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource)\r
+{\r
+ timer->PWMINTEN1 |= u32IntSource;\r
+}\r
+\r
+/**\r
+ * @brief Disable Fault Brake Interrupt\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32IntSource Interrupt source, could be one of following source\r
+ * - \ref TPWM_BRAKE_EDGE\r
+ * - \ref TPWM_BRAKE_LEVEL\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable fault brake interrupt.\r
+ * @note The register write-protection function should be disabled before using this function.\r
+ */\r
+void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource)\r
+{\r
+ timer->PWMINTEN1 &= ~u32IntSource;\r
+}\r
+\r
+/**\r
+ * @brief Indicate Fault Brake Interrupt Flag\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32IntSource Interrupt source, could be one of following source\r
+ * - \ref TPWM_BRAKE_EDGE\r
+ * - \ref TPWM_BRAKE_LEVEL\r
+ *\r
+ * @return Fault brake interrupt flag of specified source\r
+ * @retval 0 Fault brake interrupt did not occurred\r
+ * @retval 1 Fault brake interrupt occurred\r
+ *\r
+ * @details This function is used to indicate fault brake interrupt flag occurred or not of selected source.\r
+ */\r
+uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource)\r
+{\r
+ return ((timer->PWMINTSTS1 & (0x3UL << u32IntSource)) ? 1UL : 0UL);\r
+}\r
+\r
+/**\r
+ * @brief Clear Fault Brake Interrupt Flags\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32IntSource Interrupt source, could be one of following source\r
+ * - \ref TPWM_BRAKE_EDGE\r
+ * - \ref TPWM_BRAKE_LEVEL\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to clear fault brake interrupt flags of selected source.\r
+ * @note The register write-protection function should be disabled before using this function.\r
+ */\r
+void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource)\r
+{\r
+ timer->PWMINTSTS1 = (0x3UL << u32IntSource);\r
+}\r
+\r
+/**\r
+ * @brief Enable Load Mode\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32LoadMode Timer PWM counter loading mode, could be one of following mode\r
+ * - \ref TPWM_LOAD_MODE_PERIOD\r
+ * - \ref TPWM_LOAD_MODE_IMMEDIATE\r
+ * - \ref TPWM_LOAD_MODE_CENTER\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable load mode of selected channel.\r
+ * @note The default loading mode is period loading mode.\r
+ */\r
+void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode)\r
+{\r
+ timer->PWMCTL = (timer->PWMCTL & ~(TIMER_PWMCTL_IMMLDEN_Msk | TIMER_PWMCTL_CTRLD_Msk)) | u32LoadMode;\r
+}\r
+\r
+/**\r
+ * @brief Enable Brake Pin Noise Filter Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32BrakePinSrc The external brake pin source, could be one of following source\r
+ * - \ref TPWM_TM_BRAKE0\r
+ * - \ref TPWM_TM_BRAKE1\r
+ * - \ref TPWM_TM_BRAKE2\r
+ * - \ref TPWM_TM_BRAKE3\r
+ * @param[in] u32DebounceCnt This value controls the real debounce sample time.\r
+ * The target debounce sample time is (debounce sample clock period) * (u32DebounceCnt).\r
+ * @param[in] u32ClkSrcSel Brake pin detector debounce clock source, could be one of following source\r
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_1\r
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_2\r
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_4\r
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_8\r
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_16\r
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_32\r
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_64\r
+ * - \ref TPWM_BKP_DBCLK_PCLK_DIV_128\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable external brake pin detector noise filter function.\r
+ */\r
+void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel)\r
+{\r
+ timer->PWMBNF = (timer->PWMBNF & ~(TIMER_PWMBNF_BKPINSRC_Msk | TIMER_PWMBNF_BRKFCNT_Msk | TIMER_PWMBNF_BRKNFSEL_Msk)) |\r
+ (u32BrakePinSrc << TIMER_PWMBNF_BKPINSRC_Pos) |\r
+ (u32DebounceCnt << TIMER_PWMBNF_BRKFCNT_Pos) |\r
+ (u32ClkSrcSel << TIMER_PWMBNF_BRKNFSEL_Pos) | TIMER_PWMBNF_BRKNFEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable Brake Pin Noise Filter Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable external brake pin detector noise filter function.\r
+ */\r
+void TPWM_DisableBrakePinDebounce(TIMER_T *timer)\r
+{\r
+ timer->PWMBNF &= ~TIMER_PWMBNF_BRKNFEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable Brake Pin Inverse Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to enable PWM brake pin inverse function.\r
+ */\r
+void TPWM_EnableBrakePinInverse(TIMER_T *timer)\r
+{\r
+ timer->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable Brake Pin Inverse Function\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to disable PWM brake pin inverse function.\r
+ */\r
+void TPWM_DisableBrakePinInverse(TIMER_T *timer)\r
+{\r
+ timer->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Set Brake Pin Source\r
+ *\r
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.\r
+ * @param[in] u32BrakePinNum Brake pin selection. One of the following:\r
+ * - \ref TPWM_TM_BRAKE0\r
+ * - \ref TPWM_TM_BRAKE1\r
+ * - \ref TPWM_TM_BRAKE2\r
+ * - \ref TPWM_TM_BRAKE3\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to set PWM brake pin source.\r
+ */\r
+void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum)\r
+{\r
+ timer->PWMBNF = (((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | (u32BrakePinNum << TIMER_PWMBNF_BKPINSRC_Pos));\r
+}\r
+\r
+\r
+/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group TIMER_PWM_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file uart.c\r
+ * @version V3.00\r
+ * @brief M2351 series UART Interface Controller (UART) driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+\r
+#include <stdio.h>\r
+#include "NuMicro.h"\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup UART_Driver UART Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Clear UART specified interrupt flag\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ * @param[in] u32InterruptFlag The specified interrupt of UART module.\r
+ * - \ref UART_INTSTS_LININT_Msk : LIN Bus interrupt\r
+ * - \ref UART_INTSTS_WKINT_Msk : Wake-up interrupt\r
+ * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt\r
+ * - \ref UART_INTSTS_MODEMINT_Msk : MODEM Status Interrupt\r
+ * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to clear UART specified interrupt flag.\r
+ */\r
+void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag)\r
+{\r
+\r
+ if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */\r
+ {\r
+ uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_ADDRDETF_Msk;\r
+ }\r
+\r
+ if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear MODEM Status Interrupt */\r
+ {\r
+ uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;\r
+ }\r
+\r
+ if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */\r
+ {\r
+ uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;\r
+ }\r
+\r
+ if(u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */\r
+ {\r
+ uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk |\r
+ UART_WKSTS_RFRTWKF_Msk | UART_WKSTS_RS485WKF_Msk |\r
+ UART_WKSTS_TOUTWKF_Msk;\r
+ }\r
+\r
+ if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */\r
+ {\r
+ uart->INTSTS = UART_INTSTS_LINIF_Msk;\r
+ uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk |\r
+ UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk |\r
+ UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ;\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable UART interrupt\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to disable UART interrupt.\r
+ */\r
+void UART_Close(UART_T* uart)\r
+{\r
+ uart->INTEN = 0ul;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable UART auto flow control function\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to disable UART auto flow control.\r
+ */\r
+void UART_DisableFlowCtrl(UART_T* uart)\r
+{\r
+ uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable UART specified interrupt\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ * @param[in] u32InterruptFlag The specified interrupt of UART module.\r
+ * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt\r
+ * - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt\r
+ * - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt\r
+ * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt\r
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt\r
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt\r
+ * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt\r
+ * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt\r
+ * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt\r
+ * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ.\r
+ */\r
+void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag)\r
+{\r
+ /* Disable UART specified interrupt */\r
+ UART_DISABLE_INT(uart, u32InterruptFlag);\r
+\r
+ /* Disable NVIC UART IRQ */\r
+ switch((uint32_t)uart)\r
+ {\r
+ case UART0_BASE:\r
+ case UART0_BASE+NS_OFFSET:\r
+ NVIC_DisableIRQ(UART0_IRQn);\r
+ break;\r
+ case UART1_BASE:\r
+ case UART1_BASE+NS_OFFSET:\r
+ NVIC_DisableIRQ(UART1_IRQn);\r
+ break;\r
+ case UART2_BASE:\r
+ case UART2_BASE+NS_OFFSET:\r
+ NVIC_DisableIRQ(UART2_IRQn);\r
+ break;\r
+ case UART3_BASE:\r
+ case UART3_BASE+NS_OFFSET:\r
+ NVIC_DisableIRQ(UART3_IRQn);\r
+ break;\r
+ case UART4_BASE:\r
+ case UART4_BASE+NS_OFFSET:\r
+ NVIC_DisableIRQ(UART4_IRQn);\r
+ break;\r
+ case UART5_BASE:\r
+ case UART5_BASE+NS_OFFSET:\r
+ NVIC_DisableIRQ(UART5_IRQn);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enable UART auto flow control function\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to Enable UART auto flow control.\r
+ */\r
+/**\r
+ * @brief Enable UART auto flow control function\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to Enable UART auto flow control.\r
+ */\r
+void UART_EnableFlowCtrl(UART_T* uart)\r
+{\r
+ /* Set RTS pin output is low level active */\r
+ uart->MODEM |= UART_MODEM_RTSACTLV_Msk;\r
+\r
+ /* Set CTS pin input is low level active */\r
+ uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;\r
+\r
+ /* Set RTS and CTS auto flow control enable */\r
+ uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enable UART specified interrupt\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ * @param[in] u32InterruptFlag The specified interrupt of UART module:\r
+ * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt\r
+ * - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt\r
+ * - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt\r
+ * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt\r
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt\r
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt\r
+ * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt\r
+ * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt\r
+ * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt\r
+ * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ.\r
+ */\r
+void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag)\r
+{\r
+\r
+ /* Enable UART specified interrupt */\r
+ UART_ENABLE_INT(uart, u32InterruptFlag);\r
+\r
+ /* Enable NVIC UART IRQ */\r
+ switch((uint32_t)uart)\r
+ {\r
+ case UART0_BASE:\r
+ case UART0_BASE+NS_OFFSET:\r
+ NVIC_EnableIRQ(UART0_IRQn);\r
+ break;\r
+ case UART1_BASE:\r
+ case UART1_BASE+NS_OFFSET:\r
+ NVIC_EnableIRQ(UART1_IRQn);\r
+ break;\r
+ case UART2_BASE:\r
+ case UART2_BASE+NS_OFFSET:\r
+ NVIC_EnableIRQ(UART2_IRQn);\r
+ break;\r
+ case UART3_BASE:\r
+ case UART3_BASE+NS_OFFSET:\r
+ NVIC_EnableIRQ(UART3_IRQn);\r
+ break;\r
+ case UART4_BASE:\r
+ case UART4_BASE+NS_OFFSET:\r
+ NVIC_EnableIRQ(UART4_IRQn);\r
+ break;\r
+ case UART5_BASE:\r
+ case UART5_BASE+NS_OFFSET:\r
+ NVIC_EnableIRQ(UART5_IRQn);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Open and set UART function\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ * @param[in] u32baudrate The baudrate of UART module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function use to enable UART function and set baud-rate.\r
+ */\r
+void UART_Open(UART_T* uart, uint32_t u32baudrate)\r
+{\r
+ uint32_t u32UartClkSrcSel, u32UartClkDivNum;\r
+ uint32_t au32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC};\r
+ uint32_t u32BaudDiv = 0ul;\r
+\r
+ /* Get UART clock source selection and UART clock divider number */\r
+ switch((uint32_t)uart)\r
+ {\r
+ case UART0_BASE:\r
+ case UART0_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE);\r
+ break;\r
+ case UART1_BASE:\r
+ case UART1_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE);\r
+ break;\r
+ case UART2_BASE:\r
+ case UART2_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE);\r
+ break;\r
+ case UART3_BASE:\r
+ case UART3_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE);\r
+ break;\r
+ case UART4_BASE:\r
+ case UART4_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE);\r
+ break;\r
+ case UART5_BASE:\r
+ case UART5_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Select UART function */\r
+ uart->FUNCSEL = UART_FUNCSEL_UART;\r
+\r
+ /* Set UART line configuration */\r
+ uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;\r
+\r
+ /* Set UART Rx and RTS trigger level */\r
+ uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);\r
+\r
+ /* Get PLL clock frequency if UART clock source selection is PLL */\r
+ if(u32UartClkSrcSel == 1ul)\r
+ {\r
+ au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();\r
+ }\r
+\r
+ /* Set UART baud rate */\r
+ if(u32baudrate != 0ul)\r
+ {\r
+ u32BaudDiv = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);\r
+\r
+ if(u32BaudDiv > 0xFFFFul)\r
+ {\r
+ uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));\r
+ }\r
+ else\r
+ {\r
+ uart->BAUD = (UART_BAUD_MODE2 | u32BaudDiv);\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Read UART data\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO.\r
+ * @param[in] u32ReadBytes The the read bytes number of data.\r
+ *\r
+ * @return u32Count Receive byte count\r
+ *\r
+ * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.\r
+ */\r
+uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)\r
+{\r
+ uint32_t u32Count, u32delayno;\r
+ uint32_t u32Exit = 0ul;\r
+\r
+ for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)\r
+ {\r
+ u32delayno = 0ul;\r
+\r
+ while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */\r
+ {\r
+ u32delayno++;\r
+ if(u32delayno >= 0x40000000ul)\r
+ {\r
+ u32Exit = 1ul;\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ }\r
+ }\r
+\r
+ if(u32Exit == 1ul)\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */\r
+ }\r
+ }\r
+\r
+ return u32Count;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set UART line configuration\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ * @param[in] u32baudrate The register value of baudrate of UART module.\r
+ * If u32baudrate = 0, UART baudrate will not change.\r
+ * @param[in] u32data_width The data length of UART module.\r
+ * - \ref UART_WORD_LEN_5\r
+ * - \ref UART_WORD_LEN_6\r
+ * - \ref UART_WORD_LEN_7\r
+ * - \ref UART_WORD_LEN_8\r
+ * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module.\r
+ * - \ref UART_PARITY_NONE\r
+ * - \ref UART_PARITY_ODD\r
+ * - \ref UART_PARITY_EVEN\r
+ * - \ref UART_PARITY_MARK\r
+ * - \ref UART_PARITY_SPACE\r
+ * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module.\r
+ * - \ref UART_STOP_BIT_1\r
+ * - \ref UART_STOP_BIT_1_5\r
+ * - \ref UART_STOP_BIT_2\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function use to config UART line setting.\r
+ */\r
+void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)\r
+{\r
+ uint32_t u32UartClkSrcSel, u32UartClkDivNum;\r
+ uint32_t au32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC};\r
+ uint32_t u32BaudDiv = 0ul;\r
+\r
+ /* Get UART clock source selection and UART clock divider number */\r
+ switch((uint32_t)uart)\r
+ {\r
+ case UART0_BASE:\r
+ case UART0_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE);\r
+ break;\r
+ case UART1_BASE:\r
+ case UART1_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE);\r
+ break;\r
+ case UART2_BASE:\r
+ case UART2_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE);\r
+ break;\r
+ case UART3_BASE:\r
+ case UART3_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE);\r
+ break;\r
+ case UART4_BASE:\r
+ case UART4_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE);\r
+ break;\r
+ case UART5_BASE:\r
+ case UART5_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Get PLL clock frequency if UART clock source selection is PLL */\r
+ if(u32UartClkSrcSel == 1ul)\r
+ {\r
+ au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();\r
+ }\r
+\r
+ /* Set UART baud rate */\r
+ if(u32baudrate != 0ul)\r
+ {\r
+ u32BaudDiv = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);\r
+\r
+ if(u32BaudDiv > 0xFFFFul)\r
+ {\r
+ uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));\r
+ }\r
+ else\r
+ {\r
+ uart->BAUD = (UART_BAUD_MODE2 | u32BaudDiv);\r
+ }\r
+ }\r
+\r
+ /* Set UART line configuration */\r
+ uart->LINE = u32data_width | u32parity | u32stop_bits;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set Rx timeout count\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ * @param[in] u32TOC Rx timeout counter.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function use to set Rx timeout count.\r
+ */\r
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)\r
+{\r
+ /* Set time-out interrupt comparator */\r
+ uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);\r
+\r
+ /* Set time-out counter enable */\r
+ uart->INTEN |= UART_INTEN_TOCNTEN_Msk;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Select and configure IrDA function\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ * @param[in] u32Buadrate The baudrate of UART module.\r
+ * @param[in] u32Direction The direction of UART module in IrDA mode:\r
+ * - \ref UART_IRDA_TXEN\r
+ * - \ref UART_IRDA_RXEN\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.\r
+ */\r
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)\r
+{\r
+ uint32_t u32UartClkSrcSel, u32UartClkDivNum;\r
+ uint32_t au32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC};\r
+ uint32_t u32BaudDiv;\r
+\r
+ /* Select IrDA function mode */\r
+ uart->FUNCSEL = UART_FUNCSEL_IrDA;\r
+\r
+ /* Get UART clock source selection and UART clock divider number */\r
+ switch((uint32_t)uart)\r
+ {\r
+ case UART0_BASE:\r
+ case UART0_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE);\r
+ break;\r
+ case UART1_BASE:\r
+ case UART1_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE);\r
+ break;\r
+ case UART2_BASE:\r
+ case UART2_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE);\r
+ break;\r
+ case UART3_BASE:\r
+ case UART3_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE);\r
+ break;\r
+ case UART4_BASE:\r
+ case UART4_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE);\r
+ break;\r
+ case UART5_BASE:\r
+ case UART5_BASE+NS_OFFSET:\r
+ u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE);\r
+ u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Get PLL clock frequency if UART clock source selection is PLL */\r
+ if(u32UartClkSrcSel == 1ul)\r
+ {\r
+ au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();\r
+ }\r
+\r
+ /* Set UART IrDA baud rate in mode 0 */\r
+ if(u32Buadrate != 0ul)\r
+ {\r
+ u32BaudDiv = UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate);\r
+\r
+ if(u32BaudDiv < 0xFFFFul)\r
+ {\r
+ uart->BAUD = (UART_BAUD_MODE0 | u32BaudDiv);\r
+ }\r
+ }\r
+\r
+ /* Configure IrDA relative settings */\r
+ if(u32Direction == UART_IRDA_RXEN)\r
+ {\r
+ uart->IRDA |= UART_IRDA_RXINV_Msk; /* Rx signal is inverse */\r
+ uart->IRDA &= ~UART_IRDA_TXEN_Msk;\r
+ }\r
+ else\r
+ {\r
+ uart->IRDA &= ~UART_IRDA_TXINV_Msk; /* Tx signal is not inverse */\r
+ uart->IRDA |= UART_IRDA_TXEN_Msk;\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Select and configure RS485 function\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ * @param[in] u32Mode The operation mode(NMM/AUD/AAD).\r
+ * - \ref UART_ALTCTL_RS485NMM_Msk\r
+ * - \ref UART_ALTCTL_RS485AUD_Msk\r
+ * - \ref UART_ALTCTL_RS485AAD_Msk\r
+ * @param[in] u32Addr The RS485 address.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to set RS485 relative setting.\r
+ */\r
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)\r
+{\r
+ /* Select UART RS485 function mode */\r
+ uart->FUNCSEL = UART_FUNCSEL_RS485;\r
+\r
+ /* Set RS585 configuration */\r
+ uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);\r
+ uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Select and configure LIN function\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ * @param[in] u32Mode The LIN direction :\r
+ * - \ref UART_ALTCTL_LINTXEN_Msk\r
+ * - \ref UART_ALTCTL_LINRXEN_Msk\r
+ * @param[in] u32BreakLength The breakfield length.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to set LIN relative setting.\r
+ */\r
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)\r
+{\r
+ /* Select LIN function mode */\r
+ uart->FUNCSEL = UART_FUNCSEL_LIN;\r
+\r
+ /* Select LIN function setting : Tx enable, Rx enable and break field length */\r
+ uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);\r
+ uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Write UART data\r
+ *\r
+ * @param[in] uart The pointer of the specified UART module.\r
+ * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO.\r
+ * @param[out] u32WriteBytes The byte number of data.\r
+ *\r
+ * @return u32Count transfer byte count\r
+ *\r
+ * @details The function is to write data into TX buffer to transmit data by UART.\r
+ */\r
+uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)\r
+{\r
+ uint32_t u32Count, u32delayno;\r
+ uint32_t u32Exit = 0ul;\r
+\r
+ for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)\r
+ {\r
+ u32delayno = 0ul;\r
+ while((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) == 0ul) /* Wait Tx empty and Time-out manner */\r
+ {\r
+ u32delayno++;\r
+ if(u32delayno >= 0x40000000ul)\r
+ {\r
+ u32Exit = 1ul;\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ }\r
+ }\r
+\r
+ if(u32Exit == 1ul)\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */\r
+ }\r
+ }\r
+\r
+ return u32Count;\r
+}\r
+\r
+\r
+/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group UART_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file usbd.c\r
+ * @version V3.00\r
+ * @brief M2351 series USBD driver source file\r
+ *\r
+ * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+\r
+#include <string.h>\r
+#include "NuMicro.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USBD_Driver USBD Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions\r
+ @{\r
+*/\r
+\r
+/* Global variables for Control Pipe */\r
+uint8_t g_USBD_au8SetupPacket[8] = {0UL}; /*!< Setup packet buffer */\r
+volatile uint8_t g_USBD_u8RemoteWakeupEn = 0UL; /*!< Remote wake up function enable flag */\r
+\r
+/**\r
+ * @cond HIDDEN_SYMBOLS\r
+ */\r
+static uint8_t *g_USBD_pu8CtrlInPointer = 0;\r
+static uint8_t *g_USBD_pu8CtrlOutPointer = 0;\r
+static volatile uint32_t g_USBD_u32CtrlInSize = 0UL;\r
+static volatile uint32_t g_USBD_u32CtrlOutSize = 0UL;\r
+static volatile uint32_t g_USBD_u32CtrlOutSizeLimit = 0UL;\r
+static volatile uint32_t g_USBD_u32UsbAddr = 0UL;\r
+static volatile uint32_t g_USBD_u32UsbConfig = 0UL;\r
+static volatile uint32_t g_USBD_u32CtrlMaxPktSize = 8UL;\r
+static volatile uint32_t g_USBD_u32UsbAltInterface = 0UL;\r
+static volatile uint8_t g_USBD_u8CtrlInZeroFlag = 0UL;\r
+/**\r
+ * @endcond\r
+ */\r
+\r
+const S_USBD_INFO_T *g_USBD_sInfo; /*!< A pointer for USB information structure */\r
+\r
+VENDOR_REQ g_USBD_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */\r
+CLASS_REQ g_USBD_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */\r
+SET_INTERFACE_REQ g_USBD_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */\r
+SET_CONFIG_CB g_USBD_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */\r
+uint32_t g_USBD_u32EpStallLock = 0UL; /*!< Bit map flag to lock specified EP when SET_FEATURE */\r
+\r
+/**\r
+ * @brief This function makes USBD module to be ready to use\r
+ *\r
+ * @param[in] param The structure of USBD information.\r
+ * @param[in] pfnClassReq USB Class request callback function.\r
+ * @param[in] pfnSetInterface USB Set Interface request callback function.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus.\r
+ */\r
+void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface)\r
+{\r
+ USBD_T *pUSBD;\r
+\r
+ if((__PC() & NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pUSBD = USBD_NS;\r
+ }\r
+ else\r
+ {\r
+ pUSBD = USBD;\r
+ }\r
+\r
+ g_USBD_sInfo = param;\r
+ g_USBD_pfnClassRequest = pfnClassReq;\r
+ g_USBD_pfnSetInterface = pfnSetInterface;\r
+\r
+ /* get EP0 maximum packet size */\r
+ g_USBD_u32CtrlMaxPktSize = g_USBD_sInfo->gu8DevDesc[7];\r
+\r
+ /* Initial USB engine */\r
+#ifdef SUPPORT_LPM\r
+ pUSBD->ATTR = 0x7D0UL | USBD_LPMACK;\r
+#else\r
+ pUSBD->ATTR = 0x7D0UL;\r
+#endif\r
+ /* Force SE0 */\r
+ USBD_SET_SE0();\r
+}\r
+\r
+/**\r
+ * @brief This function makes USB host to recognize the device\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer.\r
+ */\r
+void USBD_Start(void)\r
+{\r
+ /* Disable software-disconnect function */\r
+ USBD_CLR_SE0();\r
+\r
+ /* Clear USB-related interrupts before enable interrupt */\r
+ USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);\r
+\r
+ /* Enable USB-related interrupts. */\r
+ USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);\r
+}\r
+\r
+/**\r
+ * @brief Get the received SETUP packet\r
+ *\r
+ * @param[in] buf A buffer pointer used to store 8-byte SETUP packet.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Store SETUP packet to a user-specified buffer.\r
+ *\r
+ */\r
+void USBD_GetSetupPacket(uint8_t *buf)\r
+{\r
+ USBD_MemCopy(buf, g_USBD_au8SetupPacket, 8UL);\r
+}\r
+\r
+/**\r
+ * @brief Process SETUP packet\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Parse SETUP packet and perform the corresponding action.\r
+ *\r
+ */\r
+void USBD_ProcessSetupPacket(void)\r
+{\r
+ /* Get SETUP packet from USB buffer */\r
+ USBD_MemCopy(g_USBD_au8SetupPacket, (uint8_t *)USBD_BUF_BASE, 8UL);\r
+\r
+ /* Check the request type */\r
+ switch(g_USBD_au8SetupPacket[0] & 0x60UL)\r
+ {\r
+ case REQ_STANDARD: /* Standard */\r
+ {\r
+ USBD_StandardRequest();\r
+ break;\r
+ }\r
+ case REQ_CLASS: /* Class */\r
+ {\r
+ if(g_USBD_pfnClassRequest != NULL)\r
+ {\r
+ g_USBD_pfnClassRequest();\r
+ }\r
+ break;\r
+ }\r
+ case REQ_VENDOR: /* Vendor */\r
+ {\r
+ if(g_USBD_pfnVendorRequest != NULL)\r
+ {\r
+ g_USBD_pfnVendorRequest();\r
+ }\r
+ break;\r
+ }\r
+ default: /* reserved */\r
+ {\r
+ /* Setup error, stall the device */\r
+ USBD_SET_EP_STALL(EP0);\r
+ USBD_SET_EP_STALL(EP1);\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Process GetDescriptor request\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Parse GetDescriptor request and perform the corresponding action.\r
+ *\r
+ */\r
+void USBD_GetDescriptor(void)\r
+{\r
+ uint32_t u32Len;\r
+\r
+ g_USBD_u8CtrlInZeroFlag = (uint8_t)0UL;\r
+ u32Len = 0UL;\r
+ u32Len = g_USBD_au8SetupPacket[7];\r
+ u32Len <<= 8UL;\r
+ u32Len += g_USBD_au8SetupPacket[6];\r
+\r
+ switch(g_USBD_au8SetupPacket[3])\r
+ {\r
+ /* Get Device Descriptor */\r
+ case DESC_DEVICE:\r
+ {\r
+ u32Len = USBD_Minimum(u32Len, (uint32_t)LEN_DEVICE);\r
+ USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8DevDesc, u32Len);\r
+ break;\r
+ }\r
+ /* Get Configuration Descriptor */\r
+ case DESC_CONFIG:\r
+ {\r
+ uint32_t u32TotalLen;\r
+\r
+ u32TotalLen = g_USBD_sInfo->gu8ConfigDesc[3];\r
+ u32TotalLen = g_USBD_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8UL);\r
+\r
+ if(u32Len > u32TotalLen)\r
+ {\r
+ u32Len = u32TotalLen;\r
+ if((u32Len % g_USBD_u32CtrlMaxPktSize) == 0UL)\r
+ {\r
+ g_USBD_u8CtrlInZeroFlag = (uint8_t)1UL;\r
+ }\r
+ }\r
+ USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8ConfigDesc, u32Len);\r
+ break;\r
+ }\r
+ /* Get BOS Descriptor */\r
+ case DESC_BOS:\r
+ {\r
+ uint32_t u32TotalLen;\r
+\r
+ u32TotalLen = g_USBD_sInfo->gu8BosDesc[3];\r
+ u32TotalLen = g_USBD_sInfo->gu8BosDesc[2] + (u32TotalLen << 8UL);\r
+\r
+ u32Len = USBD_Minimum(u32Len, u32TotalLen);\r
+ USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8BosDesc, u32Len);\r
+ break;\r
+ }\r
+ /* Get HID Descriptor */\r
+ case DESC_HID:\r
+ {\r
+ /* CV3.0 HID Class Descriptor Test,\r
+ Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */\r
+ uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */\r
+ u32Len = USBD_Minimum(u32Len, LEN_HID);\r
+ u32ConfigDescOffset = g_USBD_sInfo->gu32ConfigHidDescIdx[g_USBD_au8SetupPacket[4]];\r
+ USBD_PrepareCtrlIn((uint8_t *)&g_USBD_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len);\r
+ break;\r
+ }\r
+ /* Get Report Descriptor */\r
+ case DESC_HID_RPT:\r
+ {\r
+ if(u32Len > g_USBD_sInfo->gu32HidReportSize[g_USBD_au8SetupPacket[4]])\r
+ {\r
+ u32Len = g_USBD_sInfo->gu32HidReportSize[g_USBD_au8SetupPacket[4]];\r
+ if((u32Len % g_USBD_u32CtrlMaxPktSize) == 0UL)\r
+ {\r
+ g_USBD_u8CtrlInZeroFlag = (uint8_t)1UL;\r
+ }\r
+ }\r
+ USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8HidReportDesc[g_USBD_au8SetupPacket[4]], u32Len);\r
+ break;\r
+ }\r
+ /* Get String Descriptor */\r
+ case DESC_STRING:\r
+ {\r
+ /* Get String Descriptor */\r
+ if(g_USBD_au8SetupPacket[2] < 4UL)\r
+ {\r
+ if(u32Len > g_USBD_sInfo->gu8StringDesc[g_USBD_au8SetupPacket[2]][0])\r
+ {\r
+ u32Len = g_USBD_sInfo->gu8StringDesc[g_USBD_au8SetupPacket[2]][0];\r
+ if((u32Len % g_USBD_u32CtrlMaxPktSize) == 0UL)\r
+ {\r
+ g_USBD_u8CtrlInZeroFlag = (uint8_t)1UL;\r
+ }\r
+ }\r
+ USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8StringDesc[g_USBD_au8SetupPacket[2]], u32Len);\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ /* Not support. Reply STALL. */\r
+ USBD_SET_EP_STALL(EP0);\r
+ USBD_SET_EP_STALL(EP1);\r
+ break;\r
+ }\r
+ }\r
+ default:\r
+ /* Not support. Reply STALL. */\r
+ USBD_SET_EP_STALL(EP0);\r
+ USBD_SET_EP_STALL(EP1);\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Process standard request\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Parse standard request and perform the corresponding action.\r
+ *\r
+ */\r
+void USBD_StandardRequest(void)\r
+{\r
+ uint32_t u32Addr;\r
+ USBD_T *pUSBD;\r
+ OTG_T *pOTG;\r
+\r
+ if((__PC() & NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pUSBD = USBD_NS;\r
+ pOTG = OTG_NS;\r
+ }\r
+ else\r
+ {\r
+ pUSBD = USBD;\r
+ pOTG = OTG;\r
+ }\r
+\r
+ /* clear global variables for new request */\r
+ g_USBD_pu8CtrlInPointer = 0;\r
+ g_USBD_u32CtrlInSize = 0UL;\r
+\r
+ if((g_USBD_au8SetupPacket[0] & 0x80UL) == 0x80UL) /* request data transfer direction */\r
+ {\r
+ /* Device to host */\r
+ switch(g_USBD_au8SetupPacket[1])\r
+ {\r
+ case GET_CONFIGURATION:\r
+ {\r
+ /* Return current configuration setting */\r
+ /* Data stage */\r
+ u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);\r
+ M8(u32Addr) = (uint8_t)g_USBD_u32UsbConfig;\r
+ USBD_SET_DATA1(EP0);\r
+ USBD_SET_PAYLOAD_LEN(EP0, 1UL);\r
+ /* Status stage */\r
+ USBD_PrepareCtrlOut(0, 0UL);\r
+ break;\r
+ }\r
+ case GET_DESCRIPTOR:\r
+ {\r
+ USBD_GetDescriptor();\r
+ USBD_PrepareCtrlOut(0, 0UL); /* For status stage */\r
+ break;\r
+ }\r
+ case GET_INTERFACE:\r
+ {\r
+ /* Return current interface setting */\r
+ /* Data stage */\r
+ u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);\r
+ M8(u32Addr) = (uint8_t)g_USBD_u32UsbAltInterface;\r
+ USBD_SET_DATA1(EP0);\r
+ USBD_SET_PAYLOAD_LEN(EP0, 1UL);\r
+ /* Status stage */\r
+ USBD_PrepareCtrlOut(0, 0UL);\r
+ break;\r
+ }\r
+ case GET_STATUS:\r
+ {\r
+ /* Device */\r
+ if(g_USBD_au8SetupPacket[0] == 0x80UL)\r
+ {\r
+ uint8_t u8Tmp;\r
+\r
+ u8Tmp = (uint8_t)0UL;\r
+ if((g_USBD_sInfo->gu8ConfigDesc[7] & 0x40UL) == 0x40UL)\r
+ {\r
+ u8Tmp |= (uint8_t)1UL; /* Self-Powered/Bus-Powered. */\r
+ }\r
+ if((g_USBD_sInfo->gu8ConfigDesc[7] & 0x20UL) == 0x20UL)\r
+ {\r
+ u8Tmp |= (uint8_t)(g_USBD_u8RemoteWakeupEn << 1UL); /* Remote wake up */\r
+ }\r
+\r
+ u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);\r
+ M8(u32Addr) = u8Tmp;\r
+\r
+ }\r
+ /* Interface */\r
+ else if(g_USBD_au8SetupPacket[0] == 0x81UL)\r
+ {\r
+ u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);\r
+ M8(u32Addr) = (uint8_t)0UL;\r
+ }\r
+ /* Endpoint */\r
+ else if(g_USBD_au8SetupPacket[0] == 0x82UL)\r
+ {\r
+ uint8_t ep = (uint8_t)(g_USBD_au8SetupPacket[4] & 0xFUL);\r
+ u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);\r
+ M8(u32Addr) = (uint8_t)(USBD_GetStall(ep) ? 1UL : 0UL);\r
+ }\r
+\r
+ u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1UL;\r
+ M8(u32Addr) = (uint8_t)0UL;\r
+ /* Data stage */\r
+ USBD_SET_DATA1(EP0);\r
+ USBD_SET_PAYLOAD_LEN(EP0, 2UL);\r
+ /* Status stage */\r
+ USBD_PrepareCtrlOut(0, 0UL);\r
+ break;\r
+ }\r
+ default:\r
+ {\r
+ /* Setup error, stall the device */\r
+ USBD_SET_EP_STALL(EP0);\r
+ USBD_SET_EP_STALL(EP1);\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Host to device */\r
+ switch(g_USBD_au8SetupPacket[1])\r
+ {\r
+ case CLEAR_FEATURE:\r
+ {\r
+ if(g_USBD_au8SetupPacket[2] == FEATURE_ENDPOINT_HALT)\r
+ {\r
+ uint32_t epNum, i;\r
+\r
+ /* EP number stall is not allow to be clear in MSC class "Error Recovery Test".\r
+ a flag: g_USBD_u32EpStallLock is added to support it */\r
+ epNum = (uint8_t)(g_USBD_au8SetupPacket[4] & 0xFUL);\r
+ for(i = 0UL; i < USBD_MAX_EP; i++)\r
+ {\r
+ if(((pUSBD->EP[i].CFG & 0xFUL) == epNum) && ((g_USBD_u32EpStallLock & (1UL << i)) == 0UL))\r
+ {\r
+ pUSBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk;\r
+ pUSBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;\r
+ }\r
+ }\r
+ }\r
+ else if(g_USBD_au8SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)\r
+ {\r
+ g_USBD_u8RemoteWakeupEn = (uint8_t)0UL;\r
+ }\r
+\r
+ /* Status stage */\r
+ USBD_SET_DATA1(EP0);\r
+ USBD_SET_PAYLOAD_LEN(EP0, 0UL);\r
+ break;\r
+ }\r
+ case SET_ADDRESS:\r
+ {\r
+ g_USBD_u32UsbAddr = g_USBD_au8SetupPacket[2];\r
+\r
+ /* DATA IN for end of setup */\r
+ /* Status Stage */\r
+ USBD_SET_DATA1(EP0);\r
+ USBD_SET_PAYLOAD_LEN(EP0, 0UL);\r
+ break;\r
+ }\r
+ case SET_CONFIGURATION:\r
+ {\r
+ g_USBD_u32UsbConfig = g_USBD_au8SetupPacket[2];\r
+\r
+ if(g_USBD_pfnSetConfigCallback)\r
+ {\r
+ g_USBD_pfnSetConfigCallback();\r
+ }\r
+\r
+ /* DATA IN for end of setup */\r
+ /* Status stage */\r
+ USBD_SET_DATA1(EP0);\r
+ USBD_SET_PAYLOAD_LEN(EP0, 0UL);\r
+ break;\r
+ }\r
+ case SET_FEATURE:\r
+ {\r
+ if((g_USBD_au8SetupPacket[0] & 0xFUL) == 0UL) /* 0: device */\r
+ {\r
+ if((g_USBD_au8SetupPacket[2] == 3UL) && (g_USBD_au8SetupPacket[3] == 0UL)) /* 3: HNP enable */\r
+ {\r
+ pOTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk);\r
+ }\r
+ }\r
+ if(g_USBD_au8SetupPacket[2] == FEATURE_ENDPOINT_HALT)\r
+ {\r
+ USBD_SetStall((uint8_t)(g_USBD_au8SetupPacket[4] & 0xFUL));\r
+ }\r
+ else if(g_USBD_au8SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)\r
+ {\r
+ g_USBD_u8RemoteWakeupEn = (uint8_t)1UL;\r
+ }\r
+\r
+ /* Status stage */\r
+ USBD_SET_DATA1(EP0);\r
+ USBD_SET_PAYLOAD_LEN(EP0, 0UL);\r
+ break;\r
+ }\r
+ case SET_INTERFACE:\r
+ {\r
+ g_USBD_u32UsbAltInterface = g_USBD_au8SetupPacket[2];\r
+ if(g_USBD_pfnSetInterface != NULL)\r
+ {\r
+ g_USBD_pfnSetInterface(g_USBD_u32UsbAltInterface);\r
+ }\r
+\r
+ /* Status stage */\r
+ USBD_SET_DATA1(EP0);\r
+ USBD_SET_PAYLOAD_LEN(EP0, 0UL);\r
+ break;\r
+ }\r
+ default:\r
+ {\r
+ /* Setup error, stall the device */\r
+ USBD_SET_EP_STALL(EP0);\r
+ USBD_SET_EP_STALL(EP1);\r
+ break;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Prepare the first Control IN pipe\r
+ *\r
+ * @param[in] pu8Buf The pointer of data sent to USB host.\r
+ * @param[in] u32Size The IN transfer size.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Prepare data for Control IN transfer.\r
+ *\r
+ */\r
+void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size)\r
+{\r
+ uint32_t u32Addr;\r
+\r
+ if(u32Size > g_USBD_u32CtrlMaxPktSize)\r
+ {\r
+ /* Data size > MXPLD */\r
+ g_USBD_pu8CtrlInPointer = pu8Buf + g_USBD_u32CtrlMaxPktSize;\r
+ g_USBD_u32CtrlInSize = u32Size - g_USBD_u32CtrlMaxPktSize;\r
+ USBD_SET_DATA1(EP0);\r
+ u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);\r
+ USBD_MemCopy((uint8_t *)u32Addr, pu8Buf, g_USBD_u32CtrlMaxPktSize);\r
+ USBD_SET_PAYLOAD_LEN(EP0, g_USBD_u32CtrlMaxPktSize);\r
+ }\r
+ else\r
+ {\r
+ /* Data size <= MXPLD */\r
+ g_USBD_pu8CtrlInPointer = 0;\r
+ g_USBD_u32CtrlInSize = 0UL;\r
+ USBD_SET_DATA1(EP0);\r
+ u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);\r
+ USBD_MemCopy((uint8_t *)u32Addr, pu8Buf, u32Size);\r
+ USBD_SET_PAYLOAD_LEN(EP0, u32Size);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Repeat Control IN pipe\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function processes the remained data of Control IN transfer.\r
+ *\r
+ */\r
+void USBD_CtrlIn(void)\r
+{\r
+ uint32_t u32Addr;\r
+\r
+ if(g_USBD_u32CtrlInSize)\r
+ {\r
+ /* Process remained data */\r
+ if(g_USBD_u32CtrlInSize > g_USBD_u32CtrlMaxPktSize)\r
+ {\r
+ /* Data size > MXPLD */\r
+ u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);\r
+ USBD_MemCopy((uint8_t *)u32Addr, (uint8_t *)g_USBD_pu8CtrlInPointer, g_USBD_u32CtrlMaxPktSize);\r
+ USBD_SET_PAYLOAD_LEN(EP0, g_USBD_u32CtrlMaxPktSize);\r
+ g_USBD_pu8CtrlInPointer += g_USBD_u32CtrlMaxPktSize;\r
+ g_USBD_u32CtrlInSize -= g_USBD_u32CtrlMaxPktSize;\r
+ }\r
+ else\r
+ {\r
+ /* Data size <= MXPLD */\r
+ u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);\r
+ USBD_MemCopy((uint8_t *)u32Addr, (uint8_t *)g_USBD_pu8CtrlInPointer, g_USBD_u32CtrlInSize);\r
+ USBD_SET_PAYLOAD_LEN(EP0, g_USBD_u32CtrlInSize);\r
+ g_USBD_pu8CtrlInPointer = 0;\r
+ g_USBD_u32CtrlInSize = 0UL;\r
+ }\r
+ }\r
+ else /* No more data for IN token */\r
+ {\r
+ /* In ACK for Set address */\r
+ if((g_USBD_au8SetupPacket[0] == REQ_STANDARD) && (g_USBD_au8SetupPacket[1] == SET_ADDRESS))\r
+ {\r
+ u32Addr = USBD_GET_ADDR();\r
+ if((u32Addr != g_USBD_u32UsbAddr) && (u32Addr == 0UL))\r
+ {\r
+ USBD_SET_ADDR(g_USBD_u32UsbAddr);\r
+ }\r
+ }\r
+\r
+ /* For the case of data size is integral times maximum packet size */\r
+ if(g_USBD_u8CtrlInZeroFlag)\r
+ {\r
+ USBD_SET_PAYLOAD_LEN(EP0, 0UL);\r
+ g_USBD_u8CtrlInZeroFlag = (uint8_t)0UL;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Prepare the first Control OUT pipe\r
+ *\r
+ * @param[in] pu8Buf The pointer of data received from USB host.\r
+ * @param[in] u32Size The OUT transfer size.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to prepare the first Control OUT transfer.\r
+ *\r
+ */\r
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size)\r
+{\r
+ g_USBD_pu8CtrlOutPointer = pu8Buf;\r
+ g_USBD_u32CtrlOutSize = 0UL;\r
+ g_USBD_u32CtrlOutSizeLimit = u32Size;\r
+ USBD_SET_PAYLOAD_LEN(EP1, g_USBD_u32CtrlMaxPktSize);\r
+}\r
+\r
+/**\r
+ * @brief Repeat Control OUT pipe\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function processes the successive Control OUT transfer.\r
+ *\r
+ */\r
+void USBD_CtrlOut(void)\r
+{\r
+ uint32_t u32Size;\r
+ uint32_t u32Addr;\r
+\r
+ if(g_USBD_u32CtrlOutSize < g_USBD_u32CtrlOutSizeLimit)\r
+ {\r
+ u32Size = USBD_GET_PAYLOAD_LEN(EP1);\r
+ u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1);\r
+ USBD_MemCopy((uint8_t *)g_USBD_pu8CtrlOutPointer, (uint8_t *)u32Addr, u32Size);\r
+ g_USBD_pu8CtrlOutPointer += u32Size;\r
+ g_USBD_u32CtrlOutSize += u32Size;\r
+\r
+ if(g_USBD_u32CtrlOutSize < g_USBD_u32CtrlOutSizeLimit)\r
+ {\r
+ USBD_SET_PAYLOAD_LEN(EP1, g_USBD_u32CtrlMaxPktSize);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Reset software flags\r
+ *\r
+ * @param None\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function resets all variables for protocol and resets USB device address to 0.\r
+ *\r
+ */\r
+void USBD_SwReset(void)\r
+{\r
+ uint32_t i;\r
+ USBD_T *pUSBD;\r
+\r
+ if((__PC() & NS_OFFSET) == NS_OFFSET)\r
+ {\r
+ pUSBD = USBD_NS;\r
+ }\r
+ else\r
+ {\r
+ pUSBD = USBD;\r
+ }\r
+\r
+ /* Reset all variables for protocol */\r
+ g_USBD_pu8CtrlInPointer = 0;\r
+ g_USBD_u32CtrlInSize = 0UL;\r
+ g_USBD_pu8CtrlOutPointer = 0;\r
+ g_USBD_u32CtrlOutSize = 0UL;\r
+ g_USBD_u32CtrlOutSizeLimit = 0UL;\r
+ g_USBD_u32EpStallLock = 0UL;\r
+ memset(g_USBD_au8SetupPacket, 0, 8UL);\r
+\r
+ /* Reset PID DATA0 */\r
+ for(i = 0UL; i < USBD_MAX_EP; i++)\r
+ {\r
+ pUSBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;\r
+ }\r
+\r
+ /* Reset USB device address */\r
+ USBD_SET_ADDR(0UL);\r
+}\r
+\r
+/**\r
+ * @brief USBD Set Vendor Request\r
+ *\r
+ * @param[in] pfnVendorReq Vendor Request Callback Function\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to set USBD vendor request callback function\r
+ */\r
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq)\r
+{\r
+ g_USBD_pfnVendorRequest = pfnVendorReq;\r
+}\r
+\r
+/**\r
+ * @brief The callback function which called when get SET CONFIGURATION request\r
+ *\r
+ * @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to set the callback function which will be called at SET CONFIGURATION request.\r
+ */\r
+void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback)\r
+{\r
+ g_USBD_pfnSetConfigCallback = pfnSetConfigCallback;\r
+}\r
+\r
+\r
+/**\r
+ * @brief EP stall lock function to avoid stall clear by USB SET FEATURE request.\r
+ *\r
+ * @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request.\r
+ * If ep stall locked, user needs to reset USB device or re-configure device to clear it.\r
+ */\r
+void USBD_LockEpStall(uint32_t u32EpBitmap)\r
+{\r
+ g_USBD_u32EpStallLock = u32EpBitmap;\r
+}\r
+\r
+/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group USBD_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/****************************************************************************//**\r
+ * @file usci_i2c.c\r
+ * @version V3.00\r
+ * $Revision: 1 $\r
+ * $Date: 16/07/07 7:50p $\r
+ * @brief M2351 series USCI I2C(UI2C) driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USCI_I2C_Driver USCI_I2C Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief This function makes USCI_I2C module be ready and set the wanted bus clock\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u32BusClock The target bus speed of USCI_I2C module.\r
+ *\r
+ * @return Actual USCI_I2C bus clock frequency.\r
+ *\r
+ * @details Enable USCI_I2C module and configure USCI_I2C module(bus clock, data format).\r
+ */\r
+uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock)\r
+{\r
+ uint32_t u32ClkDiv;\r
+ uint32_t u32Pclk;\r
+\r
+ if((ui2c == UI2C1) || (ui2c == UI2C1_NS))\r
+ {\r
+ u32Pclk = CLK_GetPCLK1Freq();\r
+ }\r
+ else\r
+ {\r
+ u32Pclk = CLK_GetPCLK0Freq();\r
+ }\r
+\r
+ u32ClkDiv = (uint32_t)((((((u32Pclk / 2u) * 10u) / (u32BusClock)) + 5u) / 10u) - 1u); /* Compute proper divider for USCI_I2C clock */\r
+\r
+ /* Enable USCI_I2C protocol */\r
+ ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk;\r
+ ui2c->CTL = 4u << UI2C_CTL_FUNMODE_Pos;\r
+\r
+ /* Data format configuration */\r
+ /* 8 bit data length */\r
+ ui2c->LINECTL &= ~UI2C_LINECTL_DWIDTH_Msk;\r
+ ui2c->LINECTL |= 8u << UI2C_LINECTL_DWIDTH_Pos;\r
+\r
+ /* MSB data format */\r
+ ui2c->LINECTL &= ~UI2C_LINECTL_LSB_Msk;\r
+\r
+ /* Set USCI_I2C bus clock */\r
+ ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk;\r
+ ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos);\r
+ ui2c->PROTCTL |= UI2C_PROTCTL_PROTEN_Msk;\r
+\r
+ return (u32Pclk / ((u32ClkDiv + 1u) << 1u));\r
+}\r
+\r
+/**\r
+ * @brief This function closes the USCI_I2C module\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Close USCI_I2C protocol function.\r
+ */\r
+void UI2C_Close(UI2C_T *ui2c)\r
+{\r
+ /* Disable USCI_I2C function */\r
+ ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk;\r
+}\r
+\r
+/**\r
+ * @brief This function clears the time-out flag\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Clear time-out flag when time-out flag is set.\r
+ */\r
+void UI2C_ClearTimeoutFlag(UI2C_T *ui2c)\r
+{\r
+ ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk;\r
+}\r
+\r
+/**\r
+ * @brief This function sets the control bit of the USCI_I2C module.\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8Start Set START bit to USCI_I2C module.\r
+ * @param[in] u8Stop Set STOP bit to USCI_I2C module.\r
+ * @param[in] u8Ptrg Set PTRG bit to USCI_I2C module.\r
+ * @param[in] u8Ack Set ACK bit to USCI_I2C module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function set USCI_I2C control bit of USCI_I2C bus protocol.\r
+ */\r
+void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack)\r
+{\r
+ uint32_t u32Reg = 0u;\r
+ uint32_t u32Val = ui2c->PROTCTL & ~(UI2C_PROTCTL_STA_Msk | UI2C_PROTCTL_STO_Msk | UI2C_PROTCTL_AA_Msk);\r
+\r
+ if(u8Start)\r
+ {\r
+ u32Reg |= UI2C_PROTCTL_STA_Msk;\r
+ }\r
+ if(u8Stop)\r
+ {\r
+ u32Reg |= UI2C_PROTCTL_STO_Msk;\r
+ }\r
+ if(u8Ptrg)\r
+ {\r
+ u32Reg |= UI2C_PROTCTL_PTRG_Msk;\r
+ }\r
+ if(u8Ack)\r
+ {\r
+ u32Reg |= UI2C_PROTCTL_AA_Msk;\r
+ }\r
+ ui2c->PROTCTL = u32Val | u32Reg;\r
+}\r
+\r
+/**\r
+ * @brief This function disables the interrupt of USCI_I2C module\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u32Mask The combination of all related interrupt enable bits.\r
+ * Each bit corresponds to an interrupt enable bit.\r
+ * This parameter decides which interrupts will be disabled. It is combination of:\r
+ * - \ref UI2C_TO_INT_MASK\r
+ * - \ref UI2C_STAR_INT_MASK\r
+ * - \ref UI2C_STOR_INT_MASK\r
+ * - \ref UI2C_NACK_INT_MASK\r
+ * - \ref UI2C_ARBLO_INT_MASK\r
+ * - \ref UI2C_ERR_INT_MASK\r
+ * - \ref UI2C_ACK_INT_MASK\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to disable USCI_I2C bus interrupt events.\r
+ */\r
+void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask)\r
+{\r
+ /* Disable time-out interrupt flag */\r
+ if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_TOIEN_Msk;\r
+ }\r
+ /* Disable start condition received interrupt flag */\r
+ if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_STARIEN_Msk;\r
+ }\r
+ /* Disable stop condition received interrupt flag */\r
+ if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_STORIEN_Msk;\r
+ }\r
+ /* Disable non-acknowledge interrupt flag */\r
+ if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_NACKIEN_Msk;\r
+ }\r
+ /* Disable arbitration lost interrupt flag */\r
+ if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_ARBLOIEN_Msk;\r
+ }\r
+\r
+ /* Disable error interrupt flag */\r
+ if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_ERRIEN_Msk;\r
+ }\r
+ /* Disable acknowledge interrupt flag */\r
+ if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN &= ~UI2C_PROTIEN_ACKIEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function enables the interrupt of USCI_I2C module.\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u32Mask The combination of all related interrupt enable bits.\r
+ * Each bit corresponds to a interrupt enable bit.\r
+ * This parameter decides which interrupts will be enabled. It is combination of:\r
+ * - \ref UI2C_TO_INT_MASK\r
+ * - \ref UI2C_STAR_INT_MASK\r
+ * - \ref UI2C_STOR_INT_MASK\r
+ * - \ref UI2C_NACK_INT_MASK\r
+ * - \ref UI2C_ARBLO_INT_MASK\r
+ * - \ref UI2C_ERR_INT_MASK\r
+ * - \ref UI2C_ACK_INT_MASK\r
+ * @return None\r
+ *\r
+ * @details The function is used to enable USCI_I2C bus interrupt events.\r
+ */\r
+void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask)\r
+{\r
+ /* Enable time-out interrupt flag */\r
+ if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN |= UI2C_PROTIEN_TOIEN_Msk;\r
+ }\r
+ /* Enable start condition received interrupt flag */\r
+ if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN |= UI2C_PROTIEN_STARIEN_Msk;\r
+ }\r
+ /* Enable stop condition received interrupt flag */\r
+ if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN |= UI2C_PROTIEN_STORIEN_Msk;\r
+ }\r
+ /* Enable non-acknowledge interrupt flag */\r
+ if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN |= UI2C_PROTIEN_NACKIEN_Msk;\r
+ }\r
+ /* Enable arbitration lost interrupt flag */\r
+ if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN |= UI2C_PROTIEN_ARBLOIEN_Msk;\r
+ }\r
+ /* Enable error interrupt flag */\r
+ if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN |= UI2C_PROTIEN_ERRIEN_Msk;\r
+ }\r
+ /* Enable acknowledge interrupt flag */\r
+ if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK)\r
+ {\r
+ ui2c->PROTIEN |= UI2C_PROTIEN_ACKIEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function returns the real bus clock of USCI_I2C module\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return Actual USCI_I2C bus clock frequency.\r
+ *\r
+ * @details The function returns the actual USCI_I2C module bus clock.\r
+ */\r
+uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c)\r
+{\r
+ uint32_t u32Divider;\r
+ uint32_t u32Pclk;\r
+\r
+ if((ui2c == UI2C1) || (ui2c == UI2C1_NS))\r
+ {\r
+ u32Pclk = CLK_GetPCLK1Freq();\r
+ }\r
+ else\r
+ {\r
+ u32Pclk = CLK_GetPCLK0Freq();\r
+ }\r
+ u32Divider = (ui2c->BRGEN & UI2C_BRGEN_CLKDIV_Msk) >> UI2C_BRGEN_CLKDIV_Pos;\r
+\r
+ return (u32Pclk / ((u32Divider + 1u) << 1u));\r
+}\r
+\r
+/**\r
+ * @brief This function sets bus clock frequency of USCI_I2C module\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u32BusClock The target bus speed of USCI_I2C module.\r
+ *\r
+ * @return Actual USCI_I2C bus clock frequency.\r
+ *\r
+ * @details Use this function set USCI_I2C bus clock frequency and return actual bus clock.\r
+ */\r
+uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock)\r
+{\r
+ uint32_t u32ClkDiv;\r
+ uint32_t u32Pclk;\r
+\r
+ if((ui2c == UI2C1) || (ui2c == UI2C1_NS))\r
+ {\r
+ u32Pclk = CLK_GetPCLK1Freq();\r
+ }\r
+ else\r
+ {\r
+ u32Pclk = CLK_GetPCLK0Freq();\r
+ }\r
+ u32ClkDiv = (uint32_t)((((((u32Pclk / 2u) * 10u) / (u32BusClock)) + 5u) / 10u) - 1u); /* Compute proper divider for USCI_I2C clock */\r
+\r
+ /* Set USCI_I2C bus clock */\r
+ ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk;\r
+ ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos);\r
+\r
+ return (u32Pclk / ((u32ClkDiv + 1u) << 1u));\r
+}\r
+\r
+/**\r
+ * @brief This function gets the interrupt flag of USCI_I2C module\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u32Mask The combination of all related interrupt sources.\r
+ * Each bit corresponds to a interrupt source.\r
+ * This parameter decides which interrupt flags will be read. It is combination of:\r
+ * - \ref UI2C_TO_INT_MASK\r
+ * - \ref UI2C_STAR_INT_MASK\r
+ * - \ref UI2C_STOR_INT_MASK\r
+ * - \ref UI2C_NACK_INT_MASK\r
+ * - \ref UI2C_ARBLO_INT_MASK\r
+ * - \ref UI2C_ERR_INT_MASK\r
+ * - \ref UI2C_ACK_INT_MASK\r
+ *\r
+ * @return Interrupt flags of selected sources.\r
+ *\r
+ * @details Use this function to get USCI_I2C interrupt flag when module occurs interrupt event.\r
+ */\r
+uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask)\r
+{\r
+ uint32_t u32IntFlag = 0U;\r
+ uint32_t u32TmpValue;\r
+\r
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_TOIF_Msk;\r
+ /* Check Time-out Interrupt Flag */\r
+ if((u32Mask & UI2C_TO_INT_MASK) && (u32TmpValue))\r
+ {\r
+ u32IntFlag |= UI2C_TO_INT_MASK;\r
+ }\r
+\r
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STARIF_Msk;\r
+ /* Check Start Condition Received Interrupt Flag */\r
+ if((u32Mask & UI2C_STAR_INT_MASK) && (u32TmpValue))\r
+ {\r
+ u32IntFlag |= UI2C_STAR_INT_MASK;\r
+ }\r
+\r
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STORIF_Msk;\r
+ /* Check Stop Condition Received Interrupt Flag */\r
+ if((u32Mask & UI2C_STOR_INT_MASK) && (u32TmpValue))\r
+ {\r
+ u32IntFlag |= UI2C_STOR_INT_MASK;\r
+ }\r
+\r
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_NACKIF_Msk;\r
+ /* Check Non-Acknowledge Interrupt Flag */\r
+ if((u32Mask & UI2C_NACK_INT_MASK) && (u32TmpValue))\r
+ {\r
+ u32IntFlag |= UI2C_NACK_INT_MASK;\r
+ }\r
+\r
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ARBLOIF_Msk;\r
+ /* Check Arbitration Lost Interrupt Flag */\r
+ if((u32Mask & UI2C_ARBLO_INT_MASK) && (u32TmpValue))\r
+ {\r
+ u32IntFlag |= UI2C_ARBLO_INT_MASK;\r
+ }\r
+\r
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ERRIF_Msk;\r
+ /* Check Error Interrupt Flag */\r
+ if((u32Mask & UI2C_ERR_INT_MASK) && (u32TmpValue))\r
+ {\r
+ u32IntFlag |= UI2C_ERR_INT_MASK;\r
+ }\r
+\r
+ u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ACKIF_Msk;\r
+ /* Check Acknowledge Interrupt Flag */\r
+ if((u32Mask & UI2C_ACK_INT_MASK) && (u32TmpValue))\r
+ {\r
+ u32IntFlag |= UI2C_ACK_INT_MASK;\r
+ }\r
+\r
+ return u32IntFlag;\r
+}\r
+\r
+/**\r
+ * @brief This function clears the interrupt flag of USCI_I2C module.\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u32Mask The combination of all related interrupt sources.\r
+ * Each bit corresponds to a interrupt source.\r
+ * This parameter decides which interrupt flags will be cleared. It is combination of:\r
+ * - \ref UI2C_TO_INT_MASK\r
+ * - \ref UI2C_STAR_INT_MASK\r
+ * - \ref UI2C_STOR_INT_MASK\r
+ * - \ref UI2C_NACK_INT_MASK\r
+ * - \ref UI2C_ARBLO_INT_MASK\r
+ * - \ref UI2C_ERR_INT_MASK\r
+ * - \ref UI2C_ACK_INT_MASK\r
+ *\r
+ * @return None\r
+ *\r
+ * @details Use this function to clear USCI_I2C interrupt flag when module occurs interrupt event and set flag.\r
+ */\r
+void UI2C_ClearIntFlag(UI2C_T *ui2c, uint32_t u32Mask)\r
+{\r
+ /* Clear Time-out Interrupt Flag */\r
+ if(u32Mask & UI2C_TO_INT_MASK)\r
+ {\r
+ ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk;\r
+ }\r
+ /* Clear Start Condition Received Interrupt Flag */\r
+ if(u32Mask & UI2C_STAR_INT_MASK)\r
+ {\r
+ ui2c->PROTSTS = UI2C_PROTSTS_STARIF_Msk;\r
+ }\r
+ /* Clear Stop Condition Received Interrupt Flag */\r
+ if(u32Mask & UI2C_STOR_INT_MASK)\r
+ {\r
+ ui2c->PROTSTS = UI2C_PROTSTS_STORIF_Msk;\r
+ }\r
+ /* Clear Non-Acknowledge Interrupt Flag */\r
+ if(u32Mask & UI2C_NACK_INT_MASK)\r
+ {\r
+ ui2c->PROTSTS = UI2C_PROTSTS_NACKIF_Msk;\r
+ }\r
+ /* Clear Arbitration Lost Interrupt Flag */\r
+ if(u32Mask & UI2C_ARBLO_INT_MASK)\r
+ {\r
+ ui2c->PROTSTS = UI2C_PROTSTS_ARBLOIF_Msk;\r
+ }\r
+ /* Clear Error Interrupt Flag */\r
+ if(u32Mask & UI2C_ERR_INT_MASK)\r
+ {\r
+ ui2c->PROTSTS = UI2C_PROTSTS_ERRIF_Msk;\r
+ }\r
+ /* Clear Acknowledge Interrupt Flag */\r
+ if(u32Mask & UI2C_ACK_INT_MASK)\r
+ {\r
+ ui2c->PROTSTS = UI2C_PROTSTS_ACKIF_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function returns the data stored in data register of USCI_I2C module.\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return USCI_I2C data.\r
+ *\r
+ * @details To read a byte data from USCI_I2C module receive data register.\r
+ */\r
+uint32_t UI2C_GetData(UI2C_T *ui2c)\r
+{\r
+ return (ui2c->RXDAT);\r
+}\r
+\r
+/**\r
+ * @brief This function writes a byte data to data register of USCI_I2C module\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8Data The data which will be written to data register of USCI_I2C module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To write a byte data to transmit data register to transmit data.\r
+ */\r
+void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data)\r
+{\r
+ ui2c->TXDAT = u8Data;\r
+}\r
+\r
+/**\r
+ * @brief Configure slave address and enable GC mode\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveNo Slave channel number [0/1]\r
+ * @param[in] u16SlaveAddr The slave address.\r
+ * @param[in] u8GCMode GC mode enable or not. Valid values are:\r
+ * - \ref UI2C_GCMODE_ENABLE\r
+ * - \ref UI2C_GCMODE_DISABLE\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To configure USCI_I2C module slave address and GC mode.\r
+ */\r
+void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode)\r
+{\r
+ if(u8SlaveNo)\r
+ {\r
+ ui2c->DEVADDR1 = u16SlaveAddr;\r
+ }\r
+ else\r
+ {\r
+ ui2c->DEVADDR0 = u16SlaveAddr;\r
+ }\r
+ ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_GCFUNC_Msk) | u8GCMode;\r
+}\r
+\r
+/**\r
+ * @brief Configure the mask bit of slave address.\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveNo Slave channle number [0/1]\r
+ * @param[in] u16SlaveAddrMask The slave address mask.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To configure USCI_I2C module slave address mask bit.\r
+ * @note The corresponding address bit is "Don't Care".\r
+ */\r
+void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask)\r
+{\r
+ if(u8SlaveNo)\r
+ {\r
+ ui2c->ADDRMSK1 = u16SlaveAddrMask;\r
+ }\r
+ else\r
+ {\r
+ ui2c->ADDRMSK0 = u16SlaveAddrMask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function enables time-out function and configures timeout counter\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u32TimeoutCnt Timeout counter. Valid values are between 0~0x3FF.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To enable USCI_I2C bus time-out function and set time-out counter.\r
+ */\r
+void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt)\r
+{\r
+ ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_TOCNT_Msk) | (u32TimeoutCnt << UI2C_PROTCTL_TOCNT_Pos);\r
+ ui2c->BRGEN = (ui2c->BRGEN & ~UI2C_BRGEN_TMCNTSRC_Msk) | UI2C_BRGEN_TMCNTEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief This function disables time-out function\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To disable USCI_I2C bus time-out function.\r
+ */\r
+void UI2C_DisableTimeout(UI2C_T *ui2c)\r
+{\r
+ ui2c->PROTCTL &= ~UI2C_PROTCTL_TOCNT_Msk;\r
+ ui2c->BRGEN &= ~UI2C_BRGEN_TMCNTEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief This function enables the wakeup function of USCI_I2C module\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8WakeupMode The wake-up mode selection. Valid values are:\r
+ * - \ref UI2C_DATA_TOGGLE_WK\r
+ * - \ref UI2C_ADDR_MATCH_WK\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To enable USCI_I2C module wake-up function.\r
+ */\r
+void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode)\r
+{\r
+ ui2c->WKCTL = (ui2c->WKCTL & ~UI2C_WKCTL_WKADDREN_Msk) | (u8WakeupMode | UI2C_WKCTL_WKEN_Msk);\r
+}\r
+\r
+/**\r
+ * @brief This function disables the wakeup function of USCI_I2C module\r
+ *\r
+ * @param[in] ui2c The pointer of the specified USCI_I2C module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details To disable USCI_I2C module wake-up function.\r
+ */\r
+void UI2C_DisableWakeup(UI2C_T *ui2c)\r
+{\r
+ ui2c->WKCTL &= ~UI2C_WKCTL_WKEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Write a byte to Slave\r
+ *\r
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] data Write a byte data to Slave\r
+ *\r
+ * @retval 0 Write data success\r
+ * @retval 1 Write data fail, or bus occurs error events\r
+ *\r
+ * @details The function is used for USCI_I2C Master write a byte data to Slave.\r
+ *\r
+ */\r
+\r
+uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data)\r
+{\r
+ uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U;\r
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;\r
+\r
+ UI2C_START(ui2c); /* Send START */\r
+\r
+ while(u8Xfering)\r
+ {\r
+ while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */\r
+\r
+ switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)\r
+ {\r
+ case UI2C_PROTSTS_STARIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */\r
+ eEvent = MASTER_SEND_ADDRESS;\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_ADDRESS)\r
+ {\r
+ UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */\r
+ eEvent = MASTER_SEND_DATA;\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ }\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_NACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ u8Err = 1U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_STORIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ u8Xfering = 0U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ u8Err = 1U;\r
+ break;\r
+ }\r
+\r
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */\r
+ }\r
+\r
+ return (u8Err | u8Xfering); /* return (Success)/(Fail) status */\r
+}\r
+\r
+/**\r
+ * @brief Write multi bytes to Slave\r
+ *\r
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] *data Pointer to array to write data to Slave\r
+ * @param[in] u32wLen How many bytes need to write to Slave\r
+ *\r
+ * @return A length of how many bytes have been transmitted.\r
+ *\r
+ * @details The function is used for USCI_I2C Master write multi bytes data to Slave.\r
+ *\r
+ */\r
+\r
+uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen)\r
+{\r
+ uint8_t u8Xfering = 1U, u8Ctrl = 0U;\r
+ uint32_t u32txLen = 0U;\r
+\r
+ UI2C_START(ui2c); /* Send START */\r
+\r
+ while(u8Xfering)\r
+ {\r
+ while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */\r
+\r
+ switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)\r
+ {\r
+ case UI2C_PROTSTS_STARIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */\r
+\r
+ if(u32txLen < u32wLen)\r
+ UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */\r
+ else\r
+ {\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ }\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_NACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ break;\r
+\r
+ case UI2C_PROTSTS_STORIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ u8Xfering = 0U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ break;\r
+ }\r
+\r
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */\r
+ }\r
+\r
+ return u32txLen; /* Return bytes length that have been transmitted */\r
+}\r
+\r
+/**\r
+ * @brief Specify a byte register address and write a byte to Slave\r
+ *\r
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u8DataAddr Specify a address (1 byte) of data write to\r
+ * @param[in] data A byte data to write it to Slave\r
+ *\r
+ * @retval 0 Write data success\r
+ * @retval 1 Write data fail, or bus occurs error events\r
+ *\r
+ * @details The function is used for USCI_I2C Master specify a address that data write to in Slave.\r
+ *\r
+ */\r
+\r
+uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data)\r
+{\r
+ uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U;\r
+ uint32_t u32txLen = 0U;\r
+\r
+ UI2C_START(ui2c); /* Send START */\r
+\r
+ while(u8Xfering)\r
+ {\r
+ while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */\r
+\r
+ switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)\r
+ {\r
+ case UI2C_PROTSTS_STARIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */\r
+\r
+ if(u32txLen == 0U)\r
+ {\r
+ UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */\r
+ u32txLen++;\r
+ }\r
+ else if(u32txLen == 1U)\r
+ {\r
+ UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */\r
+ u32txLen++;\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ }\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_NACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ u8Err = 1U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_STORIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ u8Xfering = 0U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ u8Err = 1U;\r
+ break;\r
+ }\r
+\r
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */\r
+ }\r
+\r
+ return (u8Err | u8Xfering); /* return (Success)/(Fail) status */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Specify a byte register address and write multi bytes to Slave\r
+ *\r
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u8DataAddr Specify a address (1 byte) of data write to\r
+ * @param[in] *data Pointer to array to write data to Slave\r
+ * @param[in] u32wLen How many bytes need to write to Slave\r
+ *\r
+ * @return A length of how many bytes have been transmitted.\r
+ *\r
+ * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes write to in Slave.\r
+ *\r
+ */\r
+\r
+uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen)\r
+{\r
+ uint8_t u8Xfering = 1U, u8Ctrl = 0U;\r
+ uint32_t u32txLen = 0U;\r
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;\r
+\r
+ UI2C_START(ui2c); /* Send START */\r
+\r
+ while(u8Xfering)\r
+ {\r
+ while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */\r
+\r
+ switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)\r
+ {\r
+ case UI2C_PROTSTS_STARIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */\r
+ eEvent = MASTER_SEND_ADDRESS;\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_ADDRESS)\r
+ {\r
+ UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */\r
+ eEvent = MASTER_SEND_DATA;\r
+ }\r
+ else\r
+ {\r
+ if(u32txLen < u32wLen)\r
+ UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */\r
+ else\r
+ {\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ }\r
+ }\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_NACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ break;\r
+\r
+ case UI2C_PROTSTS_STORIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ u8Xfering = 0U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ break;\r
+ }\r
+\r
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */\r
+ }\r
+\r
+ return u32txLen; /* Return bytes length that have been transmitted */\r
+}\r
+\r
+/**\r
+ * @brief Specify two bytes register address and Write a byte to Slave\r
+ *\r
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u16DataAddr Specify a address (2 byte) of data write to\r
+ * @param[in] data Write a byte data to Slave\r
+ *\r
+ * @retval 0 Write data success\r
+ * @retval 1 Write data fail, or bus occurs error events\r
+ *\r
+ * @details The function is used for USCI_I2C Master specify two bytes address that data write to in Slave.\r
+ *\r
+ */\r
+\r
+uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data)\r
+{\r
+ uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U;\r
+ uint32_t u32txLen = 0U;\r
+\r
+ UI2C_START(ui2c); /* Send START */\r
+\r
+ while(u8Xfering)\r
+ {\r
+ while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */\r
+\r
+ switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)\r
+ {\r
+ case UI2C_PROTSTS_STARIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */\r
+\r
+ if(u32txLen == 0U)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte data address to UI2C_TXDAT */\r
+ u32txLen++;\r
+ }\r
+ else if(u32txLen == 1U)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */\r
+ u32txLen++;\r
+ }\r
+ else if(u32txLen == 2U)\r
+ {\r
+ UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */\r
+ u32txLen++;\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ }\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_NACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ u8Err = 1U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_STORIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ u8Xfering = 0U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ u8Err = 1U;\r
+ break;\r
+ }\r
+\r
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */\r
+ }\r
+\r
+ return (u8Err | u8Xfering);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Specify two bytes register address and write multi bytes to Slave\r
+ *\r
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u16DataAddr Specify a address (2 bytes) of data write to\r
+ * @param[in] *data Pointer to array to write data to Slave\r
+ * @param[in] u32wLen How many bytes need to write to Slave\r
+ *\r
+ * @return A length of how many bytes have been transmitted.\r
+ *\r
+ * @details The function is used for USCI_I2C Master specify a byte address that multi data write to in Slave.\r
+ *\r
+ */\r
+\r
+uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen)\r
+{\r
+ uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U;\r
+ uint32_t u32txLen = 0U;\r
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;\r
+\r
+ UI2C_START(ui2c); /* Send START */\r
+\r
+ while(u8Xfering)\r
+ {\r
+ while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */\r
+\r
+ switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)\r
+ {\r
+ case UI2C_PROTSTS_STARIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */\r
+ eEvent = MASTER_SEND_ADDRESS;\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_ADDRESS)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte data address to UI2C_TXDAT */\r
+ eEvent = MASTER_SEND_DATA;\r
+ }\r
+ else if(eEvent == MASTER_SEND_DATA)\r
+ {\r
+ if(u8Addr)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */\r
+ u8Addr = 0;\r
+ }\r
+ else\r
+ {\r
+ if(u32txLen < u32wLen)\r
+ {\r
+ UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ }\r
+ }\r
+ }\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_NACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ break;\r
+\r
+ case UI2C_PROTSTS_STORIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ u8Xfering = 0U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ break;\r
+ }\r
+\r
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */\r
+ }\r
+\r
+ return u32txLen; /* Return bytes length that have been transmitted */\r
+}\r
+\r
+/**\r
+ * @brief Read a byte from Slave\r
+ *\r
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ *\r
+ * @return Read a byte data from Slave\r
+ *\r
+ * @details The function is used for USCI_I2C Master to read a byte data from Slave.\r
+ *\r
+ */\r
+uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr)\r
+{\r
+ uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U;\r
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;\r
+\r
+ UI2C_START(ui2c); /* Send START */\r
+\r
+ while(u8Xfering)\r
+ {\r
+ while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */\r
+\r
+ switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)\r
+ {\r
+ case UI2C_PROTSTS_STARIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */\r
+ eEvent = MASTER_SEND_H_RD_ADDRESS;\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */\r
+ eEvent = MASTER_READ_DATA;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_NACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_H_RD_ADDRESS)\r
+ {\r
+ u8Err = 1U;\r
+ }\r
+ else\r
+ {\r
+ rdata = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */\r
+ }\r
+\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_STORIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ u8Xfering = 0U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ u8Err = 1U;\r
+ break;\r
+ }\r
+\r
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */\r
+ }\r
+\r
+ if(u8Err)\r
+ rdata = 0U;\r
+\r
+ return rdata; /* Return read data */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Read multi bytes from Slave\r
+ *\r
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[out] *rdata Point to array to store data from Slave\r
+ * @param[in] u32rLen How many bytes need to read from Slave\r
+ *\r
+ * @return A length of how many bytes have been received\r
+ *\r
+ * @details The function is used for USCI_I2C Master to read multi data bytes from Slave.\r
+ *\r
+ *\r
+ */\r
+uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen)\r
+{\r
+ uint8_t u8Xfering = 1U, u8Ctrl = 0U;\r
+ uint32_t u32rxLen = 0U;\r
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;\r
+\r
+ UI2C_START(ui2c); /* Send START */\r
+\r
+ while(u8Xfering)\r
+ {\r
+ while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */\r
+\r
+ switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)\r
+ {\r
+ case UI2C_PROTSTS_STARIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */\r
+ eEvent = MASTER_SEND_H_RD_ADDRESS;\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_H_RD_ADDRESS)\r
+ {\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);\r
+ eEvent = MASTER_READ_DATA;\r
+ }\r
+ else\r
+ {\r
+ rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */\r
+\r
+ if(u32rxLen < (u32rLen - 1U))\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);\r
+ else\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ }\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_NACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */\r
+\r
+ if(eEvent == MASTER_READ_DATA)\r
+ rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */\r
+\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_STORIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ u8Xfering = 0U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ break;\r
+ }\r
+\r
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */\r
+ }\r
+\r
+ return u32rxLen; /* Return bytes length that have been received */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Specify a byte register address and read a byte from Slave\r
+ *\r
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u8DataAddr Specify a address(1 byte) of data read from\r
+ *\r
+ * @return Read a byte data from Slave\r
+ *\r
+ * @details The function is used for USCI_I2C Master specify a byte address that a data byte read from Slave.\r
+ *\r
+ *\r
+ */\r
+uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)\r
+{\r
+ uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U;\r
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;\r
+\r
+ UI2C_START(ui2c); /* Send START */\r
+\r
+ while(u8Xfering)\r
+ {\r
+ while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */\r
+\r
+ switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)\r
+ {\r
+ case UI2C_PROTSTS_STARIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_START)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */\r
+ eEvent = MASTER_SEND_ADDRESS;\r
+ }\r
+ else if(eEvent == MASTER_SEND_REPEAT_START)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */\r
+ eEvent = MASTER_SEND_H_RD_ADDRESS;\r
+ }\r
+\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_ADDRESS)\r
+ {\r
+ UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ eEvent = MASTER_SEND_DATA;\r
+ }\r
+ else if(eEvent == MASTER_SEND_DATA)\r
+ {\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */\r
+ eEvent = MASTER_SEND_REPEAT_START;\r
+ }\r
+ else\r
+ {\r
+ /* SLA+R ACK */\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ eEvent = MASTER_READ_DATA;\r
+ }\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_NACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */\r
+\r
+ if(eEvent == MASTER_READ_DATA)\r
+ {\r
+ rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */\r
+ }\r
+ else\r
+ {\r
+ u8Err = 1U;\r
+ }\r
+\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_STORIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ u8Xfering = 0U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ u8Err = 1U;\r
+ break;\r
+ }\r
+\r
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */\r
+ }\r
+\r
+ if(u8Err)\r
+ rdata = 0U; /* If occurs error, return 0 */\r
+\r
+ return rdata; /* Return read data */\r
+}\r
+\r
+/**\r
+ * @brief Specify a byte register address and read multi bytes from Slave\r
+ *\r
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u8DataAddr Specify a address (1 bytes) of data read from\r
+ * @param[out] *rdata Point to array to store data from Slave\r
+ * @param[in] u32rLen How many bytes need to read from Slave\r
+ *\r
+ * @return A length of how many bytes have been received\r
+ *\r
+ * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes read from Slave.\r
+ *\r
+ *\r
+ */\r
+uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen)\r
+{\r
+ uint8_t u8Xfering = 1U, u8Ctrl = 0U;\r
+ uint32_t u32rxLen = 0U;\r
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;\r
+\r
+ UI2C_START(ui2c); /* Send START */\r
+\r
+ while(u8Xfering)\r
+ {\r
+ while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */\r
+\r
+ switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)\r
+ {\r
+ case UI2C_PROTSTS_STARIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_START)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */\r
+ eEvent = MASTER_SEND_ADDRESS;\r
+ }\r
+ else if(eEvent == MASTER_SEND_REPEAT_START)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */\r
+ eEvent = MASTER_SEND_H_RD_ADDRESS;\r
+ }\r
+\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_ADDRESS)\r
+ {\r
+ UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ eEvent = MASTER_SEND_DATA;\r
+ }\r
+ else if(eEvent == MASTER_SEND_DATA)\r
+ {\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */\r
+ eEvent = MASTER_SEND_REPEAT_START;\r
+ }\r
+ else if(eEvent == MASTER_SEND_H_RD_ADDRESS)\r
+ {\r
+ /* SLA+R ACK */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);\r
+ eEvent = MASTER_READ_DATA;\r
+ }\r
+ else\r
+ {\r
+ rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */\r
+\r
+ if(u32rxLen < u32rLen - 1U)\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);\r
+ else\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ }\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_NACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */\r
+\r
+ if(eEvent == MASTER_READ_DATA)\r
+ rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */\r
+\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_STORIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ u8Xfering = 0U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ break;\r
+ }\r
+\r
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */\r
+ }\r
+\r
+ return u32rxLen; /* Return bytes length that have been received */\r
+}\r
+\r
+/**\r
+ * @brief Specify two bytes register address and read a byte from Slave\r
+ *\r
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u16DataAddr Specify a address(2 byte) of data read from\r
+ *\r
+ * @return Read a byte data from Slave\r
+ *\r
+ * @details The function is used for USCI_I2C Master specify two bytes address that a data byte read from Slave.\r
+ *\r
+ *\r
+ */\r
+uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr)\r
+{\r
+ uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Addr = 1U, u8Ctrl = 0U;\r
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;\r
+\r
+ UI2C_START(ui2c); /* Send START */\r
+\r
+ while(u8Xfering)\r
+ {\r
+ while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */\r
+\r
+ switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)\r
+ {\r
+ case UI2C_PROTSTS_STARIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_START)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */\r
+ eEvent = MASTER_SEND_ADDRESS;\r
+ }\r
+ else if(eEvent == MASTER_SEND_REPEAT_START)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */\r
+ eEvent = MASTER_SEND_H_RD_ADDRESS;\r
+ }\r
+\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_ADDRESS)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte address of register */\r
+ eEvent = MASTER_SEND_DATA;\r
+ }\r
+ else if(eEvent == MASTER_SEND_DATA)\r
+ {\r
+ if(u8Addr)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */\r
+ u8Addr = 0;\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */\r
+ eEvent = MASTER_SEND_REPEAT_START;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* SLA+R ACK */\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ eEvent = MASTER_READ_DATA;\r
+ }\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_NACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */\r
+\r
+ if(eEvent == MASTER_READ_DATA)\r
+ {\r
+ rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */\r
+ }\r
+ else\r
+ {\r
+ u8Err = 1U;\r
+ }\r
+\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_STORIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ u8Xfering = 0U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ u8Err = 1U;\r
+ break;\r
+ }\r
+\r
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */\r
+ }\r
+\r
+ if(u8Err)\r
+ rdata = 0U; /* If occurs error, return 0 */\r
+\r
+ return rdata; /* Return read data */\r
+}\r
+\r
+/**\r
+ * @brief Specify two bytes register address and read multi bytes from Slave\r
+ *\r
+ * @param[in] *ui2c The pointer of the specified USCI_I2C module.\r
+ * @param[in] u8SlaveAddr Access Slave address(7-bit)\r
+ * @param[in] u16DataAddr Specify a address (2 bytes) of data read from\r
+ * @param[out] *rdata Point to array to store data from Slave\r
+ * @param[in] u32rLen How many bytes need to read from Slave\r
+ *\r
+ * @return A length of how many bytes have been received\r
+ *\r
+ * @details The function is used for USCI_I2C Master specify two bytes address that multi data bytes read from Slave.\r
+ *\r
+ *\r
+ */\r
+uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen)\r
+{\r
+ uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U;\r
+ uint32_t u32rxLen = 0U;\r
+ enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;\r
+\r
+ UI2C_START(ui2c); /* Send START */\r
+\r
+ while(u8Xfering)\r
+ {\r
+ while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */\r
+\r
+ switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)\r
+ {\r
+ case UI2C_PROTSTS_STARIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_START)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */\r
+ eEvent = MASTER_SEND_ADDRESS;\r
+ }\r
+ else if(eEvent == MASTER_SEND_REPEAT_START)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */\r
+ eEvent = MASTER_SEND_H_RD_ADDRESS;\r
+ }\r
+\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */\r
+\r
+ if(eEvent == MASTER_SEND_ADDRESS)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte address of register */\r
+ eEvent = MASTER_SEND_DATA;\r
+ }\r
+ else if(eEvent == MASTER_SEND_DATA)\r
+ {\r
+ if(u8Addr)\r
+ {\r
+ UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */\r
+ u8Addr = 0;\r
+ }\r
+ else\r
+ {\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */\r
+ eEvent = MASTER_SEND_REPEAT_START;\r
+ }\r
+ }\r
+ else if(eEvent == MASTER_SEND_H_RD_ADDRESS)\r
+ {\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);\r
+ eEvent = MASTER_READ_DATA;\r
+ }\r
+ else\r
+ {\r
+ rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */\r
+\r
+ if(u32rxLen < u32rLen - 1U)\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);\r
+ else\r
+ u8Ctrl = UI2C_CTL_PTRG;\r
+ }\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_NACKIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */\r
+\r
+ if(eEvent == MASTER_READ_DATA)\r
+ rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */\r
+\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+\r
+ break;\r
+\r
+ case UI2C_PROTSTS_STORIF_Msk:\r
+ UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */\r
+ u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */\r
+ u8Xfering = 0U;\r
+ break;\r
+\r
+ case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */\r
+ default: /* Unknow status */\r
+ u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */\r
+ break;\r
+ }\r
+\r
+ UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */\r
+ }\r
+\r
+ return u32rxLen; /* Return bytes length that have been received */\r
+}\r
+\r
+/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group USCI_I2C_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/****************************************************************************//**\r
+ * @file usci_spi.c\r
+ * @version V3.00\r
+ * @brief M2351 series USCI_SPI driver source file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USCI_SPI_Driver USCI_SPI Driver\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief This function make USCI_SPI module be ready to transfer.\r
+ * By default, the USCI_SPI transfer sequence is MSB first, the slave selection\r
+ * signal is active low and the automatic slave select function is disabled. In\r
+ * Slave mode, the u32BusClock must be NULL and the USCI_SPI clock\r
+ * divider setting will be 0.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are:\r
+ * - \ref USPI_SLAVE\r
+ * - \ref USPI_MASTER\r
+ * @param[in] u32SPIMode Decide the transfer timing. Valid values are:\r
+ * - \ref USPI_MODE_0\r
+ * - \ref USPI_MODE_1\r
+ * - \ref USPI_MODE_2\r
+ * - \ref USPI_MODE_3\r
+ * @param[in] u32DataWidth The data width of a USCI_SPI transaction.\r
+ * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock in Hz.\r
+ * @return Actual frequency of USCI_SPI peripheral clock.\r
+ */\r
+uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)\r
+{\r
+ uint32_t u32ClkDiv = 0UL;\r
+ uint32_t u32Pclk;\r
+ uint32_t u32RetValue = 0UL;\r
+\r
+ if((uspi == USPI0) || (uspi == USPI0_NS))\r
+ {\r
+ u32Pclk = CLK_GetPCLK0Freq();\r
+ }\r
+ else\r
+ {\r
+ u32Pclk = CLK_GetPCLK1Freq();\r
+ }\r
+\r
+ if(u32BusClock != 0UL)\r
+ {\r
+ u32ClkDiv = (uint32_t)((((((u32Pclk / 2UL) * 10UL) / (u32BusClock)) + 5UL) / 10UL) - 1UL); /* Compute proper divider for USCI_SPI clock */\r
+ }\r
+\r
+ /* Enable USCI_SPI protocol */\r
+ uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;\r
+ uspi->CTL = 1UL << USPI_CTL_FUNMODE_Pos;\r
+\r
+ /* Data format configuration */\r
+ if(u32DataWidth == 16UL)\r
+ {\r
+ u32DataWidth = 0UL;\r
+ }\r
+ uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk;\r
+ uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos);\r
+\r
+ /* MSB data format */\r
+ uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk;\r
+\r
+ /* Set slave selection signal active low */\r
+ if(u32MasterSlave == USPI_MASTER)\r
+ {\r
+ uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk;\r
+ }\r
+ else\r
+ {\r
+ uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk;\r
+ }\r
+\r
+ /* Set operating mode and transfer timing */\r
+ uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk);\r
+ uspi->PROTCTL |= (u32MasterSlave | u32SPIMode);\r
+\r
+ /* Set USCI_SPI bus clock */\r
+ uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;\r
+ uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);\r
+ uspi->PROTCTL |= USPI_PROTCTL_PROTEN_Msk;\r
+\r
+ if(u32BusClock != 0UL)\r
+ {\r
+ u32RetValue = (u32Pclk / ((u32ClkDiv + 1UL) << 1UL));\r
+ }\r
+ else\r
+ {\r
+ u32RetValue = 0UL;\r
+ }\r
+\r
+ return u32RetValue;\r
+}\r
+\r
+/**\r
+ * @brief Disable USCI_SPI function mode.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None\r
+ */\r
+void USPI_Close(USPI_T *uspi)\r
+{\r
+ uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Clear Rx buffer.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None\r
+ */\r
+void USPI_ClearRxBuf(USPI_T *uspi)\r
+{\r
+ uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Clear Tx buffer.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None\r
+ */\r
+void USPI_ClearTxBuf(USPI_T *uspi)\r
+{\r
+ uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable the automatic slave select function.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None\r
+ */\r
+void USPI_DisableAutoSS(USPI_T *uspi)\r
+{\r
+ uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk);\r
+}\r
+\r
+/**\r
+ * @brief Enable the automatic slave select function. Only available in Master mode.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32SSPinMask This parameter is not used.\r
+ * @param[in] u32ActiveLevel The active level of slave select signal. Valid values are:\r
+ * - \ref USPI_SS_ACTIVE_HIGH\r
+ * - \ref USPI_SS_ACTIVE_LOW\r
+ * @return None\r
+ */\r
+void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)\r
+{\r
+ uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel;\r
+ uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Set the USCI_SPI bus clock. Only available in Master mode.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock.\r
+ * @return Actual frequency of USCI_SPI peripheral clock.\r
+ */\r
+uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock)\r
+{\r
+ uint32_t u32ClkDiv;\r
+ uint32_t u32Pclk;\r
+\r
+ if((uspi == USPI0) || (uspi == USPI0_NS))\r
+ {\r
+ u32Pclk = CLK_GetPCLK0Freq();\r
+ }\r
+ else\r
+ {\r
+ u32Pclk = CLK_GetPCLK1Freq();\r
+ }\r
+\r
+ u32ClkDiv = (uint32_t)((((((u32Pclk / 2UL) * 10UL) / (u32BusClock)) + 5UL) / 10UL) - 1UL); /* Compute proper divider for USCI_SPI clock */\r
+\r
+ /* Set USCI_SPI bus clock */\r
+ uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;\r
+ uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);\r
+\r
+ return (u32Pclk / ((u32ClkDiv + 1UL) << 1UL));\r
+}\r
+\r
+/**\r
+ * @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return Actual USCI_SPI bus clock frequency.\r
+ */\r
+uint32_t USPI_GetBusClock(USPI_T *uspi)\r
+{\r
+ uint32_t u32ClkDiv, u32BusClk;\r
+\r
+ u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos;\r
+\r
+ if((uspi == USPI0) || (uspi == USPI0_NS))\r
+ {\r
+ u32BusClk = (CLK_GetPCLK0Freq() / ((u32ClkDiv + 1UL) << 1UL));\r
+ }\r
+ else\r
+ {\r
+ u32BusClk = (CLK_GetPCLK1Freq() / ((u32ClkDiv + 1UL) << 1UL));\r
+ }\r
+\r
+ return u32BusClk;\r
+}\r
+\r
+/**\r
+ * @brief Enable related interrupts specified by u32Mask parameter.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32Mask The combination of all related interrupt enable bits.\r
+ * Each bit corresponds to a interrupt bit.\r
+ * This parameter decides which interrupts will be enabled. Valid values are:\r
+ * - \ref USPI_SSINACT_INT_MASK\r
+ * - \ref USPI_SSACT_INT_MASK\r
+ * - \ref USPI_SLVTO_INT_MASK\r
+ * - \ref USPI_SLVBE_INT_MASK\r
+ * - \ref USPI_TXUDR_INT_MASK\r
+ * - \ref USPI_RXOV_INT_MASK\r
+ * - \ref USPI_TXST_INT_MASK\r
+ * - \ref USPI_TXEND_INT_MASK\r
+ * - \ref USPI_RXST_INT_MASK\r
+ * - \ref USPI_RXEND_INT_MASK\r
+ * @return None\r
+ */\r
+void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask)\r
+{\r
+ /* Enable slave selection signal inactive interrupt flag */\r
+ if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK)\r
+ {\r
+ uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk;\r
+ }\r
+\r
+ /* Enable slave selection signal active interrupt flag */\r
+ if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK)\r
+ {\r
+ uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk;\r
+ }\r
+\r
+ /* Enable slave time-out interrupt flag */\r
+ if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK)\r
+ {\r
+ uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk;\r
+ }\r
+\r
+ /* Enable slave bit count error interrupt flag */\r
+ if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK)\r
+ {\r
+ uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk;\r
+ }\r
+\r
+ /* Enable TX under run interrupt flag */\r
+ if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK)\r
+ {\r
+ uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk;\r
+ }\r
+\r
+ /* Enable RX overrun interrupt flag */\r
+ if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)\r
+ {\r
+ uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk;\r
+ }\r
+\r
+ /* Enable TX start interrupt flag */\r
+ if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)\r
+ {\r
+ uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk;\r
+ }\r
+\r
+ /* Enable TX end interrupt flag */\r
+ if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK)\r
+ {\r
+ uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk;\r
+ }\r
+\r
+ /* Enable RX start interrupt flag */\r
+ if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)\r
+ {\r
+ uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk;\r
+ }\r
+\r
+ /* Enable RX end interrupt flag */\r
+ if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK)\r
+ {\r
+ uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable related interrupts specified by u32Mask parameter.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32Mask The combination of all related interrupt enable bits.\r
+ * Each bit corresponds to a interrupt bit.\r
+ * This parameter decides which interrupts will be disabled. Valid values are:\r
+ * - \ref USPI_SSINACT_INT_MASK\r
+ * - \ref USPI_SSACT_INT_MASK\r
+ * - \ref USPI_SLVTO_INT_MASK\r
+ * - \ref USPI_SLVBE_INT_MASK\r
+ * - \ref USPI_TXUDR_INT_MASK\r
+ * - \ref USPI_RXOV_INT_MASK\r
+ * - \ref USPI_TXST_INT_MASK\r
+ * - \ref USPI_TXEND_INT_MASK\r
+ * - \ref USPI_RXST_INT_MASK\r
+ * - \ref USPI_RXEND_INT_MASK\r
+ * @return None\r
+ */\r
+void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask)\r
+{\r
+ /* Disable slave selection signal inactive interrupt flag */\r
+ if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK)\r
+ {\r
+ uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk;\r
+ }\r
+\r
+ /* Disable slave selection signal active interrupt flag */\r
+ if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK)\r
+ {\r
+ uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk;\r
+ }\r
+\r
+ /* Disable slave time-out interrupt flag */\r
+ if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK)\r
+ {\r
+ uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk;\r
+ }\r
+\r
+ /* Disable slave bit count error interrupt flag */\r
+ if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK)\r
+ {\r
+ uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk;\r
+ }\r
+\r
+ /* Disable TX under run interrupt flag */\r
+ if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK)\r
+ {\r
+ uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk;\r
+ }\r
+\r
+ /* Disable RX overrun interrupt flag */\r
+ if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)\r
+ {\r
+ uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk;\r
+ }\r
+\r
+ /* Disable TX start interrupt flag */\r
+ if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)\r
+ {\r
+ uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk;\r
+ }\r
+\r
+ /* Disable TX end interrupt flag */\r
+ if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK)\r
+ {\r
+ uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk;\r
+ }\r
+\r
+ /* Disable RX start interrupt flag */\r
+ if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)\r
+ {\r
+ uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk;\r
+ }\r
+\r
+ /* Disable RX end interrupt flag */\r
+ if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK)\r
+ {\r
+ uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get interrupt flag.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32Mask The combination of all related interrupt sources.\r
+ * Each bit corresponds to a interrupt source.\r
+ * This parameter decides which interrupt flags will be read. It is combination of:\r
+ * - \ref USPI_SSINACT_INT_MASK\r
+ * - \ref USPI_SSACT_INT_MASK\r
+ * - \ref USPI_SLVTO_INT_MASK\r
+ * - \ref USPI_SLVBE_INT_MASK\r
+ * - \ref USPI_TXUDR_INT_MASK\r
+ * - \ref USPI_RXOV_INT_MASK\r
+ * - \ref USPI_TXST_INT_MASK\r
+ * - \ref USPI_TXEND_INT_MASK\r
+ * - \ref USPI_RXST_INT_MASK\r
+ * - \ref USPI_RXEND_INT_MASK\r
+ * @return Interrupt flags of selected sources.\r
+ */\r
+uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask)\r
+{\r
+ uint32_t u32ProtStatus, u32BufStatus;\r
+ uint32_t u32IntFlag = 0UL;\r
+\r
+ u32ProtStatus = uspi->PROTSTS;\r
+ u32BufStatus = uspi->BUFSTS;\r
+\r
+ /* Check slave selection signal inactive interrupt flag */\r
+ if((u32Mask & USPI_SSINACT_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SSINAIF_Msk))\r
+ {\r
+ u32IntFlag |= USPI_SSINACT_INT_MASK;\r
+ }\r
+\r
+ /* Check slave selection signal active interrupt flag */\r
+ if((u32Mask & USPI_SSACT_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SSACTIF_Msk))\r
+ {\r
+ u32IntFlag |= USPI_SSACT_INT_MASK;\r
+ }\r
+\r
+ /* Check slave time-out interrupt flag */\r
+ if((u32Mask & USPI_SLVTO_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SLVTOIF_Msk))\r
+ {\r
+ u32IntFlag |= USPI_SLVTO_INT_MASK;\r
+ }\r
+\r
+ /* Check slave bit count error interrupt flag */\r
+ if((u32Mask & USPI_SLVBE_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SLVBEIF_Msk))\r
+ {\r
+ u32IntFlag |= USPI_SLVBE_INT_MASK;\r
+ }\r
+\r
+ /* Check TX under run interrupt flag */\r
+ if((u32Mask & USPI_TXUDR_INT_MASK) && (u32BufStatus & USPI_BUFSTS_TXUDRIF_Msk))\r
+ {\r
+ u32IntFlag |= USPI_TXUDR_INT_MASK;\r
+ }\r
+\r
+ /* Check RX overrun interrupt flag */\r
+ if((u32Mask & USPI_RXOV_INT_MASK) && (u32BufStatus & USPI_BUFSTS_RXOVIF_Msk))\r
+ {\r
+ u32IntFlag |= USPI_RXOV_INT_MASK;\r
+ }\r
+\r
+ /* Check TX start interrupt flag */\r
+ if((u32Mask & USPI_TXST_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_TXSTIF_Msk))\r
+ {\r
+ u32IntFlag |= USPI_TXST_INT_MASK;\r
+ }\r
+\r
+ /* Check TX end interrupt flag */\r
+ if((u32Mask & USPI_TXEND_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_TXENDIF_Msk))\r
+ {\r
+ u32IntFlag |= USPI_TXEND_INT_MASK;\r
+ }\r
+\r
+ /* Check RX start interrupt flag */\r
+ if((u32Mask & USPI_RXST_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_RXSTIF_Msk))\r
+ {\r
+ u32IntFlag |= USPI_RXST_INT_MASK;\r
+ }\r
+\r
+ /* Check RX end interrupt flag */\r
+ if((u32Mask & USPI_RXEND_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_RXENDIF_Msk))\r
+ {\r
+ u32IntFlag |= USPI_RXEND_INT_MASK;\r
+ }\r
+\r
+ return u32IntFlag;\r
+}\r
+\r
+/**\r
+ * @brief Clear interrupt flag.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32Mask The combination of all related interrupt sources.\r
+ * Each bit corresponds to a interrupt source.\r
+ * This parameter decides which interrupt flags will be cleared. It could be the combination of:\r
+ * - \ref USPI_SSINACT_INT_MASK\r
+ * - \ref USPI_SSACT_INT_MASK\r
+ * - \ref USPI_SLVTO_INT_MASK\r
+ * - \ref USPI_SLVBE_INT_MASK\r
+ * - \ref USPI_TXUDR_INT_MASK\r
+ * - \ref USPI_RXOV_INT_MASK\r
+ * - \ref USPI_TXST_INT_MASK\r
+ * - \ref USPI_TXEND_INT_MASK\r
+ * - \ref USPI_RXST_INT_MASK\r
+ * - \ref USPI_RXEND_INT_MASK\r
+ * @return None\r
+ */\r
+void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask)\r
+{\r
+ /* Clear slave selection signal inactive interrupt flag */\r
+ if(u32Mask & USPI_SSINACT_INT_MASK)\r
+ {\r
+ uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk;\r
+ }\r
+\r
+ /* Clear slave selection signal active interrupt flag */\r
+ if(u32Mask & USPI_SSACT_INT_MASK)\r
+ {\r
+ uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk;\r
+ }\r
+\r
+ /* Clear slave time-out interrupt flag */\r
+ if(u32Mask & USPI_SLVTO_INT_MASK)\r
+ {\r
+ uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk;\r
+ }\r
+\r
+ /* Clear slave bit count error interrupt flag */\r
+ if(u32Mask & USPI_SLVBE_INT_MASK)\r
+ {\r
+ uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk;\r
+ }\r
+\r
+ /* Clear TX under run interrupt flag */\r
+ if(u32Mask & USPI_TXUDR_INT_MASK)\r
+ {\r
+ uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk;\r
+ }\r
+\r
+ /* Clear RX overrun interrupt flag */\r
+ if(u32Mask & USPI_RXOV_INT_MASK)\r
+ {\r
+ uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk;\r
+ }\r
+\r
+ /* Clear TX start interrupt flag */\r
+ if(u32Mask & USPI_TXST_INT_MASK)\r
+ {\r
+ uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk;\r
+ }\r
+\r
+ /* Clear TX end interrupt flag */\r
+ if(u32Mask & USPI_TXEND_INT_MASK)\r
+ {\r
+ uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk;\r
+ }\r
+\r
+ /* Clear RX start interrupt flag */\r
+ if(u32Mask & USPI_RXST_INT_MASK)\r
+ {\r
+ uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk;\r
+ }\r
+\r
+ /* Clear RX end interrupt flag */\r
+ if(u32Mask & USPI_RXEND_INT_MASK)\r
+ {\r
+ uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get USCI_SPI status.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @param[in] u32Mask The combination of all related sources.\r
+ * Each bit corresponds to a source.\r
+ * This parameter decides which flags will be read. It is combination of:\r
+ * - \ref USPI_BUSY_MASK\r
+ * - \ref USPI_RX_EMPTY_MASK\r
+ * - \ref USPI_RX_FULL_MASK\r
+ * - \ref USPI_TX_EMPTY_MASK\r
+ * - \ref USPI_TX_FULL_MASK\r
+ * - \ref USPI_SSLINE_STS_MASK\r
+ * @return Flags of selected sources.\r
+ */\r
+uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask)\r
+{\r
+ uint32_t u32ProtStatus, u32BufStatus;\r
+ uint32_t u32Flag = 0UL;\r
+\r
+ u32ProtStatus = uspi->PROTSTS;\r
+ u32BufStatus = uspi->BUFSTS;\r
+\r
+ /* Check busy status */\r
+ if((u32Mask & USPI_BUSY_MASK) && (u32ProtStatus & USPI_PROTSTS_BUSY_Msk))\r
+ {\r
+ u32Flag |= USPI_BUSY_MASK;\r
+ }\r
+\r
+ /* Check RX empty flag */\r
+ if((u32Mask & USPI_RX_EMPTY_MASK) && (u32BufStatus & USPI_BUFSTS_RXEMPTY_Msk))\r
+ {\r
+ u32Flag |= USPI_RX_EMPTY_MASK;\r
+ }\r
+\r
+ /* Check RX full flag */\r
+ if((u32Mask & USPI_RX_FULL_MASK) && (u32BufStatus & USPI_BUFSTS_RXFULL_Msk))\r
+ {\r
+ u32Flag |= USPI_RX_FULL_MASK;\r
+ }\r
+\r
+ /* Check TX empty flag */\r
+ if((u32Mask & USPI_TX_EMPTY_MASK) && (u32BufStatus & USPI_BUFSTS_TXEMPTY_Msk))\r
+ {\r
+ u32Flag |= USPI_TX_EMPTY_MASK;\r
+ }\r
+\r
+ /* Check TX full flag */\r
+ if((u32Mask & USPI_TX_FULL_MASK) && (u32BufStatus & USPI_BUFSTS_TXFULL_Msk))\r
+ {\r
+ u32Flag |= USPI_TX_FULL_MASK;\r
+ }\r
+\r
+ /* Check USCI_SPI_SS line status */\r
+ if((u32Mask & USPI_SSLINE_STS_MASK) && (u32ProtStatus & USPI_PROTSTS_SSLINE_Msk))\r
+ {\r
+ u32Flag |= USPI_SSLINE_STS_MASK;\r
+ }\r
+\r
+ return u32Flag;\r
+}\r
+\r
+/**\r
+ * @brief Enable USCI_SPI Wake-up Function.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None\r
+ */\r
+void USPI_EnableWakeup(USPI_T *uspi)\r
+{\r
+ uspi->WKCTL |= USPI_WKCTL_WKEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable USCI_SPI Wake-up Function.\r
+ * @param[in] uspi The pointer of the specified USCI_SPI module.\r
+ * @return None\r
+ */\r
+void USPI_DisableWakeup(USPI_T *uspi)\r
+{\r
+ uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk;\r
+}\r
+\r
+/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group USCI_SPI_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file usci_uart.c\r
+ * @version V3.00\r
+ * @brief M2351 series USCI UART (UUART) driver source file\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+\r
+#include <stdio.h>\r
+#include "NuMicro.h"\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USCI_UART_Driver USCI_UART Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Clear USCI_UART specified interrupt flag\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ * @param[in] u32Mask The combination of all related interrupt sources.\r
+ * Each bit corresponds to a interrupt source.\r
+ * This parameter decides which interrupt flags will be cleared. It could be the combination of:\r
+ * - \ref UUART_ABR_INT_MASK\r
+ * - \ref UUART_RLS_INT_MASK\r
+ * - \ref UUART_BUF_RXOV_INT_MASK\r
+ * - \ref UUART_TXST_INT_MASK\r
+ * - \ref UUART_TXEND_INT_MASK\r
+ * - \ref UUART_RXST_INT_MASK\r
+ * - \ref UUART_RXEND_INT_MASK\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to clear USCI_UART related interrupt flags specified by u32Mask parameter.\r
+ */\r
+\r
+void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask)\r
+{\r
+\r
+ if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */\r
+ {\r
+ uuart->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk;\r
+ }\r
+\r
+ if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */\r
+ {\r
+ uuart->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk);\r
+ }\r
+\r
+ if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */\r
+ {\r
+ uuart->BUFSTS = UUART_BUFSTS_RXOVIF_Msk;\r
+ }\r
+\r
+ if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */\r
+ {\r
+ uuart->PROTSTS = UUART_PROTSTS_TXSTIF_Msk;\r
+ }\r
+\r
+ if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */\r
+ {\r
+ uuart->PROTSTS = UUART_PROTSTS_TXENDIF_Msk;\r
+ }\r
+\r
+ if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */\r
+ {\r
+ uuart->PROTSTS = UUART_PROTSTS_RXSTIF_Msk;\r
+ }\r
+\r
+ if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */\r
+ {\r
+ uuart->PROTSTS = UUART_PROTSTS_RXENDIF_Msk;\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Get USCI_UART specified interrupt flag\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ * @param[in] u32Mask The combination of all related interrupt sources.\r
+ * Each bit corresponds to a interrupt source.\r
+ * This parameter decides which interrupt flags will be read. It is combination of:\r
+ * - \ref UUART_ABR_INT_MASK\r
+ * - \ref UUART_RLS_INT_MASK\r
+ * - \ref UUART_BUF_RXOV_INT_MASK\r
+ * - \ref UUART_TXST_INT_MASK\r
+ * - \ref UUART_TXEND_INT_MASK\r
+ * - \ref UUART_RXST_INT_MASK\r
+ * - \ref UUART_RXEND_INT_MASK\r
+ *\r
+ * @return Interrupt flags of selected sources.\r
+ *\r
+ * @details The function is used to get USCI_UART related interrupt flags specified by u32Mask parameter.\r
+ */\r
+\r
+uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask)\r
+{\r
+ uint32_t u32IntFlag = 0ul;\r
+ uint32_t u32Tmp1, u32Tmp2;\r
+\r
+ /* Check Auto-baud Rate Interrupt Flag */\r
+ u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK);\r
+ u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk);\r
+ if(u32Tmp1 && u32Tmp2)\r
+ {\r
+ u32IntFlag |= UUART_ABR_INT_MASK;\r
+ }\r
+\r
+ /* Check Receive Line Status Interrupt Flag */\r
+ u32Tmp1 = (u32Mask & UUART_RLS_INT_MASK);\r
+ u32Tmp2 = (uuart->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk));\r
+ if(u32Tmp1 && u32Tmp2)\r
+ {\r
+ u32IntFlag |= UUART_RLS_INT_MASK;\r
+ }\r
+\r
+ /* Check Receive Buffer Over-run Error Interrupt Flag */\r
+ u32Tmp1 = (u32Mask & UUART_BUF_RXOV_INT_MASK);\r
+ u32Tmp2 = (uuart->BUFSTS & UUART_BUFSTS_RXOVIF_Msk);\r
+ if(u32Tmp1 && u32Tmp2)\r
+ {\r
+ u32IntFlag |= UUART_BUF_RXOV_INT_MASK;\r
+ }\r
+\r
+ /* Check Transmit Start Interrupt Flag */\r
+ u32Tmp1 = (u32Mask & UUART_TXST_INT_MASK);\r
+ u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXSTIF_Msk);\r
+ if(u32Tmp1 && u32Tmp2)\r
+ {\r
+ u32IntFlag |= UUART_TXST_INT_MASK;\r
+ }\r
+\r
+ /* Check Transmit End Interrupt Flag */\r
+ u32Tmp1 = (u32Mask & UUART_TXEND_INT_MASK);\r
+ u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXENDIF_Msk);\r
+ if(u32Tmp1 && u32Tmp2)\r
+ {\r
+ u32IntFlag |= UUART_TXEND_INT_MASK;\r
+ }\r
+\r
+ /* Check Receive Start Interrupt Flag */\r
+ u32Tmp1 = (u32Mask & UUART_RXST_INT_MASK);\r
+ u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXSTIF_Msk);\r
+ if(u32Tmp1 && u32Tmp2)\r
+ {\r
+ u32IntFlag |= UUART_RXST_INT_MASK;\r
+ }\r
+\r
+ /* Check Receive End Interrupt Flag */\r
+ u32Tmp1 = (u32Mask & UUART_RXEND_INT_MASK);\r
+ u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXENDIF_Msk);\r
+ if(u32Tmp1 && u32Tmp2)\r
+ {\r
+ u32IntFlag |= UUART_RXEND_INT_MASK;\r
+ }\r
+\r
+ return u32IntFlag;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable USCI_UART function mode\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to disable USCI_UART function mode.\r
+ */\r
+void UUART_Close(UUART_T* uuart)\r
+{\r
+ uuart->CTL = 0UL;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable interrupt function.\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ * @param[in] u32Mask The combination of all related interrupt enable bits.\r
+ * Each bit corresponds to a interrupt enable bit.\r
+ * This parameter decides which interrupts will be disabled. It is combination of:\r
+ * - \ref UUART_ABR_INT_MASK\r
+ * - \ref UUART_RLS_INT_MASK\r
+ * - \ref UUART_BUF_RXOV_INT_MASK\r
+ * - \ref UUART_TXST_INT_MASK\r
+ * - \ref UUART_TXEND_INT_MASK\r
+ * - \ref UUART_RXST_INT_MASK\r
+ * - \ref UUART_RXEND_INT_MASK\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to disabled USCI_UART related interrupts specified by u32Mask parameter.\r
+ */\r
+void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask)\r
+{\r
+\r
+ /* Disable Auto-baud rate interrupt flag */\r
+ if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK)\r
+ {\r
+ uuart->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk;\r
+ }\r
+\r
+ /* Disable receive line status interrupt flag */\r
+ if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK)\r
+ {\r
+ uuart->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk;\r
+ }\r
+\r
+ /* Disable RX overrun interrupt flag */\r
+ if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK)\r
+ {\r
+ uuart->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk;\r
+ }\r
+\r
+ /* Disable TX start interrupt flag */\r
+ if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK)\r
+ {\r
+ uuart->INTEN &= ~UUART_INTEN_TXSTIEN_Msk;\r
+ }\r
+\r
+ /* Disable TX end interrupt flag */\r
+ if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK)\r
+ {\r
+ uuart->INTEN &= ~UUART_INTEN_TXENDIEN_Msk;\r
+ }\r
+\r
+ /* Disable RX start interrupt flag */\r
+ if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK)\r
+ {\r
+ uuart->INTEN &= ~UUART_INTEN_RXSTIEN_Msk;\r
+ }\r
+\r
+ /* Disable RX end interrupt flag */\r
+ if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK)\r
+ {\r
+ uuart->INTEN &= ~UUART_INTEN_RXENDIEN_Msk;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enable interrupt function.\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ * @param[in] u32Mask The combination of all related interrupt enable bits.\r
+ * Each bit corresponds to a interrupt enable bit.\r
+ * This parameter decides which interrupts will be enabled. It is combination of:\r
+ * - \ref UUART_ABR_INT_MASK\r
+ * - \ref UUART_RLS_INT_MASK\r
+ * - \ref UUART_BUF_RXOV_INT_MASK\r
+ * - \ref UUART_TXST_INT_MASK\r
+ * - \ref UUART_TXEND_INT_MASK\r
+ * - \ref UUART_RXST_INT_MASK\r
+ * - \ref UUART_RXEND_INT_MASK\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to enable USCI_UART related interrupts specified by u32Mask parameter..\r
+ */\r
+void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask)\r
+{\r
+ /* Enable Auto-baud rate interrupt flag */\r
+ if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK)\r
+ {\r
+ uuart->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk;\r
+ }\r
+\r
+ /* Enable receive line status interrupt flag */\r
+ if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK)\r
+ {\r
+ uuart->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk;\r
+ }\r
+\r
+ /* Enable RX overrun interrupt flag */\r
+ if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK)\r
+ {\r
+ uuart->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk;\r
+ }\r
+\r
+ /* Enable TX start interrupt flag */\r
+ if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK)\r
+ {\r
+ uuart->INTEN |= UUART_INTEN_TXSTIEN_Msk;\r
+ }\r
+\r
+ /* Enable TX end interrupt flag */\r
+ if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK)\r
+ {\r
+ uuart->INTEN |= UUART_INTEN_TXENDIEN_Msk;\r
+ }\r
+\r
+ /* Enable RX start interrupt flag */\r
+ if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK)\r
+ {\r
+ uuart->INTEN |= UUART_INTEN_RXSTIEN_Msk;\r
+ }\r
+\r
+ /* Enable RX end interrupt flag */\r
+ if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK)\r
+ {\r
+ uuart->INTEN |= UUART_INTEN_RXENDIEN_Msk;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Open and set USCI_UART function\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ * @param[in] u32baudrate The baud rate of USCI_UART module.\r
+ *\r
+ * @return Real baud rate of USCI_UART module.\r
+ *\r
+ * @details This function use to enable USCI_UART function and set baud-rate.\r
+ */\r
+uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate)\r
+{\r
+ uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv;\r
+ uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt;\r
+ uint32_t u32Div;\r
+\r
+ /* Get PCLK frequency */\r
+ if((uuart == UUART0) || (uuart == UUART0_NS))\r
+ {\r
+ u32PCLKFreq = CLK_GetPCLK0Freq();\r
+ }\r
+ else\r
+ {\r
+ u32PCLKFreq = CLK_GetPCLK1Freq();\r
+ }\r
+\r
+ /* Calculate baud rate divider */\r
+ u32Div = u32PCLKFreq / u32baudrate;\r
+ u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate;\r
+ u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div + 1ul));\r
+\r
+ if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul;\r
+\r
+ if(u32Div >= 65536ul)\r
+ {\r
+\r
+ /* Set the smallest baud rate that USCI_UART can generate */\r
+ u32PDSCnt = 0x4ul;\r
+ u32MinDSCnt = 0x10ul;\r
+ u32MinClkDiv = 0x400ul;\r
+\r
+ }\r
+ else\r
+ {\r
+\r
+ u32Tmp = 0x400ul * 0x10ul;\r
+ for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++)\r
+ {\r
+ if(u32Div <= (u32Tmp * u32PDSCnt)) break;\r
+ }\r
+\r
+ if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul;\r
+\r
+ u32Div = u32Div / u32PDSCnt;\r
+\r
+ /* Find best solution */\r
+ u32Min = (uint32_t) - 1;\r
+ u32MinDSCnt = 0ul;\r
+ u32MinClkDiv = 0ul;\r
+ u32Tmp = 0ul;\r
+\r
+ for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */\r
+ {\r
+\r
+ u32ClkDiv = u32Div / u32DSCnt;\r
+\r
+ if(u32ClkDiv > 0x400ul)\r
+ {\r
+ u32ClkDiv = 0x400ul;\r
+ u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);\r
+ u32Tmp2 = u32Tmp + 1ul;\r
+ }\r
+ else\r
+ {\r
+ u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);\r
+ u32Tmp2 = ((u32ClkDiv + 1ul) * u32DSCnt) - u32Div;\r
+ }\r
+\r
+ if(u32Tmp >= u32Tmp2)\r
+ {\r
+ u32ClkDiv = u32ClkDiv + 1ul;\r
+ }\r
+ else u32Tmp2 = u32Tmp;\r
+\r
+ if(u32Tmp2 < u32Min)\r
+ {\r
+ u32Min = u32Tmp2;\r
+ u32MinDSCnt = u32DSCnt;\r
+ u32MinClkDiv = u32ClkDiv;\r
+\r
+ /* Break when get good results */\r
+ if(u32Min == 0ul)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+ /* Enable USCI_UART protocol */\r
+ uuart->CTL &= ~UUART_CTL_FUNMODE_Msk;\r
+ uuart->CTL = 2ul << UUART_CTL_FUNMODE_Pos;\r
+\r
+ /* Set USCI_UART line configuration */\r
+ uuart->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk;\r
+ uuart->DATIN0 = (2ul << UUART_DATIN0_EDGEDET_Pos); /* Set falling edge detection */\r
+\r
+ /* Set USCI_UART baud rate */\r
+ uuart->BRGEN = ((u32MinClkDiv - 1ul) << UUART_BRGEN_CLKDIV_Pos) |\r
+ ((u32MinDSCnt - 1ul) << UUART_BRGEN_DSCNT_Pos) |\r
+ ((u32PDSCnt - 1ul) << UUART_BRGEN_PDSCNT_Pos);\r
+\r
+ uuart->PROTCTL |= UUART_PROTCTL_PROTEN_Msk;\r
+\r
+ return (u32PCLKFreq / u32PDSCnt / u32MinDSCnt / u32MinClkDiv);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Read USCI_UART data\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ * @param[in] pu8RxBuf The buffer to receive the data of receive buffer.\r
+ * @param[in] u32ReadBytes The read bytes number of data.\r
+ *\r
+ * @return Receive byte count\r
+ *\r
+ * @details The function is used to read Rx data from RX buffer and the data will be stored in pu8RxBuf.\r
+ */\r
+uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)\r
+{\r
+ uint32_t u32Count, u32delayno;\r
+\r
+ for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)\r
+ {\r
+ u32delayno = 0ul;\r
+\r
+ while(uuart->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) /* Check RX empty => failed */\r
+ {\r
+ u32delayno++;\r
+ if(u32delayno >= 0x40000000ul)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(u32delayno >= 0x40000000ul)\r
+ {\r
+ break;\r
+ }\r
+\r
+ pu8RxBuf[u32Count] = (uint8_t)uuart->RXDAT; /* Get Data from USCI RX */\r
+ }\r
+\r
+ return u32Count;\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set USCI_UART line configuration\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ * @param[in] u32baudrate The register value of baud rate of USCI_UART module.\r
+ * If u32baudrate = 0, USCI_UART baud rate will not change.\r
+ * @param[in] u32data_width The data length of USCI_UART module.\r
+ * - \ref UUART_WORD_LEN_6\r
+ * - \ref UUART_WORD_LEN_7\r
+ * - \ref UUART_WORD_LEN_8\r
+ * - \ref UUART_WORD_LEN_9\r
+ * @param[in] u32parity The parity setting (none/odd/even) of USCI_UART module.\r
+ * - \ref UUART_PARITY_NONE\r
+ * - \ref UUART_PARITY_ODD\r
+ * - \ref UUART_PARITY_EVEN\r
+ * @param[in] u32stop_bits The stop bit length (1/2 bit) of USCI_UART module.\r
+ * - \ref UUART_STOP_BIT_1\r
+ * - \ref UUART_STOP_BIT_2\r
+ *\r
+ * @return Real baud rate of USCI_UART module.\r
+ *\r
+ * @details This function use to config USCI_UART line setting.\r
+ */\r
+uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)\r
+{\r
+ uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv;\r
+ uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt;\r
+ uint32_t u32Div;\r
+\r
+ /* Get PCLK frequency */\r
+ if((uuart == UUART0) || (uuart == UUART0_NS))\r
+ {\r
+ u32PCLKFreq = CLK_GetPCLK0Freq();\r
+ }\r
+ else /* UUART1 */\r
+ {\r
+ u32PCLKFreq = CLK_GetPCLK1Freq();\r
+ }\r
+\r
+ if(u32baudrate != 0ul)\r
+ {\r
+\r
+ /* Calculate baud rate divider */\r
+ u32Div = u32PCLKFreq / u32baudrate;\r
+ u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate;\r
+ u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div + 1ul));\r
+\r
+ if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul;\r
+\r
+ if(u32Div >= 65536ul)\r
+ {\r
+\r
+ /* Set the smallest baud rate that USCI_UART can generate */\r
+ u32PDSCnt = 0x4ul;\r
+ u32MinDSCnt = 0x10ul;\r
+ u32MinClkDiv = 0x400ul;\r
+\r
+ }\r
+ else\r
+ {\r
+\r
+ u32Tmp = 0x400ul * 0x10ul;\r
+ for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++)\r
+ {\r
+ if(u32Div <= (u32Tmp * u32PDSCnt)) break;\r
+ }\r
+\r
+ if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul;\r
+\r
+ u32Div = u32Div / u32PDSCnt;\r
+\r
+ /* Find best solution */\r
+ u32Min = (uint32_t) - 1;\r
+ u32MinDSCnt = 0ul;\r
+ u32MinClkDiv = 0ul;\r
+\r
+ for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */\r
+ {\r
+ u32ClkDiv = u32Div / u32DSCnt;\r
+\r
+ if(u32ClkDiv > 0x400ul)\r
+ {\r
+ u32ClkDiv = 0x400ul;\r
+ u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);\r
+ u32Tmp2 = u32Tmp + 1ul;\r
+ }\r
+ else\r
+ {\r
+ u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);\r
+ u32Tmp2 = ((u32ClkDiv + 1ul) * u32DSCnt) - u32Div;\r
+ }\r
+\r
+ if(u32Tmp >= u32Tmp2)\r
+ {\r
+ u32ClkDiv = u32ClkDiv + 1ul;\r
+ }\r
+ else u32Tmp2 = u32Tmp;\r
+\r
+ if(u32Tmp2 < u32Min)\r
+ {\r
+ u32Min = u32Tmp2;\r
+ u32MinDSCnt = u32DSCnt;\r
+ u32MinClkDiv = u32ClkDiv;\r
+\r
+ /* Break when get good results */\r
+ if(u32Min == 0ul)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+ /* Set USCI_UART baud rate */\r
+ uuart->BRGEN = ((u32MinClkDiv - 1ul) << UUART_BRGEN_CLKDIV_Pos) |\r
+ ((u32MinDSCnt - 1ul) << UUART_BRGEN_DSCNT_Pos) |\r
+ ((u32PDSCnt - 1ul) << UUART_BRGEN_PDSCNT_Pos);\r
+ }\r
+ else\r
+ {\r
+ u32PDSCnt = ((uuart->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1ul;\r
+ u32MinDSCnt = ((uuart->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1ul;\r
+ u32MinClkDiv = ((uuart->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1ul;\r
+ }\r
+\r
+ /* Set USCI_UART line configuration */\r
+ uuart->LINECTL = (uuart->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32data_width;\r
+ uuart->PROTCTL = (uuart->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk |\r
+ UUART_PROTCTL_PARITYEN_Msk)) | u32parity;\r
+ uuart->PROTCTL = (uuart->PROTCTL & ~UUART_PROTCTL_STOPB_Msk) | u32stop_bits;\r
+\r
+ return (u32PCLKFreq / u32PDSCnt / u32MinDSCnt / u32MinClkDiv);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Write USCI_UART data\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ * @param[in] pu8TxBuf The buffer to send the data to USCI transmission buffer.\r
+ * @param[out] u32WriteBytes The byte number of data.\r
+ *\r
+ * @return Transfer byte count\r
+ *\r
+ * @details The function is to write data into TX buffer to transmit data by USCI_UART.\r
+ */\r
+uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)\r
+{\r
+ uint32_t u32Count, u32delayno;\r
+\r
+ for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)\r
+ {\r
+ u32delayno = 0ul;\r
+ while((uuart->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0ul) /* Wait Tx empty */\r
+ {\r
+ u32delayno++;\r
+ if(u32delayno >= 0x40000000ul)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(u32delayno >= 0x40000000ul)\r
+ {\r
+ break;\r
+ }\r
+\r
+ uuart->TXDAT = (uint8_t)pu8TxBuf[u32Count]; /* Send USCI_UART Data to buffer */\r
+ }\r
+\r
+ return u32Count;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enable USCI_UART Wake-up Function\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ * @param[in] u32WakeupMode The wakeup mode of USCI_UART module.\r
+* - \ref UUART_PROTCTL_DATWKEN_Msk : Data wake-up Mode\r
+* - \ref UUART_PROTCTL_CTSWKEN_Msk : nCTS wake-up Mode\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to enable Wake-up function of USCI_UART.\r
+ */\r
+void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode)\r
+{\r
+ uuart->PROTCTL |= u32WakeupMode;\r
+ uuart->WKCTL |= UUART_WKCTL_WKEN_Msk;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable USCI_UART Wake-up Function\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to disable Wake-up function of USCI_UART.\r
+ */\r
+void UUART_DisableWakeup(UUART_T* uuart)\r
+{\r
+ uuart->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk | UUART_PROTCTL_CTSWKEN_Msk);\r
+ uuart->WKCTL &= ~UUART_WKCTL_WKEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Enable USCI_UART auto flow control\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to enable USCI_UART auto flow control.\r
+ */\r
+void UUART_EnableFlowCtrl(UUART_T* uuart)\r
+{\r
+ /* Set RTS signal is low level active */\r
+ uuart->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk;\r
+\r
+ /* Set CTS signal is low level active */\r
+ uuart->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk;\r
+\r
+ /* Enable CTS and RTS auto flow control function */\r
+ uuart->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk | UUART_PROTCTL_CTSAUTOEN_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Disable USCI_UART auto flow control\r
+ *\r
+ * @param[in] uuart The pointer of the specified USCI_UART module.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details The function is used to disable USCI_UART auto flow control.\r
+ */\r
+void UUART_DisableFlowCtrl(UUART_T* uuart)\r
+{\r
+ /* Disable CTS and RTS auto flow control function */\r
+ uuart->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk | UUART_PROTCTL_CTSAUTOEN_Msk);\r
+}\r
+\r
+\r
+\r
+\r
+/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group USCI_UART_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file wdt.c\r
+ * @version V3.00\r
+ * @brief Watchdog Timer(WDT) driver source file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup WDT_Driver WDT Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Initialize WDT and start counting\r
+ *\r
+ * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are:\r
+ * - \ref WDT_TIMEOUT_2POW4\r
+ * - \ref WDT_TIMEOUT_2POW6\r
+ * - \ref WDT_TIMEOUT_2POW8\r
+ * - \ref WDT_TIMEOUT_2POW10\r
+ * - \ref WDT_TIMEOUT_2POW12\r
+ * - \ref WDT_TIMEOUT_2POW14\r
+ * - \ref WDT_TIMEOUT_2POW16\r
+ * - \ref WDT_TIMEOUT_2POW18\r
+ * @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are:\r
+ * - \ref WDT_RESET_DELAY_1026CLK\r
+ * - \ref WDT_RESET_DELAY_130CLK\r
+ * - \ref WDT_RESET_DELAY_18CLK\r
+ * - \ref WDT_RESET_DELAY_3CLK\r
+ * @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE.\r
+ * @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n\r
+ * enable or disable WDT time-out reset system or wake-up system.\r
+ * @note Please make sure that Register Write-Protection Function has been disabled before using this function.\r
+ */\r
+void WDT_Open(uint32_t u32TimeoutInterval,\r
+ uint32_t u32ResetDelay,\r
+ uint32_t u32EnableReset,\r
+ uint32_t u32EnableWakeup)\r
+{\r
+ WDT->ALTCTL = u32ResetDelay;\r
+\r
+ WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk |\r
+ (u32EnableReset << WDT_CTL_RSTEN_Pos) |\r
+ (u32EnableWakeup << WDT_CTL_WKEN_Pos);\r
+}\r
+\r
+/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group WDT_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file wwdt.c\r
+ * @version V3.00\r
+ * @brief Window Watchdog Timer(WWDT) driver source file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup WWDT_Driver WWDT Driver\r
+ @{\r
+*/\r
+\r
+/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions\r
+ @{\r
+*/\r
+\r
+/**\r
+ * @brief Open WWDT and start counting\r
+ *\r
+ * @param[in] u32PreScale Pre-scale setting of WWDT counter. Valid values are:\r
+ * - \ref WWDT_PRESCALER_1\r
+ * - \ref WWDT_PRESCALER_2\r
+ * - \ref WWDT_PRESCALER_4\r
+ * - \ref WWDT_PRESCALER_8\r
+ * - \ref WWDT_PRESCALER_16\r
+ * - \ref WWDT_PRESCALER_32\r
+ * - \ref WWDT_PRESCALER_64\r
+ * - \ref WWDT_PRESCALER_128\r
+ * - \ref WWDT_PRESCALER_192\r
+ * - \ref WWDT_PRESCALER_256\r
+ * - \ref WWDT_PRESCALER_384\r
+ * - \ref WWDT_PRESCALER_512\r
+ * - \ref WWDT_PRESCALER_768\r
+ * - \ref WWDT_PRESCALER_1024\r
+ * - \ref WWDT_PRESCALER_1536\r
+ * - \ref WWDT_PRESCALER_2048\r
+ * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F.\r
+ * @param[in] u32EnableInt Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE.\r
+ *\r
+ * @return None\r
+ *\r
+ * @details This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value.\r
+ * @note Application can call this function only once after boot up.\r
+ */\r
+void WWDT_Open(uint32_t u32PreScale,\r
+ uint32_t u32CmpValue,\r
+ uint32_t u32EnableInt)\r
+{\r
+ WWDT->CTL = u32PreScale |\r
+ (u32CmpValue << WWDT_CTL_CMPDAT_Pos) |\r
+ ((u32EnableInt == (uint32_t)TRUE) ? WWDT_CTL_INTEN_Msk : 0UL) |\r
+ WWDT_CTL_WWDTEN_Msk;\r
+}\r
+\r
+/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group WWDT_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r
+\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/******************************************************************************\r
+ See http://www.freertos.org/a00110.html for an explanation of the\r
+ definitions contained in this file.\r
+******************************************************************************/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ * http://www.freertos.org/a00110.html\r
+ *----------------------------------------------------------*/\r
+\r
+extern uint32_t SystemCoreClock;\r
+\r
+/* Cortex M33 port configuration. */\r
+#define configENABLE_MPU 1\r
+#define configENABLE_FPU 0\r
+#define configENABLE_TRUSTZONE 1\r
+\r
+/* Constants related to the behaviour or the scheduler. */\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_TIME_SLICING 1\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */\r
+\r
+/* Constants that describe the hardware and memory usage. */\r
+#define configCPU_CLOCK_HZ SystemCoreClock\r
+#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 )\r
+#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) )\r
+\r
+/* Constants that build features in or out. */\r
+#define configUSE_MUTEXES 1\r
+#define configUSE_TICKLESS_IDLE 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_NEWLIB_REENTRANT 0\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_QUEUE_SETS 0\r
+#define configUSE_TASK_NOTIFICATIONS 1\r
+#define configUSE_TRACE_FACILITY 1\r
+\r
+/* Constants that define which hook (callback) functions should be used. */\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+\r
+/* Constants provided for debugging and optimisation assistance. */\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 3 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+ * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is\r
+ * only necessary if the linker does not automatically remove functions that are\r
+ * not referenced anyway. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 0\r
+#define INCLUDE_xTaskGetIdleTaskHandle 0\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xTaskResumeFromISR 0\r
+#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
+#define INCLUDE_xTaskGetSchedulerState 0\r
+#define INCLUDE_xSemaphoreGetMutexHolder 0\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+\r
+/* This demo makes use of one or more example stats formatting functions. These\r
+ * format the raw data provided by the uxTaskGetSystemState() function in to\r
+ * human readable ASCII form. See the notes in the implementation of vTaskList()\r
+ * within FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
+\r
+/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter.\r
+ * See the FreeRTOS+CLI documentation for more information:\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */\r
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048\r
+\r
+/* Interrupt priority configuration follows...................... */\r
+\r
+/* Use the system definition, if there is one. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 3 /* 8 priority levels. */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+ * function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+ * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT\r
+ * CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A\r
+ * HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+ * to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )\r
+\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+ * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )\r
+\r
+/* The #ifdef guards against the file being included from IAR assembly files. */\r
+#ifndef __IASMARM__\r
+\r
+ /* Constants related to the generation of run time stats. */\r
+ #define configGENERATE_RUN_TIME_STATS 0\r
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
+ #define portGET_RUN_TIME_COUNTER_VALUE() 0\r
+ #define configTICK_RATE_HZ ( ( TickType_t ) 100 )\r
+\r
+#endif /* __IASMARM__ */\r
+\r
+/* Enable static allocation. */\r
+#define configSUPPORT_STATIC_ALLOCATION 1\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+ <project>
+ <path>$WS_DIR$\Secure\FreeRTOSDemo_s.ewp</path>
+ </project>
+ <project>
+ <path>$WS_DIR$\Nonsecure\FreeRTOSDemo_ns.ewp</path>
+ </project>
+
+
+ <batchBuild>
+ <batchDefinition>
+ <name>all</name>
+ <member>
+ <project>FreeRTOSDemo_s</project>
+ <configuration>Release</configuration>
+ </member>
+ <member>
+ <project>FreeRTOSDemo_ns</project>
+ <configuration>Release</configuration>
+ </member>
+ </batchDefinition>
+ </batchBuild>
+</workspace>
+
+
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+ <fileVersion>3</fileVersion>
+ <configuration>
+ <name>Release</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>0</debug>
+ <settings>
+ <name>C-SPY</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>30</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCVariant</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>MemOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MemFile</name>
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\Nuvoton\iom2351ae.ddf</state>
+ </option>
+ <option>
+ <name>RunToEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RunToName</name>
+ <state>main</state>
+ </option>
+ <option>
+ <name>CExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDDFArgumentProducer</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCDownloadSuppressDownload</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDownloadVerifyAll</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCProductVersion</name>
+ <state>7.80.2.11970</state>
+ </option>
+ <option>
+ <name>OCDynDriverList</name>
+ <state>THIRDPARTY_ID</state>
+ </option>
+ <option>
+ <name>OCLastSavedByProductVersion</name>
+ <state>8.30.1.17146</state>
+ </option>
+ <option>
+ <name>UseFlashLoader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CLowLevel</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCBE8Slave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacFile2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CDevice</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>FlashLoadersV3</name>
+ <state>$TOOLKIT_DIR$\config\flashloader\Nuvoton\M2351_APROM.board</state>
+ </option>
+ <option>
+ <name>OCImagesSuppressCheck1</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCImagesPath1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCImagesSuppressCheck2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCImagesPath2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCImagesSuppressCheck3</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCImagesPath3</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OverrideDefFlashBoard</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCImagesOffset1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCImagesOffset2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCImagesOffset3</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCImagesUse1</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCImagesUse2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCImagesUse3</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDeviceConfigMacroFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDebuggerExtraOption</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCAllMTBOptions</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCMulticoreNrOfCores</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCMulticoreMaster</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCMulticorePort</name>
+ <state>53461</state>
+ </option>
+ <option>
+ <name>OCMulticoreWorkspace</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCMulticoreSlaveProject</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCMulticoreSlaveConfiguration</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCDownloadExtraImage</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCAttachSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MassEraseBeforeFlashing</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCMulticoreNrOfCoresSlave</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ARMSIM_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCSimDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCSimEnablePSP</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCSimPspOverrideConfig</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCSimPspConfigFile</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CADI_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CCadiMemory</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Fast Model</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCADILogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCADILogFileEditB</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CMSISDAP_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>4</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCIarProbeScriptFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CMSISDAPResetList</name>
+ <version>1</version>
+ <state>10</state>
+ </option>
+ <option>
+ <name>CMSISDAPHWResetDuration</name>
+ <state>300</state>
+ </option>
+ <option>
+ <name>CMSISDAPHWResetDelay</name>
+ <state>200</state>
+ </option>
+ <option>
+ <name>CMSISDAPDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPLogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CMSISDAPInterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPInterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPMultiTargetEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPJtagSpeedList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPBreakpointRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPRestoreBreakpointsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPUpdateBreakpointsEdit</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>RDICatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RDICatchUndef</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RDICatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RDICatchData</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RDICatchPrefetch</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RDICatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RDICatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CatchMMERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchNOCPERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchCHKERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchSTATERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchBUSERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchINTERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchSFERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchHARDERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPMultiCPUEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPMultiCPUNumber</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCProbeCfgOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCProbeConfig</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CMSISDAPProbeConfigRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPSelectedCPUBehaviour</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ICpuName</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCJetEmuParams</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCCMSISDAPUsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCCMSISDAPUsbSerialNoSelect</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>GDBSERVER_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>TCPIP</name>
+ <state>aaa.bbb.ccc.ddd</state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCJTagBreakpointRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJTagDoUpdateBreakpoints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJTagUpdateBreakpoints</name>
+ <state>_call_main</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>IJET_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCIarProbeScriptFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IjetResetList</name>
+ <version>1</version>
+ <state>10</state>
+ </option>
+ <option>
+ <name>IjetHWResetDuration</name>
+ <state>300</state>
+ </option>
+ <option>
+ <name>IjetHWResetDelay</name>
+ <state>200</state>
+ </option>
+ <option>
+ <name>IjetPowerFromProbe</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IjetPowerRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetLogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>IjetInterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetInterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetMultiTargetEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetScanChainNonARMDevices</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetIRLength</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetJtagSpeedList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetProtocolRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetSwoPin</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetCpuClockEdit</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IjetSwoPrescalerList</name>
+ <version>1</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetBreakpointRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetRestoreBreakpointsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetUpdateBreakpointsEdit</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>RDICatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RDICatchUndef</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RDICatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RDICatchData</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RDICatchPrefetch</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RDICatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RDICatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CatchMMERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchNOCPERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchCHKERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchSTATERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchBUSERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchINTERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchSFERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchHARDERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCProbeCfgOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCProbeConfig</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IjetProbeConfigRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetMultiCPUEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetMultiCPUNumber</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetSelectedCPUBehaviour</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ICpuName</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCJetEmuParams</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IjetPreferETB</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IjetTraceSettingsList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetTraceSizeList</name>
+ <version>0</version>
+ <state>4</state>
+ </option>
+ <option>
+ <name>FlashBoardPathSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIjetUsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCIjetUsbSerialNoSelect</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>JLINK_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>16</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>JLinkSpeed</name>
+ <state>1000</state>
+ </option>
+ <option>
+ <name>CCJLinkDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkLogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCJLinkHWResetDelay</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>JLinkInitialSpeed</name>
+ <state>1000</state>
+ </option>
+ <option>
+ <name>CCDoJlinkMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCScanChainNonARMDevices</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkIRLength</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkCommRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkTCPIP</name>
+ <state>aaa.bbb.ccc.ddd</state>
+ </option>
+ <option>
+ <name>CCJLinkSpeedRadioV2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCUSBDevice</name>
+ <version>1</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRDICatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchUndef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchData</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchPrefetch</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkBreakpointRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkDoUpdateBreakpoints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkUpdateBreakpoints</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>CCJLinkInterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkResetList</name>
+ <version>6</version>
+ <state>5</state>
+ </option>
+ <option>
+ <name>CCJLinkInterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchMMERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchNOCPERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchCHRERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchSTATERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchBUSERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchINTERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchSFERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchHARDERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCJLinkScriptFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCJLinkUsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCTcpIpAlt</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkTcpIpSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCCpuClockEdit</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCSwoClockAuto</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSwoClockEdit</name>
+ <state>2000</state>
+ </option>
+ <option>
+ <name>OCJLinkTraceSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCJLinkTraceSourceDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCJLinkDeviceName</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>LMIFTDI_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>2</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>LmiftdiSpeed</name>
+ <state>500</state>
+ </option>
+ <option>
+ <name>CCLmiftdiDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCLmiftdiLogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCLmiFtdiInterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCLmiFtdiInterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>NULINK_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>PEMICRO_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>3</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCJPEMicroShowSettings</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>STLINK_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>5</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCSTLinkInterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkInterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkResetList</name>
+ <version>3</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCpuClockEdit</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCSwoClockAuto</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSwoClockEdit</name>
+ <state>2000</state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCSTLinkDoUpdateBreakpoints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkUpdateBreakpoints</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchMMERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchNOCPERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchCHRERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchSTATERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchBUSERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchINTERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchSFERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchHARDERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkUsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCSTLinkUsbSerialNoSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkJtagSpeedList</name>
+ <version>1</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkDAPNumber</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCSTLinkDebugAccessPortRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkUseServerSelect</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>THIRDPARTY_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CThirdPartyDriverDll</name>
+ <state>$TOOLKIT_DIR$\..\..\..\Nuvoton Tools\Nu-Link_IAR\Nu-Link_IAR.dll</state>
+ </option>
+ <option>
+ <name>CThirdPartyLogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CThirdPartyLogFileEditB</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>TIFET_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCMSPFetResetList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetInterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetInterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetTargetVccTypeDefault</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetTargetVoltage</name>
+ <state>###Uninitialized###</state>
+ </option>
+ <option>
+ <name>CCMSPFetVCCDefault</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCMSPFetTargetSettlingtime</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetRadioJtagSpeedType</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCMSPFetConnection</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetUsbComPort</name>
+ <state>Automatic</state>
+ </option>
+ <option>
+ <name>CCMSPFetAllowAccessToBSL</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetLogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCMSPFetRadioEraseFlash</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>XDS100_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>TIPackageOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>TIPackage</name>
+ <state></state>
+ </option>
+ <option>
+ <name>BoardFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCXds100BreakpointRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100DoUpdateBreakpoints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100UpdateBreakpoints</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>CCXds100CatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchUndef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchData</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchPrefetch</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchMMERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchNOCPERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchCHRERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchSTATERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchBUSERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchINTERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchSFERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchHARDERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CpuClockEdit</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCXds100SwoClockAuto</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100SwoClockEdit</name>
+ <state>1000</state>
+ </option>
+ <option>
+ <name>CCXds100HWResetDelay</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100ResetList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100UsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCXds100UsbSerialNoSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100JtagSpeedList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100InterfaceRadio</name>
+ <state>2</state>
+ </option>
+ <option>
+ <name>CCXds100InterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100ProbeList</name>
+ <version>0</version>
+ <state>2</state>
+ </option>
+ <option>
+ <name>CCXds100SWOPortRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100SWOPort</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCXDSTargetVccEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXDSTargetVoltage</name>
+ <state>###Uninitialized###</state>
+ </option>
+ <option>
+ <name>OCXDSDigitalStatesConfigFile</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <debuggerPlugins>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+ <loadFlag>1</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ </debuggerPlugins>
+ </configuration>
+</project>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<project>\r
+ <fileVersion>3</fileVersion>\r
+ <configuration>\r
+ <name>Release</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>0</debug>\r
+ <settings>\r
+ <name>General</name>\r
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+ <state>$PROJ_DIR$\..\Config</state>\r
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+ <prebuild></prebuild>\r
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+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsWarn</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsErr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkWarningsAreErrors</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkUseExtraOptions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLowLevelInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAutoLibEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAdditionalLibs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOverrideProgramEntryLabel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabel</name>\r
+ <state>Reset_Handler</state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerStart</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerEnd</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcSize</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcPoly</name>\r
+ <state>0x11021</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcCompl</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcBitOrder</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcInitialValue</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoCrc</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkBufferedTerminalOutput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStdoutInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcFullSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIElfToolPostProcess</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogAutoLibSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogRedirSymbols</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogUnusedFragments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcUseAsInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptInline</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsAllow</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsForce</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackAnalysisEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackControlFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackCallGraphFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlgorithm</name>\r
+ <version>1</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcUnitSize</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkThreadsSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogCallGraph</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfFile_AltDefault</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkEncInput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkEncOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkEncOutputBom</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkHeapSelect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLocaleSelect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTrustzoneImportLibraryOut</name>\r
+ <state>FreeRTOSDemo_ns_importlib.o</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARCHIVE</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>IarchiveInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data />\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>Config</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Config\FreeRTOSConfig.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Demos</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\Common\ARMv8M\mpu_demo\mpu_demo.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\Common\ARMv8M\mpu_demo\mpu_demo.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\Common\ARMv8M\tz_demo\tz_demo.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\Common\ARMv8M\tz_demo\tz_demo.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Device</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Nuvoton_Code\Device\Nuvoton\M2351\Source\IAR\startup_M2351.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Nuvoton_Code\Device\Nuvoton\M2351\Source\system_M2351.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Drivers</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Secure\Objects\FreeRTOSDemo_s_importlib.o</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Nuvoton_Code\StdDriver\src\gpio.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Nuvoton_Code\StdDriver\src\retarget.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>FreeRTOS</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\event_groups.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\MemMang\heap_4.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\Common\mpu_wrappers.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\non_secure\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\non_secure\portasm.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\non_secure\portasm.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\non_secure\portmacro.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\stream_buffer.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\tasks.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\timers.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>User</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\fault_handler.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main_ns.c</name>\r
+ </file>\r
+ </group>\r
+</project>\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v2_1.xml" */
+
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x10040000;
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10040000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x1007FFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x30008000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x30017FFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_proc_s_stack__ = 0x0;
+define symbol __ICFEDIT_size_main_ns_stack__ = 0x0;
+define symbol __ICFEDIT_size_proc_ns_stack__ = 0x0;
+define symbol __ICFEDIT_size_heap__ = 0x0;
+
+/**** End of ICF editor section. ###ICF###*/
+
+/* Flash Organization
+ * 1. Privileged Code:
+ * Start : 0x10040000
+ * End : 0x10046FFF
+ * Size : 28 Kbytes
+ * 2. System calls:
+ * Start : 0x10047000
+ * End : 0x10047FFF
+ * Size : 4 Kbytes
+ * 3. Unprivileged Code:
+ * Start : 0x10048000
+ * End : 0x1007FFFF
+ * Size : 224 Kbytes
+ */
+define symbol __region_ROM_Privileged_start__ = 0x10040000;
+define symbol __region_ROM_Privileged_end__ = 0x10046FFF;
+define symbol __region_ROM_SystemCalls_start__ = 0x10047000;
+define symbol __region_ROM_SystemCalls_end__ = 0x10047FFF;
+define symbol __region_ROM_Unprivileged_start__ = 0x10048000;
+define symbol __region_ROM_Unprivileged_end__ = 0x1007FFFF;
+
+/* RAM Organization
+ * 1. Privileged Data:
+ * Start : 0x30008000
+ * End : 0x30008FFF
+ * Size : 4 Kbytes
+ * 2. Unprivileged Data:
+ * Start : 0x30009000
+ * End : 0x30017FFF
+ * Size : 60 Kbytes
+ */
+define symbol __region_RAM_Privileged_start__ = 0x30008000;
+define symbol __region_RAM_Privileged_end__ = 0x30008FFF;
+define symbol __region_RAM_Unprivileged_start__ = 0x30009000;
+define symbol __region_RAM_Unprivileged_end__ = 0x30017FFF;
+
+/* Memory Regions. */
+define memory mem with size = 4G;
+define region ROM_Privileged_region = mem:[from __region_ROM_Privileged_start__ to __region_ROM_Privileged_end__];
+define region ROM_SystemCalls_region = mem:[from __region_ROM_SystemCalls_start__ to __region_ROM_SystemCalls_end__];
+define region ROM_Unprivileged_region = mem:[from __region_ROM_Unprivileged_start__ to __region_ROM_Unprivileged_end__];
+define region RAM_Privileged_region = mem:[from __region_RAM_Privileged_start__ to __region_RAM_Privileged_end__];
+define region RAM_Unprivileged_region = mem:[from __region_RAM_Unprivileged_start__ to __region_RAM_Unprivileged_end__];
+
+/* Stack and Heap. */
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block PROC_STACK_S with alignment = 8, size = __ICFEDIT_size_proc_s_stack__ { };
+define block MAIN_STACK_NS with alignment = 8, size = __ICFEDIT_size_main_ns_stack__ { };
+define block PROC_STACK_NS with alignment = 8, size = __ICFEDIT_size_proc_ns_stack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+/* Initialization. */
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+if( isdefinedsymbol(__USE_DLIB_PERTHREAD) )
+{
+ /* Required in a multi-threaded application. */
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+/* Exported symbols. */
+define exported symbol __privileged_functions_start__ = __region_ROM_Privileged_start__;
+define exported symbol __privileged_functions_end__ = __region_ROM_Privileged_end__;
+define exported symbol __syscalls_flash_start__ = __region_ROM_SystemCalls_start__;
+define exported symbol __syscalls_flash_end__ = __region_ROM_SystemCalls_end__;
+define exported symbol __unprivileged_flash_start__ = __region_ROM_Unprivileged_start__;
+define exported symbol __unprivileged_flash_end__ = __region_ROM_Unprivileged_end__;
+define exported symbol __privileged_sram_start__ = __region_RAM_Privileged_start__;
+define exported symbol __privileged_sram_end__ = __region_RAM_Privileged_end__;
+
+/* Placements. */
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_Privileged_region { readonly section privileged_functions };
+place in ROM_SystemCalls_region { readonly section freertos_system_calls };
+place in ROM_Unprivileged_region { readonly };
+
+place in RAM_Privileged_region { readwrite section privileged_data };
+place in RAM_Unprivileged_region { readwrite,
+ block CSTACK, block PROC_STACK_S, block MAIN_STACK_NS, block PROC_STACK_NS, block HEAP };
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ EXTERN vHandleMemoryFault\r
+ PUBLIC HardFault_Handler\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+HardFault_Handler:\r
+ movs r0, #4\r
+ mov r1, lr\r
+ tst r0, r1\r
+ beq stacking_used_msp\r
+ mrs r0, psp\r
+ b vHandleMemoryFault\r
+ stacking_used_msp:\r
+ mrs r0, msp\r
+ b vHandleMemoryFault\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Device includes. */\r
+#include <arm_cmse.h>\r
+#include "NuMicro.h"\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "tz_demo.h"\r
+#include "mpu_demo.h"\r
+\r
+/**\r
+ * @brief Create all demo tasks.\r
+ */\r
+static void prvCreateTasks( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCreateTasks( void )\r
+{\r
+ /* Create tasks for the MPU Demo. */\r
+ vStartMPUDemo();\r
+\r
+ /* Create tasks for the TZ Demo. */\r
+ vStartTZDemo();\r
+\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Stack overflow hook. */\r
+void vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName )\r
+{\r
+ /* Force an assert. */\r
+ configASSERT( pcTaskName == 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Non-Secure main. */\r
+int main( void )\r
+{\r
+ /* Initialize debug port. */\r
+ DEBUG_PORT->BAUD = UART_BAUD_MODE2 | UART_BAUD_MODE2_DIVIDER( __HIRC, 115200 );\r
+ DEBUG_PORT->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;\r
+\r
+ /* Print banner. */\r
+ printf( "\n" );\r
+ printf( "+---------------------------------------------+\n" );\r
+ printf( "| Nonsecure is running ... |\n" );\r
+ printf( "+---------------------------------------------+\n" );\r
+\r
+ /* Create tasks. */\r
+ prvCreateTasks();\r
+\r
+ /* Start scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not reach here as the schedular is already started. */\r
+ for( ; ; )\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an\r
+ * implementation of vApplicationGetIdleTaskMemory() to provide the memory that\r
+ * is used by the Idle task. */\r
+void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,\r
+ StackType_t ** ppxIdleTaskStackBuffer,\r
+ uint32_t * pulIdleTaskStackSize )\r
+{\r
+ /* If the buffers to be provided to the Idle task are declared inside this\r
+ * function then they must be declared static - otherwise they will be\r
+ * allocated on the stack and so not exists after this function exits. */\r
+ static StaticTask_t xIdleTaskTCB;\r
+ static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle\r
+ * task's state will be stored. */\r
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Idle task's stack. */\r
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
+ * Note that, as the array is necessarily of type StackType_t,\r
+ * configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the\r
+ * application must provide an implementation of vApplicationGetTimerTaskMemory()\r
+ * to provide the memory that is used by the Timer service task. */\r
+void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,\r
+ StackType_t ** ppxTimerTaskStackBuffer,\r
+ uint32_t * pulTimerTaskStackSize )\r
+{\r
+ /* If the buffers to be provided to the Timer task are declared inside this\r
+ * function then they must be declared static - otherwise they will be\r
+ * allocated on the stack and so not exists after this function exits. */\r
+ static StaticTask_t xTimerTaskTCB;\r
+ static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__( ( aligned( 32 ) ) );\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
+ * task's state will be stored. */\r
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Timer task's stack. */\r
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
+ * Note that, as the array is necessarily of type StackType_t,\r
+ * configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */\r
+ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+ <fileVersion>3</fileVersion>
+ <configuration>
+ <name>Release</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>0</debug>
+ <settings>
+ <name>C-SPY</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>30</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCVariant</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>MemOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MemFile</name>
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\Nuvoton\iom2351ae.ddf</state>
+ </option>
+ <option>
+ <name>RunToEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RunToName</name>
+ <state>main</state>
+ </option>
+ <option>
+ <name>CExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDDFArgumentProducer</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCDownloadSuppressDownload</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDownloadVerifyAll</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCProductVersion</name>
+ <state>7.80.2.11970</state>
+ </option>
+ <option>
+ <name>OCDynDriverList</name>
+ <state>THIRDPARTY_ID</state>
+ </option>
+ <option>
+ <name>OCLastSavedByProductVersion</name>
+ <state>8.30.1.17146</state>
+ </option>
+ <option>
+ <name>UseFlashLoader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CLowLevel</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCBE8Slave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacFile2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CDevice</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>FlashLoadersV3</name>
+ <state>$TOOLKIT_DIR$\config\flashloader\Nuvoton\M2351_APROM.board</state>
+ </option>
+ <option>
+ <name>OCImagesSuppressCheck1</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCImagesPath1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCImagesSuppressCheck2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCImagesPath2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCImagesSuppressCheck3</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCImagesPath3</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OverrideDefFlashBoard</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCImagesOffset1</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCImagesOffset2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCImagesOffset3</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCImagesUse1</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCImagesUse2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCImagesUse3</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDeviceConfigMacroFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDebuggerExtraOption</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCAllMTBOptions</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCMulticoreNrOfCores</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCMulticoreMaster</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCMulticorePort</name>
+ <state>53461</state>
+ </option>
+ <option>
+ <name>OCMulticoreWorkspace</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCMulticoreSlaveProject</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCMulticoreSlaveConfiguration</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCDownloadExtraImage</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCAttachSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MassEraseBeforeFlashing</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCMulticoreNrOfCoresSlave</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ARMSIM_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCSimDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCSimEnablePSP</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCSimPspOverrideConfig</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCSimPspConfigFile</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CADI_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CCadiMemory</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Fast Model</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCADILogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCADILogFileEditB</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CMSISDAP_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>4</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCIarProbeScriptFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CMSISDAPResetList</name>
+ <version>1</version>
+ <state>10</state>
+ </option>
+ <option>
+ <name>CMSISDAPHWResetDuration</name>
+ <state>300</state>
+ </option>
+ <option>
+ <name>CMSISDAPHWResetDelay</name>
+ <state>200</state>
+ </option>
+ <option>
+ <name>CMSISDAPDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPLogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CMSISDAPInterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPInterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPMultiTargetEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPJtagSpeedList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPBreakpointRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPRestoreBreakpointsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPUpdateBreakpointsEdit</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>RDICatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RDICatchUndef</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RDICatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RDICatchData</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RDICatchPrefetch</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RDICatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RDICatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CatchMMERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchNOCPERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchCHKERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchSTATERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchBUSERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchINTERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchSFERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchHARDERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPMultiCPUEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPMultiCPUNumber</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCProbeCfgOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCProbeConfig</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CMSISDAPProbeConfigRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CMSISDAPSelectedCPUBehaviour</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ICpuName</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCJetEmuParams</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCCMSISDAPUsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCCMSISDAPUsbSerialNoSelect</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>GDBSERVER_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>TCPIP</name>
+ <state>aaa.bbb.ccc.ddd</state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCJTagBreakpointRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJTagDoUpdateBreakpoints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJTagUpdateBreakpoints</name>
+ <state>_call_main</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>IJET_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCIarProbeScriptFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IjetResetList</name>
+ <version>1</version>
+ <state>10</state>
+ </option>
+ <option>
+ <name>IjetHWResetDuration</name>
+ <state>300</state>
+ </option>
+ <option>
+ <name>IjetHWResetDelay</name>
+ <state>200</state>
+ </option>
+ <option>
+ <name>IjetPowerFromProbe</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IjetPowerRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetLogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>IjetInterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetInterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetMultiTargetEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetScanChainNonARMDevices</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetIRLength</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetJtagSpeedList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetProtocolRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetSwoPin</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetCpuClockEdit</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IjetSwoPrescalerList</name>
+ <version>1</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetBreakpointRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetRestoreBreakpointsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetUpdateBreakpointsEdit</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>RDICatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RDICatchUndef</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RDICatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RDICatchData</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RDICatchPrefetch</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RDICatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RDICatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CatchMMERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchNOCPERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchCHKERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchSTATERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchBUSERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchINTERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchSFERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchHARDERR</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCProbeCfgOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCProbeConfig</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IjetProbeConfigRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetMultiCPUEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetMultiCPUNumber</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetSelectedCPUBehaviour</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ICpuName</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCJetEmuParams</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IjetPreferETB</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IjetTraceSettingsList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IjetTraceSizeList</name>
+ <version>0</version>
+ <state>4</state>
+ </option>
+ <option>
+ <name>FlashBoardPathSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIjetUsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCIjetUsbSerialNoSelect</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>JLINK_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>16</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>JLinkSpeed</name>
+ <state>1000</state>
+ </option>
+ <option>
+ <name>CCJLinkDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkLogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCJLinkHWResetDelay</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>JLinkInitialSpeed</name>
+ <state>1000</state>
+ </option>
+ <option>
+ <name>CCDoJlinkMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCScanChainNonARMDevices</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkIRLength</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkCommRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkTCPIP</name>
+ <state>aaa.bbb.ccc.ddd</state>
+ </option>
+ <option>
+ <name>CCJLinkSpeedRadioV2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCUSBDevice</name>
+ <version>1</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRDICatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchUndef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchData</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchPrefetch</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkBreakpointRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkDoUpdateBreakpoints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkUpdateBreakpoints</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>CCJLinkInterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkResetList</name>
+ <version>6</version>
+ <state>5</state>
+ </option>
+ <option>
+ <name>CCJLinkInterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchMMERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchNOCPERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchCHRERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchSTATERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchBUSERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchINTERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchSFERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchHARDERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCJLinkScriptFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCJLinkUsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCTcpIpAlt</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkTcpIpSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCCpuClockEdit</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCSwoClockAuto</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSwoClockEdit</name>
+ <state>2000</state>
+ </option>
+ <option>
+ <name>OCJLinkTraceSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCJLinkTraceSourceDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCJLinkDeviceName</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>LMIFTDI_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>2</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>LmiftdiSpeed</name>
+ <state>500</state>
+ </option>
+ <option>
+ <name>CCLmiftdiDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCLmiftdiLogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCLmiFtdiInterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCLmiFtdiInterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>NULINK_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>PEMICRO_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>3</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCJPEMicroShowSettings</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>STLINK_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>5</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCSTLinkInterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkInterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkResetList</name>
+ <version>3</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCpuClockEdit</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCSwoClockAuto</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSwoClockEdit</name>
+ <state>2000</state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCSTLinkDoUpdateBreakpoints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkUpdateBreakpoints</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchMMERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchNOCPERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchCHRERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchSTATERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchBUSERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchINTERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchSFERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchHARDERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkUsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCSTLinkUsbSerialNoSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkJtagSpeedList</name>
+ <version>1</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkDAPNumber</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCSTLinkDebugAccessPortRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkUseServerSelect</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>THIRDPARTY_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CThirdPartyDriverDll</name>
+ <state>$TOOLKIT_DIR$\..\..\..\Nuvoton Tools\Nu-Link_IAR\Nu-Link_IAR.dll</state>
+ </option>
+ <option>
+ <name>CThirdPartyLogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CThirdPartyLogFileEditB</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>TIFET_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCMSPFetResetList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetInterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetInterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetTargetVccTypeDefault</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetTargetVoltage</name>
+ <state>###Uninitialized###</state>
+ </option>
+ <option>
+ <name>CCMSPFetVCCDefault</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCMSPFetTargetSettlingtime</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetRadioJtagSpeedType</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCMSPFetConnection</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetUsbComPort</name>
+ <state>Automatic</state>
+ </option>
+ <option>
+ <name>CCMSPFetAllowAccessToBSL</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMSPFetLogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCMSPFetRadioEraseFlash</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>XDS100_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>TIPackageOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>TIPackage</name>
+ <state></state>
+ </option>
+ <option>
+ <name>BoardFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCXds100BreakpointRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100DoUpdateBreakpoints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100UpdateBreakpoints</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>CCXds100CatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchUndef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchData</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchPrefetch</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchMMERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchNOCPERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchCHRERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchSTATERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchBUSERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchINTERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchSFERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchHARDERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CpuClockEdit</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCXds100SwoClockAuto</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100SwoClockEdit</name>
+ <state>1000</state>
+ </option>
+ <option>
+ <name>CCXds100HWResetDelay</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100ResetList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100UsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCXds100UsbSerialNoSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100JtagSpeedList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100InterfaceRadio</name>
+ <state>2</state>
+ </option>
+ <option>
+ <name>CCXds100InterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100ProbeList</name>
+ <version>0</version>
+ <state>2</state>
+ </option>
+ <option>
+ <name>CCXds100SWOPortRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100SWOPort</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCXDSTargetVccEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXDSTargetVoltage</name>
+ <state>###Uninitialized###</state>
+ </option>
+ <option>
+ <name>OCXDSDigitalStatesConfigFile</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <debuggerPlugins>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+ <loadFlag>1</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ </debuggerPlugins>
+ </configuration>
+</project>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<project>\r
+ <fileVersion>3</fileVersion>\r
+ <configuration>\r
+ <name>Release</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>0</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>31</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Objects</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Objects</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Listings</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>Automatic choice of formatter, without multibyte support.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>Automatic choice of formatter, without multibyte support.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>7.80.2.11970</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>8.30.2.18207</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>M2351 series Nuvoton M2351 series</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLowLevelInterface</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianModeBE</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGBufferedTerminalOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>26</version>\r
+ <state>58</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibThreads</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CoreVariant</name>\r
+ <version>26</version>\r
+ <state>58</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUDeviceSlave</name>\r
+ <state>M2351 series Nuvoton M2351 series</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU2</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>NrRegs</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>NEON</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave2</name>\r
+ <version>26</version>\r
+ <state>58</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCMSISPackSelectDevice</name>\r
+ </option>\r
+ <option>\r
+ <name>OgLibHeap</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLibAdditionalLocale</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGPrintfVariant</name>\r
+ <version>0</version>\r
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+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfFile_AltDefault</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkEncInput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkEncOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkEncOutputBom</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkHeapSelect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLocaleSelect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTrustzoneImportLibraryOut</name>\r
+ <state>FreeRTOSDemo_s_importlib.o</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARCHIVE</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>IarchiveInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data />\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>Device</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\partition_M2351.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Nuvoton_Code\Device\Nuvoton\M2351\Source\IAR\startup_M2351.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Nuvoton_Code\Device\Nuvoton\M2351\Source\system_M2351.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Drivers</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Nuvoton_Code\StdDriver\src\clk.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Nuvoton_Code\StdDriver\src\gpio.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Nuvoton_Code\StdDriver\src\retarget.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>NSCFunctions</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\Common\ARMv8M\tz_demo\nsc_functions.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\Common\ARMv8M\tz_demo\nsc_functions.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>SecureContext</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\secure\secure_context.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\secure\secure_context.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\secure\secure_context_port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\secure\secure_context_port_asm.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\secure\secure_port_macros.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>SecureHeap</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\secure\secure_heap.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\secure\secure_heap.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>SecureInit</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\secure\secure_init.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM23\secure\secure_init.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>User</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\main_s.c</name>\r
+ </file>\r
+ </group>\r
+</project>\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v2_1.xml" */
+
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x0003FFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x20007FFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_proc_s_stack__ = 0x0;
+define symbol __ICFEDIT_size_main_ns_stack__ = 0x0;
+define symbol __ICFEDIT_size_proc_ns_stack__ = 0x0;
+define symbol __ICFEDIT_size_heap__ = 0x0;
+
+/**** End of ICF editor section. ###ICF###*/
+
+/* Memory Regions. */
+define memory mem with size = 4G;
+define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+ | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region EROM_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]
+ | mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__]
+ | mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__];
+define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+ | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+ | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+ | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region NSC_region = mem:[from 0x0003F000 to 0x0003FFFF];
+
+/* Stack and Heap. */
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block PROC_STACK_S with alignment = 8, size = __ICFEDIT_size_proc_s_stack__ { };
+define block MAIN_STACK_NS with alignment = 8, size = __ICFEDIT_size_main_ns_stack__ { };
+define block PROC_STACK_NS with alignment = 8, size = __ICFEDIT_size_proc_ns_stack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+/* Initialization. */
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+if( isdefinedsymbol(__USE_DLIB_PERTHREAD) )
+{
+ /* Required in a multi-threaded application. */
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+/* Placements. */
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in IROM_region { readonly };
+place in EROM_region { readonly section application_specific_ro };
+place in NSC_region { section Veneer$$CMSE };
+
+place in IRAM_region { readwrite, block CSTACK, block PROC_STACK_S, block MAIN_STACK_NS, block PROC_STACK_NS, block HEAP };
+place in ERAM_region { readwrite section application_specific_rw };
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <arm_cmse.h>\r
+#include <stdio.h>\r
+\r
+/* Device includes. */\r
+#include "NuMicro.h"\r
+#include "partition_M2351.h"\r
+\r
+/* FreeRTOS includes. */\r
+#include "secure_port_macros.h"\r
+\r
+/* Start address of non-secure application. */\r
+#define mainNONSECURE_APP_START_ADDRESS ( 0x10040000 )\r
+\r
+/* typedef for non-secure Reset Handler. */\r
+typedef __cmse_nonsecure_call void ( *NonSecureResetHandler_t )( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Sets up the hardware - clocks and UARTs.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/**\r
+ * @brief Boots into the non-secure code.\r
+ *\r
+ * @param[in] ulNonSecureStartAddress Start address of the non-secure application.\r
+ */\r
+static void prvBootNonSecure( uint32_t ulNonSecureStartAddress );\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Init System Clock. */\r
+ /* Enable PLL */\r
+ CLK->PLLCTL = CLK_PLLCTL_64MHz_HIRC;\r
+ /* Wait for PLL to be stable. */\r
+ while( ( CLK->STATUS & CLK_STATUS_PLLSTB_Msk ) == 0 );\r
+\r
+ /* Set HCLK divider to 1. */\r
+ CLK->CLKDIV0 = ( CLK->CLKDIV0 & ( ~CLK_CLKDIV0_HCLKDIV_Msk ) );\r
+\r
+ /* Switch HCLK clock source to PLL. */\r
+ CLK->CLKSEL0 = ( CLK->CLKSEL0 & ( ~CLK_CLKSEL0_HCLKSEL_Msk ) ) | CLK_CLKSEL0_HCLKSEL_PLL;\r
+\r
+ /* Initialize UART0 - It is used for debug output from the non-secure side. */\r
+ /* Enable UART0 clock. */\r
+ CLK->APBCLK0 |= CLK_APBCLK0_UART0CKEN_Msk;\r
+\r
+ /* Select UART0 clock source. */\r
+ CLK->CLKSEL1 = ( CLK->CLKSEL1 & ( ~CLK_CLKSEL1_UART0SEL_Msk ) ) | CLK_CLKSEL1_UART0SEL_HIRC;\r
+\r
+ /* Set multi-function pins for UART0 RXD and TXD. */\r
+ SYS->GPB_MFPH = ( SYS->GPB_MFPH & ( ~UART0_RXD_PB12_Msk ) ) | UART0_RXD_PB12;\r
+ SYS->GPB_MFPH = ( SYS->GPB_MFPH & ( ~UART0_TXD_PB13_Msk ) ) | UART0_TXD_PB13;\r
+\r
+ /* Initialize UART1 - It is used for debug output from the secure side. */\r
+ /* Enable UART1 clock. */\r
+ CLK->APBCLK0 |= CLK_APBCLK0_UART1CKEN_Msk;\r
+\r
+ /* Select UART1 clock source. */\r
+ CLK->CLKSEL1 = ( CLK->CLKSEL1 & ( ~CLK_CLKSEL1_UART1SEL_Msk ) ) | CLK_CLKSEL1_UART1SEL_HIRC;\r
+\r
+ /* Set multi-function pins for UART1 RXD and TXD. */\r
+ SYS->GPA_MFPL = ( SYS->GPA_MFPL & ( ~UART1_RXD_PA2_Msk ) ) | UART1_RXD_PA2;\r
+ SYS->GPA_MFPL = ( SYS->GPA_MFPL & ( ~UART1_TXD_PA3_Msk ) ) | UART1_TXD_PA3;\r
+\r
+ /* Update System Core Clock. */\r
+ PllClock = 64000000; /* PLL. */\r
+ SystemCoreClock = 64000000 / 1; /* HCLK. */\r
+ CyclesPerUs = 64000000 / 1000000; /* For SYS_SysTickDelay(). */\r
+\r
+ /* Initialize the debug port. */\r
+ DEBUG_PORT->BAUD = UART_BAUD_MODE2 | UART_BAUD_MODE2_DIVIDER(__HIRC, 115200);\r
+ DEBUG_PORT->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvBootNonSecure( uint32_t ulNonSecureStartAddress )\r
+{\r
+ NonSecureResetHandler_t pxNonSecureResetHandler;\r
+\r
+ /* Setup the non-secure vector table. */\r
+ SCB_NS->VTOR = ulNonSecureStartAddress;\r
+\r
+ /* Main Stack Pointer value for the non-secure side is the first entry in\r
+ * the non-secure vector table. Read the first entry and assign the same to\r
+ * the non-secure main stack pointer(MSP_NS). */\r
+ secureportSET_MSP_NS( *( ( uint32_t * )( ulNonSecureStartAddress ) ) );\r
+\r
+ /* Reset Handler for the non-secure side is the second entry in the\r
+ * non-secure vector table. Read the second entry to get the non-secure\r
+ * Reset Handler. */\r
+ pxNonSecureResetHandler = ( NonSecureResetHandler_t )( * ( ( uint32_t * ) ( ( ulNonSecureStartAddress ) + 4U ) ) );\r
+\r
+ /* Start non-secure state software application by jumping to the non-secure\r
+ * Reset Handler. */\r
+ pxNonSecureResetHandler();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Secure main. */\r
+int main(void)\r
+{\r
+ /* Unlock protected registers. */\r
+ SYS_UnlockReg();\r
+\r
+ /* Initialize the hardware. */\r
+ prvSetupHardware();\r
+\r
+ /* Print banner. */\r
+ printf( "\n" );\r
+ printf( "+---------------------------------------------+\n" );\r
+ printf( "| Secure is running ... |\n" );\r
+ printf( "+---------------------------------------------+\n" );\r
+\r
+ /* Do not generate Systick interrupt on secure side. */\r
+ SysTick_Config( 1 );\r
+\r
+ /* Set GPIO Port A to non-secure for controlling LEDs from the non-secure\r
+ * side . */\r
+ SCU_SET_IONSSET( SCU_IONSSET_PA_Msk );\r
+\r
+ /* Set UART0 to non-secure for debug output from non-secure side. */\r
+ SCU_SET_PNSSET( UART0_Attr );\r
+\r
+ /* Lock protected registers before booting non-secure code. */\r
+ SYS_LockReg();\r
+\r
+ /* Boot the non-secure code. */\r
+ printf( "Entering non-secure world ...\n" );\r
+ prvBootNonSecure( mainNONSECURE_APP_START_ADDRESS );\r
+\r
+ /* Non-secure software does not return, this code is not executed. */\r
+ for( ; ; )\r
+ {\r
+ /* Should not reach here. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/**************************************************************************//**
+ * @file partition_M2351.c
+ * @version V3.00
+ * @brief SAU configuration for secure/nonsecure region settings.
+ *
+ * @note
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+
+#ifndef PARTITION_M2351
+#define PARTITION_M2351
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+
+/*
+ SRAMNSSET
+*/
+/*
+// Bit 0..16
+// <o.0..16> Secure SRAM Size <0=> 0 KB
+// <0x2000=> 8KB
+// <0x4000=> 16KB
+// <0x6000=> 24KB
+// <0x8000=> 32KB
+// <0xa000=> 40KB
+// <0xc000=> 48KB
+// <0xe000=> 56KB
+// <0x10000=> 64KB
+// <0x12000=> 72KB
+// <0x14000=> 80KB
+// <0x16000=> 88KB
+// <0x18000=> 96KB
+*/
+#define SCU_SECURE_SRAM_SIZE 0x8000
+#define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE)
+
+
+
+/*--------------------------------------------------------------------------------------------------------*/
+
+/*
+ NSBA
+*/
+#define FMC_INIT_NSBA 1
+/*
+// <o>Secure Flash ROM Size <0x800-0x7FFFF:0x800>
+*/
+
+#define FMC_SECURE_ROM_SIZE 0x40000
+
+#define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE)
+
+__STATIC_INLINE void FMC_NSBA_Setup(void)
+{
+ /* Skip NSBA Setupt according config */
+ if(FMC_INIT_NSBA == 0)
+ return;
+
+ /* Check if NSBA value with current active NSBA */
+ if(SCU->FNSADDR != FMC_SECURE_ROM_SIZE)
+ {
+ /* Unlock Protected Register */
+ SYS_UnlockReg();
+
+ /* Enable ISP and config update */
+ FMC->ISPCTL = FMC_ISPCTL_ISPEN_Msk | FMC_ISPCTL_CFGUEN_Msk;
+
+ /* Config Base of NSBA */
+ FMC->ISPADDR = 0x200800;
+
+ /* Read Non-secure base address config */
+ FMC->ISPCMD = FMC_ISPCMD_READ;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+ while(FMC->ISPTRG);
+
+ /* Setting NSBA when it is empty */
+ if(FMC->ISPDAT == 0xfffffffful)
+ {
+ FMC->ISPDAT = FMC_SECURE_ROM_SIZE;
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+ while(FMC->ISPTRG);
+
+ /* Force Chip Reset to valid new setting */
+ SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
+ }
+
+ /* Fatal Error:
+ FMC NSBA setting is different to FMC_INIT_NSBA_VAL.
+ User must double confirm which one is wrong.
+
+ If user need to change NSBA config of FMC, user must do Mess-erase by
+ ISP or ICP.
+ */
+ while(1);
+ }
+
+}
+
+
+/*--------------------------------------------------------------------------------------------------------*/
+
+
+/*
+// <h> Peripheral Secure Attribution Configuration
+*/
+
+/*
+ PNSSET0
+*/
+/*
+// Module 0..31
+// <o.9> USBH <0=> Secure <1=> Non-Secure
+// <o.13> SD0 <0=> Secure <1=> Non-Secure
+// <o.16> EBI <0=> Secure <1=> Non-Secure
+// <o.24> PDMA1 <0=> Secure <1=> Non-Secure
+*/
+#define SCU_INIT_PNSSET0_VAL 0x0
+/*
+ PNSSET1
+*/
+/*
+// Module 0..31
+// <o.17> CRC <0=> Secure <1=> Non-Secure
+// <o.18> CRPT <0=> Secure <1=> Non-Secure
+*/
+#define SCU_INIT_PNSSET1_VAL 0x0
+/*
+ PNSSET2
+*/
+/*
+// Module 0..31
+// <o.1> RTC <0=> Secure <1=> Non-Secure
+// <o.3> EADC <0=> Secure <1=> Non-Secure
+// <o.5> ACMP01 <0=> Secure <1=> Non-Secure
+//
+// <o.7> DAC <0=> Secure <1=> Non-Secure
+// <o.8> I2S0 <0=> Secure <1=> Non-Secure
+// <o.13> OTG <0=> Secure <1=> Non-Secure
+// <o.17> TMR23 <0=> Secure <1=> Non-Secure
+// <h> EPWM
+// <o.24> EPWM0 <0=> Secure <1=> Non-Secure
+// <o.25> EPWM1 <0=> Secure <1=> Non-Secure
+// <o.26> BPWM0 <0=> Secure <1=> Non-Secure
+// <o.27> BPWM1 <0=> Secure <1=> Non-Secure
+// </h>
+*/
+#define SCU_INIT_PNSSET2_VAL 0x0
+/*
+ PNSSET3
+*/
+/*
+// Module 0..31
+// <h> SPI
+// <o.0> QSPI0 <0=> Secure <1=> Non-Secure
+// <o.1> SPI0 <0=> Secure <1=> Non-Secure
+// <o.2> SPI1 <0=> Secure <1=> Non-Secure
+// <o.3> SPI2 <0=> Secure <1=> Non-Secure
+// <o.4> SPI3 <0=> Secure <1=> Non-Secure
+// </h>
+// <h> UART
+// <o.16> UART0 <0=> Secure <1=> Non-Secure
+// <o.17> UART1 <0=> Secure <1=> Non-Secure
+// <o.18> UART2 <0=> Secure <1=> Non-Secure
+// <o.19> UART3 <0=> Secure <1=> Non-Secure
+// <o.20> UART4 <0=> Secure <1=> Non-Secure
+// <o.21> UART5 <0=> Secure <1=> Non-Secure
+// </h>
+*/
+#define SCU_INIT_PNSSET3_VAL 0x20000
+/*
+ PNSSET4
+*/
+/*
+// Module 0..31
+// <h> I2C
+// <o.0> I2C0 <0=> Secure <1=> Non-Secure
+// <o.1> I2C1 <0=> Secure <1=> Non-Secure
+// <o.2> I2C2 <0=> Secure <1=> Non-Secure
+// </h>
+// <h> Smart Card
+// <o.16> SC0 <0=> Secure <1=> Non-Secure
+// <o.17> SC1 <0=> Secure <1=> Non-Secure
+// <o.18> SC2 <0=> Secure <1=> Non-Secure
+// </h>
+*/
+#define SCU_INIT_PNSSET4_VAL 0x0
+/*
+ PNSSET5
+*/
+/*
+// Module 0..31
+// <o.0> CAN0 <0=> Secure <1=> Non-Secure
+// <h> QEI
+// <o.16> QEI0 <0=> Secure <1=> Non-Secure
+// <o.17> QEI1 <0=> Secure <1=> Non-Secure
+// </h>
+// <h> ECAP
+// <o.20> ECAP0 <0=> Secure <1=> Non-Secure
+// <o.21> ECAP1 <0=> Secure <1=> Non-Secure
+// </h>
+// <o.25> TRNG <0=> Secure <1=> Non-Secure
+*/
+#define SCU_INIT_PNSSET5_VAL 0x0
+/*
+ PNSSET6
+*/
+/*
+// Module 0..31
+// <o.0> USBD <0=> Secure <1=> Non-Secure
+// <h> USCI
+// <o.16> USCI0 <0=> Secure <1=> Non-Secure
+// <o.17> USCI1 <0=> Secure <1=> Non-Secure
+// </h>
+*/
+#define SCU_INIT_PNSSET6_VAL 0x0
+/*
+// </h>
+*/
+
+
+
+/*
+// <h> GPIO Secure Attribution Configuration
+*/
+
+/*
+ IONSSET
+*/
+/*
+// Bit 0..31
+// <o.0> PA <0=> Secure <1=> Non-Secure
+// <o.1> PB <0=> Secure <1=> Non-Secure
+// <o.2> PC <0=> Secure <1=> Non-Secure
+// <o.3> PD <0=> Secure <1=> Non-Secure
+// <o.4> PE <0=> Secure <1=> Non-Secure
+// <o.5> PF <0=> Secure <1=> Non-Secure
+// <o.6> PG <0=> Secure <1=> Non-Secure
+// <o.7> PH <0=> Secure <1=> Non-Secure
+*/
+#define SCU_INIT_IONSSET_VAL 0x0
+/*
+// </h>
+*/
+
+
+
+/**
+ \brief Setup SCU Configuration Unit
+ \details
+
+ */
+__STATIC_INLINE void SCU_Setup(void)
+{
+ int32_t i;
+
+ SCU->PNSSET[0] = SCU_INIT_PNSSET0_VAL;
+ SCU->PNSSET[1] = SCU_INIT_PNSSET1_VAL;
+ SCU->PNSSET[2] = SCU_INIT_PNSSET2_VAL;
+ SCU->PNSSET[3] = SCU_INIT_PNSSET3_VAL;
+ SCU->PNSSET[4] = SCU_INIT_PNSSET4_VAL;
+ SCU->PNSSET[5] = SCU_INIT_PNSSET5_VAL;
+ SCU->PNSSET[6] = SCU_INIT_PNSSET6_VAL;
+
+ SCU->IONSSET = SCU_INIT_IONSSET_VAL;
+
+ /* Set Non-secure SRAM */
+ for(i = 11; i >= SCU_SECURE_SRAM_SIZE / 8192; i--)
+ {
+ SCU->SRAMNSSET |= (1U << i);
+ }
+
+
+}
+
+
+/* ---------------------------------------------------------------------------------------------------- */
+
+/*
+// <e>Secure Attribute Unit (SAU) Control
+*/
+#define SAU_INIT_CTRL 1
+
+/*
+// <q> Enable SAU
+// <i> To enable Secure Attribute Unit (SAU).
+*/
+#define SAU_INIT_CTRL_ENABLE 1
+
+/*
+// <o> All Memory Attribute When SAU is disabled
+// <0=> All Memory is Secure
+// <1=> All Memory is Non-Secure
+// <i> To set the ALLNS bit in SAU CTRL.
+// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS 0
+
+/*
+// </e>
+*/
+
+
+/*
+// <h>Enable and Set Secure/Non-Secure region
+*/
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
+
+/*
+// <e>SAU Region 0
+// <i> Setup SAU Region 0
+*/
+#define SAU_INIT_REGION0 0
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0 0x0003F000 /* start address of SAU region 0 */
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0 0x0003FFFF /* end address of SAU region 0 */
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0 1
+/*
+// </e>
+*/
+
+/*
+// <e>SAU Region 1
+// <i> Setup SAU Region 1
+*/
+#define SAU_INIT_REGION1 0
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1 0x10040000
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1 0x1007FFFF
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1 0
+/*
+// </e>
+*/
+
+/*
+// <e>SAU Region 2
+// <i> Setup SAU Region 2
+*/
+#define SAU_INIT_REGION2 0
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2 0x2000F000
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2 0x2000FFFF
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2 1
+/*
+// </e>
+*/
+
+/*
+// <e>SAU Region 3
+// <i> Setup SAU Region 3
+*/
+#define SAU_INIT_REGION3 1
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3 0x3f000
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3 0x3ffff
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3 1
+/*
+// </e>
+*/
+
+/*
+ <e>SAU Region 4
+ <i> Setup SAU Region 4
+*/
+#define SAU_INIT_REGION4 1
+/*
+ <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4 FMC_NON_SECURE_BASE /* start address of SAU region 4 */
+
+/*
+ <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4 0x1007FFFF /* end address of SAU region 4 */
+
+/*
+ <o>Region is
+ <0=>Non-Secure
+ <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4 0
+/*
+ </e>
+*/
+
+/*
+ <e>SAU Region 5
+ <i> Setup SAU Region 5
+*/
+#define SAU_INIT_REGION5 1
+
+/*
+ <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5 0x00807E00
+
+/*
+ <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5 0x00807FFF
+
+/*
+ <o>Region is
+ <0=>Non-Secure
+ <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5 1
+/*
+ </e>
+*/
+
+/*
+ <e>SAU Region 6
+ <i> Setup SAU Region 6
+*/
+#define SAU_INIT_REGION6 1
+
+/*
+ <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6 NON_SECURE_SRAM_BASE
+
+/*
+ <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6 0x30017FFF
+
+/*
+ <o>Region is
+ <0=>Non-Secure
+ <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6 0
+/*
+ </e>
+*/
+
+/*
+ <e>SAU Region 7
+ <i> Setup SAU Region 7
+*/
+#define SAU_INIT_REGION7 1
+
+/*
+ <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7 0x50000000
+
+/*
+ <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7 0x5FFFFFFF
+
+/*
+ <o>Region is
+ <0=>Non-Secure
+ <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7 0
+/*
+ </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behavior of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT 1
+
+/*
+// <o> Deep Sleep can be enabled by
+// <0=>Secure and Non-Secure state
+// <1=>Secure state only
+// <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL 0
+
+/*
+// <o>System reset request accessible from
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL 0
+
+/*
+// <o>Priority of Non-Secure exceptions is
+// <0=> Not altered
+// <1=> Lowered to 0x80-0xFF
+// <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL 0
+
+/*
+// <o>BusFault, HardFault, and NMI target
+// <0=> Secure state
+// <1=> Non-Secure state
+// <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 1
+
+/*
+// </e>
+*/
+
+
+/*
+// <h>Assign Interrupt to Secure or Non-secure Vector
+*/
+
+
+/*
+ Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0 1
+/*
+// BODOUT Always secure
+// IRC Always secure
+// PWRWU_ Always secure
+// SRAM_PERR Always secure
+// CLKFAIL Always secure
+
+// <o.6> RTC <0=> Secure <1=> Non-Secure
+// <o.7> TAMPER <0=> Secure <1=> Non-Secure
+// WDT Always secure
+// WWDT Always secure
+// <h> EINT
+// <o.10> EINT0 <0=> Secure <1=> Non-Secure
+// <o.11> EINT1 <0=> Secure <1=> Non-Secure
+// <o.12> EINT2 <0=> Secure <1=> Non-Secure
+// <o.13> EINT3 <0=> Secure <1=> Non-Secure
+// <o.14> EINT4 <0=> Secure <1=> Non-Secure
+// <o.15> EINT5 <0=> Secure <1=> Non-Secure
+// </h>
+// <h> GPIO
+// <o.16> GPA <0=> Secure <1=> Non-Secure
+// <o.17> GPB <0=> Secure <1=> Non-Secure
+// <o.18> GPC <0=> Secure <1=> Non-Secure
+// <o.19> GPD <0=> Secure <1=> Non-Secure
+// <o.20> GPE <0=> Secure <1=> Non-Secure
+// <o.21> GPF <0=> Secure <1=> Non-Secure
+// </h>
+// <o.22> QSPI0 <0=> Secure <1=> Non-Secure
+// <o.23> SPI0 <0=> Secure <1=> Non-Secure
+// <h> EPWM
+// <o.24> BRAKE0 <0=> Secure <1=> Non-Secure
+// <o.25> EPWM0_P0 <0=> Secure <1=> Non-Secure
+// <o.26> EPWM0_P1 <0=> Secure <1=> Non-Secure
+// <o.27> EPWM0_P2 <0=> Secure <1=> Non-Secure
+// <o.28> BRAKE1 <0=> Secure <1=> Non-Secure
+// <o.29> EPWM1_P0 <0=> Secure <1=> Non-Secure
+// <o.30> EPWM1_P1 <0=> Secure <1=> Non-Secure
+// <o.31> EPWM1_P2 <0=> Secure <1=> Non-Secure
+// </h>
+//
+*/
+#define NVIC_INIT_ITNS0_VAL 0x0
+
+/*
+ Initialize ITNS 1 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS1 1
+/*
+// <h> TIMER
+// TMR0 Always secure
+// TMR1 Always secure
+// <o.2> TMR2 <0=> Secure <1=> Non-Secure
+// <o.3> TMR3 <0=> Secure <1=> Non-Secure
+// </h>
+// <o.4> UART0 <0=> Secure <1=> Non-Secure
+// <o.5> UART1 <0=> Secure <1=> Non-Secure
+// <o.6> I2C0 <0=> Secure <1=> Non-Secure
+// <o.7> I2C1 <0=> Secure <1=> Non-Secure
+// PDMA0 is secure only
+// <o.9> DAC <0=> Secure <1=> Non-Secure
+// <o.10> EADC0 <0=> Secure <1=> Non-Secure
+// <o.11> EADC1 <0=> Secure <1=> Non-Secure
+// <o.12> ACMP01 <0=> Secure <1=> Non-Secure
+
+// <o.14> EADC2 <0=> Secure <1=> Non-Secure
+// <o.15> EADC3 <0=> Secure <1=> Non-Secure
+// <o.16> UART2 <0=> Secure <1=> Non-Secure
+// <o.17> UART3 <0=> Secure <1=> Non-Secure
+
+// <o.19> SPI1 <0=> Secure <1=> Non-Secure
+// <o.20> SPI2 <0=> Secure <1=> Non-Secure
+// <o.21> USBD <0=> Secure <1=> Non-Secure
+// <o.22> USBH <0=> Secure <1=> Non-Secure
+// <o.23> USBOTG <0=> Secure <1=> Non-Secure
+// <o.24> CAN0 <0=> Secure <1=> Non-Secure
+
+// <h> Smart Card
+// <o.26> SC0 <0=> Secure <1=> Non-Secure
+// <o.27> SC1 <0=> Secure <1=> Non-Secure
+// <o.28> SC2 <0=> Secure <1=> Non-Secure
+// </h>
+
+// <o.30> SPI3 <0=> Secure <1=> Non-Secure
+
+//
+*/
+#define NVIC_INIT_ITNS1_VAL 0x20
+
+/*
+ Initialize ITNS 2 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS2 1
+/*
+// <o.0> SDH0 <0=> Secure <1=> Non-Secure
+
+
+
+// <o.4> I2S0 <0=> Secure <1=> Non-Secure
+
+//
+// <o.7> CRYPTO <0=> Secure <1=> Non-Secure
+// <o.8> GPG <0=> Secure <1=> Non-Secure
+// <o.9> EINT6 <0=> Secure <1=> Non-Secure
+// <o.10> UART4 <0=> Secure <1=> Non-Secure
+// <o.11> UART5 <0=> Secure <1=> Non-Secure
+// <o.12> USCI0 <0=> Secure <1=> Non-Secure
+// <o.13> USCI1 <0=> Secure <1=> Non-Secure
+// <o.14> BPWM0 <0=> Secure <1=> Non-Secure
+// <o.15> BPWM1 <0=> Secure <1=> Non-Secure
+
+
+// <o.18> I2C2 <0=> Secure <1=> Non-Secure
+
+// <o.20> QEI0 <0=> Secure <1=> Non-Secure
+// <o.21> QEI1 <0=> Secure <1=> Non-Secure
+// <o.22> ECAP0 <0=> Secure <1=> Non-Secure
+// <o.23> ECAP1 <0=> Secure <1=> Non-Secure
+// <o.24> GPH <0=> Secure <1=> Non-Secure
+// <o.25> EINT7 <0=> Secure <1=> Non-Secure
+
+
+// <o.28> USBH <0=> Secure <1=> Non-Secure
+
+
+
+//
+*/
+#define NVIC_INIT_ITNS2_VAL 0x0
+
+
+/*
+ Initialize ITNS 3 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS3 1
+/*
+// <o.2> PDMA1 <0=> Secure <1=> Non-Secure
+// SCU Always secure
+//
+// <o.5> TRNG <0=> Secure <1=> Non-Secure
+*/
+#define NVIC_INIT_ITNS3_VAL 0x0
+
+
+
+/*
+// </h>
+*/
+
+
+
+/*
+ max 128 SAU regions.
+ SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
+
+/**
+ \brief Setup a SAU Region
+ \details Writes the region information contained in SAU_Region to the
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup(void)
+{
+
+#if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
+
+#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+ SAU_INIT_REGION(0);
+#endif
+
+#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+ SAU_INIT_REGION(1);
+#endif
+
+#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+ SAU_INIT_REGION(2);
+#endif
+
+#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+ SAU_INIT_REGION(3);
+#endif
+
+#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+ SAU_INIT_REGION(4);
+#endif
+
+#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+ SAU_INIT_REGION(5);
+#endif
+
+#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+ SAU_INIT_REGION(6);
+#endif
+
+#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+ SAU_INIT_REGION(7);
+#endif
+
+ /* repeat this for all possible SAU regions */
+
+
+#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
+#endif
+
+#endif /* defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U) */
+
+#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) |
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
+
+// SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) |
+// ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+// ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |
+// ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);
+
+ SCB->AIRCR = (0x05FA << 16) |
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);
+
+
+
+#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+#if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
+ SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk)) |
+ ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
+#endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
+
+#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+#endif
+
+#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+#endif
+
+#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+#endif
+
+#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+#endif
+
+
+ /* repeat this for all possible ITNS elements */
+
+}
+
+
+#endif /* PARTITION_M2351 */
+
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/******************************************************************************\r
+ See http://www.freertos.org/a00110.html for an explanation of the\r
+ definitions contained in this file.\r
+******************************************************************************/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ * http://www.freertos.org/a00110.html\r
+ *----------------------------------------------------------*/\r
+\r
+extern uint32_t SystemCoreClock;\r
+\r
+/* Cortex M33 port configuration. */\r
+#define configENABLE_MPU 1\r
+#define configENABLE_FPU 0\r
+#define configENABLE_TRUSTZONE 1\r
+\r
+/* Constants related to the behaviour or the scheduler. */\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_TIME_SLICING 1\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */\r
+\r
+/* Constants that describe the hardware and memory usage. */\r
+#define configCPU_CLOCK_HZ SystemCoreClock\r
+#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 )\r
+#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) )\r
+\r
+/* Constants that build features in or out. */\r
+#define configUSE_MUTEXES 1\r
+#define configUSE_TICKLESS_IDLE 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_NEWLIB_REENTRANT 0\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_QUEUE_SETS 0\r
+#define configUSE_TASK_NOTIFICATIONS 1\r
+#define configUSE_TRACE_FACILITY 1\r
+\r
+/* Constants that define which hook (callback) functions should be used. */\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+\r
+/* Constants provided for debugging and optimisation assistance. */\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 3 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+ * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is\r
+ * only necessary if the linker does not automatically remove functions that are\r
+ * not referenced anyway. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 0\r
+#define INCLUDE_xTaskGetIdleTaskHandle 0\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xTaskResumeFromISR 0\r
+#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
+#define INCLUDE_xTaskGetSchedulerState 0\r
+#define INCLUDE_xSemaphoreGetMutexHolder 0\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+\r
+/* This demo makes use of one or more example stats formatting functions. These\r
+ * format the raw data provided by the uxTaskGetSystemState() function in to\r
+ * human readable ASCII form. See the notes in the implementation of vTaskList()\r
+ * within FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
+\r
+/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter.\r
+ * See the FreeRTOS+CLI documentation for more information:\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */\r
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048\r
+\r
+/* Interrupt priority configuration follows...................... */\r
+\r
+/* Use the system definition, if there is one. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 3 /* 8 priority levels. */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+ * function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+ * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT\r
+ * CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A\r
+ * HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+ * to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )\r
+\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+ * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )\r
+\r
+/* The #ifdef guards against the file being included from IAR assembly files. */\r
+#ifndef __IASMARM__\r
+\r
+ /* Constants related to the generation of run time stats. */\r
+ #define configGENERATE_RUN_TIME_STATS 0\r
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
+ #define portGET_RUN_TIME_COUNTER_VALUE() 0\r
+ #define configTICK_RATE_HZ ( ( TickType_t ) 100 )\r
+\r
+#endif /* __IASMARM__ */\r
+\r
+/* Enable static allocation. */\r
+#define configSUPPORT_STATIC_ALLOCATION 1\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
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+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <WorkspaceName>WorkSpace</WorkspaceName>
+
+ <project>
+ <PathAndName>.\Secure\FreeRTOSDemo_s.uvprojx</PathAndName>
+ <NodeIsActive>1</NodeIsActive>
+ <NodeIsExpanded>1</NodeIsExpanded>
+ </project>
+
+ <project>
+ <PathAndName>.\Nonsecure\FreeRTOSDemo_ns.uvprojx</PathAndName>
+ <NodeIsExpanded>1</NodeIsExpanded>
+ </project>
+
+</ProjectWorkspace>
--- /dev/null
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+<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->\r
+ <events>\r
+ </events>\r
+\r
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--- /dev/null
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+;\r
+; Privileged Data:\r
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+LR_IROM_NS_PRIVILEGED 0x10040000 0x00007000 ; load region size_region\r
+{\r
+ ER_IROM_NS_PRIVILEGED +0 ; load address = execution address\r
+ {\r
+ *.o(RESET, +First)\r
+ *(InRoot$$Sections) ; All sections that must be in a root region\r
+ *(privileged_functions)\r
+ }\r
+\r
+ ER_IRAM_NS_PRIVILEGED 0x30008000 0x00001000\r
+ {\r
+ *(privileged_data)\r
+ }\r
+}\r
+\r
+; System Calls:\r
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+; Size : 4 Kbytes\r
+LR_IROM_NS_SYSTEM_CALLS 0x10047000 0x00001000 ; load region size_region\r
+{\r
+ ER_IROM_NS_SYSTEM_CALLS +0 ; load address = execution address\r
+ {\r
+ *(freertos_system_calls)\r
+ }\r
+}\r
+\r
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+;\r
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+{\r
+ ER_IROM_NS_UNPRIVILEGED +0 ; load address = execution address\r
+ {\r
+ *(+RO)\r
+ }\r
+\r
+ ER_IRAM_NS_UNPRIVILEGED 0x30009000 0x0000F000\r
+ {\r
+ *(+RW, +ZI)\r
+ }\r
+}\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj; *.o</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ <nMigrate>0</nMigrate>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>FreeRTOSDemo_ns</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
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+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
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+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
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+ </OPTHX>
+ <OPTLEX>
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+ <TabStop>8</TabStop>
+ <ListingPath>.\Listings\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
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+ <CListInc>0</CListInc>
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+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
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+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
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+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
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+ <bEvRecOn>1</bEvRecOn>
+ <nTsel>19</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
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+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile>.\FreeRTOSDemo_ns_debug.ini</tIfile>
+ <pMon>Bin\Nu_Link.dll</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGTARM</Key>
+ <Name>(6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=3048,372,3621,908,0)(6000=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
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+ <Key>ARMDBGFLAGS</Key>
+ <Name></Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>Nu_Link</Key>
+ <Name></Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2V8M</Key>
+ <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <MemoryWindow1>
+ <Mm>
+ <WinNumber>1</WinNumber>
+ <SubType>2</SubType>
+ <ItemText>0x30016060</ItemText>
+ <AccSizeX>0</AccSizeX>
+ </Mm>
+ </MemoryWindow1>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>0</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
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+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ <bAutoGenD>0</bAutoGenD>
+ <LntExFlags>0</LntExFlags>
+ <pMisraName></pMisraName>
+ <pszMrule></pszMrule>
+ <pSingCmds></pSingCmds>
+ <pMultCmds></pMultCmds>
+ <pMisraNamep></pMisraNamep>
+ <pszMrulep></pszMrulep>
+ <pSingCmdsp></pSingCmdsp>
+ <pMultCmdsp></pMultCmdsp>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Config</GroupName>
+ <tvExp>0</tvExp>
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--- /dev/null
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+ <FileType>5</FileType>
+ <FilePath>..\..\..\..\Common\ARMv8M\tz_demo\tz_demo.h</FilePath>
+ </File>
+ <File>
+ <FileName>tz_demo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\Common\ARMv8M\tz_demo\tz_demo.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>User</GroupName>
+ <Files>
+ <File>
+ <FileName>main_ns.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main_ns.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+ <RTE>
+ <apis/>
+ <components/>
+ <files>
+ <file attr="config" category="header" name="Device\ARM\ARMv8MBL\Include\Template\partition_ARMv8MBL.h" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMv8MBL\partition_ARMv8MBL.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.6.0-RC1"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC_V6" name="Device\ARM\ARMv8MBL\Source\ARM\startup_ARMv8MBL.s" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMv8MBL\startup_ARMv8MBL.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.6.0-RC1"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceC" condition="ARMCC_V6" name="Device\ARM\ARMv8MBL\Source\system_ARMv8MBL.c" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMv8MBL\system_ARMv8MBL.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.6.0-RC1"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="header" name="Device\CMSDK_ARMv8MBL\Include\Template\partition_ARMv8MBL.h" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\partition_ARMv8MBL.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.2.0-RC2"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="header" name="Device\CMSDK_ARMv8MBL\Include\Template\partition_CMSDK_ARMv8MBL.h" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\partition_CMSDK_ARMv8MBL.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="source" condition="ARMCC" name="Device\CMSDK_ARMv8MBL\Source\ARM\startup_CMSDK_ARMv8MBL.s" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\startup_CMSDK_ARMv8MBL.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="source" name="Device\CMSDK_ARMv8MBL\Source\system_CMSDK_ARMv8MBL.c" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\system_CMSDK_ARMv8MBL.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="header" name="Device\ARMv8MBL\Include\Template\partition_ARMv8MBL.h" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\MPS2_ARMv8MBL\partition_ARMv8MBL.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.1" condition="ARMv8MBL CMSIS"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.2.0-alpha"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARMv8MBL\Source\ARM\startup_ARMv8MBL.s" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\MPS2_ARMv8MBL\startup_ARMv8MBL.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.1" condition="ARMv8MBL CMSIS"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.2.0-alpha"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceC" name="Device\ARMv8MBL\Source\system_ARMv8MBL.c" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\MPS2_ARMv8MBL\system_ARMv8MBL.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.1" condition="ARMv8MBL CMSIS"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.2.0-alpha"/>
+ <targetInfos/>
+ </file>
+ </files>
+ </RTE>
+
+</Project>
--- /dev/null
+LOAD ".\\Objects\\FreeRTOSDemo_ns.axf" incremental\r
+LOAD "..\\Secure\\Objects\\FreeRTOSDemo_s.axf" incremental\r
+RESET\r
+g, \\FreeRTOSDemo_s\main_s\main
\ No newline at end of file
--- /dev/null
+LOAD "..\\Secure\\Objects\\FreeRTOSDemo_s.axf" incremental
\ No newline at end of file
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Device includes. */\r
+#include <arm_cmse.h>\r
+#include "NuMicro.h"\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "tz_demo.h"\r
+#include "mpu_demo.h"\r
+\r
+/* Externs needed by the MPU setup code. These must match the memory map as\r
+ * specified in Scatter-Loading description file (FreeRTOSDemo_ns.sct). */\r
+/* Privileged flash. */\r
+const uint32_t * __privileged_functions_start__ = ( uint32_t * ) ( 0x10040000 );\r
+const uint32_t * __privileged_functions_end__ = ( uint32_t * ) ( 0x10047000 - 0x1 ); /* Last address in privileged Flash region. */\r
+\r
+/* Flash containing system calls. Note that the section containing system calls\r
+ * is unprivileged so that unprivileged tasks can make system calls.*/\r
+const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) ( 0x10047000 );\r
+const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) ( 0x10048000 - 0x1 ); /* Last address in Flash region containing system calls. */\r
+\r
+/* Unprivileged flash. */\r
+const uint32_t * __unprivileged_flash_start__ = ( uint32_t * ) ( 0x10048000 );\r
+const uint32_t * __unprivileged_flash_end__ = ( uint32_t * ) ( 0x10080000 - 0x1 ); /* Last address in un-privileged Flash region. */\r
+\r
+/* Privileged RAM. It contains kernel data. */\r
+const uint32_t * __privileged_sram_start__ = ( uint32_t * ) ( 0x30008000 );\r
+const uint32_t * __privileged_sram_end__ = ( uint32_t * ) ( 0x30009000 - 0x1 ); /* Last address in privileged RAM. */\r
+\r
+/* Unprivileged RAM. */\r
+const uint32_t * __unprivileged_sram_start__ = ( uint32_t * ) ( 0x30009000 );\r
+const uint32_t * __unprivileged_sram_end__ = ( uint32_t * ) ( 0x30018000 - 0x1 ); /* Last address in un-privileged RAM. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Create all demo tasks.\r
+ */\r
+static void prvCreateTasks( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCreateTasks( void )\r
+{\r
+ /* Create tasks for the MPU Demo. */\r
+ vStartMPUDemo();\r
+\r
+ /* Create tasks for the TZ Demo. */\r
+ vStartTZDemo();\r
+\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Stack overflow hook. */\r
+void vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName )\r
+{\r
+ /* Force an assert. */\r
+ configASSERT( pcTaskName == 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Non-Secure main. */\r
+int main( void )\r
+{\r
+ /* Initialize debug port. */\r
+ DEBUG_PORT->BAUD = UART_BAUD_MODE2 | UART_BAUD_MODE2_DIVIDER( __HIRC, 115200 );\r
+ DEBUG_PORT->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;\r
+\r
+ /* Print banner. */\r
+ printf( "\n" );\r
+ printf( "+---------------------------------------------+\n" );\r
+ printf( "| Nonsecure is running ... |\n" );\r
+ printf( "+---------------------------------------------+\n" );\r
+\r
+ /* Create tasks. */\r
+ prvCreateTasks();\r
+\r
+ /* Start scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not reach here as the schedular is already started. */\r
+ for( ; ; )\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an\r
+ * implementation of vApplicationGetIdleTaskMemory() to provide the memory that\r
+ * is used by the Idle task. */\r
+void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,\r
+ StackType_t ** ppxIdleTaskStackBuffer,\r
+ uint32_t * pulIdleTaskStackSize )\r
+{\r
+ /* If the buffers to be provided to the Idle task are declared inside this\r
+ * function then they must be declared static - otherwise they will be\r
+ * allocated on the stack and so not exists after this function exits. */\r
+ static StaticTask_t xIdleTaskTCB;\r
+ static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle\r
+ * task's state will be stored. */\r
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Idle task's stack. */\r
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
+ * Note that, as the array is necessarily of type StackType_t,\r
+ * configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the\r
+ * application must provide an implementation of vApplicationGetTimerTaskMemory()\r
+ * to provide the memory that is used by the Timer service task. */\r
+void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,\r
+ StackType_t ** ppxTimerTaskStackBuffer,\r
+ uint32_t * pulTimerTaskStackSize )\r
+{\r
+ /* If the buffers to be provided to the Timer task are declared inside this\r
+ * function then they must be declared static - otherwise they will be\r
+ * allocated on the stack and so not exists after this function exits. */\r
+ static StaticTask_t xTimerTaskTCB;\r
+ static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__( ( aligned( 32 ) ) );\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
+ * task's state will be stored. */\r
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Timer task's stack. */\r
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
+ * Note that, as the array is necessarily of type StackType_t,\r
+ * configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */\r
+ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief The fault handler implementation calls a function called\r
+ * vHandleMemoryFault.\r
+ */\r
+void HardFault_Handler( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ " movs r0, #4 \n"\r
+ " mov r1, lr \n"\r
+ " tst r0, r1 \n"\r
+ " beq stacking_used_msp \n"\r
+ " mrs r0, psp \n"\r
+ " ldr r2, handler_address_const \n"\r
+ " bx r2 \n"\r
+ "stacking_used_msp: \n"\r
+ " mrs r0, msp \n"\r
+ " ldr r2, handler_address_const \n"\r
+ " bx r2 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ " handler_address_const: .word vHandleMemoryFault \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+\r
+/*\r
+ * Auto generated Run-Time-Environment Component Configuration File\r
+ * *** Do not modify ! ***\r
+ *\r
+ * Project: 'CM33_ns' \r
+ * Target: 'FVP Simulation Model' \r
+ */\r
+\r
+#ifndef RTE_COMPONENTS_H\r
+#define RTE_COMPONENTS_H\r
+\r
+\r
+/*\r
+ * Define the Device Header File: \r
+ */\r
+#define CMSIS_device_header "M2351.h"\r
+\r
+\r
+#endif /* RTE_COMPONENTS_H */\r
--- /dev/null
+<?xml version="1.0" encoding="utf-8"?>\r
+\r
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">\r
+\r
+<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->\r
+ <events>\r
+ </events>\r
+\r
+</component_viewer>\r
--- /dev/null
+\r
+LR_IROM_S 0x00000000 0x0003F000 ; load region size_region\r
+{\r
+ ER_IROM_S +0 ; load address = execution address\r
+ {\r
+ *.o(RESET, +First)\r
+ *(+RO)\r
+ }\r
+\r
+ RW_IRAM_S 0x20000000 0x00008000 ; RW data\r
+ {\r
+ *(+RW, +ZI)\r
+ }\r
+}\r
+\r
+LR_IROM_NSC 0x0003F000 0x00001000\r
+{\r
+ ER_IROM_NSC +0 ; load address = execution address\r
+ {\r
+ *(Veneer$$CMSE)\r
+ }\r
+}\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj; *.o</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ <nMigrate>0</nMigrate>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>FreeRTOSDemo_s</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\Listings\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>0</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>1</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <bEvRecOn>1</bEvRecOn>
+ <nTsel>19</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile>.\FreeRTOSDemo_s_debug.ini</tIfile>
+ <pMon>Bin\Nu_Link.dll</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGTARM</Key>
+ <Name>(6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name></Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>Nu_Link</Key>
+ <Name></Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2V8M</Key>
+ <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>0</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ <bAutoGenD>0</bAutoGenD>
+ <LntExFlags>0</LntExFlags>
+ <pMisraName></pMisraName>
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+ <pSingCmds></pSingCmds>
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--- /dev/null
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+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <v6Lang>5</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <v6Lto>0</v6Lto>
+ <v6WtE>0</v6WtE>
+ <v6Rtti>0</v6Rtti>
+ <VariousControls>
+ <MiscControls>-mfloat-abi=soft -Wno-documentation -Wno-reserved-id-macro</MiscControls>
+ <Define>DEBUG_PORT = UART1</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\Config;..\..\Keil;..\..\..\..\Common\ARMv8M\tz_demo;..\..\..\..\..\Source\portable\GCC\ARM_CM23\secure;..\..\..\Nuvoton_Code\StdDriver\inc;..\..\..\Nuvoton_Code\CMSIS\Include;..\..\..\Nuvoton_Code\Device\Nuvoton\M2351\Include</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>1</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>1</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <uClangAs>0</uClangAs>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile>.\FreeRTOSDemo_s.sct</ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc>--import-cmse-lib-out .\Objects\FreeRTOSDemo_importlib.o</Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Device</GroupName>
+ <Files>
+ <File>
+ <FileName>system_M2351.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Nuvoton_Code\Device\Nuvoton\M2351\Source\system_M2351.c</FilePath>
+ </File>
+ <File>
+ <FileName>startup_M2351.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>..\..\..\Nuvoton_Code\Device\Nuvoton\M2351\Source\ARM\startup_M2351.s</FilePath>
+ </File>
+ <File>
+ <FileName>partition_M2351.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\partition_M2351.h</FilePath>
+ </File>
+ <File>
+ <FileName>RTE_Components.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\RTE_Components.h</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Drivers</GroupName>
+ <Files>
+ <File>
+ <FileName>clk.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Nuvoton_Code\StdDriver\src\clk.c</FilePath>
+ </File>
+ <File>
+ <FileName>gpio.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Nuvoton_Code\StdDriver\src\gpio.c</FilePath>
+ </File>
+ <File>
+ <FileName>retarget.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Nuvoton_Code\StdDriver\src\retarget.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>NSCFunctions</GroupName>
+ <Files>
+ <File>
+ <FileName>nsc_functions.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\..\Common\ARMv8M\tz_demo\nsc_functions.h</FilePath>
+ </File>
+ <File>
+ <FileName>nsc_functions.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\Common\ARMv8M\tz_demo\nsc_functions.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>SecureContext</GroupName>
+ <Files>
+ <File>
+ <FileName>secure_context.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\..\..\Source\portable\GCC\ARM_CM23\secure\secure_context.h</FilePath>
+ </File>
+ <File>
+ <FileName>secure_context.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\..\Source\portable\GCC\ARM_CM23\secure\secure_context.c</FilePath>
+ </File>
+ <File>
+ <FileName>secure_context_port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\..\Source\portable\GCC\ARM_CM23\secure\secure_context_port.c</FilePath>
+ </File>
+ <File>
+ <FileName>secure_port_macros.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\..\..\Source\portable\GCC\ARM_CM23\secure\secure_port_macros.h</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>SecureHeap</GroupName>
+ <Files>
+ <File>
+ <FileName>secure_heap.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\..\..\Source\portable\GCC\ARM_CM23\secure\secure_heap.h</FilePath>
+ </File>
+ <File>
+ <FileName>secure_heap.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\..\Source\portable\GCC\ARM_CM23\secure\secure_heap.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>SecureInit</GroupName>
+ <Files>
+ <File>
+ <FileName>secure_init.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\..\..\Source\portable\GCC\ARM_CM23\secure\secure_init.h</FilePath>
+ </File>
+ <File>
+ <FileName>secure_init.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\..\..\Source\portable\GCC\ARM_CM23\secure\secure_init.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>User</GroupName>
+ <Files>
+ <File>
+ <FileName>main_s.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main_s.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+ <RTE>
+ <apis/>
+ <components/>
+ <files>
+ <file attr="config" category="header" name="Device\ARM\ARMv8MBL\Include\Template\partition_ARMv8MBL.h" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMv8MBL\partition_ARMv8MBL.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.6.0-RC1"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC_V6" name="Device\ARM\ARMv8MBL\Source\ARM\startup_ARMv8MBL.s" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMv8MBL\startup_ARMv8MBL.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.6.0-RC1"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceC" condition="ARMCC_V6" name="Device\ARM\ARMv8MBL\Source\system_ARMv8MBL.c" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMv8MBL\system_ARMv8MBL.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.6.0-RC1"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="header" name="Device\CMSDK_ARMv8MBL\Include\Template\partition_ARMv8MBL.h" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\partition_ARMv8MBL.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.2.0-RC2"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="header" name="Device\CMSDK_ARMv8MBL\Include\Template\partition_CMSDK_ARMv8MBL.h" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\partition_CMSDK_ARMv8MBL.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="source" condition="ARMCC" name="Device\CMSDK_ARMv8MBL\Source\ARM\startup_CMSDK_ARMv8MBL.s" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\startup_CMSDK_ARMv8MBL.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="source" name="Device\CMSDK_ARMv8MBL\Source\system_CMSDK_ARMv8MBL.c" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\system_CMSDK_ARMv8MBL.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.3.0"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="header" name="Device\ARMv8MBL\Include\Template\partition_ARMv8MBL.h" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\MPS2_ARMv8MBL\partition_ARMv8MBL.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.1" condition="ARMv8MBL CMSIS"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.2.0-alpha"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARMv8MBL\Source\ARM\startup_ARMv8MBL.s" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\MPS2_ARMv8MBL\startup_ARMv8MBL.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.1" condition="ARMv8MBL CMSIS"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.2.0-alpha"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceC" name="Device\ARMv8MBL\Source\system_ARMv8MBL.c" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\MPS2_ARMv8MBL\system_ARMv8MBL.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.1" condition="ARMv8MBL CMSIS"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.2.0-alpha"/>
+ <targetInfos/>
+ </file>
+ </files>
+ </RTE>
+
+</Project>
--- /dev/null
+LOAD ".\\Objects\\FreeRTOSDemo_s.axf" incremental\r
+LOAD "..\\NonSecure\\Objects\\FreeRTOSDemo_ns.axf" incremental\r
+RESET\r
+g, \\FreeRTOSDemo_s\main_s\main
\ No newline at end of file
--- /dev/null
+LOAD "..\\NonSecure\\Objects\\FreeRTOSDemo_ns.axf" incremental
\ No newline at end of file
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <arm_cmse.h>\r
+#include <stdio.h>\r
+\r
+/* Device includes. */\r
+#include "NuMicro.h"\r
+#include "partition_M2351.h"\r
+\r
+/* FreeRTOS includes. */\r
+#include "secure_port_macros.h"\r
+\r
+/* Start address of non-secure application. */\r
+#define mainNONSECURE_APP_START_ADDRESS ( 0x10040000 )\r
+\r
+/* typedef for non-secure Reset Handler. */\r
+typedef __attribute__( ( cmse_nonsecure_call ) ) void ( *NonSecureResetHandler_t )( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Sets up the hardware - clocks and UARTs.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/**\r
+ * @brief Boots into the non-secure code.\r
+ *\r
+ * @param[in] ulNonSecureStartAddress Start address of the non-secure application.\r
+ */\r
+static void prvBootNonSecure( uint32_t ulNonSecureStartAddress );\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Init System Clock. */\r
+ /* Enable PLL */\r
+ CLK->PLLCTL = CLK_PLLCTL_64MHz_HIRC;\r
+ /* Wait for PLL to be stable. */\r
+ while( ( CLK->STATUS & CLK_STATUS_PLLSTB_Msk ) == 0 );\r
+\r
+ /* Set HCLK divider to 1. */\r
+ CLK->CLKDIV0 = ( CLK->CLKDIV0 & ( ~CLK_CLKDIV0_HCLKDIV_Msk ) );\r
+\r
+ /* Switch HCLK clock source to PLL. */\r
+ CLK->CLKSEL0 = ( CLK->CLKSEL0 & ( ~CLK_CLKSEL0_HCLKSEL_Msk ) ) | CLK_CLKSEL0_HCLKSEL_PLL;\r
+\r
+ /* Initialize UART0 - It is used for debug output from the non-secure side. */\r
+ /* Enable UART0 clock. */\r
+ CLK->APBCLK0 |= CLK_APBCLK0_UART0CKEN_Msk;\r
+\r
+ /* Select UART0 clock source. */\r
+ CLK->CLKSEL1 = ( CLK->CLKSEL1 & ( ~CLK_CLKSEL1_UART0SEL_Msk ) ) | CLK_CLKSEL1_UART0SEL_HIRC;\r
+\r
+ /* Set multi-function pins for UART0 RXD and TXD. */\r
+ SYS->GPB_MFPH = ( SYS->GPB_MFPH & ( ~UART0_RXD_PB12_Msk ) ) | UART0_RXD_PB12;\r
+ SYS->GPB_MFPH = ( SYS->GPB_MFPH & ( ~UART0_TXD_PB13_Msk ) ) | UART0_TXD_PB13;\r
+\r
+ /* Initialize UART1 - It is used for debug output from the secure side. */\r
+ /* Enable UART1 clock. */\r
+ CLK->APBCLK0 |= CLK_APBCLK0_UART1CKEN_Msk;\r
+\r
+ /* Select UART1 clock source. */\r
+ CLK->CLKSEL1 = ( CLK->CLKSEL1 & ( ~CLK_CLKSEL1_UART1SEL_Msk ) ) | CLK_CLKSEL1_UART1SEL_HIRC;\r
+\r
+ /* Set multi-function pins for UART1 RXD and TXD. */\r
+ SYS->GPA_MFPL = ( SYS->GPA_MFPL & ( ~UART1_RXD_PA2_Msk ) ) | UART1_RXD_PA2;\r
+ SYS->GPA_MFPL = ( SYS->GPA_MFPL & ( ~UART1_TXD_PA3_Msk ) ) | UART1_TXD_PA3;\r
+\r
+ /* Update System Core Clock. */\r
+ PllClock = 64000000; /* PLL. */\r
+ SystemCoreClock = 64000000 / 1; /* HCLK. */\r
+ CyclesPerUs = 64000000 / 1000000; /* For SYS_SysTickDelay(). */\r
+\r
+ /* Initialize the debug port. */\r
+ DEBUG_PORT->BAUD = UART_BAUD_MODE2 | UART_BAUD_MODE2_DIVIDER(__HIRC, 115200);\r
+ DEBUG_PORT->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvBootNonSecure( uint32_t ulNonSecureStartAddress )\r
+{\r
+ NonSecureResetHandler_t pxNonSecureResetHandler;\r
+\r
+ /* Setup the non-secure vector table. */\r
+ SCB_NS->VTOR = ulNonSecureStartAddress;\r
+\r
+ /* Main Stack Pointer value for the non-secure side is the first entry in\r
+ * the non-secure vector table. Read the first entry and assign the same to\r
+ * the non-secure main stack pointer(MSP_NS). */\r
+ secureportSET_MSP_NS( *( ( uint32_t * )( ulNonSecureStartAddress ) ) );\r
+\r
+ /* Reset Handler for the non-secure side is the second entry in the\r
+ * non-secure vector table. Read the second entry to get the non-secure\r
+ * Reset Handler. */\r
+ pxNonSecureResetHandler = ( NonSecureResetHandler_t )( * ( ( uint32_t * ) ( ( ulNonSecureStartAddress ) + 4U ) ) );\r
+\r
+ /* Start non-secure state software application by jumping to the non-secure\r
+ * Reset Handler. */\r
+ pxNonSecureResetHandler();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Secure main. */\r
+int main(void)\r
+{\r
+ /* Unlock protected registers. */\r
+ SYS_UnlockReg();\r
+\r
+ /* Initialize the hardware. */\r
+ prvSetupHardware();\r
+\r
+ /* Print banner. */\r
+ printf( "\n" );\r
+ printf( "+---------------------------------------------+\n" );\r
+ printf( "| Secure is running ... |\n" );\r
+ printf( "+---------------------------------------------+\n" );\r
+\r
+ /* Do not generate Systick interrupt on secure side. */\r
+ SysTick_Config( 1 );\r
+\r
+ /* Set GPIO Port A to non-secure for controlling LEDs from the non-secure\r
+ * side . */\r
+ SCU_SET_IONSSET( SCU_IONSSET_PA_Msk );\r
+\r
+ /* Set UART0 to non-secure for debug output from non-secure side. */\r
+ SCU_SET_PNSSET( UART0_Attr );\r
+\r
+ /* Lock protected registers before booting non-secure code. */\r
+ SYS_LockReg();\r
+\r
+ /* Boot the non-secure code. */\r
+ printf( "Entering non-secure world ...\n" );\r
+ prvBootNonSecure( mainNONSECURE_APP_START_ADDRESS );\r
+\r
+ /* Non-secure software does not return, this code is not executed. */\r
+ for( ; ; )\r
+ {\r
+ /* Should not reach here. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file partition_M2351.c\r
+ * @version V3.00\r
+ * @brief SAU configuration for secure/nonsecure region settings.\r
+ *\r
+ * @note\r
+ * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef PARTITION_M2351\r
+#define PARTITION_M2351\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\r
+*/\r
+\r
+\r
+/*\r
+ SRAMNSSET\r
+*/\r
+/*\r
+// Bit 0..16\r
+// <o.0..16> Secure SRAM Size <0=> 0 KB\r
+// <0x2000=> 8KB\r
+// <0x4000=> 16KB\r
+// <0x6000=> 24KB\r
+// <0x8000=> 32KB\r
+// <0xa000=> 40KB\r
+// <0xc000=> 48KB\r
+// <0xe000=> 56KB\r
+// <0x10000=> 64KB\r
+// <0x12000=> 72KB\r
+// <0x14000=> 80KB\r
+// <0x16000=> 88KB\r
+// <0x18000=> 96KB\r
+*/\r
+#define SCU_SECURE_SRAM_SIZE 0x8000\r
+#define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE)\r
+\r
+\r
+\r
+/*--------------------------------------------------------------------------------------------------------*/\r
+\r
+/*\r
+ NSBA\r
+*/\r
+#define FMC_INIT_NSBA 1\r
+/*\r
+// <o>Secure Flash ROM Size <0x800-0x7FFFF:0x800>\r
+*/\r
+\r
+#define FMC_SECURE_ROM_SIZE 0x40000\r
+\r
+#define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE)\r
+\r
+__STATIC_INLINE void FMC_NSBA_Setup(void)\r
+{\r
+ /* Skip NSBA Setupt according config */\r
+ if(FMC_INIT_NSBA == 0)\r
+ return;\r
+\r
+ /* Check if NSBA value with current active NSBA */\r
+ if(SCU->FNSADDR != FMC_SECURE_ROM_SIZE)\r
+ {\r
+ /* Unlock Protected Register */\r
+ SYS_UnlockReg();\r
+\r
+ /* Enable ISP and config update */\r
+ FMC->ISPCTL = FMC_ISPCTL_ISPEN_Msk | FMC_ISPCTL_CFGUEN_Msk;\r
+\r
+ /* Config Base of NSBA */\r
+ FMC->ISPADDR = 0x200800;\r
+\r
+ /* Read Non-secure base address config */\r
+ FMC->ISPCMD = FMC_ISPCMD_READ;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+ while(FMC->ISPTRG);\r
+\r
+ /* Setting NSBA when it is empty */\r
+ if(FMC->ISPDAT == 0xfffffffful)\r
+ {\r
+ FMC->ISPDAT = FMC_SECURE_ROM_SIZE;\r
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;\r
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;\r
+ while(FMC->ISPTRG);\r
+\r
+ /* Force Chip Reset to valid new setting */\r
+ SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;\r
+ }\r
+\r
+ /* Fatal Error:\r
+ FMC NSBA setting is different to FMC_INIT_NSBA_VAL.\r
+ User must double confirm which one is wrong.\r
+\r
+ If user need to change NSBA config of FMC, user must do Mess-erase by\r
+ ISP or ICP.\r
+ */\r
+ while(1);\r
+ }\r
+\r
+}\r
+\r
+\r
+/*--------------------------------------------------------------------------------------------------------*/\r
+\r
+\r
+/*\r
+// <h> Peripheral Secure Attribution Configuration\r
+*/\r
+\r
+/*\r
+ PNSSET0\r
+*/\r
+/*\r
+// Module 0..31\r
+// <o.9> USBH <0=> Secure <1=> Non-Secure\r
+// <o.13> SD0 <0=> Secure <1=> Non-Secure\r
+// <o.16> EBI <0=> Secure <1=> Non-Secure\r
+// <o.24> PDMA1 <0=> Secure <1=> Non-Secure\r
+*/\r
+#define SCU_INIT_PNSSET0_VAL 0x0\r
+/*\r
+ PNSSET1\r
+*/\r
+/*\r
+// Module 0..31\r
+// <o.17> CRC <0=> Secure <1=> Non-Secure\r
+// <o.18> CRPT <0=> Secure <1=> Non-Secure\r
+*/\r
+#define SCU_INIT_PNSSET1_VAL 0x0\r
+/*\r
+ PNSSET2\r
+*/\r
+/*\r
+// Module 0..31\r
+// <o.1> RTC <0=> Secure <1=> Non-Secure\r
+// <o.3> EADC <0=> Secure <1=> Non-Secure\r
+// <o.5> ACMP01 <0=> Secure <1=> Non-Secure\r
+//\r
+// <o.7> DAC <0=> Secure <1=> Non-Secure\r
+// <o.8> I2S0 <0=> Secure <1=> Non-Secure\r
+// <o.13> OTG <0=> Secure <1=> Non-Secure\r
+// <o.17> TMR23 <0=> Secure <1=> Non-Secure\r
+// <h> EPWM\r
+// <o.24> EPWM0 <0=> Secure <1=> Non-Secure\r
+// <o.25> EPWM1 <0=> Secure <1=> Non-Secure\r
+// <o.26> BPWM0 <0=> Secure <1=> Non-Secure\r
+// <o.27> BPWM1 <0=> Secure <1=> Non-Secure\r
+// </h>\r
+*/\r
+#define SCU_INIT_PNSSET2_VAL 0x0\r
+/*\r
+ PNSSET3\r
+*/\r
+/*\r
+// Module 0..31\r
+// <h> SPI\r
+// <o.0> SPI0 <0=> Secure <1=> Non-Secure\r
+// <o.1> SPI1 <0=> Secure <1=> Non-Secure\r
+// <o.2> SPI2 <0=> Secure <1=> Non-Secure\r
+// <o.3> SPI3 <0=> Secure <1=> Non-Secure\r
+// <o.4> SPI4 <0=> Secure <1=> Non-Secure\r
+// <o.5> SPI5 <0=> Secure <1=> Non-Secure\r
+// </h>\r
+// <h> UART\r
+// <o.16> UART0 <0=> Secure <1=> Non-Secure\r
+// <o.17> UART1 <0=> Secure <1=> Non-Secure\r
+// <o.18> UART2 <0=> Secure <1=> Non-Secure\r
+// <o.19> UART3 <0=> Secure <1=> Non-Secure\r
+// <o.20> UART4 <0=> Secure <1=> Non-Secure\r
+// <o.21> UART5 <0=> Secure <1=> Non-Secure\r
+// </h>\r
+*/\r
+#define SCU_INIT_PNSSET3_VAL 0x0\r
+/*\r
+ PNSSET4\r
+*/\r
+/*\r
+// Module 0..31\r
+// <h> I2C\r
+// <o.0> I2C0 <0=> Secure <1=> Non-Secure\r
+// <o.1> I2C1 <0=> Secure <1=> Non-Secure\r
+// <o.2> I2C2 <0=> Secure <1=> Non-Secure\r
+// </h>\r
+// <h> Smart Card\r
+// <o.16> SC0 <0=> Secure <1=> Non-Secure\r
+// <o.17> SC1 <0=> Secure <1=> Non-Secure\r
+// <o.18> SC2 <0=> Secure <1=> Non-Secure\r
+// </h>\r
+*/\r
+#define SCU_INIT_PNSSET4_VAL 0x0\r
+/*\r
+ PNSSET5\r
+*/\r
+/*\r
+// Module 0..31\r
+// <o.0> CAN0 <0=> Secure <1=> Non-Secure\r
+// <h> QEI\r
+// <o.16> QEI0 <0=> Secure <1=> Non-Secure\r
+// <o.17> QEI1 <0=> Secure <1=> Non-Secure\r
+// </h>\r
+// <h> ECAP\r
+// <o.20> ECAP0 <0=> Secure <1=> Non-Secure\r
+// <o.21> ECAP1 <0=> Secure <1=> Non-Secure\r
+// </h>\r
+// <o.23> DSRC <0=> Secure <1=> Non-Secure\r
+//\r
+// <o.25> TRNG <0=> Secure <1=> Non-Secure\r
+*/\r
+#define SCU_INIT_PNSSET5_VAL 0x0\r
+/*\r
+ PNSSET6\r
+*/\r
+/*\r
+// Module 0..31\r
+// <o.0> USBD <0=> Secure <1=> Non-Secure\r
+// <h> USCI\r
+// <o.16> USCI0 <0=> Secure <1=> Non-Secure\r
+// <o.17> USCI1 <0=> Secure <1=> Non-Secure\r
+// </h>\r
+*/\r
+#define SCU_INIT_PNSSET6_VAL 0x0\r
+/*\r
+// </h>\r
+*/\r
+\r
+\r
+\r
+/*\r
+// <h> GPIO Secure Attribution Configuration\r
+*/\r
+\r
+/*\r
+ IONSSET\r
+*/\r
+/*\r
+// Bit 0..31\r
+// <o.0> PA <0=> Secure <1=> Non-Secure\r
+// <o.1> PB <0=> Secure <1=> Non-Secure\r
+// <o.2> PC <0=> Secure <1=> Non-Secure\r
+// <o.3> PD <0=> Secure <1=> Non-Secure\r
+// <o.4> PE <0=> Secure <1=> Non-Secure\r
+// <o.5> PF <0=> Secure <1=> Non-Secure\r
+// <o.6> PG <0=> Secure <1=> Non-Secure\r
+// <o.7> PH <0=> Secure <1=> Non-Secure\r
+*/\r
+#define SCU_INIT_IONSSET_VAL 0x0\r
+/*\r
+// </h>\r
+*/\r
+\r
+\r
+\r
+/**\r
+ \brief Setup SCU Configuration Unit\r
+ \details\r
+\r
+ */\r
+__STATIC_INLINE void SCU_Setup(void)\r
+{\r
+ int32_t i;\r
+\r
+ SCU->PNSSET[0] = SCU_INIT_PNSSET0_VAL;\r
+ SCU->PNSSET[1] = SCU_INIT_PNSSET1_VAL;\r
+ SCU->PNSSET[2] = SCU_INIT_PNSSET2_VAL;\r
+ SCU->PNSSET[3] = SCU_INIT_PNSSET3_VAL;\r
+ SCU->PNSSET[4] = SCU_INIT_PNSSET4_VAL;\r
+ SCU->PNSSET[5] = SCU_INIT_PNSSET5_VAL;\r
+ SCU->PNSSET[6] = SCU_INIT_PNSSET6_VAL;\r
+\r
+ SCU->IONSSET = SCU_INIT_IONSSET_VAL;\r
+\r
+ /* Set Non-secure SRAM */\r
+ for(i = 11; i >= SCU_SECURE_SRAM_SIZE / 8192; i--)\r
+ {\r
+ SCU->SRAMNSSET |= (1U << i);\r
+ }\r
+\r
+\r
+}\r
+\r
+\r
+/* ---------------------------------------------------------------------------------------------------- */\r
+\r
+/*\r
+// <e>Secure Attribute Unit (SAU) Control\r
+*/\r
+#define SAU_INIT_CTRL 1\r
+\r
+/*\r
+// <q> Enable SAU\r
+// <i> To enable Secure Attribute Unit (SAU).\r
+*/\r
+#define SAU_INIT_CTRL_ENABLE 1\r
+\r
+/*\r
+// <o> All Memory Attribute When SAU is disabled\r
+// <0=> All Memory is Secure\r
+// <1=> All Memory is Non-Secure\r
+// <i> To set the ALLNS bit in SAU CTRL.\r
+// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\r
+*/\r
+#define SAU_INIT_CTRL_ALLNS 0\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+\r
+/*\r
+// <h>Enable and Set Secure/Non-Secure region\r
+*/\r
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */\r
+\r
+/*\r
+// <e>SAU Region 0\r
+// <i> Setup SAU Region 0\r
+*/\r
+#define SAU_INIT_REGION0 0\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START0 0x0003F000 /* start address of SAU region 0 */\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END0 0x0003FFFF /* end address of SAU region 0 */\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC0 1\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>SAU Region 1\r
+// <i> Setup SAU Region 1\r
+*/\r
+#define SAU_INIT_REGION1 0\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START1 0x10040000\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END1 0x1007FFFF\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC1 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>SAU Region 2\r
+// <i> Setup SAU Region 2\r
+*/\r
+#define SAU_INIT_REGION2 0\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START2 0x2000F000\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END2 0x2000FFFF\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC2 1\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>SAU Region 3\r
+// <i> Setup SAU Region 3\r
+*/\r
+#define SAU_INIT_REGION3 1\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START3 0x3f000\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END3 0x3ffff\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC3 1\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+ <e>SAU Region 4\r
+ <i> Setup SAU Region 4\r
+*/\r
+#define SAU_INIT_REGION4 1\r
+/*\r
+ <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START4 FMC_NON_SECURE_BASE /* start address of SAU region 4 */\r
+\r
+/*\r
+ <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END4 0x1007FFFF /* end address of SAU region 4 */\r
+\r
+/*\r
+ <o>Region is\r
+ <0=>Non-Secure\r
+ <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC4 0\r
+/*\r
+ </e>\r
+*/\r
+\r
+/*\r
+ <e>SAU Region 5\r
+ <i> Setup SAU Region 5\r
+*/\r
+#define SAU_INIT_REGION5 1\r
+\r
+/*\r
+ <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START5 0x00807E00\r
+\r
+/*\r
+ <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END5 0x00807FFF\r
+\r
+/*\r
+ <o>Region is\r
+ <0=>Non-Secure\r
+ <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC5 1\r
+/*\r
+ </e>\r
+*/\r
+\r
+/*\r
+ <e>SAU Region 6\r
+ <i> Setup SAU Region 6\r
+*/\r
+#define SAU_INIT_REGION6 1\r
+\r
+/*\r
+ <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START6 NON_SECURE_SRAM_BASE\r
+\r
+/*\r
+ <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END6 0x30017FFF\r
+\r
+/*\r
+ <o>Region is\r
+ <0=>Non-Secure\r
+ <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC6 0\r
+/*\r
+ </e>\r
+*/\r
+\r
+/*\r
+ <e>SAU Region 7\r
+ <i> Setup SAU Region 7\r
+*/\r
+#define SAU_INIT_REGION7 1\r
+\r
+/*\r
+ <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START7 0x50000000\r
+\r
+/*\r
+ <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END7 0x5FFFFFFF\r
+\r
+/*\r
+ <o>Region is\r
+ <0=>Non-Secure\r
+ <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC7 0\r
+/*\r
+ </e>\r
+*/\r
+\r
+/*\r
+// </h>\r
+*/\r
+\r
+/*\r
+// <e>Setup behavior of Sleep and Exception Handling\r
+*/\r
+#define SCB_CSR_AIRCR_INIT 1\r
+\r
+/*\r
+// <o> Deep Sleep can be enabled by\r
+// <0=>Secure and Non-Secure state\r
+// <1=>Secure state only\r
+// <i> Value for SCB->CSR register bit DEEPSLEEPS\r
+*/\r
+#define SCB_CSR_DEEPSLEEPS_VAL 0\r
+\r
+/*\r
+// <o>System reset request accessible from\r
+// <0=> Secure and Non-Secure state\r
+// <1=> Secure state only\r
+// <i> Value for SCB->AIRCR register bit SYSRESETREQS\r
+*/\r
+#define SCB_AIRCR_SYSRESETREQS_VAL 0\r
+\r
+/*\r
+// <o>Priority of Non-Secure exceptions is\r
+// <0=> Not altered\r
+// <1=> Lowered to 0x80-0xFF\r
+// <i> Value for SCB->AIRCR register bit PRIS\r
+*/\r
+#define SCB_AIRCR_PRIS_VAL 1\r
+\r
+/*\r
+// <o>BusFault, HardFault, and NMI target\r
+// <0=> Secure state\r
+// <1=> Non-Secure state\r
+// <i> Value for SCB->AIRCR register bit BFHFNMINS\r
+*/\r
+#define SCB_AIRCR_BFHFNMINS_VAL 1\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+\r
+/*\r
+// <h>Assign Interrupt to Secure or Non-secure Vector\r
+*/\r
+\r
+\r
+/*\r
+ Initialize ITNS 0 (Interrupts 0..31)\r
+*/\r
+#define NVIC_INIT_ITNS0 1\r
+/*\r
+// BODOUT Always secure\r
+// IRC Always secure\r
+// PWRWU_ Always secure\r
+// SRAM_PERR Always secure\r
+// CLKFAIL Always secure\r
+\r
+// <o.6> RTC <0=> Secure <1=> Non-Secure\r
+// <o.7> TAMPER <0=> Secure <1=> Non-Secure\r
+// WDT Always secure\r
+// WWDT Always secure\r
+// <h> EINT\r
+// <o.10> EINT0 <0=> Secure <1=> Non-Secure\r
+// <o.11> EINT1 <0=> Secure <1=> Non-Secure\r
+// <o.12> EINT2 <0=> Secure <1=> Non-Secure\r
+// <o.13> EINT3 <0=> Secure <1=> Non-Secure\r
+// <o.14> EINT4 <0=> Secure <1=> Non-Secure\r
+// <o.15> EINT5 <0=> Secure <1=> Non-Secure\r
+// </h>\r
+// <h> GPIO\r
+// <o.16> GPA <0=> Secure <1=> Non-Secure\r
+// <o.17> GPB <0=> Secure <1=> Non-Secure\r
+// <o.18> GPC <0=> Secure <1=> Non-Secure\r
+// <o.19> GPD <0=> Secure <1=> Non-Secure\r
+// <o.20> GPE <0=> Secure <1=> Non-Secure\r
+// <o.21> GPF <0=> Secure <1=> Non-Secure\r
+// </h>\r
+// <o.22> SPI0 <0=> Secure <1=> Non-Secure\r
+// <o.23> SPI1 <0=> Secure <1=> Non-Secure\r
+// <h> EPWM\r
+// <o.24> BRAKE0 <0=> Secure <1=> Non-Secure\r
+// <o.25> EPWM0_P0 <0=> Secure <1=> Non-Secure\r
+// <o.26> EPWM0_P1 <0=> Secure <1=> Non-Secure\r
+// <o.27> EPWM0_P2 <0=> Secure <1=> Non-Secure\r
+// <o.28> BRAKE1 <0=> Secure <1=> Non-Secure\r
+// <o.29> EPWM1_P0 <0=> Secure <1=> Non-Secure\r
+// <o.30> EPWM1_P1 <0=> Secure <1=> Non-Secure\r
+// <o.31> EPWM1_P2 <0=> Secure <1=> Non-Secure\r
+// </h>\r
+//\r
+*/\r
+#define NVIC_INIT_ITNS0_VAL 0x0\r
+\r
+/*\r
+ Initialize ITNS 1 (Interrupts 0..31)\r
+*/\r
+#define NVIC_INIT_ITNS1 1\r
+/*\r
+// <h> TIMER\r
+// TMR0 Always secure\r
+// TMR1 Always secure\r
+// <o.2> TMR2 <0=> Secure <1=> Non-Secure\r
+// <o.3> TMR3 <0=> Secure <1=> Non-Secure\r
+// </h>\r
+// <o.4> UART0 <0=> Secure <1=> Non-Secure\r
+// <o.5> UART1 <0=> Secure <1=> Non-Secure\r
+// <o.6> I2C0 <0=> Secure <1=> Non-Secure\r
+// <o.7> I2C1 <0=> Secure <1=> Non-Secure\r
+// PDMA0 is secure only\r
+// <o.9> DAC <0=> Secure <1=> Non-Secure\r
+// <o.10> EADC0 <0=> Secure <1=> Non-Secure\r
+// <o.11> EADC1 <0=> Secure <1=> Non-Secure\r
+// <o.12> ACMP01 <0=> Secure <1=> Non-Secure\r
+\r
+// <o.14> EADC2 <0=> Secure <1=> Non-Secure\r
+// <o.15> EADC3 <0=> Secure <1=> Non-Secure\r
+// <o.16> UART2 <0=> Secure <1=> Non-Secure\r
+// <o.17> UART3 <0=> Secure <1=> Non-Secure\r
+\r
+// <o.19> SPI2 <0=> Secure <1=> Non-Secure\r
+// <o.20> SPI3 <0=> Secure <1=> Non-Secure\r
+// <o.21> USBD <0=> Secure <1=> Non-Secure\r
+// <o.22> USBH <0=> Secure <1=> Non-Secure\r
+// <o.23> USBOTG <0=> Secure <1=> Non-Secure\r
+// <o.24> CAN0 <0=> Secure <1=> Non-Secure\r
+\r
+// <h> Smart Card\r
+// <o.26> SC0 <0=> Secure <1=> Non-Secure\r
+// <o.27> SC1 <0=> Secure <1=> Non-Secure\r
+// <o.28> SC2 <0=> Secure <1=> Non-Secure\r
+// </h>\r
+\r
+// <o.30> SPI4 <0=> Secure <1=> Non-Secure\r
+\r
+//\r
+*/\r
+#define NVIC_INIT_ITNS1_VAL 0x20\r
+\r
+/*\r
+ Initialize ITNS 2 (Interrupts 0..31)\r
+*/\r
+#define NVIC_INIT_ITNS2 1\r
+/*\r
+// <o.0> SDH0 <0=> Secure <1=> Non-Secure\r
+\r
+\r
+\r
+// <o.4> I2S0 <0=> Secure <1=> Non-Secure\r
+\r
+//\r
+// <o.7> CRYPTO <0=> Secure <1=> Non-Secure\r
+// <o.8> GPG <0=> Secure <1=> Non-Secure\r
+// <o.9> EINT6 <0=> Secure <1=> Non-Secure\r
+// <o.10> UART4 <0=> Secure <1=> Non-Secure\r
+// <o.11> UART5 <0=> Secure <1=> Non-Secure\r
+// <o.12> USCI0 <0=> Secure <1=> Non-Secure\r
+// <o.13> USCI1 <0=> Secure <1=> Non-Secure\r
+// <o.14> BPWM0 <0=> Secure <1=> Non-Secure\r
+// <o.15> BPWM1 <0=> Secure <1=> Non-Secure\r
+\r
+\r
+// <o.18> I2C2 <0=> Secure <1=> Non-Secure\r
+\r
+// <o.20> QEI0 <0=> Secure <1=> Non-Secure\r
+// <o.21> QEI1 <0=> Secure <1=> Non-Secure\r
+// <o.22> ECAP0 <0=> Secure <1=> Non-Secure\r
+// <o.23> ECAP1 <0=> Secure <1=> Non-Secure\r
+// <o.24> GPH <0=> Secure <1=> Non-Secure\r
+// <o.25> EINT7 <0=> Secure <1=> Non-Secure\r
+\r
+\r
+// <o.28> USBH <0=> Secure <1=> Non-Secure\r
+\r
+\r
+\r
+//\r
+*/\r
+#define NVIC_INIT_ITNS2_VAL 0x0\r
+\r
+\r
+/*\r
+ Initialize ITNS 3 (Interrupts 0..31)\r
+*/\r
+#define NVIC_INIT_ITNS3 1\r
+/*\r
+// <o.0> SPI5 <0=> Secure <1=> Non-Secure\r
+// <o.1> DSRC <0=> Secure <1=> Non-Secure\r
+// <o.2> PDMA1 <0=> Secure <1=> Non-Secure\r
+// SCU Always secure\r
+//\r
+// <o.5> TRNG <0=> Secure <1=> Non-Secure\r
+*/\r
+#define NVIC_INIT_ITNS3_VAL 0x0\r
+\r
+\r
+\r
+/*\r
+// </h>\r
+*/\r
+\r
+\r
+\r
+/*\r
+ max 128 SAU regions.\r
+ SAU regions are defined in partition.h\r
+ */\r
+\r
+#define SAU_INIT_REGION(n) \\r
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \\r
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \\r
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \\r
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U\r
+\r
+/**\r
+ \brief Setup a SAU Region\r
+ \details Writes the region information contained in SAU_Region to the\r
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Setup(void)\r
+{\r
+\r
+#if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)\r
+\r
+#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\r
+ SAU_INIT_REGION(0);\r
+#endif\r
+\r
+#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\r
+ SAU_INIT_REGION(1);\r
+#endif\r
+\r
+#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\r
+ SAU_INIT_REGION(2);\r
+#endif\r
+\r
+#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\r
+ SAU_INIT_REGION(3);\r
+#endif\r
+\r
+#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\r
+ SAU_INIT_REGION(4);\r
+#endif\r
+\r
+#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\r
+ SAU_INIT_REGION(5);\r
+#endif\r
+\r
+#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\r
+ SAU_INIT_REGION(6);\r
+#endif\r
+\r
+#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\r
+ SAU_INIT_REGION(7);\r
+#endif\r
+\r
+ /* repeat this for all possible SAU regions */\r
+\r
+\r
+#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\r
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\r
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;\r
+#endif\r
+\r
+#endif /* defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U) */\r
+\r
+#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\r
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) |\r
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);\r
+\r
+// SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) |\r
+// ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\r
+// ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |\r
+// ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);\r
+\r
+ SCB->AIRCR = (0x05FA << 16) |\r
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\r
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |\r
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);\r
+\r
+\r
+\r
+#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\r
+\r
+#if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)\r
+ SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk)) |\r
+ ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);\r
+#endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */\r
+\r
+#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\r
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\r
+#endif\r
+\r
+#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\r
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\r
+#endif\r
+\r
+#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\r
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\r
+#endif\r
+\r
+#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\r
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\r
+#endif\r
+\r
+\r
+ /* repeat this for all possible ITNS elements */\r
+\r
+}\r
+\r
+\r
+#endif /* PARTITION_M2351 */\r
+\r
_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_)\r
\r
_COMPILERS_ = ['GCC', 'IAR']\r
-_ARCH_NS_ = ['ARM_CM33', 'ARM_CM33_NTZ']\r
-_ARCH_S_ = ['ARM_CM33']\r
+_ARCH_NS_ = ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']\r
+_ARCH_S_ = ['ARM_CM33', 'ARM_CM23']\r
+\r
+_SUPPORTED_CONFIGS_ = {\r
+ 'GCC' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ'],\r
+ 'IAR' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']\r
+ }\r
\r
# Files to be complied in the Secure Project\r
_SECURE_FILE_PATHS_ = [\r
os.path.join('non_secure', 'portable', '_COMPILER_ARCH_')\r
]\r
\r
+\r
+def is_supported_config(compiler, arch):\r
+ return arch in _SUPPORTED_CONFIGS_[compiler]\r
+\r
+\r
def copy_files_in_dir(src_abs_path, dst_abs_path):\r
for src_file in os.listdir(src_abs_path):\r
src_file_abs_path = os.path.join(src_abs_path, src_file)\r
# Copy Secure Files\r
for compiler in _COMPILERS_:\r
for arch in _ARCH_S_:\r
- copy_files_for_compiler_and_arch(compiler, arch, _SECURE_FILE_PATHS_, 'secure')\r
+ if is_supported_config(compiler, arch):\r
+ copy_files_for_compiler_and_arch(compiler, arch, _SECURE_FILE_PATHS_, 'secure')\r
\r
# Copy Non-Secure Files\r
for compiler in _COMPILERS_:\r
for arch in _ARCH_NS_:\r
- copy_files_for_compiler_and_arch(compiler, arch, _NONSECURE_FILE_PATHS_, 'non_secure')\r
+ if is_supported_config(compiler, arch):\r
+ copy_files_for_compiler_and_arch(compiler, arch, _NONSECURE_FILE_PATHS_, 'non_secure')\r
\r
\r
def main():\r
extern uint32_t * __privileged_functions_start__;\r
extern uint32_t * __privileged_functions_end__;\r
extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ extern uint32_t * __unprivileged_flash_start__;\r
extern uint32_t * __unprivileged_flash_end__;\r
extern uint32_t * __privileged_sram_start__;\r
extern uint32_t * __privileged_sram_end__;\r
extern uint32_t __privileged_functions_start__[];\r
extern uint32_t __privileged_functions_end__[];\r
extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ extern uint32_t __unprivileged_flash_start__[];\r
extern uint32_t __unprivileged_flash_end__[];\r
extern uint32_t __privileged_sram_start__[];\r
extern uint32_t __privileged_sram_end__[];\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
- /* Setup unprivileged flash and system calls flash as Read Only by\r
- * both privileged and unprivileged tasks. All tasks can read it but\r
- * no-one can modify. */\r
+ /* Setup unprivileged flash as Read Only by both privileged and\r
+ * unprivileged tasks. All tasks can read it but no-one can modify. */\r
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
( portMPU_REGION_NON_SHAREABLE ) |\r
( portMPU_REGION_READ_ONLY );\r
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
+ /* Setup unprivileged syscalls flash as Read Only by both privileged\r
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
/* Setup RAM containing kernel data for privileged access only. */\r
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
- /* By default allow everything to access the general peripherals.\r
- * The system peripherals and registers are protected. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX1 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
/* Enable mem fault. */\r
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
+ * is defined correctly and privileged functions are placed in correct sections. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
+ * header files. */\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
+#endif\r
+\r
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r5, #1 \n" /* r5 = 1. */\r
+ " bics r4, r5 \n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " movs r5, #4 \n" /* r5 = 4. */\r
+ " str r5, [r2] \n" /* Program RNR = 4. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read first set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write first set of RBAR/RLAR registers. */\r
+ " movs r5, #5 \n" /* r5 = 5. */\r
+ " str r5, [r2] \n" /* Program RNR = 5. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read second set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write second set of RBAR/RLAR registers. */\r
+ " movs r5, #6 \n" /* r5 = 6. */\r
+ " str r5, [r2] \n" /* Program RNR = 6. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read third set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write third set of RBAR/RLAR registers. */\r
+ " movs r5, #7 \n" /* r5 = 7. */\r
+ " str r5, [r2] \n" /* Program RNR = 7. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read fourth set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write fourth set of RBAR/RLAR registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r5, #1 \n" /* r5 = 1. */\r
+ " orrs r4, r5 \n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ " ldr r5, xSecureContextConst2 \n"\r
+ " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r3 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r4 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ " ldr r4, xSecureContextConst2 \n"\r
+ " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ "xSecureContextConst2: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " movs r1, #1 \n" /* r1 = 1. */\r
+ " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\r
+ " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */\r
+ " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " running_privileged: \n"\r
+ " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " movs r1, #1 \n" /* r1 = 1. */\r
+ " bics r0, r1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " movs r1, #1 \n" /* r1 = 1. */\r
+ " orrs r0, r1 \n" /* r0 = r0 | r1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " .extern SecureContext_SaveContext \n"\r
+ " .extern SecureContext_LoadContext \n"\r
+ " \n"\r
+ " mrs r1, psp \n" /* Read PSP in r1. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+ " \n"\r
+ " cbz r0, save_ns_context \n" /* No secure context to save. */\r
+ " push {r0-r2, r14} \n"\r
+ " bl SecureContext_SaveContext \n"\r
+ " pop {r0-r3} \n" /* LR is now in r3. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " b select_next_task \n"\r
+ " \n"\r
+ " save_ns_context: \n"\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " adds r1, r1, #16 \n" /* r1 = r1 + 16. */\r
+ " stmia r1!, {r4-r7} \n" /* Store the low registers that are not saved automatically. */\r
+ " mov r4, r8 \n" /* r4 = r8. */\r
+ " mov r5, r9 \n" /* r5 = r9. */\r
+ " mov r6, r10 \n" /* r6 = r10. */\r
+ " mov r7, r11 \n" /* r7 = r11. */\r
+ " stmia r1!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " subs r1, r1, #48 \n" /* r1 = r1 - 48. */\r
+ " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r7} \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */\r
+ " mov r4, r8 \n" /* r4 = r8. */\r
+ " mov r5, r9 \n" /* r5 = r9. */\r
+ " mov r6, r10 \n" /* r6 = r10. */\r
+ " mov r7, r11 \n" /* r7 = r11. */\r
+ " stmia r1!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " select_next_task: \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r5, #1 \n" /* r5 = 1. */\r
+ " bics r4, r5 \n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " movs r5, #4 \n" /* r5 = 4. */\r
+ " str r5, [r2] \n" /* Program RNR = 4. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read first set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write first set of RBAR/RLAR registers. */\r
+ " movs r5, #5 \n" /* r5 = 5. */\r
+ " str r5, [r2] \n" /* Program RNR = 5. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read second set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write second set of RBAR/RLAR registers. */\r
+ " movs r5, #6 \n" /* r5 = 6. */\r
+ " str r5, [r2] \n" /* Program RNR = 6. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read third set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write third set of RBAR/RLAR registers. */\r
+ " movs r5, #7 \n" /* r5 = 7. */\r
+ " str r5, [r2] \n" /* Program RNR = 7. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read fourth set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write fourth set of RBAR/RLAR registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r5, #1 \n" /* r5 = 1. */\r
+ " orrs r4, r5 \n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r3 \n" /* Restore the CONTROL register value for the task. */\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r4} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r4} \n"\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #else /* configENABLE_MPU */\r
+ " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r3} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r3} \n"\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " restore_ns_context: \n"\r
+ " adds r1, r1, #16 \n" /* Move to the high registers. */\r
+ " ldmia r1!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */\r
+ " mov r8, r4 \n" /* r8 = r4. */\r
+ " mov r9, r5 \n" /* r9 = r5. */\r
+ " mov r10, r6 \n" /* r10 = r6. */\r
+ " mov r11, r7 \n" /* r11 = r7. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " subs r1, r1, #32 \n" /* Go back to the low registers. */\r
+ " ldmia r1!, {r4-r7} \n" /* Restore the low registers that are not automatically restored. */\r
+ " bx lr \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "xSecureContextConst: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst: .word 0xe000ed94 \n"\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " movs r0, #4 \n"\r
+ " mov r1, lr \n"\r
+ " tst r0, r1 \n"\r
+ " beq stacking_used_msp \n"\r
+ " mrs r0, psp \n"\r
+ " ldr r2, svchandler_address_const \n"\r
+ " bx r2 \n"\r
+ " stacking_used_msp: \n"\r
+ " mrs r0, msp \n"\r
+ " ldr r2, svchandler_address_const \n"\r
+ " bx r2 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " svc %0 \n" /* Secure context is allocated in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */\r
+ " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */\r
+ " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */\r
+ " beq free_secure_context \n"\r
+ " bx lr \n" /* There is no secure context (xSecureContext is NULL). */\r
+ " free_secure_context: \n"\r
+ " svc %0 \n" /* Secure context is freed in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
+ * is defined correctly and privileged functions are placed in correct sections. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
+ * header files. */\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
+#endif\r
+\r
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r4, #1 \n" /* r4 = 1. */\r
+ " bics r3, r4 \n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\r
+ " str r3, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r1] \n" /* r4 = *r1 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read first set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write first set of RBAR/RLAR registers. */\r
+ " movs r4, #5 \n" /* r4 = 5. */\r
+ " str r4, [r2] \n" /* Program RNR = 5. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read second set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write second set of RBAR/RLAR registers. */\r
+ " movs r4, #6 \n" /* r4 = 6. */\r
+ " str r4, [r2] \n" /* Program RNR = 6. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read third set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write third set of RBAR/RLAR registers. */\r
+ " movs r4, #7 \n" /* r4 = 7. */\r
+ " str r4, [r2] \n" /* Program RNR = 7. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read fourth set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write fourth set of RBAR/RLAR registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r4, #1 \n" /* r4 = 1. */\r
+ " orrs r3, r4 \n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\r
+ " str r3, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r2 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r2 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " movs r1, #1 \n" /* r1 = 1. */\r
+ " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\r
+ " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */\r
+ " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " running_privileged: \n"\r
+ " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " movs r1, #1 \n" /* r1 = 1. */\r
+ " bics r0, r1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " movs r1, #1 \n" /* r1 = 1. */\r
+ " orrs r0, r1 \n" /* r0 = r0 | r1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r0, psp \n" /* Read PSP in r0. */\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r0, r0, #44 \n" /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r1, psplim \n" /* r1 = PSPLIM. */\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r0!, {r1-r7} \n" /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */\r
+ " mov r4, r8 \n" /* r4 = r8. */\r
+ " mov r5, r9 \n" /* r5 = r9. */\r
+ " mov r6, r10 \n" /* r6 = r10. */\r
+ " mov r7, r11 \n" /* r7 = r11. */\r
+ " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */\r
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r0!, {r2-r7} \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */\r
+ " mov r4, r8 \n" /* r4 = r8. */\r
+ " mov r5, r9 \n" /* r5 = r9. */\r
+ " mov r6, r10 \n" /* r6 = r10. */\r
+ " mov r7, r11 \n" /* r7 = r11. */\r
+ " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r4, #1 \n" /* r4 = 1. */\r
+ " bics r3, r4 \n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\r
+ " str r3, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r1] \n" /* r4 = *r1 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read first set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write first set of RBAR/RLAR registers. */\r
+ " movs r4, #5 \n" /* r4 = 5. */\r
+ " str r4, [r2] \n" /* Program RNR = 5. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read second set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write second set of RBAR/RLAR registers. */\r
+ " movs r4, #6 \n" /* r4 = 6. */\r
+ " str r4, [r2] \n" /* Program RNR = 6. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read third set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write third set of RBAR/RLAR registers. */\r
+ " movs r4, #7 \n" /* r4 = 7. */\r
+ " str r4, [r2] \n" /* Program RNR = 7. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read fourth set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write fourth set of RBAR/RLAR registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r4, #1 \n" /* r4 = 1. */\r
+ " orrs r3, r4 \n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\r
+ " str r3, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r0, r0, #28 \n" /* Move to the high registers. */\r
+ " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */\r
+ " mov r8, r4 \n" /* r8 = r4. */\r
+ " mov r9, r5 \n" /* r9 = r5. */\r
+ " mov r10, r6 \n" /* r10 = r6. */\r
+ " mov r11, r7 \n" /* r11 = r7. */\r
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
+ " subs r0, r0, #44 \n" /* Move to the starting of the saved context. */\r
+ " ldmia r0!, {r1-r7} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */\r
+ " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r2 \n" /* Restore the CONTROL register value for the task. */\r
+ " bx r3 \n"\r
+ #else /* configENABLE_MPU */\r
+ " adds r0, r0, #24 \n" /* Move to the high registers. */\r
+ " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */\r
+ " mov r8, r4 \n" /* r8 = r4. */\r
+ " mov r9, r5 \n" /* r9 = r5. */\r
+ " mov r10, r6 \n" /* r10 = r6. */\r
+ " mov r11, r7 \n" /* r11 = r7. */\r
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
+ " subs r0, r0, #40 \n" /* Move to the starting of the saved context. */\r
+ " ldmia r0!, {r2-r7} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " bx r3 \n"\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst: .word 0xe000ed94 \n"\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " movs r0, #4 \n"\r
+ " mov r1, lr \n"\r
+ " tst r0, r1 \n"\r
+ " beq stacking_used_msp \n"\r
+ " mrs r0, psp \n"\r
+ " ldr r2, svchandler_address_const \n"\r
+ " bx r2 \n"\r
+ " stacking_used_msp: \n"\r
+ " mrs r0, msp \n"\r
+ " ldr r2, svchandler_address_const \n"\r
+ " bx r2 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
/* Standard includes. */\r
#include <stdint.h>\r
\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
+ * is defined correctly and privileged functions are placed in correct sections. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
/* Portasm includes. */\r
#include "portasm.h"\r
\r
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
+ * header files. */\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
" ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
" adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
" ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
" ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
" ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
" stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
"pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
"xSecureContextConst2: .word xSecureContext \n"\r
#if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"\r
"xMAIR0Const2: .word 0xe000edc0 \n"\r
"xRNRConst2: .word 0xe000ed98 \n"\r
"xRBARConst2: .word 0xe000ed9c \n"\r
" ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
" adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
" ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
" ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
" ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
" stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
"pxCurrentTCBConst: .word pxCurrentTCB \n"\r
"xSecureContextConst: .word xSecureContext \n"\r
#if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst: .word 0xe000ed94 \n"\r
"xMAIR0Const: .word 0xe000edc0 \n"\r
"xRNRConst: .word 0xe000ed98 \n"\r
"xRBARConst: .word 0xe000ed9c \n"\r
/* Standard includes. */\r
#include <stdint.h>\r
\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
+ * is defined correctly and privileged functions are placed in correct sections. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
/* Portasm includes. */\r
#include "portasm.h"\r
\r
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
+ * header files. */\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
" ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
" adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
" ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
" ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
" ldmia r1!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
" stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
" .align 4 \n"\r
"pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
#if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"\r
"xMAIR0Const2: .word 0xe000edc0 \n"\r
"xRNRConst2: .word 0xe000ed98 \n"\r
"xRBARConst2: .word 0xe000ed9c \n"\r
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
" adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
" ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
" ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
" ldmia r1!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
" stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
" \n"\r
" .align 4 \n"\r
"pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst: .word 0xe000ed94 \n"\r
"xMAIR0Const: .word 0xe000edc0 \n"\r
"xRNRConst: .word 0xe000ed98 \n"\r
"xRBARConst: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
);\r
}\r
/*-----------------------------------------------------------*/\r
{\r
__asm volatile\r
(\r
- " tst lr, #4 \n"\r
- " ite eq \n"\r
- " mrseq r0, msp \n"\r
- " mrsne r0, psp \n"\r
- " ldr r1, svchandler_address_const \n"\r
- " bx r1 \n"\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, svchandler_address_const \n"\r
+ " bx r1 \n"\r
" \n"\r
- " .align 4 \n"\r
+ " .align 4 \n"\r
"svchandler_address_const: .word vPortSVCHandler_C \n"\r
);\r
}\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ EXTERN pxCurrentTCB\r
+ EXTERN xSecureContext\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+ EXTERN SecureContext_SaveContext\r
+ EXTERN SecureContext_LoadContext\r
+\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vPortAllocateSecureContext\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
+ PUBLIC vPortFreeSecureContext\r
+\r
+#if ( configENABLE_FPU == 1 )\r
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/*---------------- Unprivileged Functions -------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+xIsPrivileged:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ movs r1, #1 /* r1 = 1. */\r
+ tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\r
+ beq running_privileged /* If the result of previous AND operation was 0, branch. */\r
+ movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
+ running_privileged:\r
+ movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vResetPrivilege:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ movs r1, #1 /* r1 = 1. */\r
+ orrs r0, r1 /* r0 = r0 | r1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vPortAllocateSecureContext:\r
+ svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/*----------------- Privileged Functions --------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+vRestoreContextOfFirstTask:\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r5, #1 /* r5 = 1. */\r
+ bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\r
+ str r4, [r2] /* Disable MPU. */\r
+\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ movs r5, #4 /* r5 = 4. */\r
+ str r5, [r2] /* Program RNR = 4. */\r
+ ldmia r3!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write first set of RBAR/RLAR registers. */\r
+ movs r5, #5 /* r5 = 5. */\r
+ str r5, [r2] /* Program RNR = 5. */\r
+ ldmia r3!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write second set of RBAR/RLAR registers. */\r
+ movs r5, #6 /* r5 = 6. */\r
+ str r5, [r2] /* Program RNR = 6. */\r
+ ldmia r3!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write third set of RBAR/RLAR registers. */\r
+ movs r5, #7 /* r5 = 7. */\r
+ str r5, [r2] /* Program RNR = 7. */\r
+ ldmia r3!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r5, #1 /* r5 = 1. */\r
+ orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\r
+ str r4, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ ldr r5, =xSecureContext\r
+ str r1, [r5] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ msr control, r3 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r4 /* Finally, branch to EXC_RETURN. */\r
+#else /* configENABLE_MPU */\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ ldr r4, =xSecureContext\r
+ str r1, [r4] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+vRaisePrivilege:\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ movs r1, #1 /* r1 = 1. */\r
+ bics r0, r1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vStartFirstTask:\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+/*-----------------------------------------------------------*/\r
+\r
+ulSetInterruptMaskFromISR:\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+vClearInterruptMaskFromISR:\r
+ msr PRIMASK, r0\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+PendSV_Handler:\r
+ mrs r1, psp /* Read PSP in r1. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+\r
+ cbz r0, save_ns_context /* No secure context to save. */\r
+ push {r0-r2, r14}\r
+ bl SecureContext_SaveContext\r
+ pop {r0-r3} /* LR is now in r3. */\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
+#if ( configENABLE_MPU == 1 )\r
+ subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+#else /* configENABLE_MPU */\r
+ subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+#endif /* configENABLE_MPU */\r
+ b select_next_task\r
+\r
+ save_ns_context:\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
+ #if ( configENABLE_MPU == 1 )\r
+ subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ adds r1, r1, #16 /* r1 = r1 + 16. */\r
+ stmia r1!, {r4-r7} /* Store the low registers that are not saved automatically. */\r
+ mov r4, r8 /* r4 = r8. */\r
+ mov r5, r9 /* r5 = r9. */\r
+ mov r6, r10 /* r6 = r10. */\r
+ mov r7, r11 /* r7 = r11. */\r
+ stmia r1!, {r4-r7} /* Store the high registers that are not saved automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ subs r1, r1, #48 /* r1 = r1 - 48. */\r
+ stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */\r
+ mov r4, r8 /* r4 = r8. */\r
+ mov r5, r9 /* r5 = r9. */\r
+ mov r6, r10 /* r6 = r10. */\r
+ mov r7, r11 /* r7 = r11. */\r
+ stmia r1!, {r4-r7} /* Store the high registers that are not saved automatically. */\r
+ #endif /* configENABLE_MPU */\r
+\r
+ select_next_task:\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
+\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+\r
+ #if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r5, #1 /* r5 = 1. */\r
+ bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\r
+ str r4, [r2] /* Disable MPU. */\r
+\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ movs r5, #4 /* r5 = 4. */\r
+ str r5, [r2] /* Program RNR = 4. */\r
+ ldmia r3!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write first set of RBAR/RLAR registers. */\r
+ movs r5, #5 /* r5 = 5. */\r
+ str r5, [r2] /* Program RNR = 5. */\r
+ ldmia r3!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write second set of RBAR/RLAR registers. */\r
+ movs r5, #6 /* r5 = 6. */\r
+ str r5, [r2] /* Program RNR = 6. */\r
+ ldmia r3!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write third set of RBAR/RLAR registers. */\r
+ movs r5, #7 /* r5 = 7. */\r
+ str r5, [r2] /* Program RNR = 7. */\r
+ ldmia r3!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r5, #1 /* r5 = 1. */\r
+ orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\r
+ str r4, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
+ #endif /* configENABLE_MPU */\r
+\r
+ #if ( configENABLE_MPU == 1 )\r
+ ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r3 /* Restore the CONTROL register value for the task. */\r
+ mov lr, r4 /* LR = r4. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r4}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r4}\r
+ mov lr, r4 /* LR = r4. */\r
+ lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #else /* configENABLE_MPU */\r
+ ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ mov lr, r3 /* LR = r3. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r3}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r3}\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #endif /* configENABLE_MPU */\r
+\r
+ restore_ns_context:\r
+ adds r1, r1, #16 /* Move to the high registers. */\r
+ ldmia r1!, {r4-r7} /* Restore the high registers that are not automatically restored. */\r
+ mov r8, r4 /* r8 = r4. */\r
+ mov r9, r5 /* r9 = r5. */\r
+ mov r10, r6 /* r10 = r6. */\r
+ mov r11, r7 /* r11 = r7. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ subs r1, r1, #32 /* Go back to the low registers. */\r
+ ldmia r1!, {r4-r7} /* Restore the low registers that are not automatically restored. */\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+SVC_Handler:\r
+ movs r0, #4\r
+ mov r1, lr\r
+ tst r0, r1\r
+ beq stacking_used_msp\r
+ mrs r0, psp\r
+ b vPortSVCHandler_C\r
+ stacking_used_msp:\r
+ mrs r0, msp\r
+ b vPortSVCHandler_C\r
+/*-----------------------------------------------------------*/\r
+\r
+vPortFreeSecureContext:\r
+ ldr r1, [r0] /* The first item in the TCB is the top of the stack. */\r
+ ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */\r
+ cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */\r
+ beq free_secure_context\r
+ bx lr /* There is no secure context (xSecureContext is NULL). */\r
+ free_secure_context:\r
+ svc 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ EXTERN pxCurrentTCB\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
+\r
+#if ( configENABLE_FPU == 1 )\r
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/*---------------- Unprivileged Functions -------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+xIsPrivileged:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ movs r1, #1 /* r1 = 1. */\r
+ tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\r
+ beq running_privileged /* If the result of previous AND operation was 0, branch. */\r
+ movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
+ running_privileged:\r
+ movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ bx lr /* Return. */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vResetPrivilege:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ movs r1, #1 /* r1 = 1. */\r
+ orrs r0, r1 /* r0 = r0 | r1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/*----------------- Privileged Functions --------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+vRestoreContextOfFirstTask:\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r4, #1 /* r4 = 1. */\r
+ bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\r
+ str r3, [r2] /* Disable MPU. */\r
+\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */\r
+ movs r4, #5 /* r4 = 5. */\r
+ str r4, [r2] /* Program RNR = 5. */\r
+ ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */\r
+ movs r4, #6 /* r4 = 6. */\r
+ str r4, [r2] /* Program RNR = 6. */\r
+ ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */\r
+ movs r4, #7 /* r4 = 7. */\r
+ str r4, [r2] /* Program RNR = 7. */\r
+ ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r4, #1 /* r4 = 1. */\r
+ orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\r
+ str r3, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ msr control, r2 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
+#else /* configENABLE_MPU */\r
+ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r2 /* Finally, branch to EXC_RETURN. */\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+vRaisePrivilege:\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ movs r1, #1 /* r1 = 1. */\r
+ bics r0, r1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vStartFirstTask:\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+ nop\r
+/*-----------------------------------------------------------*/\r
+\r
+ulSetInterruptMaskFromISR:\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+vClearInterruptMaskFromISR:\r
+ msr PRIMASK, r0\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+PendSV_Handler:\r
+ mrs r0, psp /* Read PSP in r0. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+#if ( configENABLE_MPU == 1 )\r
+ subs r0, r0, #44 /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ str r0, [r1] /* Save the new top of stack in TCB. */\r
+ mrs r1, psplim /* r1 = PSPLIM. */\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r0!, {r1-r7} /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */\r
+ mov r4, r8 /* r4 = r8. */\r
+ mov r5, r9 /* r5 = r9. */\r
+ mov r6, r10 /* r6 = r10. */\r
+ mov r7, r11 /* r7 = r11. */\r
+ stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */\r
+#else /* configENABLE_MPU */\r
+ subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */\r
+ str r0, [r1] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */\r
+ mov r4, r8 /* r4 = r8. */\r
+ mov r5, r9 /* r5 = r9. */\r
+ mov r6, r10 /* r6 = r10. */\r
+ mov r7, r11 /* r7 = r11. */\r
+ stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */\r
+#endif /* configENABLE_MPU */\r
+\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
+\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r4, #1 /* r4 = 1. */\r
+ bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\r
+ str r3, [r2] /* Disable MPU. */\r
+\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */\r
+ movs r4, #5 /* r4 = 5. */\r
+ str r4, [r2] /* Program RNR = 5. */\r
+ ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */\r
+ movs r4, #6 /* r4 = 6. */\r
+ str r4, [r2] /* Program RNR = 6. */\r
+ ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */\r
+ movs r4, #7 /* r4 = 7. */\r
+ str r4, [r2] /* Program RNR = 7. */\r
+ ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r4, #1 /* r4 = 1. */\r
+ orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\r
+ str r3, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ adds r0, r0, #28 /* Move to the high registers. */\r
+ ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */\r
+ mov r8, r4 /* r8 = r4. */\r
+ mov r9, r5 /* r9 = r5. */\r
+ mov r10, r6 /* r10 = r6. */\r
+ mov r11, r7 /* r11 = r7. */\r
+ msr psp, r0 /* Remember the new top of stack for the task. */\r
+ subs r0, r0, #44 /* Move to the starting of the saved context. */\r
+ ldmia r0!, {r1-r7} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */\r
+ msr psplim, r1 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r2 /* Restore the CONTROL register value for the task. */\r
+ bx r3\r
+#else /* configENABLE_MPU */\r
+ adds r0, r0, #24 /* Move to the high registers. */\r
+ ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */\r
+ mov r8, r4 /* r8 = r4. */\r
+ mov r9, r5 /* r9 = r5. */\r
+ mov r10, r6 /* r10 = r6. */\r
+ mov r11, r7 /* r11 = r7. */\r
+ msr psp, r0 /* Remember the new top of stack for the task. */\r
+ subs r0, r0, #40 /* Move to the starting of the saved context. */\r
+ ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ bx r3\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+SVC_Handler:\r
+ movs r0, #4\r
+ mov r1, lr\r
+ tst r0, r1\r
+ beq stacking_used_msp\r
+ mrs r0, psp\r
+ b vPortSVCHandler_C\r
+ stacking_used_msp:\r
+ mrs r0, msp\r
+ b vPortSVCHandler_C\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ str r4, [r2] /* Disable MPU. */\r
+\r
adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */\r
stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ str r4, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ str r4, [r2] /* Disable MPU. */\r
+\r
adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ str r4, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ str r4, [r2] /* Disable MPU. */\r
+\r
adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ str r4, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ str r4, [r2] /* Disable MPU. */\r
+\r
adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ str r4, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
/* MPU regions. */\r
#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
-#define portPRIVILEGED_RAM_REGION ( 2UL )\r
-#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
#define portSTACK_REGION ( 4UL )\r
#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
-/* Devices Region. */\r
-#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
-#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
-\r
/* Device memory attributes used in MPU_MAIR registers.\r
*\r
* 8-bit values encoded as follows:\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
+/**\r
+ * @brief Barriers.\r
+ */\r
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
\r
#ifdef __cplusplus\r
}\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
+#endif\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ /* xSecureContextHandle value is in r0. */\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r1, ipsr \n" /* r1 = IPSR. */\r
+ " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+ " ldmia r0!, {r1, r2} \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+ " msr control, r3 \n" /* CONTROL = r3. */\r
+ #endif /* configENABLE_MPU */\r
+ " msr psplim, r2 \n" /* PSPLIM = r2. */\r
+ " msr psp, r1 \n" /* PSP = r1. */\r
+ " \n"\r
+ " load_ctx_therad_mode: \n"\r
+ " nop \n"\r
+ " \n"\r
+ :::"r0", "r1", "r2"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ /* xSecureContextHandle value is in r0. */\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r1, ipsr \n" /* r1 = IPSR. */\r
+ " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+ " mrs r1, psp \n" /* r1 = PSP. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " subs r1, r1, #4 \n" /* Make space for the CONTROL value on the stack. */\r
+ " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ " stmia r1!, {r2} \n" /* Store CONTROL value on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ #endif /* configENABLE_MPU */\r
+ " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */\r
+ " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */\r
+ " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+ " \n"\r
+ " save_ctx_therad_mode: \n"\r
+ " nop \n"\r
+ " \n"\r
+ :: "i" ( securecontextNO_STACK ) : "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/* Functions implemented in assembler file. */\r
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );\r
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ SecureContext_LoadContextAsm( xSecureContextHandle );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ SecureContext_SaveContextAsm( xSecureContextHandle );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+\r
+ PUBLIC SecureContext_LoadContextAsm\r
+ PUBLIC SecureContext_SaveContextAsm\r
+\r
+#if ( configENABLE_FPU == 1 )\r
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+SecureContext_LoadContextAsm:\r
+ /* xSecureContextHandle value is in r0. */\r
+ mrs r1, ipsr /* r1 = IPSR. */\r
+ cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
+ ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+#if ( configENABLE_MPU == 1 )\r
+ ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+ msr control, r3 /* CONTROL = r3. */\r
+#endif /* configENABLE_MPU */\r
+ msr psplim, r2 /* PSPLIM = r2. */\r
+ msr psp, r1 /* PSP = r1. */\r
+\r
+ load_ctx_therad_mode:\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+SecureContext_SaveContextAsm:\r
+ /* xSecureContextHandle value is in r0. */\r
+ mrs r1, ipsr /* r1 = IPSR. */\r
+ cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
+ mrs r1, psp /* r1 = PSP. */\r
+#if ( configENABLE_MPU == 1 )\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */\r
+ str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ stmia r1!, {r2} /* Store CONTROL value on the stack. */\r
+#else /* configENABLE_MPU */\r
+ str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+#endif /* configENABLE_MPU */\r
+ movs r1, #0 /* r1 = securecontextNO_STACK. */\r
+ msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */\r
+ msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+\r
+ save_ctx_therad_mode:\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+ * all the API functions to use the MPU wrappers. That should only be done when\r
+ * task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/**\r
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
+ * i.e. the processor boots as secure and never jumps to the non-secure side.\r
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
+ * on the secure side. The following are the valid configuration seetings:\r
+ *\r
+ * 1. Run FreeRTOS on the Secure Side:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
+ *\r
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
+ *\r
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
+ */\r
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the NVIC.\r
+ */\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the MPU.\r
+ */\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+\r
+/* Enable privileged access to unmapped region. */\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+\r
+/* Enable MPU. */\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
+\r
+/* Expected value of the portMPU_TYPE register. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to set up the initial stack.\r
+ */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF FD\r
+ * 1111 1111 1111 1111 1111 1111 1111 1101\r
+ *\r
+ * Bit[6] - 1 --> The exception was taken from the Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 1 --> The exception was taken to the Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )\r
+#else\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#endif /* configRUN_FREERTOS_SECURE_ONLY */\r
+\r
+/**\r
+ * @brief CONTROL register privileged bit mask.\r
+ *\r
+ * Bit[0] in CONTROL register tells the privilege:\r
+ * Bit[0] = 0 ==> The task is privileged.\r
+ * Bit[0] = 1 ==> The task is not privileged.\r
+ */\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+\r
+/**\r
+ * @brief Initial CONTROL register values.\r
+ */\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+\r
+/**\r
+ * @brief Let the user override the pre-loading of the initial LR with the\r
+ * address of prvTaskExitError() in case it messes up unwinding of the stack\r
+ * in the debugger.\r
+ */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/**\r
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
+ * when a task is created. This helps in debugging at the cost of code size.\r
+ */\r
+#define portPRELOAD_REGISTERS 1\r
+\r
+/**\r
+ * @brief A task is created without a secure context, and must call\r
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
+ * any secure calls.\r
+ */\r
+#define portNO_SECURE_CONTEXT 0\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Used to catch tasks that attempt to return from their implementing\r
+ * function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_MPU */\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_FPU */\r
+\r
+/**\r
+ * @brief Yield the processor.\r
+ */\r
+void vPortYield( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enter critical section.\r
+ */\r
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Exit from critical section.\r
+ */\r
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SysTick handler.\r
+ */\r
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief C part of SVC handler.\r
+ */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Each task maintains its own interrupt status in the critical nesting\r
+ * variable.\r
+ */\r
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+volatile uint32_t ulDummy = 0UL;\r
+\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ extern uint32_t * __unprivileged_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ extern uint32_t __unprivileged_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash as Read Only by both privileged and\r
+ * unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged syscalls flash as Read Only by both privileged\r
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
+#endif /* configENABLE_FPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
+\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+uint32_t ulPreviousMask;\r
+\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+{\r
+#if( configENABLE_MPU == 1 )\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+#endif /* configENABLE_MPU */\r
+\r
+uint32_t ulPC;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
+#endif /* configENABLE_TRUSTZONE */\r
+uint8_t ucSVCNumber;\r
+\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+#else\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+#endif /* configENABLE_MPU */\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
+ * is defined correctly and privileged functions are placed in correct sections. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
+ * header files. */\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
+#endif\r
+\r
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r5, #1 \n" /* r5 = 1. */\r
+ " bics r4, r5 \n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " movs r5, #4 \n" /* r5 = 4. */\r
+ " str r5, [r2] \n" /* Program RNR = 4. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read first set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write first set of RBAR/RLAR registers. */\r
+ " movs r5, #5 \n" /* r5 = 5. */\r
+ " str r5, [r2] \n" /* Program RNR = 5. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read second set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write second set of RBAR/RLAR registers. */\r
+ " movs r5, #6 \n" /* r5 = 6. */\r
+ " str r5, [r2] \n" /* Program RNR = 6. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read third set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write third set of RBAR/RLAR registers. */\r
+ " movs r5, #7 \n" /* r5 = 7. */\r
+ " str r5, [r2] \n" /* Program RNR = 7. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read fourth set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write fourth set of RBAR/RLAR registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r5, #1 \n" /* r5 = 1. */\r
+ " orrs r4, r5 \n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ " ldr r5, xSecureContextConst2 \n"\r
+ " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r3 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r4 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ " ldr r4, xSecureContextConst2 \n"\r
+ " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ "xSecureContextConst2: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " movs r1, #1 \n" /* r1 = 1. */\r
+ " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\r
+ " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */\r
+ " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " running_privileged: \n"\r
+ " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " movs r1, #1 \n" /* r1 = 1. */\r
+ " bics r0, r1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " movs r1, #1 \n" /* r1 = 1. */\r
+ " orrs r0, r1 \n" /* r0 = r0 | r1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " .extern SecureContext_SaveContext \n"\r
+ " .extern SecureContext_LoadContext \n"\r
+ " \n"\r
+ " mrs r1, psp \n" /* Read PSP in r1. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+ " \n"\r
+ " cbz r0, save_ns_context \n" /* No secure context to save. */\r
+ " push {r0-r2, r14} \n"\r
+ " bl SecureContext_SaveContext \n"\r
+ " pop {r0-r3} \n" /* LR is now in r3. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " b select_next_task \n"\r
+ " \n"\r
+ " save_ns_context: \n"\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " adds r1, r1, #16 \n" /* r1 = r1 + 16. */\r
+ " stmia r1!, {r4-r7} \n" /* Store the low registers that are not saved automatically. */\r
+ " mov r4, r8 \n" /* r4 = r8. */\r
+ " mov r5, r9 \n" /* r5 = r9. */\r
+ " mov r6, r10 \n" /* r6 = r10. */\r
+ " mov r7, r11 \n" /* r7 = r11. */\r
+ " stmia r1!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " subs r1, r1, #48 \n" /* r1 = r1 - 48. */\r
+ " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r7} \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */\r
+ " mov r4, r8 \n" /* r4 = r8. */\r
+ " mov r5, r9 \n" /* r5 = r9. */\r
+ " mov r6, r10 \n" /* r6 = r10. */\r
+ " mov r7, r11 \n" /* r7 = r11. */\r
+ " stmia r1!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " select_next_task: \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r5, #1 \n" /* r5 = 1. */\r
+ " bics r4, r5 \n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " movs r5, #4 \n" /* r5 = 4. */\r
+ " str r5, [r2] \n" /* Program RNR = 4. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read first set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write first set of RBAR/RLAR registers. */\r
+ " movs r5, #5 \n" /* r5 = 5. */\r
+ " str r5, [r2] \n" /* Program RNR = 5. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read second set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write second set of RBAR/RLAR registers. */\r
+ " movs r5, #6 \n" /* r5 = 6. */\r
+ " str r5, [r2] \n" /* Program RNR = 6. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read third set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write third set of RBAR/RLAR registers. */\r
+ " movs r5, #7 \n" /* r5 = 7. */\r
+ " str r5, [r2] \n" /* Program RNR = 7. */\r
+ " ldmia r3!, {r6,r7} \n" /* Read fourth set of RBAR/RLAR from TCB. */\r
+ " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r4!, {r6,r7} \n" /* Write fourth set of RBAR/RLAR registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r5, #1 \n" /* r5 = 1. */\r
+ " orrs r4, r5 \n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r3 \n" /* Restore the CONTROL register value for the task. */\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r4} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r4} \n"\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #else /* configENABLE_MPU */\r
+ " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r3} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r3} \n"\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " restore_ns_context: \n"\r
+ " adds r1, r1, #16 \n" /* Move to the high registers. */\r
+ " ldmia r1!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */\r
+ " mov r8, r4 \n" /* r8 = r4. */\r
+ " mov r9, r5 \n" /* r9 = r5. */\r
+ " mov r10, r6 \n" /* r10 = r6. */\r
+ " mov r11, r7 \n" /* r11 = r7. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " subs r1, r1, #32 \n" /* Go back to the low registers. */\r
+ " ldmia r1!, {r4-r7} \n" /* Restore the low registers that are not automatically restored. */\r
+ " bx lr \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "xSecureContextConst: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst: .word 0xe000ed94 \n"\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " movs r0, #4 \n"\r
+ " mov r1, lr \n"\r
+ " tst r0, r1 \n"\r
+ " beq stacking_used_msp \n"\r
+ " mrs r0, psp \n"\r
+ " ldr r2, svchandler_address_const \n"\r
+ " bx r2 \n"\r
+ " stacking_used_msp: \n"\r
+ " mrs r0, msp \n"\r
+ " ldr r2, svchandler_address_const \n"\r
+ " bx r2 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " svc %0 \n" /* Secure context is allocated in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */\r
+ " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */\r
+ " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */\r
+ " beq free_secure_context \n"\r
+ " bx lr \n" /* There is no secure context (xSecureContext is NULL). */\r
+ " free_secure_context: \n"\r
+ " svc %0 \n" /* Secure context is freed in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __PORT_ASM_H__\r
+#define __PORT_ASM_H__\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/**\r
+ * @brief Restore the context of the first task so that the first task starts\r
+ * executing.\r
+ */\r
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * @note This is a privileged function and should only be called from the kenrel\r
+ * code.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Starts the first task.\r
+ */\r
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Disables interrupts.\r
+ */\r
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enables interrupts.\r
+ */\r
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief PendSV Exception handler.\r
+ */\r
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SVC Handler.\r
+ */\r
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Allocate a Secure context for the calling task.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the\r
+ * secure side for the calling task.\r
+ */\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Free the task's secure context.\r
+ *\r
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\r
+ */\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+#endif /* __PORT_ASM_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M33"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure heap includes. */\r
+#include "secure_heap.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief CONTROL value for privileged tasks.\r
+ *\r
+ * Bit[0] - 0 --> Thread mode is privileged.\r
+ * Bit[1] - 1 --> Thread mode uses PSP.\r
+ */\r
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02\r
+\r
+/**\r
+ * @brief CONTROL value for un-privileged tasks.\r
+ *\r
+ * Bit[0] - 1 --> Thread mode is un-privileged.\r
+ * Bit[1] - 1 --> Thread mode uses PSP.\r
+ */\r
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Structure to represent secure context.\r
+ *\r
+ * @note Since stack grows down, pucStackStart is the highest address while\r
+ * pucStackLimit is the first addess of the allocated memory.\r
+ */\r
+typedef struct SecureContext\r
+{\r
+ uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\r
+ uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */\r
+ uint8_t *pucStackStart; /**< First location of the stack memory. */\r
+} SecureContext_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* No stack for thread mode until a task's context is loaded. */\r
+ secureportSET_PSPLIM( securecontextNO_STACK );\r
+ secureportSET_PSP( securecontextNO_STACK );\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Configure thread mode to use PSP and to be unprivileged. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Configure thread mode to use PSP and to be privileged.. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )\r
+#else /* configENABLE_MPU */\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )\r
+#endif /* configENABLE_MPU */\r
+{\r
+ uint8_t *pucStackMemory = NULL;\r
+ uint32_t ulIPSR;\r
+ SecureContextHandle_t xSecureContextHandle = NULL;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t *pulCurrentStackPointer = NULL;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Allocate the context structure. */\r
+ xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );\r
+\r
+ if( xSecureContextHandle != NULL )\r
+ {\r
+ /* Allocate the stack space. */\r
+ pucStackMemory = pvPortMalloc( ulSecureStackSize );\r
+\r
+ if( pucStackMemory != NULL )\r
+ {\r
+ /* Since stack grows down, the starting point will be the last\r
+ * location. Note that this location is next to the last\r
+ * allocated byte because the hardware decrements the stack\r
+ * pointer before writing i.e. if stack pointer is 0x2, a push\r
+ * operation will decrement the stack pointer to 0x1 and then\r
+ * write at 0x1. */\r
+ xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;\r
+\r
+ /* The stack cannot go beyond this location. This value is\r
+ * programmed in the PSPLIM register on context switch.*/\r
+ xSecureContextHandle->pucStackLimit = pucStackMemory;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Store the correct CONTROL value for the task on the stack.\r
+ * This value is programmed in the CONTROL register on\r
+ * context switch. */\r
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;\r
+ pulCurrentStackPointer--;\r
+ if( ulIsTaskPrivileged )\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\r
+ }\r
+ else\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\r
+ }\r
+\r
+ /* Store the current stack pointer. This value is programmed in\r
+ * the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Current SP is set to the starting of the stack. This\r
+ * value programmed in the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;\r
+\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+ else\r
+ {\r
+ /* Free the context to avoid memory leak and make sure to return\r
+ * NULL to indicate failure. */\r
+ vPortFree( xSecureContextHandle );\r
+ xSecureContextHandle = NULL;\r
+ }\r
+ }\r
+ }\r
+\r
+ return xSecureContextHandle;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Ensure that valid parameters are passed. */\r
+ secureportASSERT( xSecureContextHandle != NULL );\r
+\r
+ /* Free the stack space. */\r
+ vPortFree( xSecureContextHandle->pucStackLimit );\r
+\r
+ /* Free the context itself. */\r
+ vPortFree( xSecureContextHandle );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_CONTEXT_H__\r
+#define __SECURE_CONTEXT_H__\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOSConfig.h"\r
+\r
+/**\r
+ * @brief PSP value when no task's context is loaded.\r
+ */\r
+#define securecontextNO_STACK 0x0\r
+\r
+/**\r
+ * @brief Opaque handle.\r
+ */\r
+struct SecureContext;\r
+typedef struct SecureContext* SecureContextHandle_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Initializes the secure context management system.\r
+ *\r
+ * PSP is set to NULL and therefore a task must allocate and load a context\r
+ * before calling any secure side function in the thread mode.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureContext_Init( void );\r
+\r
+/**\r
+ * @brief Allocates a context on the secure side.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\r
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\r
+ *\r
+ * @return Opaque context handle if context is successfully allocated, NULL\r
+ * otherwise.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );\r
+#else /* configENABLE_MPU */\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );\r
+#endif /* configENABLE_MPU */\r
+\r
+/**\r
+ * @brief Frees the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the\r
+ * context to be freed.\r
+ */\r
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+/**\r
+ * @brief Loads the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the context\r
+ * to be loaded.\r
+ */\r
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+/**\r
+ * @brief Saves the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the context\r
+ * to be saved.\r
+ */\r
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+#endif /* __SECURE_CONTEXT_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
+#endif\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ /* xSecureContextHandle value is in r0. */\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r1, ipsr \n" /* r1 = IPSR. */\r
+ " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+ " ldmia r0!, {r1, r2} \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+ " msr control, r3 \n" /* CONTROL = r3. */\r
+ #endif /* configENABLE_MPU */\r
+ " msr psplim, r2 \n" /* PSPLIM = r2. */\r
+ " msr psp, r1 \n" /* PSP = r1. */\r
+ " \n"\r
+ " load_ctx_therad_mode: \n"\r
+ " nop \n"\r
+ " \n"\r
+ :::"r0", "r1", "r2"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ /* xSecureContextHandle value is in r0. */\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r1, ipsr \n" /* r1 = IPSR. */\r
+ " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+ " mrs r1, psp \n" /* r1 = PSP. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " subs r1, r1, #4 \n" /* Make space for the CONTROL value on the stack. */\r
+ " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ " stmia r1!, {r2} \n" /* Store CONTROL value on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ #endif /* configENABLE_MPU */\r
+ " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */\r
+ " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */\r
+ " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+ " \n"\r
+ " save_ctx_therad_mode: \n"\r
+ " nop \n"\r
+ " \n"\r
+ :: "i" ( securecontextNO_STACK ) : "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Secure context heap includes. */\r
+#include "secure_heap.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief Total heap size.\r
+ */\r
+#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )\r
+\r
+/* No test marker by default. */\r
+#ifndef mtCOVERAGE_TEST_MARKER\r
+ #define mtCOVERAGE_TEST_MARKER()\r
+#endif\r
+\r
+/* No tracing by default. */\r
+#ifndef traceMALLOC\r
+ #define traceMALLOC( pvReturn, xWantedSize )\r
+#endif\r
+\r
+/* No tracing by default. */\r
+#ifndef traceFREE\r
+ #define traceFREE( pv, xBlockSize )\r
+#endif\r
+\r
+/* Block sizes must not get too small. */\r
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )\r
+\r
+/* Assumes 8bit bytes! */\r
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Allocate the memory for the heap. */\r
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )\r
+ /* The application writer has already defined the array used for the RTOS\r
+ * heap - probably so it can be placed in a special segment or address. */\r
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+#else /* configAPPLICATION_ALLOCATED_HEAP */\r
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+#endif /* configAPPLICATION_ALLOCATED_HEAP */\r
+\r
+/**\r
+ * @brief The linked list structure.\r
+ *\r
+ * This is used to link free blocks in order of their memory address.\r
+ */\r
+typedef struct A_BLOCK_LINK\r
+{\r
+ struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */\r
+ size_t xBlockSize; /**< The size of the free block. */\r
+} BlockLink_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Called automatically to setup the required heap structures the first\r
+ * time pvPortMalloc() is called.\r
+ */\r
+static void prvHeapInit( void );\r
+\r
+/**\r
+ * @brief Inserts a block of memory that is being freed into the correct\r
+ * position in the list of free memory blocks.\r
+ *\r
+ * The block being freed will be merged with the block in front it and/or the\r
+ * block behind it if the memory blocks are adjacent to each other.\r
+ *\r
+ * @param[in] pxBlockToInsert The block being freed.\r
+ */\r
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief The size of the structure placed at the beginning of each allocated\r
+ * memory block must by correctly byte aligned.\r
+ */\r
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+\r
+/**\r
+ * @brief Create a couple of list links to mark the start and end of the list.\r
+ */\r
+static BlockLink_t xStart, *pxEnd = NULL;\r
+\r
+/**\r
+ * @brief Keeps track of the number of free bytes remaining, but says nothing\r
+ * about fragmentation.\r
+ */\r
+static size_t xFreeBytesRemaining = 0U;\r
+static size_t xMinimumEverFreeBytesRemaining = 0U;\r
+\r
+/**\r
+ * @brief Gets set to the top bit of an size_t type.\r
+ *\r
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set\r
+ * then the block belongs to the application. When the bit is free the block is\r
+ * still part of the free heap space.\r
+ */\r
+static size_t xBlockAllocatedBit = 0;\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHeapInit( void )\r
+{\r
+BlockLink_t *pxFirstFreeBlock;\r
+uint8_t *pucAlignedHeap;\r
+size_t uxAddress;\r
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\r
+\r
+ /* Ensure the heap starts on a correctly aligned boundary. */\r
+ uxAddress = ( size_t ) ucHeap;\r
+\r
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\r
+ {\r
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\r
+ }\r
+\r
+ pucAlignedHeap = ( uint8_t * ) uxAddress;\r
+\r
+ /* xStart is used to hold a pointer to the first item in the list of free\r
+ * blocks. The void cast is used to prevent compiler warnings. */\r
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
+ xStart.xBlockSize = ( size_t ) 0;\r
+\r
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted\r
+ * at the end of the heap space. */\r
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\r
+ uxAddress -= xHeapStructSize;\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ pxEnd = ( void * ) uxAddress;\r
+ pxEnd->xBlockSize = 0;\r
+ pxEnd->pxNextFreeBlock = NULL;\r
+\r
+ /* To start with there is a single free block that is sized to take up the\r
+ * entire heap space, minus the space taken by pxEnd. */\r
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\r
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\r
+\r
+ /* Only one block exists - and it covers the entire usable heap space. */\r
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+\r
+ /* Work out the position of the top bit in a size_t variable. */\r
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )\r
+{\r
+BlockLink_t *pxIterator;\r
+uint8_t *puc;\r
+\r
+ /* Iterate through the list until a block is found that has a higher address\r
+ * than the block being inserted. */\r
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\r
+ {\r
+ /* Nothing to do here, just iterate to the right position. */\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted after\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxIterator;\r
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\r
+ {\r
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\r
+ pxBlockToInsert = pxIterator;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted before\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxBlockToInsert;\r
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\r
+ {\r
+ if( pxIterator->pxNextFreeBlock != pxEnd )\r
+ {\r
+ /* Form one big block from the two blocks. */\r
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the block being inserted plugged a gab, so was merged with the block\r
+ * before and the block after, then it's pxNextFreeBlock pointer will have\r
+ * already been set, and should not be set here as that would make it point\r
+ * to itself. */\r
+ if( pxIterator != pxBlockToInsert )\r
+ {\r
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvPortMalloc( size_t xWantedSize )\r
+{\r
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
+void *pvReturn = NULL;\r
+\r
+ /* If this is the first call to malloc then the heap will require\r
+ * initialisation to setup the list of free blocks. */\r
+ if( pxEnd == NULL )\r
+ {\r
+ prvHeapInit();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Check the requested block size is not so large that the top bit is set.\r
+ * The top bit of the block size member of the BlockLink_t structure is used\r
+ * to determine who owns the block - the application or the kernel, so it\r
+ * must be free. */\r
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\r
+ {\r
+ /* The wanted size is increased so it can contain a BlockLink_t\r
+ * structure in addition to the requested amount of bytes. */\r
+ if( xWantedSize > 0 )\r
+ {\r
+ xWantedSize += xHeapStructSize;\r
+\r
+ /* Ensure that blocks are always aligned to the required number of\r
+ * bytes. */\r
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\r
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\r
+ {\r
+ /* Traverse the list from the start (lowest address) block until\r
+ * one of adequate size is found. */\r
+ pxPreviousBlock = &xStart;\r
+ pxBlock = xStart.pxNextFreeBlock;\r
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
+ {\r
+ pxPreviousBlock = pxBlock;\r
+ pxBlock = pxBlock->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the end marker was reached then a block of adequate size was\r
+ * not found. */\r
+ if( pxBlock != pxEnd )\r
+ {\r
+ /* Return the memory space pointed to - jumping over the\r
+ * BlockLink_t structure at its start. */\r
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\r
+\r
+ /* This block is being returned for use so must be taken out\r
+ * of the list of free blocks. */\r
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
+\r
+ /* If the block is larger than required it can be split into\r
+ * two. */\r
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\r
+ {\r
+ /* This block is to be split into two. Create a new\r
+ * block following the number of bytes requested. The void\r
+ * cast is used to prevent byte alignment warnings from the\r
+ * compiler. */\r
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+\r
+ /* Calculate the sizes of two blocks split from the single\r
+ * block. */\r
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
+ pxBlock->xBlockSize = xWantedSize;\r
+\r
+ /* Insert the new block into the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( pxNewBlockLink );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ xFreeBytesRemaining -= pxBlock->xBlockSize;\r
+\r
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\r
+ {\r
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* The block is being returned - it is allocated and owned by\r
+ * the application and has no "next" block. */\r
+ pxBlock->xBlockSize |= xBlockAllocatedBit;\r
+ pxBlock->pxNextFreeBlock = NULL;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ traceMALLOC( pvReturn, xWantedSize );\r
+\r
+ #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\r
+ {\r
+ if( pvReturn == NULL )\r
+ {\r
+ extern void vApplicationMallocFailedHook( void );\r
+ vApplicationMallocFailedHook();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ return pvReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFree( void *pv )\r
+{\r
+uint8_t *puc = ( uint8_t * ) pv;\r
+BlockLink_t *pxLink;\r
+\r
+ if( pv != NULL )\r
+ {\r
+ /* The memory being freed will have an BlockLink_t structure immediately\r
+ * before it. */\r
+ puc -= xHeapStructSize;\r
+\r
+ /* This casting is to keep the compiler from issuing warnings. */\r
+ pxLink = ( void * ) puc;\r
+\r
+ /* Check the block is actually allocated. */\r
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\r
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );\r
+\r
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\r
+ {\r
+ if( pxLink->pxNextFreeBlock == NULL )\r
+ {\r
+ /* The block is being returned to the heap - it is no longer\r
+ * allocated. */\r
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;\r
+\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS();\r
+ {\r
+ /* Add this block to the list of free blocks. */\r
+ xFreeBytesRemaining += pxLink->xBlockSize;\r
+ traceFREE( pv, pxLink->xBlockSize );\r
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
+ }\r
+ secureportENABLE_NON_SECURE_INTERRUPTS();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+size_t xPortGetFreeHeapSize( void )\r
+{\r
+ return xFreeBytesRemaining;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+size_t xPortGetMinimumEverFreeHeapSize( void )\r
+{\r
+ return xMinimumEverFreeBytesRemaining;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortInitialiseBlocks( void )\r
+{\r
+ /* This just exists to keep the linker quiet. */\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_HEAP_H__\r
+#define __SECURE_HEAP_H__\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/**\r
+ * @brief Allocates memory from heap.\r
+ *\r
+ * @param[in] xWantedSize The size of the memory to be allocated.\r
+ *\r
+ * @return Pointer to the memory region if the allocation is successful, NULL\r
+ * otherwise.\r
+ */\r
+void *pvPortMalloc( size_t xWantedSize );\r
+\r
+/**\r
+ * @brief Frees the previously allocated memory.\r
+ *\r
+ * @param[in] pv Pointer to the memory to be freed.\r
+ */\r
+void vPortFree( void *pv );\r
+\r
+#endif /* __SECURE_HEAP_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Secure init includes. */\r
+#include "secure_init.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */\r
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )\r
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )\r
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define secureinitFPCCR_LSPENS_POS ( 29UL )\r
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )\r
+#define secureinitFPCCR_TS_POS ( 26UL )\r
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )\r
+\r
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */\r
+#define secureinitNSACR_CP10_POS ( 10UL )\r
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )\r
+#define secureinitNSACR_CP11_POS ( 11UL )\r
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
+ * permitted. CP11 should be programmed to the same value as CP10. */\r
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
+\r
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
+ * that we can enable/disable lazy stacking in port.c file. */\r
+ *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
+\r
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
+ * registers (S16-S31) are also pushed to stack on exception entry and\r
+ * restored on exception return. */\r
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_INIT_H__\r
+#define __SECURE_INIT_H__\r
+\r
+/**\r
+ * @brief De-prioritizes the non-secure exceptions.\r
+ *\r
+ * This is needed to ensure that the non-secure PendSV runs at the lowest\r
+ * priority. Context switch is done in the non-secure PendSV handler.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureInit_DePrioritizeNSExceptions( void );\r
+\r
+/**\r
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\r
+ *\r
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\r
+ * Registers are not leaked to the non-secure side.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureInit_EnableNSFPUAccess( void );\r
+\r
+#endif /* __SECURE_INIT_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_PORT_MACROS_H__\r
+#define __SECURE_PORT_MACROS_H__\r
+\r
+/**\r
+ * @brief Byte alignment requirements.\r
+ */\r
+#define secureportBYTE_ALIGNMENT 8\r
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )\r
+\r
+/**\r
+ * @brief Macro to declare a function as non-secure callable.\r
+ */\r
+#if defined( __IAR_SYSTEMS_ICC__ )\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+#else\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+#endif\r
+\r
+/**\r
+ * @brief Set the secure PRIMASK value.\r
+ */\r
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\r
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+\r
+/**\r
+ * @brief Set the non-secure PRIMASK value.\r
+ */\r
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\r
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+\r
+/**\r
+ * @brief Read the PSP value in the given variable.\r
+ */\r
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\r
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the PSP to the given value.\r
+ */\r
+#define secureportSET_PSP( pucCurrentStackPointer ) \\r
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the PSPLIM to the given value.\r
+ */\r
+#define secureportSET_PSPLIM( pucStackLimit ) \\r
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )\r
+\r
+/**\r
+ * @brief Set the NonSecure MSP to the given value.\r
+ */\r
+#define secureportSET_MSP_NS( pucMainStackPointer ) \\r
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the CONTROL register to the given value.\r
+ */\r
+#define secureportSET_CONTROL( ulControl ) \\r
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )\r
+\r
+/**\r
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given\r
+ * variable.\r
+ */\r
+#define secureportREAD_IPSR( ulIPSR ) \\r
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )\r
+\r
+/**\r
+ * @brief PRIMASK value to enable interrupts.\r
+ */\r
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0\r
+\r
+/**\r
+ * @brief PRIMASK value to disable interrupts.\r
+ */\r
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1\r
+\r
+/**\r
+ * @brief Disable secure interrupts.\r
+ */\r
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Disable non-secure interrupts.\r
+ *\r
+ * This effectively disables context switches.\r
+ */\r
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Enable non-secure interrupts.\r
+ */\r
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Assert definition.\r
+ */\r
+#define secureportASSERT( x ) \\r
+ if( ( x ) == 0 ) \\r
+ { \\r
+ secureportDISABLE_SECURE_INTERRUPTS(); \\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \\r
+ for( ;; ); \\r
+ }\r
+\r
+#endif /* __SECURE_PORT_MACROS_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+ * all the API functions to use the MPU wrappers. That should only be done when\r
+ * task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/**\r
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
+ * i.e. the processor boots as secure and never jumps to the non-secure side.\r
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
+ * on the secure side. The following are the valid configuration seetings:\r
+ *\r
+ * 1. Run FreeRTOS on the Secure Side:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
+ *\r
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
+ *\r
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
+ */\r
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the NVIC.\r
+ */\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the MPU.\r
+ */\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+\r
+/* Enable privileged access to unmapped region. */\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+\r
+/* Enable MPU. */\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
+\r
+/* Expected value of the portMPU_TYPE register. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to set up the initial stack.\r
+ */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF FD\r
+ * 1111 1111 1111 1111 1111 1111 1111 1101\r
+ *\r
+ * Bit[6] - 1 --> The exception was taken from the Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 1 --> The exception was taken to the Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )\r
+#else\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#endif /* configRUN_FREERTOS_SECURE_ONLY */\r
+\r
+/**\r
+ * @brief CONTROL register privileged bit mask.\r
+ *\r
+ * Bit[0] in CONTROL register tells the privilege:\r
+ * Bit[0] = 0 ==> The task is privileged.\r
+ * Bit[0] = 1 ==> The task is not privileged.\r
+ */\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+\r
+/**\r
+ * @brief Initial CONTROL register values.\r
+ */\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+\r
+/**\r
+ * @brief Let the user override the pre-loading of the initial LR with the\r
+ * address of prvTaskExitError() in case it messes up unwinding of the stack\r
+ * in the debugger.\r
+ */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/**\r
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
+ * when a task is created. This helps in debugging at the cost of code size.\r
+ */\r
+#define portPRELOAD_REGISTERS 1\r
+\r
+/**\r
+ * @brief A task is created without a secure context, and must call\r
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
+ * any secure calls.\r
+ */\r
+#define portNO_SECURE_CONTEXT 0\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Used to catch tasks that attempt to return from their implementing\r
+ * function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_MPU */\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_FPU */\r
+\r
+/**\r
+ * @brief Yield the processor.\r
+ */\r
+void vPortYield( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enter critical section.\r
+ */\r
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Exit from critical section.\r
+ */\r
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SysTick handler.\r
+ */\r
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief C part of SVC handler.\r
+ */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Each task maintains its own interrupt status in the critical nesting\r
+ * variable.\r
+ */\r
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+volatile uint32_t ulDummy = 0UL;\r
+\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ extern uint32_t * __unprivileged_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ extern uint32_t __unprivileged_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash as Read Only by both privileged and\r
+ * unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged syscalls flash as Read Only by both privileged\r
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
+#endif /* configENABLE_FPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
+\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+uint32_t ulPreviousMask;\r
+\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+{\r
+#if( configENABLE_MPU == 1 )\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+#endif /* configENABLE_MPU */\r
+\r
+uint32_t ulPC;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
+#endif /* configENABLE_TRUSTZONE */\r
+uint8_t ucSVCNumber;\r
+\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+#else\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+#endif /* configENABLE_MPU */\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
+ * is defined correctly and privileged functions are placed in correct sections. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
+ * header files. */\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
+#endif\r
+\r
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r4, #1 \n" /* r4 = 1. */\r
+ " bics r3, r4 \n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\r
+ " str r3, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r1] \n" /* r4 = *r1 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read first set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write first set of RBAR/RLAR registers. */\r
+ " movs r4, #5 \n" /* r4 = 5. */\r
+ " str r4, [r2] \n" /* Program RNR = 5. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read second set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write second set of RBAR/RLAR registers. */\r
+ " movs r4, #6 \n" /* r4 = 6. */\r
+ " str r4, [r2] \n" /* Program RNR = 6. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read third set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write third set of RBAR/RLAR registers. */\r
+ " movs r4, #7 \n" /* r4 = 7. */\r
+ " str r4, [r2] \n" /* Program RNR = 7. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read fourth set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write fourth set of RBAR/RLAR registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r4, #1 \n" /* r4 = 1. */\r
+ " orrs r3, r4 \n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\r
+ " str r3, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r2 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r2 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " movs r1, #1 \n" /* r1 = 1. */\r
+ " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\r
+ " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */\r
+ " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " running_privileged: \n"\r
+ " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " movs r1, #1 \n" /* r1 = 1. */\r
+ " bics r0, r1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " movs r1, #1 \n" /* r1 = 1. */\r
+ " orrs r0, r1 \n" /* r0 = r0 | r1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r0, psp \n" /* Read PSP in r0. */\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r0, r0, #44 \n" /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r1, psplim \n" /* r1 = PSPLIM. */\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r0!, {r1-r7} \n" /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */\r
+ " mov r4, r8 \n" /* r4 = r8. */\r
+ " mov r5, r9 \n" /* r5 = r9. */\r
+ " mov r6, r10 \n" /* r6 = r10. */\r
+ " mov r7, r11 \n" /* r7 = r11. */\r
+ " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */\r
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r0!, {r2-r7} \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */\r
+ " mov r4, r8 \n" /* r4 = r8. */\r
+ " mov r5, r9 \n" /* r5 = r9. */\r
+ " mov r6, r10 \n" /* r6 = r10. */\r
+ " mov r7, r11 \n" /* r7 = r11. */\r
+ " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r4, #1 \n" /* r4 = 1. */\r
+ " bics r3, r4 \n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\r
+ " str r3, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r1] \n" /* r4 = *r1 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read first set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write first set of RBAR/RLAR registers. */\r
+ " movs r4, #5 \n" /* r4 = 5. */\r
+ " str r4, [r2] \n" /* Program RNR = 5. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read second set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write second set of RBAR/RLAR registers. */\r
+ " movs r4, #6 \n" /* r4 = 6. */\r
+ " str r4, [r2] \n" /* Program RNR = 6. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read third set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write third set of RBAR/RLAR registers. */\r
+ " movs r4, #7 \n" /* r4 = 7. */\r
+ " str r4, [r2] \n" /* Program RNR = 7. */\r
+ " ldmia r1!, {r5,r6} \n" /* Read fourth set of RBAR/RLAR from TCB. */\r
+ " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ " stmia r3!, {r5,r6} \n" /* Write fourth set of RBAR/RLAR registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " movs r4, #1 \n" /* r4 = 1. */\r
+ " orrs r3, r4 \n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\r
+ " str r3, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r0, r0, #28 \n" /* Move to the high registers. */\r
+ " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */\r
+ " mov r8, r4 \n" /* r8 = r4. */\r
+ " mov r9, r5 \n" /* r9 = r5. */\r
+ " mov r10, r6 \n" /* r10 = r6. */\r
+ " mov r11, r7 \n" /* r11 = r7. */\r
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
+ " subs r0, r0, #44 \n" /* Move to the starting of the saved context. */\r
+ " ldmia r0!, {r1-r7} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */\r
+ " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r2 \n" /* Restore the CONTROL register value for the task. */\r
+ " bx r3 \n"\r
+ #else /* configENABLE_MPU */\r
+ " adds r0, r0, #24 \n" /* Move to the high registers. */\r
+ " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */\r
+ " mov r8, r4 \n" /* r8 = r4. */\r
+ " mov r9, r5 \n" /* r9 = r5. */\r
+ " mov r10, r6 \n" /* r10 = r6. */\r
+ " mov r11, r7 \n" /* r11 = r7. */\r
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
+ " subs r0, r0, #40 \n" /* Move to the starting of the saved context. */\r
+ " ldmia r0!, {r2-r7} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " bx r3 \n"\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst: .word 0xe000ed94 \n"\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " movs r0, #4 \n"\r
+ " mov r1, lr \n"\r
+ " tst r0, r1 \n"\r
+ " beq stacking_used_msp \n"\r
+ " mrs r0, psp \n"\r
+ " ldr r2, svchandler_address_const \n"\r
+ " bx r2 \n"\r
+ " stacking_used_msp: \n"\r
+ " mrs r0, msp \n"\r
+ " ldr r2, svchandler_address_const \n"\r
+ " bx r2 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __PORT_ASM_H__\r
+#define __PORT_ASM_H__\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/**\r
+ * @brief Restore the context of the first task so that the first task starts\r
+ * executing.\r
+ */\r
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * @note This is a privileged function and should only be called from the kenrel\r
+ * code.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Starts the first task.\r
+ */\r
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Disables interrupts.\r
+ */\r
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enables interrupts.\r
+ */\r
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief PendSV Exception handler.\r
+ */\r
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SVC Handler.\r
+ */\r
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Allocate a Secure context for the calling task.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the\r
+ * secure side for the calling task.\r
+ */\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Free the task's secure context.\r
+ *\r
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\r
+ */\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+#endif /* __PORT_ASM_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M33"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
extern uint32_t * __privileged_functions_start__;\r
extern uint32_t * __privileged_functions_end__;\r
extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ extern uint32_t * __unprivileged_flash_start__;\r
extern uint32_t * __unprivileged_flash_end__;\r
extern uint32_t * __privileged_sram_start__;\r
extern uint32_t * __privileged_sram_end__;\r
extern uint32_t __privileged_functions_start__[];\r
extern uint32_t __privileged_functions_end__[];\r
extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ extern uint32_t __unprivileged_flash_start__[];\r
extern uint32_t __unprivileged_flash_end__[];\r
extern uint32_t __privileged_sram_start__[];\r
extern uint32_t __privileged_sram_end__[];\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
- /* Setup unprivileged flash and system calls flash as Read Only by\r
- * both privileged and unprivileged tasks. All tasks can read it but\r
- * no-one can modify. */\r
+ /* Setup unprivileged flash as Read Only by both privileged and\r
+ * unprivileged tasks. All tasks can read it but no-one can modify. */\r
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
( portMPU_REGION_NON_SHAREABLE ) |\r
( portMPU_REGION_READ_ONLY );\r
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
+ /* Setup unprivileged syscalls flash as Read Only by both privileged\r
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
/* Setup RAM containing kernel data for privileged access only. */\r
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
- /* By default allow everything to access the general peripherals.\r
- * The system peripherals and registers are protected. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX1 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
/* Enable mem fault. */\r
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
\r
/* Standard includes. */\r
#include <stdint.h>\r
\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
+ * is defined correctly and privileged functions are placed in correct sections. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
/* Portasm includes. */\r
#include "portasm.h"\r
\r
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
+ * header files. */\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
" ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
" adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
" ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
" ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
" ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
" stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
"pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
"xSecureContextConst2: .word xSecureContext \n"\r
#if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"\r
"xMAIR0Const2: .word 0xe000edc0 \n"\r
"xRNRConst2: .word 0xe000ed98 \n"\r
"xRBARConst2: .word 0xe000ed9c \n"\r
" ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
" adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
" ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
" ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
" ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
" stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
"pxCurrentTCBConst: .word pxCurrentTCB \n"\r
"xSecureContextConst: .word xSecureContext \n"\r
#if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst: .word 0xe000ed94 \n"\r
"xMAIR0Const: .word 0xe000edc0 \n"\r
"xRNRConst: .word 0xe000ed98 \n"\r
"xRBARConst: .word 0xe000ed9c \n"\r
/* MPU regions. */\r
#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
-#define portPRIVILEGED_RAM_REGION ( 2UL )\r
-#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
#define portSTACK_REGION ( 4UL )\r
#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
-/* Devices Region. */\r
-#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
-#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
-\r
/* Device memory attributes used in MPU_MAIR registers.\r
*\r
* 8-bit values encoded as follows:\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
+/**\r
+ * @brief Barriers.\r
+ */\r
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
\r
#ifdef __cplusplus\r
}\r
extern uint32_t * __privileged_functions_start__;\r
extern uint32_t * __privileged_functions_end__;\r
extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ extern uint32_t * __unprivileged_flash_start__;\r
extern uint32_t * __unprivileged_flash_end__;\r
extern uint32_t * __privileged_sram_start__;\r
extern uint32_t * __privileged_sram_end__;\r
extern uint32_t __privileged_functions_start__[];\r
extern uint32_t __privileged_functions_end__[];\r
extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ extern uint32_t __unprivileged_flash_start__[];\r
extern uint32_t __unprivileged_flash_end__[];\r
extern uint32_t __privileged_sram_start__[];\r
extern uint32_t __privileged_sram_end__[];\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
- /* Setup unprivileged flash and system calls flash as Read Only by\r
- * both privileged and unprivileged tasks. All tasks can read it but\r
- * no-one can modify. */\r
+ /* Setup unprivileged flash as Read Only by both privileged and\r
+ * unprivileged tasks. All tasks can read it but no-one can modify. */\r
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
( portMPU_REGION_NON_SHAREABLE ) |\r
( portMPU_REGION_READ_ONLY );\r
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
+ /* Setup unprivileged syscalls flash as Read Only by both privileged\r
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
/* Setup RAM containing kernel data for privileged access only. */\r
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
- /* By default allow everything to access the general peripherals.\r
- * The system peripherals and registers are protected. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX1 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
/* Enable mem fault. */\r
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
\r
/* Standard includes. */\r
#include <stdint.h>\r
\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
+ * is defined correctly and privileged functions are placed in correct sections. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
/* Portasm includes. */\r
#include "portasm.h"\r
\r
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
+ * header files. */\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
__asm volatile\r
" ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
" adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
" ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
" ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
" ldmia r1!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
" stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
" .align 4 \n"\r
"pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
#if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"\r
"xMAIR0Const2: .word 0xe000edc0 \n"\r
"xRNRConst2: .word 0xe000ed98 \n"\r
"xRBARConst2: .word 0xe000ed9c \n"\r
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Disable MPU. */\r
+ " \n"\r
" adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
" ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
" ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
" ldmia r1!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
" stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ " \n"\r
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */\r
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ " str r4, [r2] \n" /* Enable MPU. */\r
+ " dsb \n" /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
" \n"\r
#if( configENABLE_MPU == 1 )\r
" \n"\r
" .align 4 \n"\r
"pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMPUCTRLConst: .word 0xe000ed94 \n"\r
"xMAIR0Const: .word 0xe000edc0 \n"\r
"xRNRConst: .word 0xe000ed98 \n"\r
"xRBARConst: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
);\r
}\r
/*-----------------------------------------------------------*/\r
{\r
__asm volatile\r
(\r
- " tst lr, #4 \n"\r
- " ite eq \n"\r
- " mrseq r0, msp \n"\r
- " mrsne r0, psp \n"\r
- " ldr r1, svchandler_address_const \n"\r
- " bx r1 \n"\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, svchandler_address_const \n"\r
+ " bx r1 \n"\r
" \n"\r
- " .align 4 \n"\r
+ " .align 4 \n"\r
"svchandler_address_const: .word vPortSVCHandler_C \n"\r
);\r
}\r
/* MPU regions. */\r
#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
-#define portPRIVILEGED_RAM_REGION ( 2UL )\r
-#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
#define portSTACK_REGION ( 4UL )\r
#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
-/* Devices Region. */\r
-#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
-#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
-\r
/* Device memory attributes used in MPU_MAIR registers.\r
*\r
* 8-bit values encoded as follows:\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
+/**\r
+ * @brief Barriers.\r
+ */\r
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
\r
#ifdef __cplusplus\r
}\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+ * all the API functions to use the MPU wrappers. That should only be done when\r
+ * task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/**\r
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
+ * i.e. the processor boots as secure and never jumps to the non-secure side.\r
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
+ * on the secure side. The following are the valid configuration seetings:\r
+ *\r
+ * 1. Run FreeRTOS on the Secure Side:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
+ *\r
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
+ *\r
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
+ */\r
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the NVIC.\r
+ */\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the MPU.\r
+ */\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+\r
+/* Enable privileged access to unmapped region. */\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+\r
+/* Enable MPU. */\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
+\r
+/* Expected value of the portMPU_TYPE register. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to set up the initial stack.\r
+ */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF FD\r
+ * 1111 1111 1111 1111 1111 1111 1111 1101\r
+ *\r
+ * Bit[6] - 1 --> The exception was taken from the Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 1 --> The exception was taken to the Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )\r
+#else\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#endif /* configRUN_FREERTOS_SECURE_ONLY */\r
+\r
+/**\r
+ * @brief CONTROL register privileged bit mask.\r
+ *\r
+ * Bit[0] in CONTROL register tells the privilege:\r
+ * Bit[0] = 0 ==> The task is privileged.\r
+ * Bit[0] = 1 ==> The task is not privileged.\r
+ */\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+\r
+/**\r
+ * @brief Initial CONTROL register values.\r
+ */\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+\r
+/**\r
+ * @brief Let the user override the pre-loading of the initial LR with the\r
+ * address of prvTaskExitError() in case it messes up unwinding of the stack\r
+ * in the debugger.\r
+ */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/**\r
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
+ * when a task is created. This helps in debugging at the cost of code size.\r
+ */\r
+#define portPRELOAD_REGISTERS 1\r
+\r
+/**\r
+ * @brief A task is created without a secure context, and must call\r
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
+ * any secure calls.\r
+ */\r
+#define portNO_SECURE_CONTEXT 0\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Used to catch tasks that attempt to return from their implementing\r
+ * function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_MPU */\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_FPU */\r
+\r
+/**\r
+ * @brief Yield the processor.\r
+ */\r
+void vPortYield( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enter critical section.\r
+ */\r
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Exit from critical section.\r
+ */\r
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SysTick handler.\r
+ */\r
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief C part of SVC handler.\r
+ */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Each task maintains its own interrupt status in the critical nesting\r
+ * variable.\r
+ */\r
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+volatile uint32_t ulDummy = 0UL;\r
+\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ extern uint32_t * __unprivileged_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ extern uint32_t __unprivileged_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash as Read Only by both privileged and\r
+ * unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged syscalls flash as Read Only by both privileged\r
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
+#endif /* configENABLE_FPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
+\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+uint32_t ulPreviousMask;\r
+\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+{\r
+#if( configENABLE_MPU == 1 )\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+#endif /* configENABLE_MPU */\r
+\r
+uint32_t ulPC;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
+#endif /* configENABLE_TRUSTZONE */\r
+uint8_t ucSVCNumber;\r
+\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+#else\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+#endif /* configENABLE_MPU */\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __PORT_ASM_H__\r
+#define __PORT_ASM_H__\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/**\r
+ * @brief Restore the context of the first task so that the first task starts\r
+ * executing.\r
+ */\r
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * @note This is a privileged function and should only be called from the kenrel\r
+ * code.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Starts the first task.\r
+ */\r
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Disables interrupts.\r
+ */\r
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enables interrupts.\r
+ */\r
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief PendSV Exception handler.\r
+ */\r
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SVC Handler.\r
+ */\r
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Allocate a Secure context for the calling task.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the\r
+ * secure side for the calling task.\r
+ */\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Free the task's secure context.\r
+ *\r
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\r
+ */\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+#endif /* __PORT_ASM_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ EXTERN pxCurrentTCB\r
+ EXTERN xSecureContext\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+ EXTERN SecureContext_SaveContext\r
+ EXTERN SecureContext_LoadContext\r
+\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vPortAllocateSecureContext\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
+ PUBLIC vPortFreeSecureContext\r
+\r
+#if ( configENABLE_FPU == 1 )\r
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/*---------------- Unprivileged Functions -------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+xIsPrivileged:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ movs r1, #1 /* r1 = 1. */\r
+ tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\r
+ beq running_privileged /* If the result of previous AND operation was 0, branch. */\r
+ movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
+ running_privileged:\r
+ movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vResetPrivilege:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ movs r1, #1 /* r1 = 1. */\r
+ orrs r0, r1 /* r0 = r0 | r1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vPortAllocateSecureContext:\r
+ svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/*----------------- Privileged Functions --------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+vRestoreContextOfFirstTask:\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r5, #1 /* r5 = 1. */\r
+ bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\r
+ str r4, [r2] /* Disable MPU. */\r
+\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ movs r5, #4 /* r5 = 4. */\r
+ str r5, [r2] /* Program RNR = 4. */\r
+ ldmia r3!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write first set of RBAR/RLAR registers. */\r
+ movs r5, #5 /* r5 = 5. */\r
+ str r5, [r2] /* Program RNR = 5. */\r
+ ldmia r3!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write second set of RBAR/RLAR registers. */\r
+ movs r5, #6 /* r5 = 6. */\r
+ str r5, [r2] /* Program RNR = 6. */\r
+ ldmia r3!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write third set of RBAR/RLAR registers. */\r
+ movs r5, #7 /* r5 = 7. */\r
+ str r5, [r2] /* Program RNR = 7. */\r
+ ldmia r3!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r5, #1 /* r5 = 1. */\r
+ orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\r
+ str r4, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ ldr r5, =xSecureContext\r
+ str r1, [r5] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ msr control, r3 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r4 /* Finally, branch to EXC_RETURN. */\r
+#else /* configENABLE_MPU */\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ ldr r4, =xSecureContext\r
+ str r1, [r4] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+vRaisePrivilege:\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ movs r1, #1 /* r1 = 1. */\r
+ bics r0, r1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vStartFirstTask:\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+/*-----------------------------------------------------------*/\r
+\r
+ulSetInterruptMaskFromISR:\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+vClearInterruptMaskFromISR:\r
+ msr PRIMASK, r0\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+PendSV_Handler:\r
+ mrs r1, psp /* Read PSP in r1. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+\r
+ cbz r0, save_ns_context /* No secure context to save. */\r
+ push {r0-r2, r14}\r
+ bl SecureContext_SaveContext\r
+ pop {r0-r3} /* LR is now in r3. */\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
+#if ( configENABLE_MPU == 1 )\r
+ subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+#else /* configENABLE_MPU */\r
+ subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+#endif /* configENABLE_MPU */\r
+ b select_next_task\r
+\r
+ save_ns_context:\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
+ #if ( configENABLE_MPU == 1 )\r
+ subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ adds r1, r1, #16 /* r1 = r1 + 16. */\r
+ stmia r1!, {r4-r7} /* Store the low registers that are not saved automatically. */\r
+ mov r4, r8 /* r4 = r8. */\r
+ mov r5, r9 /* r5 = r9. */\r
+ mov r6, r10 /* r6 = r10. */\r
+ mov r7, r11 /* r7 = r11. */\r
+ stmia r1!, {r4-r7} /* Store the high registers that are not saved automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ subs r1, r1, #48 /* r1 = r1 - 48. */\r
+ stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */\r
+ mov r4, r8 /* r4 = r8. */\r
+ mov r5, r9 /* r5 = r9. */\r
+ mov r6, r10 /* r6 = r10. */\r
+ mov r7, r11 /* r7 = r11. */\r
+ stmia r1!, {r4-r7} /* Store the high registers that are not saved automatically. */\r
+ #endif /* configENABLE_MPU */\r
+\r
+ select_next_task:\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
+\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+\r
+ #if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r5, #1 /* r5 = 1. */\r
+ bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\r
+ str r4, [r2] /* Disable MPU. */\r
+\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ movs r5, #4 /* r5 = 4. */\r
+ str r5, [r2] /* Program RNR = 4. */\r
+ ldmia r3!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write first set of RBAR/RLAR registers. */\r
+ movs r5, #5 /* r5 = 5. */\r
+ str r5, [r2] /* Program RNR = 5. */\r
+ ldmia r3!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write second set of RBAR/RLAR registers. */\r
+ movs r5, #6 /* r5 = 6. */\r
+ str r5, [r2] /* Program RNR = 6. */\r
+ ldmia r3!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write third set of RBAR/RLAR registers. */\r
+ movs r5, #7 /* r5 = 7. */\r
+ str r5, [r2] /* Program RNR = 7. */\r
+ ldmia r3!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */\r
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r4!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r5, #1 /* r5 = 1. */\r
+ orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\r
+ str r4, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
+ #endif /* configENABLE_MPU */\r
+\r
+ #if ( configENABLE_MPU == 1 )\r
+ ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r3 /* Restore the CONTROL register value for the task. */\r
+ mov lr, r4 /* LR = r4. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r4}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r4}\r
+ mov lr, r4 /* LR = r4. */\r
+ lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #else /* configENABLE_MPU */\r
+ ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ mov lr, r3 /* LR = r3. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r3}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r3}\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #endif /* configENABLE_MPU */\r
+\r
+ restore_ns_context:\r
+ adds r1, r1, #16 /* Move to the high registers. */\r
+ ldmia r1!, {r4-r7} /* Restore the high registers that are not automatically restored. */\r
+ mov r8, r4 /* r8 = r4. */\r
+ mov r9, r5 /* r9 = r5. */\r
+ mov r10, r6 /* r10 = r6. */\r
+ mov r11, r7 /* r11 = r7. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ subs r1, r1, #32 /* Go back to the low registers. */\r
+ ldmia r1!, {r4-r7} /* Restore the low registers that are not automatically restored. */\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+SVC_Handler:\r
+ movs r0, #4\r
+ mov r1, lr\r
+ tst r0, r1\r
+ beq stacking_used_msp\r
+ mrs r0, psp\r
+ b vPortSVCHandler_C\r
+ stacking_used_msp:\r
+ mrs r0, msp\r
+ b vPortSVCHandler_C\r
+/*-----------------------------------------------------------*/\r
+\r
+vPortFreeSecureContext:\r
+ ldr r1, [r0] /* The first item in the TCB is the top of the stack. */\r
+ ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */\r
+ cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */\r
+ beq free_secure_context\r
+ bx lr /* There is no secure context (xSecureContext is NULL). */\r
+ free_secure_context:\r
+ svc 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M33"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure heap includes. */\r
+#include "secure_heap.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief CONTROL value for privileged tasks.\r
+ *\r
+ * Bit[0] - 0 --> Thread mode is privileged.\r
+ * Bit[1] - 1 --> Thread mode uses PSP.\r
+ */\r
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02\r
+\r
+/**\r
+ * @brief CONTROL value for un-privileged tasks.\r
+ *\r
+ * Bit[0] - 1 --> Thread mode is un-privileged.\r
+ * Bit[1] - 1 --> Thread mode uses PSP.\r
+ */\r
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Structure to represent secure context.\r
+ *\r
+ * @note Since stack grows down, pucStackStart is the highest address while\r
+ * pucStackLimit is the first addess of the allocated memory.\r
+ */\r
+typedef struct SecureContext\r
+{\r
+ uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\r
+ uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */\r
+ uint8_t *pucStackStart; /**< First location of the stack memory. */\r
+} SecureContext_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* No stack for thread mode until a task's context is loaded. */\r
+ secureportSET_PSPLIM( securecontextNO_STACK );\r
+ secureportSET_PSP( securecontextNO_STACK );\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Configure thread mode to use PSP and to be unprivileged. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Configure thread mode to use PSP and to be privileged.. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )\r
+#else /* configENABLE_MPU */\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )\r
+#endif /* configENABLE_MPU */\r
+{\r
+ uint8_t *pucStackMemory = NULL;\r
+ uint32_t ulIPSR;\r
+ SecureContextHandle_t xSecureContextHandle = NULL;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t *pulCurrentStackPointer = NULL;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Allocate the context structure. */\r
+ xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );\r
+\r
+ if( xSecureContextHandle != NULL )\r
+ {\r
+ /* Allocate the stack space. */\r
+ pucStackMemory = pvPortMalloc( ulSecureStackSize );\r
+\r
+ if( pucStackMemory != NULL )\r
+ {\r
+ /* Since stack grows down, the starting point will be the last\r
+ * location. Note that this location is next to the last\r
+ * allocated byte because the hardware decrements the stack\r
+ * pointer before writing i.e. if stack pointer is 0x2, a push\r
+ * operation will decrement the stack pointer to 0x1 and then\r
+ * write at 0x1. */\r
+ xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;\r
+\r
+ /* The stack cannot go beyond this location. This value is\r
+ * programmed in the PSPLIM register on context switch.*/\r
+ xSecureContextHandle->pucStackLimit = pucStackMemory;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Store the correct CONTROL value for the task on the stack.\r
+ * This value is programmed in the CONTROL register on\r
+ * context switch. */\r
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;\r
+ pulCurrentStackPointer--;\r
+ if( ulIsTaskPrivileged )\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\r
+ }\r
+ else\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\r
+ }\r
+\r
+ /* Store the current stack pointer. This value is programmed in\r
+ * the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Current SP is set to the starting of the stack. This\r
+ * value programmed in the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;\r
+\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+ else\r
+ {\r
+ /* Free the context to avoid memory leak and make sure to return\r
+ * NULL to indicate failure. */\r
+ vPortFree( xSecureContextHandle );\r
+ xSecureContextHandle = NULL;\r
+ }\r
+ }\r
+ }\r
+\r
+ return xSecureContextHandle;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Ensure that valid parameters are passed. */\r
+ secureportASSERT( xSecureContextHandle != NULL );\r
+\r
+ /* Free the stack space. */\r
+ vPortFree( xSecureContextHandle->pucStackLimit );\r
+\r
+ /* Free the context itself. */\r
+ vPortFree( xSecureContextHandle );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_CONTEXT_H__\r
+#define __SECURE_CONTEXT_H__\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOSConfig.h"\r
+\r
+/**\r
+ * @brief PSP value when no task's context is loaded.\r
+ */\r
+#define securecontextNO_STACK 0x0\r
+\r
+/**\r
+ * @brief Opaque handle.\r
+ */\r
+struct SecureContext;\r
+typedef struct SecureContext* SecureContextHandle_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Initializes the secure context management system.\r
+ *\r
+ * PSP is set to NULL and therefore a task must allocate and load a context\r
+ * before calling any secure side function in the thread mode.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureContext_Init( void );\r
+\r
+/**\r
+ * @brief Allocates a context on the secure side.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\r
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\r
+ *\r
+ * @return Opaque context handle if context is successfully allocated, NULL\r
+ * otherwise.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );\r
+#else /* configENABLE_MPU */\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );\r
+#endif /* configENABLE_MPU */\r
+\r
+/**\r
+ * @brief Frees the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the\r
+ * context to be freed.\r
+ */\r
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+/**\r
+ * @brief Loads the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the context\r
+ * to be loaded.\r
+ */\r
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+/**\r
+ * @brief Saves the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the context\r
+ * to be saved.\r
+ */\r
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+#endif /* __SECURE_CONTEXT_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/* Functions implemented in assembler file. */\r
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );\r
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ SecureContext_LoadContextAsm( xSecureContextHandle );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ SecureContext_SaveContextAsm( xSecureContextHandle );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+\r
+ PUBLIC SecureContext_LoadContextAsm\r
+ PUBLIC SecureContext_SaveContextAsm\r
+\r
+#if ( configENABLE_FPU == 1 )\r
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+SecureContext_LoadContextAsm:\r
+ /* xSecureContextHandle value is in r0. */\r
+ mrs r1, ipsr /* r1 = IPSR. */\r
+ cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
+ ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+#if ( configENABLE_MPU == 1 )\r
+ ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+ msr control, r3 /* CONTROL = r3. */\r
+#endif /* configENABLE_MPU */\r
+ msr psplim, r2 /* PSPLIM = r2. */\r
+ msr psp, r1 /* PSP = r1. */\r
+\r
+ load_ctx_therad_mode:\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+SecureContext_SaveContextAsm:\r
+ /* xSecureContextHandle value is in r0. */\r
+ mrs r1, ipsr /* r1 = IPSR. */\r
+ cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
+ mrs r1, psp /* r1 = PSP. */\r
+#if ( configENABLE_MPU == 1 )\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */\r
+ str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ stmia r1!, {r2} /* Store CONTROL value on the stack. */\r
+#else /* configENABLE_MPU */\r
+ str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+#endif /* configENABLE_MPU */\r
+ movs r1, #0 /* r1 = securecontextNO_STACK. */\r
+ msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */\r
+ msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+\r
+ save_ctx_therad_mode:\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Secure context heap includes. */\r
+#include "secure_heap.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief Total heap size.\r
+ */\r
+#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )\r
+\r
+/* No test marker by default. */\r
+#ifndef mtCOVERAGE_TEST_MARKER\r
+ #define mtCOVERAGE_TEST_MARKER()\r
+#endif\r
+\r
+/* No tracing by default. */\r
+#ifndef traceMALLOC\r
+ #define traceMALLOC( pvReturn, xWantedSize )\r
+#endif\r
+\r
+/* No tracing by default. */\r
+#ifndef traceFREE\r
+ #define traceFREE( pv, xBlockSize )\r
+#endif\r
+\r
+/* Block sizes must not get too small. */\r
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )\r
+\r
+/* Assumes 8bit bytes! */\r
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Allocate the memory for the heap. */\r
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )\r
+ /* The application writer has already defined the array used for the RTOS\r
+ * heap - probably so it can be placed in a special segment or address. */\r
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+#else /* configAPPLICATION_ALLOCATED_HEAP */\r
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+#endif /* configAPPLICATION_ALLOCATED_HEAP */\r
+\r
+/**\r
+ * @brief The linked list structure.\r
+ *\r
+ * This is used to link free blocks in order of their memory address.\r
+ */\r
+typedef struct A_BLOCK_LINK\r
+{\r
+ struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */\r
+ size_t xBlockSize; /**< The size of the free block. */\r
+} BlockLink_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Called automatically to setup the required heap structures the first\r
+ * time pvPortMalloc() is called.\r
+ */\r
+static void prvHeapInit( void );\r
+\r
+/**\r
+ * @brief Inserts a block of memory that is being freed into the correct\r
+ * position in the list of free memory blocks.\r
+ *\r
+ * The block being freed will be merged with the block in front it and/or the\r
+ * block behind it if the memory blocks are adjacent to each other.\r
+ *\r
+ * @param[in] pxBlockToInsert The block being freed.\r
+ */\r
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief The size of the structure placed at the beginning of each allocated\r
+ * memory block must by correctly byte aligned.\r
+ */\r
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+\r
+/**\r
+ * @brief Create a couple of list links to mark the start and end of the list.\r
+ */\r
+static BlockLink_t xStart, *pxEnd = NULL;\r
+\r
+/**\r
+ * @brief Keeps track of the number of free bytes remaining, but says nothing\r
+ * about fragmentation.\r
+ */\r
+static size_t xFreeBytesRemaining = 0U;\r
+static size_t xMinimumEverFreeBytesRemaining = 0U;\r
+\r
+/**\r
+ * @brief Gets set to the top bit of an size_t type.\r
+ *\r
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set\r
+ * then the block belongs to the application. When the bit is free the block is\r
+ * still part of the free heap space.\r
+ */\r
+static size_t xBlockAllocatedBit = 0;\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHeapInit( void )\r
+{\r
+BlockLink_t *pxFirstFreeBlock;\r
+uint8_t *pucAlignedHeap;\r
+size_t uxAddress;\r
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\r
+\r
+ /* Ensure the heap starts on a correctly aligned boundary. */\r
+ uxAddress = ( size_t ) ucHeap;\r
+\r
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\r
+ {\r
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\r
+ }\r
+\r
+ pucAlignedHeap = ( uint8_t * ) uxAddress;\r
+\r
+ /* xStart is used to hold a pointer to the first item in the list of free\r
+ * blocks. The void cast is used to prevent compiler warnings. */\r
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
+ xStart.xBlockSize = ( size_t ) 0;\r
+\r
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted\r
+ * at the end of the heap space. */\r
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\r
+ uxAddress -= xHeapStructSize;\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ pxEnd = ( void * ) uxAddress;\r
+ pxEnd->xBlockSize = 0;\r
+ pxEnd->pxNextFreeBlock = NULL;\r
+\r
+ /* To start with there is a single free block that is sized to take up the\r
+ * entire heap space, minus the space taken by pxEnd. */\r
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\r
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\r
+\r
+ /* Only one block exists - and it covers the entire usable heap space. */\r
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+\r
+ /* Work out the position of the top bit in a size_t variable. */\r
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )\r
+{\r
+BlockLink_t *pxIterator;\r
+uint8_t *puc;\r
+\r
+ /* Iterate through the list until a block is found that has a higher address\r
+ * than the block being inserted. */\r
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\r
+ {\r
+ /* Nothing to do here, just iterate to the right position. */\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted after\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxIterator;\r
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\r
+ {\r
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\r
+ pxBlockToInsert = pxIterator;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted before\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxBlockToInsert;\r
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\r
+ {\r
+ if( pxIterator->pxNextFreeBlock != pxEnd )\r
+ {\r
+ /* Form one big block from the two blocks. */\r
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the block being inserted plugged a gab, so was merged with the block\r
+ * before and the block after, then it's pxNextFreeBlock pointer will have\r
+ * already been set, and should not be set here as that would make it point\r
+ * to itself. */\r
+ if( pxIterator != pxBlockToInsert )\r
+ {\r
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvPortMalloc( size_t xWantedSize )\r
+{\r
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
+void *pvReturn = NULL;\r
+\r
+ /* If this is the first call to malloc then the heap will require\r
+ * initialisation to setup the list of free blocks. */\r
+ if( pxEnd == NULL )\r
+ {\r
+ prvHeapInit();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Check the requested block size is not so large that the top bit is set.\r
+ * The top bit of the block size member of the BlockLink_t structure is used\r
+ * to determine who owns the block - the application or the kernel, so it\r
+ * must be free. */\r
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\r
+ {\r
+ /* The wanted size is increased so it can contain a BlockLink_t\r
+ * structure in addition to the requested amount of bytes. */\r
+ if( xWantedSize > 0 )\r
+ {\r
+ xWantedSize += xHeapStructSize;\r
+\r
+ /* Ensure that blocks are always aligned to the required number of\r
+ * bytes. */\r
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\r
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\r
+ {\r
+ /* Traverse the list from the start (lowest address) block until\r
+ * one of adequate size is found. */\r
+ pxPreviousBlock = &xStart;\r
+ pxBlock = xStart.pxNextFreeBlock;\r
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
+ {\r
+ pxPreviousBlock = pxBlock;\r
+ pxBlock = pxBlock->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the end marker was reached then a block of adequate size was\r
+ * not found. */\r
+ if( pxBlock != pxEnd )\r
+ {\r
+ /* Return the memory space pointed to - jumping over the\r
+ * BlockLink_t structure at its start. */\r
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\r
+\r
+ /* This block is being returned for use so must be taken out\r
+ * of the list of free blocks. */\r
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
+\r
+ /* If the block is larger than required it can be split into\r
+ * two. */\r
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\r
+ {\r
+ /* This block is to be split into two. Create a new\r
+ * block following the number of bytes requested. The void\r
+ * cast is used to prevent byte alignment warnings from the\r
+ * compiler. */\r
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+\r
+ /* Calculate the sizes of two blocks split from the single\r
+ * block. */\r
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
+ pxBlock->xBlockSize = xWantedSize;\r
+\r
+ /* Insert the new block into the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( pxNewBlockLink );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ xFreeBytesRemaining -= pxBlock->xBlockSize;\r
+\r
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\r
+ {\r
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* The block is being returned - it is allocated and owned by\r
+ * the application and has no "next" block. */\r
+ pxBlock->xBlockSize |= xBlockAllocatedBit;\r
+ pxBlock->pxNextFreeBlock = NULL;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ traceMALLOC( pvReturn, xWantedSize );\r
+\r
+ #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\r
+ {\r
+ if( pvReturn == NULL )\r
+ {\r
+ extern void vApplicationMallocFailedHook( void );\r
+ vApplicationMallocFailedHook();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ return pvReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFree( void *pv )\r
+{\r
+uint8_t *puc = ( uint8_t * ) pv;\r
+BlockLink_t *pxLink;\r
+\r
+ if( pv != NULL )\r
+ {\r
+ /* The memory being freed will have an BlockLink_t structure immediately\r
+ * before it. */\r
+ puc -= xHeapStructSize;\r
+\r
+ /* This casting is to keep the compiler from issuing warnings. */\r
+ pxLink = ( void * ) puc;\r
+\r
+ /* Check the block is actually allocated. */\r
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\r
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );\r
+\r
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\r
+ {\r
+ if( pxLink->pxNextFreeBlock == NULL )\r
+ {\r
+ /* The block is being returned to the heap - it is no longer\r
+ * allocated. */\r
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;\r
+\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS();\r
+ {\r
+ /* Add this block to the list of free blocks. */\r
+ xFreeBytesRemaining += pxLink->xBlockSize;\r
+ traceFREE( pv, pxLink->xBlockSize );\r
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
+ }\r
+ secureportENABLE_NON_SECURE_INTERRUPTS();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+size_t xPortGetFreeHeapSize( void )\r
+{\r
+ return xFreeBytesRemaining;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+size_t xPortGetMinimumEverFreeHeapSize( void )\r
+{\r
+ return xMinimumEverFreeBytesRemaining;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortInitialiseBlocks( void )\r
+{\r
+ /* This just exists to keep the linker quiet. */\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_HEAP_H__\r
+#define __SECURE_HEAP_H__\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/**\r
+ * @brief Allocates memory from heap.\r
+ *\r
+ * @param[in] xWantedSize The size of the memory to be allocated.\r
+ *\r
+ * @return Pointer to the memory region if the allocation is successful, NULL\r
+ * otherwise.\r
+ */\r
+void *pvPortMalloc( size_t xWantedSize );\r
+\r
+/**\r
+ * @brief Frees the previously allocated memory.\r
+ *\r
+ * @param[in] pv Pointer to the memory to be freed.\r
+ */\r
+void vPortFree( void *pv );\r
+\r
+#endif /* __SECURE_HEAP_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Secure init includes. */\r
+#include "secure_init.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */\r
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )\r
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )\r
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define secureinitFPCCR_LSPENS_POS ( 29UL )\r
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )\r
+#define secureinitFPCCR_TS_POS ( 26UL )\r
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )\r
+\r
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */\r
+#define secureinitNSACR_CP10_POS ( 10UL )\r
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )\r
+#define secureinitNSACR_CP11_POS ( 11UL )\r
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
+ * permitted. CP11 should be programmed to the same value as CP10. */\r
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
+\r
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
+ * that we can enable/disable lazy stacking in port.c file. */\r
+ *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
+\r
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
+ * registers (S16-S31) are also pushed to stack on exception entry and\r
+ * restored on exception return. */\r
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_INIT_H__\r
+#define __SECURE_INIT_H__\r
+\r
+/**\r
+ * @brief De-prioritizes the non-secure exceptions.\r
+ *\r
+ * This is needed to ensure that the non-secure PendSV runs at the lowest\r
+ * priority. Context switch is done in the non-secure PendSV handler.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureInit_DePrioritizeNSExceptions( void );\r
+\r
+/**\r
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\r
+ *\r
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\r
+ * Registers are not leaked to the non-secure side.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureInit_EnableNSFPUAccess( void );\r
+\r
+#endif /* __SECURE_INIT_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_PORT_MACROS_H__\r
+#define __SECURE_PORT_MACROS_H__\r
+\r
+/**\r
+ * @brief Byte alignment requirements.\r
+ */\r
+#define secureportBYTE_ALIGNMENT 8\r
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )\r
+\r
+/**\r
+ * @brief Macro to declare a function as non-secure callable.\r
+ */\r
+#if defined( __IAR_SYSTEMS_ICC__ )\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+#else\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+#endif\r
+\r
+/**\r
+ * @brief Set the secure PRIMASK value.\r
+ */\r
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\r
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+\r
+/**\r
+ * @brief Set the non-secure PRIMASK value.\r
+ */\r
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\r
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+\r
+/**\r
+ * @brief Read the PSP value in the given variable.\r
+ */\r
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\r
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the PSP to the given value.\r
+ */\r
+#define secureportSET_PSP( pucCurrentStackPointer ) \\r
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the PSPLIM to the given value.\r
+ */\r
+#define secureportSET_PSPLIM( pucStackLimit ) \\r
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )\r
+\r
+/**\r
+ * @brief Set the NonSecure MSP to the given value.\r
+ */\r
+#define secureportSET_MSP_NS( pucMainStackPointer ) \\r
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the CONTROL register to the given value.\r
+ */\r
+#define secureportSET_CONTROL( ulControl ) \\r
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )\r
+\r
+/**\r
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given\r
+ * variable.\r
+ */\r
+#define secureportREAD_IPSR( ulIPSR ) \\r
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )\r
+\r
+/**\r
+ * @brief PRIMASK value to enable interrupts.\r
+ */\r
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0\r
+\r
+/**\r
+ * @brief PRIMASK value to disable interrupts.\r
+ */\r
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1\r
+\r
+/**\r
+ * @brief Disable secure interrupts.\r
+ */\r
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Disable non-secure interrupts.\r
+ *\r
+ * This effectively disables context switches.\r
+ */\r
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Enable non-secure interrupts.\r
+ */\r
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Assert definition.\r
+ */\r
+#define secureportASSERT( x ) \\r
+ if( ( x ) == 0 ) \\r
+ { \\r
+ secureportDISABLE_SECURE_INTERRUPTS(); \\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \\r
+ for( ;; ); \\r
+ }\r
+\r
+#endif /* __SECURE_PORT_MACROS_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+ * all the API functions to use the MPU wrappers. That should only be done when\r
+ * task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/**\r
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
+ * i.e. the processor boots as secure and never jumps to the non-secure side.\r
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
+ * on the secure side. The following are the valid configuration seetings:\r
+ *\r
+ * 1. Run FreeRTOS on the Secure Side:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
+ *\r
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
+ *\r
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
+ */\r
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the NVIC.\r
+ */\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the MPU.\r
+ */\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+\r
+/* Enable privileged access to unmapped region. */\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+\r
+/* Enable MPU. */\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
+\r
+/* Expected value of the portMPU_TYPE register. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to set up the initial stack.\r
+ */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF FD\r
+ * 1111 1111 1111 1111 1111 1111 1111 1101\r
+ *\r
+ * Bit[6] - 1 --> The exception was taken from the Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 1 --> The exception was taken to the Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )\r
+#else\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#endif /* configRUN_FREERTOS_SECURE_ONLY */\r
+\r
+/**\r
+ * @brief CONTROL register privileged bit mask.\r
+ *\r
+ * Bit[0] in CONTROL register tells the privilege:\r
+ * Bit[0] = 0 ==> The task is privileged.\r
+ * Bit[0] = 1 ==> The task is not privileged.\r
+ */\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+\r
+/**\r
+ * @brief Initial CONTROL register values.\r
+ */\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+\r
+/**\r
+ * @brief Let the user override the pre-loading of the initial LR with the\r
+ * address of prvTaskExitError() in case it messes up unwinding of the stack\r
+ * in the debugger.\r
+ */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/**\r
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
+ * when a task is created. This helps in debugging at the cost of code size.\r
+ */\r
+#define portPRELOAD_REGISTERS 1\r
+\r
+/**\r
+ * @brief A task is created without a secure context, and must call\r
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
+ * any secure calls.\r
+ */\r
+#define portNO_SECURE_CONTEXT 0\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Used to catch tasks that attempt to return from their implementing\r
+ * function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_MPU */\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_FPU */\r
+\r
+/**\r
+ * @brief Yield the processor.\r
+ */\r
+void vPortYield( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enter critical section.\r
+ */\r
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Exit from critical section.\r
+ */\r
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SysTick handler.\r
+ */\r
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief C part of SVC handler.\r
+ */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Each task maintains its own interrupt status in the critical nesting\r
+ * variable.\r
+ */\r
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+volatile uint32_t ulDummy = 0UL;\r
+\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ extern uint32_t * __unprivileged_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ extern uint32_t __unprivileged_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash as Read Only by both privileged and\r
+ * unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged syscalls flash as Read Only by both privileged\r
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
+#endif /* configENABLE_FPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
+\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+uint32_t ulPreviousMask;\r
+\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+{\r
+#if( configENABLE_MPU == 1 )\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+#endif /* configENABLE_MPU */\r
+\r
+uint32_t ulPC;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
+#endif /* configENABLE_TRUSTZONE */\r
+uint8_t ucSVCNumber;\r
+\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+#else\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+#endif /* configENABLE_MPU */\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __PORT_ASM_H__\r
+#define __PORT_ASM_H__\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/**\r
+ * @brief Restore the context of the first task so that the first task starts\r
+ * executing.\r
+ */\r
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * @note This is a privileged function and should only be called from the kenrel\r
+ * code.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Starts the first task.\r
+ */\r
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Disables interrupts.\r
+ */\r
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enables interrupts.\r
+ */\r
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief PendSV Exception handler.\r
+ */\r
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SVC Handler.\r
+ */\r
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Allocate a Secure context for the calling task.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the\r
+ * secure side for the calling task.\r
+ */\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Free the task's secure context.\r
+ *\r
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\r
+ */\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+#endif /* __PORT_ASM_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ EXTERN pxCurrentTCB\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
+\r
+#if ( configENABLE_FPU == 1 )\r
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/*---------------- Unprivileged Functions -------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+xIsPrivileged:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ movs r1, #1 /* r1 = 1. */\r
+ tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\r
+ beq running_privileged /* If the result of previous AND operation was 0, branch. */\r
+ movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
+ running_privileged:\r
+ movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ bx lr /* Return. */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vResetPrivilege:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ movs r1, #1 /* r1 = 1. */\r
+ orrs r0, r1 /* r0 = r0 | r1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/*----------------- Privileged Functions --------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+vRestoreContextOfFirstTask:\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r4, #1 /* r4 = 1. */\r
+ bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\r
+ str r3, [r2] /* Disable MPU. */\r
+\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */\r
+ movs r4, #5 /* r4 = 5. */\r
+ str r4, [r2] /* Program RNR = 5. */\r
+ ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */\r
+ movs r4, #6 /* r4 = 6. */\r
+ str r4, [r2] /* Program RNR = 6. */\r
+ ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */\r
+ movs r4, #7 /* r4 = 7. */\r
+ str r4, [r2] /* Program RNR = 7. */\r
+ ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r4, #1 /* r4 = 1. */\r
+ orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\r
+ str r3, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ msr control, r2 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
+#else /* configENABLE_MPU */\r
+ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r2 /* Finally, branch to EXC_RETURN. */\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+vRaisePrivilege:\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ movs r1, #1 /* r1 = 1. */\r
+ bics r0, r1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vStartFirstTask:\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+ nop\r
+/*-----------------------------------------------------------*/\r
+\r
+ulSetInterruptMaskFromISR:\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+vClearInterruptMaskFromISR:\r
+ msr PRIMASK, r0\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+PendSV_Handler:\r
+ mrs r0, psp /* Read PSP in r0. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+#if ( configENABLE_MPU == 1 )\r
+ subs r0, r0, #44 /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ str r0, [r1] /* Save the new top of stack in TCB. */\r
+ mrs r1, psplim /* r1 = PSPLIM. */\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r0!, {r1-r7} /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */\r
+ mov r4, r8 /* r4 = r8. */\r
+ mov r5, r9 /* r5 = r9. */\r
+ mov r6, r10 /* r6 = r10. */\r
+ mov r7, r11 /* r7 = r11. */\r
+ stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */\r
+#else /* configENABLE_MPU */\r
+ subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */\r
+ str r0, [r1] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */\r
+ mov r4, r8 /* r4 = r8. */\r
+ mov r5, r9 /* r5 = r9. */\r
+ mov r6, r10 /* r6 = r10. */\r
+ mov r7, r11 /* r7 = r11. */\r
+ stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */\r
+#endif /* configENABLE_MPU */\r
+\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
+\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r4, #1 /* r4 = 1. */\r
+ bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\r
+ str r3, [r2] /* Disable MPU. */\r
+\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */\r
+ movs r4, #5 /* r4 = 5. */\r
+ str r4, [r2] /* Program RNR = 5. */\r
+ ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */\r
+ movs r4, #6 /* r4 = 6. */\r
+ str r4, [r2] /* Program RNR = 6. */\r
+ ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */\r
+ movs r4, #7 /* r4 = 7. */\r
+ str r4, [r2] /* Program RNR = 7. */\r
+ ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */\r
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */\r
+ stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */\r
+ movs r4, #1 /* r4 = 1. */\r
+ orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\r
+ str r3, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ adds r0, r0, #28 /* Move to the high registers. */\r
+ ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */\r
+ mov r8, r4 /* r8 = r4. */\r
+ mov r9, r5 /* r9 = r5. */\r
+ mov r10, r6 /* r10 = r6. */\r
+ mov r11, r7 /* r11 = r7. */\r
+ msr psp, r0 /* Remember the new top of stack for the task. */\r
+ subs r0, r0, #44 /* Move to the starting of the saved context. */\r
+ ldmia r0!, {r1-r7} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */\r
+ msr psplim, r1 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r2 /* Restore the CONTROL register value for the task. */\r
+ bx r3\r
+#else /* configENABLE_MPU */\r
+ adds r0, r0, #24 /* Move to the high registers. */\r
+ ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */\r
+ mov r8, r4 /* r8 = r4. */\r
+ mov r9, r5 /* r9 = r5. */\r
+ mov r10, r6 /* r10 = r6. */\r
+ mov r11, r7 /* r11 = r7. */\r
+ msr psp, r0 /* Remember the new top of stack for the task. */\r
+ subs r0, r0, #40 /* Move to the starting of the saved context. */\r
+ ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ bx r3\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+SVC_Handler:\r
+ movs r0, #4\r
+ mov r1, lr\r
+ tst r0, r1\r
+ beq stacking_used_msp\r
+ mrs r0, psp\r
+ b vPortSVCHandler_C\r
+ stacking_used_msp:\r
+ mrs r0, msp\r
+ b vPortSVCHandler_C\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M33"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
extern uint32_t * __privileged_functions_start__;\r
extern uint32_t * __privileged_functions_end__;\r
extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ extern uint32_t * __unprivileged_flash_start__;\r
extern uint32_t * __unprivileged_flash_end__;\r
extern uint32_t * __privileged_sram_start__;\r
extern uint32_t * __privileged_sram_end__;\r
extern uint32_t __privileged_functions_start__[];\r
extern uint32_t __privileged_functions_end__[];\r
extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ extern uint32_t __unprivileged_flash_start__[];\r
extern uint32_t __unprivileged_flash_end__[];\r
extern uint32_t __privileged_sram_start__[];\r
extern uint32_t __privileged_sram_end__[];\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
- /* Setup unprivileged flash and system calls flash as Read Only by\r
- * both privileged and unprivileged tasks. All tasks can read it but\r
- * no-one can modify. */\r
+ /* Setup unprivileged flash as Read Only by both privileged and\r
+ * unprivileged tasks. All tasks can read it but no-one can modify. */\r
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
( portMPU_REGION_NON_SHAREABLE ) |\r
( portMPU_REGION_READ_ONLY );\r
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
+ /* Setup unprivileged syscalls flash as Read Only by both privileged\r
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
/* Setup RAM containing kernel data for privileged access only. */\r
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
- /* By default allow everything to access the general peripherals.\r
- * The system peripherals and registers are protected. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX1 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
/* Enable mem fault. */\r
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
\r
ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ str r4, [r2] /* Disable MPU. */\r
+\r
adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */\r
stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ str r4, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ str r4, [r2] /* Disable MPU. */\r
+\r
adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ str r4, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
/* MPU regions. */\r
#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
-#define portPRIVILEGED_RAM_REGION ( 2UL )\r
-#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
#define portSTACK_REGION ( 4UL )\r
#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
-/* Devices Region. */\r
-#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
-#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
-\r
/* Device memory attributes used in MPU_MAIR registers.\r
*\r
* 8-bit values encoded as follows:\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
#ifdef __cplusplus\r
}\r
#endif\r
extern uint32_t * __privileged_functions_start__;\r
extern uint32_t * __privileged_functions_end__;\r
extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ extern uint32_t * __unprivileged_flash_start__;\r
extern uint32_t * __unprivileged_flash_end__;\r
extern uint32_t * __privileged_sram_start__;\r
extern uint32_t * __privileged_sram_end__;\r
extern uint32_t __privileged_functions_start__[];\r
extern uint32_t __privileged_functions_end__[];\r
extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ extern uint32_t __unprivileged_flash_start__[];\r
extern uint32_t __unprivileged_flash_end__[];\r
extern uint32_t __privileged_sram_start__[];\r
extern uint32_t __privileged_sram_end__[];\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
- /* Setup unprivileged flash and system calls flash as Read Only by\r
- * both privileged and unprivileged tasks. All tasks can read it but\r
- * no-one can modify. */\r
+ /* Setup unprivileged flash as Read Only by both privileged and\r
+ * unprivileged tasks. All tasks can read it but no-one can modify. */\r
portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
( portMPU_REGION_NON_SHAREABLE ) |\r
( portMPU_REGION_READ_ONLY );\r
portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
+ /* Setup unprivileged syscalls flash as Read Only by both privileged\r
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
/* Setup RAM containing kernel data for privileged access only. */\r
portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
( portMPU_RLAR_ATTR_INDEX0 ) |\r
( portMPU_RLAR_REGION_ENABLE );\r
\r
- /* By default allow everything to access the general peripherals.\r
- * The system peripherals and registers are protected. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX1 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
/* Enable mem fault. */\r
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
\r
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ str r4, [r2] /* Disable MPU. */\r
+\r
adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ str r4, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
+ dmb /* Complete outstanding transfers before disabling MPU. */\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
+ str r4, [r2] /* Disable MPU. */\r
+\r
adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+\r
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */\r
+ orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
+ str r4, [r2] /* Enable MPU. */\r
+ dsb /* Force memory writes before continuing. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
/* MPU regions. */\r
#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
-#define portPRIVILEGED_RAM_REGION ( 2UL )\r
-#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
#define portSTACK_REGION ( 4UL )\r
#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
-/* Devices Region. */\r
-#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
-#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
-\r
/* Device memory attributes used in MPU_MAIR registers.\r
*\r
* 8-bit values encoded as follows:\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
#ifdef __cplusplus\r
}\r
#endif\r
projects / freertos / commitdiff