--- /dev/null
+/**************************************************************************//**\r
+ * @file fmc_reg.h\r
+ * @version V1.00\r
+ * @brief FMC register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __FMC_REG_H__\r
+#define __FMC_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- Flash Memory Controller -------------------------*/\r
+/**\r
+ @addtogroup FMC Flash Memory Controller(FMC)\r
+ Memory Mapped Structure for FMC Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var FMC_T::ISPCTL\r
+ * Offset: 0x00 ISP Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ISPEN |ISP Enable Bit (Write Protect)\r
+ * | | |ISP function enable bit. Set this bit to enable ISP function.\r
+ * | | |0 = ISP function Disabled.\r
+ * | | |1 = ISP function Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[1] |BS |Boot Select (Write Protect)\r
+ * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively\r
+ * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from\r
+ * | | |This bit is initiated with the inverse value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened\r
+ * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.\r
+ * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[3] |APUEN |APROM Update Enable Bit (Write Protect)\r
+ * | | |0 = APROM cannot be updated when the chip runs in APROM.\r
+ * | | |1 = APROM can be updated when the chip runs in APROM.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)\r
+ * | | |0 = CONFIG cannot be updated.\r
+ * | | |1 = CONFIG can be updated.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)\r
+ * | | |LDROM update enable bit.\r
+ * | | |0 = LDROM cannot be updated.\r
+ * | | |1 = LDROM can be updated.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[6] |ISPFF |ISP Fail Flag (Write Protect)\r
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:\r
+ * | | |This bit needs to be cleared by writing 1 to it.\r
+ * | | |(1) APROM writes to itself if APUEN is set to 0.\r
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.\r
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.\r
+ * | | |(4) Page Erase command at LOCK mode with ICE connection\r
+ * | | |(5) Erase or Program command at brown-out detected\r
+ * | | |(6) Destination address is illegal, such as over an available range.\r
+ * | | |(7) Invalid ISP commands\r
+ * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1\r
+ * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1\r
+ * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1\r
+ * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0\r
+ * | | |(12) Read any content of boot loader with ICE connection\r
+ * | | |(13) The address of block erase and bank erase is not in APROM\r
+ * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command\r
+ * | | |(15) The wrong setting of page erase ISP CMD in XOM\r
+ * | | |(16) Violate XOM setting one time protection\r
+ * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page\r
+ * | | |(18) Mass erase when MERASE (CFG0[13]) is disable\r
+ * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[16] |BL |Boot Loader Booting (Write Protect)\r
+ * | | |This bit is initiated with the inverses value of MBS (CONFIG0[5])\r
+ * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded\r
+ * | | |This bit is used to check chip boot from Boot Loader or not\r
+ * | | |User should keep original value of this bit when updating FMC_ISPCTL register.\r
+ * | | |0 = Booting from APROM or LDROM.\r
+ * | | |1 = Booting from Boot Loader.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[24] |INTEN |Interrupt Enable (Write Protect)\r
+ * | | |0 = ISP INT Disabled.\r
+ * | | |1 = ISP INT Enabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. Before use INT, user need to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time.\r
+ * @var FMC_T::ISPADDR\r
+ * Offset: 0x04 ISP Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ISPADDR |ISP Address\r
+ * | | |The NuMicro M2351 series is equipped with embedded flash\r
+ * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation\r
+ * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.\r
+ * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 KBytes alignment is necessary for CRC32 checksum calculation.\r
+ * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte)\r
+ * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte).\r
+ * @var FMC_T::ISPDAT\r
+ * Offset: 0x08 ISP Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ISPDAT |ISP Data\r
+ * | | |Write data to this register before ISP program operation.\r
+ * | | |Read data from this register after ISP read operation.\r
+ * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff\r
+ * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 2 KBytes alignment\r
+ * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result\r
+ * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect\r
+ * | | |For XOM page erase function, , ISPDAT = 0x0055_aa03.\r
+ * @var FMC_T::ISPCMD\r
+ * Offset: 0x0C ISP Command Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[6:0] |CMD |ISP Command\r
+ * | | |ISP command table is shown below:\r
+ * | | |0x00= FLASH Read.\r
+ * | | |0x04= Read Unique ID.\r
+ * | | |0x08= Read Flash All-One Result.\r
+ * | | |0x0B= Read Company ID.\r
+ * | | |0x0C= Read Device ID.\r
+ * | | |0x0D= Read Checksum.\r
+ * | | |0x21= FLASH 32-bit Program.\r
+ * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP.\r
+ * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1.\r
+ * | | |0x25= FLASH Block Erase Erase four pages alignment of APROM in BANK0 or BANK1..\r
+ * | | |0x27= FLASH Multi-Word Program.\r
+ * | | |0x28= Run Flash All-One Verification.\r
+ * | | |0x2D= Run Checksum Calculation.\r
+ * | | |0x2E= Vector Remap.\r
+ * | | |0x40= FLASH 64-bit Read.\r
+ * | | |0x61= FLASH 64-bit Program.\r
+ * | | |The other commands are invalid.\r
+ * @var FMC_T::ISPTRG\r
+ * Offset: 0x10 ISP Trigger Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ISPGO |ISP Start Trigger (Write Protect)\r
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished\r
+ * | | |When ISPGO=1, the operation of accessing value from address FMC_BA+0x00 to FMC_BA+0x68 would halt CPU still ISPGO =0\r
+ * | | |If user want to monitor whether ISP finish or not,user can access FMC_MPSTS[0] MPBUSY.\r
+ * | | |0 = ISP operation is finished.\r
+ * | | |1 = ISP is progressed.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * @var FMC_T::ISPSTS\r
+ * Offset: 0x40 ISP Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |ISPBUSY |ISP Busy Flag (Read Only)\r
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\r
+ * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).\r
+ * | | |0 = ISP operation is finished.\r
+ * | | |1 = ISP is progressed.\r
+ * |[2] |CBS |Boot Selection of CONFIG (Read Only)\r
+ * | | |This bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.\r
+ * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.\r
+ * | | |0 = LDROM with IAP mode.\r
+ * | | |1 = APROM with IAP mode.\r
+ * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)\r
+ * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened\r
+ * | | |0 = Booting from Boot Loader.\r
+ * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting)\r
+ * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only)\r
+ * | | |This bit is set if flash access cycle auto-tuning function is disabled\r
+ * | | |The auto-tuning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.\r
+ * | | |0 = Flash access cycle auto-tuning is Enabled.\r
+ * | | |1 = Flash access cycle auto-tuning is Disabled.\r
+ * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only)\r
+ * | | |This bit is set if data is mismatched at ISP programming verification\r
+ * | | |This bit is clear by performing ISP flash erase or ISP read CID operation\r
+ * | | |0 = Flash Program is success.\r
+ * | | |1 = Flash Program is fail. Program data is different with data in the flash memory\r
+ * |[6] |ISPFF |ISP Fail Flag (Write Protect)\r
+ * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] if this bit is set.\r
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:\r
+ * | | |(1) APROM writes to itself if APUEN is set to 0.\r
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.\r
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.\r
+ * | | |(4) Page Erase command at LOCK mode with ICE connection\r
+ * | | |(5) Erase or Program command at brown-out detected\r
+ * | | |(6) Destination address is illegal, such as over an available range.\r
+ * | | |(7) Invalid ISP commands\r
+ * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1\r
+ * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1\r
+ * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1\r
+ * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0.\r
+ * | | |(12) Read any content of boot loader with ICE connection\r
+ * | | |(13) The address of block erase and bank erase is not in APROM\r
+ * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command\r
+ * | | |(15) The wrong setting of page erase ISP CMD in XOM\r
+ * | | |(16) Violate XOM setting one time protection\r
+ * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page\r
+ * | | |(18) Mass erase when MERASE (CFG0[13]) is disable\r
+ * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[7] |ALLONE |Flash All-one Verification Flag\r
+ * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete; this bit also can be clear by writing 1\r
+ * | | |0 = All of flash bits are 1 after Run Flash All-One Verification complete.\r
+ * | | |1 = Flash bits are not all 1 after Run Flash All-One Verification complete.\r
+ * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)\r
+ * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}\r
+ * |[24] |INTFLAG |Interrupt Flag\r
+ * | | |0 = ISP is not finish.\r
+ * | | |1 = ISP done or ISPFF set.\r
+ * @var FMC_T::CYCCTL\r
+ * Offset: 0x4C Flash Access Cycle Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect)\r
+ * | | |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1).\r
+ * | | |When auto-tuning function disabled, user needs to check the speed of HCLK and set the cycle >0.\r
+ * | | |0000 = CPU access with zero wait cycle ; Flash access cycle is 1. The HCLK working frequency range is <27MHz; Cache is disabled by hardware.\r
+ * | | |0001 = CPU access with one wait cycle if cache miss; Flash access cycle is 1. The HCLK working frequency range range is<27MHz.\r
+ * | | |0010 = CPU access with two wait cycles if cache miss; Flash access cycle is 2. The optimized HCLK working frequency range is 25~52 MHz.\r
+ * | | |0011 = CPU access with three wait cycles if cache miss; Flash access cycle is 3. The optimized HCLK working frequency range is 49~79MHz.\r
+ * | | |Others = Reserved.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * |[8] |FADIS |Flash Access Cycle Auto-tuning Disabled Control (Write Protect)\r
+ * | | |Set this bit to disable flash access cycle auto-tuning function\r
+ * | | |0 = Flash access cycle auto-tuning is enabled.\r
+ * | | |1 = Flash access cycle auto-tuning is disabled.\r
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.\r
+ * @var FMC_T::KPKEY0\r
+ * Offset: 0x50 KPROM KEY0 Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only)\r
+ * | | |Write KPKEY0 data to this register before KEY Comparison operation.\r
+ * @var FMC_T::KPKEY1\r
+ * Offset: 0x54 KPROM KEY1 Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only)\r
+ * | | |Write KPKEY1 data to this register before KEY Comparison operation.\r
+ * @var FMC_T::KPKEY2\r
+ * Offset: 0x58 KPROM KEY2 Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only)\r
+ * | | |Write KPKEY2 data to this register before KEY Comparison operation.\r
+ * @var FMC_T::KPKEYTRG\r
+ * Offset: 0x5C KPROM KEY Comparison Trigger Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection)\r
+ * | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished\r
+ * | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0.\r
+ * | | |0 = KEY comparison operation is finished.\r
+ * | | |1 = KEY comparison is progressed.\r
+ * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.\r
+ * |[1] |TCEN |Timeout Counting Enable (Write Protection)\r
+ * | | |0 = Timeout counting is disabled.\r
+ * | | |1 = Timeout counting is enabled if input key is matched after key comparison finish.\r
+ * | | |10 minutes is at least for timeout, and average is about 20 minutes.\r
+ * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.\r
+ * @var FMC_T::KPKEYSTS\r
+ * Offset: 0x60 KPROM KEY Comparison Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |KEYBUSY |KEY Comparison Busy (Read Only)\r
+ * | | |0 = KEY comparison is finished.\r
+ * | | |1 = KEY comparison is busy.\r
+ * |[1] |KEYLOCK |KEY LOCK Flag\r
+ * | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection\r
+ * | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0\r
+ * | | |This bit also can be set to 1 while\r
+ * | | |l CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or\r
+ * | | |l KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or\r
+ * | | |l KEYENROM is programmed a non-0x5a value or\r
+ * | | |l Timeout event or\r
+ * | | |l FORBID(FMC_KPKEYSTS[3]) is 1\r
+ * | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection.\r
+ * | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection.\r
+ * | | |CONFIG write protect is depended on CFGFLAG\r
+ * |[2] |KEYMATCH |KEY Match Flag (Read Only)\r
+ * | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched\r
+ * | | |This bit is also cleared to 0 while\r
+ * | | |l CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or\r
+ * | | |l Timeout event or\r
+ * | | |l KPROM is erased or\r
+ * | | |l KEYENROM is programmed to a non-0x5a value.\r
+ * | | |l Chip is in power down mode.\r
+ * | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting.\r
+ * | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting.\r
+ * |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only)\r
+ * | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]).\r
+ * | | |0 = KEY comparison is not forbidden.\r
+ * | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger.\r
+ * |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only)\r
+ * | | |This bit is set while the KEYENROM [7:0] is not 0x5a at power-on or reset\r
+ * | | |This bit is cleared to 0 by hardware while KPROM is erased\r
+ * | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0x5a value.\r
+ * | | |0 = Security Key protection is disabled.\r
+ * | | |1 = Security Key protection is enabled.\r
+ * |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only)\r
+ * | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset\r
+ * | | |This bit is cleared to 0 by hardware while KPROM is erased\r
+ * | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0.\r
+ * | | |0 = CONFIG write-protection is disabled.\r
+ * | | |1 = CONFIG write-protection is enabled.\r
+ * |[8] |SBKPBUSY |Secure Boot Key Programming BUSY (Read Only)\r
+ * | | |This bit is set to 1 while secure boot key program function is running\r
+ * | | |This bit is cleared to 0 while secure boot key key program function had been done.\r
+ * | | |0 = Secure boot key program function is done.\r
+ * | | |1 = Secure boot key program function is busy.\r
+ * |[9] |SBKPFLAG |Secure Boot Key Programming Flag (Read Only)\r
+ * | | |This bit is set to 1 while secure boot key program function fails\r
+ * | | |This bit is cleared to 0 while secure boot key had been programmed into flash memory.\r
+ * | | |0 = Secure boot key program function is successful.\r
+ * | | |1 = Secure boot key program function fails.\r
+ * @var FMC_T::KPKEYCNT\r
+ * Offset: 0x64 KPROM KEY-Unmatched Counting Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only)\r
+ * | | |KPKECNT is increased when entry keys is wrong in Security Key protection\r
+ * | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on.\r
+ * |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only)\r
+ * | | |KPKEMAX is the maximum error key entry number at each power-on\r
+ * | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated\r
+ * | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting\r
+ * | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX.\r
+ * @var FMC_T::KPCNT\r
+ * Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only)\r
+ * | | |KPCNT is the power-on counting for error key entry in Security Key protection\r
+ * | | |KPCNT is cleared to 0 if key comparison is matched.\r
+ * |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only)\r
+ * | | |KPMAX is the power-on maximum number for error key entry\r
+ * | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated\r
+ * | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting\r
+ * | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX\r
+ * @var FMC_T::MPDAT0\r
+ * Offset: 0x80 ISP Data0 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ISPDAT0 |ISP Data 0\r
+ * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data\r
+ * @var FMC_T::MPDAT1\r
+ * Offset: 0x84 ISP Data1 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ISPDAT1 |ISP Data 1\r
+ * | | |This register is the second 32-bit data for 64-bit/multi-word programming.\r
+ * @var FMC_T::MPDAT2\r
+ * Offset: 0x88 ISP Data2 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ISPDAT2 |ISP Data 2\r
+ * | | |This register is the third 32-bit data for multi-word programming.\r
+ * @var FMC_T::MPDAT3\r
+ * Offset: 0x8C ISP Data3 Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |ISPDAT3 |ISP Data 3\r
+ * | | |This register is the fourth 32-bit data for multi-word programming.\r
+ * @var FMC_T::MPSTS\r
+ * Offset: 0xC0 ISP Multi-Program Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only)\r
+ * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\r
+ * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).\r
+ * | | |0 = ISP Multi-Word program operation is finished.\r
+ * | | |1 = ISP Multi-Word program operation is progressed.\r
+ * |[1] |PPGO |ISP Multi-program Status (Read Only)\r
+ * | | |0 = ISP multi-word program operation is not active.\r
+ * | | |1 = ISP multi-word program operation is in progress.\r
+ * |[2] |ISPFF |ISP Fail Flag (Read Only)\r
+ * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]\r
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:\r
+ * | | |(1) APROM writes to itself if APUEN is set to 0.\r
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.\r
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.\r
+ * | | |(4) Page Erase command at LOCK mode with ICE connection\r
+ * | | |(5) Erase or Program command at brown-out detected\r
+ * | | |(6) Destination address is illegal, such as over an available range.\r
+ * | | |(7) Invalid ISP commands\r
+ * |[4] |D0 |ISP DATA 0 Flag (Read Only)\r
+ * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.\r
+ * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.\r
+ * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.\r
+ * |[5] |D1 |ISP DATA 1 Flag (Read Only)\r
+ * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.\r
+ * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.\r
+ * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.\r
+ * |[6] |D2 |ISP DATA 2 Flag (Read Only)\r
+ * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.\r
+ * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.\r
+ * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.\r
+ * |[7] |D3 |ISP DATA 3 Flag (Read Only)\r
+ * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.\r
+ * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.\r
+ * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.\r
+ * @var FMC_T::MPADDR\r
+ * Offset: 0xC4 ISP Multi-Program Address Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[31:0] |MPADDR |ISP Multi-word Program Address\r
+ * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\r
+ * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.\r
+ * @var FMC_T::XOMR0STS\r
+ * Offset: 0xD0 XOM Region 0 Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |SIZE |XOM Region 0 Size (Page-aligned)\r
+ * | | |SIZE is the page number of XOM Region 0.\r
+ * |[31:8] |BASE |XOM Region 0 Base Address (Page-aligned)\r
+ * | | |BASE is the base address of XOM Region 0.\r
+ * @var FMC_T::XOMR1STS\r
+ * Offset: 0xD4 XOM Region 1 Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |SIZE |XOM Region 1 Size (Page-aligned)\r
+ * | | |SIZE is the page number of XOM Region 1.\r
+ * |[31:8] |BASE |XOM Region 1 Base Address (Page-aligned)\r
+ * | | |BASE is the base address of XOM Region 1.\r
+ * @var FMC_T::XOMR2STS\r
+ * Offset: 0xD8 XOM Region 2 Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |SIZE |XOM Region 2 Size (Page-aligned)\r
+ * | | |SIZE is the page number of XOM Region 2.\r
+ * |[31:8] |BASE |XOM Region 2 Base Address (Page-aligned)\r
+ * | | |BASE is the base address of XOM Region 2.\r
+ * @var FMC_T::XOMR3STS\r
+ * Offset: 0xDC XOM Region 3 Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[7:0] |SIZE |XOM Region 3 Size (Page-aligned)\r
+ * | | |SIZE is the page number of XOM Region 3.\r
+ * |[31:8] |BASE |XOM Region 3 Base Address (Page-aligned)\r
+ * | | |BASE is the base address of XOM Region 3.\r
+ * @var FMC_T::XOMSTS\r
+ * Offset: 0xE0 XOM Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |XOMR0ON |XOM Region 0 On\r
+ * | | |XOM Region 0 active status.\r
+ * | | |0 = No active.\r
+ * | | |1 = XOM region 0 is active.\r
+ * |[1] |XOMR1ON |XOM Region 1 On\r
+ * | | |XOM Region 1 active status.\r
+ * | | |0 = No active.\r
+ * | | |1 = XOM region 1 is active.\r
+ * |[2] |XOMR2ON |XOM Region 2 On\r
+ * | | |XOM Region 2 active status.\r
+ * | | |0 = No active.\r
+ * | | |1 = XOM region 2 is active.\r
+ * |[3] |XOMR3ON |XOM Region 3 On\r
+ * | | |XOM Region 3 active status.\r
+ * | | |0 = No active.\r
+ * | | |1 = XOM region 3 is active.\r
+ * |[4] |XOMPEF |XOM Page Erase Function Fail\r
+ * | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.\r
+ * | | |0 = Success.\r
+ * | | |1 = Fail.\r
+ */\r
+ __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */\r
+ __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */\r
+ __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */\r
+ __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */\r
+ __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */\r
+ __I uint32_t RESERVE0[11];\r
+ __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */\r
+ __I uint32_t RESERVE1[2];\r
+ __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */\r
+ __O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */\r
+ __O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */\r
+ __O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */\r
+ __IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */\r
+ __IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */\r
+ __I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */\r
+ __I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */\r
+ __I uint32_t RESERVE2[5];\r
+ __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */\r
+ __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */\r
+ __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */\r
+ __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */\r
+ __I uint32_t RESERVE3[12];\r
+ __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */\r
+ __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */\r
+ __I uint32_t RESERVE4[2];\r
+ __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */\r
+ __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */\r
+ __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */\r
+ __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */\r
+ __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */\r
+\r
+} FMC_T;\r
+\r
+/**\r
+ @addtogroup FMC_CONST FMC Bit Field Definition\r
+ Constant Definitions for FMC Controller\r
+@{ */\r
+\r
+#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */\r
+#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */\r
+\r
+#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */\r
+#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */\r
+\r
+#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */\r
+#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */\r
+\r
+#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */\r
+#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */\r
+\r
+#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */\r
+#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */\r
+\r
+#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */\r
+#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */\r
+\r
+#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */\r
+#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */\r
+\r
+#define FMC_ISPCTL_INTEN_Pos (24) /*!< FMC_T::ISPCTL: INTEN Position */\r
+#define FMC_ISPCTL_INTEN_Msk (0x1ul << FMC_ISPCTL_INTEN_Pos) /*!< FMC_T::ISPCTL: INTEN Mask */\r
+\r
+#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */\r
+#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */\r
+\r
+#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */\r
+#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */\r
+\r
+#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */\r
+#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */\r
+\r
+#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */\r
+#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */\r
+\r
+#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */\r
+#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */\r
+\r
+#define FMC_ISPSTS_CBS_Pos (2) /*!< FMC_T::ISPSTS: CBS Position */\r
+#define FMC_ISPSTS_CBS_Msk (0x1ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */\r
+\r
+#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */\r
+#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */\r
+\r
+#define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */\r
+#define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */\r
+\r
+#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */\r
+#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */\r
+\r
+#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */\r
+#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */\r
+\r
+#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */\r
+#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */\r
+\r
+#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */\r
+#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */\r
+\r
+#define FMC_ISPSTS_INTFLAG_Pos (24) /*!< FMC_T::ISPSTS: INTFLAG Position */\r
+#define FMC_ISPSTS_INTFLAG_Msk (0x1ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Mask */\r
+\r
+#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */\r
+#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */\r
+\r
+#define FMC_CYCCTL_FADIS_Pos (8) /*!< FMC_T::CYCCTL: FADIS Position */\r
+#define FMC_CYCCTL_FADIS_Msk (0x1ul << FMC_CYCCTL_FADIS_Pos) /*!< FMC_T::CYCCTL: FADIS Mask */\r
+\r
+#define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */\r
+#define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */\r
+\r
+#define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */\r
+#define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */\r
+\r
+#define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */\r
+#define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */\r
+\r
+#define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */\r
+#define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */\r
+\r
+#define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */\r
+#define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */\r
+\r
+#define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */\r
+#define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */\r
+\r
+#define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */\r
+#define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */\r
+\r
+#define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */\r
+#define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */\r
+\r
+#define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */\r
+#define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */\r
+\r
+#define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */\r
+#define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */\r
+\r
+#define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */\r
+#define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */\r
+\r
+#define FMC_KPKEYSTS_SBKPBUSY_Pos (8) /*!< FMC_T::KPKEYSTS: SBKPBUSY Position */\r
+#define FMC_KPKEYSTS_SBKPBUSY_Msk (0x1ul << FMC_KPKEYSTS_SBKPBUSY_Pos) /*!< FMC_T::KPKEYSTS: SBKPBUSY Mask */\r
+\r
+#define FMC_KPKEYSTS_SBKPFLAG_Pos (9) /*!< FMC_T::KPKEYSTS: SBKPFLAG Position */\r
+#define FMC_KPKEYSTS_SBKPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SBKPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SBKPFLAG Mask */\r
+\r
+#define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */\r
+#define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */\r
+\r
+#define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */\r
+#define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */\r
+\r
+#define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */\r
+#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */\r
+\r
+#define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */\r
+#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */\r
+\r
+#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */\r
+#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */\r
+\r
+#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */\r
+#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */\r
+\r
+#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */\r
+#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */\r
+\r
+#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */\r
+#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */\r
+\r
+#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */\r
+#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */\r
+\r
+#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */\r
+#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */\r
+\r
+#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */\r
+#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */\r
+\r
+#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */\r
+#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */\r
+\r
+#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */\r
+#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */\r
+\r
+#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */\r
+#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */\r
+\r
+#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */\r
+#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */\r
+\r
+#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */\r
+#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */\r
+\r
+#define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */\r
+#define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */\r
+\r
+#define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */\r
+#define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */\r
+\r
+#define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */\r
+#define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */\r
+\r
+#define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */\r
+#define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */\r
+\r
+#define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */\r
+#define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */\r
+\r
+#define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */\r
+#define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOMR2STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */\r
+\r
+#define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */\r
+#define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */\r
+\r
+#define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */\r
+#define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */\r
+\r
+#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */\r
+#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */\r
+\r
+#define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */\r
+#define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */\r
+\r
+#define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */\r
+#define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */\r
+\r
+#define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */\r
+#define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */\r
+\r
+#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */\r
+#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */\r
+\r
+/**@}*/ /* FMC_CONST */\r
+/**@}*/ /* end of FMC register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+#endif /* __FMC_REG_H__ */\r
projects / freertos / blobdiff