Add Cortex M23 GCC and IAR ports. Add demo projects for Nuvoton NuMaker-PFM-2351.

[freertos] / FreeRTOS / Demo / CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC / Nuvoton_Code / Device / Nuvoton / M2351 / Include / hdiv_reg.h

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Nuvoton_Code/Device/Nuvoton/M2351/Include/hdiv_reg.h b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Nuvoton_Code/Device/Nuvoton/M2351/Include/hdiv_reg.h
new file mode 100644 (file)
index 0000000..a7c5f1a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Nuvoton_Code/Device/Nuvoton/M2351/Include/hdiv_reg.h
@@ -0,0 +1,111 @@
+/**************************************************************************//**\r
+ * @file     hdiv_reg.h\r
+ * @version  V1.00\r
+ * @brief    HDIV register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __HDIV_REG_H__\r
+#define __HDIV_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+  @{\r
+\r
+*/\r
+\r
+/*---------------------- Hardware Divider --------------------------------*/\r
+/**\r
+    @addtogroup HDIV Hardware Divider(HDIV)\r
+    Memory Mapped Structure for HDIV Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+    /**\r
+     * @var HDIV_T::DIVIDEND\r
+     * Offset: 0x00  Dividend Source Register\r
+     * ---------------------------------------------------------------------------------------------------\r
+     * |Bits    |Field     |Descriptions\r
+     * | :----: | :----:   | :---- |\r
+     * |[31:0]  |DIVIDEND  |Dividend Source\r
+     * |        |          |This register is given the dividend of divider before calculation starting.\r
+     * @var HDIV_T::DIVISOR\r
+     * Offset: 0x04  Divisor Source Resister\r
+     * ---------------------------------------------------------------------------------------------------\r
+     * |Bits    |Field     |Descriptions\r
+     * | :----: | :----:   | :---- |\r
+     * |[15:0]  |DIVISOR   |Divisor Source\r
+     * |        |          |This register is given the divisor of divider before calculation starts.\r
+     * |        |          |Note: When this register is written, hardware divider will start calculate.\r
+     * @var HDIV_T::DIVQUO\r
+     * Offset: 0x08  Quotient Result Resister\r
+     * ---------------------------------------------------------------------------------------------------\r
+     * |Bits    |Field     |Descriptions\r
+     * | :----: | :----:   | :---- |\r
+     * |[31:0]  |QUOTIENT  |Quotient Result\r
+     * |        |          |This register holds the quotient result of divider after calculation complete.\r
+     * @var HDIV_T::DIVREM\r
+     * Offset: 0x0C  Remainder Result Register\r
+     * ---------------------------------------------------------------------------------------------------\r
+     * |Bits    |Field     |Descriptions\r
+     * | :----: | :----:   | :---- |\r
+     * |[31:0]  |REMAINDER |Remainder Result\r
+     * |        |          |The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete.\r
+     * |        |          |The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer.\r
+     * |        |          |This register holds the remainder result of divider after calculation complete.\r
+     * @var HDIV_T::DIVSTS\r
+     * Offset: 0x10  Divider Status Register\r
+     * ---------------------------------------------------------------------------------------------------\r
+     * |Bits    |Field     |Descriptions\r
+     * | :----: | :----:   | :---- |\r
+     * |[0]     |FINISH    |Division Finish Flag\r
+     * |        |          |0 = Under Calculation.\r
+     * |        |          |1 = Calculation finished.\r
+     * |        |          |The flag will become low when the divider is in calculation.\r
+     * |        |          |The flag will go back to high once the calculation finished.\r
+     * |[1]     |DIV0      |Divisor Zero Warning\r
+     * |        |          |0 = The divisor is not 0.\r
+     * |        |          |1 = The divisor is 0.\r
+     * |        |          |Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written\r
+     * |        |          |This register is read only.\r
+     */\r
+    __IO uint32_t DIVIDEND;              /*!< [0x0000] Dividend Source Register                                         */\r
+    __IO uint32_t DIVISOR;               /*!< [0x0004] Divisor Source Resister                                          */\r
+    __IO uint32_t DIVQUO;                /*!< [0x0008] Quotient Result Resister                                         */\r
+    __IO uint32_t DIVREM;                /*!< [0x000c] Remainder Result Register                                        */\r
+    __I  uint32_t DIVSTS;                /*!< [0x0010] Divider Status Register                                          */\r
+\r
+} HDIV_T;\r
+\r
+/**\r
+    @addtogroup HDIV_CONST HDIV Bit Field Definition\r
+    Constant Definitions for HDIV Controller\r
+@{ */\r
+\r
+#define HDIV_DIVIDEND_DIVIDEND_Pos       (0)                                               /*!< HDIV_T::DIVIDEND: DIVIDEND Position    */\r
+#define HDIV_DIVIDEND_DIVIDEND_Msk       (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos)      /*!< HDIV_T::DIVIDEND: DIVIDEND Mask        */\r
+\r
+#define HDIV_DIVISOR_DIVISOR_Pos         (0)                                               /*!< HDIV_T::DIVISOR: DIVISOR Position      */\r
+#define HDIV_DIVISOR_DIVISOR_Msk         (0xfffful << HDIV_DIVISOR_DIVISOR_Pos)            /*!< HDIV_T::DIVISOR: DIVISOR Mask          */\r
+\r
+#define HDIV_DIVQUO_QUOTIENT_Pos         (0)                                               /*!< HDIV_T::DIVQUO: QUOTIENT Position      */\r
+#define HDIV_DIVQUO_QUOTIENT_Msk         (0xfffffffful << HDIV_DIVQUO_QUOTIENT_Pos)        /*!< HDIV_T::DIVQUO: QUOTIENT Mask          */\r
+\r
+#define HDIV_DIVREM_REMAINDER_Pos        (0)                                               /*!< HDIV_T::DIVREM: REMAINDER Position     */\r
+#define HDIV_DIVREM_REMAINDER_Msk        (0xfffffffful << HDIV_DIVREM_REMAINDER_Pos)       /*!< HDIV_T::DIVREM: REMAINDER Mask         */\r
+\r
+#define HDIV_DIVSTS_FINISH_Pos           (0)                                               /*!< HDIV_T::DIVSTS: FINISH Position        */\r
+#define HDIV_DIVSTS_FINISH_Msk           (0x1ul << HDIV_DIVSTS_FINISH_Pos)                 /*!< HDIV_T::DIVSTS: FINISH Mask            */\r
+\r
+#define HDIV_DIVSTS_DIV0_Pos             (1)                                               /*!< HDIV_T::DIVSTS: DIV0 Position          */\r
+#define HDIV_DIVSTS_DIV0_Msk             (0x1ul << HDIV_DIVSTS_DIV0_Pos)                   /*!< HDIV_T::DIVSTS: DIV0 Mask              */\r
+\r
+/**@}*/ /* HDIV_CONST */\r
+/**@}*/ /* end of HDIV register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __HDIV_REG_H__ */\r