--- /dev/null
+/**************************************************************************//**\r
+ * @file uspi_reg.h\r
+ * @version V1.00\r
+ * @brief USPI register definition header file\r
+ *\r
+ * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.\r
+ *****************************************************************************/\r
+#ifndef __USPI_REG_H__\r
+#define __USPI_REG_H__\r
+\r
+/** @addtogroup REGISTER Control Register\r
+\r
+ @{\r
+\r
+*/\r
+\r
+\r
+/*---------------------- SPI Mode of USCI Controller -------------------------*/\r
+/**\r
+ @addtogroup USPI SPI Mode of USCI Controller(USPI)\r
+ Memory Mapped Structure for USPI Controller\r
+@{ */\r
+\r
+typedef struct\r
+{\r
+\r
+\r
+ /**\r
+ * @var USPI_T::CTL\r
+ * Offset: 0x00 USCI Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[2:0] |FUNMODE |Function Mode\r
+ * | | |This bit field selects the protocol for this USCI controller\r
+ * | | |Selecting a protocol that is not available or a reserved combination disables the USCI\r
+ * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol\r
+ * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\r
+ * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.\r
+ * | | |001 = The SPI protocol is selected.\r
+ * | | |010 = The UART protocol is selected.\r
+ * | | |100 = The I2C protocol is selected.\r
+ * | | |Note: Other bit combinations are reserved.\r
+ * @var USPI_T::INTEN\r
+ * Offset: 0x04 USCI Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit\r
+ * | | |This bit enables the interrupt generation in case of a transmit start event.\r
+ * | | |0 = The transmit start interrupt is disabled.\r
+ * | | |1 = The transmit start interrupt is enabled.\r
+ * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit\r
+ * | | |This bit enables the interrupt generation in case of a transmit finish event.\r
+ * | | |0 = The transmit finish interrupt is disabled.\r
+ * | | |1 = The transmit finish interrupt is enabled.\r
+ * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit\r
+ * | | |This bit enables the interrupt generation in case of a receive start event.\r
+ * | | |0 = The receive start interrupt is disabled.\r
+ * | | |1 = The receive start interrupt is enabled.\r
+ * |[4] |RXENDIEN |Receive End Interrupt Enable Bit\r
+ * | | |This bit enables the interrupt generation in case of a receive finish event.\r
+ * | | |0 = The receive end interrupt is disabled.\r
+ * | | |1 = The receive end interrupt is enabled.\r
+ * @var USPI_T::BRGEN\r
+ * Offset: 0x08 USCI Baud Rate Generator Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RCLKSEL |Reference Clock Source Selection\r
+ * | | |This bit selects the source of reference clock (fREF_CLK).\r
+ * | | |0 = Peripheral device clock fPCLK.\r
+ * | | |1 = Reserved.\r
+ * |[1] |PTCLKSEL |Protocol Clock Source Selection\r
+ * | | |This bit selects the source of protocol clock (fPROT_CLK).\r
+ * | | |0 = Reference clock fREF_CLK.\r
+ * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).\r
+ * |[3:2] |SPCLKSEL |Sample Clock Source Selection\r
+ * | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.\r
+ * | | |00 = fDIV_CLK.\r
+ * | | |01 = fPROT_CLK.\r
+ * | | |10 = fSCLK.\r
+ * | | |11 = fREF_CLK.\r
+ * |[4] |TMCNTEN |Time Measurement Counter Enable Bit\r
+ * | | |This bit enables the 10-bit timing measurement counter.\r
+ * | | |0 = Time measurement counter is Disabled.\r
+ * | | |1 = Time measurement counter is Enabled.\r
+ * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection\r
+ * | | |0 = Time measurement counter with fPROT_CLK.\r
+ * | | |1 = Time measurement counter with fDIV_CLK.\r
+ * |[25:16] |CLKDIV |Clock Divider\r
+ * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).\r
+ * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled\r
+ * | | |The revised value is the average bit time between bit 5 and bit 6\r
+ * | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate.\r
+ * @var USPI_T::DATIN0\r
+ * Offset: 0x10 USCI Input Data Signal Configuration Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SYNCSEL |Input Signal Synchronization Selection\r
+ * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\r
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.\r
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.\r
+ * | | |Note: In SPI protocol, we suggest this bit should be set as 0.\r
+ * |[2] |ININV |Input Signal Inverse Selection\r
+ * | | |This bit defines the inverter enable of the input asynchronous signal.\r
+ * | | |0 = The un-synchronized input signal will not be inverted.\r
+ * | | |1 = The un-synchronized input signal will be inverted.\r
+ * | | |Note: In SPI protocol, we suggest this bit should be set as 0.\r
+ * @var USPI_T::CTLIN0\r
+ * Offset: 0x20 USCI Input Control Signal Configuration Register 0\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SYNCSEL |Input Synchronization Signal Selection\r
+ * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\r
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.\r
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.\r
+ * | | |Note: In SPI protocol, we suggest this bit should be set as 0.\r
+ * |[2] |ININV |Input Signal Inverse Selection\r
+ * | | |This bit defines the inverter enable of the input asynchronous signal.\r
+ * | | |0 = The un-synchronized input signal will not be inverted.\r
+ * | | |1 = The un-synchronized input signal will be inverted.\r
+ * @var USPI_T::CLKIN\r
+ * Offset: 0x28 USCI Input Clock Signal Configuration Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SYNCSEL |Input Synchronization Signal Selection\r
+ * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\r
+ * | | |0 = The un-synchronized signal can be taken as input for the data shift unit.\r
+ * | | |1 = The synchronized signal can be taken as input for the data shift unit.\r
+ * | | |Note: In SPI protocol, we suggest this bit should be set as 0.\r
+ * @var USPI_T::LINECTL\r
+ * Offset: 0x2C USCI Line Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |LSB |LSB First Transmission Selection\r
+ * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.\r
+ * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.\r
+ * |[5] |DATOINV |Data Output Inverse Selection\r
+ * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.\r
+ * | | |0 = Data output level is not inverted.\r
+ * | | |1 = Data output level is inverted.\r
+ * |[7] |CTLOINV |Control Signal Output Inverse Selection\r
+ * | | |This bit defines the relation between the internal control signal and the output control signal.\r
+ * | | |0 = No effect.\r
+ * | | |1 = The control signal will be inverted before its output.\r
+ * | | |Note: The control signal has different definitions in different protocol\r
+ * | | |In SPI protocol, the control signal means slave select signal\r
+ * |[11:8] |DWIDTH |Word Length of Transmission\r
+ * | | |This bit field defines the data word length (amount of bits) for reception and transmission\r
+ * | | |The data word is always right-aligned in the data buffer\r
+ * | | |USCI support word length from 4 to 16 bits.\r
+ * | | |0x0: The data word contains 16 bits located at bit positions [15:0].\r
+ * | | |0x1: Reserved.\r
+ * | | |0x2: Reserved.\r
+ * | | |0x3: Reserved.\r
+ * | | |0x4: The data word contains 4 bits located at bit positions [3:0].\r
+ * | | |0x5: The data word contains 5 bits located at bit positions [4:0].\r
+ * | | |...\r
+ * | | |0xF: The data word contains 15 bits located at bit positions [14:0].\r
+ * @var USPI_T::TXDAT\r
+ * Offset: 0x30 USCI Transmit Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |TXDAT |Transmit Data\r
+ * | | |Software can use this bit field to write 16-bit transmit data for transmission\r
+ * | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.\r
+ * |[16] |PORTDIR |Port Direction Control\r
+ * | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer\r
+ * | | |It is used to define the direction of the data port pin\r
+ * | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously.\r
+ * | | |0 = The data pin is configured as output mode.\r
+ * | | |1 = The data pin is configured as input mode.\r
+ * @var USPI_T::RXDAT\r
+ * Offset: 0x34 USCI Receive Data Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[15:0] |RXDAT |Received Data\r
+ * | | |This bit field monitors the received data which stored in receive data buffer.\r
+ * @var USPI_T::BUFCTL\r
+ * Offset: 0x38 USCI Transmit/Receive Buffer Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[6] |TXUDRIEN |Slave Transmit Under-run Interrupt Enable Bit\r
+ * | | |0 = Transmit under-run interrupt Disabled.\r
+ * | | |1 = Transmit under-run interrupt Enabled.\r
+ * |[7] |TXCLR |Clear Transmit Buffer\r
+ * | | |0 = No effect.\r
+ * | | |1 = The transmit buffer is cleared\r
+ * | | |Should only be used while the buffer is not taking part in data traffic.\r
+ * | | |Note: It is cleared automatically after one PCLK cycle.\r
+ * |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit\r
+ * | | |0 = Receive overrun interrupt Disabled.\r
+ * | | |1 = Receive overrun interrupt Enabled.\r
+ * |[15] |RXCLR |Clear Receive Buffer\r
+ * | | |0 = No effect.\r
+ * | | |1 = The receive buffer is cleared\r
+ * | | |Should only be used while the buffer is not taking part in data traffic.\r
+ * | | |Note: It is cleared automatically after one PCLK cycle.\r
+ * |[16] |TXRST |Transmit Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.\r
+ * | | |Note: It is cleared automatically after one PCLK cycle.\r
+ * |[17] |RXRST |Receive Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.\r
+ * | | |Note: It is cleared automatically after one PCLK cycle.\r
+ * @var USPI_T::BUFSTS\r
+ * Offset: 0x3C USCI Transmit/Receive Buffer Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |RXEMPTY |Receive Buffer Empty Indicator\r
+ * | | |0 = Receive buffer is not empty.\r
+ * | | |1 = Receive buffer is empty.\r
+ * |[1] |RXFULL |Receive Buffer Full Indicator\r
+ * | | |0 = Receive buffer is not full.\r
+ * | | |1 = Receive buffer is full.\r
+ * |[3] |RXOVIF |Receive Buffer Overrun Interrupt Status\r
+ * | | |This bit indicates that a receive buffer overrun event has been detected\r
+ * | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated\r
+ * | | |It is cleared by software writes 1 to this bit.\r
+ * | | |0 = A receive buffer overrun event has not been detected.\r
+ * | | |1 = A receive buffer overrun event has been detected.\r
+ * |[8] |TXEMPTY |Transmit Buffer Empty Indicator\r
+ * | | |0 = Transmit buffer is not empty.\r
+ * | | |1 = Transmit buffer is empty and available for the next transmission datum.\r
+ * |[9] |TXFULL |Transmit Buffer Full Indicator\r
+ * | | |0 = Transmit buffer is not full.\r
+ * | | |1 = Transmit buffer is full.\r
+ * |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status\r
+ * | | |This bit indicates that a transmit buffer under-run event has been detected\r
+ * | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated\r
+ * | | |It is cleared by software writes 1 to this bit\r
+ * | | |0 = A transmit buffer under-run event has not been detected.\r
+ * | | |1 = A transmit buffer under-run event has been detected.\r
+ * @var USPI_T::PDMACTL\r
+ * Offset: 0x40 USCI PDMA Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |PDMARST |PDMA Reset\r
+ * | | |0 = No effect.\r
+ * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.\r
+ * |[1] |TXPDMAEN |PDMA Transmit Channel Available\r
+ * | | |0 = Transmit PDMA function Disabled.\r
+ * | | |1 = Transmit PDMA function Enabled.\r
+ * |[2] |RXPDMAEN |PDMA Receive Channel Available\r
+ * | | |0 = Receive PDMA function Disabled.\r
+ * | | |1 = Receive PDMA function Enabled.\r
+ * |[3] |PDMAEN |PDMA Mode Enable Bit\r
+ * | | |0 = PDMA function Disabled.\r
+ * | | |1 = PDMA function Enabled.\r
+ * | | |Notice: The I2C is not supporting PDMA function.\r
+ * @var USPI_T::WKCTL\r
+ * Offset: 0x54 USCI Wake-up Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKEN |Wake-up Enable Bit\r
+ * | | |0 = Wake-up function Disabled.\r
+ * | | |1 = Wake-up function Enabled.\r
+ * |[1] |WKADDREN |Wake-up Address Match Enable Bit\r
+ * | | |0 = The chip is woken up according data toggle.\r
+ * | | |1 = The chip is woken up according address match.\r
+ * |[2] |PDBOPT |Power Down Blocking Option\r
+ * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.\r
+ * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.\r
+ * @var USPI_T::WKSTS\r
+ * Offset: 0x58 USCI Wake-up Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |WKF |Wake-up Flag\r
+ * | | |When chip is woken up from Power-down mode, this bit is set to 1\r
+ * | | |Software can write 1 to clear this bit.\r
+ * @var USPI_T::PROTCTL\r
+ * Offset: 0x5C USCI Protocol Control Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SLAVE |Slave Mode Selection\r
+ * | | |0 = Master mode.\r
+ * | | |1 = Slave mode.\r
+ * |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only)\r
+ * | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.\r
+ * | | |0 = 4-wire bi-direction interface.\r
+ * | | |1 = 3-wire bi-direction interface.\r
+ * |[2] |SS |Slave Select Control (Master Only)\r
+ * | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.\r
+ * | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal.\r
+ * | | |Note: In SPI protocol, the internal slave select signal is active high.\r
+ * |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only)\r
+ * | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit.\r
+ * | | |1 = Slave select signal will be generated automatically\r
+ * | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.\r
+ * |[7:6] |SCLKMODE |Serial Bus Clock Mode\r
+ * | | |This bit field defines the SCLK idle status, data transmit, and data receive edge.\r
+ * | | |MODE0 = The idle state of SPI clock is low level\r
+ * | | |Data is transmitted with falling edge and received with rising edge.\r
+ * | | |MODE1 = The idle state of SPI clock is low level\r
+ * | | |Data is transmitted with rising edge and received with falling edge.\r
+ * | | |MODE2 = The idle state of SPI clock is high level\r
+ * | | |Data is transmitted with rising edge and received with falling edge.\r
+ * | | |MODE3 = The idle state of SPI clock is high level\r
+ * | | |Data is transmitted with falling edge and received with rising edge.\r
+ * |[11:8] |SUSPITV |Suspend Interval (Master Only)\r
+ * | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer\r
+ * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word\r
+ * | | |The default value is 0x3\r
+ * | | |The period of the suspend interval is obtained according to the following equation.\r
+ * | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\r
+ * | | |Example:\r
+ * | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle.\r
+ * | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle.\r
+ * | | |.....\r
+ * | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle.\r
+ * | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle.\r
+ * |[14:12] |TSMSEL |Transmit Data Mode Selection\r
+ * | | |This bit field describes how receive and transmit data is shifted in and out.\r
+ * | | |TSMSEL = 000b: Full-duplex SPI.\r
+ * | | |TSMSEL = 100b: Half-duplex SPI.\r
+ * | | |Other values are reserved.\r
+ * | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.\r
+ * |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only)\r
+ * | | |In Slave mode, this bit field is used for Slave time-out period\r
+ * | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event\r
+ * | | |Writing 0x0 into this bit field will disable the Slave time-out function.\r
+ * | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.\r
+ * |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave)\r
+ * | | |This bit defines the transmitting data level when no data is available for transferring.\r
+ * | | |0 = The output data level is 0 if TX under-run event occurs.\r
+ * | | |1 = The output data level is 1 if TX under-run event occurs.\r
+ * |[31] |PROTEN |SPI Protocol Enable Bit\r
+ * | | |0 = SPI Protocol Disabled.\r
+ * | | |1 = SPI Protocol Enabled.\r
+ * @var USPI_T::PROTIEN\r
+ * Offset: 0x60 USCI Protocol Interrupt Enable Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Control\r
+ * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.\r
+ * | | |0 = Slave select inactive interrupt generation Disabled.\r
+ * | | |1 = Slave select inactive interrupt generation Enabled.\r
+ * |[1] |SSACTIEN |Slave Select Active Interrupt Enable Control\r
+ * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active.\r
+ * | | |0 = Slave select active interrupt generation Disabled.\r
+ * | | |1 = Slave select active interrupt generation Enabled.\r
+ * |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Control\r
+ * | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.\r
+ * | | |0 = The Slave time-out interrupt Disabled.\r
+ * | | |1 = The Slave time-out interrupt Enabled.\r
+ * |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Control\r
+ * | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])\r
+ * | | |Bit count error event occurs.\r
+ * | | |0 = The Slave mode bit count error interrupt Disabled.\r
+ * | | |1 = The Slave mode bit count error interrupt Enabled.\r
+ * @var USPI_T::PROTSTS\r
+ * Offset: 0x64 USCI Protocol Status Register\r
+ * ---------------------------------------------------------------------------------------------------\r
+ * |Bits |Field |Descriptions\r
+ * | :----: | :----: | :---- |\r
+ * |[1] |TXSTIF |Transmit Start Interrupt Flag\r
+ * | | |0 = Transmit start event does not occur.\r
+ * | | |1 = Transmit start event occurs.\r
+ * | | |Note: It is cleared by software writes 1 to this bit\r
+ * |[2] |TXENDIF |Transmit End Interrupt Flag\r
+ * | | |0 = Transmit end event does not occur.\r
+ * | | |1 = Transmit end event occurs.\r
+ * | | |Note: It is cleared by software writes 1 to this bit\r
+ * |[3] |RXSTIF |Receive Start Interrupt Flag\r
+ * | | |0 = Receive start event does not occur.\r
+ * | | |1 = Receive start event occurs.\r
+ * | | |Note: It is cleared by software writes 1 to this bit\r
+ * |[4] |RXENDIF |Receive End Interrupt Flag\r
+ * | | |0 = Receive end event does not occur.\r
+ * | | |1 = Receive end event occurs.\r
+ * | | |Note: It is cleared by software writes 1 to this bit\r
+ * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only)\r
+ * | | |0 = Slave time-out event does not occur.\r
+ * | | |1 = Slave time-out event occurs.\r
+ * | | |Note: It is cleared by software writes 1 to this bit\r
+ * |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only)\r
+ * | | |0 = Slave bit count error event does not occur.\r
+ * | | |1 = Slave bit count error event occurs.\r
+ * | | |Note: It is cleared by software writes 1 to this bit.\r
+ * |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only)\r
+ * | | |This bit indicates that the internal slave select signal has changed to inactive\r
+ * | | |It is cleared by software writes 1 to this bit\r
+ * | | |0 = The slave select signal has not changed to inactive.\r
+ * | | |1 = The slave select signal has changed to inactive.\r
+ * | | |Note: The internal slave select signal is active high.\r
+ * |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only)\r
+ * | | |This bit indicates that the internal slave select signal has changed to active\r
+ * | | |It is cleared by software writes one to this bit\r
+ * | | |0 = The slave select signal has not changed to active.\r
+ * | | |1 = The slave select signal has changed to active.\r
+ * | | |Note: The internal slave select signal is active high.\r
+ * |[16] |SSLINE |Slave Select Line Bus Status (Read Only)\r
+ * | | |This bit is only available in Slave mode\r
+ * | | |It used to monitor the current status of the input slave select signal on the bus.\r
+ * | | |0 = The slave select line status is 0.\r
+ * | | |1 = The slave select line status is 1.\r
+ * |[17] |BUSY |Busy Status (Read Only)\r
+ * | | |0 = SPI is in idle state.\r
+ * | | |1 = SPI is in busy state.\r
+ * | | |The following listing are the bus busy conditions:\r
+ * | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0.\r
+ * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.\r
+ * | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active.\r
+ * | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.\r
+ * |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only)\r
+ * | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1\r
+ * | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.\r
+ * | | |0 = Slave transmit under-run event does not occur.\r
+ * | | |1 = Slave transmit under-run event occurs.\r
+ */\r
+ __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */\r
+ __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */\r
+ __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */\r
+ __I uint32_t RESERVE0[1];\r
+ __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */\r
+ __I uint32_t RESERVE1[3];\r
+ __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */\r
+ __I uint32_t RESERVE2[1];\r
+ __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */\r
+ __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */\r
+ __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */\r
+ __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */\r
+ __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */\r
+ __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */\r
+ __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */\r
+ __I uint32_t RESERVE3[4];\r
+ __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */\r
+ __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */\r
+ __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */\r
+ __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */\r
+ __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */\r
+\r
+} USPI_T;\r
+\r
+/**\r
+ @addtogroup USPI_CONST USPI Bit Field Definition\r
+ Constant Definitions for USPI Controller\r
+@{ */\r
+\r
+#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */\r
+#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */\r
+\r
+#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */\r
+#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */\r
+\r
+#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */\r
+#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */\r
+\r
+#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */\r
+#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */\r
+\r
+#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */\r
+#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */\r
+\r
+#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */\r
+#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */\r
+\r
+#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */\r
+#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */\r
+\r
+#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */\r
+#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */\r
+\r
+#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */\r
+#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */\r
+\r
+#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */\r
+#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */\r
+\r
+#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */\r
+#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */\r
+\r
+#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */\r
+#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */\r
+\r
+#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */\r
+#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */\r
+\r
+#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */\r
+#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */\r
+\r
+#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */\r
+#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */\r
+\r
+#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */\r
+#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */\r
+\r
+#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */\r
+#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */\r
+\r
+#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */\r
+#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */\r
+\r
+#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */\r
+#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */\r
+\r
+#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */\r
+#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */\r
+\r
+#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */\r
+#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */\r
+\r
+#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */\r
+#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */\r
+\r
+#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */\r
+#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */\r
+\r
+#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */\r
+#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */\r
+\r
+#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */\r
+#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */\r
+\r
+#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */\r
+#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */\r
+\r
+#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */\r
+#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */\r
+\r
+#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */\r
+#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */\r
+\r
+#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */\r
+#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */\r
+\r
+#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */\r
+#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */\r
+\r
+#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */\r
+#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */\r
+\r
+#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */\r
+#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */\r
+\r
+#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */\r
+#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */\r
+\r
+#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */\r
+#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */\r
+\r
+#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */\r
+#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */\r
+\r
+#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */\r
+#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */\r
+\r
+#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */\r
+#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */\r
+\r
+#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */\r
+#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */\r
+\r
+#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */\r
+#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */\r
+\r
+#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */\r
+#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */\r
+\r
+#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */\r
+#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */\r
+\r
+#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */\r
+#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */\r
+\r
+#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */\r
+#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */\r
+\r
+#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */\r
+#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */\r
+\r
+#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */\r
+#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */\r
+\r
+#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */\r
+#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */\r
+\r
+#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */\r
+#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */\r
+\r
+#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */\r
+#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */\r
+\r
+#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */\r
+#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */\r
+\r
+#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */\r
+#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */\r
+\r
+#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */\r
+#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */\r
+\r
+#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */\r
+#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */\r
+\r
+#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */\r
+#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */\r
+\r
+#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */\r
+#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */\r
+\r
+#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */\r
+#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */\r
+\r
+#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */\r
+#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */\r
+\r
+#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */\r
+#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */\r
+\r
+#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */\r
+#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */\r
+\r
+#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */\r
+#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */\r
+\r
+#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */\r
+#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */\r
+\r
+#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */\r
+#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */\r
+\r
+#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */\r
+#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */\r
+\r
+#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */\r
+#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */\r
+\r
+#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */\r
+#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */\r
+\r
+#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */\r
+#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */\r
+\r
+#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */\r
+#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */\r
+\r
+#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */\r
+#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */\r
+\r
+#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */\r
+#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */\r
+\r
+/**@}*/ /* USPI_CONST */\r
+/**@}*/ /* end of USPI register group */\r
+/**@}*/ /* end of REGISTER group */\r
+\r
+\r
+#endif /* __USPI_REG_H__ */\r
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