Add Cortex M23 GCC and IAR ports. Add demo projects for Nuvoton NuMaker-PFM-2351.

[freertos] / FreeRTOS / Demo / CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC / Nuvoton_Code / StdDriver / src / crc.c

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Nuvoton_Code/StdDriver/src/crc.c b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Nuvoton_Code/StdDriver/src/crc.c
new file mode 100644 (file)
index 0000000..7e13177
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Nuvoton_Code/StdDriver/src/crc.c
@@ -0,0 +1,118 @@
+/**************************************************************************//**\r
+ * @file     crc.c\r
+ * @version  V3.00\r
+ * @brief    Cyclic Redundancy Check(CRC) driver source file\r
+ *\r
+ * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.\r
+*****************************************************************************/\r
+#include "NuMicro.h"\r
+\r
+\r
+/** @addtogroup Standard_Driver Standard Driver\r
+  @{\r
+*/\r
+\r
+/** @addtogroup CRC_Driver CRC Driver\r
+  @{\r
+*/\r
+\r
+/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions\r
+  @{\r
+*/\r
+\r
+/**\r
+  * @brief      CRC Open\r
+  *\r
+  * @param[in]  u32Mode         CRC operation polynomial mode. Valid values are:\r
+  *                             - \ref CRC_CCITT\r
+  *                             - \ref CRC_8\r
+  *                             - \ref CRC_16\r
+  *                             - \ref CRC_32\r
+  * @param[in]  u32Attribute    CRC operation data attribute. Valid values are combined with:\r
+  *                             - \ref CRC_CHECKSUM_COM\r
+  *                             - \ref CRC_CHECKSUM_RVS\r
+  *                             - \ref CRC_WDATA_COM\r
+  *                             - \ref CRC_WDATA_RVS\r
+  * @param[in]  u32Seed         Seed value.\r
+  * @param[in]  u32DataLen      CPU Write Data Length. Valid values are:\r
+  *                             - \ref CRC_CPU_WDATA_8\r
+  *                             - \ref CRC_CPU_WDATA_16\r
+  *                             - \ref CRC_CPU_WDATA_32\r
+  *\r
+  * @return     None\r
+  *\r
+  * @details    This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n\r
+  *             After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.\r
+  */\r
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)\r
+{\r
+    CRC_T *pCRC;\r
+\r
+    if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+    {\r
+        pCRC = CRC_NS;\r
+    }\r
+    else\r
+    {\r
+        pCRC = CRC;\r
+    }\r
+\r
+    pCRC->SEED = u32Seed;\r
+    pCRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;\r
+\r
+    /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */\r
+    pCRC->CTL |= CRC_CTL_CHKSINIT_Msk;\r
+}\r
+\r
+/**\r
+  * @brief      Get CRC Checksum\r
+  *\r
+  * @param[in]  None\r
+  *\r
+  * @return     Checksum Result\r
+  *\r
+  * @details    This macro gets the CRC checksum result by current CRC polynomial mode.\r
+  */\r
+uint32_t CRC_GetChecksum(void)\r
+{\r
+    CRC_T *pCRC;\r
+    uint32_t u32Checksum = 0UL;\r
+\r
+    if((__PC()&NS_OFFSET) == NS_OFFSET)\r
+    {\r
+        pCRC = CRC_NS;\r
+    }\r
+    else\r
+    {\r
+        pCRC = CRC;\r
+    }\r
+\r
+    switch(pCRC->CTL & CRC_CTL_CRCMODE_Msk)\r
+    {\r
+        case CRC_CCITT:\r
+        case CRC_16:\r
+            u32Checksum = (pCRC->CHECKSUM & 0xFFFFUL);\r
+            break;\r
+\r
+        case CRC_32:\r
+            u32Checksum = pCRC->CHECKSUM;\r
+            break;\r
+\r
+        case CRC_8:\r
+            u32Checksum = (pCRC->CHECKSUM & 0xFFUL);\r
+            break;\r
+\r
+        default:\r
+            break;\r
+    }\r
+\r
+    return u32Checksum;\r
+}\r
+\r
+/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */\r
+\r
+/*@}*/ /* end of group CRC_Driver */\r
+\r
+/*@}*/ /* end of group Standard_Driver */\r
+\r
+/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/\r