--- /dev/null
+;/**************************************************************************//**\r
+; * @file startup_ARMCM33.s\r
+; * @brief CMSIS Core Device Startup File for\r
+; * ARMCM33 Device Series\r
+; * @version V5.00\r
+; * @date 21. October 2016\r
+; ******************************************************************************/\r
+;/*\r
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
+; *\r
+; * SPDX-License-Identifier: Apache-2.0\r
+; *\r
+; * Licensed under the Apache License, Version 2.0 (the License); you may\r
+; * not use this file except in compliance with the License.\r
+; * You may obtain a copy of the License at\r
+; *\r
+; * www.apache.org/licenses/LICENSE-2.0\r
+; *\r
+; * Unless required by applicable law or agreed to in writing, software\r
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+; * See the License for the specific language governing permissions and\r
+; * limitations under the License.\r
+; */\r
+\r
+;/*\r
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+;*/\r
+\r
+\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000C00\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+\r
+__Vectors DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD SecureFault_Handler ; Secure Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WDT_IRQHandler ; 0: Watchdog Timer\r
+ DCD RTC_IRQHandler ; 1: Real Time Clock\r
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1\r
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3\r
+ DCD MCIA_IRQHandler ; 4: MCIa\r
+ DCD MCIB_IRQHandler ; 5: MCIb\r
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA\r
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA\r
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA\r
+ DCD UART4_IRQHandler ; 9: UART4 - not connected\r
+ DCD AACI_IRQHandler ; 10: AACI / AC97\r
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt\r
+ DCD ENET_IRQHandler ; 12: Ethernet\r
+ DCD USBDC_IRQHandler ; 13: USB Device\r
+ DCD USBHC_IRQHandler ; 14: USB Host Controller\r
+ DCD CHLCD_IRQHandler ; 15: Character LCD\r
+ DCD FLEXRAY_IRQHandler ; 16: Flexray\r
+ DCD CAN_IRQHandler ; 17: CAN\r
+ DCD LIN_IRQHandler ; 18: LIN\r
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC\r
+ DCD 0 ; 20: Reserved\r
+ DCD 0 ; 21: Reserved\r
+ DCD 0 ; 22: Reserved\r
+ DCD 0 ; 23: Reserved\r
+ DCD 0 ; 24: Reserved\r
+ DCD 0 ; 25: Reserved\r
+ DCD 0 ; 26: Reserved\r
+ DCD 0 ; 27: Reserved\r
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD\r
+ DCD 0 ; 29: Reserved - CPU FPGA\r
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA\r
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA\r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+ AREA |.text|, CODE, READONLY\r
+\r
+\r
+; Reset Handler\r
+\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT SystemInit\r
+ IMPORT __main\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SecureFault_Handler\\r
+ PROC\r
+ EXPORT SecureFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ EXPORT WDT_IRQHandler [WEAK]\r
+ EXPORT RTC_IRQHandler [WEAK]\r
+ EXPORT TIM0_IRQHandler [WEAK]\r
+ EXPORT TIM2_IRQHandler [WEAK]\r
+ EXPORT MCIA_IRQHandler [WEAK]\r
+ EXPORT MCIB_IRQHandler [WEAK]\r
+ EXPORT UART0_IRQHandler [WEAK]\r
+ EXPORT UART1_IRQHandler [WEAK]\r
+ EXPORT UART2_IRQHandler [WEAK]\r
+ EXPORT UART3_IRQHandler [WEAK]\r
+ EXPORT UART4_IRQHandler [WEAK]\r
+ EXPORT AACI_IRQHandler [WEAK]\r
+ EXPORT CLCD_IRQHandler [WEAK]\r
+ EXPORT ENET_IRQHandler [WEAK]\r
+ EXPORT USBDC_IRQHandler [WEAK]\r
+ EXPORT USBHC_IRQHandler [WEAK]\r
+ EXPORT CHLCD_IRQHandler [WEAK]\r
+ EXPORT FLEXRAY_IRQHandler [WEAK]\r
+ EXPORT CAN_IRQHandler [WEAK]\r
+ EXPORT LIN_IRQHandler [WEAK]\r
+ EXPORT I2C_IRQHandler [WEAK]\r
+ EXPORT CPU_CLCD_IRQHandler [WEAK]\r
+ EXPORT SPI_IRQHandler [WEAK]\r
+\r
+WDT_IRQHandler\r
+RTC_IRQHandler\r
+TIM0_IRQHandler\r
+TIM2_IRQHandler\r
+MCIA_IRQHandler\r
+MCIB_IRQHandler\r
+UART0_IRQHandler\r
+UART1_IRQHandler\r
+UART2_IRQHandler\r
+UART3_IRQHandler\r
+UART4_IRQHandler\r
+AACI_IRQHandler\r
+CLCD_IRQHandler\r
+ENET_IRQHandler\r
+USBDC_IRQHandler\r
+USBHC_IRQHandler\r
+CHLCD_IRQHandler\r
+FLEXRAY_IRQHandler\r
+CAN_IRQHandler\r
+LIN_IRQHandler\r
+I2C_IRQHandler\r
+CPU_CLCD_IRQHandler\r
+SPI_IRQHandler\r
+ B .\r
+\r
+ ENDP\r
+\r
+\r
+ ALIGN\r
+\r
+\r
+; User Initial Stack & Heap\r
+\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+\r
+__user_initial_stackheap PROC\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+\r
+ END\r
projects / freertos / blobdiff