--- /dev/null
+# Parameters:\r
+# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]\r
+#----------------------------------------------------------------------------------------------\r
+cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support\r
+cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension\r
+cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\r
+cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\r
+cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\r
+cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\r
+cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]\r
+cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode\r
+cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\r
+cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\r
+cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]\r
+cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset\r
+cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set\r
+idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : \r
+cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write\r
+cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write\r
+cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write\r
+cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included\r
+cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included\r
+fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic\r
+fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]\r
+fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]\r
+fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2]\r
+fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb\r
+fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)\r
+fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART\r
+fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output\r
+fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence\r
+fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)\r
+fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted\r
+fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)\r
+fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART\r
+fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output\r
+fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence\r
+fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)\r
+fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted\r
+fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.\r
+fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation\r
+fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)\r
+fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.\r
+fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode\r
+fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected\r
+fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]\r
+fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr\r
+fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)\r
+fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode\r
+fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected\r
+fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]\r
+fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr\r
+fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)\r
+fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode\r
+fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected\r
+fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]\r
+fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr\r
+fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)\r
+fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size\r
+fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)\r
+fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART\r
+fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output\r
+fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence\r
+fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)\r
+fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted\r
+fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.\r
+fvp_mps2.sse200.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.\r
+fvp_mps2.sse200.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.\r
+fvp_mps2.sse200.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.\r
+fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size\r
+fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size\r
+fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size\r
+fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.sse200.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size\r
+fvp_mps2.sse200.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.sse200.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.sse200.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size\r
+fvp_mps2.sse200.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.sse200.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.sse200.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size\r
+fvp_mps2.sse200.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.sse200.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.sse200.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size\r
+fvp_mps2.sse200.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.sse200.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern\r
+fvp_mps2.sse200.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal\r
+fvp_mps2.sse200.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision\r
+fvp_mps2.sse200.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision\r
+fvp_mps2.sse200.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision\r
+fvp_mps2.sse200.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal\r
+fvp_mps2.sse200.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision\r
+fvp_mps2.sse200.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal\r
+fvp_mps2.sse200.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision\r
+fvp_mps2.sse200.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal\r
+fvp_mps2.sse200.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision\r
+fvp_mps2.sse200.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal\r
+fvp_mps2.sse200.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision\r
+fvp_mps2.sse200.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal\r
+fvp_mps2.sse200.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision\r
+fvp_mps2.sse200.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal\r
+fvp_mps2.sse200.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision\r
+fvp_mps2.sse200.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal\r
+fvp_mps2.sse200.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision\r
+fvp_mps2.sse200.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal\r
+fvp_mps2.sse200.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision\r
+fvp_mps2.sse200.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal\r
+fvp_mps2.sse200.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision\r
+fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled\r
+fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address\r
+fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode\r
+fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface\r
+fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking\r
+fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking\r
+fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking\r
+fvp_mps2.mps2_secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]\r
+fvp_mps2.mps2_secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]\r
+fvp_mps2.mps2_secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported\r
+fvp_mps2.mps2_secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported\r
+fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component\r
+fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]\r
+fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]\r
+fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master\r
+fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit\r
+fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]\r
+fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores\r
+fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component\r
+fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]\r
+fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]\r
+fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master\r
+fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit\r
+fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]\r
+fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores\r
+fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component\r
+fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]\r
+fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]\r
+fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master\r
+fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit\r
+fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]\r
+fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores\r
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component\r
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]\r
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]\r
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master\r
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit\r
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]\r
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores\r
+fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S\r
+fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S\r
+fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S\r
+fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S\r
+fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes\r
+fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer\r
+fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response\r
+fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay\r
+fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes\r
+fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer\r
+fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response\r
+fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay\r
+fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes\r
+fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer\r
+fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response\r
+fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay\r
+fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes\r
+fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer\r
+fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response\r
+fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay\r
+fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot\r
+fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot\r
+fvp_mps2.sse200.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]\r
+#----------------------------------------------------------------------------------------------\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/******************************************************************************\r
+ See http://www.freertos.org/a00110.html for an explanation of the\r
+ definitions contained in this file.\r
+******************************************************************************/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ * http://www.freertos.org/a00110.html\r
+ *----------------------------------------------------------*/\r
+\r
+extern uint32_t SystemCoreClock;\r
+\r
+/* Cortex M33 port configuration. */\r
+#define configENABLE_MPU 1\r
+#define configENABLE_FPU 1\r
+#define configENABLE_TRUSTZONE 1\r
+\r
+/* Constants related to the behaviour or the scheduler. */\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_TIME_SLICING 1\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */\r
+\r
+/* Constants that describe the hardware and memory usage. */\r
+#define configCPU_CLOCK_HZ SystemCoreClock\r
+#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 )\r
+#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) )\r
+\r
+/* Constants that build features in or out. */\r
+#define configUSE_MUTEXES 1\r
+#define configUSE_TICKLESS_IDLE 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_NEWLIB_REENTRANT 0\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_QUEUE_SETS 0\r
+#define configUSE_TASK_NOTIFICATIONS 1\r
+#define configUSE_TRACE_FACILITY 1\r
+\r
+/* Constants that define which hook (callback) functions should be used. */\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+\r
+/* Constants provided for debugging and optimisation assistance. */\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 3 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+ * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is\r
+ * only necessary if the linker does not automatically remove functions that are\r
+ * not referenced anyway. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 0\r
+#define INCLUDE_xTaskGetIdleTaskHandle 0\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xTaskResumeFromISR 0\r
+#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
+#define INCLUDE_xTaskGetSchedulerState 0\r
+#define INCLUDE_xSemaphoreGetMutexHolder 0\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+\r
+/* This demo makes use of one or more example stats formatting functions. These\r
+ * format the raw data provided by the uxTaskGetSystemState() function in to\r
+ * human readable ASCII form. See the notes in the implementation of vTaskList()\r
+ * within FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
+\r
+/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter.\r
+ * See the FreeRTOS+CLI documentation for more information:\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */\r
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048\r
+\r
+/* Interrupt priority configuration follows...................... */\r
+\r
+/* Use the system definition, if there is one. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 3 /* 8 priority levels. */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+ * function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+ * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT\r
+ * CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A\r
+ * HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+ * to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )\r
+\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+ * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )\r
+\r
+/* The #ifdef guards against the file being included from IAR assembly files. */\r
+#ifndef __IASMARM__\r
+\r
+ /* Constants related to the generation of run time stats. */\r
+ #define configGENERATE_RUN_TIME_STATS 0\r
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
+ #define portGET_RUN_TIME_COUNTER_VALUE() 0\r
+ #define configTICK_RATE_HZ ( ( TickType_t ) 100 )\r
+\r
+#endif /* __IASMARM__ */\r
+\r
+/* Enable static allocation. */\r
+#define configSUPPORT_STATIC_ALLOCATION 1\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+LOAD "..\\NonSecure\\Objects\\FreeRTOSDemo_ns.axf" incremental\r
+LOAD "..\\Secure\\Objects\\FreeRTOSDemo_s.axf" incremental\r
+RESET\r
+g, \\FreeRTOSDemo_s\main_s\main
\ No newline at end of file
--- /dev/null
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+
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+ <NodeIsActive>1</NodeIsActive>
+ <NodeIsExpanded>1</NodeIsExpanded>
+ </project>
+
+ <project>
+ <PathAndName>.\NonSecure\FreeRTOSDemo_ns.uvprojx</PathAndName>
+ <NodeIsExpanded>1</NodeIsExpanded>
+ </project>
+
+</ProjectWorkspace>
--- /dev/null
+; *************************************************************\r
+; *** Scatter-Loading Description File generated by uVision ***\r
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+LR_IROM_NS_UNPRIVILEGED 0x00209000 0x001F7000 ; load region size_region\r
+{\r
+ ER_IROM_NS_UNPRIVILEGED +0 ; load address = execution address\r
+ {\r
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+ }\r
+\r
+ ER_IRAM_NS_UNPRIVILEGED 0x20201000 0x0001F000\r
+ {\r
+ *(+RW, +ZI)\r
+ }\r
+}\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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+
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+ <Header>### uVision Project, (C) Keil Software</Header>
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+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj; *.o</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ <nMigrate>0</nMigrate>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>FVP Simulation Model</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
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+ <CListInc>0</CListInc>
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+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
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+ <sRSysVw>1</sRSysVw>
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+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <bEvRecOn>1</bEvRecOn>
+ <nTsel>15</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
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+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile>..\Debug.ini</tIfile>
+ <pMon>BIN\DbgFMv8M.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGTARM</Key>
+ <Name>(6010=70,43,547,639,0)(6018=1091,145,1280,478,0)(6019=1091,137,1280,457,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=1022,0,1280,731,0)(6015=777,40,1035,662,1)(6003=207,84,780,620,1)(6000=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
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+ <Key>ARMDBGFLAGS</Key>
+ <Name></Name>
+ </SetRegEntry>
+ <SetRegEntry>
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+ <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
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+ </SetRegEntry>
+ <SetRegEntry>
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+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
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+ <DebugFlag>
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+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ <bAutoGenD>0</bAutoGenD>
+ <LntExFlags>0</LntExFlags>
+ <pMisraName></pMisraName>
+ <pszMrule></pszMrule>
+ <pSingCmds></pSingCmds>
+ <pMultCmds></pMultCmds>
+ <pMisraNamep></pMisraNamep>
+ <pszMrulep></pszMrulep>
+ <pSingCmdsp></pSingCmdsp>
+ <pMultCmdsp></pMultCmdsp>
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+ </Target>
+
+ <Group>
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+ <tvExp>0</tvExp>
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+ <bDave2>0</bDave2>
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+ <FilenameWithoutPath>list.c</FilenameWithoutPath>
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+ <ScatterFile>.\FreeRTOSDemo_ns.sct</ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>CMSE Library</GroupName>
+ <Files>
+ <File>
+ <FileName>FreeRTOSDemo_s_CMSE_Lib.o</FileName>
+ <FileType>3</FileType>
+ <FilePath>..\Secure\Objects\FreeRTOSDemo_s_CMSE_Lib.o</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS</GroupName>
+ <Files>
+ <File>
+ <FileName>event_groups.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\event_groups.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>stream_buffer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\stream_buffer.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\tasks.c</FilePath>
+ </File>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\MemMang\heap_4.c</FilePath>
+ </File>
+ <File>
+ <FileName>mpu_wrappers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\Common\mpu_wrappers.c</FilePath>
+ </File>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM33\non_secure\port.c</FilePath>
+ </File>
+ <File>
+ <FileName>portasm.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM33\non_secure\portasm.h</FilePath>
+ </File>
+ <File>
+ <FileName>portmacro.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM33\non_secure\portmacro.h</FilePath>
+ </File>
+ <File>
+ <FileName>portasm.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM33\non_secure\portasm.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Config</GroupName>
+ <Files>
+ <File>
+ <FileName>FreeRTOSConfig.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\Config\FreeRTOSConfig.h</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Demos</GroupName>
+ <Files>
+ <File>
+ <FileName>mpu_demo.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\Common\ARMv8M\mpu_demo\mpu_demo.h</FilePath>
+ </File>
+ <File>
+ <FileName>mpu_demo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\ARMv8M\mpu_demo\mpu_demo.c</FilePath>
+ </File>
+ <File>
+ <FileName>tz_demo.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\Common\ARMv8M\tz_demo\tz_demo.h</FilePath>
+ </File>
+ <File>
+ <FileName>tz_demo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\ARMv8M\tz_demo\tz_demo.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>User</GroupName>
+ <Files>
+ <File>
+ <FileName>main_ns.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main_ns.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+ <RTE>
+ <apis/>
+ <components>
+ <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.0" condition="ARMv6_7_8-M Device">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+ <targetInfos>
+ <targetInfo name="FVP Simulation Model"/>
+ </targetInfos>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.2.0"/>
+ <targetInfos>
+ <targetInfo name="FVP Simulation Model"/>
+ </targetInfos>
+ </component>
+ </components>
+ <files>
+ <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP\startup_ARMCM33.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceC" condition="ARMCC GCC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMCM33_DSP_FP\system_ARMCM33.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.4.0"/>
+ <targetInfos>
+ <targetInfo name="FVP Simulation Model"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.4.0"/>
+ <targetInfos>
+ <targetInfo name="FVP Simulation Model"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.4.0"/>
+ <targetInfos>
+ <targetInfo name="FVP Simulation Model"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMCM33_TZ\partition_ARMCM33.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMCM33_TZ\startup_ARMCM33.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceC" condition="ARMCC GCC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMCM33_TZ\system_ARMCM33.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="header" name="Device\ARM\ARMv8MBL\Include\Template\partition_ARMv8MBL.h" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMv8MBL\partition_ARMv8MBL.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMv8MBL\Source\ARM\startup_ARMv8MBL.s" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMv8MBL\startup_ARMv8MBL.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="sourceC" condition="ARMCC GCC" name="Device\ARM\ARMv8MBL\Source\system_ARMv8MBL.c" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\ARMv8MBL\system_ARMv8MBL.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" condition="ARMv8MBL CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="header" name="CMSIS\Config\RTE_Device.h" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\RTE_Device.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="header" name="Device\CMSDK_ARMv8MBL\Include\Template\partition_CMSDK_ARMv8MBL.h" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\partition_CMSDK_ARMv8MBL.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="source" condition="ARMCC" name="Device\CMSDK_ARMv8MBL\Source\ARM\startup_CMSDK_ARMv8MBL.s" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\startup_CMSDK_ARMv8MBL.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
+ <targetInfos/>
+ </file>
+ <file attr="config" category="source" name="Device\CMSDK_ARMv8MBL\Source\system_CMSDK_ARMv8MBL.c" version="1.0.0">
+ <instance index="0" removed="1">RTE\Device\CMSDK_ARMv8MBL\system_CMSDK_ARMv8MBL.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="CMSDK_ARMv8MBL CMSIS Device"/>
+ <package name="V2M-MPS2_CMx_BSP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.4.0"/>
+ <targetInfos/>
+ </file>
+ </files>
+ </RTE>
+
+</Project>
--- /dev/null
+/**************************************************************************//**\r
+ * @file partition_ARMCM33.h\r
+ * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33\r
+ * @version V5.0.1\r
+ * @date 07. December 2016\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef PARTITION_ARMCM33_H\r
+#define PARTITION_ARMCM33_H\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\r
+*/\r
+\r
+/*\r
+// <e>Initialize Security Attribution Unit (SAU) CTRL register\r
+*/\r
+#define SAU_INIT_CTRL 1\r
+\r
+/*\r
+// <q> Enable SAU\r
+// <i> Value for SAU->CTRL register bit ENABLE\r
+*/\r
+#define SAU_INIT_CTRL_ENABLE 1\r
+\r
+/*\r
+// <o> When SAU is disabled\r
+// <0=> All Memory is Secure\r
+// <1=> All Memory is Non-Secure\r
+// <i> Value for SAU->CTRL register bit ALLNS\r
+// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\r
+*/\r
+#define SAU_INIT_CTRL_ALLNS 0\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <h>Initialize Security Attribution Unit (SAU) Address Regions\r
+// <i>SAU configuration specifies regions to be one of:\r
+// <i> - Secure and Non-Secure Callable\r
+// <i> - Non-Secure\r
+// <i>Note: All memory regions not configured by SAU are Secure\r
+*/\r
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */\r
+\r
+/*\r
+// <e>Initialize SAU Region 0\r
+// <i> Setup SAU Region 0 memory attributes\r
+*/\r
+#define SAU_INIT_REGION0 1\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC0 1\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 1\r
+// <i> Setup SAU Region 1 memory attributes\r
+*/\r
+#define SAU_INIT_REGION1 1\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START1 0x00200000\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END1 0x003FFFFF\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC1 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 2\r
+// <i> Setup SAU Region 2 memory attributes\r
+*/\r
+#define SAU_INIT_REGION2 1\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START2 0x20200000\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END2 0x203FFFFF\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC2 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 3\r
+// <i> Setup SAU Region 3 memory attributes\r
+*/\r
+#define SAU_INIT_REGION3 1\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START3 0x40000000\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END3 0x40040000\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC3 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 4\r
+// <i> Setup SAU Region 4 memory attributes\r
+*/\r
+#define SAU_INIT_REGION4 0\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC4 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 5\r
+// <i> Setup SAU Region 5 memory attributes\r
+*/\r
+#define SAU_INIT_REGION5 0\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START5 0x00000000\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END5 0x00000000\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC5 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 6\r
+// <i> Setup SAU Region 6 memory attributes\r
+*/\r
+#define SAU_INIT_REGION6 0\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START6 0x00000000\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END6 0x00000000\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC6 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 7\r
+// <i> Setup SAU Region 7 memory attributes\r
+*/\r
+#define SAU_INIT_REGION7 0\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START7 0x00000000\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END7 0x00000000\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC7 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// </h>\r
+*/\r
+\r
+/*\r
+// <e>Setup behaviour of Sleep and Exception Handling\r
+*/\r
+#define SCB_CSR_AIRCR_INIT 1\r
+\r
+/*\r
+// <o> Deep Sleep can be enabled by\r
+// <0=>Secure and Non-Secure state\r
+// <1=>Secure state only\r
+// <i> Value for SCB->CSR register bit DEEPSLEEPS\r
+*/\r
+#define SCB_CSR_DEEPSLEEPS_VAL 1\r
+\r
+/*\r
+// <o>System reset request accessible from\r
+// <0=> Secure and Non-Secure state\r
+// <1=> Secure state only\r
+// <i> Value for SCB->AIRCR register bit SYSRESETREQS\r
+*/\r
+#define SCB_AIRCR_SYSRESETREQS_VAL 1\r
+\r
+/*\r
+// <o>Priority of Non-Secure exceptions is\r
+// <0=> Not altered\r
+// <1=> Lowered to 0x80-0xFF\r
+// <i> Value for SCB->AIRCR register bit PRIS\r
+*/\r
+#define SCB_AIRCR_PRIS_VAL 1\r
+\r
+/*\r
+// <o>BusFault, HardFault, and NMI target\r
+// <0=> Secure state\r
+// <1=> Non-Secure state\r
+// <i> Value for SCB->AIRCR register bit BFHFNMINS\r
+*/\r
+#define SCB_AIRCR_BFHFNMINS_VAL 1\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Setup behaviour of Floating Point Unit\r
+*/\r
+#define TZ_FPU_NS_USAGE 1\r
+\r
+/*\r
+// <o>Floating Point Unit usage\r
+// <0=> Secure state only\r
+// <3=> Secure and Non-Secure state\r
+// <i> Value for SCB->NSACR register bits CP10, CP11\r
+*/\r
+#define SCB_NSACR_CP10_11_VAL 3\r
+\r
+/*\r
+// <o>Treat floating-point registers as Secure\r
+// <0=> Disabled\r
+// <1=> Enabled\r
+// <i> Value for FPU->FPCCR register bit TS\r
+*/\r
+#define FPU_FPCCR_TS_VAL 0\r
+\r
+/*\r
+// <o>Clear on return (CLRONRET) accessibility\r
+// <0=> Secure and Non-Secure state\r
+// <1=> Secure state only\r
+// <i> Value for FPU->FPCCR register bit CLRONRETS\r
+*/\r
+#define FPU_FPCCR_CLRONRETS_VAL 0\r
+\r
+/*\r
+// <o>Clear floating-point caller saved registers on exception return\r
+// <0=> Disabled\r
+// <1=> Enabled\r
+// <i> Value for FPU->FPCCR register bit CLRONRET\r
+*/\r
+#define FPU_FPCCR_CLRONRET_VAL 1\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <h>Setup Interrupt Target\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 0 (Interrupts 0..31)\r
+*/\r
+#define NVIC_INIT_ITNS0 1\r
+\r
+/*\r
+// Interrupts 0..31\r
+// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS0_VAL 0x0000122B\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 1 (Interrupts 32..63)\r
+*/\r
+#define NVIC_INIT_ITNS1 1\r
+\r
+/*\r
+// Interrupts 32..63\r
+// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS1_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 2 (Interrupts 64..95)\r
+*/\r
+#define NVIC_INIT_ITNS2 0\r
+\r
+/*\r
+// Interrupts 64..95\r
+// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS2_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 3 (Interrupts 96..127)\r
+*/\r
+#define NVIC_INIT_ITNS3 0\r
+\r
+/*\r
+// Interrupts 96..127\r
+// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS3_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 4 (Interrupts 128..159)\r
+*/\r
+#define NVIC_INIT_ITNS4 0\r
+\r
+/*\r
+// Interrupts 128..159\r
+// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS4_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 5 (Interrupts 160..191)\r
+*/\r
+#define NVIC_INIT_ITNS5 0\r
+\r
+/*\r
+// Interrupts 160..191\r
+// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS5_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 6 (Interrupts 192..223)\r
+*/\r
+#define NVIC_INIT_ITNS6 0\r
+\r
+/*\r
+// Interrupts 192..223\r
+// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS6_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 7 (Interrupts 224..255)\r
+*/\r
+#define NVIC_INIT_ITNS7 0\r
+\r
+/*\r
+// Interrupts 224..255\r
+// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS7_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 8 (Interrupts 256..287)\r
+*/\r
+#define NVIC_INIT_ITNS8 0\r
+\r
+/*\r
+// Interrupts 0..31\r
+// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS8_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 9 (Interrupts 288..319)\r
+*/\r
+#define NVIC_INIT_ITNS9 0\r
+\r
+/*\r
+// Interrupts 32..63\r
+// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS9_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 10 (Interrupts 320..351)\r
+*/\r
+#define NVIC_INIT_ITNS10 0\r
+\r
+/*\r
+// Interrupts 64..95\r
+// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS10_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 11 (Interrupts 352..383)\r
+*/\r
+#define NVIC_INIT_ITNS11 0\r
+\r
+/*\r
+// Interrupts 96..127\r
+// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS11_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 12 (Interrupts 384..415)\r
+*/\r
+#define NVIC_INIT_ITNS12 0\r
+\r
+/*\r
+// Interrupts 128..159\r
+// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS12_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 13 (Interrupts 416..447)\r
+*/\r
+#define NVIC_INIT_ITNS13 0\r
+\r
+/*\r
+// Interrupts 160..191\r
+// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS13_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 14 (Interrupts 448..479)\r
+*/\r
+#define NVIC_INIT_ITNS14 0\r
+\r
+/*\r
+// Interrupts 192..223\r
+// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS14_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 15 (Interrupts 480..511)\r
+*/\r
+#define NVIC_INIT_ITNS15 0\r
+\r
+/*\r
+// Interrupts 224..255\r
+// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS15_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// </h>\r
+*/\r
+\r
+\r
+\r
+/*\r
+ max 128 SAU regions.\r
+ SAU regions are defined in partition.h\r
+ */\r
+\r
+#define SAU_INIT_REGION(n) \\r
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \\r
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \\r
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \\r
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U\r
+\r
+/**\r
+ \brief Setup a SAU Region\r
+ \details Writes the region information contained in SAU_Region to the\r
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Setup (void)\r
+{\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+\r
+ #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\r
+ SAU_INIT_REGION(0);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\r
+ SAU_INIT_REGION(1);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\r
+ SAU_INIT_REGION(2);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\r
+ SAU_INIT_REGION(3);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\r
+ SAU_INIT_REGION(4);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\r
+ SAU_INIT_REGION(5);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\r
+ SAU_INIT_REGION(6);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\r
+ SAU_INIT_REGION(7);\r
+ #endif\r
+\r
+ /* repeat this for all possible SAU regions */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+\r
+ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\r
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\r
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;\r
+ #endif\r
+\r
+ #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\r
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |\r
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);\r
+\r
+ SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |\r
+ SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |\r
+ ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |\r
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\r
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |\r
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);\r
+ #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\r
+\r
+ #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\r
+ defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\r
+\r
+ SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) |\r
+ ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\r
+\r
+ FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\r
+ ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |\r
+ ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\r
+ ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\r
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\r
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\r
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\r
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\r
+ NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\r
+ NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\r
+ NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\r
+ NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\r
+ NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\r
+ NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\r
+ NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\r
+ NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\r
+ NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\r
+ NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\r
+ NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\r
+ NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\r
+ #endif\r
+\r
+ /* repeat this for all possible ITNS elements */\r
+\r
+}\r
+\r
+#endif /* PARTITION_ARMCM33_H */\r
--- /dev/null
+;/**************************************************************************//**\r
+; * @file startup_ARMCM33.s\r
+; * @brief CMSIS Core Device Startup File for\r
+; * ARMCM33 Device Series\r
+; * @version V5.00\r
+; * @date 21. October 2016\r
+; ******************************************************************************/\r
+;/*\r
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
+; *\r
+; * SPDX-License-Identifier: Apache-2.0\r
+; *\r
+; * Licensed under the Apache License, Version 2.0 (the License); you may\r
+; * not use this file except in compliance with the License.\r
+; * You may obtain a copy of the License at\r
+; *\r
+; * www.apache.org/licenses/LICENSE-2.0\r
+; *\r
+; * Unless required by applicable law or agreed to in writing, software\r
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+; * See the License for the specific language governing permissions and\r
+; * limitations under the License.\r
+; */\r
+\r
+;/*\r
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+;*/\r
+\r
+\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000C00\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+\r
+__Vectors DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD SecureFault_Handler ; Secure Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WDT_IRQHandler ; 0: Watchdog Timer\r
+ DCD RTC_IRQHandler ; 1: Real Time Clock\r
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1\r
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3\r
+ DCD MCIA_IRQHandler ; 4: MCIa\r
+ DCD MCIB_IRQHandler ; 5: MCIb\r
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA\r
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA\r
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA\r
+ DCD UART4_IRQHandler ; 9: UART4 - not connected\r
+ DCD AACI_IRQHandler ; 10: AACI / AC97\r
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt\r
+ DCD ENET_IRQHandler ; 12: Ethernet\r
+ DCD USBDC_IRQHandler ; 13: USB Device\r
+ DCD USBHC_IRQHandler ; 14: USB Host Controller\r
+ DCD CHLCD_IRQHandler ; 15: Character LCD\r
+ DCD FLEXRAY_IRQHandler ; 16: Flexray\r
+ DCD CAN_IRQHandler ; 17: CAN\r
+ DCD LIN_IRQHandler ; 18: LIN\r
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC\r
+ DCD 0 ; 20: Reserved\r
+ DCD 0 ; 21: Reserved\r
+ DCD 0 ; 22: Reserved\r
+ DCD 0 ; 23: Reserved\r
+ DCD 0 ; 24: Reserved\r
+ DCD 0 ; 25: Reserved\r
+ DCD 0 ; 26: Reserved\r
+ DCD 0 ; 27: Reserved\r
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD\r
+ DCD 0 ; 29: Reserved - CPU FPGA\r
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA\r
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA\r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+ AREA |.text|, CODE, READONLY\r
+\r
+\r
+; Reset Handler\r
+\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT SystemInit\r
+ IMPORT __main\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SecureFault_Handler\\r
+ PROC\r
+ EXPORT SecureFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ EXPORT WDT_IRQHandler [WEAK]\r
+ EXPORT RTC_IRQHandler [WEAK]\r
+ EXPORT TIM0_IRQHandler [WEAK]\r
+ EXPORT TIM2_IRQHandler [WEAK]\r
+ EXPORT MCIA_IRQHandler [WEAK]\r
+ EXPORT MCIB_IRQHandler [WEAK]\r
+ EXPORT UART0_IRQHandler [WEAK]\r
+ EXPORT UART1_IRQHandler [WEAK]\r
+ EXPORT UART2_IRQHandler [WEAK]\r
+ EXPORT UART3_IRQHandler [WEAK]\r
+ EXPORT UART4_IRQHandler [WEAK]\r
+ EXPORT AACI_IRQHandler [WEAK]\r
+ EXPORT CLCD_IRQHandler [WEAK]\r
+ EXPORT ENET_IRQHandler [WEAK]\r
+ EXPORT USBDC_IRQHandler [WEAK]\r
+ EXPORT USBHC_IRQHandler [WEAK]\r
+ EXPORT CHLCD_IRQHandler [WEAK]\r
+ EXPORT FLEXRAY_IRQHandler [WEAK]\r
+ EXPORT CAN_IRQHandler [WEAK]\r
+ EXPORT LIN_IRQHandler [WEAK]\r
+ EXPORT I2C_IRQHandler [WEAK]\r
+ EXPORT CPU_CLCD_IRQHandler [WEAK]\r
+ EXPORT SPI_IRQHandler [WEAK]\r
+\r
+WDT_IRQHandler\r
+RTC_IRQHandler\r
+TIM0_IRQHandler\r
+TIM2_IRQHandler\r
+MCIA_IRQHandler\r
+MCIB_IRQHandler\r
+UART0_IRQHandler\r
+UART1_IRQHandler\r
+UART2_IRQHandler\r
+UART3_IRQHandler\r
+UART4_IRQHandler\r
+AACI_IRQHandler\r
+CLCD_IRQHandler\r
+ENET_IRQHandler\r
+USBDC_IRQHandler\r
+USBHC_IRQHandler\r
+CHLCD_IRQHandler\r
+FLEXRAY_IRQHandler\r
+CAN_IRQHandler\r
+LIN_IRQHandler\r
+I2C_IRQHandler\r
+CPU_CLCD_IRQHandler\r
+SPI_IRQHandler\r
+ B .\r
+\r
+ ENDP\r
+\r
+\r
+ ALIGN\r
+\r
+\r
+; User Initial Stack & Heap\r
+\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+\r
+__user_initial_stackheap PROC\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+\r
+ END\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_ARMCM33.c\r
+ * @brief CMSIS Device System Source File for\r
+ * ARMCM33 Device Series\r
+ * @version V5.00\r
+ * @date 02. November 2016\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined (ARMCM33)\r
+ #include "ARMCM33.h"\r
+#elif defined (ARMCM33_TZ)\r
+ #include "ARMCM33_TZ.h"\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #include "partition_ARMCM33.h"\r
+ #endif\r
+#elif defined (ARMCM33_DSP_FP)\r
+ #include "ARMCM33_DSP_FP.h"\r
+#elif defined (ARMCM33_DSP_FP_TZ)\r
+ #include "ARMCM33_DSP_FP_TZ.h"\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #include "partition_ARMCM33.h"\r
+ #endif\r
+#else\r
+ #error device not specified!\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ Define clocks\r
+ *----------------------------------------------------------------------------*/\r
+#define XTAL ( 5000000UL) /* Oscillator frequency */\r
+\r
+#define SYSTEM_CLOCK (5U * XTAL)\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Externals\r
+ *----------------------------------------------------------------------------*/\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ extern uint32_t __Vectors;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ System Core Clock Variable\r
+ *----------------------------------------------------------------------------*/\r
+uint32_t SystemCoreClock = SYSTEM_CLOCK;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ System Core Clock update function\r
+ *----------------------------------------------------------------------------*/\r
+void SystemCoreClockUpdate (void)\r
+{\r
+ SystemCoreClock = SYSTEM_CLOCK;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ System initialization function\r
+ *----------------------------------------------------------------------------*/\r
+void SystemInit (void)\r
+{\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ SCB->VTOR = (uint32_t) &__Vectors;\r
+#endif\r
+\r
+#if defined (__FPU_USED) && (__FPU_USED == 1U)\r
+ SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */\r
+ (3U << 11U*2U) ); /* set CP11 Full Access */\r
+#endif\r
+\r
+#ifdef UNALIGNED_SUPPORT_DISABLE\r
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\r
+#endif\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ TZ_SAU_Setup();\r
+#endif\r
+\r
+ SystemCoreClock = SYSTEM_CLOCK;\r
+}\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "tz_demo.h"\r
+#include "mpu_demo.h"\r
+\r
+/* Externs needed by the MPU setup code. These must match the memory map as\r
+ * specified in Scatter-Loading description file (FreeRTOSDemo_ns.sct). */\r
+/* Privileged flash. */\r
+const uint32_t * __privileged_functions_start__ = ( uint32_t * ) ( 0x00200000 );\r
+const uint32_t * __privileged_functions_end__ = ( uint32_t * ) ( 0x00208000 - 0x1 ); /* Last address in privileged Flash region. */\r
+\r
+/* Flash containing system calls. */\r
+const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) ( 0x00208000 );\r
+const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) ( 0x00209000 - 0x1 ); /* Last address in Flash region containing system calls. */\r
+\r
+/* Unprivileged flash. Note that the section containing\r
+ * system calls is unprivilged so that unprivleged tasks\r
+ * can make system calls. */\r
+const uint32_t * __unprivileged_flash_start__ = ( uint32_t * ) ( 0x00209000 );\r
+const uint32_t * __unprivileged_flash_end__ = ( uint32_t * ) ( 0x00400000 - 0x1 ); /* Last address in un-privileged Flash region. */\r
+\r
+/* 512 bytes (0x200) of RAM starting at 0x30008000 is\r
+ * priviledged access only. This contains kernel data. */\r
+const uint32_t * __privileged_sram_start__ = ( uint32_t * ) ( 0x20200000 );\r
+const uint32_t * __privileged_sram_end__ = ( uint32_t * ) ( 0x20201000 - 0x1 ); /* Last address in privileged RAM. */\r
+;\r
+/* Unprivileged RAM. */\r
+const uint32_t * __unprivileged_sram_start__ = ( uint32_t * ) ( 0x20201000 );\r
+const uint32_t * __unprivileged_sram_end__ = ( uint32_t * ) ( 0x20220000 - 0x1 ); /* Last address in un-privileged RAM. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Create all demo tasks.\r
+ */\r
+static void prvCreateTasks( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCreateTasks( void )\r
+{\r
+ /* Create tasks for the MPU Demo. */\r
+ vStartMPUDemo();\r
+\r
+ /* Create tasks for the TZ Demo. */\r
+ vStartTZDemo();\r
+\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Stack overflow hook. */\r
+void vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName )\r
+{\r
+ /* Force an assert. */\r
+ configASSERT( pcTaskName == 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Non-Secure main. */\r
+int main( void )\r
+{\r
+ /* Create tasks. */\r
+ prvCreateTasks();\r
+\r
+ /* Start scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not reach here as the schedular is already started. */\r
+ for( ; ; )\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an\r
+ * implementation of vApplicationGetIdleTaskMemory() to provide the memory that\r
+ * is used by the Idle task. */\r
+void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,\r
+ StackType_t ** ppxIdleTaskStackBuffer,\r
+ uint32_t * pulIdleTaskStackSize )\r
+{\r
+ /* If the buffers to be provided to the Idle task are declared inside this\r
+ * function then they must be declared static - otherwise they will be\r
+ * allocated on the stack and so not exists after this function exits. */\r
+ static StaticTask_t xIdleTaskTCB;\r
+ static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__((aligned(32)));\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle\r
+ * task's state will be stored. */\r
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Idle task's stack. */\r
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
+ * Note that, as the array is necessarily of type StackType_t,\r
+ * configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the\r
+ * application must provide an implementation of vApplicationGetTimerTaskMemory()\r
+ * to provide the memory that is used by the Timer service task. */\r
+void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,\r
+ StackType_t ** ppxTimerTaskStackBuffer,\r
+ uint32_t * pulTimerTaskStackSize )\r
+{\r
+ /* If the buffers to be provided to the Timer task are declared inside this\r
+ * function then they must be declared static - otherwise they will be\r
+ * allocated on the stack and so not exists after this function exits. */\r
+ static StaticTask_t xTimerTaskTCB;\r
+ static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__((aligned(32)));\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
+ * task's state will be stored. */\r
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Timer task's stack. */\r
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
+ * Note that, as the array is necessarily of type StackType_t,\r
+ * configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */\r
+ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief The mem fault handler implementation calls a function called\r
+ * vHandleMemoryFault.\r
+ */\r
+void MemManage_Handler( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, handler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " handler_address_const: .word vHandleMemoryFault \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+; *************************************************************\r
+; *** Scatter-Loading Description File generated by uVision ***\r
+; *************************************************************\r
+\r
+LR_IROM_S 0x00000000 0x00200000 ; load region size_region\r
+{\r
+ ER_IROM_S +0 ; load address = execution address\r
+ {\r
+ *.o (RESET, +First)\r
+ *(InRoot$$Sections)\r
+ *(Veneer$$CMSE) ; This region is marked as Non-Secure callable in partition.h.\r
+ .ANY (+RO)\r
+ .ANY (+XO)\r
+ }\r
+\r
+ RW_IRAM_S 0x20000000 0x00020000 ; RW data\r
+ {\r
+ .ANY (+RW +ZI)\r
+ }\r
+}\r
--- /dev/null
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+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj; *.o</oExt>
+ <lExt>*.lib</lExt>
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+ <pExt>*.plm</pExt>
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+ <DaveTm>
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+ <TabStop>8</TabStop>
+ <ListingPath>.\Listings\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
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+ <OPTXL>
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+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
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+ <OPTFL>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
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+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
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+ <tDlgPa></tDlgPa>
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+ <pMon>BIN\DbgFMv8M.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGTARM</Key>
+ <Name>(6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
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+ <Key>ARMDBGFLAGS</Key>
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+ </SetRegEntry>
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+ <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
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+ <Key>DbgFMv8M</Key>
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+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2V8M</Key>
+ <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>0</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
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+ <AscS3>0</AscS3>
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+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ <bAutoGenD>0</bAutoGenD>
+ <LntExFlags>0</LntExFlags>
+ <pMisraName></pMisraName>
+ <pszMrule></pszMrule>
+ <pSingCmds></pSingCmds>
+ <pMultCmds></pMultCmds>
+ <pMisraNamep></pMisraNamep>
+ <pszMrulep></pszMrulep>
+ <pSingCmdsp></pSingCmdsp>
+ <pMultCmdsp></pMultCmdsp>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>SecureContext</GroupName>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
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+ <FilenameWithoutPath>secure_context.h</FilenameWithoutPath>
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--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+ <SchemaVersion>2.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>FVP Simulation Model</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+ <uAC6>1</uAC6>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM33_DSP_FP_TZ</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.5.4.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>
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+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
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+ <SLE66LinkerMisc></SLE66LinkerMisc>
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+ <bCustSvd>0</bCustSvd>
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+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
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+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Objects\</OutputDirectory>
+ <OutputName>FreeRTOSDemo_s</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\Listings\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
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+ <UserProg2Name></UserProg2Name>
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+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
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+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ </BeforeMake>
+ <AfterMake>
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+ </AfterMake>
+ <SelectedForBatchBuild>1</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
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+ <ModuleSelection>0</ModuleSelection>
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+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
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+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
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+ <DllOption>
+ <SimDllName></SimDllName>
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+ <SimDlgDll></SimDlgDll>
+ <SimDlgDllArguments></SimDlgDllArguments>
+ <TargetDllName>SARMV8M.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4098</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2V8M.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M33"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>1</hadIRAM2>
+ <hadIROM2>1</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>1</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x200000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x200000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x200000</StartAddress>
+ <Size>0x200000</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x20200000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>2</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <v6Lang>3</v6Lang>
+ <v6LangP>1</v6LangP>
+ <vShortEn>1</vShortEn>
+ <vShortWch>1</vShortWch>
+ <v6Lto>0</v6Lto>
+ <v6WtE>0</v6WtE>
+ <v6Rtti>0</v6Rtti>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\Config;..\..\..\Source\include;..\..\..\Source\portable\GCC\ARM_CM33\secure</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <uClangAs>0</uClangAs>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile>.\FreeRTOSDemo_s.sct</ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>SecureContext</GroupName>
+ <Files>
+ <File>
+ <FileName>secure_context.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM33\secure\secure_context.h</FilePath>
+ </File>
+ <File>
+ <FileName>secure_context.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM33\secure\secure_context.c</FilePath>
+ </File>
+ <File>
+ <FileName>secure_context_port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM33\secure\secure_context_port.c</FilePath>
+ </File>
+ <File>
+ <FileName>secure_port_macros.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM33\secure\secure_port_macros.h</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>SecureInit</GroupName>
+ <Files>
+ <File>
+ <FileName>secure_init.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM33\secure\secure_init.h</FilePath>
+ </File>
+ <File>
+ <FileName>secure_init.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM33\secure\secure_init.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>SecureHeap</GroupName>
+ <Files>
+ <File>
+ <FileName>secure_heap.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM33\secure\secure_heap.h</FilePath>
+ </File>
+ <File>
+ <FileName>secure_heap.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM33\secure\secure_heap.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>NSCFunctions</GroupName>
+ <Files>
+ <File>
+ <FileName>nsc_functions.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\Common\ARMv8M\tz_demo\nsc_functions.h</FilePath>
+ </File>
+ <File>
+ <FileName>nsc_functions.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\ARMv8M\tz_demo\nsc_functions.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>User</GroupName>
+ <Files>
+ <File>
+ <FileName>main_s.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main_s.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ <Group>
+ <GroupName>::Device</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+ <RTE>
+ <apis/>
+ <components>
+ <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.0" condition="ARMv6_7_8-M Device">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta16"/>
+ <targetInfos>
+ <targetInfo name="FVP Simulation Model"/>
+ </targetInfos>
+ </component>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.2.0"/>
+ <targetInfos>
+ <targetInfo name="FVP Simulation Model"/>
+ </targetInfos>
+ </component>
+ </components>
+ <files>
+ <file attr="config" category="header" condition="ARMv8-M TZ Device" name="Device\ARM\ARMCM33\Include\Template\partition_ARMCM33.h" version="1.1.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.4.0"/>
+ <targetInfos>
+ <targetInfo name="FVP Simulation Model"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM33\Source\ARM\startup_ARMCM33.s" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.4.0"/>
+ <targetInfos>
+ <targetInfo name="FVP Simulation Model"/>
+ </targetInfos>
+ </file>
+ <file attr="config" category="sourceC" name="Device\ARM\ARMCM33\Source\system_ARMCM33.c" version="1.0.0">
+ <instance index="0">RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c</instance>
+ <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.1.0" condition="ARMCM33 CMSIS"/>
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.4.0"/>
+ <targetInfos>
+ <targetInfo name="FVP Simulation Model"/>
+ </targetInfos>
+ </file>
+ </files>
+ </RTE>
+
+</Project>
--- /dev/null
+/**************************************************************************//**\r
+ * @file partition_ARMCM33.h\r
+ * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33\r
+ * @version V5.0.1\r
+ * @date 07. December 2016\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef PARTITION_ARMCM33_H\r
+#define PARTITION_ARMCM33_H\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\r
+*/\r
+\r
+/*\r
+// <e>Initialize Security Attribution Unit (SAU) CTRL register\r
+*/\r
+#define SAU_INIT_CTRL 1\r
+\r
+/*\r
+// <q> Enable SAU\r
+// <i> Value for SAU->CTRL register bit ENABLE\r
+*/\r
+#define SAU_INIT_CTRL_ENABLE 1\r
+\r
+/*\r
+// <o> When SAU is disabled\r
+// <0=> All Memory is Secure\r
+// <1=> All Memory is Non-Secure\r
+// <i> Value for SAU->CTRL register bit ALLNS\r
+// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\r
+*/\r
+#define SAU_INIT_CTRL_ALLNS 0\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <h>Initialize Security Attribution Unit (SAU) Address Regions\r
+// <i>SAU configuration specifies regions to be one of:\r
+// <i> - Secure and Non-Secure Callable\r
+// <i> - Non-Secure\r
+// <i>Note: All memory regions not configured by SAU are Secure\r
+*/\r
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */\r
+\r
+/*\r
+// <e>Initialize SAU Region 0\r
+// <i> Setup SAU Region 0 memory attributes\r
+*/\r
+#define SAU_INIT_REGION0 1\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC0 1\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 1\r
+// <i> Setup SAU Region 1 memory attributes\r
+*/\r
+#define SAU_INIT_REGION1 1\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START1 0x00200000\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END1 0x003FFFFF\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC1 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 2\r
+// <i> Setup SAU Region 2 memory attributes\r
+*/\r
+#define SAU_INIT_REGION2 1\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START2 0x20200000\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END2 0x203FFFFF\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC2 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 3\r
+// <i> Setup SAU Region 3 memory attributes\r
+*/\r
+#define SAU_INIT_REGION3 1\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START3 0x40000000\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END3 0x40040000\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC3 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 4\r
+// <i> Setup SAU Region 4 memory attributes\r
+*/\r
+#define SAU_INIT_REGION4 0\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC4 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 5\r
+// <i> Setup SAU Region 5 memory attributes\r
+*/\r
+#define SAU_INIT_REGION5 0\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START5 0x00000000\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END5 0x00000000\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC5 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 6\r
+// <i> Setup SAU Region 6 memory attributes\r
+*/\r
+#define SAU_INIT_REGION6 0\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START6 0x00000000\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END6 0x00000000\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC6 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize SAU Region 7\r
+// <i> Setup SAU Region 7 memory attributes\r
+*/\r
+#define SAU_INIT_REGION7 0\r
+\r
+/*\r
+// <o>Start Address <0-0xFFFFFFE0>\r
+*/\r
+#define SAU_INIT_START7 0x00000000\r
+\r
+/*\r
+// <o>End Address <0x1F-0xFFFFFFFF>\r
+*/\r
+#define SAU_INIT_END7 0x00000000\r
+\r
+/*\r
+// <o>Region is\r
+// <0=>Non-Secure\r
+// <1=>Secure, Non-Secure Callable\r
+*/\r
+#define SAU_INIT_NSC7 0\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// </h>\r
+*/\r
+\r
+/*\r
+// <e>Setup behaviour of Sleep and Exception Handling\r
+*/\r
+#define SCB_CSR_AIRCR_INIT 1\r
+\r
+/*\r
+// <o> Deep Sleep can be enabled by\r
+// <0=>Secure and Non-Secure state\r
+// <1=>Secure state only\r
+// <i> Value for SCB->CSR register bit DEEPSLEEPS\r
+*/\r
+#define SCB_CSR_DEEPSLEEPS_VAL 1\r
+\r
+/*\r
+// <o>System reset request accessible from\r
+// <0=> Secure and Non-Secure state\r
+// <1=> Secure state only\r
+// <i> Value for SCB->AIRCR register bit SYSRESETREQS\r
+*/\r
+#define SCB_AIRCR_SYSRESETREQS_VAL 1\r
+\r
+/*\r
+// <o>Priority of Non-Secure exceptions is\r
+// <0=> Not altered\r
+// <1=> Lowered to 0x80-0xFF\r
+// <i> Value for SCB->AIRCR register bit PRIS\r
+*/\r
+#define SCB_AIRCR_PRIS_VAL 1\r
+\r
+/*\r
+// <o>BusFault, HardFault, and NMI target\r
+// <0=> Secure state\r
+// <1=> Non-Secure state\r
+// <i> Value for SCB->AIRCR register bit BFHFNMINS\r
+*/\r
+#define SCB_AIRCR_BFHFNMINS_VAL 0\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Setup behaviour of Floating Point Unit\r
+*/\r
+#define TZ_FPU_NS_USAGE 1\r
+\r
+/*\r
+// <o>Floating Point Unit usage\r
+// <0=> Secure state only\r
+// <3=> Secure and Non-Secure state\r
+// <i> Value for SCB->NSACR register bits CP10, CP11\r
+*/\r
+#define SCB_NSACR_CP10_11_VAL 3\r
+\r
+/*\r
+// <o>Treat floating-point registers as Secure\r
+// <0=> Disabled\r
+// <1=> Enabled\r
+// <i> Value for FPU->FPCCR register bit TS\r
+*/\r
+#define FPU_FPCCR_TS_VAL 0\r
+\r
+/*\r
+// <o>Clear on return (CLRONRET) accessibility\r
+// <0=> Secure and Non-Secure state\r
+// <1=> Secure state only\r
+// <i> Value for FPU->FPCCR register bit CLRONRETS\r
+*/\r
+#define FPU_FPCCR_CLRONRETS_VAL 0\r
+\r
+/*\r
+// <o>Clear floating-point caller saved registers on exception return\r
+// <0=> Disabled\r
+// <1=> Enabled\r
+// <i> Value for FPU->FPCCR register bit CLRONRET\r
+*/\r
+#define FPU_FPCCR_CLRONRET_VAL 1\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <h>Setup Interrupt Target\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 0 (Interrupts 0..31)\r
+*/\r
+#define NVIC_INIT_ITNS0 1\r
+\r
+/*\r
+// Interrupts 0..31\r
+// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS0_VAL 0x0000122B\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 1 (Interrupts 32..63)\r
+*/\r
+#define NVIC_INIT_ITNS1 1\r
+\r
+/*\r
+// Interrupts 32..63\r
+// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS1_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 2 (Interrupts 64..95)\r
+*/\r
+#define NVIC_INIT_ITNS2 0\r
+\r
+/*\r
+// Interrupts 64..95\r
+// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS2_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 3 (Interrupts 96..127)\r
+*/\r
+#define NVIC_INIT_ITNS3 0\r
+\r
+/*\r
+// Interrupts 96..127\r
+// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS3_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 4 (Interrupts 128..159)\r
+*/\r
+#define NVIC_INIT_ITNS4 0\r
+\r
+/*\r
+// Interrupts 128..159\r
+// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS4_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 5 (Interrupts 160..191)\r
+*/\r
+#define NVIC_INIT_ITNS5 0\r
+\r
+/*\r
+// Interrupts 160..191\r
+// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS5_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 6 (Interrupts 192..223)\r
+*/\r
+#define NVIC_INIT_ITNS6 0\r
+\r
+/*\r
+// Interrupts 192..223\r
+// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS6_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 7 (Interrupts 224..255)\r
+*/\r
+#define NVIC_INIT_ITNS7 0\r
+\r
+/*\r
+// Interrupts 224..255\r
+// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS7_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 8 (Interrupts 256..287)\r
+*/\r
+#define NVIC_INIT_ITNS8 0\r
+\r
+/*\r
+// Interrupts 0..31\r
+// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS8_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 9 (Interrupts 288..319)\r
+*/\r
+#define NVIC_INIT_ITNS9 0\r
+\r
+/*\r
+// Interrupts 32..63\r
+// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS9_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 10 (Interrupts 320..351)\r
+*/\r
+#define NVIC_INIT_ITNS10 0\r
+\r
+/*\r
+// Interrupts 64..95\r
+// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS10_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 11 (Interrupts 352..383)\r
+*/\r
+#define NVIC_INIT_ITNS11 0\r
+\r
+/*\r
+// Interrupts 96..127\r
+// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS11_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 12 (Interrupts 384..415)\r
+*/\r
+#define NVIC_INIT_ITNS12 0\r
+\r
+/*\r
+// Interrupts 128..159\r
+// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS12_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 13 (Interrupts 416..447)\r
+*/\r
+#define NVIC_INIT_ITNS13 0\r
+\r
+/*\r
+// Interrupts 160..191\r
+// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS13_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 14 (Interrupts 448..479)\r
+*/\r
+#define NVIC_INIT_ITNS14 0\r
+\r
+/*\r
+// Interrupts 192..223\r
+// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS14_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// <e>Initialize ITNS 15 (Interrupts 480..511)\r
+*/\r
+#define NVIC_INIT_ITNS15 0\r
+\r
+/*\r
+// Interrupts 224..255\r
+// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state\r
+// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state\r
+// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state\r
+// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state\r
+// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state\r
+// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state\r
+// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state\r
+// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state\r
+// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state\r
+// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state\r
+// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\r
+// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\r
+// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\r
+// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\r
+// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\r
+// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\r
+// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\r
+// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\r
+// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\r
+// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\r
+// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\r
+// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\r
+// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\r
+// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\r
+// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\r
+// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\r
+// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\r
+// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\r
+// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\r
+// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\r
+// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\r
+// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\r
+*/\r
+#define NVIC_INIT_ITNS15_VAL 0x00000000\r
+\r
+/*\r
+// </e>\r
+*/\r
+\r
+/*\r
+// </h>\r
+*/\r
+\r
+\r
+\r
+/*\r
+ max 128 SAU regions.\r
+ SAU regions are defined in partition.h\r
+ */\r
+\r
+#define SAU_INIT_REGION(n) \\r
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \\r
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \\r
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \\r
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U\r
+\r
+/**\r
+ \brief Setup a SAU Region\r
+ \details Writes the region information contained in SAU_Region to the\r
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Setup (void)\r
+{\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+\r
+ #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\r
+ SAU_INIT_REGION(0);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\r
+ SAU_INIT_REGION(1);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\r
+ SAU_INIT_REGION(2);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\r
+ SAU_INIT_REGION(3);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\r
+ SAU_INIT_REGION(4);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\r
+ SAU_INIT_REGION(5);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\r
+ SAU_INIT_REGION(6);\r
+ #endif\r
+\r
+ #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\r
+ SAU_INIT_REGION(7);\r
+ #endif\r
+\r
+ /* repeat this for all possible SAU regions */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+\r
+ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\r
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\r
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;\r
+ #endif\r
+\r
+ #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\r
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |\r
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);\r
+\r
+ SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |\r
+ SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |\r
+ ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |\r
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\r
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |\r
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);\r
+ #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\r
+\r
+ #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\r
+ defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\r
+\r
+ SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) |\r
+ ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\r
+\r
+ FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\r
+ ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |\r
+ ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\r
+ ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\r
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\r
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\r
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\r
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\r
+ NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\r
+ NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\r
+ NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\r
+ NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\r
+ NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\r
+ NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\r
+ NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\r
+ NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\r
+ NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\r
+ NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\r
+ NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\r
+ #endif\r
+\r
+ #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\r
+ NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\r
+ #endif\r
+\r
+ /* repeat this for all possible ITNS elements */\r
+\r
+}\r
+\r
+#endif /* PARTITION_ARMCM33_H */\r
--- /dev/null
+;/**************************************************************************//**\r
+; * @file startup_ARMCM33.s\r
+; * @brief CMSIS Core Device Startup File for\r
+; * ARMCM33 Device Series\r
+; * @version V5.00\r
+; * @date 21. October 2016\r
+; ******************************************************************************/\r
+;/*\r
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
+; *\r
+; * SPDX-License-Identifier: Apache-2.0\r
+; *\r
+; * Licensed under the Apache License, Version 2.0 (the License); you may\r
+; * not use this file except in compliance with the License.\r
+; * You may obtain a copy of the License at\r
+; *\r
+; * www.apache.org/licenses/LICENSE-2.0\r
+; *\r
+; * Unless required by applicable law or agreed to in writing, software\r
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+; * See the License for the specific language governing permissions and\r
+; * limitations under the License.\r
+; */\r
+\r
+;/*\r
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+;*/\r
+\r
+\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000C00\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+\r
+__Vectors DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD SecureFault_Handler ; Secure Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WDT_IRQHandler ; 0: Watchdog Timer\r
+ DCD RTC_IRQHandler ; 1: Real Time Clock\r
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1\r
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3\r
+ DCD MCIA_IRQHandler ; 4: MCIa\r
+ DCD MCIB_IRQHandler ; 5: MCIb\r
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA\r
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA\r
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA\r
+ DCD UART4_IRQHandler ; 9: UART4 - not connected\r
+ DCD AACI_IRQHandler ; 10: AACI / AC97\r
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt\r
+ DCD ENET_IRQHandler ; 12: Ethernet\r
+ DCD USBDC_IRQHandler ; 13: USB Device\r
+ DCD USBHC_IRQHandler ; 14: USB Host Controller\r
+ DCD CHLCD_IRQHandler ; 15: Character LCD\r
+ DCD FLEXRAY_IRQHandler ; 16: Flexray\r
+ DCD CAN_IRQHandler ; 17: CAN\r
+ DCD LIN_IRQHandler ; 18: LIN\r
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC\r
+ DCD 0 ; 20: Reserved\r
+ DCD 0 ; 21: Reserved\r
+ DCD 0 ; 22: Reserved\r
+ DCD 0 ; 23: Reserved\r
+ DCD 0 ; 24: Reserved\r
+ DCD 0 ; 25: Reserved\r
+ DCD 0 ; 26: Reserved\r
+ DCD 0 ; 27: Reserved\r
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD\r
+ DCD 0 ; 29: Reserved - CPU FPGA\r
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA\r
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA\r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+ AREA |.text|, CODE, READONLY\r
+\r
+\r
+; Reset Handler\r
+\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT SystemInit\r
+ IMPORT __main\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SecureFault_Handler\\r
+ PROC\r
+ EXPORT SecureFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ EXPORT WDT_IRQHandler [WEAK]\r
+ EXPORT RTC_IRQHandler [WEAK]\r
+ EXPORT TIM0_IRQHandler [WEAK]\r
+ EXPORT TIM2_IRQHandler [WEAK]\r
+ EXPORT MCIA_IRQHandler [WEAK]\r
+ EXPORT MCIB_IRQHandler [WEAK]\r
+ EXPORT UART0_IRQHandler [WEAK]\r
+ EXPORT UART1_IRQHandler [WEAK]\r
+ EXPORT UART2_IRQHandler [WEAK]\r
+ EXPORT UART3_IRQHandler [WEAK]\r
+ EXPORT UART4_IRQHandler [WEAK]\r
+ EXPORT AACI_IRQHandler [WEAK]\r
+ EXPORT CLCD_IRQHandler [WEAK]\r
+ EXPORT ENET_IRQHandler [WEAK]\r
+ EXPORT USBDC_IRQHandler [WEAK]\r
+ EXPORT USBHC_IRQHandler [WEAK]\r
+ EXPORT CHLCD_IRQHandler [WEAK]\r
+ EXPORT FLEXRAY_IRQHandler [WEAK]\r
+ EXPORT CAN_IRQHandler [WEAK]\r
+ EXPORT LIN_IRQHandler [WEAK]\r
+ EXPORT I2C_IRQHandler [WEAK]\r
+ EXPORT CPU_CLCD_IRQHandler [WEAK]\r
+ EXPORT SPI_IRQHandler [WEAK]\r
+\r
+WDT_IRQHandler\r
+RTC_IRQHandler\r
+TIM0_IRQHandler\r
+TIM2_IRQHandler\r
+MCIA_IRQHandler\r
+MCIB_IRQHandler\r
+UART0_IRQHandler\r
+UART1_IRQHandler\r
+UART2_IRQHandler\r
+UART3_IRQHandler\r
+UART4_IRQHandler\r
+AACI_IRQHandler\r
+CLCD_IRQHandler\r
+ENET_IRQHandler\r
+USBDC_IRQHandler\r
+USBHC_IRQHandler\r
+CHLCD_IRQHandler\r
+FLEXRAY_IRQHandler\r
+CAN_IRQHandler\r
+LIN_IRQHandler\r
+I2C_IRQHandler\r
+CPU_CLCD_IRQHandler\r
+SPI_IRQHandler\r
+ B .\r
+\r
+ ENDP\r
+\r
+\r
+ ALIGN\r
+\r
+\r
+; User Initial Stack & Heap\r
+\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+\r
+__user_initial_stackheap PROC\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+\r
+ END\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_ARMCM33.c\r
+ * @brief CMSIS Device System Source File for\r
+ * ARMCM33 Device Series\r
+ * @version V5.00\r
+ * @date 02. November 2016\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined (ARMCM33)\r
+ #include "ARMCM33.h"\r
+#elif defined (ARMCM33_TZ)\r
+ #include "ARMCM33_TZ.h"\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #include "partition_ARMCM33.h"\r
+ #endif\r
+#elif defined (ARMCM33_DSP_FP)\r
+ #include "ARMCM33_DSP_FP.h"\r
+#elif defined (ARMCM33_DSP_FP_TZ)\r
+ #include "ARMCM33_DSP_FP_TZ.h"\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #include "partition_ARMCM33.h"\r
+ #endif\r
+#else\r
+ #error device not specified!\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ Define clocks\r
+ *----------------------------------------------------------------------------*/\r
+#define XTAL ( 5000000UL) /* Oscillator frequency */\r
+\r
+#define SYSTEM_CLOCK (5U * XTAL)\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Externals\r
+ *----------------------------------------------------------------------------*/\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ extern uint32_t __Vectors;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ System Core Clock Variable\r
+ *----------------------------------------------------------------------------*/\r
+uint32_t SystemCoreClock = SYSTEM_CLOCK;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ System Core Clock update function\r
+ *----------------------------------------------------------------------------*/\r
+void SystemCoreClockUpdate (void)\r
+{\r
+ SystemCoreClock = SYSTEM_CLOCK;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ System initialization function\r
+ *----------------------------------------------------------------------------*/\r
+void SystemInit (void)\r
+{\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ SCB->VTOR = (uint32_t) &__Vectors;\r
+#endif\r
+\r
+#if defined (__FPU_USED) && (__FPU_USED == 1U)\r
+ SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */\r
+ (3U << 11U*2U) ); /* set CP11 Full Access */\r
+#endif\r
+\r
+#ifdef UNALIGNED_SUPPORT_DISABLE\r
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\r
+#endif\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ TZ_SAU_Setup();\r
+#endif\r
+\r
+ SystemCoreClock = SYSTEM_CLOCK;\r
+}\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Use CMSE intrinsics */\r
+#include <arm_cmse.h>\r
+#include "RTE_Components.h"\r
+#include CMSIS_device_header\r
+\r
+/* FreeRTOS includes. */\r
+#include "secure_port_macros.h"\r
+\r
+/* Start address of non-secure application. */\r
+#define mainNONSECURE_APP_START_ADDRESS ( 0x200000U )\r
+\r
+/* typedef for non-secure Reset Handler. */\r
+typedef void ( *NonSecureResetHandler_t ) ( void ) __attribute__( ( cmse_nonsecure_call ) );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Boot into the non-secure code. */\r
+void BootNonSecure( uint32_t ulNonSecureStartAddress );\r
+/*-----------------------------------------------------------*/\r
+\r
+void BootNonSecure( uint32_t ulNonSecureStartAddress )\r
+{\r
+ NonSecureResetHandler_t pxNonSecureResetHandler;\r
+\r
+ /* Main Stack Pointer value for the non-secure side is the first entry in\r
+ * the non-secure vector table. Read the first entry and assign the same to\r
+ * the non-secure main stack pointer(MSP_NS). */\r
+ secureportSET_MSP_NS( *( ( uint32_t * )( ulNonSecureStartAddress ) ) );\r
+\r
+ /* Non secure Reset Handler is the second entry in the non-secure vector\r
+ * table. Read the non-secure reset handler.\r
+ */\r
+ pxNonSecureResetHandler = ( NonSecureResetHandler_t )( * ( ( uint32_t * ) ( ( ulNonSecureStartAddress ) + 4U ) ) );\r
+\r
+ /* Start non-secure software application by jumping to the non-secure Reset\r
+ * Handler. */\r
+ pxNonSecureResetHandler();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Secure main() */\r
+int main( void )\r
+{\r
+ /* Boot the non-secure code. */\r
+ BootNonSecure( mainNONSECURE_APP_START_ADDRESS );\r
+\r
+ /* Non-secure software does not return, this code is not executed. */\r
+ for( ; ; )\r
+ {\r
+ /* Should not reach here. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/**\r
+ * @brief Size of the shared memory region.\r
+ */\r
+#define SHARED_MEMORY_SIZE 32\r
+\r
+/**\r
+ * @brief Memory region shared between two tasks.\r
+ */\r
+static uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) );\r
+\r
+/**\r
+ * @brief Memory region used to track Memory Fault intentionally caused by the\r
+ * RO Access task.\r
+ *\r
+ * RO Access task sets ucROTaskFaultTracker[ 0 ] to 1 before accessing illegal\r
+ * memory. Illegal memory access causes Memory Fault and the fault handler\r
+ * checks ucROTaskFaultTracker[ 0 ] to see if this is an expected fault. We\r
+ * recover gracefully from an expected fault by jumping to the next instruction.\r
+ *\r
+ * @note We are declaring a region of 32 bytes even though we need only one. The\r
+ * reason is that the size of an MPU region must be a multiple of 32 bytes.\r
+ */\r
+static uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ) = { 0 };\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Implements the task which has Read Only access to the memory region\r
+ * ucSharedMemory.\r
+ *\r
+ * @param pvParameters[in] Parameters as passed during task creation.\r
+ */\r
+static void prvROAccessTask( void * pvParameters );\r
+\r
+/**\r
+ * @brief Implements the task which has Read Write access to the memory region\r
+ * ucSharedMemory.\r
+ *\r
+ * @param pvParameters[in] Parameters as passed during task creation.\r
+ */\r
+static void prvRWAccessTask( void * pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvROAccessTask( void * pvParameters )\r
+{\r
+uint8_t ucVal;\r
+\r
+ /* Unused parameters. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ; ; )\r
+ {\r
+ /* This task has RO access to ucSharedMemory and therefore it can read\r
+ * it but cannot modify it. */\r
+ ucVal = ucSharedMemory[ 0 ];\r
+\r
+ /* Silent compiler warnings about unused variables. */\r
+ ( void ) ucVal;\r
+\r
+ /* Since this task has Read Only access to the ucSharedMemory region,\r
+ * writing to it results in Memory Fault. Set ucROTaskFaultTracker[ 0 ]\r
+ * to 1 to tell the Memory Fault Handler that this is an expected fault.\r
+ * The handler will recover from this fault gracefully by jumping to the\r
+ * next instruction. */\r
+ ucROTaskFaultTracker[ 0 ] = 1;\r
+\r
+ /* Illegal access to generate Memory Fault. */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Wait for a second. */\r
+ vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRWAccessTask( void * pvParameters )\r
+{\r
+ /* Unused parameters. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ; ; )\r
+ {\r
+ /* This task has RW access to ucSharedMemory and therefore can write to\r
+ * it. */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Wait for a second. */\r
+ vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartMPUDemo( void )\r
+{\r
+static StackType_t xROAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );\r
+static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );\r
+TaskParameters_t xROAccessTaskParameters =\r
+{\r
+ .pvTaskCode = prvROAccessTask,\r
+ .pcName = "ROAccess",\r
+ .usStackDepth = configMINIMAL_STACK_SIZE,\r
+ .pvParameters = NULL,\r
+ .uxPriority = tskIDLE_PRIORITY,\r
+ .puxStackBuffer = xROAccessTaskStack,\r
+ .xRegions = {\r
+ { ucSharedMemory, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },\r
+ { ucROTaskFaultTracker, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },\r
+ { 0, 0, 0 },\r
+ }\r
+};\r
+TaskParameters_t xRWAccessTaskParameters =\r
+{\r
+ .pvTaskCode = prvRWAccessTask,\r
+ .pcName = "RWAccess",\r
+ .usStackDepth = configMINIMAL_STACK_SIZE,\r
+ .pvParameters = NULL,\r
+ .uxPriority = tskIDLE_PRIORITY,\r
+ .puxStackBuffer = xRWAccessTaskStack,\r
+ .xRegions = {\r
+ { ucSharedMemory, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },\r
+ { 0, 0, 0 },\r
+ { 0, 0, 0 },\r
+ }\r
+};\r
+\r
+ /* Create an unprivileged task with RO access to ucSharedMemory. */\r
+ xTaskCreateRestricted( &( xROAccessTaskParameters ), NULL );\r
+\r
+ /* Create an unprivileged task with RW access to ucSharedMemory. */\r
+ xTaskCreateRestricted( &( xRWAccessTaskParameters ), NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vHandleMemoryFault( uint32_t * pulFaultStackAddress )\r
+{\r
+uint32_t ulPC;\r
+\r
+ /* Is this an expected fault? */\r
+ if( ucROTaskFaultTracker[ 0 ] == 1 )\r
+ {\r
+ /* Read program counter. */\r
+ ulPC = pulFaultStackAddress[ 6 ];\r
+\r
+ /* Increment the program counter by 2 to move to the next instruction. */\r
+ ulPC += 2;\r
+\r
+ /* Save the new program counter on the stack. */\r
+ pulFaultStackAddress[ 6 ] = ulPC;\r
+\r
+ /* Mark the fault as handled. */\r
+ ucROTaskFaultTracker[ 0 ] = 0;\r
+ }\r
+ else\r
+ {\r
+ /* This is an unexpected fault - loop forever. */\r
+ for( ; ; )\r
+ {\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __MPU_DEMO_H__\r
+#define __MPU_DEMO_H__\r
+\r
+/**\r
+ * @brief Creates all the tasks for MPU demo.\r
+ *\r
+ * The MPU demo creates 2 unprivileged tasks - One of which has Read Only access\r
+ * to a shared memory region while the other has Read Write access. The task\r
+ * with Read Only access then tries to write to the shared memory which results\r
+ * in a Memory fault. The fault handler examines that it is the fault generated\r
+ * by the task with Read Only access and if so, it recovers from the fault\r
+ * greacefully by moving the Program Counter to the next instruction to the one\r
+ * which generated the fault. If any other memory access violation occurs, the\r
+ * fault handler will get stuck in an inifinite loop.\r
+ */\r
+void vStartMPUDemo( void );\r
+\r
+#endif /* __MPU_DEMO_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#include <arm_cmse.h>\r
+#include "nsc_functions.h"\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief Counter returned from NSCFunction.\r
+ */\r
+static uint32_t ulSecureCounter = 0;\r
+\r
+/**\r
+ * @brief typedef for non-secure callback.\r
+ */\r
+typedef void ( *NonSecureCallback_t ) ( void ) __attribute__( ( cmse_nonsecure_call ) );\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE uint32_t NSCFunction( Callback_t pxCallback )\r
+{\r
+NonSecureCallback_t pxNonSecureCallback;\r
+\r
+ /* Return function pointer with cleared LSB. */\r
+ pxNonSecureCallback = ( NonSecureCallback_t ) cmse_nsfptr_create( pxCallback );\r
+\r
+ /* Invoke the supplied callback. */\r
+ pxNonSecureCallback();\r
+\r
+ /* Increment the secure side counter. */\r
+ ulSecureCounter += 1;\r
+\r
+ /* Return the secure side counter. */\r
+ return ulSecureCounter;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __NSC_FUNCTIONS_H__\r
+#define __NSC_FUNCTIONS_H__\r
+\r
+#include <stdint.h>\r
+\r
+/**\r
+ * @brief Callback function pointer definition.\r
+ */\r
+typedef void ( *Callback_t ) ( void );\r
+\r
+/**\r
+ * @brief Invokes the supplied callback which is on the non-secure side.\r
+ *\r
+ * Returns a number which is one more than the value returned in previous\r
+ * invocation of this function. Initial invocation returns 1.\r
+ *\r
+ * @param pxCallback[in] The callback to invoke.\r
+ *\r
+ * @return A number which is one more than the value returned in previous\r
+ * invocation of this function.\r
+ */\r
+uint32_t NSCFunction( Callback_t pxCallback );\r
+\r
+#endif /* __NSC_FUNCTIONS_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Non-Secure callable functions. */\r
+#include "nsc_functions.h"\r
+\r
+/**\r
+ * @brief Counter incremented in the callback which is called from the secure\r
+ * side.\r
+ *\r
+ * The size of an MPU region must be a multiple of 32 bytes. Therefore we need\r
+ * to declare an array of size 8 to ensure that the total size is 32 bytes -\r
+ * even though we only need 4 bytes. If we do not do that, anything placed after\r
+ * 4 bytes and upto 32 bytes will also fall in the same MPU region and the task\r
+ * having access to ulNonSecureCounter will also have access to all those items.\r
+ */\r
+static uint32_t ulNonSecureCounter[8] __attribute__( ( aligned( 32 ) ) ) = { 0 };\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Creates all the tasks for TZ demo.\r
+ */\r
+void vStartTZDemo( void );\r
+\r
+/**\r
+ * @brief Increments the ulNonSecureCounter.\r
+ *\r
+ * This function is called from the secure side.\r
+ */\r
+static void prvCallback( void );\r
+\r
+/**\r
+ * @brief Implements the task which calls the functions exported from the secure\r
+ * side.\r
+ *\r
+ * @param pvParameters[in] Parameters as passed during task creation.\r
+ */\r
+static void prvSecureCallingTask( void * pvParameters );\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartTZDemo( void )\r
+{\r
+static StackType_t xSecureCallingTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );\r
+TaskParameters_t xSecureCallingTaskParameters =\r
+{\r
+ .pvTaskCode = prvSecureCallingTask,\r
+ .pcName = "SecCalling",\r
+ .usStackDepth = configMINIMAL_STACK_SIZE,\r
+ .pvParameters = NULL,\r
+ .uxPriority = tskIDLE_PRIORITY,\r
+ .puxStackBuffer = xSecureCallingTaskStack,\r
+ .xRegions = {\r
+ { ulNonSecureCounter, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },\r
+ { 0, 0, 0 },\r
+ { 0, 0, 0 },\r
+ }\r
+};\r
+\r
+ /* Create an unprivileged task which calls secure functions. */\r
+ xTaskCreateRestricted( &( xSecureCallingTaskParameters ), NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCallback( void )\r
+{\r
+ /* This function is called from the secure side. Just increment the counter\r
+ * here. The check that this counter keeps incrementing is performed in the\r
+ * prvSecureCallingTask. */\r
+ ulNonSecureCounter[ 0 ] += 1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSecureCallingTask( void * pvParameters )\r
+{\r
+uint32_t ulLastSecureCounter = 0, ulLastNonSecureCounter = 0;\r
+uint32_t ulCurrentSecureCounter = 0;\r
+\r
+ /* This task calls secure side functions. So allocate a secure context for\r
+ * it. */\r
+ portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );\r
+\r
+ for( ; ; )\r
+ {\r
+ /* Call the secure side function. It does two things:\r
+ * - It calls the supplied function (prvCallback) which in turn\r
+ * increments the non-secure counter.\r
+ * - It increments the secure counter and returns the incremented value.\r
+ * Therefore at the end of this function call both the secure and\r
+ * non-secure counters must have been incremented.\r
+ */\r
+ ulCurrentSecureCounter = NSCFunction( prvCallback );\r
+\r
+ /* Make sure that both the counters are incremented. */\r
+ configASSERT( ulCurrentSecureCounter == ulLastSecureCounter + 1 );\r
+ configASSERT( ulNonSecureCounter[ 0 ] == ulLastNonSecureCounter + 1 );\r
+\r
+ /* Update the last values for both the counters. */\r
+ ulLastSecureCounter = ulCurrentSecureCounter;\r
+ ulLastNonSecureCounter = ulNonSecureCounter[ 0 ];\r
+\r
+ /* Wait for a second. */\r
+ vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __TZ_DEMO_H__\r
+#define __TZ_DEMO_H__\r
+\r
+/**\r
+ * @brief Creates all the tasks for TZ demo.\r
+ *\r
+ * The Trust Zone (TZ) demo creates an unprivileged task which calls a secure\r
+ * side function and passes a pointer to a callback function. The secure side\r
+ * function does two things:\r
+ * 1. It calls the provided callback function. The callback function increments\r
+ * a counter.\r
+ * 2. It increments a counter and returns the incremented value.\r
+ * After the secure function call finishes, it verifies that both the counters\r
+ * are incremented.\r
+ */\r
+void vStartTZDemo( void );\r
+\r
+#endif /* __TZ_DEMO_H__ */\r
#define portTASK_USES_FLOATING_POINT()\r
#endif\r
\r
-#ifndef portTASK_CALLS_SECURE_FUNCTIONS\r
- #define portTASK_CALLS_SECURE_FUNCTIONS()\r
+#ifndef portALLOCATE_SECURE_CONTEXT\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+#endif\r
+\r
+#ifndef portHAS_STACK_OVERFLOW_CHECKING\r
+ #define portHAS_STACK_OVERFLOW_CHECKING 0\r
#endif\r
\r
#ifndef configUSE_TIME_SLICING\r
#define configUSE_TASK_FPU_SUPPORT 1\r
#endif\r
\r
+/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is\r
+currently used in ARMv8M ports. */\r
+#ifndef configENABLE_MPU\r
+ #define configENABLE_MPU 0\r
+#endif\r
+\r
+/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is\r
+currently used in ARMv8M ports. */\r
+#ifndef configENABLE_FPU\r
+ #define configENABLE_FPU 1\r
+#endif\r
+\r
+/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.\r
+This is currently used in ARMv8M ports. */\r
+#ifndef configENABLE_TRUSTZONE\r
+ #define configENABLE_TRUSTZONE 1\r
+#endif\r
+\r
/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using\r
* dynamically allocated RAM, in which case when any task is deleted it is known\r
* that both the task's stack and TCB need to be freed. Sometimes the\r
#define MPU_PROTOTYPES_H\r
\r
/* MPU versions of tasks.h API functions. */\r
-BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask );\r
-TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer );\r
-BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );\r
-BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );\r
-void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );\r
-void MPU_vTaskDelete( TaskHandle_t xTaskToDelete );\r
-void MPU_vTaskDelay( const TickType_t xTicksToDelay );\r
-void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement );\r
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask );\r
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask );\r
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask );\r
-void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );\r
-void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );\r
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend );\r
-void MPU_vTaskResume( TaskHandle_t xTaskToResume );\r
-void MPU_vTaskStartScheduler( void );\r
-void MPU_vTaskSuspendAll( void );\r
-BaseType_t MPU_xTaskResumeAll( void );\r
-TickType_t MPU_xTaskGetTickCount( void );\r
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void );\r
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery );\r
-TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery );\r
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask );\r
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );\r
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );\r
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask );\r
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue );\r
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex );\r
-BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );\r
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void );\r
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime );\r
-TickType_t MPU_xTaskGetIdleRunTimeCounter( void );\r
-void MPU_vTaskList( char * pcWriteBuffer );\r
-void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer );\r
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue );\r
-BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );\r
-uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );\r
-BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask );\r
-BaseType_t MPU_xTaskIncrementTick( void );\r
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void );\r
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );\r
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );\r
-void MPU_vTaskMissedYield( void );\r
-BaseType_t MPU_xTaskGetSchedulerState( void );\r
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;\r
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\r
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\r
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;\r
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;\r
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;\r
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;\r
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;\r
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\r
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;\r
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;\r
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;\r
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;\r
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;\r
+TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;\r
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;\r
\r
/* MPU versions of queue.h API functions. */\r
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition );\r
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );\r
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );\r
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait );\r
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue );\r
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue );\r
-void MPU_vQueueDelete( QueueHandle_t xQueue );\r
-QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType );\r
-QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue );\r
-QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount );\r
-QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue );\r
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore );\r
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait );\r
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex );\r
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName );\r
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue );\r
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue );\r
-QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType );\r
-QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType );\r
-QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength );\r
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );\r
-BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );\r
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait );\r
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue );\r
-void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber );\r
-UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue );\r
-uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue );\r
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\r
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\r
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;\r
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;\r
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;\r
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;\r
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\r
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\r
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;\r
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;\r
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;\r
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;\r
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\r
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\r
\r
/* MPU versions of timers.h API functions. */\r
-TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction );\r
-TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer );\r
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer );\r
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );\r
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer );\r
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void );\r
-BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );\r
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer );\r
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );\r
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer );\r
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer );\r
-BaseType_t MPU_xTimerCreateTimerTask( void );\r
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait );\r
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;\r
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;\r
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\r
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;\r
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\r
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
\r
/* MPU versions of event_group.h API functions. */\r
-EventGroupHandle_t MPU_xEventGroupCreate( void );\r
-EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer );\r
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait );\r
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );\r
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );\r
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait );\r
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup );\r
-UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup );\r
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;\r
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;\r
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;\r
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;\r
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;\r
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;\r
\r
/* MPU versions of message/stream_buffer.h API functions. */\r
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait );\r
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait );\r
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer );\r
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );\r
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );\r
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );\r
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );\r
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );\r
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );\r
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );\r
-StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer );\r
-StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer );\r
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\r
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\r
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\r
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\r
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\r
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;\r
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;\r
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;\r
\r
\r
\r
(useful when using statically allocated objects). */\r
#define PRIVILEGED_FUNCTION\r
#define PRIVILEGED_DATA __attribute__((section("privileged_data")))\r
+ #define FREERTOS_SYSTEM_CALL\r
\r
#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\r
\r
/* Ensure API functions go in the privileged execution section. */\r
#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))\r
#define PRIVILEGED_DATA __attribute__((section("privileged_data")))\r
+ #define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))\r
\r
#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\r
\r
\r
#define PRIVILEGED_FUNCTION\r
#define PRIVILEGED_DATA\r
+ #define FREERTOS_SYSTEM_CALL\r
#define portUSING_MPU_WRAPPERS 0\r
\r
#endif /* portUSING_MPU_WRAPPERS */\r
*\r
*/\r
#if( portUSING_MPU_WRAPPERS == 1 )\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;\r
+ #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;\r
+ #else\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;\r
+ #endif\r
#else\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;\r
+ #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;\r
+ #else\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;\r
+ #endif\r
#endif\r
\r
/* Used by heap_5.c. */\r
#define tskKERNEL_VERSION_MINOR 2\r
#define tskKERNEL_VERSION_BUILD 0\r
\r
+/* MPU region parameters passed in ulParameters\r
+ * of MemoryRegion_t struct. */\r
+#define tskMPU_REGION_READ_ONLY ( 1UL << 0UL )\r
+#define tskMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define tskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL )\r
+#define tskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL )\r
+#define tskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL )\r
+\r
/**\r
* task. h\r
*\r
--- /dev/null
+#/*\r
+# * FreeRTOS Kernel V10.2.0\r
+# * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+# *\r
+# * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+# * this software and associated documentation files (the "Software"), to deal in\r
+# * the Software without restriction, including without limitation the rights to\r
+# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+# * the Software, and to permit persons to whom the Software is furnished to do so,\r
+# * subject to the following conditions:\r
+# *\r
+# * The above copyright notice and this permission notice shall be included in all\r
+# * copies or substantial portions of the Software.\r
+# *\r
+# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+# *\r
+# * http://www.FreeRTOS.org\r
+# * http://aws.amazon.com/freertos\r
+# *\r
+# * 1 tab == 4 spaces!\r
+# */\r
+\r
+import os\r
+import shutil\r
+\r
+_THIS_FILE_DIRECTORY_ = os.path.dirname(os.path.realpath(__file__))\r
+_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_)\r
+\r
+_COMPILERS_ = ['GCC', 'IAR']\r
+_ARCH_NS_ = ['ARM_CM33', 'ARM_CM33_NTZ']\r
+_ARCH_S_ = ['ARM_CM33']\r
+\r
+# Files to be complied in the Secure Project\r
+_SECURE_FILE_PATHS_ = [\r
+ os.path.join('secure', 'context'),\r
+ os.path.join('secure', 'context', 'portable', '_COMPILER_ARCH_'),\r
+ os.path.join('secure', 'heap'),\r
+ os.path.join('secure', 'init'),\r
+ os.path.join('secure', 'macros')\r
+]\r
+\r
+# Files to be complied in the Non-Secure Project\r
+_NONSECURE_FILE_PATHS_ = [\r
+ 'non_secure',\r
+ os.path.join('non_secure', 'portable', '_COMPILER_ARCH_')\r
+]\r
+\r
+def copy_files_in_dir(src_abs_path, dst_abs_path):\r
+ for src_file in os.listdir(src_abs_path):\r
+ src_file_abs_path = os.path.join(src_abs_path, src_file)\r
+ if os.path.isfile(src_file_abs_path):\r
+ if not os.path.exists(dst_abs_path):\r
+ os.makedirs(dst_abs_path)\r
+ print('Copying {}...'.format(os.path.basename(src_file_abs_path)))\r
+ shutil.copy2(src_file_abs_path, dst_abs_path)\r
+\r
+\r
+def copy_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path):\r
+ _COMPILER_ARCH_ = os.path.join(compiler, arch)\r
+ for src_path in src_paths:\r
+ src_path_sanitized = src_path.replace('_COMPILER_ARCH_', _COMPILER_ARCH_ )\r
+\r
+ src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path_sanitized)\r
+ dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, _COMPILER_ARCH_, dst_path)\r
+\r
+ copy_files_in_dir(src_abs_path, dst_abs_path)\r
+\r
+\r
+def copy_files():\r
+ # Copy Secure Files\r
+ for compiler in _COMPILERS_:\r
+ for arch in _ARCH_S_:\r
+ copy_files_for_compiler_and_arch(compiler, arch, _SECURE_FILE_PATHS_, 'secure')\r
+\r
+ # Copy Non-Secure Files\r
+ for compiler in _COMPILERS_:\r
+ for arch in _ARCH_NS_:\r
+ copy_files_for_compiler_and_arch(compiler, arch, _NONSECURE_FILE_PATHS_, 'non_secure')\r
+\r
+\r
+def main():\r
+ copy_files()\r
+\r
+\r
+if __name__ == '__main__':\r
+ main()\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+ * all the API functions to use the MPU wrappers. That should only be done when\r
+ * task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the NVIC.\r
+ */\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the MPU.\r
+ */\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+\r
+/* Enable privileged access to unmapped region. */\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+\r
+/* Enable MPU. */\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
+\r
+/* Expected value of the portMPU_TYPE register. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to set up the initial stack.\r
+ */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+/**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+#define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+\r
+/**\r
+ * @brief CONTROL register privileged bit mask.\r
+ *\r
+ * Bit[0] in CONTROL register tells the privilege:\r
+ * Bit[0] = 0 ==> The task is privileged.\r
+ * Bit[0] = 1 ==> The task is not privileged.\r
+ */\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+\r
+/**\r
+ * @brief Initial CONTROL register values.\r
+ */\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+\r
+/**\r
+ * @brief Let the user override the pre-loading of the initial LR with the\r
+ * address of prvTaskExitError() in case it messes up unwinding of the stack\r
+ * in the debugger.\r
+ */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/**\r
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
+ * when a task is created. This helps in debugging at the cost of code size.\r
+ */\r
+#define portPRELOAD_REGISTERS 1\r
+\r
+/**\r
+ * @brief A task is created without a secure context, and must call\r
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
+ * any secure calls.\r
+ */\r
+#define portNO_SECURE_CONTEXT 0\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Used to catch tasks that attempt to return from their implementing\r
+ * function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_MPU */\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_FPU */\r
+\r
+/**\r
+ * @brief Yield the processor.\r
+ */\r
+void vPortYield( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enter critical section.\r
+ */\r
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Exit from critical section.\r
+ */\r
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SysTick handler.\r
+ */\r
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief C part of SVC handler.\r
+ */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Each task maintains its own interrupt status in the critical nesting\r
+ * variable.\r
+ */\r
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+volatile uint32_t ulDummy = 0UL;\r
+\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash and system calls flash as Read Only by\r
+ * both privileged and unprivileged tasks. All tasks can read it but\r
+ * no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* By default allow everything to access the general peripherals.\r
+ * The system peripherals and registers are protected. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX1 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
+#endif /* configENABLE_FPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
+\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+uint32_t ulPreviousMask;\r
+\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+{\r
+#if( configENABLE_MPU == 1 )\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+#endif /* configENABLE_MPU */\r
+\r
+uint32_t ulPC;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
+#endif /* configENABLE_TRUSTZONE */\r
+uint8_t ucSVCNumber;\r
+\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+#else\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+#endif /* configENABLE_MPU */\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ " ldr r5, xSecureContextConst2 \n"\r
+ " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r3 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r4 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ " ldr r4, xSecureContextConst2 \n"\r
+ " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ "xSecureContextConst2: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ " ite ne \n"\r
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " bic r0, #1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " orr r0, #1 \n" /* r0 = r0 | 1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " .extern SecureContext_SaveContext \n"\r
+ " .extern SecureContext_LoadContext \n"\r
+ " \n"\r
+ " mrs r1, psp \n" /* Read PSP in r1. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+ " \n"\r
+ " cbz r0, save_ns_context \n" /* No secure context to save. */\r
+ " push {r0-r2, r14} \n"\r
+ " bl SecureContext_SaveContext \n"\r
+ " pop {r0-r3} \n" /* LR is now in r3. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " b select_next_task \n"\r
+ " \n"\r
+ " save_ns_context: \n"\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vstmdbeq r1!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " adds r1, r1, #16 \n" /* r1 = r1 + 16. */\r
+ " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " subs r1, r1, #16 \n" /* r1 = r1 - 16. */\r
+ " stm r1, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " adds r1, r1, #12 \n" /* r1 = r1 + 12. */\r
+ " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " subs r1, r1, #12 \n" /* r1 = r1 - 12. */\r
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " select_next_task: \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r3 \n" /* Restore the CONTROL register value for the task. */\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r4} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r4} \n"\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #else /* configENABLE_MPU */\r
+ " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r3} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r3} \n"\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " restore_ns_context: \n"\r
+ " ldmia r1!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vldmiaeq r1!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "xSecureContextConst: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, svchandler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " svc %0 \n" /* Secure context is allocated in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */\r
+ " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */\r
+ " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */\r
+ " it ne \n"\r
+ " svcne %0 \n" /* Secure context is freed in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r3, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r3, #4 \n" /* r3 = 4. */\r
+ " str r3, [r2] \n" /* Program RNR = 4. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r1!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r2 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r2 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ " ite ne \n"\r
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " bic r0, #1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " orr r0, #1 \n" /* r0 = r0 | 1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r0, psp \n" /* Read PSP in r0. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vstmdbeq r0!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " mrs r1, psplim \n" /* r1 = PSPLIM. */\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmdb r0!, {r1-r11} \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
+ #else /* configENABLE_MPU */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
+ " \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r3, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r3, #4 \n" /* r3 = 4. */\r
+ " str r3, [r2] \n" /* Program RNR = 4. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r1!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r0!, {r1-r11} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
+ #else /* configENABLE_MPU */\r
+ " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vldmiaeq r0!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r2 \n" /* Restore the CONTROL register value for the task. */\r
+ #else /* configENABLE_MPU */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ #endif /* configENABLE_MPU */\r
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
+ " bx r3 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, svchandler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ EXTERN pxCurrentTCB\r
+ EXTERN xSecureContext\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+ EXTERN SecureContext_SaveContext\r
+ EXTERN SecureContext_LoadContext\r
+\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vPortAllocateSecureContext\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
+ PUBLIC vPortFreeSecureContext\r
+/*-----------------------------------------------------------*/\r
+\r
+/*---------------- Unprivileged Functions -------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+xIsPrivileged:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vResetPrivilege:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orr r0, r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vPortAllocateSecureContext:\r
+ svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/*----------------- Privileged Functions --------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+vRestoreContextOfFirstTask:\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ ldr r5, =xSecureContext\r
+ str r1, [r5] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ msr control, r3 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r4 /* Finally, branch to EXC_RETURN. */\r
+#else /* configENABLE_MPU */\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ ldr r4, =xSecureContext\r
+ str r1, [r4] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+vRaisePrivilege:\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ bic r0, r0, #1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vStartFirstTask:\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+/*-----------------------------------------------------------*/\r
+\r
+ulSetInterruptMaskFromISR:\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+vClearInterruptMaskFromISR:\r
+ msr PRIMASK, r0\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+PendSV_Handler:\r
+ mrs r1, psp /* Read PSP in r1. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+\r
+ cbz r0, save_ns_context /* No secure context to save. */\r
+ push {r0-r2, r14}\r
+ bl SecureContext_SaveContext\r
+ pop {r0-r3} /* LR is now in r3. */\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
+#if ( configENABLE_MPU == 1 )\r
+ subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+#else /* configENABLE_MPU */\r
+ subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+#endif /* configENABLE_MPU */\r
+ b select_next_task\r
+\r
+ save_ns_context:\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
+ #if ( configENABLE_FPU == 1 )\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if ( configENABLE_MPU == 1 )\r
+ subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ adds r1, r1, #16 /* r1 = r1 + 16. */\r
+ stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ subs r1, r1, #16 /* r1 = r1 - 16. */\r
+ stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ adds r1, r1, #12 /* r1 = r1 + 12. */\r
+ stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ subs r1, r1, #12 /* r1 = r1 - 12. */\r
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+\r
+ select_next_task:\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
+\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+\r
+ #if ( configENABLE_MPU == 1 )\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+\r
+ #if ( configENABLE_MPU == 1 )\r
+ ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r3 /* Restore the CONTROL register value for the task. */\r
+ mov lr, r4 /* LR = r4. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r4}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r4}\r
+ mov lr, r4 /* LR = r4. */\r
+ lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #else /* configENABLE_MPU */\r
+ ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ mov lr, r3 /* LR = r3. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r3}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r3}\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #endif /* configENABLE_MPU */\r
+\r
+ restore_ns_context:\r
+ ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */\r
+ #if ( configENABLE_FPU == 1 )\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+SVC_Handler:\r
+ tst lr, #4\r
+ ite eq\r
+ mrseq r0, msp\r
+ mrsne r0, psp\r
+ b vPortSVCHandler_C\r
+/*-----------------------------------------------------------*/\r
+\r
+vPortFreeSecureContext:\r
+ /* r0 = uint32_t *pulTCB. */\r
+ ldr r1, [r0] /* The first item in the TCB is the top of the stack. */\r
+ ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */\r
+ cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */\r
+ it ne\r
+ svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ EXTERN pxCurrentTCB\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
+/*-----------------------------------------------------------*/\r
+\r
+/*---------------- Unprivileged Functions -------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+xIsPrivileged:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vResetPrivilege:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orr r0, r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/*----------------- Privileged Functions --------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+vRestoreContextOfFirstTask:\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r3, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r3, #4 /* r3 = 4. */\r
+ str r3, [r2] /* Program RNR = 4. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ msr control, r2 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
+#else /* configENABLE_MPU */\r
+ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r2 /* Finally, branch to EXC_RETURN. */\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+vRaisePrivilege:\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ bic r0, r0, #1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vStartFirstTask:\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+/*-----------------------------------------------------------*/\r
+\r
+ulSetInterruptMaskFromISR:\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+vClearInterruptMaskFromISR:\r
+ msr PRIMASK, r0\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+PendSV_Handler:\r
+ mrs r0, psp /* Read PSP in r0. */\r
+#if ( configENABLE_FPU == 1 )\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vstmdbeq r0!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
+#endif /* configENABLE_FPU */\r
+#if ( configENABLE_MPU == 1 )\r
+ mrs r1, psplim /* r1 = PSPLIM. */\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
+#else /* configENABLE_MPU */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */\r
+#endif /* configENABLE_MPU */\r
+\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ str r0, [r1] /* Save the new top of stack in TCB. */\r
+\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
+\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r3, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r3, #4 /* r3 = 4. */\r
+ str r3, [r2] /* Program RNR = 4. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
+#else /* configENABLE_MPU */\r
+ ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_FPU == 1 )\r
+ tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vldmiaeq r0!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
+#endif /* configENABLE_FPU */\r
+\r
+ #if ( configENABLE_MPU == 1 )\r
+ msr psplim, r1 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r2 /* Restore the CONTROL register value for the task. */\r
+#else /* configENABLE_MPU */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+#endif /* configENABLE_MPU */\r
+ msr psp, r0 /* Remember the new top of stack for the task. */\r
+ bx r3\r
+/*-----------------------------------------------------------*/\r
+\r
+SVC_Handler:\r
+ tst lr, #4\r
+ ite eq\r
+ mrseq r0, msp\r
+ mrsne r0, psp\r
+ b vPortSVCHandler_C\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __PORT_ASM_H__\r
+#define __PORT_ASM_H__\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/**\r
+ * @brief Restore the context of the first task so that the first task starts\r
+ * executing.\r
+ */\r
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * @note This is a privileged function and should only be called from the kenrel\r
+ * code.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Starts the first task.\r
+ */\r
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Disables interrupts.\r
+ */\r
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enables interrupts.\r
+ */\r
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief PendSV Exception handler.\r
+ */\r
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SVC Handler.\r
+ */\r
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Allocate a Secure context for the calling task.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the\r
+ * secure side for the calling task.\r
+ */\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Free the task's secure context.\r
+ *\r
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\r
+ */\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+#endif /* __PORT_ASM_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portPRIVILEGED_RAM_REGION ( 2UL )\r
+#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Devices Region. */\r
+#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
+#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ /* xSecureContextHandle value is in r0. */\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r1, ipsr \n" /* r1 = IPSR. */\r
+ " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+ " ldmia r0!, {r1, r2} \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+ " msr control, r3 \n" /* CONTROL = r3. */\r
+ #endif /* configENABLE_MPU */\r
+ " msr psplim, r2 \n" /* PSPLIM = r2. */\r
+ " msr psp, r1 \n" /* PSP = r1. */\r
+ " \n"\r
+ " load_ctx_therad_mode: \n"\r
+ " nop \n"\r
+ " \n"\r
+ :::"r0", "r1", "r2"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ /* xSecureContextHandle value is in r0. */\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r1, ipsr \n" /* r1 = IPSR. */\r
+ " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+ " mrs r1, psp \n" /* r1 = PSP. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " vstmdb r1!, {s0} \n" /* Trigger the defferred stacking of FPU registers. */\r
+ " vldmia r1!, {s0} \n" /* Nullify the effect of the pervious statement. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */\r
+ " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */\r
+ " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+ " \n"\r
+ " save_ctx_therad_mode: \n"\r
+ " nop \n"\r
+ " \n"\r
+ :: "i" ( securecontextNO_STACK ) : "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/* Functions implemented in assembler file. */\r
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );\r
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ SecureContext_LoadContextAsm( xSecureContextHandle );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ SecureContext_SaveContextAsm( xSecureContextHandle );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+\r
+ PUBLIC SecureContext_LoadContextAsm\r
+ PUBLIC SecureContext_SaveContextAsm\r
+/*-----------------------------------------------------------*/\r
+\r
+SecureContext_LoadContextAsm:\r
+ /* xSecureContextHandle value is in r0. */\r
+ mrs r1, ipsr /* r1 = IPSR. */\r
+ cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
+ ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+#if ( configENABLE_MPU == 1 )\r
+ ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+ msr control, r3 /* CONTROL = r3. */\r
+#endif /* configENABLE_MPU */\r
+ msr psplim, r2 /* PSPLIM = r2. */\r
+ msr psp, r1 /* PSP = r1. */\r
+\r
+ load_ctx_therad_mode:\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+SecureContext_SaveContextAsm:\r
+ /* xSecureContextHandle value is in r0. */\r
+ mrs r1, ipsr /* r1 = IPSR. */\r
+ cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
+ mrs r1, psp /* r1 = PSP. */\r
+#if ( configENABLE_FPU == 1 )\r
+ vstmdb r1!, {s0} /* Trigger the defferred stacking of FPU registers. */\r
+ vldmia r1!, {s0} /* Nullify the effect of the pervious statement. */\r
+#endif /* configENABLE_FPU */\r
+#if ( configENABLE_MPU == 1 )\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ stmdb r1!, {r2} /* Store CONTROL value on the stack. */\r
+#endif /* configENABLE_MPU */\r
+ str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ movs r1, #0 /* r1 = securecontextNO_STACK. */\r
+ msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */\r
+ msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+\r
+ save_ctx_therad_mode:\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure heap includes. */\r
+#include "secure_heap.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief CONTROL value for privileged tasks.\r
+ *\r
+ * Bit[0] - 0 --> Thread mode is privileged.\r
+ * Bit[1] - 1 --> Thread mode uses PSP.\r
+ */\r
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02\r
+\r
+/**\r
+ * @brief CONTROL value for un-privileged tasks.\r
+ *\r
+ * Bit[0] - 1 --> Thread mode is un-privileged.\r
+ * Bit[1] - 1 --> Thread mode uses PSP.\r
+ */\r
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Structure to represent secure context.\r
+ *\r
+ * @note Since stack grows down, pucStackStart is the highest address while\r
+ * pucStackLimit is the first addess of the allocated memory.\r
+ */\r
+typedef struct SecureContext\r
+{\r
+ uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\r
+ uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */\r
+ uint8_t *pucStackStart; /**< First location of the stack memory. */\r
+} SecureContext_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* No stack for thread mode until a task's context is loaded. */\r
+ secureportSET_PSPLIM( securecontextNO_STACK );\r
+ secureportSET_PSP( securecontextNO_STACK );\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Configure thread mode to use PSP and to be unprivileged. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Configure thread mode to use PSP and to be privileged.. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )\r
+#else /* configENABLE_MPU */\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )\r
+#endif /* configENABLE_MPU */\r
+{\r
+ uint8_t *pucStackMemory = NULL;\r
+ uint32_t ulIPSR;\r
+ SecureContextHandle_t xSecureContextHandle = NULL;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t *pulCurrentStackPointer = NULL;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Allocate the context structure. */\r
+ xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );\r
+\r
+ if( xSecureContextHandle != NULL )\r
+ {\r
+ /* Allocate the stack space. */\r
+ pucStackMemory = pvPortMalloc( ulSecureStackSize );\r
+\r
+ if( pucStackMemory != NULL )\r
+ {\r
+ /* Since stack grows down, the starting point will be the last\r
+ * location. Note that this location is next to the last\r
+ * allocated byte because the hardware decrements the stack\r
+ * pointer before writing i.e. if stack pointer is 0x2, a push\r
+ * operation will decrement the stack pointer to 0x1 and then\r
+ * write at 0x1. */\r
+ xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;\r
+\r
+ /* The stack cannot go beyond this location. This value is\r
+ * programmed in the PSPLIM register on context switch.*/\r
+ xSecureContextHandle->pucStackLimit = pucStackMemory;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Store the correct CONTROL value for the task on the stack.\r
+ * This value is programmed in the CONTROL register on\r
+ * context switch. */\r
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;\r
+ pulCurrentStackPointer--;\r
+ if( ulIsTaskPrivileged )\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\r
+ }\r
+ else\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\r
+ }\r
+\r
+ /* Store the current stack pointer. This value is programmed in\r
+ * the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Current SP is set to the starting of the stack. This\r
+ * value programmed in the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;\r
+\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+ else\r
+ {\r
+ /* Free the context to avoid memory leak and make sure to return\r
+ * NULL to indicate failure. */\r
+ vPortFree( xSecureContextHandle );\r
+ xSecureContextHandle = NULL;\r
+ }\r
+ }\r
+ }\r
+\r
+ return xSecureContextHandle;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Ensure that valid parameters are passed. */\r
+ secureportASSERT( xSecureContextHandle != NULL );\r
+\r
+ /* Free the stack space. */\r
+ vPortFree( xSecureContextHandle->pucStackLimit );\r
+\r
+ /* Free the context itself. */\r
+ vPortFree( xSecureContextHandle );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_CONTEXT_H__\r
+#define __SECURE_CONTEXT_H__\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOSConfig.h"\r
+\r
+/**\r
+ * @brief PSP value when no task's context is loaded.\r
+ */\r
+#define securecontextNO_STACK 0x0\r
+\r
+/**\r
+ * @brief Opaque handle.\r
+ */\r
+struct SecureContext;\r
+typedef struct SecureContext* SecureContextHandle_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Initializes the secure context management system.\r
+ *\r
+ * PSP is set to NULL and therefore a task must allocate and load a context\r
+ * before calling any secure side function in the thread mode.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureContext_Init( void );\r
+\r
+/**\r
+ * @brief Allocates a context on the secure side.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\r
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\r
+ *\r
+ * @return Opaque context handle if context is successfully allocated, NULL\r
+ * otherwise.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );\r
+#else /* configENABLE_MPU */\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );\r
+#endif /* configENABLE_MPU */\r
+\r
+/**\r
+ * @brief Frees the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the\r
+ * context to be freed.\r
+ */\r
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+/**\r
+ * @brief Loads the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the context\r
+ * to be loaded.\r
+ */\r
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+/**\r
+ * @brief Saves the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the context\r
+ * to be saved.\r
+ */\r
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+#endif /* __SECURE_CONTEXT_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Secure context heap includes. */\r
+#include "secure_heap.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief Total heap size.\r
+ */\r
+#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )\r
+\r
+/* No test marker by default. */\r
+#ifndef mtCOVERAGE_TEST_MARKER\r
+ #define mtCOVERAGE_TEST_MARKER()\r
+#endif\r
+\r
+/* No tracing by default. */\r
+#ifndef traceMALLOC\r
+ #define traceMALLOC( pvReturn, xWantedSize )\r
+#endif\r
+\r
+/* No tracing by default. */\r
+#ifndef traceFREE\r
+ #define traceFREE( pv, xBlockSize )\r
+#endif\r
+\r
+/* Block sizes must not get too small. */\r
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )\r
+\r
+/* Assumes 8bit bytes! */\r
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Allocate the memory for the heap. */\r
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )\r
+ /* The application writer has already defined the array used for the RTOS\r
+ * heap - probably so it can be placed in a special segment or address. */\r
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+#else /* configAPPLICATION_ALLOCATED_HEAP */\r
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+#endif /* configAPPLICATION_ALLOCATED_HEAP */\r
+\r
+/**\r
+ * @brief The linked list structure.\r
+ *\r
+ * This is used to link free blocks in order of their memory address.\r
+ */\r
+typedef struct A_BLOCK_LINK\r
+{\r
+ struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */\r
+ size_t xBlockSize; /**< The size of the free block. */\r
+} BlockLink_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Called automatically to setup the required heap structures the first\r
+ * time pvPortMalloc() is called.\r
+ */\r
+static void prvHeapInit( void );\r
+\r
+/**\r
+ * @brief Inserts a block of memory that is being freed into the correct\r
+ * position in the list of free memory blocks.\r
+ *\r
+ * The block being freed will be merged with the block in front it and/or the\r
+ * block behind it if the memory blocks are adjacent to each other.\r
+ *\r
+ * @param[in] pxBlockToInsert The block being freed.\r
+ */\r
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief The size of the structure placed at the beginning of each allocated\r
+ * memory block must by correctly byte aligned.\r
+ */\r
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+\r
+/**\r
+ * @brief Create a couple of list links to mark the start and end of the list.\r
+ */\r
+static BlockLink_t xStart, *pxEnd = NULL;\r
+\r
+/**\r
+ * @brief Keeps track of the number of free bytes remaining, but says nothing\r
+ * about fragmentation.\r
+ */\r
+static size_t xFreeBytesRemaining = 0U;\r
+static size_t xMinimumEverFreeBytesRemaining = 0U;\r
+\r
+/**\r
+ * @brief Gets set to the top bit of an size_t type.\r
+ *\r
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set\r
+ * then the block belongs to the application. When the bit is free the block is\r
+ * still part of the free heap space.\r
+ */\r
+static size_t xBlockAllocatedBit = 0;\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHeapInit( void )\r
+{\r
+BlockLink_t *pxFirstFreeBlock;\r
+uint8_t *pucAlignedHeap;\r
+size_t uxAddress;\r
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\r
+\r
+ /* Ensure the heap starts on a correctly aligned boundary. */\r
+ uxAddress = ( size_t ) ucHeap;\r
+\r
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\r
+ {\r
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\r
+ }\r
+\r
+ pucAlignedHeap = ( uint8_t * ) uxAddress;\r
+\r
+ /* xStart is used to hold a pointer to the first item in the list of free\r
+ * blocks. The void cast is used to prevent compiler warnings. */\r
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
+ xStart.xBlockSize = ( size_t ) 0;\r
+\r
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted\r
+ * at the end of the heap space. */\r
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\r
+ uxAddress -= xHeapStructSize;\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ pxEnd = ( void * ) uxAddress;\r
+ pxEnd->xBlockSize = 0;\r
+ pxEnd->pxNextFreeBlock = NULL;\r
+\r
+ /* To start with there is a single free block that is sized to take up the\r
+ * entire heap space, minus the space taken by pxEnd. */\r
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\r
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\r
+\r
+ /* Only one block exists - and it covers the entire usable heap space. */\r
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+\r
+ /* Work out the position of the top bit in a size_t variable. */\r
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )\r
+{\r
+BlockLink_t *pxIterator;\r
+uint8_t *puc;\r
+\r
+ /* Iterate through the list until a block is found that has a higher address\r
+ * than the block being inserted. */\r
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\r
+ {\r
+ /* Nothing to do here, just iterate to the right position. */\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted after\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxIterator;\r
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\r
+ {\r
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\r
+ pxBlockToInsert = pxIterator;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted before\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxBlockToInsert;\r
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\r
+ {\r
+ if( pxIterator->pxNextFreeBlock != pxEnd )\r
+ {\r
+ /* Form one big block from the two blocks. */\r
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the block being inserted plugged a gab, so was merged with the block\r
+ * before and the block after, then it's pxNextFreeBlock pointer will have\r
+ * already been set, and should not be set here as that would make it point\r
+ * to itself. */\r
+ if( pxIterator != pxBlockToInsert )\r
+ {\r
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvPortMalloc( size_t xWantedSize )\r
+{\r
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
+void *pvReturn = NULL;\r
+\r
+ /* If this is the first call to malloc then the heap will require\r
+ * initialisation to setup the list of free blocks. */\r
+ if( pxEnd == NULL )\r
+ {\r
+ prvHeapInit();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Check the requested block size is not so large that the top bit is set.\r
+ * The top bit of the block size member of the BlockLink_t structure is used\r
+ * to determine who owns the block - the application or the kernel, so it\r
+ * must be free. */\r
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\r
+ {\r
+ /* The wanted size is increased so it can contain a BlockLink_t\r
+ * structure in addition to the requested amount of bytes. */\r
+ if( xWantedSize > 0 )\r
+ {\r
+ xWantedSize += xHeapStructSize;\r
+\r
+ /* Ensure that blocks are always aligned to the required number of\r
+ * bytes. */\r
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\r
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\r
+ {\r
+ /* Traverse the list from the start (lowest address) block until\r
+ * one of adequate size is found. */\r
+ pxPreviousBlock = &xStart;\r
+ pxBlock = xStart.pxNextFreeBlock;\r
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
+ {\r
+ pxPreviousBlock = pxBlock;\r
+ pxBlock = pxBlock->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the end marker was reached then a block of adequate size was\r
+ * not found. */\r
+ if( pxBlock != pxEnd )\r
+ {\r
+ /* Return the memory space pointed to - jumping over the\r
+ * BlockLink_t structure at its start. */\r
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\r
+\r
+ /* This block is being returned for use so must be taken out\r
+ * of the list of free blocks. */\r
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
+\r
+ /* If the block is larger than required it can be split into\r
+ * two. */\r
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\r
+ {\r
+ /* This block is to be split into two. Create a new\r
+ * block following the number of bytes requested. The void\r
+ * cast is used to prevent byte alignment warnings from the\r
+ * compiler. */\r
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+\r
+ /* Calculate the sizes of two blocks split from the single\r
+ * block. */\r
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
+ pxBlock->xBlockSize = xWantedSize;\r
+\r
+ /* Insert the new block into the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( pxNewBlockLink );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ xFreeBytesRemaining -= pxBlock->xBlockSize;\r
+\r
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\r
+ {\r
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* The block is being returned - it is allocated and owned by\r
+ * the application and has no "next" block. */\r
+ pxBlock->xBlockSize |= xBlockAllocatedBit;\r
+ pxBlock->pxNextFreeBlock = NULL;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ traceMALLOC( pvReturn, xWantedSize );\r
+\r
+ #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\r
+ {\r
+ if( pvReturn == NULL )\r
+ {\r
+ extern void vApplicationMallocFailedHook( void );\r
+ vApplicationMallocFailedHook();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ return pvReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFree( void *pv )\r
+{\r
+uint8_t *puc = ( uint8_t * ) pv;\r
+BlockLink_t *pxLink;\r
+\r
+ if( pv != NULL )\r
+ {\r
+ /* The memory being freed will have an BlockLink_t structure immediately\r
+ * before it. */\r
+ puc -= xHeapStructSize;\r
+\r
+ /* This casting is to keep the compiler from issuing warnings. */\r
+ pxLink = ( void * ) puc;\r
+\r
+ /* Check the block is actually allocated. */\r
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\r
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );\r
+\r
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\r
+ {\r
+ if( pxLink->pxNextFreeBlock == NULL )\r
+ {\r
+ /* The block is being returned to the heap - it is no longer\r
+ * allocated. */\r
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;\r
+\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS();\r
+ {\r
+ /* Add this block to the list of free blocks. */\r
+ xFreeBytesRemaining += pxLink->xBlockSize;\r
+ traceFREE( pv, pxLink->xBlockSize );\r
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
+ }\r
+ secureportENABLE_NON_SECURE_INTERRUPTS();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+size_t xPortGetFreeHeapSize( void )\r
+{\r
+ return xFreeBytesRemaining;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+size_t xPortGetMinimumEverFreeHeapSize( void )\r
+{\r
+ return xMinimumEverFreeBytesRemaining;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortInitialiseBlocks( void )\r
+{\r
+ /* This just exists to keep the linker quiet. */\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_HEAP_H__\r
+#define __SECURE_HEAP_H__\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/**\r
+ * @brief Allocates memory from heap.\r
+ *\r
+ * @param[in] xWantedSize The size of the memory to be allocated.\r
+ *\r
+ * @return Pointer to the memory region if the allocation is successful, NULL\r
+ * otherwise.\r
+ */\r
+void *pvPortMalloc( size_t xWantedSize );\r
+\r
+/**\r
+ * @brief Frees the previously allocated memory.\r
+ *\r
+ * @param[in] pv Pointer to the memory to be freed.\r
+ */\r
+void vPortFree( void *pv );\r
+\r
+#endif /* __SECURE_HEAP_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Secure init includes. */\r
+#include "secure_init.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */\r
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )\r
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )\r
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define secureinitFPCCR_LSPENS_POS ( 29UL )\r
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )\r
+#define secureinitFPCCR_TS_POS ( 26UL )\r
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )\r
+\r
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */\r
+#define secureinitNSACR_CP10_POS ( 10UL )\r
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )\r
+#define secureinitNSACR_CP11_POS ( 11UL )\r
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
+ * permitted. CP11 should be programmed to the same value as CP10. */\r
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
+\r
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
+ * that we can enable/disable lazy stacking in port.c file. */\r
+ *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
+\r
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
+ * registers (S16-S31) are also pushed to stack on exception entry and\r
+ * restored on exception return. */\r
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_INIT_H__\r
+#define __SECURE_INIT_H__\r
+\r
+/**\r
+ * @brief De-prioritizes the non-secure exceptions.\r
+ *\r
+ * This is needed to ensure that the non-secure PendSV runs at the lowest\r
+ * priority. Context switch is done in the non-secure PendSV handler.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureInit_DePrioritizeNSExceptions( void );\r
+\r
+/**\r
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\r
+ *\r
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\r
+ * Registers are not leaked to the non-secure side.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureInit_EnableNSFPUAccess( void );\r
+\r
+#endif /* __SECURE_INIT_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_PORT_MACROS_H__\r
+#define __SECURE_PORT_MACROS_H__\r
+\r
+/**\r
+ * @brief Byte alignment requirements.\r
+ */\r
+#define secureportBYTE_ALIGNMENT 8\r
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )\r
+\r
+/**\r
+ * @brief Macro to declare a function as non-secure callable.\r
+ */\r
+#if defined( __IAR_SYSTEMS_ICC__ )\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+#else\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+#endif\r
+\r
+/**\r
+ * @brief Set the secure PRIMASK value.\r
+ */\r
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\r
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+\r
+/**\r
+ * @brief Set the non-secure PRIMASK value.\r
+ */\r
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\r
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+\r
+/**\r
+ * @brief Read the PSP value in the given variable.\r
+ */\r
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\r
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the PSP to the given value.\r
+ */\r
+#define secureportSET_PSP( pucCurrentStackPointer ) \\r
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the PSPLIM to the given value.\r
+ */\r
+#define secureportSET_PSPLIM( pucStackLimit ) \\r
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )\r
+\r
+/**\r
+ * @brief Set the NonSecure MSP to the given value.\r
+ */\r
+#define secureportSET_MSP_NS( pucMainStackPointer ) \\r
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the CONTROL register to the given value.\r
+ */\r
+#define secureportSET_CONTROL( ulControl ) \\r
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )\r
+\r
+/**\r
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given\r
+ * variable.\r
+ */\r
+#define secureportREAD_IPSR( ulIPSR ) \\r
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )\r
+\r
+/**\r
+ * @brief PRIMASK value to enable interrupts.\r
+ */\r
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0\r
+\r
+/**\r
+ * @brief PRIMASK value to disable interrupts.\r
+ */\r
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1\r
+\r
+/**\r
+ * @brief Disable secure interrupts.\r
+ */\r
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Disable non-secure interrupts.\r
+ *\r
+ * This effectively disables context switches.\r
+ */\r
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Enable non-secure interrupts.\r
+ */\r
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Assert definition.\r
+ */\r
+#define secureportASSERT( x ) \\r
+ if( ( x ) == 0 ) \\r
+ { \\r
+ secureportDISABLE_SECURE_INTERRUPTS(); \\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \\r
+ for( ;; ); \\r
+ }\r
+\r
+#endif /* __SECURE_PORT_MACROS_H__ */\r
\r
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
\r
-/*\r
- * Checks to see if being called from the context of an unprivileged task, and\r
- * if so raises the privilege level and returns false - otherwise does nothing\r
- * other than return true.\r
+/**\r
+ * @brief Calls the port specific code to raise the privilege.\r
+ *\r
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.\r
*/\r
-extern BaseType_t xPortRaisePrivilege( void );\r
+BaseType_t xPortRaisePrivilege( void ) FREERTOS_SYSTEM_CALL;\r
\r
+/**\r
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific\r
+ * code to reset the privilege, otherwise does nothing.\r
+ */\r
+void vPortResetPrivilege( BaseType_t xRunningPrivileged );\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortRaisePrivilege( void ) /* FREERTOS_SYSTEM_CALL */\r
+{\r
+BaseType_t xRunningPrivileged;\r
+\r
+ /* Check whether the processor is already privileged. */\r
+ xRunningPrivileged = portIS_PRIVILEGED();\r
+\r
+ /* If the processor is not already privileged, raise privilege. */\r
+ if( xRunningPrivileged != pdTRUE )\r
+ {\r
+ portRAISE_PRIVILEGE();\r
+ }\r
+\r
+ return xRunningPrivileged;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortResetPrivilege( BaseType_t xRunningPrivileged )\r
+{\r
+ if( xRunningPrivileged != pdTRUE )\r
+ {\r
+ portRESET_PRIVILEGE();\r
+ }\r
+}\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
- BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )\r
+ BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_STATIC_ALLOCATION == 1 )\r
- BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )\r
+ BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
- BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask )\r
+ BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_STATIC_ALLOCATION == 1 )\r
- TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer )\r
+ TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
TaskHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
#endif /* configSUPPORT_STATIC_ALLOCATION */\r
/*-----------------------------------------------------------*/\r
\r
-void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions )\r
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_vTaskDelete == 1 )\r
- void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete )\r
+ void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_vTaskDelayUntil == 1 )\r
- void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement )\r
+ void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_xTaskAbortDelay == 1 )\r
- BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask )\r
+ BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_vTaskDelay == 1 )\r
- void MPU_vTaskDelay( TickType_t xTicksToDelay )\r
+ void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_uxTaskPriorityGet == 1 )\r
- UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask )\r
+ UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */\r
{\r
UBaseType_t uxReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_vTaskPrioritySet == 1 )\r
- void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority )\r
+ void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_eTaskGetState == 1 )\r
- eTaskState MPU_eTaskGetState( TaskHandle_t pxTask )\r
+ eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
eTaskState eReturn;\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TRACE_FACILITY == 1 )\r
- void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )\r
+ void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
- TaskHandle_t MPU_xTaskGetIdleTaskHandle( void )\r
+ TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */\r
{\r
TaskHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_vTaskSuspend == 1 )\r
- void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend )\r
+ void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_vTaskSuspend == 1 )\r
- void MPU_vTaskResume( TaskHandle_t pxTaskToResume )\r
+ void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
#endif\r
/*-----------------------------------------------------------*/\r
\r
-void MPU_vTaskSuspendAll( void )\r
+void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t MPU_xTaskResumeAll( void )\r
+BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-TickType_t MPU_xTaskGetTickCount( void )\r
+TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */\r
{\r
TickType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void )\r
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */\r
{\r
UBaseType_t uxReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery )\r
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */\r
{\r
char *pcReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_xTaskGetHandle == 1 )\r
- TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery )\r
+ TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */\r
{\r
TaskHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\r
- void MPU_vTaskList( char *pcWriteBuffer )\r
+ void MPU_vTaskList( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\r
- void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer )\r
+ void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )\r
- TickType_t MPU_xTaskGetIdleRunTimeCounter( void )\r
+ TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */\r
{\r
TickType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
- void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue )\r
+ void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
- TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask )\r
+ TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\r
{\r
TaskHookFunction_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\r
- void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )\r
+ void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\r
- void *MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )\r
+ void *MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */\r
{\r
void *pvReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
- BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )\r
+ BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( configUSE_TRACE_FACILITY == 1 )\r
- UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime )\r
+ UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */\r
{\r
UBaseType_t uxReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r
- UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask )\r
+ UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\r
{\r
UBaseType_t uxReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )\r
- configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )\r
+ configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\r
{\r
configSTACK_DEPTH_TYPE uxReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )\r
- TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void )\r
+ TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */\r
{\r
TaskHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( INCLUDE_xTaskGetSchedulerState == 1 )\r
- BaseType_t MPU_xTaskGetSchedulerState( void )\r
+ BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
#endif\r
/*-----------------------------------------------------------*/\r
\r
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )\r
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )\r
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TASK_NOTIFICATIONS == 1 )\r
- BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )\r
+ BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TASK_NOTIFICATIONS == 1 )\r
- BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )\r
+ BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TASK_NOTIFICATIONS == 1 )\r
- uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )\r
+ uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\r
{\r
uint32_t ulReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TASK_NOTIFICATIONS == 1 )\r
- BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask )\r
+ BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
- QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType )\r
+ QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */\r
{\r
QueueHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_STATIC_ALLOCATION == 1 )\r
- QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )\r
+ QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */\r
{\r
QueueHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
#endif\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue )\r
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition )\r
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue )\r
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
UBaseType_t uxReturn;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue )\r
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
UBaseType_t uxReturn;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait )\r
+BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
BaseType_t xReturn;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )\r
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
BaseType_t xReturn;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )\r
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
BaseType_t xReturn;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore )\r
-{\r
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
-void * xReturn;\r
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\r
+ TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */\r
+ {\r
+ BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
+ void * xReturn;\r
\r
- xReturn = xQueueGetMutexHolder( xSemaphore );\r
- vPortResetPrivilege( xRunningPrivileged );\r
- return xReturn;\r
-}\r
+ xReturn = xQueueGetMutexHolder( xSemaphore );\r
+ vPortResetPrivilege( xRunningPrivileged );\r
+ return xReturn;\r
+ }\r
+#endif\r
/*-----------------------------------------------------------*/\r
\r
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\r
- QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType )\r
+ QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */\r
{\r
QueueHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\r
- QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )\r
+ QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */\r
{\r
QueueHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\r
- QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount )\r
+ QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */\r
{\r
QueueHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\r
\r
- QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )\r
+ QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */\r
{\r
QueueHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( configUSE_RECURSIVE_MUTEXES == 1 )\r
- BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime )\r
+ BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( configUSE_RECURSIVE_MUTEXES == 1 )\r
- BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex )\r
+ BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\r
- QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength )\r
+ QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */\r
{\r
QueueSetHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( configUSE_QUEUE_SETS == 1 )\r
- QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks )\r
+ QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */\r
{\r
QueueSetMemberHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( configUSE_QUEUE_SETS == 1 )\r
- BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r
+ BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if ( configUSE_QUEUE_SETS == 1 )\r
- BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r
+ BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if configQUEUE_REGISTRY_SIZE > 0\r
- void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName )\r
+ void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if configQUEUE_REGISTRY_SIZE > 0\r
- void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue )\r
+ void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if configQUEUE_REGISTRY_SIZE > 0\r
- const char *MPU_pcQueueGetName( QueueHandle_t xQueue )\r
+ const char *MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
const char *pcReturn;\r
#endif\r
/*-----------------------------------------------------------*/\r
\r
-void MPU_vQueueDelete( QueueHandle_t xQueue )\r
+void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
- void *MPU_pvPortMalloc( size_t xSize )\r
+ void *MPU_pvPortMalloc( size_t xSize ) /* FREERTOS_SYSTEM_CALL */\r
{\r
void *pvReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
- void MPU_vPortFree( void *pv )\r
+ void MPU_vPortFree( void *pv ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
- void MPU_vPortInitialiseBlocks( void )\r
+ void MPU_vPortInitialiseBlocks( void ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
- size_t MPU_xPortGetFreeHeapSize( void )\r
+ size_t MPU_xPortGetFreeHeapSize( void ) /* FREERTOS_SYSTEM_CALL */\r
{\r
size_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )\r
- TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction )\r
+ TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /* FREERTOS_SYSTEM_CALL */\r
{\r
TimerHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )\r
- TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer )\r
+ TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
TimerHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TIMERS == 1 )\r
- void *MPU_pvTimerGetTimerID( const TimerHandle_t xTimer )\r
+ void *MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
void * pvReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TIMERS == 1 )\r
- void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )\r
+ void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TIMERS == 1 )\r
- BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer )\r
+ BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TIMERS == 1 )\r
- TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void )\r
+ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */\r
{\r
TaskHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\r
- BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )\r
+ BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TIMERS == 1 )\r
- void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )\r
+ void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TIMERS == 1 )\r
- const char * MPU_pcTimerGetName( TimerHandle_t xTimer )\r
+ const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
const char * pcReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TIMERS == 1 )\r
- TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer )\r
+ TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
TickType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TIMERS == 1 )\r
- TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer )\r
+ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
TickType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configUSE_TIMERS == 1 )\r
- BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )\r
+ BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
- EventGroupHandle_t MPU_xEventGroupCreate( void )\r
+ EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */\r
{\r
EventGroupHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_STATIC_ALLOCATION == 1 )\r
- EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer )\r
+ EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
EventGroupHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
#endif\r
/*-----------------------------------------------------------*/\r
\r
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )\r
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\r
{\r
EventBits_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )\r
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */\r
{\r
EventBits_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )\r
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */\r
{\r
EventBits_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )\r
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\r
{\r
EventBits_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup )\r
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait )\r
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\r
{\r
size_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )\r
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
size_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait )\r
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\r
{\r
size_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )\r
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )\r
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )\r
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )\r
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )\r
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
size_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )\r
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
size_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )\r
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */\r
{\r
BaseType_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
- StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )\r
+ StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
StreamBufferHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
/*-----------------------------------------------------------*/\r
\r
#if( configSUPPORT_STATIC_ALLOCATION == 1 )\r
- StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer )\r
+ StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\r
{\r
StreamBufferHandle_t xReturn;\r
BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+ * all the API functions to use the MPU wrappers. That should only be done when\r
+ * task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the NVIC.\r
+ */\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the MPU.\r
+ */\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+\r
+/* Enable privileged access to unmapped region. */\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+\r
+/* Enable MPU. */\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
+\r
+/* Expected value of the portMPU_TYPE register. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to set up the initial stack.\r
+ */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+/**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+#define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+\r
+/**\r
+ * @brief CONTROL register privileged bit mask.\r
+ *\r
+ * Bit[0] in CONTROL register tells the privilege:\r
+ * Bit[0] = 0 ==> The task is privileged.\r
+ * Bit[0] = 1 ==> The task is not privileged.\r
+ */\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+\r
+/**\r
+ * @brief Initial CONTROL register values.\r
+ */\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+\r
+/**\r
+ * @brief Let the user override the pre-loading of the initial LR with the\r
+ * address of prvTaskExitError() in case it messes up unwinding of the stack\r
+ * in the debugger.\r
+ */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/**\r
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
+ * when a task is created. This helps in debugging at the cost of code size.\r
+ */\r
+#define portPRELOAD_REGISTERS 1\r
+\r
+/**\r
+ * @brief A task is created without a secure context, and must call\r
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
+ * any secure calls.\r
+ */\r
+#define portNO_SECURE_CONTEXT 0\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Used to catch tasks that attempt to return from their implementing\r
+ * function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_MPU */\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_FPU */\r
+\r
+/**\r
+ * @brief Yield the processor.\r
+ */\r
+void vPortYield( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enter critical section.\r
+ */\r
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Exit from critical section.\r
+ */\r
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SysTick handler.\r
+ */\r
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief C part of SVC handler.\r
+ */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Each task maintains its own interrupt status in the critical nesting\r
+ * variable.\r
+ */\r
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+volatile uint32_t ulDummy = 0UL;\r
+\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash and system calls flash as Read Only by\r
+ * both privileged and unprivileged tasks. All tasks can read it but\r
+ * no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* By default allow everything to access the general peripherals.\r
+ * The system peripherals and registers are protected. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX1 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
+#endif /* configENABLE_FPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
+\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+uint32_t ulPreviousMask;\r
+\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+{\r
+#if( configENABLE_MPU == 1 )\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+#endif /* configENABLE_MPU */\r
+\r
+uint32_t ulPC;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
+#endif /* configENABLE_TRUSTZONE */\r
+uint8_t ucSVCNumber;\r
+\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+#else\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+#endif /* configENABLE_MPU */\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ " ldr r5, xSecureContextConst2 \n"\r
+ " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r3 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r4 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ " ldr r4, xSecureContextConst2 \n"\r
+ " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ "xSecureContextConst2: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ " ite ne \n"\r
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " bic r0, #1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " orr r0, #1 \n" /* r0 = r0 | 1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " .extern SecureContext_SaveContext \n"\r
+ " .extern SecureContext_LoadContext \n"\r
+ " \n"\r
+ " mrs r1, psp \n" /* Read PSP in r1. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+ " \n"\r
+ " cbz r0, save_ns_context \n" /* No secure context to save. */\r
+ " push {r0-r2, r14} \n"\r
+ " bl SecureContext_SaveContext \n"\r
+ " pop {r0-r3} \n" /* LR is now in r3. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " b select_next_task \n"\r
+ " \n"\r
+ " save_ns_context: \n"\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vstmdbeq r1!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " adds r1, r1, #16 \n" /* r1 = r1 + 16. */\r
+ " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " subs r1, r1, #16 \n" /* r1 = r1 - 16. */\r
+ " stm r1, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " adds r1, r1, #12 \n" /* r1 = r1 + 12. */\r
+ " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " subs r1, r1, #12 \n" /* r1 = r1 - 12. */\r
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " select_next_task: \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r3 \n" /* Restore the CONTROL register value for the task. */\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r4} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r4} \n"\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #else /* configENABLE_MPU */\r
+ " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r3} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r3} \n"\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " restore_ns_context: \n"\r
+ " ldmia r1!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vldmiaeq r1!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "xSecureContextConst: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, svchandler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " svc %0 \n" /* Secure context is allocated in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */\r
+ " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */\r
+ " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */\r
+ " it ne \n"\r
+ " svcne %0 \n" /* Secure context is freed in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __PORT_ASM_H__\r
+#define __PORT_ASM_H__\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/**\r
+ * @brief Restore the context of the first task so that the first task starts\r
+ * executing.\r
+ */\r
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * @note This is a privileged function and should only be called from the kenrel\r
+ * code.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Starts the first task.\r
+ */\r
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Disables interrupts.\r
+ */\r
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enables interrupts.\r
+ */\r
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief PendSV Exception handler.\r
+ */\r
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SVC Handler.\r
+ */\r
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Allocate a Secure context for the calling task.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the\r
+ * secure side for the calling task.\r
+ */\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Free the task's secure context.\r
+ *\r
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\r
+ */\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+#endif /* __PORT_ASM_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portPRIVILEGED_RAM_REGION ( 2UL )\r
+#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Devices Region. */\r
+#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
+#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure heap includes. */\r
+#include "secure_heap.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief CONTROL value for privileged tasks.\r
+ *\r
+ * Bit[0] - 0 --> Thread mode is privileged.\r
+ * Bit[1] - 1 --> Thread mode uses PSP.\r
+ */\r
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02\r
+\r
+/**\r
+ * @brief CONTROL value for un-privileged tasks.\r
+ *\r
+ * Bit[0] - 1 --> Thread mode is un-privileged.\r
+ * Bit[1] - 1 --> Thread mode uses PSP.\r
+ */\r
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Structure to represent secure context.\r
+ *\r
+ * @note Since stack grows down, pucStackStart is the highest address while\r
+ * pucStackLimit is the first addess of the allocated memory.\r
+ */\r
+typedef struct SecureContext\r
+{\r
+ uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\r
+ uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */\r
+ uint8_t *pucStackStart; /**< First location of the stack memory. */\r
+} SecureContext_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* No stack for thread mode until a task's context is loaded. */\r
+ secureportSET_PSPLIM( securecontextNO_STACK );\r
+ secureportSET_PSP( securecontextNO_STACK );\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Configure thread mode to use PSP and to be unprivileged. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Configure thread mode to use PSP and to be privileged.. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )\r
+#else /* configENABLE_MPU */\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )\r
+#endif /* configENABLE_MPU */\r
+{\r
+ uint8_t *pucStackMemory = NULL;\r
+ uint32_t ulIPSR;\r
+ SecureContextHandle_t xSecureContextHandle = NULL;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t *pulCurrentStackPointer = NULL;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Allocate the context structure. */\r
+ xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );\r
+\r
+ if( xSecureContextHandle != NULL )\r
+ {\r
+ /* Allocate the stack space. */\r
+ pucStackMemory = pvPortMalloc( ulSecureStackSize );\r
+\r
+ if( pucStackMemory != NULL )\r
+ {\r
+ /* Since stack grows down, the starting point will be the last\r
+ * location. Note that this location is next to the last\r
+ * allocated byte because the hardware decrements the stack\r
+ * pointer before writing i.e. if stack pointer is 0x2, a push\r
+ * operation will decrement the stack pointer to 0x1 and then\r
+ * write at 0x1. */\r
+ xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;\r
+\r
+ /* The stack cannot go beyond this location. This value is\r
+ * programmed in the PSPLIM register on context switch.*/\r
+ xSecureContextHandle->pucStackLimit = pucStackMemory;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Store the correct CONTROL value for the task on the stack.\r
+ * This value is programmed in the CONTROL register on\r
+ * context switch. */\r
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;\r
+ pulCurrentStackPointer--;\r
+ if( ulIsTaskPrivileged )\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\r
+ }\r
+ else\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\r
+ }\r
+\r
+ /* Store the current stack pointer. This value is programmed in\r
+ * the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Current SP is set to the starting of the stack. This\r
+ * value programmed in the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;\r
+\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+ else\r
+ {\r
+ /* Free the context to avoid memory leak and make sure to return\r
+ * NULL to indicate failure. */\r
+ vPortFree( xSecureContextHandle );\r
+ xSecureContextHandle = NULL;\r
+ }\r
+ }\r
+ }\r
+\r
+ return xSecureContextHandle;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Ensure that valid parameters are passed. */\r
+ secureportASSERT( xSecureContextHandle != NULL );\r
+\r
+ /* Free the stack space. */\r
+ vPortFree( xSecureContextHandle->pucStackLimit );\r
+\r
+ /* Free the context itself. */\r
+ vPortFree( xSecureContextHandle );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_CONTEXT_H__\r
+#define __SECURE_CONTEXT_H__\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOSConfig.h"\r
+\r
+/**\r
+ * @brief PSP value when no task's context is loaded.\r
+ */\r
+#define securecontextNO_STACK 0x0\r
+\r
+/**\r
+ * @brief Opaque handle.\r
+ */\r
+struct SecureContext;\r
+typedef struct SecureContext* SecureContextHandle_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Initializes the secure context management system.\r
+ *\r
+ * PSP is set to NULL and therefore a task must allocate and load a context\r
+ * before calling any secure side function in the thread mode.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureContext_Init( void );\r
+\r
+/**\r
+ * @brief Allocates a context on the secure side.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\r
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\r
+ *\r
+ * @return Opaque context handle if context is successfully allocated, NULL\r
+ * otherwise.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );\r
+#else /* configENABLE_MPU */\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );\r
+#endif /* configENABLE_MPU */\r
+\r
+/**\r
+ * @brief Frees the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the\r
+ * context to be freed.\r
+ */\r
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+/**\r
+ * @brief Loads the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the context\r
+ * to be loaded.\r
+ */\r
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+/**\r
+ * @brief Saves the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the context\r
+ * to be saved.\r
+ */\r
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+#endif /* __SECURE_CONTEXT_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ /* xSecureContextHandle value is in r0. */\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r1, ipsr \n" /* r1 = IPSR. */\r
+ " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+ " ldmia r0!, {r1, r2} \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+ " msr control, r3 \n" /* CONTROL = r3. */\r
+ #endif /* configENABLE_MPU */\r
+ " msr psplim, r2 \n" /* PSPLIM = r2. */\r
+ " msr psp, r1 \n" /* PSP = r1. */\r
+ " \n"\r
+ " load_ctx_therad_mode: \n"\r
+ " nop \n"\r
+ " \n"\r
+ :::"r0", "r1", "r2"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ /* xSecureContextHandle value is in r0. */\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r1, ipsr \n" /* r1 = IPSR. */\r
+ " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+ " mrs r1, psp \n" /* r1 = PSP. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " vstmdb r1!, {s0} \n" /* Trigger the defferred stacking of FPU registers. */\r
+ " vldmia r1!, {s0} \n" /* Nullify the effect of the pervious statement. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */\r
+ " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */\r
+ " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+ " \n"\r
+ " save_ctx_therad_mode: \n"\r
+ " nop \n"\r
+ " \n"\r
+ :: "i" ( securecontextNO_STACK ) : "r1", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Secure context heap includes. */\r
+#include "secure_heap.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief Total heap size.\r
+ */\r
+#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )\r
+\r
+/* No test marker by default. */\r
+#ifndef mtCOVERAGE_TEST_MARKER\r
+ #define mtCOVERAGE_TEST_MARKER()\r
+#endif\r
+\r
+/* No tracing by default. */\r
+#ifndef traceMALLOC\r
+ #define traceMALLOC( pvReturn, xWantedSize )\r
+#endif\r
+\r
+/* No tracing by default. */\r
+#ifndef traceFREE\r
+ #define traceFREE( pv, xBlockSize )\r
+#endif\r
+\r
+/* Block sizes must not get too small. */\r
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )\r
+\r
+/* Assumes 8bit bytes! */\r
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Allocate the memory for the heap. */\r
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )\r
+ /* The application writer has already defined the array used for the RTOS\r
+ * heap - probably so it can be placed in a special segment or address. */\r
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+#else /* configAPPLICATION_ALLOCATED_HEAP */\r
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+#endif /* configAPPLICATION_ALLOCATED_HEAP */\r
+\r
+/**\r
+ * @brief The linked list structure.\r
+ *\r
+ * This is used to link free blocks in order of their memory address.\r
+ */\r
+typedef struct A_BLOCK_LINK\r
+{\r
+ struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */\r
+ size_t xBlockSize; /**< The size of the free block. */\r
+} BlockLink_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Called automatically to setup the required heap structures the first\r
+ * time pvPortMalloc() is called.\r
+ */\r
+static void prvHeapInit( void );\r
+\r
+/**\r
+ * @brief Inserts a block of memory that is being freed into the correct\r
+ * position in the list of free memory blocks.\r
+ *\r
+ * The block being freed will be merged with the block in front it and/or the\r
+ * block behind it if the memory blocks are adjacent to each other.\r
+ *\r
+ * @param[in] pxBlockToInsert The block being freed.\r
+ */\r
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief The size of the structure placed at the beginning of each allocated\r
+ * memory block must by correctly byte aligned.\r
+ */\r
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+\r
+/**\r
+ * @brief Create a couple of list links to mark the start and end of the list.\r
+ */\r
+static BlockLink_t xStart, *pxEnd = NULL;\r
+\r
+/**\r
+ * @brief Keeps track of the number of free bytes remaining, but says nothing\r
+ * about fragmentation.\r
+ */\r
+static size_t xFreeBytesRemaining = 0U;\r
+static size_t xMinimumEverFreeBytesRemaining = 0U;\r
+\r
+/**\r
+ * @brief Gets set to the top bit of an size_t type.\r
+ *\r
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set\r
+ * then the block belongs to the application. When the bit is free the block is\r
+ * still part of the free heap space.\r
+ */\r
+static size_t xBlockAllocatedBit = 0;\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHeapInit( void )\r
+{\r
+BlockLink_t *pxFirstFreeBlock;\r
+uint8_t *pucAlignedHeap;\r
+size_t uxAddress;\r
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\r
+\r
+ /* Ensure the heap starts on a correctly aligned boundary. */\r
+ uxAddress = ( size_t ) ucHeap;\r
+\r
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\r
+ {\r
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\r
+ }\r
+\r
+ pucAlignedHeap = ( uint8_t * ) uxAddress;\r
+\r
+ /* xStart is used to hold a pointer to the first item in the list of free\r
+ * blocks. The void cast is used to prevent compiler warnings. */\r
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
+ xStart.xBlockSize = ( size_t ) 0;\r
+\r
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted\r
+ * at the end of the heap space. */\r
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\r
+ uxAddress -= xHeapStructSize;\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ pxEnd = ( void * ) uxAddress;\r
+ pxEnd->xBlockSize = 0;\r
+ pxEnd->pxNextFreeBlock = NULL;\r
+\r
+ /* To start with there is a single free block that is sized to take up the\r
+ * entire heap space, minus the space taken by pxEnd. */\r
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\r
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\r
+\r
+ /* Only one block exists - and it covers the entire usable heap space. */\r
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+\r
+ /* Work out the position of the top bit in a size_t variable. */\r
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )\r
+{\r
+BlockLink_t *pxIterator;\r
+uint8_t *puc;\r
+\r
+ /* Iterate through the list until a block is found that has a higher address\r
+ * than the block being inserted. */\r
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\r
+ {\r
+ /* Nothing to do here, just iterate to the right position. */\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted after\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxIterator;\r
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\r
+ {\r
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\r
+ pxBlockToInsert = pxIterator;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted before\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxBlockToInsert;\r
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\r
+ {\r
+ if( pxIterator->pxNextFreeBlock != pxEnd )\r
+ {\r
+ /* Form one big block from the two blocks. */\r
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the block being inserted plugged a gab, so was merged with the block\r
+ * before and the block after, then it's pxNextFreeBlock pointer will have\r
+ * already been set, and should not be set here as that would make it point\r
+ * to itself. */\r
+ if( pxIterator != pxBlockToInsert )\r
+ {\r
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvPortMalloc( size_t xWantedSize )\r
+{\r
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
+void *pvReturn = NULL;\r
+\r
+ /* If this is the first call to malloc then the heap will require\r
+ * initialisation to setup the list of free blocks. */\r
+ if( pxEnd == NULL )\r
+ {\r
+ prvHeapInit();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Check the requested block size is not so large that the top bit is set.\r
+ * The top bit of the block size member of the BlockLink_t structure is used\r
+ * to determine who owns the block - the application or the kernel, so it\r
+ * must be free. */\r
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\r
+ {\r
+ /* The wanted size is increased so it can contain a BlockLink_t\r
+ * structure in addition to the requested amount of bytes. */\r
+ if( xWantedSize > 0 )\r
+ {\r
+ xWantedSize += xHeapStructSize;\r
+\r
+ /* Ensure that blocks are always aligned to the required number of\r
+ * bytes. */\r
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\r
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\r
+ {\r
+ /* Traverse the list from the start (lowest address) block until\r
+ * one of adequate size is found. */\r
+ pxPreviousBlock = &xStart;\r
+ pxBlock = xStart.pxNextFreeBlock;\r
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
+ {\r
+ pxPreviousBlock = pxBlock;\r
+ pxBlock = pxBlock->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the end marker was reached then a block of adequate size was\r
+ * not found. */\r
+ if( pxBlock != pxEnd )\r
+ {\r
+ /* Return the memory space pointed to - jumping over the\r
+ * BlockLink_t structure at its start. */\r
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\r
+\r
+ /* This block is being returned for use so must be taken out\r
+ * of the list of free blocks. */\r
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
+\r
+ /* If the block is larger than required it can be split into\r
+ * two. */\r
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\r
+ {\r
+ /* This block is to be split into two. Create a new\r
+ * block following the number of bytes requested. The void\r
+ * cast is used to prevent byte alignment warnings from the\r
+ * compiler. */\r
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+\r
+ /* Calculate the sizes of two blocks split from the single\r
+ * block. */\r
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
+ pxBlock->xBlockSize = xWantedSize;\r
+\r
+ /* Insert the new block into the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( pxNewBlockLink );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ xFreeBytesRemaining -= pxBlock->xBlockSize;\r
+\r
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\r
+ {\r
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* The block is being returned - it is allocated and owned by\r
+ * the application and has no "next" block. */\r
+ pxBlock->xBlockSize |= xBlockAllocatedBit;\r
+ pxBlock->pxNextFreeBlock = NULL;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ traceMALLOC( pvReturn, xWantedSize );\r
+\r
+ #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\r
+ {\r
+ if( pvReturn == NULL )\r
+ {\r
+ extern void vApplicationMallocFailedHook( void );\r
+ vApplicationMallocFailedHook();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ return pvReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFree( void *pv )\r
+{\r
+uint8_t *puc = ( uint8_t * ) pv;\r
+BlockLink_t *pxLink;\r
+\r
+ if( pv != NULL )\r
+ {\r
+ /* The memory being freed will have an BlockLink_t structure immediately\r
+ * before it. */\r
+ puc -= xHeapStructSize;\r
+\r
+ /* This casting is to keep the compiler from issuing warnings. */\r
+ pxLink = ( void * ) puc;\r
+\r
+ /* Check the block is actually allocated. */\r
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\r
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );\r
+\r
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\r
+ {\r
+ if( pxLink->pxNextFreeBlock == NULL )\r
+ {\r
+ /* The block is being returned to the heap - it is no longer\r
+ * allocated. */\r
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;\r
+\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS();\r
+ {\r
+ /* Add this block to the list of free blocks. */\r
+ xFreeBytesRemaining += pxLink->xBlockSize;\r
+ traceFREE( pv, pxLink->xBlockSize );\r
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
+ }\r
+ secureportENABLE_NON_SECURE_INTERRUPTS();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+size_t xPortGetFreeHeapSize( void )\r
+{\r
+ return xFreeBytesRemaining;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+size_t xPortGetMinimumEverFreeHeapSize( void )\r
+{\r
+ return xMinimumEverFreeBytesRemaining;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortInitialiseBlocks( void )\r
+{\r
+ /* This just exists to keep the linker quiet. */\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_HEAP_H__\r
+#define __SECURE_HEAP_H__\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/**\r
+ * @brief Allocates memory from heap.\r
+ *\r
+ * @param[in] xWantedSize The size of the memory to be allocated.\r
+ *\r
+ * @return Pointer to the memory region if the allocation is successful, NULL\r
+ * otherwise.\r
+ */\r
+void *pvPortMalloc( size_t xWantedSize );\r
+\r
+/**\r
+ * @brief Frees the previously allocated memory.\r
+ *\r
+ * @param[in] pv Pointer to the memory to be freed.\r
+ */\r
+void vPortFree( void *pv );\r
+\r
+#endif /* __SECURE_HEAP_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Secure init includes. */\r
+#include "secure_init.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */\r
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )\r
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )\r
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define secureinitFPCCR_LSPENS_POS ( 29UL )\r
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )\r
+#define secureinitFPCCR_TS_POS ( 26UL )\r
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )\r
+\r
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */\r
+#define secureinitNSACR_CP10_POS ( 10UL )\r
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )\r
+#define secureinitNSACR_CP11_POS ( 11UL )\r
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
+ * permitted. CP11 should be programmed to the same value as CP10. */\r
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
+\r
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
+ * that we can enable/disable lazy stacking in port.c file. */\r
+ *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
+\r
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
+ * registers (S16-S31) are also pushed to stack on exception entry and\r
+ * restored on exception return. */\r
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_INIT_H__\r
+#define __SECURE_INIT_H__\r
+\r
+/**\r
+ * @brief De-prioritizes the non-secure exceptions.\r
+ *\r
+ * This is needed to ensure that the non-secure PendSV runs at the lowest\r
+ * priority. Context switch is done in the non-secure PendSV handler.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureInit_DePrioritizeNSExceptions( void );\r
+\r
+/**\r
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\r
+ *\r
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\r
+ * Registers are not leaked to the non-secure side.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureInit_EnableNSFPUAccess( void );\r
+\r
+#endif /* __SECURE_INIT_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_PORT_MACROS_H__\r
+#define __SECURE_PORT_MACROS_H__\r
+\r
+/**\r
+ * @brief Byte alignment requirements.\r
+ */\r
+#define secureportBYTE_ALIGNMENT 8\r
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )\r
+\r
+/**\r
+ * @brief Macro to declare a function as non-secure callable.\r
+ */\r
+#if defined( __IAR_SYSTEMS_ICC__ )\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+#else\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+#endif\r
+\r
+/**\r
+ * @brief Set the secure PRIMASK value.\r
+ */\r
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\r
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+\r
+/**\r
+ * @brief Set the non-secure PRIMASK value.\r
+ */\r
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\r
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+\r
+/**\r
+ * @brief Read the PSP value in the given variable.\r
+ */\r
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\r
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the PSP to the given value.\r
+ */\r
+#define secureportSET_PSP( pucCurrentStackPointer ) \\r
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the PSPLIM to the given value.\r
+ */\r
+#define secureportSET_PSPLIM( pucStackLimit ) \\r
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )\r
+\r
+/**\r
+ * @brief Set the NonSecure MSP to the given value.\r
+ */\r
+#define secureportSET_MSP_NS( pucMainStackPointer ) \\r
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the CONTROL register to the given value.\r
+ */\r
+#define secureportSET_CONTROL( ulControl ) \\r
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )\r
+\r
+/**\r
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given\r
+ * variable.\r
+ */\r
+#define secureportREAD_IPSR( ulIPSR ) \\r
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )\r
+\r
+/**\r
+ * @brief PRIMASK value to enable interrupts.\r
+ */\r
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0\r
+\r
+/**\r
+ * @brief PRIMASK value to disable interrupts.\r
+ */\r
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1\r
+\r
+/**\r
+ * @brief Disable secure interrupts.\r
+ */\r
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Disable non-secure interrupts.\r
+ *\r
+ * This effectively disables context switches.\r
+ */\r
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Enable non-secure interrupts.\r
+ */\r
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Assert definition.\r
+ */\r
+#define secureportASSERT( x ) \\r
+ if( ( x ) == 0 ) \\r
+ { \\r
+ secureportDISABLE_SECURE_INTERRUPTS(); \\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \\r
+ for( ;; ); \\r
+ }\r
+\r
+#endif /* __SECURE_PORT_MACROS_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+ * all the API functions to use the MPU wrappers. That should only be done when\r
+ * task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the NVIC.\r
+ */\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the MPU.\r
+ */\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+\r
+/* Enable privileged access to unmapped region. */\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+\r
+/* Enable MPU. */\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
+\r
+/* Expected value of the portMPU_TYPE register. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to set up the initial stack.\r
+ */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+/**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+#define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+\r
+/**\r
+ * @brief CONTROL register privileged bit mask.\r
+ *\r
+ * Bit[0] in CONTROL register tells the privilege:\r
+ * Bit[0] = 0 ==> The task is privileged.\r
+ * Bit[0] = 1 ==> The task is not privileged.\r
+ */\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+\r
+/**\r
+ * @brief Initial CONTROL register values.\r
+ */\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+\r
+/**\r
+ * @brief Let the user override the pre-loading of the initial LR with the\r
+ * address of prvTaskExitError() in case it messes up unwinding of the stack\r
+ * in the debugger.\r
+ */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/**\r
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
+ * when a task is created. This helps in debugging at the cost of code size.\r
+ */\r
+#define portPRELOAD_REGISTERS 1\r
+\r
+/**\r
+ * @brief A task is created without a secure context, and must call\r
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
+ * any secure calls.\r
+ */\r
+#define portNO_SECURE_CONTEXT 0\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Used to catch tasks that attempt to return from their implementing\r
+ * function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_MPU */\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_FPU */\r
+\r
+/**\r
+ * @brief Yield the processor.\r
+ */\r
+void vPortYield( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enter critical section.\r
+ */\r
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Exit from critical section.\r
+ */\r
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SysTick handler.\r
+ */\r
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief C part of SVC handler.\r
+ */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Each task maintains its own interrupt status in the critical nesting\r
+ * variable.\r
+ */\r
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+volatile uint32_t ulDummy = 0UL;\r
+\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash and system calls flash as Read Only by\r
+ * both privileged and unprivileged tasks. All tasks can read it but\r
+ * no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* By default allow everything to access the general peripherals.\r
+ * The system peripherals and registers are protected. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX1 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
+#endif /* configENABLE_FPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
+\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+uint32_t ulPreviousMask;\r
+\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+{\r
+#if( configENABLE_MPU == 1 )\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+#endif /* configENABLE_MPU */\r
+\r
+uint32_t ulPC;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
+#endif /* configENABLE_TRUSTZONE */\r
+uint8_t ucSVCNumber;\r
+\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+#else\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+#endif /* configENABLE_MPU */\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r3, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r3, #4 \n" /* r3 = 4. */\r
+ " str r3, [r2] \n" /* Program RNR = 4. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r1!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r2 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r2 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ " ite ne \n"\r
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " bic r0, #1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " orr r0, #1 \n" /* r0 = r0 | 1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
+\r
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r0, psp \n" /* Read PSP in r0. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vstmdbeq r0!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " mrs r1, psplim \n" /* r1 = PSPLIM. */\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmdb r0!, {r1-r11} \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
+ #else /* configENABLE_MPU */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
+ " \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r3, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r3, #4 \n" /* r3 = 4. */\r
+ " str r3, [r2] \n" /* Program RNR = 4. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r1!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r0!, {r1-r11} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
+ #else /* configENABLE_MPU */\r
+ " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vldmiaeq r0!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r2 \n" /* Restore the CONTROL register value for the task. */\r
+ #else /* configENABLE_MPU */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ #endif /* configENABLE_MPU */\r
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
+ " bx r3 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, svchandler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __PORT_ASM_H__\r
+#define __PORT_ASM_H__\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/**\r
+ * @brief Restore the context of the first task so that the first task starts\r
+ * executing.\r
+ */\r
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * @note This is a privileged function and should only be called from the kenrel\r
+ * code.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Starts the first task.\r
+ */\r
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Disables interrupts.\r
+ */\r
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enables interrupts.\r
+ */\r
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief PendSV Exception handler.\r
+ */\r
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SVC Handler.\r
+ */\r
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Allocate a Secure context for the calling task.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the\r
+ * secure side for the calling task.\r
+ */\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Free the task's secure context.\r
+ *\r
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\r
+ */\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+#endif /* __PORT_ASM_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portPRIVILEGED_RAM_REGION ( 2UL )\r
+#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Devices Region. */\r
+#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
+#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
*/\r
static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
\r
-/*\r
- * Checks to see if being called from the context of an unprivileged task, and\r
- * if so raises the privilege level and returns false - otherwise does nothing\r
- * other than return true.\r
- */\r
-BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));\r
-\r
/*\r
* Setup the timer to generate the tick interrupts. The implementation in this\r
* file is weak to allow application writers to change the timer used to\r
*/\r
static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Calls the port specific code to raise the privilege.\r
+ *\r
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.\r
+ */\r
+extern BaseType_t xPortRaisePrivilege( void );\r
+\r
+/**\r
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific\r
+ * code to reset the privilege, otherwise does nothing.\r
+ */\r
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );\r
/*-----------------------------------------------------------*/\r
\r
/* Each task maintains its own interrupt status in the critical nesting\r
}\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t xPortRaisePrivilege( void )\r
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
{\r
__asm volatile\r
(\r
- " mrs r0, control \n"\r
- " tst r0, #1 \n" /* Is the task running privileged? */\r
- " itte ne \n"\r
- " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */\r
- " svcne %0 \n" /* Switch to privileged. */\r
- " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */\r
- " bx lr \n"\r
- :: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ " ite ne \n"\r
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "memory"\r
);\r
+}\r
+/*-----------------------------------------------------------*/\r
\r
- return 0;\r
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " orr r0, #1 \n" /* r0 = r0 | 1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
#ifndef portFORCE_INLINE\r
#define portFORCE_INLINE inline __attribute__(( always_inline))\r
#endif\r
+/*-----------------------------------------------------------*/\r
\r
-/* Set the privilege level to user mode if xRunningPrivileged is false. */\r
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )\r
-{\r
- if( xRunningPrivileged != pdTRUE )\r
- {\r
- __asm volatile ( " mrs r0, control \n" \\r
- " orr r0, #1 \n" \\r
- " msr control, r0 \n" \\r
- :::"r0", "memory" );\r
- }\r
-}\r
+extern BaseType_t xIsPrivileged( void );\r
+extern void vResetPrivilege( void );\r
+\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+#define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+/**\r
+ * @brief Raise an SVC request to raise privilege.\r
+*/\r
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+#define portRESET_PRIVILEGE() vResetPrivilege()\r
/*-----------------------------------------------------------*/\r
\r
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\r
*/\r
static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
\r
-/*\r
- * Checks to see if being called from the context of an unprivileged task, and\r
- * if so raises the privilege level and returns false - otherwise does nothing\r
- * other than return true.\r
- */\r
-BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));\r
-\r
/*\r
* Setup the timer to generate the tick interrupts. The implementation in this\r
* file is weak to allow application writers to change the timer used to\r
*/\r
static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Calls the port specific code to raise the privilege.\r
+ *\r
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.\r
+ */\r
+extern BaseType_t xPortRaisePrivilege( void );\r
+\r
+/**\r
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific\r
+ * code to reset the privilege, otherwise does nothing.\r
+ */\r
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );\r
/*-----------------------------------------------------------*/\r
\r
/* Each task maintains its own interrupt status in the critical nesting\r
}\r
/*-----------------------------------------------------------*/\r
\r
-BaseType_t xPortRaisePrivilege( void )\r
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
{\r
__asm volatile\r
(\r
- " mrs r0, control \n"\r
- " tst r0, #1 \n" /* Is the task running privileged? */\r
- " itte ne \n"\r
- " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */\r
- " svcne %0 \n" /* Switch to privileged. */\r
- " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */\r
- " bx lr \n"\r
- :: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ " ite ne \n"\r
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "memory"\r
);\r
+}\r
+/*-----------------------------------------------------------*/\r
\r
- return 0;\r
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
+{\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " orr r0, #1 \n" /* r0 = r0 | 1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
#ifndef portFORCE_INLINE\r
#define portFORCE_INLINE inline __attribute__(( always_inline))\r
#endif\r
+/*-----------------------------------------------------------*/\r
\r
-/* Set the privilege level to user mode if xRunningPrivileged is false. */\r
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )\r
-{\r
- if( xRunningPrivileged != pdTRUE )\r
- {\r
- __asm volatile ( " mrs r0, control \n" \\r
- " orr r0, #1 \n" \\r
- " msr control, r0 \n" \\r
- :::"r0", "memory" );\r
- }\r
-}\r
+extern BaseType_t xIsPrivileged( void );\r
+extern void vResetPrivilege( void );\r
+\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+#define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+/**\r
+ * @brief Raise an SVC request to raise privilege.\r
+*/\r
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+#define portRESET_PRIVILEGE() vResetPrivilege()\r
/*-----------------------------------------------------------*/\r
\r
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+ * all the API functions to use the MPU wrappers. That should only be done when\r
+ * task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the NVIC.\r
+ */\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the MPU.\r
+ */\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+\r
+/* Enable privileged access to unmapped region. */\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+\r
+/* Enable MPU. */\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
+\r
+/* Expected value of the portMPU_TYPE register. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to set up the initial stack.\r
+ */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+/**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+#define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+\r
+/**\r
+ * @brief CONTROL register privileged bit mask.\r
+ *\r
+ * Bit[0] in CONTROL register tells the privilege:\r
+ * Bit[0] = 0 ==> The task is privileged.\r
+ * Bit[0] = 1 ==> The task is not privileged.\r
+ */\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+\r
+/**\r
+ * @brief Initial CONTROL register values.\r
+ */\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+\r
+/**\r
+ * @brief Let the user override the pre-loading of the initial LR with the\r
+ * address of prvTaskExitError() in case it messes up unwinding of the stack\r
+ * in the debugger.\r
+ */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/**\r
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
+ * when a task is created. This helps in debugging at the cost of code size.\r
+ */\r
+#define portPRELOAD_REGISTERS 1\r
+\r
+/**\r
+ * @brief A task is created without a secure context, and must call\r
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
+ * any secure calls.\r
+ */\r
+#define portNO_SECURE_CONTEXT 0\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Used to catch tasks that attempt to return from their implementing\r
+ * function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_MPU */\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_FPU */\r
+\r
+/**\r
+ * @brief Yield the processor.\r
+ */\r
+void vPortYield( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enter critical section.\r
+ */\r
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Exit from critical section.\r
+ */\r
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SysTick handler.\r
+ */\r
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief C part of SVC handler.\r
+ */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Each task maintains its own interrupt status in the critical nesting\r
+ * variable.\r
+ */\r
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+volatile uint32_t ulDummy = 0UL;\r
+\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash and system calls flash as Read Only by\r
+ * both privileged and unprivileged tasks. All tasks can read it but\r
+ * no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* By default allow everything to access the general peripherals.\r
+ * The system peripherals and registers are protected. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX1 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
+#endif /* configENABLE_FPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
+\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+uint32_t ulPreviousMask;\r
+\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+{\r
+#if( configENABLE_MPU == 1 )\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+#endif /* configENABLE_MPU */\r
+\r
+uint32_t ulPC;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
+#endif /* configENABLE_TRUSTZONE */\r
+uint8_t ucSVCNumber;\r
+\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+#else\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+#endif /* configENABLE_MPU */\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __PORT_ASM_H__\r
+#define __PORT_ASM_H__\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/**\r
+ * @brief Restore the context of the first task so that the first task starts\r
+ * executing.\r
+ */\r
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * @note This is a privileged function and should only be called from the kenrel\r
+ * code.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Starts the first task.\r
+ */\r
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Disables interrupts.\r
+ */\r
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enables interrupts.\r
+ */\r
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief PendSV Exception handler.\r
+ */\r
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SVC Handler.\r
+ */\r
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Allocate a Secure context for the calling task.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the\r
+ * secure side for the calling task.\r
+ */\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Free the task's secure context.\r
+ *\r
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\r
+ */\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+#endif /* __PORT_ASM_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ EXTERN pxCurrentTCB\r
+ EXTERN xSecureContext\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+ EXTERN SecureContext_SaveContext\r
+ EXTERN SecureContext_LoadContext\r
+\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vPortAllocateSecureContext\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
+ PUBLIC vPortFreeSecureContext\r
+/*-----------------------------------------------------------*/\r
+\r
+/*---------------- Unprivileged Functions -------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+xIsPrivileged:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vResetPrivilege:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orr r0, r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vPortAllocateSecureContext:\r
+ svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/*----------------- Privileged Functions --------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+vRestoreContextOfFirstTask:\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ ldr r5, =xSecureContext\r
+ str r1, [r5] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ msr control, r3 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r4 /* Finally, branch to EXC_RETURN. */\r
+#else /* configENABLE_MPU */\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ ldr r4, =xSecureContext\r
+ str r1, [r4] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+vRaisePrivilege:\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ bic r0, r0, #1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vStartFirstTask:\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+/*-----------------------------------------------------------*/\r
+\r
+ulSetInterruptMaskFromISR:\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+vClearInterruptMaskFromISR:\r
+ msr PRIMASK, r0\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+PendSV_Handler:\r
+ mrs r1, psp /* Read PSP in r1. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+\r
+ cbz r0, save_ns_context /* No secure context to save. */\r
+ push {r0-r2, r14}\r
+ bl SecureContext_SaveContext\r
+ pop {r0-r3} /* LR is now in r3. */\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
+#if ( configENABLE_MPU == 1 )\r
+ subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+#else /* configENABLE_MPU */\r
+ subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+#endif /* configENABLE_MPU */\r
+ b select_next_task\r
+\r
+ save_ns_context:\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
+ #if ( configENABLE_FPU == 1 )\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if ( configENABLE_MPU == 1 )\r
+ subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ adds r1, r1, #16 /* r1 = r1 + 16. */\r
+ stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ subs r1, r1, #16 /* r1 = r1 - 16. */\r
+ stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ adds r1, r1, #12 /* r1 = r1 + 12. */\r
+ stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ subs r1, r1, #12 /* r1 = r1 - 12. */\r
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+\r
+ select_next_task:\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
+\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+\r
+ #if ( configENABLE_MPU == 1 )\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+\r
+ #if ( configENABLE_MPU == 1 )\r
+ ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r3 /* Restore the CONTROL register value for the task. */\r
+ mov lr, r4 /* LR = r4. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r4}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r4}\r
+ mov lr, r4 /* LR = r4. */\r
+ lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #else /* configENABLE_MPU */\r
+ ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ mov lr, r3 /* LR = r3. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r3}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r3}\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #endif /* configENABLE_MPU */\r
+\r
+ restore_ns_context:\r
+ ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */\r
+ #if ( configENABLE_FPU == 1 )\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+SVC_Handler:\r
+ tst lr, #4\r
+ ite eq\r
+ mrseq r0, msp\r
+ mrsne r0, psp\r
+ b vPortSVCHandler_C\r
+/*-----------------------------------------------------------*/\r
+\r
+vPortFreeSecureContext:\r
+ /* r0 = uint32_t *pulTCB. */\r
+ ldr r1, [r0] /* The first item in the TCB is the top of the stack. */\r
+ ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */\r
+ cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */\r
+ it ne\r
+ svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portPRIVILEGED_RAM_REGION ( 2UL )\r
+#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Devices Region. */\r
+#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
+#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure heap includes. */\r
+#include "secure_heap.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief CONTROL value for privileged tasks.\r
+ *\r
+ * Bit[0] - 0 --> Thread mode is privileged.\r
+ * Bit[1] - 1 --> Thread mode uses PSP.\r
+ */\r
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02\r
+\r
+/**\r
+ * @brief CONTROL value for un-privileged tasks.\r
+ *\r
+ * Bit[0] - 1 --> Thread mode is un-privileged.\r
+ * Bit[1] - 1 --> Thread mode uses PSP.\r
+ */\r
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Structure to represent secure context.\r
+ *\r
+ * @note Since stack grows down, pucStackStart is the highest address while\r
+ * pucStackLimit is the first addess of the allocated memory.\r
+ */\r
+typedef struct SecureContext\r
+{\r
+ uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\r
+ uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */\r
+ uint8_t *pucStackStart; /**< First location of the stack memory. */\r
+} SecureContext_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* No stack for thread mode until a task's context is loaded. */\r
+ secureportSET_PSPLIM( securecontextNO_STACK );\r
+ secureportSET_PSP( securecontextNO_STACK );\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Configure thread mode to use PSP and to be unprivileged. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Configure thread mode to use PSP and to be privileged.. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )\r
+#else /* configENABLE_MPU */\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )\r
+#endif /* configENABLE_MPU */\r
+{\r
+ uint8_t *pucStackMemory = NULL;\r
+ uint32_t ulIPSR;\r
+ SecureContextHandle_t xSecureContextHandle = NULL;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t *pulCurrentStackPointer = NULL;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Allocate the context structure. */\r
+ xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );\r
+\r
+ if( xSecureContextHandle != NULL )\r
+ {\r
+ /* Allocate the stack space. */\r
+ pucStackMemory = pvPortMalloc( ulSecureStackSize );\r
+\r
+ if( pucStackMemory != NULL )\r
+ {\r
+ /* Since stack grows down, the starting point will be the last\r
+ * location. Note that this location is next to the last\r
+ * allocated byte because the hardware decrements the stack\r
+ * pointer before writing i.e. if stack pointer is 0x2, a push\r
+ * operation will decrement the stack pointer to 0x1 and then\r
+ * write at 0x1. */\r
+ xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;\r
+\r
+ /* The stack cannot go beyond this location. This value is\r
+ * programmed in the PSPLIM register on context switch.*/\r
+ xSecureContextHandle->pucStackLimit = pucStackMemory;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Store the correct CONTROL value for the task on the stack.\r
+ * This value is programmed in the CONTROL register on\r
+ * context switch. */\r
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;\r
+ pulCurrentStackPointer--;\r
+ if( ulIsTaskPrivileged )\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\r
+ }\r
+ else\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\r
+ }\r
+\r
+ /* Store the current stack pointer. This value is programmed in\r
+ * the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Current SP is set to the starting of the stack. This\r
+ * value programmed in the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;\r
+\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+ else\r
+ {\r
+ /* Free the context to avoid memory leak and make sure to return\r
+ * NULL to indicate failure. */\r
+ vPortFree( xSecureContextHandle );\r
+ xSecureContextHandle = NULL;\r
+ }\r
+ }\r
+ }\r
+\r
+ return xSecureContextHandle;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Ensure that valid parameters are passed. */\r
+ secureportASSERT( xSecureContextHandle != NULL );\r
+\r
+ /* Free the stack space. */\r
+ vPortFree( xSecureContextHandle->pucStackLimit );\r
+\r
+ /* Free the context itself. */\r
+ vPortFree( xSecureContextHandle );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_CONTEXT_H__\r
+#define __SECURE_CONTEXT_H__\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOSConfig.h"\r
+\r
+/**\r
+ * @brief PSP value when no task's context is loaded.\r
+ */\r
+#define securecontextNO_STACK 0x0\r
+\r
+/**\r
+ * @brief Opaque handle.\r
+ */\r
+struct SecureContext;\r
+typedef struct SecureContext* SecureContextHandle_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Initializes the secure context management system.\r
+ *\r
+ * PSP is set to NULL and therefore a task must allocate and load a context\r
+ * before calling any secure side function in the thread mode.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureContext_Init( void );\r
+\r
+/**\r
+ * @brief Allocates a context on the secure side.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.\r
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.\r
+ *\r
+ * @return Opaque context handle if context is successfully allocated, NULL\r
+ * otherwise.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );\r
+#else /* configENABLE_MPU */\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );\r
+#endif /* configENABLE_MPU */\r
+\r
+/**\r
+ * @brief Frees the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the\r
+ * context to be freed.\r
+ */\r
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+/**\r
+ * @brief Loads the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the context\r
+ * to be loaded.\r
+ */\r
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+/**\r
+ * @brief Saves the given context.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ *\r
+ * @param[in] xSecureContextHandle Context handle corresponding to the context\r
+ * to be saved.\r
+ */\r
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );\r
+\r
+#endif /* __SECURE_CONTEXT_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Secure context includes. */\r
+#include "secure_context.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/* Functions implemented in assembler file. */\r
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );\r
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ SecureContext_LoadContextAsm( xSecureContextHandle );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
+{\r
+ SecureContext_SaveContextAsm( xSecureContextHandle );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+\r
+ PUBLIC SecureContext_LoadContextAsm\r
+ PUBLIC SecureContext_SaveContextAsm\r
+/*-----------------------------------------------------------*/\r
+\r
+SecureContext_LoadContextAsm:\r
+ /* xSecureContextHandle value is in r0. */\r
+ mrs r1, ipsr /* r1 = IPSR. */\r
+ cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
+ ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+#if ( configENABLE_MPU == 1 )\r
+ ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+ msr control, r3 /* CONTROL = r3. */\r
+#endif /* configENABLE_MPU */\r
+ msr psplim, r2 /* PSPLIM = r2. */\r
+ msr psp, r1 /* PSP = r1. */\r
+\r
+ load_ctx_therad_mode:\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+SecureContext_SaveContextAsm:\r
+ /* xSecureContextHandle value is in r0. */\r
+ mrs r1, ipsr /* r1 = IPSR. */\r
+ cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
+ mrs r1, psp /* r1 = PSP. */\r
+#if ( configENABLE_FPU == 1 )\r
+ vstmdb r1!, {s0} /* Trigger the defferred stacking of FPU registers. */\r
+ vldmia r1!, {s0} /* Nullify the effect of the pervious statement. */\r
+#endif /* configENABLE_FPU */\r
+#if ( configENABLE_MPU == 1 )\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ stmdb r1!, {r2} /* Store CONTROL value on the stack. */\r
+#endif /* configENABLE_MPU */\r
+ str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ movs r1, #0 /* r1 = securecontextNO_STACK. */\r
+ msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */\r
+ msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+\r
+ save_ctx_therad_mode:\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Secure context heap includes. */\r
+#include "secure_heap.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief Total heap size.\r
+ */\r
+#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )\r
+\r
+/* No test marker by default. */\r
+#ifndef mtCOVERAGE_TEST_MARKER\r
+ #define mtCOVERAGE_TEST_MARKER()\r
+#endif\r
+\r
+/* No tracing by default. */\r
+#ifndef traceMALLOC\r
+ #define traceMALLOC( pvReturn, xWantedSize )\r
+#endif\r
+\r
+/* No tracing by default. */\r
+#ifndef traceFREE\r
+ #define traceFREE( pv, xBlockSize )\r
+#endif\r
+\r
+/* Block sizes must not get too small. */\r
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )\r
+\r
+/* Assumes 8bit bytes! */\r
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Allocate the memory for the heap. */\r
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )\r
+ /* The application writer has already defined the array used for the RTOS\r
+ * heap - probably so it can be placed in a special segment or address. */\r
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+#else /* configAPPLICATION_ALLOCATED_HEAP */\r
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+#endif /* configAPPLICATION_ALLOCATED_HEAP */\r
+\r
+/**\r
+ * @brief The linked list structure.\r
+ *\r
+ * This is used to link free blocks in order of their memory address.\r
+ */\r
+typedef struct A_BLOCK_LINK\r
+{\r
+ struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */\r
+ size_t xBlockSize; /**< The size of the free block. */\r
+} BlockLink_t;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Called automatically to setup the required heap structures the first\r
+ * time pvPortMalloc() is called.\r
+ */\r
+static void prvHeapInit( void );\r
+\r
+/**\r
+ * @brief Inserts a block of memory that is being freed into the correct\r
+ * position in the list of free memory blocks.\r
+ *\r
+ * The block being freed will be merged with the block in front it and/or the\r
+ * block behind it if the memory blocks are adjacent to each other.\r
+ *\r
+ * @param[in] pxBlockToInsert The block being freed.\r
+ */\r
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief The size of the structure placed at the beginning of each allocated\r
+ * memory block must by correctly byte aligned.\r
+ */\r
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+\r
+/**\r
+ * @brief Create a couple of list links to mark the start and end of the list.\r
+ */\r
+static BlockLink_t xStart, *pxEnd = NULL;\r
+\r
+/**\r
+ * @brief Keeps track of the number of free bytes remaining, but says nothing\r
+ * about fragmentation.\r
+ */\r
+static size_t xFreeBytesRemaining = 0U;\r
+static size_t xMinimumEverFreeBytesRemaining = 0U;\r
+\r
+/**\r
+ * @brief Gets set to the top bit of an size_t type.\r
+ *\r
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set\r
+ * then the block belongs to the application. When the bit is free the block is\r
+ * still part of the free heap space.\r
+ */\r
+static size_t xBlockAllocatedBit = 0;\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHeapInit( void )\r
+{\r
+BlockLink_t *pxFirstFreeBlock;\r
+uint8_t *pucAlignedHeap;\r
+size_t uxAddress;\r
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\r
+\r
+ /* Ensure the heap starts on a correctly aligned boundary. */\r
+ uxAddress = ( size_t ) ucHeap;\r
+\r
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\r
+ {\r
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\r
+ }\r
+\r
+ pucAlignedHeap = ( uint8_t * ) uxAddress;\r
+\r
+ /* xStart is used to hold a pointer to the first item in the list of free\r
+ * blocks. The void cast is used to prevent compiler warnings. */\r
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
+ xStart.xBlockSize = ( size_t ) 0;\r
+\r
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted\r
+ * at the end of the heap space. */\r
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\r
+ uxAddress -= xHeapStructSize;\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ pxEnd = ( void * ) uxAddress;\r
+ pxEnd->xBlockSize = 0;\r
+ pxEnd->pxNextFreeBlock = NULL;\r
+\r
+ /* To start with there is a single free block that is sized to take up the\r
+ * entire heap space, minus the space taken by pxEnd. */\r
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\r
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\r
+\r
+ /* Only one block exists - and it covers the entire usable heap space. */\r
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+\r
+ /* Work out the position of the top bit in a size_t variable. */\r
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )\r
+{\r
+BlockLink_t *pxIterator;\r
+uint8_t *puc;\r
+\r
+ /* Iterate through the list until a block is found that has a higher address\r
+ * than the block being inserted. */\r
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\r
+ {\r
+ /* Nothing to do here, just iterate to the right position. */\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted after\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxIterator;\r
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\r
+ {\r
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\r
+ pxBlockToInsert = pxIterator;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted before\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxBlockToInsert;\r
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\r
+ {\r
+ if( pxIterator->pxNextFreeBlock != pxEnd )\r
+ {\r
+ /* Form one big block from the two blocks. */\r
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the block being inserted plugged a gab, so was merged with the block\r
+ * before and the block after, then it's pxNextFreeBlock pointer will have\r
+ * already been set, and should not be set here as that would make it point\r
+ * to itself. */\r
+ if( pxIterator != pxBlockToInsert )\r
+ {\r
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvPortMalloc( size_t xWantedSize )\r
+{\r
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
+void *pvReturn = NULL;\r
+\r
+ /* If this is the first call to malloc then the heap will require\r
+ * initialisation to setup the list of free blocks. */\r
+ if( pxEnd == NULL )\r
+ {\r
+ prvHeapInit();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Check the requested block size is not so large that the top bit is set.\r
+ * The top bit of the block size member of the BlockLink_t structure is used\r
+ * to determine who owns the block - the application or the kernel, so it\r
+ * must be free. */\r
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\r
+ {\r
+ /* The wanted size is increased so it can contain a BlockLink_t\r
+ * structure in addition to the requested amount of bytes. */\r
+ if( xWantedSize > 0 )\r
+ {\r
+ xWantedSize += xHeapStructSize;\r
+\r
+ /* Ensure that blocks are always aligned to the required number of\r
+ * bytes. */\r
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\r
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\r
+ {\r
+ /* Traverse the list from the start (lowest address) block until\r
+ * one of adequate size is found. */\r
+ pxPreviousBlock = &xStart;\r
+ pxBlock = xStart.pxNextFreeBlock;\r
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
+ {\r
+ pxPreviousBlock = pxBlock;\r
+ pxBlock = pxBlock->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the end marker was reached then a block of adequate size was\r
+ * not found. */\r
+ if( pxBlock != pxEnd )\r
+ {\r
+ /* Return the memory space pointed to - jumping over the\r
+ * BlockLink_t structure at its start. */\r
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\r
+\r
+ /* This block is being returned for use so must be taken out\r
+ * of the list of free blocks. */\r
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
+\r
+ /* If the block is larger than required it can be split into\r
+ * two. */\r
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\r
+ {\r
+ /* This block is to be split into two. Create a new\r
+ * block following the number of bytes requested. The void\r
+ * cast is used to prevent byte alignment warnings from the\r
+ * compiler. */\r
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+\r
+ /* Calculate the sizes of two blocks split from the single\r
+ * block. */\r
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
+ pxBlock->xBlockSize = xWantedSize;\r
+\r
+ /* Insert the new block into the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( pxNewBlockLink );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ xFreeBytesRemaining -= pxBlock->xBlockSize;\r
+\r
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\r
+ {\r
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* The block is being returned - it is allocated and owned by\r
+ * the application and has no "next" block. */\r
+ pxBlock->xBlockSize |= xBlockAllocatedBit;\r
+ pxBlock->pxNextFreeBlock = NULL;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ traceMALLOC( pvReturn, xWantedSize );\r
+\r
+ #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\r
+ {\r
+ if( pvReturn == NULL )\r
+ {\r
+ extern void vApplicationMallocFailedHook( void );\r
+ vApplicationMallocFailedHook();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ return pvReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFree( void *pv )\r
+{\r
+uint8_t *puc = ( uint8_t * ) pv;\r
+BlockLink_t *pxLink;\r
+\r
+ if( pv != NULL )\r
+ {\r
+ /* The memory being freed will have an BlockLink_t structure immediately\r
+ * before it. */\r
+ puc -= xHeapStructSize;\r
+\r
+ /* This casting is to keep the compiler from issuing warnings. */\r
+ pxLink = ( void * ) puc;\r
+\r
+ /* Check the block is actually allocated. */\r
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\r
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );\r
+\r
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\r
+ {\r
+ if( pxLink->pxNextFreeBlock == NULL )\r
+ {\r
+ /* The block is being returned to the heap - it is no longer\r
+ * allocated. */\r
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;\r
+\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS();\r
+ {\r
+ /* Add this block to the list of free blocks. */\r
+ xFreeBytesRemaining += pxLink->xBlockSize;\r
+ traceFREE( pv, pxLink->xBlockSize );\r
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
+ }\r
+ secureportENABLE_NON_SECURE_INTERRUPTS();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+size_t xPortGetFreeHeapSize( void )\r
+{\r
+ return xFreeBytesRemaining;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+size_t xPortGetMinimumEverFreeHeapSize( void )\r
+{\r
+ return xMinimumEverFreeBytesRemaining;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortInitialiseBlocks( void )\r
+{\r
+ /* This just exists to keep the linker quiet. */\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_HEAP_H__\r
+#define __SECURE_HEAP_H__\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/**\r
+ * @brief Allocates memory from heap.\r
+ *\r
+ * @param[in] xWantedSize The size of the memory to be allocated.\r
+ *\r
+ * @return Pointer to the memory region if the allocation is successful, NULL\r
+ * otherwise.\r
+ */\r
+void *pvPortMalloc( size_t xWantedSize );\r
+\r
+/**\r
+ * @brief Frees the previously allocated memory.\r
+ *\r
+ * @param[in] pv Pointer to the memory to be freed.\r
+ */\r
+void vPortFree( void *pv );\r
+\r
+#endif /* __SECURE_HEAP_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+\r
+/* Secure init includes. */\r
+#include "secure_init.h"\r
+\r
+/* Secure port macros. */\r
+#include "secure_port_macros.h"\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */\r
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )\r
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )\r
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define secureinitFPCCR_LSPENS_POS ( 29UL )\r
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )\r
+#define secureinitFPCCR_TS_POS ( 26UL )\r
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )\r
+\r
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */\r
+#define secureinitNSACR_CP10_POS ( 10UL )\r
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )\r
+#define secureinitNSACR_CP11_POS ( 11UL )\r
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\r
+{\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
+ * permitted. CP11 should be programmed to the same value as CP10. */\r
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
+\r
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
+ * that we can enable/disable lazy stacking in port.c file. */\r
+ *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
+\r
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
+ * registers (S16-S31) are also pushed to stack on exception entry and\r
+ * restored on exception return. */\r
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_INIT_H__\r
+#define __SECURE_INIT_H__\r
+\r
+/**\r
+ * @brief De-prioritizes the non-secure exceptions.\r
+ *\r
+ * This is needed to ensure that the non-secure PendSV runs at the lowest\r
+ * priority. Context switch is done in the non-secure PendSV handler.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureInit_DePrioritizeNSExceptions( void );\r
+\r
+/**\r
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.\r
+ *\r
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point\r
+ * Registers are not leaked to the non-secure side.\r
+ *\r
+ * @note This function must be called in the handler mode. It is no-op if called\r
+ * in the thread mode.\r
+ */\r
+void SecureInit_EnableNSFPUAccess( void );\r
+\r
+#endif /* __SECURE_INIT_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __SECURE_PORT_MACROS_H__\r
+#define __SECURE_PORT_MACROS_H__\r
+\r
+/**\r
+ * @brief Byte alignment requirements.\r
+ */\r
+#define secureportBYTE_ALIGNMENT 8\r
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )\r
+\r
+/**\r
+ * @brief Macro to declare a function as non-secure callable.\r
+ */\r
+#if defined( __IAR_SYSTEMS_ICC__ )\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+#else\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+#endif\r
+\r
+/**\r
+ * @brief Set the secure PRIMASK value.\r
+ */\r
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\r
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+\r
+/**\r
+ * @brief Set the non-secure PRIMASK value.\r
+ */\r
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\r
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+\r
+/**\r
+ * @brief Read the PSP value in the given variable.\r
+ */\r
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\r
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the PSP to the given value.\r
+ */\r
+#define secureportSET_PSP( pucCurrentStackPointer ) \\r
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the PSPLIM to the given value.\r
+ */\r
+#define secureportSET_PSPLIM( pucStackLimit ) \\r
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )\r
+\r
+/**\r
+ * @brief Set the NonSecure MSP to the given value.\r
+ */\r
+#define secureportSET_MSP_NS( pucMainStackPointer ) \\r
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )\r
+\r
+/**\r
+ * @brief Set the CONTROL register to the given value.\r
+ */\r
+#define secureportSET_CONTROL( ulControl ) \\r
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )\r
+\r
+/**\r
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given\r
+ * variable.\r
+ */\r
+#define secureportREAD_IPSR( ulIPSR ) \\r
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )\r
+\r
+/**\r
+ * @brief PRIMASK value to enable interrupts.\r
+ */\r
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0\r
+\r
+/**\r
+ * @brief PRIMASK value to disable interrupts.\r
+ */\r
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1\r
+\r
+/**\r
+ * @brief Disable secure interrupts.\r
+ */\r
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Disable non-secure interrupts.\r
+ *\r
+ * This effectively disables context switches.\r
+ */\r
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Enable non-secure interrupts.\r
+ */\r
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\r
+\r
+/**\r
+ * @brief Assert definition.\r
+ */\r
+#define secureportASSERT( x ) \\r
+ if( ( x ) == 0 ) \\r
+ { \\r
+ secureportDISABLE_SECURE_INTERRUPTS(); \\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \\r
+ for( ;; ); \\r
+ }\r
+\r
+#endif /* __SECURE_PORT_MACROS_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+ * all the API functions to use the MPU wrappers. That should only be done when\r
+ * task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/* Portasm includes. */\r
+#include "portasm.h"\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the NVIC.\r
+ */\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the SCB.\r
+ */\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the FPU.\r
+ */\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to manipulate the MPU.\r
+ */\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+\r
+/* Enable privileged access to unmapped region. */\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+\r
+/* Enable MPU. */\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
+\r
+/* Expected value of the portMPU_TYPE register. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Constants required to set up the initial stack.\r
+ */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+/**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+#define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+\r
+/**\r
+ * @brief CONTROL register privileged bit mask.\r
+ *\r
+ * Bit[0] in CONTROL register tells the privilege:\r
+ * Bit[0] = 0 ==> The task is privileged.\r
+ * Bit[0] = 1 ==> The task is not privileged.\r
+ */\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+\r
+/**\r
+ * @brief Initial CONTROL register values.\r
+ */\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+\r
+/**\r
+ * @brief Let the user override the pre-loading of the initial LR with the\r
+ * address of prvTaskExitError() in case it messes up unwinding of the stack\r
+ * in the debugger.\r
+ */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/**\r
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
+ * when a task is created. This helps in debugging at the cost of code size.\r
+ */\r
+#define portPRELOAD_REGISTERS 1\r
+\r
+/**\r
+ * @brief A task is created without a secure context, and must call\r
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
+ * any secure calls.\r
+ */\r
+#define portNO_SECURE_CONTEXT 0\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Used to catch tasks that attempt to return from their implementing\r
+ * function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_MPU */\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+#endif /* configENABLE_FPU */\r
+\r
+/**\r
+ * @brief Yield the processor.\r
+ */\r
+void vPortYield( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enter critical section.\r
+ */\r
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Exit from critical section.\r
+ */\r
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SysTick handler.\r
+ */\r
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief C part of SVC handler.\r
+ */\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Each task maintains its own interrupt status in the critical nesting\r
+ * variable.\r
+ */\r
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+volatile uint32_t ulDummy = 0UL;\r
+\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash and system calls flash as Read Only by\r
+ * both privileged and unprivileged tasks. All tasks can read it but\r
+ * no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* By default allow everything to access the general peripherals.\r
+ * The system peripherals and registers are protected. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX1 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_FPU == 1 )\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
+#endif /* configENABLE_FPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
+\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
+\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+uint32_t ulPreviousMask;\r
+\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
+{\r
+#if( configENABLE_MPU == 1 )\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+#endif /* configENABLE_MPU */\r
+\r
+uint32_t ulPC;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
+#endif /* configENABLE_TRUSTZONE */\r
+uint8_t ucSVCNumber;\r
+\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+#else\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+#endif /* configENABLE_MPU */\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef __PORT_ASM_H__\r
+#define __PORT_ASM_H__\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* MPU wrappers includes. */\r
+#include "mpu_wrappers.h"\r
+\r
+/**\r
+ * @brief Restore the context of the first task so that the first task starts\r
+ * executing.\r
+ */\r
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * @note This is a privileged function and should only be called from the kenrel\r
+ * code.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Starts the first task.\r
+ */\r
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Disables interrupts.\r
+ */\r
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Enables interrupts.\r
+ */\r
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief PendSV Exception handler.\r
+ */\r
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief SVC Handler.\r
+ */\r
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * @brief Allocate a Secure context for the calling task.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the\r
+ * secure side for the calling task.\r
+ */\r
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));\r
+\r
+/**\r
+ * @brief Free the task's secure context.\r
+ *\r
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.\r
+ */\r
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
+\r
+#endif /* __PORT_ASM_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ EXTERN pxCurrentTCB\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
+/*-----------------------------------------------------------*/\r
+\r
+/*---------------- Unprivileged Functions -------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+xIsPrivileged:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vResetPrivilege:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orr r0, r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/*----------------- Privileged Functions --------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
+/*-----------------------------------------------------------*/\r
+\r
+vRestoreContextOfFirstTask:\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r3, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r3, #4 /* r3 = 4. */\r
+ str r3, [r2] /* Program RNR = 4. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ msr control, r2 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
+#else /* configENABLE_MPU */\r
+ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r2 /* Finally, branch to EXC_RETURN. */\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+vRaisePrivilege:\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ bic r0, r0, #1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
+\r
+vStartFirstTask:\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+/*-----------------------------------------------------------*/\r
+\r
+ulSetInterruptMaskFromISR:\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+vClearInterruptMaskFromISR:\r
+ msr PRIMASK, r0\r
+ bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+PendSV_Handler:\r
+ mrs r0, psp /* Read PSP in r0. */\r
+#if ( configENABLE_FPU == 1 )\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vstmdbeq r0!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
+#endif /* configENABLE_FPU */\r
+#if ( configENABLE_MPU == 1 )\r
+ mrs r1, psplim /* r1 = PSPLIM. */\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
+#else /* configENABLE_MPU */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */\r
+#endif /* configENABLE_MPU */\r
+\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ str r0, [r1] /* Save the new top of stack in TCB. */\r
+\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
+\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r3, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r3, #4 /* r3 = 4. */\r
+ str r3, [r2] /* Program RNR = 4. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_MPU == 1 )\r
+ ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
+#else /* configENABLE_MPU */\r
+ ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
+#endif /* configENABLE_MPU */\r
+\r
+#if ( configENABLE_FPU == 1 )\r
+ tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vldmiaeq r0!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
+#endif /* configENABLE_FPU */\r
+\r
+ #if ( configENABLE_MPU == 1 )\r
+ msr psplim, r1 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r2 /* Restore the CONTROL register value for the task. */\r
+#else /* configENABLE_MPU */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+#endif /* configENABLE_MPU */\r
+ msr psp, r0 /* Remember the new top of stack for the task. */\r
+ bx r3\r
+/*-----------------------------------------------------------*/\r
+\r
+SVC_Handler:\r
+ tst lr, #4\r
+ ite eq\r
+ mrseq r0, msp\r
+ mrsne r0, psp\r
+ b vPortSVCHandler_C\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portPRIVILEGED_RAM_REGION ( 2UL )\r
+#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Devices Region. */\r
+#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
+#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
*/\r
static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
\r
-/*\r
- * Checks to see if being called from the context of an unprivileged task, and\r
- * if so raises the privilege level and returns false - otherwise does nothing\r
- * other than return true.\r
- */\r
-extern BaseType_t xPortRaisePrivilege( void );\r
-\r
/*\r
* Setup the timer to generate the tick interrupts. The implementation in this\r
* file is weak to allow application writers to change the timer used to\r
*/\r
extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;\r
\r
+/**\r
+ * @brief Calls the port specific code to raise the privilege.\r
+ *\r
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.\r
+ */\r
+extern BaseType_t xPortRaisePrivilege( void );\r
+\r
+/**\r
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific\r
+ * code to reset the privilege, otherwise does nothing.\r
+ */\r
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );\r
/*-----------------------------------------------------------*/\r
\r
/* Each task maintains its own interrupt status in the critical nesting\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortResetPrivilege( BaseType_t xRunningPrivileged )\r
-{\r
- if( xRunningPrivileged != pdTRUE )\r
- {\r
- __asm volatile ( " mrs r0, control \n" \\r
- " orr r0, r0, #1 \n" \\r
- " msr control, r0 \n" \\r
- :::"r0", "memory" );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
{\r
extern uint32_t __SRAM_segment_start__[];\r
PUBLIC vPortStartFirstTask\r
PUBLIC vPortEnableVFP\r
PUBLIC vPortRestoreContextOfFirstTask\r
- PUBLIC xPortRaisePrivilege\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
\r
/*-----------------------------------------------------------*/\r
\r
\r
/*-----------------------------------------------------------*/\r
\r
-vPortStartFirstTask\r
+vPortStartFirstTask:\r
/* Use the NVIC offset register to locate the stack. */\r
ldr r0, =0xE000ED08\r
ldr r0, [r0]\r
\r
/*-----------------------------------------------------------*/\r
\r
-vPortRestoreContextOfFirstTask\r
+vPortRestoreContextOfFirstTask:\r
/* Use the NVIC offset register to locate the stack. */\r
ldr r0, =0xE000ED08\r
ldr r0, [r0]\r
\r
/*-----------------------------------------------------------*/\r
\r
-vPortEnableVFP\r
+vPortEnableVFP:\r
/* The FPU enable bits are in the CPACR. */\r
ldr.w r0, =0xE000ED88\r
ldr r1, [r0]\r
\r
/*-----------------------------------------------------------*/\r
\r
-xPortRaisePrivilege\r
- mrs r0, control\r
- /* Is the task running privileged? */\r
- tst r0, #1\r
- itte ne\r
- /* CONTROL[0]!=0, return false. */\r
- movne r0, #0\r
- /* Switch to privileged. */\r
- svcne 2 /* 2 == portSVC_RAISE_PRIVILEGE */\r
- /* CONTROL[0]==0, return true. */\r
- moveq r0, #1\r
- bx lr\r
+xIsPrivileged:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ bx lr /* Return. */\r
+/*-----------------------------------------------------------*/\r
\r
+vResetPrivilege:\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orr r0, r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
+/*-----------------------------------------------------------*/\r
\r
END\r
-\r
\r
/* portNOP() is not required by this port. */\r
#define portNOP()\r
+/*-----------------------------------------------------------*/\r
\r
+extern BaseType_t xIsPrivileged( void );\r
+extern void vResetPrivilege( void );\r
\r
-/* Set the privilege level to user mode if xRunningPrivileged is false. */\r
-void vPortResetPrivilege( BaseType_t xRunningPrivileged );\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+#define portIS_PRIVILEGED() xIsPrivileged()\r
\r
+/**\r
+ * @brief Raise an SVC request to raise privilege.\r
+*/\r
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+#define portRESET_PRIVILEGE() vResetPrivilege()\r
/*-----------------------------------------------------------*/\r
\r
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\r
*/\r
static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
\r
-/*\r
- * Checks to see if being called from the context of an unprivileged task, and\r
- * if so raises the privilege level and returns false - otherwise does nothing\r
- * other than return true.\r
- */\r
-BaseType_t xPortRaisePrivilege( void );\r
-\r
/*\r
* Standard FreeRTOS exception handlers.\r
*/\r
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;\r
#endif /* configASSERT_DEFINED */\r
\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+BaseType_t xIsPrivileged( void );\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ *\r
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
+ * Bit[0] = 0 --> The processor is running privileged\r
+ * Bit[0] = 1 --> The processor is running unprivileged.\r
+ */\r
+void vResetPrivilege( void );\r
+\r
+/**\r
+ * @brief Calls the port specific code to raise the privilege.\r
+ *\r
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.\r
+ */\r
+extern BaseType_t xPortRaisePrivilege( void );\r
+\r
+/**\r
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific\r
+ * code to reset the privilege, otherwise does nothing.\r
+ */\r
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );\r
/*-----------------------------------------------------------*/\r
\r
/*\r
}\r
/*-----------------------------------------------------------*/\r
\r
-__asm BaseType_t xPortRaisePrivilege( void )\r
+__asm BaseType_t xIsPrivileged( void )\r
{\r
- mrs r0, control\r
- tst r0, #1 /* Is the task running privileged? */\r
- itte ne\r
- movne r0, #0 /* CONTROL[0]!=0, return false. */\r
- svcne portSVC_RAISE_PRIVILEGE /* Switch to privileged. */\r
- moveq r0, #1 /* CONTROL[0]==0, return true. */\r
- bx lr\r
+ PRESERVE8\r
+\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ bx lr /* Return. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void vResetPrivilege( void )\r
+{\r
+ PRESERVE8\r
+\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orrs r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return. */\r
}\r
/*-----------------------------------------------------------*/\r
\r
#define portPRIVILEGED_RAM_REGION ( 2UL )\r
#define portGENERAL_PERIPHERALS_REGION ( 3UL )\r
#define portSTACK_REGION ( 4UL )\r
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
#ifndef portFORCE_INLINE\r
#define portFORCE_INLINE __forceinline\r
#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+extern BaseType_t xIsPrivileged( void );\r
+extern void vResetPrivilege( void );\r
+\r
+/**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+#define portIS_PRIVILEGED() xIsPrivileged()\r
\r
+/**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ */\r
+#define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE }\r
+\r
+/**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+#define portRESET_PRIVILEGE() vResetPrivilege()\r
/*-----------------------------------------------------------*/\r
\r
static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* Set the privilege level to user mode if xRunningPrivileged is false. */\r
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )\r
-{\r
-uint32_t ulReg;\r
-\r
- if( xRunningPrivileged != pdTRUE )\r
- {\r
- __asm\r
- {\r
- mrs ulReg, control\r
- orr ulReg, #1\r
- msr control, ulReg\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-\r
#ifdef __cplusplus\r
}\r
#endif\r
\r
#endif /* PORTMACRO_H */\r
-\r
the top of stack variable is updated. */\r
#if( portUSING_MPU_WRAPPERS == 1 )\r
{\r
- pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );\r
+ /* If the port has capability to detect stack overflow,\r
+ pass the stack end address to the stack initialization\r
+ function as well. */\r
+ #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )\r
+ {\r
+ #if( portSTACK_GROWTH < 0 )\r
+ {\r
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );\r
+ }\r
+ #else /* portSTACK_GROWTH */\r
+ {\r
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );\r
+ }\r
+ #endif /* portSTACK_GROWTH */\r
+ }\r
+ #else /* portHAS_STACK_OVERFLOW_CHECKING */\r
+ {\r
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );\r
+ }\r
+ #endif /* portHAS_STACK_OVERFLOW_CHECKING */\r
}\r
#else /* portUSING_MPU_WRAPPERS */\r
{\r
- pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );\r
+ /* If the port has capability to detect stack overflow,\r
+ pass the stack end address to the stack initialization\r
+ function as well. */\r
+ #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )\r
+ {\r
+ #if( portSTACK_GROWTH < 0 )\r
+ {\r
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );\r
+ }\r
+ #else /* portSTACK_GROWTH */\r
+ {\r
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );\r
+ }\r
+ #endif /* portSTACK_GROWTH */\r
+ }\r
+ #else /* portHAS_STACK_OVERFLOW_CHECKING */\r
+ {\r
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );\r
+ }\r
+ #endif /* portHAS_STACK_OVERFLOW_CHECKING */\r
}\r
#endif /* portUSING_MPU_WRAPPERS */\r
\r
/* In case a task that has a secure context deletes itself, in which case\r
the idle task is responsible for deleting the task's secure context, if\r
any. */\r
- portTASK_CALLS_SECURE_FUNCTIONS();\r
+ portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );\r
\r
for( ;; )\r
{\r
projects / freertos / commitdiff