--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_hal.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains all the functions prototypes for the HAL\r
+ * module driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_HAL_H\r
+#define __STM32L1xx_HAL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_hal_conf.h"\r
+\r
+/** @addtogroup STM32L1xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HAL\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Exported_Constants HAL Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_TICK_FREQ Tick Frequency\r
+ * @{\r
+ */\r
+#define HAL_TICK_FREQ_10HZ 100U\r
+#define HAL_TICK_FREQ_100HZ 10U\r
+#define HAL_TICK_FREQ_1KHZ 1U\r
+#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ\r
+\r
+#define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ) || \\r
+ ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \\r
+ ((__FREQ__) == HAL_TICK_FREQ_1KHZ))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG_BootMode Boot Mode\r
+ * @{\r
+ */\r
+\r
+#define SYSCFG_BOOT_MAINFLASH (0x00000000U)\r
+#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)\r
+#if defined(FSMC_R_BASE)\r
+#define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)\r
+#endif /* FSMC_R_BASE */\r
+#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Constants RI: Routing Interface\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RI_InputCapture Input Capture\r
+ * @{\r
+ */\r
+\r
+#define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */\r
+#define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */\r
+#define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */\r
+#define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Select TIM Select\r
+ * @{\r
+ */\r
+\r
+#define TIM_SELECT_NONE (0x00000000U) /*!< None selected */\r
+#define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */\r
+#define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */\r
+#define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */\r
+\r
+#define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \\r
+ ((__TIM__) == TIM_SELECT_TIM2) || \\r
+ ((__TIM__) == TIM_SELECT_TIM3) || \\r
+ ((__TIM__) == TIM_SELECT_TIM4))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_InputCaptureRouting Input Capture Routing\r
+ * @{\r
+ */\r
+ /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */\r
+#define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */\r
+#define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */\r
+#define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */\r
+#define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */\r
+#define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */\r
+#define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */\r
+#define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */\r
+#define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */\r
+#define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */\r
+#define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */\r
+#define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */\r
+#define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */\r
+#define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */\r
+#define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */\r
+#define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */\r
+#define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */\r
+\r
+#define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \\r
+ ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_IOSwitch IO Switch\r
+ * @{\r
+ */\r
+#define RI_ASCR1_REGISTER (0x80000000U)\r
+/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */\r
+#define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)\r
+#define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)\r
+#define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2)\r
+#define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3)\r
+#define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4)\r
+#define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5)\r
+#define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6)\r
+#define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7)\r
+#define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8)\r
+#define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9)\r
+#define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10)\r
+#define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11)\r
+#define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12)\r
+#define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13)\r
+#define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14)\r
+#define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15)\r
+#define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18)\r
+#define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19)\r
+#define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20)\r
+#define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21)\r
+#define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22)\r
+#define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23)\r
+#define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24)\r
+#define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25)\r
+#define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */\r
+#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */\r
+#define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27)\r
+#define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28)\r
+#define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29)\r
+#define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30)\r
+#define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31)\r
+#endif /* RI_ASCR2_CH1b */\r
+\r
+/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */\r
+#define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1)\r
+#define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2)\r
+#define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3)\r
+#define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4)\r
+#define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1)\r
+#define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2)\r
+#define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1)\r
+#define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2)\r
+#define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3)\r
+#define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1)\r
+#define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2)\r
+#define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3)\r
+#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */\r
+#define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b)\r
+#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */\r
+#define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b)\r
+#define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b)\r
+#define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b)\r
+#define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b)\r
+#define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b)\r
+#define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b)\r
+#define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b)\r
+#define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b)\r
+#define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b)\r
+#define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b)\r
+#endif /* RI_ASCR2_CH1b */\r
+#define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3)\r
+#define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4)\r
+#endif /* RI_ASCR2_CH0b */\r
+\r
+\r
+#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */\r
+\r
+#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH12b))\r
+\r
+#else /* !RI_ASCR2_CH1b */\r
+\r
+#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */\r
+\r
+#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b))\r
+\r
+#else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */\r
+\r
+#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \\r
+ ((__IOSWITCH__) == RI_IOSWITCH_GR4_3))\r
+\r
+#endif /* RI_ASCR2_CH0b */\r
+#endif /* RI_ASCR2_CH1b */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Pin PIN define\r
+ * @{\r
+ */\r
+#define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
+#define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
+#define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
+#define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
+#define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
+#define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
+#define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
+#define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
+#define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
+#define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
+#define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
+#define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
+#define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
+#define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
+#define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
+#define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
+#define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */\r
+\r
+#define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Exported_Macros HAL Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU_Macros DBGMCU: Debug MCU\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode\r
+ * @brief Freeze/Unfreeze Peripherals in Debug mode\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief TIM2 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM3 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM4 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM5 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM6 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM7 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief RTC Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)\r
+#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief WWDG Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)\r
+#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief IWDG Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)\r
+#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief I2C1 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)\r
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)\r
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)\r
+#endif\r
+\r
+/**\r
+ * @brief I2C2 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)\r
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)\r
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM9 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM10 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)\r
+#endif\r
+\r
+/**\r
+ * @brief TIM11 Peripherals Debug mode\r
+ */\r
+#if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP)\r
+#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)\r
+#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)\r
+#endif\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG_VrefInt VREFINT configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the output of internal reference voltage\r
+ * (VrefInt) on I/O pin.\r
+ * @note The VrefInt output can be routed to any I/O in group 3:\r
+ * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).\r
+ * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).\r
+ * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),\r
+ * CH1b (PF11) or CH2b (PF12).\r
+ * Note: Comparator peripheral clock must be preliminarily enabled,\r
+ * either in COMP user function "HAL_COMP_MspInit()" (should be\r
+ * done if comparators are used) or by direct clock enable:\r
+ * Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()".\r
+ * Note: In addition with this macro, VrefInt output buffer must be\r
+ * connected to the selected I/O pin. Refer to macro\r
+ * "__HAL_RI_IOSWITCH_CLOSE()".\r
+ * @note VrefInt output enable: Internal reference voltage connected to I/O group 3\r
+ * VrefInt output disable: Internal reference voltage disconnected from I/O group 3\r
+ * @retval None\r
+ */\r
+#define __HAL_SYSCFG_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)\r
+#define __HAL_SYSCFG_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Main Flash memory mapped at 0x00000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)\r
+\r
+/** @brief System Flash memory mapped at 0x00000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)\r
+\r
+/** @brief Embedded SRAM mapped at 0x00000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1)\r
+\r
+#if defined(FSMC_R_BASE)\r
+/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)\r
+\r
+#endif /* FSMC_R_BASE */\r
+\r
+/**\r
+ * @brief Returns the boot mode as configured by user.\r
+ * @retval The boot mode as configured by user. The returned value can be one\r
+ * of the following values:\r
+ * @arg SYSCFG_BOOT_MAINFLASH\r
+ * @arg SYSCFG_BOOT_SYSTEMFLASH\r
+ * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD)\r
+ * @arg SYSCFG_BOOT_SRAM\r
+ */\r
+#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_USBConfig USB DP line Configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Control the internal pull-up on USB DP line.\r
+ */\r
+#define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)\r
+\r
+#define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_Macris RI: Routing Interface\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RI_InputCaputureConfig Input Capture configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin.\r
+ * @param __TIMSELECT__ Timer select.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.\r
+ * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.\r
+ * @param __INPUT__ selects which pin to be routed to Input Capture.\r
+ * This parameter must be a value of @ref RI_InputCaptureRouting\r
+ * e.g.\r
+ * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1)\r
+ * allows routing of Input capture IC1 of TIM2 to PA4.\r
+ * For details about correspondence between RI_INPUTCAPTUREROUTING_x\r
+ * and I/O pins refer to the parameters' description in the header file\r
+ * or refer to the product reference manual.\r
+ * @note Input capture selection bits are not reset by this function.\r
+ * To reset input capture selection bits, use SYSCFG_RIDeInit() function.\r
+ * @note The I/O should be configured in alternate function mode (AF14) using\r
+ * GPIO_PinAFConfig() function.\r
+ * @retval None.\r
+ */\r
+#define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \\r
+ do {assert_param(IS_RI_TIM(__TIMSELECT__)); \\r
+ assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \\r
+ SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \\r
+ }while(0)\r
+\r
+/**\r
+ * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin.\r
+ * @param __TIMSELECT__ Timer select.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.\r
+ * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.\r
+ * @param __INPUT__ selects which pin to be routed to Input Capture.\r
+ * This parameter must be a value of @ref RI_InputCaptureRouting\r
+ * @retval None.\r
+ */\r
+#define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \\r
+ do {assert_param(IS_RI_TIM(__TIMSELECT__)); \\r
+ assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \\r
+ SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \\r
+ }while(0)\r
+\r
+/**\r
+ * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin.\r
+ * @param __TIMSELECT__ Timer select.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.\r
+ * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.\r
+ * @param __INPUT__ selects which pin to be routed to Input Capture.\r
+ * This parameter must be a value of @ref RI_InputCaptureRouting\r
+ * @retval None.\r
+ */\r
+#define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \\r
+ do {assert_param(IS_RI_TIM(__TIMSELECT__)); \\r
+ assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \\r
+ SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \\r
+ }while(0)\r
+\r
+/**\r
+ * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin.\r
+ * @param __TIMSELECT__ Timer select.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.\r
+ * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.\r
+ * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.\r
+ * @param __INPUT__ selects which pin to be routed to Input Capture.\r
+ * This parameter must be a value of @ref RI_InputCaptureRouting\r
+ * @retval None.\r
+ */\r
+#define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \\r
+ do {assert_param(IS_RI_TIM(__TIMSELECT__)); \\r
+ assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \\r
+ SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \\r
+ MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \\r
+ }while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_SwitchControlConfig Switch Control configuration\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable or disable the switch control mode.\r
+ * @note ENABLE: ADC analog switches closed if the corresponding\r
+ * I/O switch is also closed.\r
+ * When using COMP1, switch control mode must be enabled.\r
+ * @note DISABLE: ADC analog switches open or controlled by the ADC interface.\r
+ * When using the ADC for acquisition, switch control mode\r
+ * must be disabled.\r
+ * @note COMP1 comparator and ADC cannot be used at the same time since\r
+ * they share the ADC switch matrix.\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM)\r
+\r
+#define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)\r
+\r
+/*\r
+ * @brief Close or Open the routing interface Input Output switches.\r
+ * @param __IOSWITCH__ selects the I/O analog switch number.\r
+ * This parameter must be a value of @ref RI_IOSwitch\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \\r
+ if ((__IOSWITCH__) >> 31 != 0 ) \\r
+ { \\r
+ SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \\r
+ } \\r
+ else \\r
+ { \\r
+ SET_BIT(RI->ASCR2, (__IOSWITCH__)); \\r
+ } \\r
+ }while(0)\r
+\r
+#define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \\r
+ if ((__IOSWITCH__) >> 31 != 0 ) \\r
+ { \\r
+ CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \\r
+ } \\r
+ }while(0)\r
+\r
+#if defined (COMP_CSR_SW1)\r
+/**\r
+ * @brief Close or open the internal switch COMP1_SW1.\r
+ * This switch connects I/O pin PC3 (can be used as ADC channel 13)\r
+ * and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel\r
+ * 26) and COMP1 non-inverting input.\r
+ * Pin PC3 connection depends on another switch setting, refer to\r
+ * macro "__HAL_ADC_CHANNEL_SPEED_FAST()".\r
+ * @retval None.\r
+ */\r
+#define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1)\r
+\r
+#define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1)\r
+#endif /* COMP_CSR_SW1 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RI_HystConfig Hysteresis Activation and Deactivation\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR1, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports B\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports C\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR2, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports D\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \\r
+ } while(0)\r
+\r
+#if defined (GPIOE_BASE)\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports E\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR3, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+#endif /* GPIOE_BASE */\r
+\r
+#if defined(GPIOF_BASE) || defined(GPIOG_BASE)\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports F\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Enable or disable Hysteresis of the input schmitt triger of Ports G\r
+ * When the I/Os are programmed in input mode by standard I/O port\r
+ * registers, the Schmitt trigger and the hysteresis are enabled by default.\r
+ * When hysteresis is disabled, it is possible to read the\r
+ * corresponding port with a trigger level of VDDIO/2.\r
+ * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.\r
+ * This parameter must be a value of @ref RI_Pin\r
+ * @retval None\r
+ */\r
+#define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+#define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \\r
+ SET_BIT(RI->HYSCR4, (__IOPIN__)); \\r
+ } while(0)\r
+\r
+#endif /* GPIOF_BASE || GPIOG_BASE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported variables --------------------------------------------------------*/\r
+/** @defgroup HAL_Exported_Variables HAL Exported Variables\r
+ * @{\r
+ */\r
+extern __IO uint32_t uwTick;\r
+extern uint32_t uwTickPrio;\r
+extern uint32_t uwTickFreq;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup HAL_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HAL_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ******************************/\r
+HAL_StatusTypeDef HAL_Init(void);\r
+HAL_StatusTypeDef HAL_DeInit(void);\r
+void HAL_MspInit(void);\r
+void HAL_MspDeInit(void);\r
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HAL_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control functions ************************************************/\r
+void HAL_IncTick(void);\r
+void HAL_Delay(uint32_t Delay);\r
+uint32_t HAL_GetTick(void);\r
+uint32_t HAL_GetTickPrio(void);\r
+HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);\r
+uint32_t HAL_GetTickFreq(void);\r
+void HAL_SuspendTick(void);\r
+void HAL_ResumeTick(void);\r
+uint32_t HAL_GetHalVersion(void);\r
+uint32_t HAL_GetREVID(void);\r
+uint32_t HAL_GetDEVID(void);\r
+uint32_t HAL_GetUIDw0(void);\r
+uint32_t HAL_GetUIDw1(void);\r
+uint32_t HAL_GetUIDw2(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup HAL_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+\r
+/* DBGMCU Peripheral Control functions *****************************************/\r
+void HAL_DBGMCU_EnableDBGSleepMode(void);\r
+void HAL_DBGMCU_DisableDBGSleepMode(void);\r
+void HAL_DBGMCU_EnableDBGStopMode(void);\r
+void HAL_DBGMCU_DisableDBGStopMode(void);\r
+void HAL_DBGMCU_EnableDBGStandbyMode(void);\r
+void HAL_DBGMCU_DisableDBGStandbyMode(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_HAL_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff