Add PIC32MEC14xx port and demo application.

[freertos] / FreeRTOS / Demo / PIC32MEC14xx_MPLAB / src / MEC14xx / interrupts / girq10.c

diff --git a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq10.c b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq10.c
new file mode 100644 (file)
index 0000000..6716bed
--- /dev/null
+++ b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq10.c
@@ -0,0 +1,197 @@
+/*****************************************************************************\r
+* Copyright 2014 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+*****************************************************************************/\r
+\r
+/** @file girq10.c\r
+ *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+ */\r
+/** @defgroup MEC14xx ISR\r
+ *  @{\r
+ */\r
+\r
+\r
+#include "appcfg.h"\r
+#include "platform.h"\r
+#include "MEC14xx/mec14xx.h"\r
+#include "MEC14xx/mec14xx_girqs.h"\r
+#include "MEC14xx/mec14xx_gpio.h"\r
+#include "MEC14xx/mec14xx_trace_func.h"\r
+\r
+\r
+#if GIRQ10_DISAGG == 0\r
+\r
+void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+girq10_isr(void)\r
+{\r
+    JTVIC_GROUP_EN_CLR->w = (1ul<<2);\r
+}\r
+\r
+#else\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b0(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 0, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b1(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 1, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b2(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 2, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b3(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 3, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b4(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 4, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b5(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 5, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b6(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 6, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b7(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 7, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b8(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 8, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b9(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 9, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b10(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 10, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b11(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 11, JTVIC_CLR_SRC);\r
+}\r
+\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b12(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 12, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b13(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 13, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b14(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 14, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b15(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 15, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b16(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 16, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b17(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 17, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b18(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 18, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b19(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 19, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b20(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 20, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b21(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 21, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b22(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 22, JTVIC_CLR_SRC);\r
+}\r
+\r
+void __attribute__((weak, interrupt, nomips16))\r
+girq10_b23(void)\r
+{\r
+    jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 23, JTVIC_CLR_SRC);\r
+}\r
+\r
+#endif\r
+\r
+/* end girq10.c */\r
+/**   @}\r
+ */\r
+\r