--- /dev/null
+Disassembly Listing for PIC32MEC14xx_RTOSDemo
+Generated From:
+C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/dist/default/debug/PIC32MEC14xx_RTOSDemo.X.debug.elf
+15-Jul-2015 17:16:07
+
+--- c:/e/dev/freertos/workingcopy/freertos/source/timers.c --------------------------------------------
+1: /*\r
+2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+3: All rights reserved\r
+4: \r
+5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+6: \r
+7: This file is part of the FreeRTOS distribution.\r
+8: \r
+9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
+10: the terms of the GNU General Public License (version 2) as published by the\r
+11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+12: \r
+13: ***************************************************************************\r
+14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+15: >>! distribute a combined work that includes FreeRTOS without being !<<\r
+16: >>! obliged to provide the source code for proprietary components !<<\r
+17: >>! outside of the FreeRTOS kernel. !<<\r
+18: ***************************************************************************\r
+19: \r
+20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+22: FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+23: link: http://www.freertos.org/a00114.html\r
+24: \r
+25: ***************************************************************************\r
+26: * *\r
+27: * FreeRTOS provides completely free yet professionally developed, *\r
+28: * robust, strictly quality controlled, supported, and cross *\r
+29: * platform software that is more than just the market leader, it *\r
+30: * is the industry's de facto standard. *\r
+31: * *\r
+32: * Help yourself get started quickly while simultaneously helping *\r
+33: * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+34: * tutorial book, reference manual, or both: *\r
+35: * http://www.FreeRTOS.org/Documentation *\r
+36: * *\r
+37: ***************************************************************************\r
+38: \r
+39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+40: the FAQ page "My application does not run, what could be wrong?". Have you\r
+41: defined configASSERT()?\r
+42: \r
+43: http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+44: embedded software for free we request you assist our global community by\r
+45: participating in the support forum.\r
+46: \r
+47: http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+48: be as productive as possible as early as possible. Now you can receive\r
+49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+50: Ltd, and the world's leading authority on the world's leading RTOS.\r
+51: \r
+52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+54: compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+55: \r
+56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+58: \r
+59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+61: licenses offer ticketed support, indemnification and commercial middleware.\r
+62: \r
+63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+64: engineered and independently SIL3 certified version for use in safety and\r
+65: mission critical applications that require provable dependability.\r
+66: \r
+67: 1 tab == 4 spaces!\r
+68: */\r
+69: \r
+70: /* Standard includes. */\r
+71: #include <stdlib.h>\r
+72: \r
+73: /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+74: all the API functions to use the MPU wrappers. That should only be done when\r
+75: task.h is included from an application file. */\r
+76: #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+77: \r
+78: #include "FreeRTOS.h"\r
+79: #include "task.h"\r
+80: #include "queue.h"\r
+81: #include "timers.h"\r
+82: \r
+83: #if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )\r
+84: #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.\r
+85: #endif\r
+86: \r
+87: /* Lint e961 and e750 are suppressed as a MISRA exception justified because the\r
+88: MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the\r
+89: header files above, but not in this file, in order to generate the correct\r
+90: privileged Vs unprivileged linkage and placement. */\r
+91: #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */\r
+92: \r
+93: \r
+94: /* This entire source file will be skipped if the application is not configured\r
+95: to include software timer functionality. This #if is closed at the very bottom\r
+96: of this file. If you want to include software timer functionality then ensure\r
+97: configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\r
+98: #if ( configUSE_TIMERS == 1 )\r
+99: \r
+100: /* Misc definitions. */\r
+101: #define tmrNO_DELAY ( TickType_t ) 0U\r
+102: \r
+103: /* The definition of the timers themselves. */\r
+104: typedef struct tmrTimerControl\r
+105: {\r
+106: const char *pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r
+107: ListItem_t xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */\r
+108: TickType_t xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */\r
+109: UBaseType_t uxAutoReload; /*<< Set to pdTRUE if the timer should be automatically restarted once expired. Set to pdFALSE if the timer is, in effect, a one-shot timer. */\r
+110: void *pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */\r
+111: TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */\r
+112: #if( configUSE_TRACE_FACILITY == 1 )\r
+113: UBaseType_t uxTimerNumber; /*<< An ID assigned by trace tools such as FreeRTOS+Trace */\r
+114: #endif\r
+115: } xTIMER;\r
+116: \r
+117: /* The old xTIMER name is maintained above then typedefed to the new Timer_t\r
+118: name below to enable the use of older kernel aware debuggers. */\r
+119: typedef xTIMER Timer_t;\r
+120: \r
+121: /* The definition of messages that can be sent and received on the timer queue.\r
+122: Two types of message can be queued - messages that manipulate a software timer,\r
+123: and messages that request the execution of a non-timer related callback. The\r
+124: two message types are defined in two separate structures, xTimerParametersType\r
+125: and xCallbackParametersType respectively. */\r
+126: typedef struct tmrTimerParameters\r
+127: {\r
+128: TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */\r
+129: Timer_t * pxTimer; /*<< The timer to which the command will be applied. */\r
+130: } TimerParameter_t;\r
+131: \r
+132: \r
+133: typedef struct tmrCallbackParameters\r
+134: {\r
+135: PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */\r
+136: void *pvParameter1; /* << The value that will be used as the callback functions first parameter. */\r
+137: uint32_t ulParameter2; /* << The value that will be used as the callback functions second parameter. */\r
+138: } CallbackParameters_t;\r
+139: \r
+140: /* The structure that contains the two message types, along with an identifier\r
+141: that is used to determine which message type is valid. */\r
+142: typedef struct tmrTimerQueueMessage\r
+143: {\r
+144: BaseType_t xMessageID; /*<< The command being sent to the timer service task. */\r
+145: union\r
+146: {\r
+147: TimerParameter_t xTimerParameters;\r
+148: \r
+149: /* Don't include xCallbackParameters if it is not going to be used as\r
+150: it makes the structure (and therefore the timer queue) larger. */\r
+151: #if ( INCLUDE_xTimerPendFunctionCall == 1 )\r
+152: CallbackParameters_t xCallbackParameters;\r
+153: #endif /* INCLUDE_xTimerPendFunctionCall */\r
+154: } u;\r
+155: } DaemonTaskMessage_t;\r
+156: \r
+157: /*lint -e956 A manual analysis and inspection has been used to determine which\r
+158: static variables must be declared volatile. */\r
+159: \r
+160: /* The list in which active timers are stored. Timers are referenced in expire\r
+161: time order, with the nearest expiry time at the front of the list. Only the\r
+162: timer service task is allowed to access these lists. */\r
+163: PRIVILEGED_DATA static List_t xActiveTimerList1;\r
+164: PRIVILEGED_DATA static List_t xActiveTimerList2;\r
+165: PRIVILEGED_DATA static List_t *pxCurrentTimerList;\r
+166: PRIVILEGED_DATA static List_t *pxOverflowTimerList;\r
+167: \r
+168: /* A queue that is used to send commands to the timer service task. */\r
+169: PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;\r
+170: \r
+171: #if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r
+172: \r
+173: PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;\r
+174: \r
+175: #endif\r
+176: \r
+177: /*lint +e956 */\r
+178: \r
+179: /*-----------------------------------------------------------*/\r
+180: \r
+181: /*\r
+182: * Initialise the infrastructure used by the timer service task if it has not\r
+183: * been initialised already.\r
+184: */\r
+185: static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;\r
+186: \r
+187: /*\r
+188: * The timer service task (daemon). Timer functionality is controlled by this\r
+189: * task. Other tasks communicate with the timer service task using the\r
+190: * xTimerQueue queue.\r
+191: */\r
+192: static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;\r
+193: \r
+194: /*\r
+195: * Called by the timer service task to interpret and process a command it\r
+196: * received on the timer queue.\r
+197: */\r
+198: static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;\r
+199: \r
+200: /*\r
+201: * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,\r
+202: * depending on if the expire time causes a timer counter overflow.\r
+203: */\r
+204: static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;\r
+205: \r
+206: /*\r
+207: * An active timer has reached its expire time. Reload the timer if it is an\r
+208: * auto reload timer, then call its callback.\r
+209: */\r
+210: static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;\r
+211: \r
+212: /*\r
+213: * The tick count has overflowed. Switch the timer lists after ensuring the\r
+214: * current timer list does not still reference some timers.\r
+215: */\r
+216: static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;\r
+217: \r
+218: /*\r
+219: * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE\r
+220: * if a tick count overflow occurred since prvSampleTimeNow() was last called.\r
+221: */\r
+222: static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;\r
+223: \r
+224: /*\r
+225: * If the timer list contains any active timers then return the expire time of\r
+226: * the timer that will expire first and set *pxListWasEmpty to false. If the\r
+227: * timer list does not contain any timers then return 0 and set *pxListWasEmpty\r
+228: * to pdTRUE.\r
+229: */\r
+230: static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;\r
+231: \r
+232: /*\r
+233: * If a timer has expired, process it. Otherwise, block the timer service task\r
+234: * until either a timer does expire or a command is received.\r
+235: */\r
+236: static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;\r
+237: \r
+238: /*-----------------------------------------------------------*/\r
+239: \r
+240: BaseType_t xTimerCreateTimerTask( void )\r
+241: {\r
+BFD07A6C 4FE9 ADDIU SP, SP, -48
+BFD07A6E CBEB SW RA, 44(SP)
+BFD07A70 CBCA SW S8, 40(SP)
+BFD07A72 0FDD MOVE S8, SP
+242: BaseType_t xReturn = pdFAIL;\r
+BFD07A74 0020F81E SW ZERO, 32(S8)
+243: \r
+244: /* This function is called when the scheduler is started if\r
+245: configUSE_TIMERS is set to 1. Check that the infrastructure used by the\r
+246: timer service task has been created/initialised. If timers have already\r
+247: been created then the initialisation will already have been performed. */\r
+248: prvCheckForValidListAndQueue();\r
+BFD07A78 35F477E8 JALS prvCheckForValidListAndQueue
+BFD07A7A 0C0035F4 LHU T7, 3072(S4)
+BFD07A7C 0C00 NOP
+249: \r
+250: if( xTimerQueue != NULL )\r
+BFD07A7E 8068FC5C LW V0, -32664(GP)
+BFD07A82 001540E2 BEQZC V0, 0xBFD07AB0
+251: {\r
+252: #if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r
+253: {\r
+254: /* Create the timer task, storing its handle in xTimerTaskHandle so\r
+255: it can be returned by the xTimerGetTimerDaemonTaskHandle() function. */\r
+256: xReturn = xTaskCreate( prvTimerTask, "Tmr Svc", ( uint16_t ) configTIMER_TASK_STACK_DEPTH, NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, &xTimerTaskHandle );\r
+257: }\r
+258: #else\r
+259: {\r
+260: /* Create the timer task without storing its handle. */\r
+261: xReturn = xTaskCreate( prvTimerTask, "Tmr Svc", ( uint16_t ) configTIMER_TASK_STACK_DEPTH, NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, NULL);\r
+BFD07A86 ED02 LI V0, 2
+BFD07A88 C844 SW V0, 16(SP)
+BFD07A8A C805 SW ZERO, 20(SP)
+BFD07A8C C806 SW ZERO, 24(SP)
+BFD07A8E C807 SW ZERO, 28(SP)
+BFD07A90 BFD141A2 LUI V0, 0xBFD1
+BFD07A92 3082BFD1 LDC1 F30, 12418(S1)
+BFD07A94 97393082 ADDIU A0, V0, -26823
+BFD07A96 41A29739 BEQ T9, T9, 0xBFD0FDDE
+BFD07A98 BFD141A2 LUI V0, 0xBFD1
+BFD07A9A 30A2BFD1 LDC1 F30, 12450(S1)
+BFD07A9C 9AE030A2 ADDIU A1, V0, -25888
+BFD07A9E 30C09AE0 SWC1 F23, 12480(ZERO)
+BFD07AA0 017C30C0 ADDIU A2, ZERO, 380
+BFD07AA4 0CE0 MOVE A3, ZERO
+BFD07AA6 0A9A77E8 JALS xTaskGenericCreate
+BFD07AA8 0A9A LBU A1, 10(S1)
+BFD07AAA 0C00 NOP
+BFD07AAC 0020F85E SW V0, 32(S8)
+262: }\r
+263: #endif\r
+264: }\r
+265: else\r
+266: {\r
+267: mtCOVERAGE_TEST_MARKER();\r
+268: }\r
+269: \r
+270: configASSERT( xReturn );\r
+BFD07AB0 0020FC5E LW V0, 32(S8)
+BFD07AB4 000940A2 BNEZC V0, 0xBFD07ACA
+BFD07AB8 BFD141A2 LUI V0, 0xBFD1
+BFD07ABA 3082BFD1 LDC1 F30, 12418(S1)
+BFD07ABC 9AE83082 ADDIU A0, V0, -25880
+BFD07ABE 30A09AE8 SWC1 F23, 12448(T0)
+BFD07AC0 010E30A0 ADDIU A1, ZERO, 270
+BFD07AC4 4B7E77E8 JALS vAssertCalled
+BFD07AC6 4B7E LW K1, 120(SP)
+BFD07AC8 0C00 NOP
+271: return xReturn;\r
+BFD07ACA 0020FC5E LW V0, 32(S8)
+272: }\r
+BFD07ACE 0FBE MOVE SP, S8
+BFD07AD0 4BEB LW RA, 44(SP)
+BFD07AD2 4BCA LW S8, 40(SP)
+BFD07AD4 4C19 ADDIU SP, SP, 48
+BFD07AD6 459F JR16 RA
+BFD07AD8 0C00 NOP
+273: /*-----------------------------------------------------------*/\r
+274: \r
+275: TimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r
+276: {\r
+BFD061D8 4FF1 ADDIU SP, SP, -32
+BFD061DA CBE7 SW RA, 28(SP)
+BFD061DC CBC6 SW S8, 24(SP)
+BFD061DE 0FDD MOVE S8, SP
+BFD061E0 0020F89E SW A0, 32(S8)
+BFD061E4 0024F8BE SW A1, 36(S8)
+BFD061E8 0028F8DE SW A2, 40(S8)
+BFD061EC 002CF8FE SW A3, 44(S8)
+277: Timer_t *pxNewTimer;\r
+278: \r
+279: /* Allocate the timer structure. */\r
+280: if( xTimerPeriodInTicks == ( TickType_t ) 0U )\r
+BFD061F0 0024FC5E LW V0, 36(S8)
+BFD061F4 000440A2 BNEZC V0, 0xBFD06200
+281: {\r
+282: pxNewTimer = NULL;\r
+BFD061F8 0010F81E SW ZERO, 16(S8)
+BFD061FC CC2E B 0xBFD0625A
+BFD061FE 0C00 NOP
+283: }\r
+284: else\r
+285: {\r
+286: pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );\r
+BFD06200 EE28 LI A0, 40
+BFD06202 111677E8 JALS pvPortMalloc
+BFD06204 0C001116 ADDI T0, S6, 3072
+BFD06206 0C00 NOP
+BFD06208 0010F85E SW V0, 16(S8)
+287: if( pxNewTimer != NULL )\r
+BFD0620C 0010FC5E LW V0, 16(S8)
+BFD06210 002340E2 BEQZC V0, 0xBFD0625A
+288: {\r
+289: /* Ensure the infrastructure used by the timer service task has been\r
+290: created/initialised. */\r
+291: prvCheckForValidListAndQueue();\r
+BFD06214 35F477E8 JALS prvCheckForValidListAndQueue
+BFD06216 0C0035F4 LHU T7, 3072(S4)
+BFD06218 0C00 NOP
+292: \r
+293: /* Initialise the timer structure members using the function parameters. */\r
+294: pxNewTimer->pcTimerName = pcTimerName;\r
+BFD0621A 0010FC5E LW V0, 16(S8)
+BFD0621E 0020FC7E LW V1, 32(S8)
+BFD06222 E9A0 SW V1, 0(V0)
+295: pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;\r
+BFD06224 0010FC5E LW V0, 16(S8)
+BFD06228 0024FC7E LW V1, 36(S8)
+BFD0622C E9A6 SW V1, 24(V0)
+296: pxNewTimer->uxAutoReload = uxAutoReload;\r
+BFD0622E 0010FC5E LW V0, 16(S8)
+BFD06232 0028FC7E LW V1, 40(S8)
+BFD06236 E9A7 SW V1, 28(V0)
+297: pxNewTimer->pvTimerID = pvTimerID;\r
+BFD06238 0010FC5E LW V0, 16(S8)
+BFD0623C 002CFC7E LW V1, 44(S8)
+BFD06240 E9A8 SW V1, 32(V0)
+298: pxNewTimer->pxCallbackFunction = pxCallbackFunction;\r
+BFD06242 0010FC5E LW V0, 16(S8)
+BFD06246 0030FC7E LW V1, 48(S8)
+BFD0624A E9A9 SW V1, 36(V0)
+299: vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );\r
+BFD0624C 0010FC5E LW V0, 16(S8)
+BFD06250 6D22 ADDIU V0, V0, 4
+BFD06252 0C82 MOVE A0, V0
+BFD06254 4EE677E8 JALS vListInitialiseItem
+BFD06256 4EE6 ADDIU S7, S7, 3
+BFD06258 0C00 NOP
+300: \r
+301: traceTIMER_CREATE( pxNewTimer );\r
+302: }\r
+303: else\r
+304: {\r
+305: traceTIMER_CREATE_FAILED();\r
+306: }\r
+307: }\r
+308: \r
+309: /* 0 is not a valid value for xTimerPeriodInTicks. */\r
+310: configASSERT( ( xTimerPeriodInTicks > 0 ) );\r
+BFD0625A 0024FC5E LW V0, 36(S8)
+BFD0625E 000940A2 BNEZC V0, 0xBFD06274
+BFD06262 BFD141A2 LUI V0, 0xBFD1
+BFD06264 3082BFD1 LDC1 F30, 12418(S1)
+BFD06266 9AE83082 ADDIU A0, V0, -25880
+BFD06268 30A09AE8 SWC1 F23, 12448(T0)
+BFD0626A 013630A0 ADDIU A1, ZERO, 310
+BFD0626E 4B7E77E8 JALS vAssertCalled
+BFD06270 4B7E LW K1, 120(SP)
+BFD06272 0C00 NOP
+311: \r
+312: return ( TimerHandle_t ) pxNewTimer;\r
+BFD06274 0010FC5E LW V0, 16(S8)
+313: }\r
+BFD06278 0FBE MOVE SP, S8
+BFD0627A 4BE7 LW RA, 28(SP)
+BFD0627C 4BC6 LW S8, 24(SP)
+BFD0627E 4C11 ADDIU SP, SP, 32
+BFD06280 459F JR16 RA
+BFD06282 0C00 NOP
+314: /*-----------------------------------------------------------*/\r
+315: \r
+316: BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )\r
+317: {\r
+BFD05A1C 4FE9 ADDIU SP, SP, -48
+BFD05A1E CBEB SW RA, 44(SP)
+BFD05A20 CBCA SW S8, 40(SP)
+BFD05A22 0FDD MOVE S8, SP
+BFD05A24 0030F89E SW A0, 48(S8)
+BFD05A28 0034F8BE SW A1, 52(S8)
+BFD05A2C 0038F8DE SW A2, 56(S8)
+BFD05A30 003CF8FE SW A3, 60(S8)
+318: BaseType_t xReturn = pdFAIL;\r
+BFD05A34 0010F81E SW ZERO, 16(S8)
+319: DaemonTaskMessage_t xMessage;\r
+320: \r
+321: /* Send a message to the timer service task to perform a particular action\r
+322: on a particular timer definition. */\r
+323: if( xTimerQueue != NULL )\r
+BFD05A38 8068FC5C LW V0, -32664(GP)
+BFD05A3C 004740E2 BEQZC V0, 0xBFD05ACE
+324: {\r
+325: /* Send a command to the timer service task to start the xTimer timer. */\r
+326: xMessage.xMessageID = xCommandID;\r
+BFD05A40 0034FC5E LW V0, 52(S8)
+BFD05A44 0014F85E SW V0, 20(S8)
+327: xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;\r
+BFD05A48 0038FC5E LW V0, 56(S8)
+BFD05A4C 0018F85E SW V0, 24(S8)
+328: xMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer;\r
+BFD05A50 0030FC5E LW V0, 48(S8)
+BFD05A54 001CF85E SW V0, 28(S8)
+329: \r
+330: if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )\r
+BFD05A58 0034FC5E LW V0, 52(S8)
+BFD05A5C 00069042 SLTI V0, V0, 6
+BFD05A60 002740E2 BEQZC V0, 0xBFD05AB2
+331: {\r
+332: if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )\r
+BFD05A64 4A8E77E8 JALS xTaskGetSchedulerState
+BFD05A66 4A8E LW S4, 56(SP)
+BFD05A68 0C00 NOP
+BFD05A6A 0C62 MOVE V1, V0
+BFD05A6C ED02 LI V0, 2
+BFD05A6E 0011B443 BNE V1, V0, 0xBFD05A94
+BFD05A70 0C000011 SLL ZERO, S1, 1
+BFD05A72 0C00 NOP
+333: {\r
+334: xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );\r
+BFD05A74 8068FC7C LW V1, -32664(GP)
+BFD05A78 0014305E ADDIU V0, S8, 20
+BFD05A7C 0C83 MOVE A0, V1
+BFD05A7E 0CA2 MOVE A1, V0
+BFD05A80 0040FCDE LW A2, 64(S8)
+BFD05A84 0CE0 MOVE A3, ZERO
+BFD05A86 06A277E8 JALS xQueueGenericSend
+BFD05A88 06A2 ADDU A1, S1, V0
+BFD05A8A 0C00 NOP
+BFD05A8C 0010F85E SW V0, 16(S8)
+BFD05A90 CC1E B 0xBFD05ACE
+BFD05A92 0C00 NOP
+335: }\r
+336: else\r
+337: {\r
+338: xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );\r
+BFD05A94 8068FC7C LW V1, -32664(GP)
+BFD05A98 0014305E ADDIU V0, S8, 20
+BFD05A9C 0C83 MOVE A0, V1
+BFD05A9E 0CA2 MOVE A1, V0
+BFD05AA0 0CC0 MOVE A2, ZERO
+BFD05AA2 0CE0 MOVE A3, ZERO
+BFD05AA4 06A277E8 JALS xQueueGenericSend
+BFD05AA6 06A2 ADDU A1, S1, V0
+BFD05AA8 0C00 NOP
+BFD05AAA 0010F85E SW V0, 16(S8)
+BFD05AAE CC0F B 0xBFD05ACE
+BFD05AB0 0C00 NOP
+339: }\r
+340: }\r
+341: else\r
+342: {\r
+343: xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\r
+BFD05AB2 8068FC7C LW V1, -32664(GP)
+BFD05AB6 0014305E ADDIU V0, S8, 20
+BFD05ABA 0C83 MOVE A0, V1
+BFD05ABC 0CA2 MOVE A1, V0
+BFD05ABE 003CFCDE LW A2, 60(S8)
+BFD05AC2 0CE0 MOVE A3, ZERO
+BFD05AC4 11EA77E8 JALS xQueueGenericSendFromISR
+BFD05AC6 0C0011EA ADDI T7, T2, 3072
+BFD05AC8 0C00 NOP
+BFD05ACA 0010F85E SW V0, 16(S8)
+344: }\r
+345: \r
+346: traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );\r
+347: }\r
+348: else\r
+349: {\r
+350: mtCOVERAGE_TEST_MARKER();\r
+351: }\r
+352: \r
+353: return xReturn;\r
+BFD05ACE 0010FC5E LW V0, 16(S8)
+354: }\r
+BFD05AD2 0FBE MOVE SP, S8
+BFD05AD4 4BEB LW RA, 44(SP)
+BFD05AD6 4BCA LW S8, 40(SP)
+BFD05AD8 4C19 ADDIU SP, SP, 48
+BFD05ADA 459F JR16 RA
+BFD05ADC 0C00 NOP
+355: /*-----------------------------------------------------------*/\r
+356: \r
+357: #if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r
+358: \r
+359: TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )\r
+360: {\r
+361: /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been\r
+362: started, then xTimerTaskHandle will be NULL. */\r
+363: configASSERT( ( xTimerTaskHandle != NULL ) );\r
+364: return xTimerTaskHandle;\r
+365: }\r
+366: \r
+367: #endif\r
+368: /*-----------------------------------------------------------*/\r
+369: \r
+370: const char * pcTimerGetTimerName( TimerHandle_t xTimer )\r
+371: {\r
+BFD09B04 4FF9 ADDIU SP, SP, -16
+BFD09B06 CBC3 SW S8, 12(SP)
+BFD09B08 0FDD MOVE S8, SP
+BFD09B0A 0010F89E SW A0, 16(S8)
+372: Timer_t *pxTimer = ( Timer_t * ) xTimer;\r
+BFD09B0E 0010FC5E LW V0, 16(S8)
+BFD09B12 0000F85E SW V0, 0(S8)
+373: \r
+374: return pxTimer->pcTimerName;\r
+BFD09B16 0000FC5E LW V0, 0(S8)
+BFD09B1A 6920 LW V0, 0(V0)
+375: }\r
+BFD09B1C 0FBE MOVE SP, S8
+BFD09B1E 4BC3 LW S8, 12(SP)
+BFD09B20 4C09 ADDIU SP, SP, 16
+BFD09B22 459F JR16 RA
+BFD09B24 0C00 NOP
+376: /*-----------------------------------------------------------*/\r
+377: \r
+378: static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )\r
+379: {\r
+BFD05F24 4FED ADDIU SP, SP, -40
+BFD05F26 CBE9 SW RA, 36(SP)
+BFD05F28 CBC8 SW S8, 32(SP)
+BFD05F2A 0FDD MOVE S8, SP
+BFD05F2C 0028F89E SW A0, 40(S8)
+BFD05F30 002CF8BE SW A1, 44(S8)
+380: BaseType_t xResult;\r
+381: Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );\r
+BFD05F34 8060FC5C LW V0, -32672(GP)
+BFD05F38 6923 LW V0, 12(V0)
+BFD05F3A 6923 LW V0, 12(V0)
+BFD05F3C 0018F85E SW V0, 24(S8)
+382: \r
+383: /* Remove the timer from the list of active timers. A check has already\r
+384: been performed to ensure the list is not empty. */\r
+385: ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\r
+BFD05F40 0018FC5E LW V0, 24(S8)
+BFD05F44 6D22 ADDIU V0, V0, 4
+BFD05F46 0C82 MOVE A0, V0
+BFD05F48 00C877E8 JALS uxListRemove
+BFD05F4A 0C0000C8 SLL A2, T0, 1
+BFD05F4C 0C00 NOP
+386: traceTIMER_EXPIRED( pxTimer );\r
+387: \r
+388: /* If the timer is an auto reload timer then calculate the next\r
+389: expiry time and re-insert the timer in the list of active timers. */\r
+390: if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )\r
+BFD05F4E 0018FC5E LW V0, 24(S8)
+BFD05F52 69A7 LW V1, 28(V0)
+BFD05F54 ED01 LI V0, 1
+BFD05F56 002FB443 BNE V1, V0, 0xBFD05FB8
+BFD05F58 0C00002F SLL AT, T7, 1
+BFD05F5A 0C00 NOP
+391: {\r
+392: /* The timer is inserted into a list using a time relative to anything\r
+393: other than the current time. It will therefore be inserted into the\r
+394: correct list relative to the time this task thinks it is now. */\r
+395: if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) == pdTRUE )\r
+BFD05F5C 0018FC5E LW V0, 24(S8)
+BFD05F60 69A6 LW V1, 24(V0)
+BFD05F62 0028FC5E LW V0, 40(S8)
+BFD05F66 0526 ADDU V0, V1, V0
+BFD05F68 0018FC9E LW A0, 24(S8)
+BFD05F6C 0CA2 MOVE A1, V0
+BFD05F6E 002CFCDE LW A2, 44(S8)
+BFD05F72 0028FCFE LW A3, 40(S8)
+BFD05F76 2BE477E8 JALS prvInsertTimerInActiveList
+BFD05F78 2BE4 LHU A3, 8(A2)
+BFD05F7A 0C00 NOP
+BFD05F7C 0C62 MOVE V1, V0
+BFD05F7E ED01 LI V0, 1
+BFD05F80 001AB443 BNE V1, V0, 0xBFD05FB8
+BFD05F82 0C00001A SLL ZERO, K0, 1
+BFD05F84 0C00 NOP
+396: {\r
+397: /* The timer expired before it was added to the active timer\r
+398: list. Reload it now. */\r
+399: xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );\r
+BFD05F86 C804 SW ZERO, 16(SP)
+BFD05F88 0018FC9E LW A0, 24(S8)
+BFD05F8C 0CA0 MOVE A1, ZERO
+BFD05F8E 0028FCDE LW A2, 40(S8)
+BFD05F92 0CE0 MOVE A3, ZERO
+BFD05F94 2D0E77E8 JALS xTimerGenericCommand
+BFD05F96 2D0E ANDI V0, S0, 0x8000
+BFD05F98 0C00 NOP
+BFD05F9A 001CF85E SW V0, 28(S8)
+400: configASSERT( xResult );\r
+BFD05F9E 001CFC5E LW V0, 28(S8)
+BFD05FA2 000940A2 BNEZC V0, 0xBFD05FB8
+BFD05FA6 BFD141A2 LUI V0, 0xBFD1
+BFD05FA8 3082BFD1 LDC1 F30, 12418(S1)
+BFD05FAA 9AE83082 ADDIU A0, V0, -25880
+BFD05FAC 30A09AE8 SWC1 F23, 12448(T0)
+BFD05FAE 019030A0 ADDIU A1, ZERO, 400
+BFD05FB2 4B7E77E8 JALS vAssertCalled
+BFD05FB4 4B7E LW K1, 120(SP)
+BFD05FB6 0C00 NOP
+401: ( void ) xResult;\r
+402: }\r
+403: else\r
+404: {\r
+405: mtCOVERAGE_TEST_MARKER();\r
+406: }\r
+407: }\r
+408: else\r
+409: {\r
+410: mtCOVERAGE_TEST_MARKER();\r
+411: }\r
+412: \r
+413: /* Call the timer callback. */\r
+414: pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\r
+BFD05FB8 0018FC5E LW V0, 24(S8)
+BFD05FBC 6929 LW V0, 36(V0)
+BFD05FBE 0018FC9E LW A0, 24(S8)
+BFD05FC2 45E2 JALRS16 V0
+BFD05FC4 0C00 NOP
+415: }\r
+BFD05FC6 0FBE MOVE SP, S8
+BFD05FC8 4BE9 LW RA, 36(SP)
+BFD05FCA 4BC8 LW S8, 32(SP)
+BFD05FCC 4C15 ADDIU SP, SP, 40
+BFD05FCE 459F JR16 RA
+BFD05FD0 0C00 NOP
+416: /*-----------------------------------------------------------*/\r
+417: \r
+418: static void prvTimerTask( void *pvParameters )\r
+419: {\r
+BFD09738 4FF1 ADDIU SP, SP, -32
+BFD0973A CBE7 SW RA, 28(SP)
+BFD0973C CBC6 SW S8, 24(SP)
+BFD0973E 0FDD MOVE S8, SP
+BFD09740 0020F89E SW A0, 32(S8)
+420: TickType_t xNextExpireTime;\r
+421: BaseType_t xListWasEmpty;\r
+422: \r
+423: /* Just to avoid compiler warnings. */\r
+424: ( void ) pvParameters;\r
+425: \r
+426: for( ;; )\r
+427: {\r
+428: /* Query the timers list to see if it contains any timers, and if so,\r
+429: obtain the time at which the next timer will expire. */\r
+430: xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );\r
+BFD09744 0014305E ADDIU V0, S8, 20
+BFD09748 0C82 MOVE A0, V0
+BFD0974A 47EE77E8 JALS prvGetNextExpireTime
+BFD0974E 0C00 NOP
+BFD09750 0010F85E SW V0, 16(S8)
+431: \r
+432: /* If a timer has expired, process it. Otherwise, block this task\r
+433: until either a timer does expire, or a command is received. */\r
+434: prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );\r
+BFD09754 0014FC5E LW V0, 20(S8)
+BFD09758 0010FC9E LW A0, 16(S8)
+BFD0975C 0CA2 MOVE A1, V0
+BFD0975E 2D7077E8 JALS prvProcessTimerOrBlockTask
+BFD09760 2D70 ANDI V0, A3, 0x80
+BFD09762 0C00 NOP
+435: \r
+436: /* Empty the command queue. */\r
+437: prvProcessReceivedCommands();\r
+BFD09764 0B9A77E8 JALS prvProcessReceivedCommands
+BFD09766 0B9A LBU A3, 10(S1)
+BFD09768 0C00 NOP
+438: }\r
+BFD0976A CFEC B 0xBFD09744
+BFD0976C 0C00 NOP
+439: }\r
+440: /*-----------------------------------------------------------*/\r
+441: \r
+442: static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty )\r
+443: {\r
+BFD05AE0 4FED ADDIU SP, SP, -40
+BFD05AE2 CBE9 SW RA, 36(SP)
+BFD05AE4 CBC8 SW S8, 32(SP)
+BFD05AE6 0FDD MOVE S8, SP
+BFD05AE8 0028F89E SW A0, 40(S8)
+BFD05AEC 002CF8BE SW A1, 44(S8)
+444: TickType_t xTimeNow;\r
+445: BaseType_t xTimerListsWereSwitched;\r
+446: \r
+447: vTaskSuspendAll();\r
+BFD05AF0 4EF477E8 JALS vTaskSuspendAll
+BFD05AF2 4EF4 ADDIU S7, S7, -6
+BFD05AF4 0C00 NOP
+448: {\r
+449: /* Obtain the time now to make an assessment as to whether the timer\r
+450: has expired or not. If obtaining the time causes the lists to switch\r
+451: then don't process this timer as any timers that remained in the list\r
+452: when the lists were switched will have been processed within the\r
+453: prvSampleTimeNow() function. */\r
+454: xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\r
+BFD05AF6 0018305E ADDIU V0, S8, 24
+BFD05AFA 0C82 MOVE A0, V0
+BFD05AFC 42A877E8 JALS prvSampleTimeNow
+BFD05AFE 0C0042A8 BC2T 2, 0xBFD07302
+BFD05B00 0C00 NOP
+BFD05B02 0010F85E SW V0, 16(S8)
+455: if( xTimerListsWereSwitched == pdFALSE )\r
+BFD05B06 0018FC5E LW V0, 24(S8)
+BFD05B0A 003D40A2 BNEZC V0, 0xBFD05B88
+456: {\r
+457: /* The tick count has not overflowed, has the timer expired? */\r
+458: if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )\r
+BFD05B0E 002CFC5E LW V0, 44(S8)
+BFD05B12 001440A2 BNEZC V0, 0xBFD05B3E
+BFD05B16 0028FC7E LW V1, 40(S8)
+BFD05B1A 0010FC5E LW V0, 16(S8)
+BFD05B1E 13900062 SLTU V0, V0, V1
+BFD05B20 40A21390 ADDI GP, S0, 16546
+BFD05B22 000C40A2 BNEZC V0, 0xBFD05B3E
+459: {\r
+460: ( void ) xTaskResumeAll();\r
+BFD05B26 158E77E8 JALS xTaskResumeAll
+BFD05B28 0C00158E LBU T4, 3072(T6)
+BFD05B2A 0C00 NOP
+461: prvProcessExpiredTimer( xNextExpireTime, xTimeNow );\r
+BFD05B2C 0028FC9E LW A0, 40(S8)
+BFD05B30 0010FCBE LW A1, 16(S8)
+BFD05B34 2F9277E8 JALS prvProcessExpiredTimer
+BFD05B36 2F92 ANDI A3, S1, 0x2
+BFD05B38 0C00 NOP
+BFD05B3A CC2C B 0xBFD05B94
+BFD05B3C 0C00 NOP
+462: }\r
+463: else\r
+464: {\r
+465: /* The tick count has not overflowed, and the next expire\r
+466: time has not been reached yet. This task should therefore\r
+467: block to wait for the next expire time or a command to be\r
+468: received - whichever comes first. The following line cannot\r
+469: be reached unless xNextExpireTime > xTimeNow, except in the\r
+470: case when the current timer list is empty. */\r
+471: vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );\r
+BFD05B3E 8068FC7C LW V1, -32664(GP)
+BFD05B42 0028FC9E LW A0, 40(S8)
+BFD05B46 0010FC5E LW V0, 16(S8)
+BFD05B4A 0529 SUBU V0, A0, V0
+BFD05B4C 0C83 MOVE A0, V1
+BFD05B4E 0CA2 MOVE A1, V0
+BFD05B50 002CFCDE LW A2, 44(S8)
+BFD05B54 349477E8 JALS vQueueWaitForMessageRestricted
+BFD05B56 0C003494 LHU A0, 3072(S4)
+BFD05B58 0C00 NOP
+472: \r
+473: if( xTaskResumeAll() == pdFALSE )\r
+BFD05B5A 158E77E8 JALS xTaskResumeAll
+BFD05B5C 0C00158E LBU T4, 3072(T6)
+BFD05B5E 0C00 NOP
+BFD05B60 001740A2 BNEZC V0, 0xBFD05B92
+474: {\r
+475: /* Yield to wait for either a command to arrive, or the\r
+476: block time to expire. If a command arrived between the\r
+477: critical section being exited and this yield then the yield\r
+478: will not cause the task to block. */\r
+479: portYIELD_WITHIN_API();\r
+BFD05B64 4E7677E8 JALS ulPortGetCP0Cause
+BFD05B66 4E76 ADDIU S3, S3, -5
+BFD05B68 0C00 NOP
+BFD05B6A 0014F85E SW V0, 20(S8)
+BFD05B6E 0014FC5E LW V0, 20(S8)
+BFD05B72 01005042 ORI V0, V0, 256
+BFD05B76 0014F85E SW V0, 20(S8)
+BFD05B7A 0014FC9E LW A0, 20(S8)
+BFD05B7E 4E8677E8 JALS vPortSetCP0Cause
+BFD05B80 4E86 ADDIU S4, S4, 3
+BFD05B82 0C00 NOP
+BFD05B84 CC07 B 0xBFD05B94
+BFD05B86 0C00 NOP
+BFD05B92 0C00 NOP
+480: }\r
+481: else\r
+482: {\r
+483: mtCOVERAGE_TEST_MARKER();\r
+484: }\r
+485: }\r
+486: }\r
+487: else\r
+488: {\r
+489: ( void ) xTaskResumeAll();\r
+BFD05B88 158E77E8 JALS xTaskResumeAll
+BFD05B8A 0C00158E LBU T4, 3072(T6)
+BFD05B8C 0C00 NOP
+BFD05B8E CC02 B 0xBFD05B94
+BFD05B90 0C00 NOP
+490: }\r
+491: }\r
+492: }\r
+BFD05B94 0FBE MOVE SP, S8
+BFD05B96 4BE9 LW RA, 36(SP)
+BFD05B98 4BC8 LW S8, 32(SP)
+BFD05B9A 4C15 ADDIU SP, SP, 40
+BFD05B9C 459F JR16 RA
+BFD05B9E 0C00 NOP
+493: /*-----------------------------------------------------------*/\r
+494: \r
+495: static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )\r
+496: {\r
+BFD08FDC 4FF9 ADDIU SP, SP, -16
+BFD08FDE CBC3 SW S8, 12(SP)
+BFD08FE0 0FDD MOVE S8, SP
+BFD08FE2 0010F89E SW A0, 16(S8)
+497: TickType_t xNextExpireTime;\r
+498: \r
+499: /* Timers are listed in expiry time order, with the head of the list\r
+500: referencing the task that will expire first. Obtain the time at which\r
+501: the timer with the nearest expiry time will expire. If there are no\r
+502: active timers then just set the next expire time to 0. That will cause\r
+503: this task to unblock when the tick count overflows, at which point the\r
+504: timer lists will be switched and the next expiry time can be\r
+505: re-assessed. */\r
+506: *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );\r
+BFD08FE6 8060FC5C LW V0, -32672(GP)
+BFD08FEA 6920 LW V0, 0(V0)
+BFD08FEC 0001B062 SLTIU V1, V0, 1
+BFD08FF0 0010FC5E LW V0, 16(S8)
+BFD08FF4 E9A0 SW V1, 0(V0)
+507: if( *pxListWasEmpty == pdFALSE )\r
+BFD08FF6 0010FC5E LW V0, 16(S8)
+BFD08FFA 6920 LW V0, 0(V0)
+BFD08FFC 000840A2 BNEZC V0, 0xBFD09010
+508: {\r
+509: xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\r
+BFD09000 8060FC5C LW V0, -32672(GP)
+BFD09004 6923 LW V0, 12(V0)
+BFD09006 6920 LW V0, 0(V0)
+BFD09008 0000F85E SW V0, 0(S8)
+BFD0900C CC03 B 0xBFD09014
+BFD0900E 0C00 NOP
+510: }\r
+511: else\r
+512: {\r
+513: /* Ensure the task unblocks when the tick count rolls over. */\r
+514: xNextExpireTime = ( TickType_t ) 0U;\r
+BFD09010 0000F81E SW ZERO, 0(S8)
+515: }\r
+516: \r
+517: return xNextExpireTime;\r
+BFD09014 0000FC5E LW V0, 0(S8)
+518: }\r
+BFD09018 0FBE MOVE SP, S8
+BFD0901A 4BC3 LW S8, 12(SP)
+BFD0901C 4C09 ADDIU SP, SP, 16
+BFD0901E 459F JR16 RA
+BFD09020 0C00 NOP
+519: /*-----------------------------------------------------------*/\r
+520: \r
+521: static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )\r
+522: {\r
+BFD08550 4FF1 ADDIU SP, SP, -32
+BFD08552 CBE7 SW RA, 28(SP)
+BFD08554 CBC6 SW S8, 24(SP)
+BFD08556 0FDD MOVE S8, SP
+BFD08558 0020F89E SW A0, 32(S8)
+523: TickType_t xTimeNow;\r
+524: PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */\r
+525: \r
+526: xTimeNow = xTaskGetTickCount();\r
+BFD0855C 4CCA77E8 JALS xTaskGetTickCount
+BFD0855E 4CCA ADDIU A2, A2, 5
+BFD08560 0C00 NOP
+BFD08562 0010F85E SW V0, 16(S8)
+527: \r
+528: if( xTimeNow < xLastTime )\r
+BFD08566 806CFC5C LW V0, -32660(GP)
+BFD0856A 0010FC7E LW V1, 16(S8)
+BFD0856E 13900043 SLTU V0, V1, V0
+BFD08570 40E21390 ADDI GP, S0, 16610
+BFD08572 000940E2 BEQZC V0, 0xBFD08588
+529: {\r
+530: prvSwitchTimerLists();\r
+BFD08576 1F7877E8 JALS prvSwitchTimerLists
+BFD08578 0C001F78 LB K1, 3072(T8)
+BFD0857A 0C00 NOP
+531: *pxTimerListsWereSwitched = pdTRUE;\r
+BFD0857C 0020FC5E LW V0, 32(S8)
+BFD08580 ED81 LI V1, 1
+BFD08582 E9A0 SW V1, 0(V0)
+BFD08584 CC04 B 0xBFD0858E
+BFD08586 0C00 NOP
+532: }\r
+533: else\r
+534: {\r
+535: *pxTimerListsWereSwitched = pdFALSE;\r
+BFD08588 0020FC5E LW V0, 32(S8)
+BFD0858C E820 SW S0, 0(V0)
+536: }\r
+537: \r
+538: xLastTime = xTimeNow;\r
+BFD0858E 0010FC5E LW V0, 16(S8)
+BFD08592 806CF85C SW V0, -32660(GP)
+539: \r
+540: return xTimeNow;\r
+BFD08596 0010FC5E LW V0, 16(S8)
+541: }\r
+BFD0859A 0FBE MOVE SP, S8
+BFD0859C 4BE7 LW RA, 28(SP)
+BFD0859E 4BC6 LW S8, 24(SP)
+BFD085A0 4C11 ADDIU SP, SP, 32
+BFD085A2 459F JR16 RA
+BFD085A4 0C00 NOP
+542: /*-----------------------------------------------------------*/\r
+543: \r
+544: static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )\r
+545: {\r
+BFD057C8 4FF1 ADDIU SP, SP, -32
+BFD057CA CBE7 SW RA, 28(SP)
+BFD057CC CBC6 SW S8, 24(SP)
+BFD057CE 0FDD MOVE S8, SP
+BFD057D0 0020F89E SW A0, 32(S8)
+BFD057D4 0024F8BE SW A1, 36(S8)
+BFD057D8 0028F8DE SW A2, 40(S8)
+BFD057DC 002CF8FE SW A3, 44(S8)
+546: BaseType_t xProcessTimerNow = pdFALSE;\r
+BFD057E0 0010F81E SW ZERO, 16(S8)
+547: \r
+548: listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );\r
+BFD057E4 0020FC5E LW V0, 32(S8)
+BFD057E8 0024FC7E LW V1, 36(S8)
+BFD057EC E9A1 SW V1, 4(V0)
+549: listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\r
+BFD057EE 0020FC5E LW V0, 32(S8)
+BFD057F2 0020FC7E LW V1, 32(S8)
+BFD057F6 E9A4 SW V1, 16(V0)
+550: \r
+551: if( xNextExpiryTime <= xTimeNow )\r
+BFD057F8 0024FC7E LW V1, 36(S8)
+BFD057FC 0028FC5E LW V0, 40(S8)
+BFD05800 13900062 SLTU V0, V0, V1
+BFD05802 40A21390 ADDI GP, S0, 16546
+BFD05804 001D40A2 BNEZC V0, 0xBFD05842
+552: {\r
+553: /* Has the expiry time elapsed between the command to start/reset a\r
+554: timer was issued, and the time the command was processed? */\r
+555: if( ( xTimeNow - xCommandTime ) >= pxTimer->xTimerPeriodInTicks )\r
+BFD05808 0028FC7E LW V1, 40(S8)
+BFD0580C 002CFC5E LW V0, 44(S8)
+BFD05810 05A7 SUBU V1, V1, V0
+BFD05812 0020FC5E LW V0, 32(S8)
+BFD05816 6926 LW V0, 24(V0)
+BFD05818 13900043 SLTU V0, V1, V0
+BFD0581A 40A21390 ADDI GP, S0, 16546
+BFD0581C 000540A2 BNEZC V0, 0xBFD0582A
+556: {\r
+557: /* The time between a command being issued and the command being\r
+558: processed actually exceeds the timers period. */\r
+559: xProcessTimerNow = pdTRUE;\r
+BFD05820 ED01 LI V0, 1
+BFD05822 0010F85E SW V0, 16(S8)
+BFD05824 CC2C0010 EXT ZERO, S0, 16, 26
+BFD05826 CC2C B 0xBFD05880
+BFD05828 0C00 NOP
+560: }\r
+561: else\r
+562: {\r
+563: vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );\r
+BFD0582A 8064FC7C LW V1, -32668(GP)
+BFD0582E 0020FC5E LW V0, 32(S8)
+BFD05832 6D22 ADDIU V0, V0, 4
+BFD05834 0C83 MOVE A0, V1
+BFD05836 0CA2 MOVE A1, V0
+BFD05838 304077E8 JALS vListInsert
+BFD0583A 0C003040 ADDIU V0, ZERO, 3072
+BFD0583C 0C00 NOP
+BFD0583E CC20 B 0xBFD05880
+BFD05840 0C00 NOP
+564: }\r
+565: }\r
+566: else\r
+567: {\r
+568: if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )\r
+BFD05842 0028FC7E LW V1, 40(S8)
+BFD05846 002CFC5E LW V0, 44(S8)
+BFD0584A 13900043 SLTU V0, V1, V0
+BFD0584C 40E21390 ADDI GP, S0, 16610
+BFD0584E 000D40E2 BEQZC V0, 0xBFD0586C
+BFD05852 0024FC7E LW V1, 36(S8)
+BFD05856 002CFC5E LW V0, 44(S8)
+BFD0585A 13900043 SLTU V0, V1, V0
+BFD0585C 40A21390 ADDI GP, S0, 16546
+BFD0585E 000540A2 BNEZC V0, 0xBFD0586C
+569: {\r
+570: /* If, since the command was issued, the tick count has overflowed\r
+571: but the expiry time has not, then the timer must have already passed\r
+572: its expiry time and should be processed immediately. */\r
+573: xProcessTimerNow = pdTRUE;\r
+BFD05862 ED01 LI V0, 1
+BFD05864 0010F85E SW V0, 16(S8)
+BFD05868 CC0B B 0xBFD05880
+BFD0586A 0C00 NOP
+574: }\r
+575: else\r
+576: {\r
+577: vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\r
+BFD0586C 8060FC7C LW V1, -32672(GP)
+BFD05870 0020FC5E LW V0, 32(S8)
+BFD05874 6D22 ADDIU V0, V0, 4
+BFD05876 0C83 MOVE A0, V1
+BFD05878 0CA2 MOVE A1, V0
+BFD0587A 304077E8 JALS vListInsert
+BFD0587C 0C003040 ADDIU V0, ZERO, 3072
+BFD0587E 0C00 NOP
+578: }\r
+579: }\r
+580: \r
+581: return xProcessTimerNow;\r
+BFD05880 0010FC5E LW V0, 16(S8)
+582: }\r
+BFD05884 0FBE MOVE SP, S8
+BFD05886 4BE7 LW RA, 28(SP)
+BFD05888 4BC6 LW S8, 24(SP)
+BFD0588A 4C11 ADDIU SP, SP, 32
+BFD0588C 459F JR16 RA
+BFD0588E 0C00 NOP
+583: /*-----------------------------------------------------------*/\r
+584: \r
+585: static void prvProcessReceivedCommands( void )\r
+586: {\r
+BFD01734 4FDD ADDIU SP, SP, -72
+BFD01736 CBF1 SW RA, 68(SP)
+BFD01738 CBD0 SW S8, 64(SP)
+BFD0173A 0FDD MOVE S8, SP
+587: DaemonTaskMessage_t xMessage;\r
+588: Timer_t *pxTimer;\r
+589: BaseType_t xTimerListsWereSwitched, xResult;\r
+590: TickType_t xTimeNow;\r
+591: \r
+592: while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */\r
+BFD0173C CCE0 B 0xBFD018FE
+BFD0173E 0C00 NOP
+BFD018FE 8068FC7C LW V1, -32664(GP)
+BFD01902 0028305E ADDIU V0, S8, 40
+BFD01906 0C83 MOVE A0, V1
+BFD01908 0CA2 MOVE A1, V0
+BFD0190A 0CC0 MOVE A2, ZERO
+BFD0190C 0CE0 MOVE A3, ZERO
+BFD0190E 081E77E8 JALS xQueueGenericReceive
+BFD01910 081E LBU S0, 14(S1)
+BFD01912 0C00 NOP
+BFD01914 FF1440A2 BNEZC V0, 0xBFD01740
+BFD01916 0FBEFF14 LW T8, 4030(S4)
+593: {\r
+594: #if ( INCLUDE_xTimerPendFunctionCall == 1 )\r
+595: {\r
+596: /* Negative commands are pended function calls rather than timer\r
+597: commands. */\r
+598: if( xMessage.xMessageID < ( BaseType_t ) 0 )\r
+BFD01740 0028FC5E LW V0, 40(S8)
+BFD01744 001F4042 BGEZ V0, 0xBFD01786
+BFD01746 0C00001F SLL ZERO, RA, 1
+BFD01748 0C00 NOP
+599: {\r
+600: const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );\r
+BFD0174A 0028305E ADDIU V0, S8, 40
+BFD0174E 6D22 ADDIU V0, V0, 4
+BFD01750 0018F85E SW V0, 24(S8)
+601: \r
+602: /* The timer uses the xCallbackParameters member to request a\r
+603: callback be executed. Check the callback is not NULL. */\r
+604: configASSERT( pxCallback );\r
+BFD01754 0018FC5E LW V0, 24(S8)
+BFD01758 000940A2 BNEZC V0, 0xBFD0176E
+BFD0175C BFD141A2 LUI V0, 0xBFD1
+BFD0175E 3082BFD1 LDC1 F30, 12418(S1)
+BFD01760 9AE83082 ADDIU A0, V0, -25880
+BFD01762 30A09AE8 SWC1 F23, 12448(T0)
+BFD01764 025C30A0 ADDIU A1, ZERO, 604
+BFD01768 4B7E77E8 JALS vAssertCalled
+BFD0176A 4B7E LW K1, 120(SP)
+BFD0176C 0C00 NOP
+605: \r
+606: /* Call the function. */\r
+607: pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );\r
+BFD0176E 0018FC5E LW V0, 24(S8)
+BFD01772 6920 LW V0, 0(V0)
+BFD01774 0018FC7E LW V1, 24(S8)
+BFD01778 6A31 LW A0, 4(V1)
+BFD0177A 0018FC7E LW V1, 24(S8)
+BFD0177E 69B2 LW V1, 8(V1)
+BFD01780 0CA3 MOVE A1, V1
+BFD01782 45E2 JALRS16 V0
+BFD01784 0C00 NOP
+608: }\r
+609: else\r
+610: {\r
+611: mtCOVERAGE_TEST_MARKER();\r
+612: }\r
+613: }\r
+614: #endif /* INCLUDE_xTimerPendFunctionCall */\r
+615: \r
+616: /* Commands that are positive are timer commands rather than pended\r
+617: function calls. */\r
+618: if( xMessage.xMessageID >= ( BaseType_t ) 0 )\r
+BFD01786 0028FC5E LW V0, 40(S8)
+BFD0178A 00B84002 BLTZ V0, 0xBFD018FE
+BFD0178C 0C0000B8 SLL A1, T8, 1
+BFD0178E 0C00 NOP
+619: {\r
+620: /* The messages uses the xTimerParameters member to work on a\r
+621: software timer. */\r
+622: pxTimer = xMessage.u.xTimerParameters.pxTimer;\r
+BFD01790 0030FC5E LW V0, 48(S8)
+BFD01794 001CF85E SW V0, 28(S8)
+623: \r
+624: if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )\r
+BFD01798 001CFC5E LW V0, 28(S8)
+BFD0179C 6925 LW V0, 20(V0)
+BFD0179E 000740E2 BEQZC V0, 0xBFD017B0
+625: {\r
+626: /* The timer is in a list, remove it. */\r
+627: ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\r
+BFD017A2 001CFC5E LW V0, 28(S8)
+BFD017A6 6D22 ADDIU V0, V0, 4
+BFD017A8 0C82 MOVE A0, V0
+BFD017AA 00C877E8 JALS uxListRemove
+BFD017AC 0C0000C8 SLL A2, T0, 1
+BFD017AE 0C00 NOP
+628: }\r
+629: else\r
+630: {\r
+631: mtCOVERAGE_TEST_MARKER();\r
+632: }\r
+633: \r
+634: traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );\r
+635: \r
+636: /* In this case the xTimerListsWereSwitched parameter is not used, but\r
+637: it must be present in the function call. prvSampleTimeNow() must be\r
+638: called after the message is received from xTimerQueue so there is no\r
+639: possibility of a higher priority task adding a message to the message\r
+640: queue with a time that is ahead of the timer daemon task (because it\r
+641: pre-empted the timer daemon task after the xTimeNow value was set). */\r
+642: xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\r
+BFD017B0 0038305E ADDIU V0, S8, 56
+BFD017B4 0C82 MOVE A0, V0
+BFD017B6 42A877E8 JALS prvSampleTimeNow
+BFD017B8 0C0042A8 BC2T 2, 0xBFD02FBC
+BFD017BA 0C00 NOP
+BFD017BC 0020F85E SW V0, 32(S8)
+643: \r
+644: switch( xMessage.xMessageID )\r
+BFD017C0 0028FC5E LW V0, 40(S8)
+BFD017C4 000AB062 SLTIU V1, V0, 10
+BFD017C8 008C40E3 BEQZC V1, 0xBFD018E4
+BFD017CC 25A4 SLL V1, V0, 2
+BFD017CE BFD041A2 LUI V0, 0xBFD0
+BFD017D0 3042BFD0 LDC1 F30, 12354(S0)
+BFD017D2 17DC3042 ADDIU V0, V0, 6108
+BFD017D4 052617DC LBU S8, 1318(GP)
+BFD017D6 0526 ADDU V0, V1, V0
+BFD017D8 6920 LW V0, 0(V0)
+BFD017DA 45A2 JRC V0
+BFD017DC BFD01805 SB ZERO, -16432(A1)
+BFD017DE 1805BFD0 LDC1 F30, 6149(S0)
+BFD017E0 BFD01805 SB ZERO, -16432(A1)
+BFD017E2 1805BFD0 LDC1 F30, 6149(S0)
+BFD017E4 BFD01805 SB ZERO, -16432(A1)
+BFD017E6 18EBBFD0 LDC1 F30, 6379(S0)
+BFD017E8 BFD018EB SB A3, -16432(T3)
+BFD017EA 188DBFD0 LDC1 F30, 6285(S0)
+BFD017EC BFD0188D SB A0, -16432(T5)
+BFD017EE 18D7BFD0 LDC1 F30, 6359(S0)
+BFD017F0 BFD018D7 SB A2, -16432(S7)
+BFD017F2 1805BFD0 LDC1 F30, 6149(S0)
+BFD017F4 BFD01805 SB ZERO, -16432(A1)
+BFD017F6 1805BFD0 LDC1 F30, 6149(S0)
+BFD017F8 BFD01805 SB ZERO, -16432(A1)
+BFD017FA 18EBBFD0 LDC1 F30, 6379(S0)
+BFD017FC BFD018EB SB A3, -16432(T3)
+BFD017FE 188DBFD0 LDC1 F30, 6285(S0)
+BFD01800 BFD0188D SB A0, -16432(T5)
+BFD01802 FC7EBFD0 LDC1 F30, -898(S0)
+645: {\r
+646: case tmrCOMMAND_START :\r
+647: case tmrCOMMAND_START_FROM_ISR :\r
+648: case tmrCOMMAND_RESET :\r
+649: case tmrCOMMAND_RESET_FROM_ISR :\r
+650: case tmrCOMMAND_START_DONT_TRACE :\r
+651: /* Start or restart a timer. */\r
+652: if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) == pdTRUE )\r
+BFD01804 002CFC7E LW V1, 44(S8)
+BFD01808 001CFC5E LW V0, 28(S8)
+BFD0180C 6926 LW V0, 24(V0)
+BFD0180E 05A6 ADDU V1, V1, V0
+BFD01810 002CFC5E LW V0, 44(S8)
+BFD01814 001CFC9E LW A0, 28(S8)
+BFD01818 0CA3 MOVE A1, V1
+BFD0181A 0020FCDE LW A2, 32(S8)
+BFD0181E 0CE2 MOVE A3, V0
+BFD01820 2BE477E8 JALS prvInsertTimerInActiveList
+BFD01822 2BE4 LHU A3, 8(A2)
+BFD01824 0C00 NOP
+BFD01826 0C62 MOVE V1, V0
+BFD01828 ED01 LI V0, 1
+BFD0182A 0061B443 BNE V1, V0, 0xBFD018F0
+BFD0182C 0C000061 SLL V1, AT, 1
+BFD0182E 0C00 NOP
+653: {\r
+654: /* The timer expired before it was added to the active\r
+655: timer list. Process it now. */\r
+656: pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\r
+BFD01830 001CFC5E LW V0, 28(S8)
+BFD01834 6929 LW V0, 36(V0)
+BFD01836 001CFC9E LW A0, 28(S8)
+BFD0183A 45E2 JALRS16 V0
+BFD0183C 0C00 NOP
+657: traceTIMER_EXPIRED( pxTimer );\r
+658: \r
+659: if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )\r
+BFD0183E 001CFC5E LW V0, 28(S8)
+BFD01842 69A7 LW V1, 28(V0)
+BFD01844 ED01 LI V0, 1
+BFD01846 0056B443 BNE V1, V0, 0xBFD018F6
+BFD01848 0C000056 SLL V0, S6, 1
+BFD0184A 0C00 NOP
+660: {\r
+661: xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );\r
+BFD0184C 002CFC7E LW V1, 44(S8)
+BFD01850 001CFC5E LW V0, 28(S8)
+BFD01854 6926 LW V0, 24(V0)
+BFD01856 0526 ADDU V0, V1, V0
+BFD01858 C804 SW ZERO, 16(SP)
+BFD0185A 001CFC9E LW A0, 28(S8)
+BFD0185E 0CA0 MOVE A1, ZERO
+BFD01860 0CC2 MOVE A2, V0
+BFD01862 0CE0 MOVE A3, ZERO
+BFD01864 2D0E77E8 JALS xTimerGenericCommand
+BFD01866 2D0E ANDI V0, S0, 0x8000
+BFD01868 0C00 NOP
+BFD0186A 0024F85E SW V0, 36(S8)
+662: configASSERT( xResult );\r
+BFD0186E 0024FC5E LW V0, 36(S8)
+BFD01872 004340A2 BNEZC V0, 0xBFD018FC
+BFD01876 BFD141A2 LUI V0, 0xBFD1
+BFD01878 3082BFD1 LDC1 F30, 12418(S1)
+BFD0187A 9AE83082 ADDIU A0, V0, -25880
+BFD0187C 30A09AE8 SWC1 F23, 12448(T0)
+BFD0187E 029630A0 ADDIU A1, ZERO, 662
+BFD01882 4B7E77E8 JALS vAssertCalled
+BFD01884 4B7E LW K1, 120(SP)
+BFD01886 0C00 NOP
+663: ( void ) xResult;\r
+664: }\r
+665: else\r
+666: {\r
+667: mtCOVERAGE_TEST_MARKER();\r
+668: }\r
+669: }\r
+670: else\r
+671: {\r
+672: mtCOVERAGE_TEST_MARKER();\r
+673: }\r
+674: break;\r
+BFD01888 CC3A B 0xBFD018FE
+BFD0188A 0C00 NOP
+BFD018F0 0C00 NOP
+BFD018F2 CC05 B 0xBFD018FE
+BFD018F4 0C00 NOP
+BFD018F6 0C00 NOP
+BFD018F8 CC02 B 0xBFD018FE
+BFD018FA 0C00 NOP
+BFD018FC 0C00 NOP
+675: \r
+676: case tmrCOMMAND_STOP :\r
+677: case tmrCOMMAND_STOP_FROM_ISR :\r
+678: /* The timer has already been removed from the active list.\r
+679: There is nothing to do here. */\r
+680: break;\r
+BFD018EA 0C00 NOP
+BFD018EC CC08 B 0xBFD018FE
+BFD018EE 0C00 NOP
+681: \r
+682: case tmrCOMMAND_CHANGE_PERIOD :\r
+683: case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :\r
+684: pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;\r
+BFD0188C 002CFC7E LW V1, 44(S8)
+BFD01890 001CFC5E LW V0, 28(S8)
+BFD01894 E9A6 SW V1, 24(V0)
+685: configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );\r
+BFD01896 001CFC5E LW V0, 28(S8)
+BFD0189A 6926 LW V0, 24(V0)
+BFD0189C 000940A2 BNEZC V0, 0xBFD018B2
+BFD018A0 BFD141A2 LUI V0, 0xBFD1
+BFD018A2 3082BFD1 LDC1 F30, 12418(S1)
+BFD018A4 9AE83082 ADDIU A0, V0, -25880
+BFD018A6 30A09AE8 SWC1 F23, 12448(T0)
+BFD018A8 02AD30A0 ADDIU A1, ZERO, 685
+BFD018AC 4B7E77E8 JALS vAssertCalled
+BFD018AE 4B7E LW K1, 120(SP)
+BFD018B0 0C00 NOP
+686: \r
+687: /* The new period does not really have a reference, and can be\r
+688: longer or shorter than the old one. The command time is\r
+689: therefore set to the current time, and as the period cannot be\r
+690: zero the next expiry time can only be in the future, meaning\r
+691: (unlike for the xTimerStart() case above) there is no fail case\r
+692: that needs to be handled here. */\r
+693: ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );\r
+BFD018B2 001CFC5E LW V0, 28(S8)
+BFD018B6 69A6 LW V1, 24(V0)
+BFD018B8 0020FC5E LW V0, 32(S8)
+BFD018BC 0526 ADDU V0, V1, V0
+BFD018BE 001CFC9E LW A0, 28(S8)
+BFD018C2 0CA2 MOVE A1, V0
+BFD018C4 0020FCDE LW A2, 32(S8)
+BFD018C8 0020FCFE LW A3, 32(S8)
+BFD018CC 2BE477E8 JALS prvInsertTimerInActiveList
+BFD018CE 2BE4 LHU A3, 8(A2)
+BFD018D0 0C00 NOP
+694: break;\r
+BFD018D2 CC15 B 0xBFD018FE
+BFD018D4 0C00 NOP
+695: \r
+696: case tmrCOMMAND_DELETE :\r
+697: /* The timer has already been removed from the active list,\r
+698: just free up the memory. */\r
+699: vPortFree( pxTimer );\r
+BFD018D6 001CFC9E LW A0, 28(S8)
+BFD018DA 2FEA77E8 JALS vPortFree
+BFD018DC 2FEA ANDI A3, A2, 0x20
+BFD018DE 0C00 NOP
+700: break;\r
+BFD018E0 CC0E B 0xBFD018FE
+BFD018E2 0C00 NOP
+701: \r
+702: default :\r
+703: /* Don't expect to get here. */\r
+704: break;\r
+BFD018E4 0C00 NOP
+BFD018E6 CC0B B 0xBFD018FE
+BFD018E8 0C00 NOP
+705: }\r
+706: }\r
+707: }\r
+708: }\r
+BFD01918 0FBE MOVE SP, S8
+BFD0191A 4BF1 LW RA, 68(SP)
+BFD0191C 4BD0 LW S8, 64(SP)
+BFD0191E 4C25 ADDIU SP, SP, 72
+BFD01920 459F JR16 RA
+BFD01922 0C00 NOP
+709: /*-----------------------------------------------------------*/\r
+710: \r
+711: static void prvSwitchTimerLists( void )\r
+712: {\r
+BFD03EF0 4FE5 ADDIU SP, SP, -56
+BFD03EF2 CBED SW RA, 52(SP)
+BFD03EF4 CBCC SW S8, 48(SP)
+BFD03EF6 0FDD MOVE S8, SP
+713: TickType_t xNextExpireTime, xReloadTime;\r
+714: List_t *pxTemp;\r
+715: Timer_t *pxTimer;\r
+716: BaseType_t xResult;\r
+717: \r
+718: /* The tick count has overflowed. The timer lists must be switched.\r
+719: If there are any timers still referenced from the current timer list\r
+720: then they must have expired and should be processed before the lists\r
+721: are switched. */\r
+722: while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )\r
+BFD03EF8 CC61 B 0xBFD03FBC
+BFD03EFA 0C00 NOP
+BFD03FBC 8060FC5C LW V0, -32672(GP)
+BFD03FC0 6920 LW V0, 0(V0)
+BFD03FC2 FF9B40A2 BNEZC V0, 0xBFD03EFC
+BFD03FC4 FC5CFF9B LW GP, -932(K1)
+723: {\r
+724: xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\r
+BFD03EFC 8060FC5C LW V0, -32672(GP)
+BFD03F00 6923 LW V0, 12(V0)
+BFD03F02 6920 LW V0, 0(V0)
+BFD03F04 0018F85E SW V0, 24(S8)
+725: \r
+726: /* Remove the timer from the list. */\r
+727: pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );\r
+BFD03F08 8060FC5C LW V0, -32672(GP)
+BFD03F0C 6923 LW V0, 12(V0)
+BFD03F0E 6923 LW V0, 12(V0)
+BFD03F10 001CF85E SW V0, 28(S8)
+728: ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\r
+BFD03F14 001CFC5E LW V0, 28(S8)
+BFD03F18 6D22 ADDIU V0, V0, 4
+BFD03F1A 0C82 MOVE A0, V0
+BFD03F1C 00C877E8 JALS uxListRemove
+BFD03F1E 0C0000C8 SLL A2, T0, 1
+BFD03F20 0C00 NOP
+729: traceTIMER_EXPIRED( pxTimer );\r
+730: \r
+731: /* Execute its callback, then send a command to restart the timer if\r
+732: it is an auto-reload timer. It cannot be restarted here as the lists\r
+733: have not yet been switched. */\r
+734: pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\r
+BFD03F22 001CFC5E LW V0, 28(S8)
+BFD03F26 6929 LW V0, 36(V0)
+BFD03F28 001CFC9E LW A0, 28(S8)
+BFD03F2C 45E2 JALRS16 V0
+BFD03F2E 0C00 NOP
+735: \r
+736: if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )\r
+BFD03F30 001CFC5E LW V0, 28(S8)
+BFD03F34 69A7 LW V1, 28(V0)
+BFD03F36 ED01 LI V0, 1
+BFD03F38 0040B443 BNE V1, V0, 0xBFD03FBC
+BFD03F3A 0C000040 SLL V0, ZERO, 1
+BFD03F3C 0C00 NOP
+737: {\r
+738: /* Calculate the reload value, and if the reload value results in\r
+739: the timer going into the same timer list then it has already expired\r
+740: and the timer should be re-inserted into the current list so it is\r
+741: processed again within this loop. Otherwise a command should be sent\r
+742: to restart the timer to ensure it is only inserted into a list after\r
+743: the lists have been swapped. */\r
+744: xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );\r
+BFD03F3E 001CFC5E LW V0, 28(S8)
+BFD03F42 69A6 LW V1, 24(V0)
+BFD03F44 0018FC5E LW V0, 24(S8)
+BFD03F48 0526 ADDU V0, V1, V0
+BFD03F4A 0020F85E SW V0, 32(S8)
+745: if( xReloadTime > xNextExpireTime )\r
+BFD03F4E 0020FC7E LW V1, 32(S8)
+BFD03F52 0018FC5E LW V0, 24(S8)
+BFD03F56 13900062 SLTU V0, V0, V1
+BFD03F58 40E21390 ADDI GP, S0, 16610
+BFD03F5A 001640E2 BEQZC V0, 0xBFD03F8A
+746: {\r
+747: listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );\r
+BFD03F5E 001CFC5E LW V0, 28(S8)
+BFD03F62 0020FC7E LW V1, 32(S8)
+BFD03F66 E9A1 SW V1, 4(V0)
+748: listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\r
+BFD03F68 001CFC5E LW V0, 28(S8)
+BFD03F6C 001CFC7E LW V1, 28(S8)
+BFD03F70 E9A4 SW V1, 16(V0)
+749: vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\r
+BFD03F72 8060FC7C LW V1, -32672(GP)
+BFD03F76 001CFC5E LW V0, 28(S8)
+BFD03F7A 6D22 ADDIU V0, V0, 4
+BFD03F7C 0C83 MOVE A0, V1
+BFD03F7E 0CA2 MOVE A1, V0
+BFD03F80 304077E8 JALS vListInsert
+BFD03F82 0C003040 ADDIU V0, ZERO, 3072
+BFD03F84 0C00 NOP
+BFD03F86 CC1A B 0xBFD03FBC
+BFD03F88 0C00 NOP
+750: }\r
+751: else\r
+752: {\r
+753: xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );\r
+BFD03F8A C804 SW ZERO, 16(SP)
+BFD03F8C 001CFC9E LW A0, 28(S8)
+BFD03F90 0CA0 MOVE A1, ZERO
+BFD03F92 0018FCDE LW A2, 24(S8)
+BFD03F96 0CE0 MOVE A3, ZERO
+BFD03F98 2D0E77E8 JALS xTimerGenericCommand
+BFD03F9A 2D0E ANDI V0, S0, 0x8000
+BFD03F9C 0C00 NOP
+BFD03F9E 0024F85E SW V0, 36(S8)
+754: configASSERT( xResult );\r
+BFD03FA2 0024FC5E LW V0, 36(S8)
+BFD03FA6 000940A2 BNEZC V0, 0xBFD03FBC
+BFD03FAA BFD141A2 LUI V0, 0xBFD1
+BFD03FAC 3082BFD1 LDC1 F30, 12418(S1)
+BFD03FAE 9AE83082 ADDIU A0, V0, -25880
+BFD03FB0 30A09AE8 SWC1 F23, 12448(T0)
+BFD03FB2 02F230A0 ADDIU A1, ZERO, 754
+BFD03FB6 4B7E77E8 JALS vAssertCalled
+BFD03FB8 4B7E LW K1, 120(SP)
+BFD03FBA 0C00 NOP
+755: ( void ) xResult;\r
+756: }\r
+757: }\r
+758: else\r
+759: {\r
+760: mtCOVERAGE_TEST_MARKER();\r
+761: }\r
+762: }\r
+763: \r
+764: pxTemp = pxCurrentTimerList;\r
+BFD03FC6 8060FC5C LW V0, -32672(GP)
+BFD03FCA 0028F85E SW V0, 40(S8)
+765: pxCurrentTimerList = pxOverflowTimerList;\r
+BFD03FCE 8064FC5C LW V0, -32668(GP)
+BFD03FD2 8060F85C SW V0, -32672(GP)
+766: pxOverflowTimerList = pxTemp;\r
+BFD03FD6 0028FC5E LW V0, 40(S8)
+BFD03FDA 8064F85C SW V0, -32668(GP)
+767: }\r
+BFD03FDE 0FBE MOVE SP, S8
+BFD03FE0 4BED LW RA, 52(SP)
+BFD03FE2 4BCC LW S8, 48(SP)
+BFD03FE4 4C1D ADDIU SP, SP, 56
+BFD03FE6 459F JR16 RA
+BFD03FE8 0C00 NOP
+768: /*-----------------------------------------------------------*/\r
+769: \r
+770: static void prvCheckForValidListAndQueue( void )\r
+771: {\r
+BFD06BE8 4FF5 ADDIU SP, SP, -24
+BFD06BEA CBE5 SW RA, 20(SP)
+BFD06BEC CBC4 SW S8, 16(SP)
+BFD06BEE 0FDD MOVE S8, SP
+772: /* Check that the list from which active timers are referenced, and the\r
+773: queue used to communicate with the timer service, have been\r
+774: initialised. */\r
+775: taskENTER_CRITICAL();\r
+BFD06BF0 33B877E8 JALS vTaskEnterCritical
+BFD06BF2 0C0033B8 ADDIU SP, T8, 3072
+BFD06BF4 0C00 NOP
+776: {\r
+777: if( xTimerQueue == NULL )\r
+BFD06BF6 8068FC5C LW V0, -32664(GP)
+BFD06BFA 002F40A2 BNEZC V0, 0xBFD06C5C
+778: {\r
+779: vListInitialise( &xActiveTimerList1 );\r
+BFD06BFE BFD241A2 LUI V0, 0xBFD2
+BFD06C00 3082BFD2 LDC1 F30, 12418(S2)
+BFD06C02 B9483082 ADDIU A0, V0, -18104
+BFD06C04 77E8B948 SDC1 F10, 30696(T0)
+BFD06C06 457077E8 JALS vListInitialise
+BFD06C08 4570 SWM16 0x3, 0(SP)
+BFD06C0A 0C00 NOP
+780: vListInitialise( &xActiveTimerList2 );\r
+BFD06C0C BFD241A2 LUI V0, 0xBFD2
+BFD06C0E 3082BFD2 LDC1 F30, 12418(S2)
+BFD06C10 B95C3082 ADDIU A0, V0, -18084
+BFD06C12 77E8B95C SDC1 F10, 30696(GP)
+BFD06C14 457077E8 JALS vListInitialise
+BFD06C16 4570 SWM16 0x3, 0(SP)
+BFD06C18 0C00 NOP
+781: pxCurrentTimerList = &xActiveTimerList1;\r
+BFD06C1A BFD241A2 LUI V0, 0xBFD2
+BFD06C1C 3042BFD2 LDC1 F30, 12354(S2)
+BFD06C1E B9483042 ADDIU V0, V0, -18104
+BFD06C20 F85CB948 SDC1 F10, -1956(T0)
+BFD06C22 8060F85C SW V0, -32672(GP)
+782: pxOverflowTimerList = &xActiveTimerList2;\r
+BFD06C26 BFD241A2 LUI V0, 0xBFD2
+BFD06C28 3042BFD2 LDC1 F30, 12354(S2)
+BFD06C2A B95C3042 ADDIU V0, V0, -18084
+BFD06C2C F85CB95C SDC1 F10, -1956(GP)
+BFD06C2E 8064F85C SW V0, -32668(GP)
+783: xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );\r
+BFD06C32 EE05 LI A0, 5
+BFD06C34 EE90 LI A1, 16
+BFD06C36 0CC0 MOVE A2, ZERO
+BFD06C38 1EFA77E8 JALS xQueueGenericCreate
+BFD06C3A 0C001EFA LB S7, 3072(K0)
+BFD06C3C 0C00 NOP
+BFD06C3E 8068F85C SW V0, -32664(GP)
+784: configASSERT( xTimerQueue );\r
+BFD06C42 8068FC5C LW V0, -32664(GP)
+BFD06C46 000940A2 BNEZC V0, 0xBFD06C5C
+BFD06C4A BFD141A2 LUI V0, 0xBFD1
+BFD06C4C 3082BFD1 LDC1 F30, 12418(S1)
+BFD06C4E 9AE83082 ADDIU A0, V0, -25880
+BFD06C50 30A09AE8 SWC1 F23, 12448(T0)
+BFD06C52 031030A0 ADDIU A1, ZERO, 784
+BFD06C56 4B7E77E8 JALS vAssertCalled
+BFD06C58 4B7E LW K1, 120(SP)
+BFD06C5A 0C00 NOP
+785: \r
+786: #if ( configQUEUE_REGISTRY_SIZE > 0 )\r
+787: {\r
+788: if( xTimerQueue != NULL )\r
+789: {\r
+790: vQueueAddToRegistry( xTimerQueue, "TmrQ" );\r
+791: }\r
+792: else\r
+793: {\r
+794: mtCOVERAGE_TEST_MARKER();\r
+795: }\r
+796: }\r
+797: #endif /* configQUEUE_REGISTRY_SIZE */\r
+798: }\r
+799: else\r
+800: {\r
+801: mtCOVERAGE_TEST_MARKER();\r
+802: }\r
+803: }\r
+804: taskEXIT_CRITICAL();\r
+BFD06C5C 40AA77E8 JALS vTaskExitCritical
+BFD06C5E 0C0040AA BNEZC T2, 0xBFD08462
+BFD06C60 0C00 NOP
+805: }\r
+BFD06C62 0FBE MOVE SP, S8
+BFD06C64 4BE5 LW RA, 20(SP)
+BFD06C66 4BC4 LW S8, 16(SP)
+BFD06C68 4C0D ADDIU SP, SP, 24
+BFD06C6A 459F JR16 RA
+BFD06C6C 0C00 NOP
+806: /*-----------------------------------------------------------*/\r
+807: \r
+808: BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )\r
+809: {\r
+BFD093E0 4FF1 ADDIU SP, SP, -32
+BFD093E2 CBE7 SW RA, 28(SP)
+BFD093E4 CBC6 SW S8, 24(SP)
+BFD093E6 0FDD MOVE S8, SP
+BFD093E8 0020F89E SW A0, 32(S8)
+810: BaseType_t xTimerIsInActiveList;\r
+811: Timer_t *pxTimer = ( Timer_t * ) xTimer;\r
+BFD093EC 0020FC5E LW V0, 32(S8)
+BFD093F0 0010F85E SW V0, 16(S8)
+812: \r
+813: /* Is the timer in the list of active timers? */\r
+814: taskENTER_CRITICAL();\r
+BFD093F4 33B877E8 JALS vTaskEnterCritical
+BFD093F6 0C0033B8 ADDIU SP, T8, 3072
+BFD093F8 0C00 NOP
+815: {\r
+816: /* Checking to see if it is in the NULL list in effect checks to see if\r
+817: it is referenced from either the current or the overflow timer lists in\r
+818: one go, but the logic has to be reversed, hence the '!'. */\r
+819: xTimerIsInActiveList = ( BaseType_t ) !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) );\r
+BFD093FA 0010FC5E LW V0, 16(S8)
+BFD093FE 6925 LW V0, 20(V0)
+BFD09400 13900040 SLTU V0, ZERO, V0
+BFD09402 F85E1390 ADDI GP, S0, -1954
+BFD09404 0014F85E SW V0, 20(S8)
+820: }\r
+821: taskEXIT_CRITICAL();\r
+BFD09408 40AA77E8 JALS vTaskExitCritical
+BFD0940A 0C0040AA BNEZC T2, 0xBFD0AC0E
+BFD0940C 0C00 NOP
+822: \r
+823: return xTimerIsInActiveList;\r
+BFD0940E 0014FC5E LW V0, 20(S8)
+824: } /*lint !e818 Can't be pointer to const due to the typedef. */\r
+BFD09412 0FBE MOVE SP, S8
+BFD09414 4BE7 LW RA, 28(SP)
+BFD09416 4BC6 LW S8, 24(SP)
+BFD09418 4C11 ADDIU SP, SP, 32
+BFD0941A 459F JR16 RA
+BFD0941C 0C00 NOP
+825: /*-----------------------------------------------------------*/\r
+826: \r
+827: void *pvTimerGetTimerID( const TimerHandle_t xTimer )\r
+828: {\r
+BFD0875C 4FF1 ADDIU SP, SP, -32
+BFD0875E CBE7 SW RA, 28(SP)
+BFD08760 CBC6 SW S8, 24(SP)
+BFD08762 0FDD MOVE S8, SP
+BFD08764 0020F89E SW A0, 32(S8)
+829: Timer_t * const pxTimer = ( Timer_t * ) xTimer;\r
+BFD08768 0020FC5E LW V0, 32(S8)
+BFD0876C 0010F85E SW V0, 16(S8)
+830: void *pvReturn;\r
+831: \r
+832: configASSERT( xTimer );\r
+BFD08770 0020FC5E LW V0, 32(S8)
+BFD08774 000940A2 BNEZC V0, 0xBFD0878A
+BFD08778 BFD141A2 LUI V0, 0xBFD1
+BFD0877A 3082BFD1 LDC1 F30, 12418(S1)
+BFD0877C 9AE83082 ADDIU A0, V0, -25880
+BFD0877E 30A09AE8 SWC1 F23, 12448(T0)
+BFD08780 034030A0 ADDIU A1, ZERO, 832
+BFD08784 4B7E77E8 JALS vAssertCalled
+BFD08786 4B7E LW K1, 120(SP)
+BFD08788 0C00 NOP
+833: \r
+834: taskENTER_CRITICAL();\r
+BFD0878A 33B877E8 JALS vTaskEnterCritical
+BFD0878C 0C0033B8 ADDIU SP, T8, 3072
+BFD0878E 0C00 NOP
+835: {\r
+836: pvReturn = pxTimer->pvTimerID;\r
+BFD08790 0010FC5E LW V0, 16(S8)
+BFD08794 6928 LW V0, 32(V0)
+BFD08796 0014F85E SW V0, 20(S8)
+837: }\r
+838: taskEXIT_CRITICAL();\r
+BFD0879A 40AA77E8 JALS vTaskExitCritical
+BFD0879C 0C0040AA BNEZC T2, 0xBFD09FA0
+BFD0879E 0C00 NOP
+839: \r
+840: return pvReturn;\r
+BFD087A0 0014FC5E LW V0, 20(S8)
+841: }\r
+BFD087A4 0FBE MOVE SP, S8
+BFD087A6 4BE7 LW RA, 28(SP)
+BFD087A8 4BC6 LW S8, 24(SP)
+BFD087AA 4C11 ADDIU SP, SP, 32
+BFD087AC 459F JR16 RA
+BFD087AE 0C00 NOP
+842: /*-----------------------------------------------------------*/\r
+843: \r
+844: void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )\r
+845: {\r
+BFD087B0 4FF1 ADDIU SP, SP, -32
+BFD087B2 CBE7 SW RA, 28(SP)
+BFD087B4 CBC6 SW S8, 24(SP)
+BFD087B6 0FDD MOVE S8, SP
+BFD087B8 0020F89E SW A0, 32(S8)
+BFD087BC 0024F8BE SW A1, 36(S8)
+846: Timer_t * const pxTimer = ( Timer_t * ) xTimer;\r
+BFD087C0 0020FC5E LW V0, 32(S8)
+BFD087C4 0010F85E SW V0, 16(S8)
+847: \r
+848: configASSERT( xTimer );\r
+BFD087C8 0020FC5E LW V0, 32(S8)
+BFD087CC 000940A2 BNEZC V0, 0xBFD087E2
+BFD087D0 BFD141A2 LUI V0, 0xBFD1
+BFD087D2 3082BFD1 LDC1 F30, 12418(S1)
+BFD087D4 9AE83082 ADDIU A0, V0, -25880
+BFD087D6 30A09AE8 SWC1 F23, 12448(T0)
+BFD087D8 035030A0 ADDIU A1, ZERO, 848
+BFD087DC 4B7E77E8 JALS vAssertCalled
+BFD087DE 4B7E LW K1, 120(SP)
+BFD087E0 0C00 NOP
+849: \r
+850: taskENTER_CRITICAL();\r
+BFD087E2 33B877E8 JALS vTaskEnterCritical
+BFD087E4 0C0033B8 ADDIU SP, T8, 3072
+BFD087E6 0C00 NOP
+851: {\r
+852: pxTimer->pvTimerID = pvNewID;\r
+BFD087E8 0010FC5E LW V0, 16(S8)
+BFD087EC 0024FC7E LW V1, 36(S8)
+BFD087F0 E9A8 SW V1, 32(V0)
+853: }\r
+854: taskEXIT_CRITICAL();\r
+BFD087F2 40AA77E8 JALS vTaskExitCritical
+BFD087F4 0C0040AA BNEZC T2, 0xBFD09FF8
+BFD087F6 0C00 NOP
+855: }\r
+BFD087F8 0FBE MOVE SP, S8
+BFD087FA 4BE7 LW RA, 28(SP)
+BFD087FC 4BC6 LW S8, 24(SP)
+BFD087FE 4C11 ADDIU SP, SP, 32
+BFD08800 459F JR16 RA
+BFD08802 0C00 NOP
+856: /*-----------------------------------------------------------*/\r
+857: \r
+858: #if( INCLUDE_xTimerPendFunctionCall == 1 )\r
+859: \r
+860: BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )\r
+861: {\r
+BFD07F64 4FE9 ADDIU SP, SP, -48
+BFD07F66 CBEB SW RA, 44(SP)
+BFD07F68 CBCA SW S8, 40(SP)
+BFD07F6A 0FDD MOVE S8, SP
+BFD07F6C 0030F89E SW A0, 48(S8)
+BFD07F70 0034F8BE SW A1, 52(S8)
+BFD07F74 0038F8DE SW A2, 56(S8)
+BFD07F78 003CF8FE SW A3, 60(S8)
+BFD07F7A 3040003C SRL AT, GP, 6
+862: DaemonTaskMessage_t xMessage;\r
+863: BaseType_t xReturn;\r
+864: \r
+865: /* Complete the message with the function parameters and post it to the\r
+866: daemon task. */\r
+867: xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;\r
+BFD07F7C FFFE3040 ADDIU V0, ZERO, -2
+BFD07F7E F85EFFFE LW RA, -1954(S8)
+BFD07F80 0014F85E SW V0, 20(S8)
+868: xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;\r
+BFD07F84 0030FC5E LW V0, 48(S8)
+BFD07F88 0018F85E SW V0, 24(S8)
+869: xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;\r
+BFD07F8C 0034FC5E LW V0, 52(S8)
+BFD07F90 001CF85E SW V0, 28(S8)
+870: xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;\r
+BFD07F94 0038FC5E LW V0, 56(S8)
+BFD07F98 0020F85E SW V0, 32(S8)
+871: \r
+872: xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\r
+BFD07F9C 8068FC7C LW V1, -32664(GP)
+BFD07FA0 0014305E ADDIU V0, S8, 20
+BFD07FA4 0C83 MOVE A0, V1
+BFD07FA6 0CA2 MOVE A1, V0
+BFD07FA8 003CFCDE LW A2, 60(S8)
+BFD07FAC 0CE0 MOVE A3, ZERO
+BFD07FAE 11EA77E8 JALS xQueueGenericSendFromISR
+BFD07FB0 0C0011EA ADDI T7, T2, 3072
+BFD07FB2 0C00 NOP
+BFD07FB4 0010F85E SW V0, 16(S8)
+873: \r
+874: tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );\r
+875: \r
+876: return xReturn;\r
+BFD07FB8 0010FC5E LW V0, 16(S8)
+877: }\r
+BFD07FBC 0FBE MOVE SP, S8
+BFD07FBE 4BEB LW RA, 44(SP)
+BFD07FC0 4BCA LW S8, 40(SP)
+BFD07FC2 4C19 ADDIU SP, SP, 48
+BFD07FC4 459F JR16 RA
+BFD07FC6 0C00 NOP
+878: \r
+879: #endif /* INCLUDE_xTimerPendFunctionCall */\r
+880: /*-----------------------------------------------------------*/\r
+881: \r
+882: #if( INCLUDE_xTimerPendFunctionCall == 1 )\r
+883: \r
+884: BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )\r
+885: {\r
+BFD06D70 4FE9 ADDIU SP, SP, -48
+BFD06D72 CBEB SW RA, 44(SP)
+BFD06D74 CBCA SW S8, 40(SP)
+BFD06D76 0FDD MOVE S8, SP
+BFD06D78 0030F89E SW A0, 48(S8)
+BFD06D7C 0034F8BE SW A1, 52(S8)
+BFD06D80 0038F8DE SW A2, 56(S8)
+BFD06D84 003CF8FE SW A3, 60(S8)
+886: DaemonTaskMessage_t xMessage;\r
+887: BaseType_t xReturn;\r
+888: \r
+889: /* This function can only be called after a timer has been created or\r
+890: after the scheduler has been started because, until then, the timer\r
+891: queue does not exist. */\r
+892: configASSERT( xTimerQueue );\r
+BFD06D88 8068FC5C LW V0, -32664(GP)
+BFD06D8C 000940A2 BNEZC V0, 0xBFD06DA2
+BFD06D90 BFD141A2 LUI V0, 0xBFD1
+BFD06D92 3082BFD1 LDC1 F30, 12418(S1)
+BFD06D94 9AE83082 ADDIU A0, V0, -25880
+BFD06D96 30A09AE8 SWC1 F23, 12448(T0)
+BFD06D98 037C30A0 ADDIU A1, ZERO, 892
+BFD06D9C 4B7E77E8 JALS vAssertCalled
+BFD06D9E 4B7E LW K1, 120(SP)
+BFD06DA0 0C00 NOP
+893: \r
+894: /* Complete the message with the function parameters and post it to the\r
+895: daemon task. */\r
+896: xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;\r
+BFD06DA2 ED7F LI V0, -1
+BFD06DA4 0014F85E SW V0, 20(S8)
+897: xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;\r
+BFD06DA8 0030FC5E LW V0, 48(S8)
+BFD06DAC 0018F85E SW V0, 24(S8)
+898: xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;\r
+BFD06DB0 0034FC5E LW V0, 52(S8)
+BFD06DB4 001CF85E SW V0, 28(S8)
+899: xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;\r
+BFD06DB8 0038FC5E LW V0, 56(S8)
+BFD06DBC 0020F85E SW V0, 32(S8)
+900: \r
+901: xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );\r
+BFD06DC0 8068FC7C LW V1, -32664(GP)
+BFD06DC4 0014305E ADDIU V0, S8, 20
+BFD06DC8 0C83 MOVE A0, V1
+BFD06DCA 0CA2 MOVE A1, V0
+BFD06DCC 003CFCDE LW A2, 60(S8)
+BFD06DD0 0CE0 MOVE A3, ZERO
+BFD06DD2 06A277E8 JALS xQueueGenericSend
+BFD06DD4 06A2 ADDU A1, S1, V0
+BFD06DD6 0C00 NOP
+BFD06DD8 0010F85E SW V0, 16(S8)
+902: \r
+903: tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );\r
+904: \r
+905: return xReturn;\r
+BFD06DDC 0010FC5E LW V0, 16(S8)
+906: }\r
+BFD06DE0 0FBE MOVE SP, S8
+BFD06DE2 4BEB LW RA, 44(SP)
+BFD06DE4 4BCA LW S8, 40(SP)
+BFD06DE6 4C19 ADDIU SP, SP, 48
+BFD06DE8 459F JR16 RA
+BFD06DEA 0C00 NOP
+907: \r
+908: #endif /* INCLUDE_xTimerPendFunctionCall */\r
+909: /*-----------------------------------------------------------*/\r
+910: \r
+911: /* This entire source file will be skipped if the application is not configured\r
+912: to include software timer functionality. If you want to include software timer\r
+913: functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\r
+914: #endif /* configUSE_TIMERS == 1 */\r
+915: \r
+916: \r
+917: \r
+--- c:/e/dev/freertos/workingcopy/freertos/source/tasks.c ---------------------------------------------
+1: /*\r
+2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+3: All rights reserved\r
+4: \r
+5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+6: \r
+7: This file is part of the FreeRTOS distribution.\r
+8: \r
+9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
+10: the terms of the GNU General Public License (version 2) as published by the\r
+11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+12: \r
+13: ***************************************************************************\r
+14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+15: >>! distribute a combined work that includes FreeRTOS without being !<<\r
+16: >>! obliged to provide the source code for proprietary components !<<\r
+17: >>! outside of the FreeRTOS kernel. !<<\r
+18: ***************************************************************************\r
+19: \r
+20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+22: FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+23: link: http://www.freertos.org/a00114.html\r
+24: \r
+25: ***************************************************************************\r
+26: * *\r
+27: * FreeRTOS provides completely free yet professionally developed, *\r
+28: * robust, strictly quality controlled, supported, and cross *\r
+29: * platform software that is more than just the market leader, it *\r
+30: * is the industry's de facto standard. *\r
+31: * *\r
+32: * Help yourself get started quickly while simultaneously helping *\r
+33: * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+34: * tutorial book, reference manual, or both: *\r
+35: * http://www.FreeRTOS.org/Documentation *\r
+36: * *\r
+37: ***************************************************************************\r
+38: \r
+39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+40: the FAQ page "My application does not run, what could be wrong?". Have you\r
+41: defined configASSERT()?\r
+42: \r
+43: http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+44: embedded software for free we request you assist our global community by\r
+45: participating in the support forum.\r
+46: \r
+47: http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+48: be as productive as possible as early as possible. Now you can receive\r
+49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+50: Ltd, and the world's leading authority on the world's leading RTOS.\r
+51: \r
+52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+54: compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+55: \r
+56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+58: \r
+59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+61: licenses offer ticketed support, indemnification and commercial middleware.\r
+62: \r
+63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+64: engineered and independently SIL3 certified version for use in safety and\r
+65: mission critical applications that require provable dependability.\r
+66: \r
+67: 1 tab == 4 spaces!\r
+68: */\r
+69: \r
+70: /* Standard includes. */\r
+71: #include <stdlib.h>\r
+72: #include <string.h>\r
+73: \r
+74: /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+75: all the API functions to use the MPU wrappers. That should only be done when\r
+76: task.h is included from an application file. */\r
+77: #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+78: \r
+79: /* FreeRTOS includes. */\r
+80: #include "FreeRTOS.h"\r
+81: #include "task.h"\r
+82: #include "timers.h"\r
+83: #include "StackMacros.h"\r
+84: \r
+85: /* Lint e961 and e750 are suppressed as a MISRA exception justified because the\r
+86: MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the\r
+87: header files above, but not in this file, in order to generate the correct\r
+88: privileged Vs unprivileged linkage and placement. */\r
+89: #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */\r
+90: \r
+91: /* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting\r
+92: functions but without including stdio.h here. */\r
+93: #if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )\r
+94: /* At the bottom of this file are two optional functions that can be used\r
+95: to generate human readable text from the raw data generated by the\r
+96: uxTaskGetSystemState() function. Note the formatting functions are provided\r
+97: for convenience only, and are NOT considered part of the kernel. */\r
+98: #include <stdio.h>\r
+99: #endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */\r
+100: \r
+101: /* Sanity check the configuration. */\r
+102: #if( configUSE_TICKLESS_IDLE != 0 )\r
+103: #if( INCLUDE_vTaskSuspend != 1 )\r
+104: #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0\r
+105: #endif /* INCLUDE_vTaskSuspend */\r
+106: #endif /* configUSE_TICKLESS_IDLE */\r
+107: \r
+108: /*\r
+109: * Defines the size, in words, of the stack allocated to the idle task.\r
+110: */\r
+111: #define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE\r
+112: \r
+113: #if( configUSE_PREEMPTION == 0 )\r
+114: /* If the cooperative scheduler is being used then a yield should not be\r
+115: performed just because a higher priority task has been woken. */\r
+116: #define taskYIELD_IF_USING_PREEMPTION()\r
+117: #else\r
+118: #define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()\r
+119: #endif\r
+120: \r
+121: /* Value that can be assigned to the eNotifyState member of the TCB. */\r
+122: typedef enum\r
+123: {\r
+124: eNotWaitingNotification = 0,\r
+125: eWaitingNotification,\r
+126: eNotified\r
+127: } eNotifyValue;\r
+128: \r
+129: /*\r
+130: * Task control block. A task control block (TCB) is allocated for each task,\r
+131: * and stores task state information, including a pointer to the task's context\r
+132: * (the task's run time environment, including register values)\r
+133: */\r
+134: typedef struct tskTaskControlBlock\r
+135: {\r
+136: volatile StackType_t *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */\r
+137: \r
+138: #if ( portUSING_MPU_WRAPPERS == 1 )\r
+139: xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */\r
+140: BaseType_t xUsingStaticallyAllocatedStack; /* Set to pdTRUE if the stack is a statically allocated array, and pdFALSE if the stack is dynamically allocated. */\r
+141: #endif\r
+142: \r
+143: ListItem_t xGenericListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */\r
+144: ListItem_t xEventListItem; /*< Used to reference a task from an event list. */\r
+145: UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */\r
+146: StackType_t *pxStack; /*< Points to the start of the stack. */\r
+147: char pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r
+148: \r
+149: #if ( portSTACK_GROWTH > 0 )\r
+150: StackType_t *pxEndOfStack; /*< Points to the end of the stack on architectures where the stack grows up from low memory. */\r
+151: #endif\r
+152: \r
+153: #if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
+154: UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */\r
+155: #endif\r
+156: \r
+157: #if ( configUSE_TRACE_FACILITY == 1 )\r
+158: UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */\r
+159: UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */\r
+160: #endif\r
+161: \r
+162: #if ( configUSE_MUTEXES == 1 )\r
+163: UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */\r
+164: UBaseType_t uxMutexesHeld;\r
+165: #endif\r
+166: \r
+167: #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+168: TaskHookFunction_t pxTaskTag;\r
+169: #endif\r
+170: \r
+171: #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )\r
+172: void *pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];\r
+173: #endif\r
+174: \r
+175: #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+176: uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */\r
+177: #endif\r
+178: \r
+179: #if ( configUSE_NEWLIB_REENTRANT == 1 )\r
+180: /* Allocate a Newlib reent structure that is specific to this task.\r
+181: Note Newlib support has been included by popular demand, but is not\r
+182: used by the FreeRTOS maintainers themselves. FreeRTOS is not\r
+183: responsible for resulting newlib operation. User must be familiar with\r
+184: newlib and must provide system-wide implementations of the necessary\r
+185: stubs. Be warned that (at the time of writing) the current newlib design\r
+186: implements a system-wide malloc() that must be provided with locks. */\r
+187: struct _reent xNewLib_reent;\r
+188: #endif\r
+189: \r
+190: #if ( configUSE_TASK_NOTIFICATIONS == 1 )\r
+191: volatile uint32_t ulNotifiedValue;\r
+192: volatile eNotifyValue eNotifyState;\r
+193: #endif\r
+194: \r
+195: } tskTCB;\r
+196: \r
+197: /* The old tskTCB name is maintained above then typedefed to the new TCB_t name\r
+198: below to enable the use of older kernel aware debuggers. */\r
+199: typedef tskTCB TCB_t;\r
+200: \r
+201: /*\r
+202: * Some kernel aware debuggers require the data the debugger needs access to to\r
+203: * be global, rather than file scope.\r
+204: */\r
+205: #ifdef portREMOVE_STATIC_QUALIFIER\r
+206: #define static\r
+207: #endif\r
+208: \r
+209: /*lint -e956 A manual analysis and inspection has been used to determine which\r
+210: static variables must be declared volatile. */\r
+211: \r
+212: PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;\r
+213: \r
+214: /* Lists for ready and blocked tasks. --------------------*/\r
+215: PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */\r
+216: PRIVILEGED_DATA static List_t xDelayedTaskList1; /*< Delayed tasks. */\r
+217: PRIVILEGED_DATA static List_t xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */\r
+218: PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */\r
+219: PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */\r
+220: PRIVILEGED_DATA static List_t xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */\r
+221: \r
+222: #if ( INCLUDE_vTaskDelete == 1 )\r
+223: \r
+224: PRIVILEGED_DATA static List_t xTasksWaitingTermination; /*< Tasks that have been deleted - but their memory not yet freed. */\r
+225: PRIVILEGED_DATA static volatile UBaseType_t uxTasksDeleted = ( UBaseType_t ) 0U;\r
+226: \r
+227: #endif\r
+228: \r
+229: #if ( INCLUDE_vTaskSuspend == 1 )\r
+230: \r
+231: PRIVILEGED_DATA static List_t xSuspendedTaskList; /*< Tasks that are currently suspended. */\r
+232: \r
+233: #endif\r
+234: \r
+235: #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
+236: \r
+237: PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL; /*< Holds the handle of the idle task. The idle task is created automatically when the scheduler is started. */\r
+238: \r
+239: #endif\r
+240: \r
+241: /* Other file private variables. --------------------------------*/\r
+242: PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;\r
+243: PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) 0U;\r
+244: PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY;\r
+245: PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE;\r
+246: PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks = ( UBaseType_t ) 0U;\r
+247: PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE;\r
+248: PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0;\r
+249: PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U;\r
+250: PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY; before the scheduler starts. */\r
+251: \r
+252: /* Context switches are held pending while the scheduler is suspended. Also,\r
+253: interrupts must not manipulate the xGenericListItem of a TCB, or any of the\r
+254: lists the xGenericListItem can be referenced from, if the scheduler is suspended.\r
+255: If an interrupt needs to unblock a task while the scheduler is suspended then it\r
+256: moves the task's event list item into the xPendingReadyList, ready for the\r
+257: kernel to move the task from the pending ready list into the real ready list\r
+258: when the scheduler is unsuspended. The pending ready list itself can only be\r
+259: accessed from a critical section. */\r
+260: PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) pdFALSE;\r
+261: \r
+262: #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+263: \r
+264: PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */\r
+265: PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */\r
+266: \r
+267: #endif\r
+268: \r
+269: /*lint +e956 */\r
+270: \r
+271: /* Debugging and trace facilities private variables and macros. ------------*/\r
+272: \r
+273: /*\r
+274: * The value used to fill the stack of a task when the task is created. This\r
+275: * is used purely for checking the high water mark for tasks.\r
+276: */\r
+277: #define tskSTACK_FILL_BYTE ( 0xa5U )\r
+278: \r
+279: /*\r
+280: * Macros used by vListTask to indicate which state a task is in.\r
+281: */\r
+282: #define tskBLOCKED_CHAR ( 'B' )\r
+283: #define tskREADY_CHAR ( 'R' )\r
+284: #define tskDELETED_CHAR ( 'D' )\r
+285: #define tskSUSPENDED_CHAR ( 'S' )\r
+286: \r
+287: /*-----------------------------------------------------------*/\r
+288: \r
+289: #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )\r
+290: \r
+291: /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is\r
+292: performed in a generic way that is not optimised to any particular\r
+293: microcontroller architecture. */\r
+294: \r
+295: /* uxTopReadyPriority holds the priority of the highest priority ready\r
+296: state task. */\r
+297: #define taskRECORD_READY_PRIORITY( uxPriority ) \\r
+298: { \\r
+299: if( ( uxPriority ) > uxTopReadyPriority ) \\r
+300: { \\r
+301: uxTopReadyPriority = ( uxPriority ); \\r
+302: } \\r
+303: } /* taskRECORD_READY_PRIORITY */\r
+304: \r
+305: /*-----------------------------------------------------------*/\r
+306: \r
+307: #define taskSELECT_HIGHEST_PRIORITY_TASK() \\r
+308: { \\r
+309: /* Find the highest priority queue that contains ready tasks. */ \\r
+310: while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) \\r
+311: { \\r
+312: configASSERT( uxTopReadyPriority ); \\r
+313: --uxTopReadyPriority; \\r
+314: } \\r
+315: \\r
+316: /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \\r
+317: the same priority get an equal share of the processor time. */ \\r
+318: listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); \\r
+319: } /* taskSELECT_HIGHEST_PRIORITY_TASK */\r
+320: \r
+321: /*-----------------------------------------------------------*/\r
+322: \r
+323: /* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as\r
+324: they are only required when a port optimised method of task selection is\r
+325: being used. */\r
+326: #define taskRESET_READY_PRIORITY( uxPriority )\r
+327: #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )\r
+328: \r
+329: #else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+330: \r
+331: /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is\r
+332: performed in a way that is tailored to the particular microcontroller\r
+333: architecture being used. */\r
+334: \r
+335: /* A port optimised version is provided. Call the port defined macros. */\r
+336: #define taskRECORD_READY_PRIORITY( uxPriority ) portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )\r
+337: \r
+338: /*-----------------------------------------------------------*/\r
+339: \r
+340: #define taskSELECT_HIGHEST_PRIORITY_TASK() \\r
+341: { \\r
+342: UBaseType_t uxTopPriority; \\r
+343: \\r
+344: /* Find the highest priority queue that contains ready tasks. */ \\r
+345: portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ); \\r
+346: configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \\r
+347: listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \\r
+348: } /* taskSELECT_HIGHEST_PRIORITY_TASK() */\r
+349: \r
+350: /*-----------------------------------------------------------*/\r
+351: \r
+352: /* A port optimised version is provided, call it only if the TCB being reset\r
+353: is being referenced from a ready list. If it is referenced from a delayed\r
+354: or suspended list then it won't be in a ready list. */\r
+355: #define taskRESET_READY_PRIORITY( uxPriority ) \\r
+356: { \\r
+357: if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \\r
+358: { \\r
+359: portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) ); \\r
+360: } \\r
+361: }\r
+362: \r
+363: #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+364: \r
+365: /*-----------------------------------------------------------*/\r
+366: \r
+367: /* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick\r
+368: count overflows. */\r
+369: #define taskSWITCH_DELAYED_LISTS() \\r
+370: { \\r
+371: List_t *pxTemp; \\r
+372: \\r
+373: /* The delayed tasks list should be empty when the lists are switched. */ \\r
+374: configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) ); \\r
+375: \\r
+376: pxTemp = pxDelayedTaskList; \\r
+377: pxDelayedTaskList = pxOverflowDelayedTaskList; \\r
+378: pxOverflowDelayedTaskList = pxTemp; \\r
+379: xNumOfOverflows++; \\r
+380: prvResetNextTaskUnblockTime(); \\r
+381: }\r
+382: \r
+383: /*-----------------------------------------------------------*/\r
+384: \r
+385: /*\r
+386: * Place the task represented by pxTCB into the appropriate ready list for\r
+387: * the task. It is inserted at the end of the list.\r
+388: */\r
+389: #define prvAddTaskToReadyList( pxTCB ) \\r
+390: traceMOVED_TASK_TO_READY_STATE( pxTCB ); \\r
+391: taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority ); \\r
+392: vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xGenericListItem ) )\r
+393: /*-----------------------------------------------------------*/\r
+394: \r
+395: /*\r
+396: * Several functions take an TaskHandle_t parameter that can optionally be NULL,\r
+397: * where NULL is used to indicate that the handle of the currently executing\r
+398: * task should be used in place of the parameter. This macro simply checks to\r
+399: * see if the parameter is NULL and returns a pointer to the appropriate TCB.\r
+400: */\r
+401: #define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( TCB_t * ) pxCurrentTCB : ( TCB_t * ) ( pxHandle ) )\r
+402: \r
+403: /* The item value of the event list item is normally used to hold the priority\r
+404: of the task to which it belongs (coded to allow it to be held in reverse\r
+405: priority order). However, it is occasionally borrowed for other purposes. It\r
+406: is important its value is not updated due to a task priority change while it is\r
+407: being used for another purpose. The following bit definition is used to inform\r
+408: the scheduler that the value should not be changed - in which case it is the\r
+409: responsibility of whichever module is using the value to ensure it gets set back\r
+410: to its original value when it is released. */\r
+411: #if configUSE_16_BIT_TICKS == 1\r
+412: #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x8000U\r
+413: #else\r
+414: #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x80000000UL\r
+415: #endif\r
+416: \r
+417: /* Callback function prototypes. --------------------------*/\r
+418: #if configCHECK_FOR_STACK_OVERFLOW > 0\r
+419: extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );\r
+420: #endif\r
+421: \r
+422: #if configUSE_TICK_HOOK > 0\r
+423: extern void vApplicationTickHook( void );\r
+424: #endif\r
+425: \r
+426: /* File private functions. --------------------------------*/\r
+427: \r
+428: /*\r
+429: * Utility to ready a TCB for a given task. Mainly just copies the parameters\r
+430: * into the TCB structure.\r
+431: */\r
+432: static void prvInitialiseTCBVariables( TCB_t * const pxTCB, const char * const pcName, UBaseType_t uxPriority, const MemoryRegion_t * const xRegions, const uint16_t usStackDepth ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r
+433: \r
+434: /**\r
+435: * Utility task that simply returns pdTRUE if the task referenced by xTask is\r
+436: * currently in the Suspended state, or pdFALSE if the task referenced by xTask\r
+437: * is in any other state.\r
+438: */\r
+439: #if ( INCLUDE_vTaskSuspend == 1 )\r
+440: static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\r
+441: #endif /* INCLUDE_vTaskSuspend */\r
+442: \r
+443: /*\r
+444: * Utility to ready all the lists used by the scheduler. This is called\r
+445: * automatically upon the creation of the first task.\r
+446: */\r
+447: static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;\r
+448: \r
+449: /*\r
+450: * The idle task, which as all tasks is implemented as a never ending loop.\r
+451: * The idle task is automatically created and added to the ready lists upon\r
+452: * creation of the first user task.\r
+453: *\r
+454: * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific\r
+455: * language extensions. The equivalent prototype for this function is:\r
+456: *\r
+457: * void prvIdleTask( void *pvParameters );\r
+458: *\r
+459: */\r
+460: static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );\r
+461: \r
+462: /*\r
+463: * Utility to free all memory allocated by the scheduler to hold a TCB,\r
+464: * including the stack pointed to by the TCB.\r
+465: *\r
+466: * This does not free memory allocated by the task itself (i.e. memory\r
+467: * allocated by calls to pvPortMalloc from within the tasks application code).\r
+468: */\r
+469: #if ( INCLUDE_vTaskDelete == 1 )\r
+470: \r
+471: static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;\r
+472: \r
+473: #endif\r
+474: \r
+475: /*\r
+476: * Used only by the idle task. This checks to see if anything has been placed\r
+477: * in the list of tasks waiting to be deleted. If so the task is cleaned up\r
+478: * and its TCB deleted.\r
+479: */\r
+480: static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;\r
+481: \r
+482: /*\r
+483: * The currently executing task is entering the Blocked state. Add the task to\r
+484: * either the current or the overflow delayed task list.\r
+485: */\r
+486: static void prvAddCurrentTaskToDelayedList( const TickType_t xTimeToWake ) PRIVILEGED_FUNCTION;\r
+487: \r
+488: /*\r
+489: * Allocates memory from the heap for a TCB and associated stack. Checks the\r
+490: * allocation was successful.\r
+491: */\r
+492: static TCB_t *prvAllocateTCBAndStack( const uint16_t usStackDepth, StackType_t * const puxStackBuffer ) PRIVILEGED_FUNCTION;\r
+493: \r
+494: /*\r
+495: * Fills an TaskStatus_t structure with information on each task that is\r
+496: * referenced from the pxList list (which may be a ready list, a delayed list,\r
+497: * a suspended list, etc.).\r
+498: *\r
+499: * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM\r
+500: * NORMAL APPLICATION CODE.\r
+501: */\r
+502: #if ( configUSE_TRACE_FACILITY == 1 )\r
+503: \r
+504: static UBaseType_t prvListTaskWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;\r
+505: \r
+506: #endif\r
+507: \r
+508: /*\r
+509: * When a task is created, the stack of the task is filled with a known value.\r
+510: * This function determines the 'high water mark' of the task stack by\r
+511: * determining how much of the stack remains at the original preset value.\r
+512: */\r
+513: #if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )\r
+514: \r
+515: static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;\r
+516: \r
+517: #endif\r
+518: \r
+519: /*\r
+520: * Return the amount of time, in ticks, that will pass before the kernel will\r
+521: * next move a task from the Blocked state to the Running state.\r
+522: *\r
+523: * This conditional compilation should use inequality to 0, not equality to 1.\r
+524: * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user\r
+525: * defined low power mode implementations require configUSE_TICKLESS_IDLE to be\r
+526: * set to a value other than 1.\r
+527: */\r
+528: #if ( configUSE_TICKLESS_IDLE != 0 )\r
+529: \r
+530: static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;\r
+531: \r
+532: #endif\r
+533: \r
+534: /*\r
+535: * Set xNextTaskUnblockTime to the time at which the next Blocked state task\r
+536: * will exit the Blocked state.\r
+537: */\r
+538: static void prvResetNextTaskUnblockTime( void );\r
+539: \r
+540: #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\r
+541: \r
+542: /*\r
+543: * Helper function used to pad task names with spaces when printing out\r
+544: * human readable tables of task information.\r
+545: */\r
+546: static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName );\r
+547: \r
+548: #endif\r
+549: /*-----------------------------------------------------------*/\r
+550: \r
+551: BaseType_t xTaskGenericCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, StackType_t * const puxStackBuffer, const MemoryRegion_t * const xRegions ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r
+552: {\r
+BFD01534 4FE9 ADDIU SP, SP, -48
+BFD01536 CBEB SW RA, 44(SP)
+BFD01538 CBCA SW S8, 40(SP)
+BFD0153A 0FDD MOVE S8, SP
+BFD0153C 0030F89E SW A0, 48(S8)
+BFD01540 0034F8BE SW A1, 52(S8)
+BFD01544 0C46 MOVE V0, A2
+BFD01546 003CF8FE SW A3, 60(S8)
+BFD0154A 0038385E SH V0, 56(S8)
+553: BaseType_t xReturn;\r
+554: TCB_t * pxNewTCB;\r
+555: StackType_t *pxTopOfStack;\r
+556: \r
+557: configASSERT( pxTaskCode );\r
+BFD0154E 0030FC5E LW V0, 48(S8)
+BFD01552 000940A2 BNEZC V0, 0xBFD01568
+BFD01556 BFD141A2 LUI V0, 0xBFD1
+BFD01558 3082BFD1 LDC1 F30, 12418(S1)
+BFD0155A 98103082 ADDIU A0, V0, -26608
+BFD0155C 30A09810 SWC1 F0, 12448(S0)
+BFD0155E 022D30A0 ADDIU A1, ZERO, 557
+BFD01562 4B7E77E8 JALS vAssertCalled
+BFD01564 4B7E LW K1, 120(SP)
+BFD01566 0C00 NOP
+558: configASSERT( ( ( uxPriority & ( UBaseType_t ) ( ~portPRIVILEGE_BIT ) ) < ( UBaseType_t ) configMAX_PRIORITIES ) );\r
+BFD01568 0040FC5E LW V0, 64(S8)
+BFD0156C 0005B042 SLTIU V0, V0, 5
+BFD01570 000940A2 BNEZC V0, 0xBFD01586
+BFD01574 BFD141A2 LUI V0, 0xBFD1
+BFD01576 3082BFD1 LDC1 F30, 12418(S1)
+BFD01578 98103082 ADDIU A0, V0, -26608
+BFD0157A 30A09810 SWC1 F0, 12448(S0)
+BFD0157C 022E30A0 ADDIU A1, ZERO, 558
+BFD01580 4B7E77E8 JALS vAssertCalled
+BFD01582 4B7E LW K1, 120(SP)
+BFD01584 0C00 NOP
+559: \r
+560: /* Allocate the memory required by the TCB and stack for the new task,\r
+561: checking that the allocation was successful. */\r
+562: pxNewTCB = prvAllocateTCBAndStack( usStackDepth, puxStackBuffer );\r
+BFD01586 0038345E LHU V0, 56(S8)
+BFD0158A 0C82 MOVE A0, V0
+BFD0158C 0048FCBE LW A1, 72(S8)
+BFD01590 319477E8 JALS prvAllocateTCBAndStack
+BFD01592 0C003194 ADDIU T4, S4, 3072
+BFD01594 0C00 NOP
+BFD01596 001CF85E SW V0, 28(S8)
+563: \r
+564: if( pxNewTCB != NULL )\r
+BFD0159A 001CFC5E LW V0, 28(S8)
+BFD0159E 009A40E2 BEQZC V0, 0xBFD016D6
+565: {\r
+566: #if( portUSING_MPU_WRAPPERS == 1 )\r
+567: /* Should the task be created in privileged mode? */\r
+568: BaseType_t xRunPrivileged;\r
+569: if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )\r
+570: {\r
+571: xRunPrivileged = pdTRUE;\r
+572: }\r
+573: else\r
+574: {\r
+575: xRunPrivileged = pdFALSE;\r
+576: }\r
+577: uxPriority &= ~portPRIVILEGE_BIT;\r
+578: \r
+579: if( puxStackBuffer != NULL )\r
+580: {\r
+581: /* The application provided its own stack. Note this so no\r
+582: attempt is made to delete the stack should that task be\r
+583: deleted. */\r
+584: pxNewTCB->xUsingStaticallyAllocatedStack = pdTRUE;\r
+585: }\r
+586: else\r
+587: {\r
+588: /* The stack was allocated dynamically. Note this so it can be\r
+589: deleted again if the task is deleted. */\r
+590: pxNewTCB->xUsingStaticallyAllocatedStack = pdFALSE;\r
+591: }\r
+592: #endif /* portUSING_MPU_WRAPPERS == 1 */\r
+593: \r
+594: /* Calculate the top of stack address. This depends on whether the\r
+595: stack grows from high memory to low (as per the 80x86) or vice versa.\r
+596: portSTACK_GROWTH is used to make the result positive or negative as\r
+597: required by the port. */\r
+598: #if( portSTACK_GROWTH < 0 )\r
+599: {\r
+600: pxTopOfStack = pxNewTCB->pxStack + ( usStackDepth - ( uint16_t ) 1 );\r
+BFD015A2 001CFC5E LW V0, 28(S8)
+BFD015A4 69AC001C EXT ZERO, GP, 6, 14
+BFD015A6 69AC LW V1, 48(V0)
+BFD015A8 0038345E LHU V0, 56(S8)
+BFD015AC 6D2E ADDIU V0, V0, -1
+BFD015AE 2524 SLL V0, V0, 2
+BFD015B0 0526 ADDU V0, V1, V0
+BFD015B2 0020F85E SW V0, 32(S8)
+601: pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. */\r
+BFD015B6 0020FC7E LW V1, 32(S8)
+BFD015B8 30400020 SRL AT, ZERO, 6
+BFD015BA FFF83040 ADDIU V0, ZERO, -8
+BFD015BC 4493FFF8 LW RA, 17555(T8)
+BFD015BE 4493 AND16 V0, V1
+BFD015C0 0020F85E SW V0, 32(S8)
+602: \r
+603: /* Check the alignment of the calculated top of stack is correct. */\r
+604: configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\r
+BFD015C4 0020FC5E LW V0, 32(S8)
+BFD015C8 2D25 ANDI V0, V0, 0x7
+BFD015CA 000940E2 BEQZC V0, 0xBFD015E0
+BFD015CE BFD141A2 LUI V0, 0xBFD1
+BFD015D0 3082BFD1 LDC1 F30, 12418(S1)
+BFD015D2 98103082 ADDIU A0, V0, -26608
+BFD015D4 30A09810 SWC1 F0, 12448(S0)
+BFD015D6 025C30A0 ADDIU A1, ZERO, 604
+BFD015DA 4B7E77E8 JALS vAssertCalled
+BFD015DC 4B7E LW K1, 120(SP)
+BFD015DE 0C00 NOP
+605: }\r
+606: #else /* portSTACK_GROWTH */\r
+607: {\r
+608: pxTopOfStack = pxNewTCB->pxStack;\r
+609: \r
+610: /* Check the alignment of the stack buffer is correct. */\r
+611: configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\r
+612: \r
+613: /* If we want to use stack checking on architectures that use\r
+614: a positive stack growth direction then we also need to store the\r
+615: other extreme of the stack space. */\r
+616: pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( usStackDepth - 1 );\r
+617: }\r
+618: #endif /* portSTACK_GROWTH */\r
+619: \r
+620: /* Setup the newly allocated TCB with the initial state of the task. */\r
+621: prvInitialiseTCBVariables( pxNewTCB, pcName, uxPriority, xRegions, usStackDepth );\r
+BFD015E0 0038345E LHU V0, 56(S8)
+BFD015E4 C844 SW V0, 16(SP)
+BFD015E6 001CFC9E LW A0, 28(S8)
+BFD015EA 0034FCBE LW A1, 52(S8)
+BFD015EE 0040FCDE LW A2, 64(S8)
+BFD015F2 004CFCFE LW A3, 76(S8)
+BFD015F6 1E7477E8 JALS prvInitialiseTCBVariables
+BFD015F8 0C001E74 LB S3, 3072(S4)
+BFD015FA 0C00 NOP
+622: \r
+623: /* Initialize the TCB stack to look as if the task was already running,\r
+624: but had been interrupted by the scheduler. The return address is set\r
+625: to the start of the task function. Once the stack has been initialised\r
+626: the top of stack variable is updated. */\r
+627: #if( portUSING_MPU_WRAPPERS == 1 )\r
+628: {\r
+629: pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );\r
+630: }\r
+631: #else /* portUSING_MPU_WRAPPERS */\r
+632: {\r
+633: pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );\r
+BFD015FC 0020FC9E LW A0, 32(S8)
+BFD01600 0030FCBE LW A1, 48(S8)
+BFD01604 003CFCDE LW A2, 60(S8)
+BFD01608 2B1877E8 JALS pxPortInitialiseStack
+BFD0160A 2B18 LHU A2, 16(S1)
+BFD0160C 0C00 NOP
+BFD0160E 0C62 MOVE V1, V0
+BFD01610 001CFC5E LW V0, 28(S8)
+BFD01614 E9A0 SW V1, 0(V0)
+634: }\r
+635: #endif /* portUSING_MPU_WRAPPERS */\r
+636: \r
+637: if( ( void * ) pxCreatedTask != NULL )\r
+BFD01616 0044FC5E LW V0, 68(S8)
+BFD0161A 000540E2 BEQZC V0, 0xBFD01628
+638: {\r
+639: /* Pass the TCB out - in an anonymous way. The calling function/\r
+640: task can use this as a handle to delete the task later if\r
+641: required.*/\r
+642: *pxCreatedTask = ( TaskHandle_t ) pxNewTCB;\r
+BFD0161E 0044FC5E LW V0, 68(S8)
+BFD01622 001CFC7E LW V1, 28(S8)
+BFD01626 E9A0 SW V1, 0(V0)
+643: }\r
+644: else\r
+645: {\r
+646: mtCOVERAGE_TEST_MARKER();\r
+647: }\r
+648: \r
+649: /* Ensure interrupts don't access the task lists while they are being\r
+650: updated. */\r
+651: taskENTER_CRITICAL();\r
+BFD01628 33B877E8 JALS vTaskEnterCritical
+BFD0162A 0C0033B8 ADDIU SP, T8, 3072
+BFD0162C 0C00 NOP
+652: {\r
+653: uxCurrentNumberOfTasks++;\r
+BFD0162E 8038FC5C LW V0, -32712(GP)
+BFD01632 6D20 ADDIU V0, V0, 1
+BFD01634 8038F85C SW V0, -32712(GP)
+654: if( pxCurrentTCB == NULL )\r
+BFD01638 8030FC5C LW V0, -32720(GP)
+BFD0163C 000F40A2 BNEZC V0, 0xBFD0165E
+655: {\r
+656: /* There are no other tasks, or all the other tasks are in\r
+657: the suspended state - make this the current task. */\r
+658: pxCurrentTCB = pxNewTCB;\r
+BFD01640 001CFC5E LW V0, 28(S8)
+BFD01644 8030F85C SW V0, -32720(GP)
+659: \r
+660: if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )\r
+BFD01648 8038FC7C LW V1, -32712(GP)
+BFD0164C ED01 LI V0, 1
+BFD0164E 0017B443 BNE V1, V0, 0xBFD01680
+BFD01650 0C000017 SLL ZERO, S7, 1
+BFD01652 0C00 NOP
+661: {\r
+662: /* This is the first task to be created so do the preliminary\r
+663: initialisation required. We will not recover if this call\r
+664: fails, but we will report the failure. */\r
+665: prvInitialiseTaskLists();\r
+BFD01654 309677E8 JALS prvInitialiseTaskLists
+BFD01656 0C003096 ADDIU A0, S6, 3072
+BFD01658 0C00 NOP
+BFD0165A CC12 B 0xBFD01680
+BFD0165C 0C00 NOP
+666: }\r
+667: else\r
+668: {\r
+669: mtCOVERAGE_TEST_MARKER();\r
+670: }\r
+671: }\r
+672: else\r
+673: {\r
+674: /* If the scheduler is not already running, make this task the\r
+675: current task if it is the highest priority task to be created\r
+676: so far. */\r
+677: if( xSchedulerRunning == pdFALSE )\r
+BFD0165E 8044FC5C LW V0, -32700(GP)
+BFD01662 000D40A2 BNEZC V0, 0xBFD01680
+678: {\r
+679: if( pxCurrentTCB->uxPriority <= uxPriority )\r
+BFD01666 8030FC5C LW V0, -32720(GP)
+BFD0166A 69AB LW V1, 44(V0)
+BFD0166C 0040FC5E LW V0, 64(S8)
+BFD01670 13900062 SLTU V0, V0, V1
+BFD01672 40A21390 ADDI GP, S0, 16546
+BFD01674 000440A2 BNEZC V0, 0xBFD01680
+680: {\r
+681: pxCurrentTCB = pxNewTCB;\r
+BFD01678 001CFC5E LW V0, 28(S8)
+BFD0167C 8030F85C SW V0, -32720(GP)
+682: }\r
+683: else\r
+684: {\r
+685: mtCOVERAGE_TEST_MARKER();\r
+686: }\r
+687: }\r
+688: else\r
+689: {\r
+690: mtCOVERAGE_TEST_MARKER();\r
+691: }\r
+692: }\r
+693: \r
+694: uxTaskNumber++;\r
+BFD01680 8054FC5C LW V0, -32684(GP)
+BFD01684 6D20 ADDIU V0, V0, 1
+BFD01686 8054F85C SW V0, -32684(GP)
+695: \r
+696: #if ( configUSE_TRACE_FACILITY == 1 )\r
+697: {\r
+698: /* Add a counter into the TCB for tracing only. */\r
+699: pxNewTCB->uxTCBNumber = uxTaskNumber;\r
+700: }\r
+701: #endif /* configUSE_TRACE_FACILITY */\r
+702: traceTASK_CREATE( pxNewTCB );\r
+703: \r
+704: prvAddTaskToReadyList( pxNewTCB );\r
+BFD0168A 001CFC5E LW V0, 28(S8)
+BFD0168E 692B LW V0, 44(V0)
+BFD01690 ED81 LI V1, 1
+BFD01692 18100062 SLLV V1, V0, V1
+BFD01694 FC5C1810 SB ZERO, -932(S0)
+BFD01696 8040FC5C LW V0, -32704(GP)
+BFD0169A 44D3 OR16 V0, V1
+BFD0169C 8040F85C SW V0, -32704(GP)
+BFD016A0 001CFC5E LW V0, 28(S8)
+BFD016A4 692B LW V0, 44(V0)
+BFD016A6 2524 SLL V0, V0, 2
+BFD016A8 25A4 SLL V1, V0, 2
+BFD016AA 05B4 ADDU V1, V0, V1
+BFD016AC BFD241A2 LUI V0, 0xBFD2
+BFD016AE 3042BFD2 LDC1 F30, 12354(S2)
+BFD016B0 806C3042 ADDIU V0, V0, -32660
+BFD016B4 05A6 ADDU V1, V1, V0
+BFD016B6 001CFC5E LW V0, 28(S8)
+BFD016BA 6D22 ADDIU V0, V0, 4
+BFD016BC 0C83 MOVE A0, V1
+BFD016BE 0CA2 MOVE A1, V0
+BFD016C0 3E4A77E8 JALS vListInsertEnd
+BFD016C2 0C003E4A LH S2, 3072(T2)
+BFD016C4 0C00 NOP
+705: \r
+706: xReturn = pdPASS;\r
+BFD016C6 ED01 LI V0, 1
+BFD016C8 0018F85E SW V0, 24(S8)
+707: portSETUP_TCB( pxNewTCB );\r
+708: }\r
+709: taskEXIT_CRITICAL();\r
+BFD016CC 40AA77E8 JALS vTaskExitCritical
+BFD016CE 0C0040AA BNEZC T2, 0xBFD02ED2
+BFD016D0 0C00 NOP
+BFD016D2 CC04 B 0xBFD016DC
+BFD016D4 0C00 NOP
+710: }\r
+711: else\r
+712: {\r
+713: xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\r
+BFD016D6 ED7F LI V0, -1
+BFD016D8 0018F85E SW V0, 24(S8)
+714: traceTASK_CREATE_FAILED();\r
+715: }\r
+716: \r
+717: if( xReturn == pdPASS )\r
+BFD016DC 0018FC7E LW V1, 24(S8)
+BFD016E0 ED01 LI V0, 1
+BFD016E2 001EB443 BNE V1, V0, 0xBFD01722
+BFD016E4 0C00001E SLL ZERO, S8, 1
+BFD016E6 0C00 NOP
+718: {\r
+719: if( xSchedulerRunning != pdFALSE )\r
+BFD016E8 8044FC5C LW V0, -32700(GP)
+BFD016EC 001940E2 BEQZC V0, 0xBFD01722
+720: {\r
+721: /* If the created task is of a higher priority than the current task\r
+722: then it should run now. */\r
+723: if( pxCurrentTCB->uxPriority < uxPriority )\r
+BFD016F0 8030FC5C LW V0, -32720(GP)
+BFD016F4 69AB LW V1, 44(V0)
+BFD016F6 0040FC5E LW V0, 64(S8)
+BFD016FA 13900043 SLTU V0, V1, V0
+BFD016FC 40E21390 ADDI GP, S0, 16610
+BFD016FE 001040E2 BEQZC V0, 0xBFD01722
+724: {\r
+725: taskYIELD_IF_USING_PREEMPTION();\r
+BFD01702 4E5677E8 JALS ulPortGetCP0Cause
+BFD01704 4E56 ADDIU S2, S2, -5
+BFD01706 0C00 NOP
+BFD01708 0024F85E SW V0, 36(S8)
+BFD0170C 0024FC5E LW V0, 36(S8)
+BFD01710 01005042 ORI V0, V0, 256
+BFD01714 0024F85E SW V0, 36(S8)
+BFD01718 0024FC9E LW A0, 36(S8)
+BFD0171C 4E6677E8 JALS vPortSetCP0Cause
+BFD0171E 4E66 ADDIU S3, S3, 3
+BFD01720 0C00 NOP
+726: }\r
+727: else\r
+728: {\r
+729: mtCOVERAGE_TEST_MARKER();\r
+730: }\r
+731: }\r
+732: else\r
+733: {\r
+734: mtCOVERAGE_TEST_MARKER();\r
+735: }\r
+736: }\r
+737: \r
+738: return xReturn;\r
+BFD01722 0018FC5E LW V0, 24(S8)
+739: }\r
+BFD01726 0FBE MOVE SP, S8
+BFD01728 4BEB LW RA, 44(SP)
+BFD0172A 4BCA LW S8, 40(SP)
+BFD0172C 4C19 ADDIU SP, SP, 48
+BFD0172E 459F JR16 RA
+BFD01730 0C00 NOP
+740: /*-----------------------------------------------------------*/\r
+741: \r
+742: #if ( INCLUDE_vTaskDelete == 1 )\r
+743: \r
+744: void vTaskDelete( TaskHandle_t xTaskToDelete )\r
+745: {\r
+BFD033F4 4FF1 ADDIU SP, SP, -32
+BFD033F6 CBE7 SW RA, 28(SP)
+BFD033F8 CBC6 SW S8, 24(SP)
+BFD033FA 0FDD MOVE S8, SP
+BFD033FC 0020F89E SW A0, 32(S8)
+746: TCB_t *pxTCB;\r
+747: \r
+748: taskENTER_CRITICAL();\r
+BFD03400 33B877E8 JALS vTaskEnterCritical
+BFD03402 0C0033B8 ADDIU SP, T8, 3072
+BFD03404 0C00 NOP
+749: {\r
+750: /* If null is passed in here then it is the calling task that is\r
+751: being deleted. */\r
+752: pxTCB = prvGetTCBFromHandle( xTaskToDelete );\r
+BFD03406 0020FC5E LW V0, 32(S8)
+BFD0340A 000440A2 BNEZC V0, 0xBFD03416
+BFD0340E 8030FC5C LW V0, -32720(GP)
+BFD03412 CC03 B 0xBFD0341A
+BFD03414 0C00 NOP
+BFD03416 0020FC5E LW V0, 32(S8)
+BFD0341A 0010F85E SW V0, 16(S8)
+753: \r
+754: /* Remove task from the ready list and place in the termination list.\r
+755: This will stop the task from be scheduled. The idle task will check\r
+756: the termination list and free up any memory allocated by the\r
+757: scheduler for the TCB and stack. */\r
+758: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
+BFD0341E 0010FC5E LW V0, 16(S8)
+BFD03422 6D22 ADDIU V0, V0, 4
+BFD03424 0C82 MOVE A0, V0
+BFD03426 00C877E8 JALS uxListRemove
+BFD03428 0C0000C8 SLL A2, T0, 1
+BFD0342A 0C00 NOP
+BFD0342C 001A40A2 BNEZC V0, 0xBFD03464
+759: {\r
+760: taskRESET_READY_PRIORITY( pxTCB->uxPriority );\r
+BFD03430 0010FC5E LW V0, 16(S8)
+BFD03434 692B LW V0, 44(V0)
+BFD03436 2524 SLL V0, V0, 2
+BFD03438 25A4 SLL V1, V0, 2
+BFD0343A 05B4 ADDU V1, V0, V1
+BFD0343C BFD241A2 LUI V0, 0xBFD2
+BFD0343E 3042BFD2 LDC1 F30, 12354(S2)
+BFD03440 806C3042 ADDIU V0, V0, -32660
+BFD03444 0526 ADDU V0, V1, V0
+BFD03446 6920 LW V0, 0(V0)
+BFD03448 000C40A2 BNEZC V0, 0xBFD03464
+BFD0344C 0010FC5E LW V0, 16(S8)
+BFD03450 692B LW V0, 44(V0)
+BFD03452 ED81 LI V1, 1
+BFD03454 10100062 SLLV V0, V0, V1
+BFD03456 441A1010 ADDI ZERO, S0, 17434
+BFD03458 441A NOT16 V1, V0
+BFD0345A 8040FC5C LW V0, -32704(GP)
+BFD0345E 4493 AND16 V0, V1
+BFD03460 8040F85C SW V0, -32704(GP)
+761: }\r
+762: else\r
+763: {\r
+764: mtCOVERAGE_TEST_MARKER();\r
+765: }\r
+766: \r
+767: /* Is the task waiting on an event also? */\r
+768: if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\r
+BFD03464 0010FC5E LW V0, 16(S8)
+BFD03468 692A LW V0, 40(V0)
+BFD0346A 000740E2 BEQZC V0, 0xBFD0347C
+769: {\r
+770: ( void ) uxListRemove( &( pxTCB->xEventListItem ) );\r
+BFD0346E 0010FC5E LW V0, 16(S8)
+BFD03470 6D2C0010 EXT ZERO, S0, 20, 14
+BFD03472 6D2C ADDIU V0, V0, 24
+BFD03474 0C82 MOVE A0, V0
+BFD03476 00C877E8 JALS uxListRemove
+BFD03478 0C0000C8 SLL A2, T0, 1
+BFD0347A 0C00 NOP
+771: }\r
+772: else\r
+773: {\r
+774: mtCOVERAGE_TEST_MARKER();\r
+775: }\r
+776: \r
+777: vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) );\r
+BFD0347C 0010FC5E LW V0, 16(S8)
+BFD03480 6D22 ADDIU V0, V0, 4
+BFD03482 BFD241A3 LUI V1, 0xBFD2
+BFD03484 3083BFD2 LDC1 F30, 12419(S2)
+BFD03486 810C3083 ADDIU A0, V1, -32500
+BFD0348A 0CA2 MOVE A1, V0
+BFD0348C 3E4A77E8 JALS vListInsertEnd
+BFD0348E 0C003E4A LH S2, 3072(T2)
+BFD03490 0C00 NOP
+778: \r
+779: /* Increment the ucTasksDeleted variable so the idle task knows\r
+780: there is a task that has been deleted and that it should therefore\r
+781: check the xTasksWaitingTermination list. */\r
+782: ++uxTasksDeleted;\r
+BFD03492 8034FC5C LW V0, -32716(GP)
+BFD03496 6D20 ADDIU V0, V0, 1
+BFD03498 8034F85C SW V0, -32716(GP)
+783: \r
+784: /* Increment the uxTaskNumberVariable also so kernel aware debuggers\r
+785: can detect that the task lists need re-generating. */\r
+786: uxTaskNumber++;\r
+BFD0349C 8054FC5C LW V0, -32684(GP)
+BFD034A0 6D20 ADDIU V0, V0, 1
+BFD034A2 8054F85C SW V0, -32684(GP)
+787: \r
+788: traceTASK_DELETE( pxTCB );\r
+789: }\r
+790: taskEXIT_CRITICAL();\r
+BFD034A6 40AA77E8 JALS vTaskExitCritical
+BFD034A8 0C0040AA BNEZC T2, 0xBFD04CAC
+BFD034AA 0C00 NOP
+791: \r
+792: /* Force a reschedule if it is the currently running task that has just\r
+793: been deleted. */\r
+794: if( xSchedulerRunning != pdFALSE )\r
+BFD034AC 8044FC5C LW V0, -32700(GP)
+BFD034B0 002F40E2 BEQZC V0, 0xBFD03512
+795: {\r
+796: if( pxTCB == pxCurrentTCB )\r
+BFD034B4 8030FC5C LW V0, -32720(GP)
+BFD034B8 0010FC7E LW V1, 16(S8)
+BFD034BC 0020B443 BNE V1, V0, 0xBFD03500
+BFD034BE 0C000020 SLL AT, ZERO, 1
+BFD034C0 0C00 NOP
+797: {\r
+798: configASSERT( uxSchedulerSuspended == 0 );\r
+BFD034C2 805CFC5C LW V0, -32676(GP)
+BFD034C6 000940E2 BEQZC V0, 0xBFD034DC
+BFD034CA BFD141A2 LUI V0, 0xBFD1
+BFD034CC 3082BFD1 LDC1 F30, 12418(S1)
+BFD034CE 98103082 ADDIU A0, V0, -26608
+BFD034D0 30A09810 SWC1 F0, 12448(S0)
+BFD034D2 031E30A0 ADDIU A1, ZERO, 798
+BFD034D6 4B7E77E8 JALS vAssertCalled
+BFD034D8 4B7E LW K1, 120(SP)
+BFD034DA 0C00 NOP
+799: \r
+800: /* The pre-delete hook is primarily for the Windows simulator,\r
+801: in which Windows specific clean up operations are performed,\r
+802: after which it is not possible to yield away from this task -\r
+803: hence xYieldPending is used to latch that a context switch is\r
+804: required. */\r
+805: portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );\r
+806: portYIELD_WITHIN_API();\r
+BFD034DC 4E5677E8 JALS ulPortGetCP0Cause
+BFD034DE 4E56 ADDIU S2, S2, -5
+BFD034E0 0C00 NOP
+BFD034E2 0014F85E SW V0, 20(S8)
+BFD034E6 0014FC5E LW V0, 20(S8)
+BFD034EA 01005042 ORI V0, V0, 256
+BFD034EE 0014F85E SW V0, 20(S8)
+BFD034F2 0014FC9E LW A0, 20(S8)
+BFD034F6 4E6677E8 JALS vPortSetCP0Cause
+BFD034F8 4E66 ADDIU S3, S3, 3
+BFD034FA 0C00 NOP
+BFD034FC CC0A B 0xBFD03512
+BFD034FE 0C00 NOP
+807: }\r
+808: else\r
+809: {\r
+810: /* Reset the next expected unblock time in case it referred to\r
+811: the task that has just been deleted. */\r
+812: taskENTER_CRITICAL();\r
+BFD03500 33B877E8 JALS vTaskEnterCritical
+BFD03502 0C0033B8 ADDIU SP, T8, 3072
+BFD03504 0C00 NOP
+813: {\r
+814: prvResetNextTaskUnblockTime();\r
+BFD03506 47CA77E8 JALS prvResetNextTaskUnblockTime
+BFD0350A 0C00 NOP
+815: }\r
+816: taskEXIT_CRITICAL();\r
+BFD0350C 40AA77E8 JALS vTaskExitCritical
+BFD0350E 0C0040AA BNEZC T2, 0xBFD04D12
+BFD03510 0C00 NOP
+817: }\r
+818: }\r
+819: }\r
+BFD03512 0FBE MOVE SP, S8
+BFD03514 4BE7 LW RA, 28(SP)
+BFD03516 4BC6 LW S8, 24(SP)
+BFD03518 4C11 ADDIU SP, SP, 32
+BFD0351A 459F JR16 RA
+BFD0351C 0C00 NOP
+820: \r
+821: #endif /* INCLUDE_vTaskDelete */\r
+822: /*-----------------------------------------------------------*/\r
+823: \r
+824: #if ( INCLUDE_vTaskDelayUntil == 1 )\r
+825: \r
+826: void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )\r
+827: {\r
+BFD00008 4FE9 ADDIU SP, SP, -48
+BFD0000A CBEB SW RA, 44(SP)
+BFD0000C CBCA SW S8, 40(SP)
+BFD0000E 0FDD MOVE S8, SP
+BFD00010 0030F89E SW A0, 48(S8)
+BFD00014 0034F8BE SW A1, 52(S8)
+828: TickType_t xTimeToWake;\r
+829: BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;\r
+BFD00018 0010F81E SW ZERO, 16(S8)
+830: \r
+831: configASSERT( pxPreviousWakeTime );\r
+BFD0001C 0030FC5E LW V0, 48(S8)
+BFD00020 000940A2 BNEZC V0, 0xBFD00036
+BFD00024 BFD141A2 LUI V0, 0xBFD1
+BFD00026 3082BFD1 LDC1 F30, 12418(S1)
+BFD00028 98103082 ADDIU A0, V0, -26608
+BFD0002A 30A09810 SWC1 F0, 12448(S0)
+BFD0002C 033F30A0 ADDIU A1, ZERO, 831
+BFD00030 4B7E77E8 JALS vAssertCalled
+BFD00032 4B7E LW K1, 120(SP)
+BFD00034 0C00 NOP
+832: configASSERT( ( xTimeIncrement > 0U ) );\r
+BFD00036 0034FC5E LW V0, 52(S8)
+BFD0003A 000940A2 BNEZC V0, 0xBFD00050
+BFD0003E BFD141A2 LUI V0, 0xBFD1
+BFD00040 3082BFD1 LDC1 F30, 12418(S1)
+BFD00042 98103082 ADDIU A0, V0, -26608
+BFD00044 30A09810 SWC1 F0, 12448(S0)
+BFD00046 034030A0 ADDIU A1, ZERO, 832
+BFD0004A 4B7E77E8 JALS vAssertCalled
+BFD0004C 4B7E LW K1, 120(SP)
+BFD0004E 0C00 NOP
+833: configASSERT( uxSchedulerSuspended == 0 );\r
+BFD00050 805CFC5C LW V0, -32676(GP)
+BFD00054 000940E2 BEQZC V0, 0xBFD0006A
+BFD00058 BFD141A2 LUI V0, 0xBFD1
+BFD0005A 3082BFD1 LDC1 F30, 12418(S1)
+BFD0005C 98103082 ADDIU A0, V0, -26608
+BFD0005E 30A09810 SWC1 F0, 12448(S0)
+BFD00060 034130A0 ADDIU A1, ZERO, 833
+BFD00064 4B7E77E8 JALS vAssertCalled
+BFD00066 4B7E LW K1, 120(SP)
+BFD00068 0C00 NOP
+834: \r
+835: vTaskSuspendAll();\r
+BFD0006A 4EF477E8 JALS vTaskSuspendAll
+BFD0006C 4EF4 ADDIU S7, S7, -6
+BFD0006E 0C00 NOP
+836: {\r
+837: /* Minor optimisation. The tick count cannot change in this\r
+838: block. */\r
+839: const TickType_t xConstTickCount = xTickCount;\r
+BFD00070 803CFC5C LW V0, -32708(GP)
+BFD00074 0014F85E SW V0, 20(S8)
+840: \r
+841: /* Generate the tick time at which the task wants to wake. */\r
+842: xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;\r
+BFD00078 0030FC5E LW V0, 48(S8)
+BFD0007C 69A0 LW V1, 0(V0)
+BFD0007E 0034FC5E LW V0, 52(S8)
+BFD00082 0526 ADDU V0, V1, V0
+BFD00084 0018F85E SW V0, 24(S8)
+843: \r
+844: if( xConstTickCount < *pxPreviousWakeTime )\r
+BFD00088 0030FC5E LW V0, 48(S8)
+BFD0008C 69A0 LW V1, 0(V0)
+BFD0008E 0014FC5E LW V0, 20(S8)
+BFD00092 13900062 SLTU V0, V0, V1
+BFD00094 40E21390 ADDI GP, S0, 16610
+BFD00096 001640E2 BEQZC V0, 0xBFD000C6
+845: {\r
+846: /* The tick count has overflowed since this function was\r
+847: lasted called. In this case the only time we should ever\r
+848: actually delay is if the wake time has also overflowed,\r
+849: and the wake time is greater than the tick time. When this\r
+850: is the case it is as if neither time had overflowed. */\r
+851: if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )\r
+BFD0009A 0030FC5E LW V0, 48(S8)
+BFD0009E 69A0 LW V1, 0(V0)
+BFD000A0 0018FC5E LW V0, 24(S8)
+BFD000A4 13900062 SLTU V0, V0, V1
+BFD000A6 40E21390 ADDI GP, S0, 16610
+BFD000A8 002140E2 BEQZC V0, 0xBFD000EE
+BFD000AC 0018FC7E LW V1, 24(S8)
+BFD000B0 0014FC5E LW V0, 20(S8)
+BFD000B4 13900062 SLTU V0, V0, V1
+BFD000B6 40E21390 ADDI GP, S0, 16610
+BFD000B8 001940E2 BEQZC V0, 0xBFD000EE
+852: {\r
+853: xShouldDelay = pdTRUE;\r
+BFD000BC ED01 LI V0, 1
+BFD000BE 0010F85E SW V0, 16(S8)
+BFD000C2 CC15 B 0xBFD000EE
+BFD000C4 0C00 NOP
+854: }\r
+855: else\r
+856: {\r
+857: mtCOVERAGE_TEST_MARKER();\r
+858: }\r
+859: }\r
+860: else\r
+861: {\r
+862: /* The tick time has not overflowed. In this case we will\r
+863: delay if either the wake time has overflowed, and/or the\r
+864: tick time is less than the wake time. */\r
+865: if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )\r
+BFD000C6 0030FC5E LW V0, 48(S8)
+BFD000CA 69A0 LW V1, 0(V0)
+BFD000CC 0018FC5E LW V0, 24(S8)
+BFD000D0 13900062 SLTU V0, V0, V1
+BFD000D2 40A21390 ADDI GP, S0, 16546
+BFD000D4 000840A2 BNEZC V0, 0xBFD000E8
+BFD000D8 0018FC7E LW V1, 24(S8)
+BFD000DC 0014FC5E LW V0, 20(S8)
+BFD000E0 13900062 SLTU V0, V0, V1
+BFD000E2 40E21390 ADDI GP, S0, 16610
+BFD000E4 000340E2 BEQZC V0, 0xBFD000EE
+866: {\r
+867: xShouldDelay = pdTRUE;\r
+BFD000E8 ED01 LI V0, 1
+BFD000EA 0010F85E SW V0, 16(S8)
+868: }\r
+869: else\r
+870: {\r
+871: mtCOVERAGE_TEST_MARKER();\r
+872: }\r
+873: }\r
+874: \r
+875: /* Update the wake time ready for the next call. */\r
+876: *pxPreviousWakeTime = xTimeToWake;\r
+BFD000EE 0030FC5E LW V0, 48(S8)
+BFD000F2 0018FC7E LW V1, 24(S8)
+BFD000F6 E9A0 SW V1, 0(V0)
+877: \r
+878: if( xShouldDelay != pdFALSE )\r
+BFD000F8 0010FC5E LW V0, 16(S8)
+BFD000FC 001A40E2 BEQZC V0, 0xBFD00134
+879: {\r
+880: traceTASK_DELAY_UNTIL();\r
+881: \r
+882: /* Remove the task from the ready list before adding it to the\r
+883: blocked list as the same list item is used for both lists. */\r
+884: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
+BFD00100 8030FC5C LW V0, -32720(GP)
+BFD00104 6D22 ADDIU V0, V0, 4
+BFD00106 0C82 MOVE A0, V0
+BFD00108 00C877E8 JALS uxListRemove
+BFD0010A 0C0000C8 SLL A2, T0, 1
+BFD0010C 0C00 NOP
+BFD0010E 000C40A2 BNEZC V0, 0xBFD0012A
+885: {\r
+886: /* The current task must be in a ready list, so there is\r
+887: no need to check, and the port reset macro can be called\r
+888: directly. */\r
+889: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
+BFD00112 8030FC5C LW V0, -32720(GP)
+BFD00116 692B LW V0, 44(V0)
+BFD00118 ED81 LI V1, 1
+BFD0011A 10100062 SLLV V0, V0, V1
+BFD0011C 441A1010 ADDI ZERO, S0, 17434
+BFD0011E 441A NOT16 V1, V0
+BFD00120 8040FC5C LW V0, -32704(GP)
+BFD00124 4493 AND16 V0, V1
+BFD00126 8040F85C SW V0, -32704(GP)
+890: }\r
+891: else\r
+892: {\r
+893: mtCOVERAGE_TEST_MARKER();\r
+894: }\r
+895: \r
+896: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+BFD0012A 0018FC9E LW A0, 24(S8)
+BFD0012E 373477E8 JALS prvAddCurrentTaskToDelayedList
+BFD00130 0C003734 LHU T9, 3072(S4)
+BFD00132 0C00 NOP
+897: }\r
+898: else\r
+899: {\r
+900: mtCOVERAGE_TEST_MARKER();\r
+901: }\r
+902: }\r
+903: xAlreadyYielded = xTaskResumeAll();\r
+BFD00134 158E77E8 JALS xTaskResumeAll
+BFD00136 0C00158E LBU T4, 3072(T6)
+BFD00138 0C00 NOP
+BFD0013A 001CF85E SW V0, 28(S8)
+904: \r
+905: /* Force a reschedule if xTaskResumeAll has not already done so, we may\r
+906: have put ourselves to sleep. */\r
+907: if( xAlreadyYielded == pdFALSE )\r
+BFD0013E 001CFC5E LW V0, 28(S8)
+BFD00142 001040A2 BNEZC V0, 0xBFD00166
+908: {\r
+909: portYIELD_WITHIN_API();\r
+BFD00146 4E5677E8 JALS ulPortGetCP0Cause
+BFD00148 4E56 ADDIU S2, S2, -5
+BFD0014A 0C00 NOP
+BFD0014C 0020F85E SW V0, 32(S8)
+BFD00150 0020FC5E LW V0, 32(S8)
+BFD00154 01005042 ORI V0, V0, 256
+BFD00158 0020F85E SW V0, 32(S8)
+BFD0015C 0020FC9E LW A0, 32(S8)
+BFD00160 4E6677E8 JALS vPortSetCP0Cause
+BFD00162 4E66 ADDIU S3, S3, 3
+BFD00164 0C00 NOP
+910: }\r
+911: else\r
+912: {\r
+913: mtCOVERAGE_TEST_MARKER();\r
+914: }\r
+915: }\r
+BFD00166 0FBE MOVE SP, S8
+BFD00168 4BEB LW RA, 44(SP)
+BFD0016A 4BCA LW S8, 40(SP)
+BFD0016C 4C19 ADDIU SP, SP, 48
+BFD0016E 459F JR16 RA
+BFD00170 0C00 NOP
+916: \r
+917: #endif /* INCLUDE_vTaskDelayUntil */\r
+918: /*-----------------------------------------------------------*/\r
+919: \r
+920: #if ( INCLUDE_vTaskDelay == 1 )\r
+921: \r
+922: void vTaskDelay( const TickType_t xTicksToDelay )\r
+923: {\r
+BFD05BA0 4FED ADDIU SP, SP, -40
+BFD05BA2 CBE9 SW RA, 36(SP)
+BFD05BA4 CBC8 SW S8, 32(SP)
+BFD05BA6 0FDD MOVE S8, SP
+BFD05BA8 0028F89E SW A0, 40(S8)
+924: TickType_t xTimeToWake;\r
+925: BaseType_t xAlreadyYielded = pdFALSE;\r
+BFD05BAC 0010F81E SW ZERO, 16(S8)
+926: \r
+927: \r
+928: /* A delay time of zero just forces a reschedule. */\r
+929: if( xTicksToDelay > ( TickType_t ) 0U )\r
+BFD05BB0 0028FC5E LW V0, 40(S8)
+BFD05BB4 003640E2 BEQZC V0, 0xBFD05C24
+930: {\r
+931: configASSERT( uxSchedulerSuspended == 0 );\r
+BFD05BB8 805CFC5C LW V0, -32676(GP)
+BFD05BBC 000940E2 BEQZC V0, 0xBFD05BD2
+BFD05BC0 BFD141A2 LUI V0, 0xBFD1
+BFD05BC2 3082BFD1 LDC1 F30, 12418(S1)
+BFD05BC4 98103082 ADDIU A0, V0, -26608
+BFD05BC6 30A09810 SWC1 F0, 12448(S0)
+BFD05BC8 03A330A0 ADDIU A1, ZERO, 931
+BFD05BCC 4B7E77E8 JALS vAssertCalled
+BFD05BCE 4B7E LW K1, 120(SP)
+BFD05BD0 0C00 NOP
+932: vTaskSuspendAll();\r
+BFD05BD2 4EF477E8 JALS vTaskSuspendAll
+BFD05BD4 4EF4 ADDIU S7, S7, -6
+BFD05BD6 0C00 NOP
+933: {\r
+934: traceTASK_DELAY();\r
+935: \r
+936: /* A task that is removed from the event list while the\r
+937: scheduler is suspended will not get placed in the ready\r
+938: list or removed from the blocked list until the scheduler\r
+939: is resumed.\r
+940: \r
+941: This task cannot be in an event list as it is the currently\r
+942: executing task. */\r
+943: \r
+944: /* Calculate the time to wake - this may overflow but this is\r
+945: not a problem. */\r
+946: xTimeToWake = xTickCount + xTicksToDelay;\r
+BFD05BD8 803CFC7C LW V1, -32708(GP)
+BFD05BDC 0028FC5E LW V0, 40(S8)
+BFD05BE0 0526 ADDU V0, V1, V0
+BFD05BE2 0014F85E SW V0, 20(S8)
+947: \r
+948: /* We must remove ourselves from the ready list before adding\r
+949: ourselves to the blocked list as the same list item is used for\r
+950: both lists. */\r
+951: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
+BFD05BE6 8030FC5C LW V0, -32720(GP)
+BFD05BEA 6D22 ADDIU V0, V0, 4
+BFD05BEC 0C82 MOVE A0, V0
+BFD05BEE 00C877E8 JALS uxListRemove
+BFD05BF0 0C0000C8 SLL A2, T0, 1
+BFD05BF2 0C00 NOP
+BFD05BF4 000C40A2 BNEZC V0, 0xBFD05C10
+952: {\r
+953: /* The current task must be in a ready list, so there is\r
+954: no need to check, and the port reset macro can be called\r
+955: directly. */\r
+956: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
+BFD05BF8 8030FC5C LW V0, -32720(GP)
+BFD05BFC 692B LW V0, 44(V0)
+BFD05BFE ED81 LI V1, 1
+BFD05C00 10100062 SLLV V0, V0, V1
+BFD05C02 441A1010 ADDI ZERO, S0, 17434
+BFD05C04 441A NOT16 V1, V0
+BFD05C06 8040FC5C LW V0, -32704(GP)
+BFD05C0A 4493 AND16 V0, V1
+BFD05C0C 8040F85C SW V0, -32704(GP)
+957: }\r
+958: else\r
+959: {\r
+960: mtCOVERAGE_TEST_MARKER();\r
+961: }\r
+962: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+BFD05C10 0014FC9E LW A0, 20(S8)
+BFD05C14 373477E8 JALS prvAddCurrentTaskToDelayedList
+BFD05C16 0C003734 LHU T9, 3072(S4)
+BFD05C18 0C00 NOP
+963: }\r
+964: xAlreadyYielded = xTaskResumeAll();\r
+BFD05C1A 158E77E8 JALS xTaskResumeAll
+BFD05C1C 0C00158E LBU T4, 3072(T6)
+BFD05C1E 0C00 NOP
+BFD05C20 0010F85E SW V0, 16(S8)
+965: }\r
+966: else\r
+967: {\r
+968: mtCOVERAGE_TEST_MARKER();\r
+969: }\r
+970: \r
+971: /* Force a reschedule if xTaskResumeAll has not already done so, we may\r
+972: have put ourselves to sleep. */\r
+973: if( xAlreadyYielded == pdFALSE )\r
+BFD05C24 0010FC5E LW V0, 16(S8)
+BFD05C28 001040A2 BNEZC V0, 0xBFD05C4C
+974: {\r
+975: portYIELD_WITHIN_API();\r
+BFD05C2C 4E5677E8 JALS ulPortGetCP0Cause
+BFD05C2E 4E56 ADDIU S2, S2, -5
+BFD05C30 0C00 NOP
+BFD05C32 0018F85E SW V0, 24(S8)
+BFD05C36 0018FC5E LW V0, 24(S8)
+BFD05C3A 01005042 ORI V0, V0, 256
+BFD05C3E 0018F85E SW V0, 24(S8)
+BFD05C42 0018FC9E LW A0, 24(S8)
+BFD05C46 4E6677E8 JALS vPortSetCP0Cause
+BFD05C48 4E66 ADDIU S3, S3, 3
+BFD05C4A 0C00 NOP
+976: }\r
+977: else\r
+978: {\r
+979: mtCOVERAGE_TEST_MARKER();\r
+980: }\r
+981: }\r
+BFD05C4C 0FBE MOVE SP, S8
+BFD05C4E 4BE9 LW RA, 36(SP)
+BFD05C50 4BC8 LW S8, 32(SP)
+BFD05C52 4C15 ADDIU SP, SP, 40
+BFD05C54 459F JR16 RA
+BFD05C56 0C00 NOP
+982: \r
+983: #endif /* INCLUDE_vTaskDelay */\r
+984: /*-----------------------------------------------------------*/\r
+985: \r
+986: #if ( INCLUDE_eTaskGetState == 1 )\r
+987: \r
+988: eTaskState eTaskGetState( TaskHandle_t xTask )\r
+989: {\r
+BFD04494 4FED ADDIU SP, SP, -40
+BFD04496 CBE9 SW RA, 36(SP)
+BFD04498 CBC8 SW S8, 32(SP)
+BFD0449A 0FDD MOVE S8, SP
+BFD0449C 0028F89E SW A0, 40(S8)
+990: eTaskState eReturn;\r
+991: List_t *pxStateList;\r
+992: const TCB_t * const pxTCB = ( TCB_t * ) xTask;\r
+BFD044A0 0028FC5E LW V0, 40(S8)
+BFD044A4 0014F85E SW V0, 20(S8)
+993: \r
+994: configASSERT( pxTCB );\r
+BFD044A8 0014FC5E LW V0, 20(S8)
+BFD044AC 000940A2 BNEZC V0, 0xBFD044C2
+BFD044B0 BFD141A2 LUI V0, 0xBFD1
+BFD044B2 3082BFD1 LDC1 F30, 12418(S1)
+BFD044B4 98103082 ADDIU A0, V0, -26608
+BFD044B6 30A09810 SWC1 F0, 12448(S0)
+BFD044B8 03E230A0 ADDIU A1, ZERO, 994
+BFD044BC 4B7E77E8 JALS vAssertCalled
+BFD044BE 4B7E LW K1, 120(SP)
+BFD044C0 0C00 NOP
+995: \r
+996: if( pxTCB == pxCurrentTCB )\r
+BFD044C2 8030FC5C LW V0, -32720(GP)
+BFD044C6 0014FC7E LW V1, 20(S8)
+BFD044CA 0005B443 BNE V1, V0, 0xBFD044D8
+BFD044CC 0C000005 SLL ZERO, A1, 1
+BFD044CE 0C00 NOP
+997: {\r
+998: /* The task calling this function is querying its own state. */\r
+999: eReturn = eRunning;\r
+BFD044D0 0010F81E SW ZERO, 16(S8)
+BFD044D4 CC48 B 0xBFD04566
+BFD044D6 0C00 NOP
+1000: }\r
+1001: else\r
+1002: {\r
+1003: taskENTER_CRITICAL();\r
+BFD044D8 33B877E8 JALS vTaskEnterCritical
+BFD044DA 0C0033B8 ADDIU SP, T8, 3072
+BFD044DC 0C00 NOP
+1004: {\r
+1005: pxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xGenericListItem ) );\r
+BFD044DE 0014FC5E LW V0, 20(S8)
+BFD044E2 6925 LW V0, 20(V0)
+BFD044E4 0018F85E SW V0, 24(S8)
+1006: }\r
+1007: taskEXIT_CRITICAL();\r
+BFD044E8 40AA77E8 JALS vTaskExitCritical
+BFD044EA 0C0040AA BNEZC T2, 0xBFD05CEE
+BFD044EC 0C00 NOP
+1008: \r
+1009: if( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) )\r
+BFD044EE 8074FC5C LW V0, -32652(GP)
+BFD044F2 0018FC7E LW V1, 24(S8)
+BFD044F6 00089443 BEQ V1, V0, 0xBFD0450A
+BFD044F8 0C000008 SLL ZERO, T0, 1
+BFD044FA 0C00 NOP
+BFD044FC 8078FC5C LW V0, -32648(GP)
+BFD04500 0018FC7E LW V1, 24(S8)
+BFD04504 0006B443 BNE V1, V0, 0xBFD04514
+BFD04506 0C000006 SLL ZERO, A2, 1
+BFD04508 0C00 NOP
+1010: {\r
+1011: /* The task being queried is referenced from one of the Blocked\r
+1012: lists. */\r
+1013: eReturn = eBlocked;\r
+BFD0450A ED02 LI V0, 2
+BFD0450C 0010F85E SW V0, 16(S8)
+BFD04510 CC2A B 0xBFD04566
+BFD04512 0C00 NOP
+1014: }\r
+1015: \r
+1016: #if ( INCLUDE_vTaskSuspend == 1 )\r
+1017: else if( pxStateList == &xSuspendedTaskList )\r
+BFD04514 0018FC7E LW V1, 24(S8)
+BFD04518 BFD241A2 LUI V0, 0xBFD2
+BFD0451A 3042BFD2 LDC1 F30, 12354(S2)
+BFD0451C 80E43042 ADDIU V0, V0, -32540
+BFD04520 0010B443 BNE V1, V0, 0xBFD04544
+BFD04522 0C000010 SLL ZERO, S0, 1
+BFD04524 0C00 NOP
+1018: {\r
+1019: /* The task being queried is referenced from the suspended\r
+1020: list. Is it genuinely suspended or is it block\r
+1021: indefinitely? */\r
+1022: if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )\r
+BFD04526 0014FC5E LW V0, 20(S8)
+BFD0452A 692A LW V0, 40(V0)
+BFD0452C 000540A2 BNEZC V0, 0xBFD0453A
+1023: {\r
+1024: eReturn = eSuspended;\r
+BFD04530 ED03 LI V0, 3
+BFD04532 0010F85E SW V0, 16(S8)
+BFD04536 CC17 B 0xBFD04566
+BFD04538 0C00 NOP
+1025: }\r
+1026: else\r
+1027: {\r
+1028: eReturn = eBlocked;\r
+BFD0453A ED02 LI V0, 2
+BFD0453C 0010F85E SW V0, 16(S8)
+BFD04540 CC12 B 0xBFD04566
+BFD04542 0C00 NOP
+1029: }\r
+1030: }\r
+1031: #endif\r
+1032: \r
+1033: #if ( INCLUDE_vTaskDelete == 1 )\r
+1034: else if( pxStateList == &xTasksWaitingTermination )\r
+BFD04544 0018FC7E LW V1, 24(S8)
+BFD04548 BFD241A2 LUI V0, 0xBFD2
+BFD0454A 3042BFD2 LDC1 F30, 12354(S2)
+BFD0454C 810C3042 ADDIU V0, V0, -32500
+BFD04550 0006B443 BNE V1, V0, 0xBFD04560
+BFD04552 0C000006 SLL ZERO, A2, 1
+BFD04554 0C00 NOP
+1035: {\r
+1036: /* The task being queried is referenced from the deleted\r
+1037: tasks list. */\r
+1038: eReturn = eDeleted;\r
+BFD04556 ED04 LI V0, 4
+BFD04558 0010F85E SW V0, 16(S8)
+BFD0455C CC04 B 0xBFD04566
+BFD0455E 0C00 NOP
+1039: }\r
+1040: #endif\r
+1041: \r
+1042: else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */\r
+1043: {\r
+1044: /* If the task is not in any other state, it must be in the\r
+1045: Ready (including pending ready) state. */\r
+1046: eReturn = eReady;\r
+BFD04560 ED01 LI V0, 1
+BFD04562 0010F85E SW V0, 16(S8)
+1047: }\r
+1048: }\r
+1049: \r
+1050: return eReturn;\r
+BFD04566 0010FC5E LW V0, 16(S8)
+1051: } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */\r
+BFD0456A 0FBE MOVE SP, S8
+BFD0456C 4BE9 LW RA, 36(SP)
+BFD0456E 4BC8 LW S8, 32(SP)
+BFD04570 4C15 ADDIU SP, SP, 40
+BFD04572 459F JR16 RA
+BFD04574 0C00 NOP
+1052: \r
+1053: #endif /* INCLUDE_eTaskGetState */\r
+1054: /*-----------------------------------------------------------*/\r
+1055: \r
+1056: #if ( INCLUDE_uxTaskPriorityGet == 1 )\r
+1057: \r
+1058: UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask )\r
+1059: {\r
+BFD08B78 4FF1 ADDIU SP, SP, -32
+BFD08B7A CBE7 SW RA, 28(SP)
+BFD08B7C CBC6 SW S8, 24(SP)
+BFD08B7E 0FDD MOVE S8, SP
+BFD08B80 0020F89E SW A0, 32(S8)
+1060: TCB_t *pxTCB;\r
+1061: UBaseType_t uxReturn;\r
+1062: \r
+1063: taskENTER_CRITICAL();\r
+BFD08B84 33B877E8 JALS vTaskEnterCritical
+BFD08B86 0C0033B8 ADDIU SP, T8, 3072
+BFD08B88 0C00 NOP
+1064: {\r
+1065: /* If null is passed in here then we are changing the\r
+1066: priority of the calling function. */\r
+1067: pxTCB = prvGetTCBFromHandle( xTask );\r
+BFD08B8A 0020FC5E LW V0, 32(S8)
+BFD08B8E 000440A2 BNEZC V0, 0xBFD08B9A
+BFD08B92 8030FC5C LW V0, -32720(GP)
+BFD08B96 CC03 B 0xBFD08B9E
+BFD08B98 0C00 NOP
+BFD08B9A 0020FC5E LW V0, 32(S8)
+BFD08B9E 0010F85E SW V0, 16(S8)
+1068: uxReturn = pxTCB->uxPriority;\r
+BFD08BA2 0010FC5E LW V0, 16(S8)
+BFD08BA6 692B LW V0, 44(V0)
+BFD08BA8 0014F85E SW V0, 20(S8)
+1069: }\r
+1070: taskEXIT_CRITICAL();\r
+BFD08BAC 40AA77E8 JALS vTaskExitCritical
+BFD08BAE 0C0040AA BNEZC T2, 0xBFD0A3B2
+BFD08BB0 0C00 NOP
+1071: \r
+1072: return uxReturn;\r
+BFD08BB2 0014FC5E LW V0, 20(S8)
+1073: }\r
+BFD08BB6 0FBE MOVE SP, S8
+BFD08BB8 4BE7 LW RA, 28(SP)
+BFD08BBA 4BC6 LW S8, 24(SP)
+BFD08BBC 4C11 ADDIU SP, SP, 32
+BFD08BBE 459F JR16 RA
+BFD08BC0 0C00 NOP
+1074: \r
+1075: #endif /* INCLUDE_uxTaskPriorityGet */\r
+1076: /*-----------------------------------------------------------*/\r
+1077: \r
+1078: #if ( INCLUDE_uxTaskPriorityGet == 1 )\r
+1079: \r
+1080: UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask )\r
+1081: {\r
+BFD08708 4FED ADDIU SP, SP, -40
+BFD0870A CBE9 SW RA, 36(SP)
+BFD0870C CBC8 SW S8, 32(SP)
+BFD0870E 0FDD MOVE S8, SP
+BFD08710 0028F89E SW A0, 40(S8)
+1082: TCB_t *pxTCB;\r
+1083: UBaseType_t uxReturn, uxSavedInterruptState;\r
+1084: \r
+1085: /* RTOS ports that support interrupt nesting have the concept of a\r
+1086: maximum system call (or maximum API call) interrupt priority.\r
+1087: Interrupts that are above the maximum system call priority are keep\r
+1088: permanently enabled, even when the RTOS kernel is in a critical section,\r
+1089: but cannot make any calls to FreeRTOS API functions. If configASSERT()\r
+1090: is defined in FreeRTOSConfig.h then\r
+1091: portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r
+1092: failure if a FreeRTOS API function is called from an interrupt that has\r
+1093: been assigned a priority above the configured maximum system call\r
+1094: priority. Only FreeRTOS functions that end in FromISR can be called\r
+1095: from interrupts that have been assigned a priority at or (logically)\r
+1096: below the maximum system call interrupt priority. FreeRTOS maintains a\r
+1097: separate interrupt safe API to ensure interrupt entry is as fast and as\r
+1098: simple as possible. More information (albeit Cortex-M specific) is\r
+1099: provided on the following link:\r
+1100: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r
+1101: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
+1102: \r
+1103: uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();\r
+BFD08714 475E77E8 JALS uxPortSetInterruptMaskFromISR
+BFD08718 0C00 NOP
+BFD0871A 0010F85E SW V0, 16(S8)
+1104: {\r
+1105: /* If null is passed in here then it is the priority of the calling\r
+1106: task that is being queried. */\r
+1107: pxTCB = prvGetTCBFromHandle( xTask );\r
+BFD0871E 0028FC5E LW V0, 40(S8)
+BFD08722 000440A2 BNEZC V0, 0xBFD0872E
+BFD08726 8030FC5C LW V0, -32720(GP)
+BFD0872A CC03 B 0xBFD08732
+BFD0872C 0C00 NOP
+BFD0872E 0028FC5E LW V0, 40(S8)
+BFD08732 0014F85E SW V0, 20(S8)
+1108: uxReturn = pxTCB->uxPriority;\r
+BFD08736 0014FC5E LW V0, 20(S8)
+BFD0873A 692B LW V0, 44(V0)
+BFD0873C 0018F85E SW V0, 24(S8)
+1109: }\r
+1110: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );\r
+BFD08740 0010FC9E LW A0, 16(S8)
+BFD08744 4D5E77E8 JALS vPortClearInterruptMaskFromISR
+BFD08746 4D5E ADDIU T2, T2, -1
+BFD08748 0C00 NOP
+1111: \r
+1112: return uxReturn;\r
+BFD0874A 0018FC5E LW V0, 24(S8)
+1113: }\r
+BFD0874E 0FBE MOVE SP, S8
+BFD08750 4BE9 LW RA, 36(SP)
+BFD08752 4BC8 LW S8, 32(SP)
+BFD08754 4C15 ADDIU SP, SP, 40
+BFD08756 459F JR16 RA
+BFD08758 0C00 NOP
+1114: \r
+1115: #endif /* INCLUDE_uxTaskPriorityGet */\r
+1116: /*-----------------------------------------------------------*/\r
+1117: \r
+1118: #if ( INCLUDE_vTaskPrioritySet == 1 )\r
+1119: \r
+1120: void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )\r
+1121: {\r
+BFD01924 4FE9 ADDIU SP, SP, -48
+BFD01926 CBEB SW RA, 44(SP)
+BFD01928 CBCA SW S8, 40(SP)
+BFD0192A 0FDD MOVE S8, SP
+BFD0192C 0030F89E SW A0, 48(S8)
+BFD01930 0034F8BE SW A1, 52(S8)
+1122: TCB_t *pxTCB;\r
+1123: UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;\r
+1124: BaseType_t xYieldRequired = pdFALSE;\r
+BFD01934 0010F81E SW ZERO, 16(S8)
+1125: \r
+1126: configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );\r
+BFD01938 0034FC5E LW V0, 52(S8)
+BFD0193C 0005B042 SLTIU V0, V0, 5
+BFD01940 000940A2 BNEZC V0, 0xBFD01956
+BFD01944 BFD141A2 LUI V0, 0xBFD1
+BFD01946 3082BFD1 LDC1 F30, 12418(S1)
+BFD01948 98103082 ADDIU A0, V0, -26608
+BFD0194A 30A09810 SWC1 F0, 12448(S0)
+BFD0194C 046630A0 ADDIU A1, ZERO, 1126
+BFD0194E 0466 ADDU S0, V1, A2
+BFD01950 4B7E77E8 JALS vAssertCalled
+BFD01952 4B7E LW K1, 120(SP)
+BFD01954 0C00 NOP
+1127: \r
+1128: /* Ensure the new priority is valid. */\r
+1129: if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )\r
+BFD01956 0034FC5E LW V0, 52(S8)
+BFD0195A 0005B042 SLTIU V0, V0, 5
+BFD0195E 000340A2 BNEZC V0, 0xBFD01968
+1130: {\r
+1131: uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;\r
+BFD01962 ED04 LI V0, 4
+BFD01964 0034F85E SW V0, 52(S8)
+1132: }\r
+1133: else\r
+1134: {\r
+1135: mtCOVERAGE_TEST_MARKER();\r
+1136: }\r
+1137: \r
+1138: taskENTER_CRITICAL();\r
+BFD01968 33B877E8 JALS vTaskEnterCritical
+BFD0196A 0C0033B8 ADDIU SP, T8, 3072
+BFD0196C 0C00 NOP
+1139: {\r
+1140: /* If null is passed in here then it is the priority of the calling\r
+1141: task that is being changed. */\r
+1142: pxTCB = prvGetTCBFromHandle( xTask );\r
+BFD0196E 0030FC5E LW V0, 48(S8)
+BFD01972 000440A2 BNEZC V0, 0xBFD0197E
+BFD01976 8030FC5C LW V0, -32720(GP)
+BFD0197A CC03 B 0xBFD01982
+BFD0197C 0C00 NOP
+BFD0197E 0030FC5E LW V0, 48(S8)
+BFD01982 0014F85E SW V0, 20(S8)
+1143: \r
+1144: traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );\r
+1145: \r
+1146: #if ( configUSE_MUTEXES == 1 )\r
+1147: {\r
+1148: uxCurrentBasePriority = pxTCB->uxBasePriority;\r
+BFD01986 0014FC5E LW V0, 20(S8)
+BFD0198A 0040FC42 LW V0, 64(V0)
+BFD0198E 0018F85E SW V0, 24(S8)
+1149: }\r
+1150: #else\r
+1151: {\r
+1152: uxCurrentBasePriority = pxTCB->uxPriority;\r
+1153: }\r
+1154: #endif\r
+1155: \r
+1156: if( uxCurrentBasePriority != uxNewPriority )\r
+BFD01992 0018FC7E LW V1, 24(S8)
+BFD01996 0034FC5E LW V0, 52(S8)
+BFD0199A 00AD9443 BEQ V1, V0, 0xBFD01AF8
+BFD0199C 0C0000AD SLL A1, T5, 1
+BFD0199E 0C00 NOP
+1157: {\r
+1158: /* The priority change may have readied a task of higher\r
+1159: priority than the calling task. */\r
+1160: if( uxNewPriority > uxCurrentBasePriority )\r
+BFD019A0 0034FC7E LW V1, 52(S8)
+BFD019A4 0018FC5E LW V0, 24(S8)
+BFD019A8 13900062 SLTU V0, V0, V1
+BFD019AA 40E21390 ADDI GP, S0, 16610
+BFD019AC 001540E2 BEQZC V0, 0xBFD019DA
+1161: {\r
+1162: if( pxTCB != pxCurrentTCB )\r
+BFD019B0 8030FC5C LW V0, -32720(GP)
+BFD019B4 0014FC7E LW V1, 20(S8)
+BFD019B8 00199443 BEQ V1, V0, 0xBFD019EE
+BFD019BA 0C000019 SLL ZERO, T9, 1
+BFD019BC 0C00 NOP
+1163: {\r
+1164: /* The priority of a task other than the currently\r
+1165: running task is being raised. Is the priority being\r
+1166: raised above that of the running task? */\r
+1167: if( uxNewPriority >= pxCurrentTCB->uxPriority )\r
+BFD019BE 8030FC5C LW V0, -32720(GP)
+BFD019C2 69AB LW V1, 44(V0)
+BFD019C4 0034FC5E LW V0, 52(S8)
+BFD019C8 13900062 SLTU V0, V0, V1
+BFD019CA 40A21390 ADDI GP, S0, 16546
+BFD019CC 000F40A2 BNEZC V0, 0xBFD019EE
+1168: {\r
+1169: xYieldRequired = pdTRUE;\r
+BFD019D0 ED01 LI V0, 1
+BFD019D2 0010F85E SW V0, 16(S8)
+BFD019D6 CC0B B 0xBFD019EE
+BFD019D8 0C00 NOP
+1170: }\r
+1171: else\r
+1172: {\r
+1173: mtCOVERAGE_TEST_MARKER();\r
+1174: }\r
+1175: }\r
+1176: else\r
+1177: {\r
+1178: /* The priority of the running task is being raised,\r
+1179: but the running task must already be the highest\r
+1180: priority task able to run so no yield is required. */\r
+1181: }\r
+1182: }\r
+1183: else if( pxTCB == pxCurrentTCB )\r
+BFD019DA 8030FC5C LW V0, -32720(GP)
+BFD019DE 0014FC7E LW V1, 20(S8)
+BFD019E2 0004B443 BNE V1, V0, 0xBFD019EE
+BFD019E4 0C000004 SLL ZERO, A0, 1
+BFD019E6 0C00 NOP
+1184: {\r
+1185: /* Setting the priority of the running task down means\r
+1186: there may now be another task of higher priority that\r
+1187: is ready to execute. */\r
+1188: xYieldRequired = pdTRUE;\r
+BFD019E8 ED01 LI V0, 1
+BFD019EA 0010F85E SW V0, 16(S8)
+1189: }\r
+1190: else\r
+1191: {\r
+1192: /* Setting the priority of any other task down does not\r
+1193: require a yield as the running task must be above the\r
+1194: new priority of the task being modified. */\r
+1195: }\r
+1196: \r
+1197: /* Remember the ready list the task might be referenced from\r
+1198: before its uxPriority member is changed so the\r
+1199: taskRESET_READY_PRIORITY() macro can function correctly. */\r
+1200: uxPriorityUsedOnEntry = pxTCB->uxPriority;\r
+BFD019EE 0014FC5E LW V0, 20(S8)
+BFD019F2 692B LW V0, 44(V0)
+BFD019F4 001CF85E SW V0, 28(S8)
+1201: \r
+1202: #if ( configUSE_MUTEXES == 1 )\r
+1203: {\r
+1204: /* Only change the priority being used if the task is not\r
+1205: currently using an inherited priority. */\r
+1206: if( pxTCB->uxBasePriority == pxTCB->uxPriority )\r
+BFD019F8 0014FC5E LW V0, 20(S8)
+BFD019FC 0040FC62 LW V1, 64(V0)
+BFD01A00 0014FC5E LW V0, 20(S8)
+BFD01A04 692B LW V0, 44(V0)
+BFD01A06 0006B443 BNE V1, V0, 0xBFD01A16
+BFD01A08 0C000006 SLL ZERO, A2, 1
+BFD01A0A 0C00 NOP
+1207: {\r
+1208: pxTCB->uxPriority = uxNewPriority;\r
+BFD01A0C 0014FC5E LW V0, 20(S8)
+BFD01A10 0034FC7E LW V1, 52(S8)
+BFD01A14 E9AB SW V1, 44(V0)
+1209: }\r
+1210: else\r
+1211: {\r
+1212: mtCOVERAGE_TEST_MARKER();\r
+1213: }\r
+1214: \r
+1215: /* The base priority gets set whatever. */\r
+1216: pxTCB->uxBasePriority = uxNewPriority;\r
+BFD01A16 0014FC5E LW V0, 20(S8)
+BFD01A1A 0034FC7E LW V1, 52(S8)
+BFD01A1E 0040F862 SW V1, 64(V0)
+1217: }\r
+1218: #else\r
+1219: {\r
+1220: pxTCB->uxPriority = uxNewPriority;\r
+1221: }\r
+1222: #endif\r
+1223: \r
+1224: /* Only reset the event list item value if the value is not\r
+1225: being used for anything else. */\r
+1226: if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\r
+BFD01A22 0014FC5E LW V0, 20(S8)
+BFD01A26 6926 LW V0, 24(V0)
+BFD01A28 00084002 BLTZ V0, 0xBFD01A3C
+BFD01A2A 0C000008 SLL ZERO, T0, 1
+BFD01A2C 0C00 NOP
+1227: {\r
+1228: listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
+BFD01A2E ED85 LI V1, 5
+BFD01A30 0034FC5E LW V0, 52(S8)
+BFD01A34 05A7 SUBU V1, V1, V0
+BFD01A36 0014FC5E LW V0, 20(S8)
+BFD01A3A E9A6 SW V1, 24(V0)
+1229: }\r
+1230: else\r
+1231: {\r
+1232: mtCOVERAGE_TEST_MARKER();\r
+1233: }\r
+1234: \r
+1235: /* If the task is in the blocked or suspended list we need do\r
+1236: nothing more than change it's priority variable. However, if\r
+1237: the task is in a ready list it needs to be removed and placed\r
+1238: in the list appropriate to its new priority. */\r
+1239: if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )\r
+BFD01A3C 0014FC5E LW V0, 20(S8)
+BFD01A3E 69A50014 LWX T5, 0(S4)
+BFD01A40 69A5 LW V1, 20(V0)
+BFD01A42 001CFC5E LW V0, 28(S8)
+BFD01A46 2524 SLL V0, V0, 2
+BFD01A48 2624 SLL A0, V0, 2
+BFD01A4A 0644 ADDU A0, V0, A0
+BFD01A4C BFD241A2 LUI V0, 0xBFD2
+BFD01A4E 3042BFD2 LDC1 F30, 12354(S2)
+BFD01A50 806C3042 ADDIU V0, V0, -32660
+BFD01A54 0528 ADDU V0, A0, V0
+BFD01A56 0004B443 BNE V1, V0, 0xBFD01A62
+BFD01A58 0C000004 SLL ZERO, A0, 1
+BFD01A5A 0C00 NOP
+BFD01A5C ED01 LI V0, 1
+BFD01A5E CC02 B 0xBFD01A64
+BFD01A60 0C00 NOP
+BFD01A62 0C40 MOVE V0, ZERO
+BFD01A64 003240E2 BEQZC V0, 0xBFD01ACC
+1240: {\r
+1241: /* The task is currently in its ready list - remove before adding\r
+1242: it to it's new ready list. As we are in a critical section we\r
+1243: can do this even if the scheduler is suspended. */\r
+1244: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
+BFD01A68 0014FC5E LW V0, 20(S8)
+BFD01A6C 6D22 ADDIU V0, V0, 4
+BFD01A6E 0C82 MOVE A0, V0
+BFD01A70 00C877E8 JALS uxListRemove
+BFD01A72 0C0000C8 SLL A2, T0, 1
+BFD01A74 0C00 NOP
+BFD01A76 000B40A2 BNEZC V0, 0xBFD01A90
+1245: {\r
+1246: /* It is known that the task is in its ready list so\r
+1247: there is no need to check again and the port level\r
+1248: reset macro can be called directly. */\r
+1249: portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );\r
+BFD01A7A 001CFC5E LW V0, 28(S8)
+BFD01A7E ED81 LI V1, 1
+BFD01A80 10100062 SLLV V0, V0, V1
+BFD01A82 441A1010 ADDI ZERO, S0, 17434
+BFD01A84 441A NOT16 V1, V0
+BFD01A86 8040FC5C LW V0, -32704(GP)
+BFD01A8A 4493 AND16 V0, V1
+BFD01A8C 8040F85C SW V0, -32704(GP)
+1250: }\r
+1251: else\r
+1252: {\r
+1253: mtCOVERAGE_TEST_MARKER();\r
+1254: }\r
+1255: prvAddTaskToReadyList( pxTCB );\r
+BFD01A90 0014FC5E LW V0, 20(S8)
+BFD01A94 692B LW V0, 44(V0)
+BFD01A96 ED81 LI V1, 1
+BFD01A98 18100062 SLLV V1, V0, V1
+BFD01A9A FC5C1810 SB ZERO, -932(S0)
+BFD01A9C 8040FC5C LW V0, -32704(GP)
+BFD01AA0 44D3 OR16 V0, V1
+BFD01AA2 8040F85C SW V0, -32704(GP)
+BFD01AA6 0014FC5E LW V0, 20(S8)
+BFD01AAA 692B LW V0, 44(V0)
+BFD01AAC 2524 SLL V0, V0, 2
+BFD01AAE 25A4 SLL V1, V0, 2
+BFD01AB0 05B4 ADDU V1, V0, V1
+BFD01AB2 BFD241A2 LUI V0, 0xBFD2
+BFD01AB4 3042BFD2 LDC1 F30, 12354(S2)
+BFD01AB6 806C3042 ADDIU V0, V0, -32660
+BFD01ABA 05A6 ADDU V1, V1, V0
+BFD01ABC 0014FC5E LW V0, 20(S8)
+BFD01AC0 6D22 ADDIU V0, V0, 4
+BFD01AC2 0C83 MOVE A0, V1
+BFD01AC4 0CA2 MOVE A1, V0
+BFD01AC6 3E4A77E8 JALS vListInsertEnd
+BFD01AC8 0C003E4A LH S2, 3072(T2)
+BFD01ACA 0C00 NOP
+1256: }\r
+1257: else\r
+1258: {\r
+1259: mtCOVERAGE_TEST_MARKER();\r
+1260: }\r
+1261: \r
+1262: if( xYieldRequired == pdTRUE )\r
+BFD01ACC 0010FC7E LW V1, 16(S8)
+BFD01AD0 ED01 LI V0, 1
+BFD01AD2 0011B443 BNE V1, V0, 0xBFD01AF8
+BFD01AD4 0C000011 SLL ZERO, S1, 1
+BFD01AD6 0C00 NOP
+1263: {\r
+1264: taskYIELD_IF_USING_PREEMPTION();\r
+BFD01AD8 4E5677E8 JALS ulPortGetCP0Cause
+BFD01ADA 4E56 ADDIU S2, S2, -5
+BFD01ADC 0C00 NOP
+BFD01ADE 0020F85E SW V0, 32(S8)
+BFD01AE2 0020FC5E LW V0, 32(S8)
+BFD01AE6 01005042 ORI V0, V0, 256
+BFD01AEA 0020F85E SW V0, 32(S8)
+BFD01AEE 0020FC9E LW A0, 32(S8)
+BFD01AF2 4E6677E8 JALS vPortSetCP0Cause
+BFD01AF4 4E66 ADDIU S3, S3, 3
+BFD01AF6 0C00 NOP
+1265: }\r
+1266: else\r
+1267: {\r
+1268: mtCOVERAGE_TEST_MARKER();\r
+1269: }\r
+1270: \r
+1271: /* Remove compiler warning about unused variables when the port\r
+1272: optimised task selection is not being used. */\r
+1273: ( void ) uxPriorityUsedOnEntry;\r
+1274: }\r
+1275: }\r
+1276: taskEXIT_CRITICAL();\r
+BFD01AF8 40AA77E8 JALS vTaskExitCritical
+BFD01AFA 0C0040AA BNEZC T2, 0xBFD032FE
+BFD01AFC 0C00 NOP
+1277: }\r
+BFD01AFE 0FBE MOVE SP, S8
+BFD01B00 4BEB LW RA, 44(SP)
+BFD01B02 4BCA LW S8, 40(SP)
+BFD01B04 4C19 ADDIU SP, SP, 48
+BFD01B06 459F JR16 RA
+BFD01B08 0C00 NOP
+1278: \r
+1279: #endif /* INCLUDE_vTaskPrioritySet */\r
+1280: /*-----------------------------------------------------------*/\r
+1281: \r
+1282: #if ( INCLUDE_vTaskSuspend == 1 )\r
+1283: \r
+1284: void vTaskSuspend( TaskHandle_t xTaskToSuspend )\r
+1285: {\r
+BFD0304C 4FF1 ADDIU SP, SP, -32
+BFD0304E CBE7 SW RA, 28(SP)
+BFD03050 CBC6 SW S8, 24(SP)
+BFD03052 0FDD MOVE S8, SP
+BFD03054 0020F89E SW A0, 32(S8)
+1286: TCB_t *pxTCB;\r
+1287: \r
+1288: taskENTER_CRITICAL();\r
+BFD03058 33B877E8 JALS vTaskEnterCritical
+BFD0305A 0C0033B8 ADDIU SP, T8, 3072
+BFD0305C 0C00 NOP
+1289: {\r
+1290: /* If null is passed in here then it is the running task that is\r
+1291: being suspended. */\r
+1292: pxTCB = prvGetTCBFromHandle( xTaskToSuspend );\r
+BFD0305E 0020FC5E LW V0, 32(S8)
+BFD03062 000440A2 BNEZC V0, 0xBFD0306E
+BFD03066 8030FC5C LW V0, -32720(GP)
+BFD0306A CC03 B 0xBFD03072
+BFD0306C 0C00 NOP
+BFD0306E 0020FC5E LW V0, 32(S8)
+BFD03072 0010F85E SW V0, 16(S8)
+1293: \r
+1294: traceTASK_SUSPEND( pxTCB );\r
+1295: \r
+1296: /* Remove task from the ready/delayed list and place in the\r
+1297: suspended list. */\r
+1298: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
+BFD03076 0010FC5E LW V0, 16(S8)
+BFD0307A 6D22 ADDIU V0, V0, 4
+BFD0307C 0C82 MOVE A0, V0
+BFD0307E 00C877E8 JALS uxListRemove
+BFD03080 0C0000C8 SLL A2, T0, 1
+BFD03082 0C00 NOP
+BFD03084 001A40A2 BNEZC V0, 0xBFD030BC
+1299: {\r
+1300: taskRESET_READY_PRIORITY( pxTCB->uxPriority );\r
+BFD03088 0010FC5E LW V0, 16(S8)
+BFD0308C 692B LW V0, 44(V0)
+BFD0308E 2524 SLL V0, V0, 2
+BFD03090 25A4 SLL V1, V0, 2
+BFD03092 05B4 ADDU V1, V0, V1
+BFD03094 BFD241A2 LUI V0, 0xBFD2
+BFD03096 3042BFD2 LDC1 F30, 12354(S2)
+BFD03098 806C3042 ADDIU V0, V0, -32660
+BFD0309C 0526 ADDU V0, V1, V0
+BFD0309E 6920 LW V0, 0(V0)
+BFD030A0 000C40A2 BNEZC V0, 0xBFD030BC
+BFD030A4 0010FC5E LW V0, 16(S8)
+BFD030A8 692B LW V0, 44(V0)
+BFD030AA ED81 LI V1, 1
+BFD030AC 10100062 SLLV V0, V0, V1
+BFD030AE 441A1010 ADDI ZERO, S0, 17434
+BFD030B0 441A NOT16 V1, V0
+BFD030B2 8040FC5C LW V0, -32704(GP)
+BFD030B6 4493 AND16 V0, V1
+BFD030B8 8040F85C SW V0, -32704(GP)
+1301: }\r
+1302: else\r
+1303: {\r
+1304: mtCOVERAGE_TEST_MARKER();\r
+1305: }\r
+1306: \r
+1307: /* Is the task waiting on an event also? */\r
+1308: if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\r
+BFD030BC 0010FC5E LW V0, 16(S8)
+BFD030C0 692A LW V0, 40(V0)
+BFD030C2 000740E2 BEQZC V0, 0xBFD030D4
+1309: {\r
+1310: ( void ) uxListRemove( &( pxTCB->xEventListItem ) );\r
+BFD030C6 0010FC5E LW V0, 16(S8)
+BFD030C8 6D2C0010 EXT ZERO, S0, 20, 14
+BFD030CA 6D2C ADDIU V0, V0, 24
+BFD030CC 0C82 MOVE A0, V0
+BFD030CE 00C877E8 JALS uxListRemove
+BFD030D0 0C0000C8 SLL A2, T0, 1
+BFD030D2 0C00 NOP
+1311: }\r
+1312: else\r
+1313: {\r
+1314: mtCOVERAGE_TEST_MARKER();\r
+1315: }\r
+1316: \r
+1317: vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) );\r
+BFD030D4 0010FC5E LW V0, 16(S8)
+BFD030D8 6D22 ADDIU V0, V0, 4
+BFD030DA BFD241A3 LUI V1, 0xBFD2
+BFD030DC 3083BFD2 LDC1 F30, 12419(S2)
+BFD030DE 80E43083 ADDIU A0, V1, -32540
+BFD030E2 0CA2 MOVE A1, V0
+BFD030E4 3E4A77E8 JALS vListInsertEnd
+BFD030E6 0C003E4A LH S2, 3072(T2)
+BFD030E8 0C00 NOP
+1318: }\r
+1319: taskEXIT_CRITICAL();\r
+BFD030EA 40AA77E8 JALS vTaskExitCritical
+BFD030EC 0C0040AA BNEZC T2, 0xBFD048F0
+BFD030EE 0C00 NOP
+1320: \r
+1321: if( pxTCB == pxCurrentTCB )\r
+BFD030F0 8030FC5C LW V0, -32720(GP)
+BFD030F4 0010FC7E LW V1, 16(S8)
+BFD030F8 0036B443 BNE V1, V0, 0xBFD03168
+BFD030FA 0C000036 SLL AT, S6, 1
+BFD030FC 0C00 NOP
+1322: {\r
+1323: if( xSchedulerRunning != pdFALSE )\r
+BFD030FE 8044FC5C LW V0, -32700(GP)
+BFD03102 001F40E2 BEQZC V0, 0xBFD03144
+1324: {\r
+1325: /* The current task has just been suspended. */\r
+1326: configASSERT( uxSchedulerSuspended == 0 );\r
+BFD03106 805CFC5C LW V0, -32676(GP)
+BFD0310A 000940E2 BEQZC V0, 0xBFD03120
+BFD0310E BFD141A2 LUI V0, 0xBFD1
+BFD03110 3082BFD1 LDC1 F30, 12418(S1)
+BFD03112 98103082 ADDIU A0, V0, -26608
+BFD03114 30A09810 SWC1 F0, 12448(S0)
+BFD03116 052E30A0 ADDIU A1, ZERO, 1326
+BFD03118 052E ADDU V0, A3, V0
+BFD0311A 4B7E77E8 JALS vAssertCalled
+BFD0311C 4B7E LW K1, 120(SP)
+BFD0311E 0C00 NOP
+1327: portYIELD_WITHIN_API();\r
+BFD03120 4E5677E8 JALS ulPortGetCP0Cause
+BFD03122 4E56 ADDIU S2, S2, -5
+BFD03124 0C00 NOP
+BFD03126 0014F85E SW V0, 20(S8)
+BFD0312A 0014FC5E LW V0, 20(S8)
+BFD0312E 01005042 ORI V0, V0, 256
+BFD03132 0014F85E SW V0, 20(S8)
+BFD03136 0014FC9E LW A0, 20(S8)
+BFD0313A 4E6677E8 JALS vPortSetCP0Cause
+BFD0313C 4E66 ADDIU S3, S3, 3
+BFD0313E 0C00 NOP
+BFD03140 CC20 B 0xBFD03182
+BFD03142 0C00 NOP
+1328: }\r
+1329: else\r
+1330: {\r
+1331: /* The scheduler is not running, but the task that was pointed\r
+1332: to by pxCurrentTCB has just been suspended and pxCurrentTCB\r
+1333: must be adjusted to point to a different task. */\r
+1334: if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )\r
+BFD03144 BFD241A2 LUI V0, 0xBFD2
+BFD03146 FC62BFD2 LDC1 F30, -926(S2)
+BFD03148 80E4FC62 LW V1, -32540(V0)
+BFD0314C 8038FC5C LW V0, -32712(GP)
+BFD03150 0005B443 BNE V1, V0, 0xBFD0315E
+BFD03152 0C000005 SLL ZERO, A1, 1
+BFD03154 0C00 NOP
+1335: {\r
+1336: /* No other tasks are ready, so set pxCurrentTCB back to\r
+1337: NULL so when the next task is created pxCurrentTCB will\r
+1338: be set to point to it no matter what its relative priority\r
+1339: is. */\r
+1340: pxCurrentTCB = NULL;\r
+BFD03156 8030F81C SW ZERO, -32720(GP)
+BFD0315A CC13 B 0xBFD03182
+BFD0315C 0C00 NOP
+1341: }\r
+1342: else\r
+1343: {\r
+1344: vTaskSwitchContext();\r
+BFD0315E 16DE77E8 JALS vTaskSwitchContext
+BFD03160 0C0016DE LBU S6, 3072(S8)
+BFD03162 0C00 NOP
+BFD03164 CC0E B 0xBFD03182
+BFD03166 0C00 NOP
+1345: }\r
+1346: }\r
+1347: }\r
+1348: else\r
+1349: {\r
+1350: if( xSchedulerRunning != pdFALSE )\r
+BFD03168 8044FC5C LW V0, -32700(GP)
+BFD0316C 000940E2 BEQZC V0, 0xBFD03182
+1351: {\r
+1352: /* A task other than the currently running task was suspended,\r
+1353: reset the next expected unblock time in case it referred to the\r
+1354: task that is now in the Suspended state. */\r
+1355: taskENTER_CRITICAL();\r
+BFD03170 33B877E8 JALS vTaskEnterCritical
+BFD03172 0C0033B8 ADDIU SP, T8, 3072
+BFD03174 0C00 NOP
+1356: {\r
+1357: prvResetNextTaskUnblockTime();\r
+BFD03176 47CA77E8 JALS prvResetNextTaskUnblockTime
+BFD0317A 0C00 NOP
+1358: }\r
+1359: taskEXIT_CRITICAL();\r
+BFD0317C 40AA77E8 JALS vTaskExitCritical
+BFD0317E 0C0040AA BNEZC T2, 0xBFD04982
+BFD03180 0C00 NOP
+1360: }\r
+1361: else\r
+1362: {\r
+1363: mtCOVERAGE_TEST_MARKER();\r
+1364: }\r
+1365: }\r
+1366: }\r
+BFD03182 0FBE MOVE SP, S8
+BFD03184 4BE7 LW RA, 28(SP)
+BFD03186 4BC6 LW S8, 24(SP)
+BFD03188 4C11 ADDIU SP, SP, 32
+BFD0318A 459F JR16 RA
+BFD0318C 0C00 NOP
+1367: \r
+1368: #endif /* INCLUDE_vTaskSuspend */\r
+1369: /*-----------------------------------------------------------*/\r
+1370: \r
+1371: #if ( INCLUDE_vTaskSuspend == 1 )\r
+1372: \r
+1373: static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )\r
+1374: {\r
+BFD066DC 4FF1 ADDIU SP, SP, -32
+BFD066DE CBE7 SW RA, 28(SP)
+BFD066E0 CBC6 SW S8, 24(SP)
+BFD066E2 0FDD MOVE S8, SP
+BFD066E4 0020F89E SW A0, 32(S8)
+1375: BaseType_t xReturn = pdFALSE;\r
+BFD066E8 0010F81E SW ZERO, 16(S8)
+1376: const TCB_t * const pxTCB = ( TCB_t * ) xTask;\r
+BFD066EC 0020FC5E LW V0, 32(S8)
+BFD066F0 0014F85E SW V0, 20(S8)
+1377: \r
+1378: /* Accesses xPendingReadyList so must be called from a critical\r
+1379: section. */\r
+1380: \r
+1381: /* It does not make sense to check if the calling task is suspended. */\r
+1382: configASSERT( xTask );\r
+BFD066F4 0020FC5E LW V0, 32(S8)
+BFD066F8 000940A2 BNEZC V0, 0xBFD0670E
+BFD066FC BFD141A2 LUI V0, 0xBFD1
+BFD066FE 3082BFD1 LDC1 F30, 12418(S1)
+BFD06700 98103082 ADDIU A0, V0, -26608
+BFD06702 30A09810 SWC1 F0, 12448(S0)
+BFD06704 056630A0 ADDIU A1, ZERO, 1382
+BFD06706 0566 ADDU V0, V1, A2
+BFD06708 4B7E77E8 JALS vAssertCalled
+BFD0670A 4B7E LW K1, 120(SP)
+BFD0670C 0C00 NOP
+1383: \r
+1384: /* Is the task being resumed actually in the suspended list? */\r
+1385: if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE )\r
+BFD0670E 0014FC5E LW V0, 20(S8)
+BFD06710 69A50014 LWX T5, 0(S4)
+BFD06712 69A5 LW V1, 20(V0)
+BFD06714 BFD241A2 LUI V0, 0xBFD2
+BFD06716 3042BFD2 LDC1 F30, 12354(S2)
+BFD06718 80E43042 ADDIU V0, V0, -32540
+BFD0671C 0004B443 BNE V1, V0, 0xBFD06728
+BFD0671E 0C000004 SLL ZERO, A0, 1
+BFD06720 0C00 NOP
+BFD06722 ED01 LI V0, 1
+BFD06724 CC02 B 0xBFD0672A
+BFD06726 0C00 NOP
+BFD06728 0C40 MOVE V0, ZERO
+BFD0672A 001840E2 BEQZC V0, 0xBFD0675E
+1386: {\r
+1387: /* Has the task already been resumed from within an ISR? */\r
+1388: if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )\r
+BFD0672E 0014FC5E LW V0, 20(S8)
+BFD06732 69AA LW V1, 40(V0)
+BFD06734 BFD241A2 LUI V0, 0xBFD2
+BFD06736 3042BFD2 LDC1 F30, 12354(S2)
+BFD06738 80D03042 ADDIU V0, V0, -32560
+BFD0673C 000F9443 BEQ V1, V0, 0xBFD0675E
+BFD0673E 0C00000F SLL ZERO, T7, 1
+BFD06740 0C00 NOP
+1389: {\r
+1390: /* Is it in the suspended list because it is in the Suspended\r
+1391: state, or because is is blocked with no timeout? */\r
+1392: if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE )\r
+BFD06742 0014FC5E LW V0, 20(S8)
+BFD06746 692A LW V0, 40(V0)
+BFD06748 000340A2 BNEZC V0, 0xBFD06752
+BFD0674C ED01 LI V0, 1
+BFD0674E CC02 B 0xBFD06754
+BFD06750 0C00 NOP
+BFD06752 0C40 MOVE V0, ZERO
+BFD06754 000340E2 BEQZC V0, 0xBFD0675E
+1393: {\r
+1394: xReturn = pdTRUE;\r
+BFD06758 ED01 LI V0, 1
+BFD0675A 0010F85E SW V0, 16(S8)
+1395: }\r
+1396: else\r
+1397: {\r
+1398: mtCOVERAGE_TEST_MARKER();\r
+1399: }\r
+1400: }\r
+1401: else\r
+1402: {\r
+1403: mtCOVERAGE_TEST_MARKER();\r
+1404: }\r
+1405: }\r
+1406: else\r
+1407: {\r
+1408: mtCOVERAGE_TEST_MARKER();\r
+1409: }\r
+1410: \r
+1411: return xReturn;\r
+BFD0675E 0010FC5E LW V0, 16(S8)
+1412: } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */\r
+BFD06762 0FBE MOVE SP, S8
+BFD06764 4BE7 LW RA, 28(SP)
+BFD06766 4BC6 LW S8, 24(SP)
+BFD06768 4C11 ADDIU SP, SP, 32
+BFD0676A 459F JR16 RA
+BFD0676C 0C00 NOP
+1413: \r
+1414: #endif /* INCLUDE_vTaskSuspend */\r
+1415: /*-----------------------------------------------------------*/\r
+1416: \r
+1417: #if ( INCLUDE_vTaskSuspend == 1 )\r
+1418: \r
+1419: void vTaskResume( TaskHandle_t xTaskToResume )\r
+1420: {\r
+BFD040E4 4FF1 ADDIU SP, SP, -32
+BFD040E6 CBE7 SW RA, 28(SP)
+BFD040E8 CBC6 SW S8, 24(SP)
+BFD040EA 0FDD MOVE S8, SP
+BFD040EC 0020F89E SW A0, 32(S8)
+1421: TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;\r
+BFD040F0 0020FC5E LW V0, 32(S8)
+BFD040F4 0010F85E SW V0, 16(S8)
+1422: \r
+1423: /* It does not make sense to resume the calling task. */\r
+1424: configASSERT( xTaskToResume );\r
+BFD040F8 0020FC5E LW V0, 32(S8)
+BFD040FC 000940A2 BNEZC V0, 0xBFD04112
+BFD04100 BFD141A2 LUI V0, 0xBFD1
+BFD04102 3082BFD1 LDC1 F30, 12418(S1)
+BFD04104 98103082 ADDIU A0, V0, -26608
+BFD04106 30A09810 SWC1 F0, 12448(S0)
+BFD04108 059030A0 ADDIU A1, ZERO, 1424
+BFD0410A 0590 ADDU V1, S0, S1
+BFD0410C 4B7E77E8 JALS vAssertCalled
+BFD0410E 4B7E LW K1, 120(SP)
+BFD04110 0C00 NOP
+1425: \r
+1426: /* The parameter cannot be NULL as it is impossible to resume the\r
+1427: currently executing task. */\r
+1428: if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )\r
+BFD04112 0010FC5E LW V0, 16(S8)
+BFD04116 005640E2 BEQZC V0, 0xBFD041C6
+BFD0411A 8030FC5C LW V0, -32720(GP)
+BFD0411E 0010FC7E LW V1, 16(S8)
+BFD04122 00509443 BEQ V1, V0, 0xBFD041C6
+BFD04124 0C000050 SLL V0, S0, 1
+BFD04126 0C00 NOP
+1429: {\r
+1430: taskENTER_CRITICAL();\r
+BFD04128 33B877E8 JALS vTaskEnterCritical
+BFD0412A 0C0033B8 ADDIU SP, T8, 3072
+BFD0412C 0C00 NOP
+1431: {\r
+1432: if( prvTaskIsTaskSuspended( pxTCB ) == pdTRUE )\r
+BFD0412E 0010FC9E LW A0, 16(S8)
+BFD04132 336E77E8 JALS prvTaskIsTaskSuspended
+BFD04134 0C00336E ADDIU K1, T6, 3072
+BFD04136 0C00 NOP
+BFD04138 0C62 MOVE V1, V0
+BFD0413A ED01 LI V0, 1
+BFD0413C 0040B443 BNE V1, V0, 0xBFD041C0
+BFD0413E 0C000040 SLL V0, ZERO, 1
+BFD04140 0C00 NOP
+1433: {\r
+1434: traceTASK_RESUME( pxTCB );\r
+1435: \r
+1436: /* As we are in a critical section we can access the ready\r
+1437: lists even if the scheduler is suspended. */\r
+1438: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
+BFD04142 0010FC5E LW V0, 16(S8)
+BFD04146 6D22 ADDIU V0, V0, 4
+BFD04148 0C82 MOVE A0, V0
+BFD0414A 00C877E8 JALS uxListRemove
+BFD0414C 0C0000C8 SLL A2, T0, 1
+BFD0414E 0C00 NOP
+1439: prvAddTaskToReadyList( pxTCB );\r
+BFD04150 0010FC5E LW V0, 16(S8)
+BFD04154 692B LW V0, 44(V0)
+BFD04156 ED81 LI V1, 1
+BFD04158 18100062 SLLV V1, V0, V1
+BFD0415A FC5C1810 SB ZERO, -932(S0)
+BFD0415C 8040FC5C LW V0, -32704(GP)
+BFD04160 44D3 OR16 V0, V1
+BFD04162 8040F85C SW V0, -32704(GP)
+BFD04166 0010FC5E LW V0, 16(S8)
+BFD0416A 692B LW V0, 44(V0)
+BFD0416C 2524 SLL V0, V0, 2
+BFD0416E 25A4 SLL V1, V0, 2
+BFD04170 05B4 ADDU V1, V0, V1
+BFD04172 BFD241A2 LUI V0, 0xBFD2
+BFD04174 3042BFD2 LDC1 F30, 12354(S2)
+BFD04176 806C3042 ADDIU V0, V0, -32660
+BFD0417A 05A6 ADDU V1, V1, V0
+BFD0417C 0010FC5E LW V0, 16(S8)
+BFD04180 6D22 ADDIU V0, V0, 4
+BFD04182 0C83 MOVE A0, V1
+BFD04184 0CA2 MOVE A1, V0
+BFD04186 3E4A77E8 JALS vListInsertEnd
+BFD04188 0C003E4A LH S2, 3072(T2)
+BFD0418A 0C00 NOP
+1440: \r
+1441: /* We may have just resumed a higher priority task. */\r
+1442: if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
+BFD0418C 0010FC5E LW V0, 16(S8)
+BFD04190 69AB LW V1, 44(V0)
+BFD04192 8030FC5C LW V0, -32720(GP)
+BFD04196 692B LW V0, 44(V0)
+BFD04198 13900043 SLTU V0, V1, V0
+BFD0419A 40A21390 ADDI GP, S0, 16546
+BFD0419C 001040A2 BNEZC V0, 0xBFD041C0
+1443: {\r
+1444: /* This yield may not cause the task just resumed to run,\r
+1445: but will leave the lists in the correct state for the\r
+1446: next yield. */\r
+1447: taskYIELD_IF_USING_PREEMPTION();\r
+BFD041A0 4E5677E8 JALS ulPortGetCP0Cause
+BFD041A2 4E56 ADDIU S2, S2, -5
+BFD041A4 0C00 NOP
+BFD041A6 0014F85E SW V0, 20(S8)
+BFD041AA 0014FC5E LW V0, 20(S8)
+BFD041AE 01005042 ORI V0, V0, 256
+BFD041B2 0014F85E SW V0, 20(S8)
+BFD041B6 0014FC9E LW A0, 20(S8)
+BFD041BA 4E6677E8 JALS vPortSetCP0Cause
+BFD041BC 4E66 ADDIU S3, S3, 3
+BFD041BE 0C00 NOP
+1448: }\r
+1449: else\r
+1450: {\r
+1451: mtCOVERAGE_TEST_MARKER();\r
+1452: }\r
+1453: }\r
+1454: else\r
+1455: {\r
+1456: mtCOVERAGE_TEST_MARKER();\r
+1457: }\r
+1458: }\r
+1459: taskEXIT_CRITICAL();\r
+BFD041C0 40AA77E8 JALS vTaskExitCritical
+BFD041C2 0C0040AA BNEZC T2, 0xBFD059C6
+BFD041C4 0C00 NOP
+1460: }\r
+1461: else\r
+1462: {\r
+1463: mtCOVERAGE_TEST_MARKER();\r
+1464: }\r
+1465: }\r
+BFD041C6 0FBE MOVE SP, S8
+BFD041C8 4BE7 LW RA, 28(SP)
+BFD041CA 4BC6 LW S8, 24(SP)
+BFD041CC 4C11 ADDIU SP, SP, 32
+BFD041CE 459F JR16 RA
+BFD041D0 0C00 NOP
+1466: \r
+1467: #endif /* INCLUDE_vTaskSuspend */\r
+1468: \r
+1469: /*-----------------------------------------------------------*/\r
+1470: \r
+1471: #if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )\r
+1472: \r
+1473: BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )\r
+1474: {\r
+BFD041D4 4FED ADDIU SP, SP, -40
+BFD041D6 CBE9 SW RA, 36(SP)
+BFD041D8 CBC8 SW S8, 32(SP)
+BFD041DA 0FDD MOVE S8, SP
+BFD041DC 0028F89E SW A0, 40(S8)
+1475: BaseType_t xYieldRequired = pdFALSE;\r
+BFD041E0 0010F81E SW ZERO, 16(S8)
+1476: TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;\r
+BFD041E4 0028FC5E LW V0, 40(S8)
+BFD041E8 0014F85E SW V0, 20(S8)
+1477: UBaseType_t uxSavedInterruptStatus;\r
+1478: \r
+1479: configASSERT( xTaskToResume );\r
+BFD041EC 0028FC5E LW V0, 40(S8)
+BFD041F0 000940A2 BNEZC V0, 0xBFD04206
+BFD041F4 BFD141A2 LUI V0, 0xBFD1
+BFD041F6 3082BFD1 LDC1 F30, 12418(S1)
+BFD041F8 98103082 ADDIU A0, V0, -26608
+BFD041FA 30A09810 SWC1 F0, 12448(S0)
+BFD041FC 05C730A0 ADDIU A1, ZERO, 1479
+BFD041FE 05C7 SUBU V1, V1, A0
+BFD04200 4B7E77E8 JALS vAssertCalled
+BFD04202 4B7E LW K1, 120(SP)
+BFD04204 0C00 NOP
+1480: \r
+1481: /* RTOS ports that support interrupt nesting have the concept of a\r
+1482: maximum system call (or maximum API call) interrupt priority.\r
+1483: Interrupts that are above the maximum system call priority are keep\r
+1484: permanently enabled, even when the RTOS kernel is in a critical section,\r
+1485: but cannot make any calls to FreeRTOS API functions. If configASSERT()\r
+1486: is defined in FreeRTOSConfig.h then\r
+1487: portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r
+1488: failure if a FreeRTOS API function is called from an interrupt that has\r
+1489: been assigned a priority above the configured maximum system call\r
+1490: priority. Only FreeRTOS functions that end in FromISR can be called\r
+1491: from interrupts that have been assigned a priority at or (logically)\r
+1492: below the maximum system call interrupt priority. FreeRTOS maintains a\r
+1493: separate interrupt safe API to ensure interrupt entry is as fast and as\r
+1494: simple as possible. More information (albeit Cortex-M specific) is\r
+1495: provided on the following link:\r
+1496: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r
+1497: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
+1498: \r
+1499: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+BFD04206 475E77E8 JALS uxPortSetInterruptMaskFromISR
+BFD0420A 0C00 NOP
+BFD0420C 0018F85E SW V0, 24(S8)
+1500: {\r
+1501: if( prvTaskIsTaskSuspended( pxTCB ) == pdTRUE )\r
+BFD04210 0014FC9E LW A0, 20(S8)
+BFD04214 336E77E8 JALS prvTaskIsTaskSuspended
+BFD04216 0C00336E ADDIU K1, T6, 3072
+BFD04218 0C00 NOP
+BFD0421A 0C62 MOVE V1, V0
+BFD0421C ED01 LI V0, 1
+BFD0421E 0044B443 BNE V1, V0, 0xBFD042AA
+BFD04220 0C000044 SLL V0, A0, 1
+BFD04222 0C00 NOP
+1502: {\r
+1503: traceTASK_RESUME_FROM_ISR( pxTCB );\r
+1504: \r
+1505: /* Check the ready lists can be accessed. */\r
+1506: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
+BFD04224 805CFC5C LW V0, -32676(GP)
+BFD04228 003440A2 BNEZC V0, 0xBFD04294
+1507: {\r
+1508: /* Ready lists can be accessed so move the task from the\r
+1509: suspended list to the ready list directly. */\r
+1510: if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
+BFD0422C 0014FC5E LW V0, 20(S8)
+BFD04230 69AB LW V1, 44(V0)
+BFD04232 8030FC5C LW V0, -32720(GP)
+BFD04236 692B LW V0, 44(V0)
+BFD04238 13900043 SLTU V0, V1, V0
+BFD0423A 40A21390 ADDI GP, S0, 16546
+BFD0423C 000340A2 BNEZC V0, 0xBFD04246
+1511: {\r
+1512: xYieldRequired = pdTRUE;\r
+BFD04240 ED01 LI V0, 1
+BFD04242 0010F85E SW V0, 16(S8)
+1513: }\r
+1514: else\r
+1515: {\r
+1516: mtCOVERAGE_TEST_MARKER();\r
+1517: }\r
+1518: \r
+1519: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
+BFD04246 0014FC5E LW V0, 20(S8)
+BFD0424A 6D22 ADDIU V0, V0, 4
+BFD0424C 0C82 MOVE A0, V0
+BFD0424E 00C877E8 JALS uxListRemove
+BFD04250 0C0000C8 SLL A2, T0, 1
+BFD04252 0C00 NOP
+1520: prvAddTaskToReadyList( pxTCB );\r
+BFD04254 0014FC5E LW V0, 20(S8)
+BFD04258 692B LW V0, 44(V0)
+BFD0425A ED81 LI V1, 1
+BFD0425C 18100062 SLLV V1, V0, V1
+BFD0425E FC5C1810 SB ZERO, -932(S0)
+BFD04260 8040FC5C LW V0, -32704(GP)
+BFD04264 44D3 OR16 V0, V1
+BFD04266 8040F85C SW V0, -32704(GP)
+BFD0426A 0014FC5E LW V0, 20(S8)
+BFD0426E 692B LW V0, 44(V0)
+BFD04270 2524 SLL V0, V0, 2
+BFD04272 25A4 SLL V1, V0, 2
+BFD04274 05B4 ADDU V1, V0, V1
+BFD04276 BFD241A2 LUI V0, 0xBFD2
+BFD04278 3042BFD2 LDC1 F30, 12354(S2)
+BFD0427A 806C3042 ADDIU V0, V0, -32660
+BFD0427E 05A6 ADDU V1, V1, V0
+BFD04280 0014FC5E LW V0, 20(S8)
+BFD04284 6D22 ADDIU V0, V0, 4
+BFD04286 0C83 MOVE A0, V1
+BFD04288 0CA2 MOVE A1, V0
+BFD0428A 3E4A77E8 JALS vListInsertEnd
+BFD0428C 0C003E4A LH S2, 3072(T2)
+BFD0428E 0C00 NOP
+BFD04290 CC0C B 0xBFD042AA
+BFD04292 0C00 NOP
+1521: }\r
+1522: else\r
+1523: {\r
+1524: /* The delayed or ready lists cannot be accessed so the task\r
+1525: is held in the pending ready list until the scheduler is\r
+1526: unsuspended. */\r
+1527: vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r
+BFD04294 0014FC5E LW V0, 20(S8)
+BFD04296 6D2C0014 EXT ZERO, S4, 20, 14
+BFD04298 6D2C ADDIU V0, V0, 24
+BFD0429A BFD241A3 LUI V1, 0xBFD2
+BFD0429C 3083BFD2 LDC1 F30, 12419(S2)
+BFD0429E 80D03083 ADDIU A0, V1, -32560
+BFD042A2 0CA2 MOVE A1, V0
+BFD042A4 3E4A77E8 JALS vListInsertEnd
+BFD042A6 0C003E4A LH S2, 3072(T2)
+BFD042A8 0C00 NOP
+1528: }\r
+1529: }\r
+1530: else\r
+1531: {\r
+1532: mtCOVERAGE_TEST_MARKER();\r
+1533: }\r
+1534: }\r
+1535: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+BFD042AA 0018FC9E LW A0, 24(S8)
+BFD042AE 4D5E77E8 JALS vPortClearInterruptMaskFromISR
+BFD042B0 4D5E ADDIU T2, T2, -1
+BFD042B2 0C00 NOP
+1536: \r
+1537: return xYieldRequired;\r
+BFD042B4 0010FC5E LW V0, 16(S8)
+1538: }\r
+BFD042B8 0FBE MOVE SP, S8
+BFD042BA 4BE9 LW RA, 36(SP)
+BFD042BC 4BC8 LW S8, 32(SP)
+BFD042BE 4C15 ADDIU SP, SP, 40
+BFD042C0 459F JR16 RA
+BFD042C2 0C00 NOP
+1539: \r
+1540: #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */\r
+1541: /*-----------------------------------------------------------*/\r
+1542: \r
+1543: void vTaskStartScheduler( void )\r
+1544: {\r
+BFD04AC0 4FE9 ADDIU SP, SP, -48
+BFD04AC2 CBEB SW RA, 44(SP)
+BFD04AC4 CBCA SW S8, 40(SP)
+BFD04AC6 0FDD MOVE S8, SP
+1545: BaseType_t xReturn;\r
+1546: \r
+1547: /* Add the idle task at the lowest priority. */\r
+1548: #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
+1549: {\r
+1550: /* Create the idle task, storing its handle in xIdleTaskHandle so it can\r
+1551: be returned by the xTaskGetIdleTaskHandle() function. */\r
+1552: xReturn = xTaskCreate( prvIdleTask, "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */\r
+1553: }\r
+1554: #else\r
+1555: {\r
+1556: /* Create the idle task without storing its handle. */\r
+1557: xReturn = xTaskCreate( prvIdleTask, "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), NULL ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */\r
+BFD04AC8 C804 SW ZERO, 16(SP)
+BFD04ACA C805 SW ZERO, 20(SP)
+BFD04ACC C806 SW ZERO, 24(SP)
+BFD04ACE C807 SW ZERO, 28(SP)
+BFD04AD0 BFD141A2 LUI V0, 0xBFD1
+BFD04AD2 3082BFD1 LDC1 F30, 12418(S1)
+BFD04AD4 8BC53082 ADDIU A0, V0, -29755
+BFD04AD6 8BC5 SB A3, 5(A0)
+BFD04AD8 BFD141A2 LUI V0, 0xBFD1
+BFD04ADA 30A2BFD1 LDC1 F30, 12450(S1)
+BFD04ADC 982830A2 ADDIU A1, V0, -26584
+BFD04ADE 30C09828 SWC1 F1, 12480(T0)
+BFD04AE0 00BE30C0 ADDIU A2, ZERO, 190
+BFD04AE4 0CE0 MOVE A3, ZERO
+BFD04AE6 0A9A77E8 JALS xTaskGenericCreate
+BFD04AE8 0A9A LBU A1, 10(S1)
+BFD04AEA 0C00 NOP
+BFD04AEC 0020F85E SW V0, 32(S8)
+1558: }\r
+1559: #endif /* INCLUDE_xTaskGetIdleTaskHandle */\r
+1560: \r
+1561: #if ( configUSE_TIMERS == 1 )\r
+1562: {\r
+1563: if( xReturn == pdPASS )\r
+BFD04AF0 0020FC7E LW V1, 32(S8)
+BFD04AF4 ED01 LI V0, 1
+BFD04AF6 0006B443 BNE V1, V0, 0xBFD04B06
+BFD04AF8 0C000006 SLL ZERO, A2, 1
+BFD04AFA 0C00 NOP
+1564: {\r
+1565: xReturn = xTimerCreateTimerTask();\r
+BFD04AFC 3D3677E8 JALS xTimerCreateTimerTask
+BFD04AFE 0C003D36 LH T1, 3072(S6)
+BFD04B00 0C00 NOP
+BFD04B02 0020F85E SW V0, 32(S8)
+1566: }\r
+1567: else\r
+1568: {\r
+1569: mtCOVERAGE_TEST_MARKER();\r
+1570: }\r
+1571: }\r
+1572: #endif /* configUSE_TIMERS */\r
+1573: \r
+1574: if( xReturn == pdPASS )\r
+BFD04B06 0020FC7E LW V1, 32(S8)
+BFD04B0A ED01 LI V0, 1
+BFD04B0C 0031B443 BNE V1, V0, 0xBFD04B72
+BFD04B0E 0C000031 SLL AT, S1, 1
+BFD04B10 0C00 NOP
+1575: {\r
+1576: /* Interrupts are turned off here, to ensure a tick does not occur\r
+1577: before or during the call to xPortStartScheduler(). The stacks of\r
+1578: the created tasks contain a status word with interrupts switched on\r
+1579: so interrupts will automatically get re-enabled when the first task\r
+1580: starts to run. */\r
+1581: portDISABLE_INTERRUPTS();\r
+BFD04B12 4E3677E8 JALS ulPortGetCP0Status
+BFD04B14 4E36 ADDIU S1, S1, -5
+BFD04B16 0C00 NOP
+BFD04B18 0024F85E SW V0, 36(S8)
+BFD04B1C 0024FC7E LW V1, 36(S8)
+BFD04B20 000141A2 LUI V0, 0x1
+BFD04B24 FC005042 ORI V0, V0, -1024
+BFD04B26 4493FC00 LW ZERO, 17555(ZERO)
+BFD04B28 4493 AND16 V0, V1
+BFD04B2A 50400042 SRL V0, V0, 10
+BFD04B2C B0425040 ORI V0, ZERO, -20414
+BFD04B2E 0003B042 SLTIU V0, V0, 3
+BFD04B32 001140E2 BEQZC V0, 0xBFD04B58
+BFD04B36 0024FC7E LW V1, 36(S8)
+BFD04B3A FFFE41A2 LUI V0, 0xFFFE
+BFD04B3C 5042FFFE LW RA, 20546(S8)
+BFD04B3E 03FF5042 ORI V0, V0, 1023
+BFD04B42 4493 AND16 V0, V1
+BFD04B44 0024F85E SW V0, 36(S8)
+BFD04B48 0024FC5E LW V0, 36(S8)
+BFD04B4C 0C005042 ORI V0, V0, 3072
+BFD04B4E 0C00 NOP
+BFD04B50 0C82 MOVE A0, V0
+BFD04B52 4E4677E8 JALS vPortSetCP0Status
+BFD04B54 4E46 ADDIU S2, S2, 3
+BFD04B56 0C00 NOP
+1582: \r
+1583: #if ( configUSE_NEWLIB_REENTRANT == 1 )\r
+1584: {\r
+1585: /* Switch Newlib's _impure_ptr variable to point to the _reent\r
+1586: structure specific to the task that will run first. */\r
+1587: _impure_ptr = &( pxCurrentTCB->xNewLib_reent );\r
+1588: }\r
+1589: #endif /* configUSE_NEWLIB_REENTRANT */\r
+1590: \r
+1591: xNextTaskUnblockTime = portMAX_DELAY;\r
+BFD04B58 ED7F LI V0, -1
+BFD04B5A 8058F85C SW V0, -32680(GP)
+1592: xSchedulerRunning = pdTRUE;\r
+BFD04B5E ED01 LI V0, 1
+BFD04B60 8044F85C SW V0, -32700(GP)
+1593: xTickCount = ( TickType_t ) 0U;\r
+BFD04B64 803CF81C SW ZERO, -32708(GP)
+1594: \r
+1595: /* If configGENERATE_RUN_TIME_STATS is defined then the following\r
+1596: macro must be defined to configure the timer/counter used to generate\r
+1597: the run time counter time base. */\r
+1598: portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();\r
+1599: \r
+1600: /* Setting up the timer tick is hardware specific and thus in the\r
+1601: portable interface. */\r
+1602: if( xPortStartScheduler() != pdFALSE )\r
+BFD04B68 344C77E8 JALS xPortStartScheduler
+BFD04B6A 0C00344C LHU V0, 3072(T4)
+BFD04B6C 0C00 NOP
+BFD04B6E CC0E B 0xBFD04B8C
+BFD04B70 0C00 NOP
+1603: {\r
+1604: /* Should not reach here as if the scheduler is running the\r
+1605: function will not return. */\r
+1606: }\r
+1607: else\r
+1608: {\r
+1609: /* Should only reach here if a task calls xTaskEndScheduler(). */\r
+1610: }\r
+1611: }\r
+1612: else\r
+1613: {\r
+1614: /* This line will only be reached if the kernel could not be started,\r
+1615: because there was not enough FreeRTOS heap to create the idle task\r
+1616: or the timer task. */\r
+1617: configASSERT( xReturn );\r
+BFD04B72 0020FC5E LW V0, 32(S8)
+BFD04B76 000940A2 BNEZC V0, 0xBFD04B8C
+BFD04B7A BFD141A2 LUI V0, 0xBFD1
+BFD04B7C 3082BFD1 LDC1 F30, 12418(S1)
+BFD04B7E 98103082 ADDIU A0, V0, -26608
+BFD04B80 30A09810 SWC1 F0, 12448(S0)
+BFD04B82 065130A0 ADDIU A1, ZERO, 1617
+BFD04B84 0651 SUBU A0, S0, A1
+BFD04B86 4B7E77E8 JALS vAssertCalled
+BFD04B88 4B7E LW K1, 120(SP)
+BFD04B8A 0C00 NOP
+1618: }\r
+1619: }\r
+BFD04B8C 0FBE MOVE SP, S8
+BFD04B8E 4BEB LW RA, 44(SP)
+BFD04B90 4BCA LW S8, 40(SP)
+BFD04B92 4C19 ADDIU SP, SP, 48
+BFD04B94 459F JR16 RA
+BFD04B96 0C00 NOP
+1620: /*-----------------------------------------------------------*/\r
+1621: \r
+1622: void vTaskEndScheduler( void )\r
+1623: {\r
+BFD07F00 4FF1 ADDIU SP, SP, -32
+BFD07F02 CBE7 SW RA, 28(SP)
+BFD07F04 CBC6 SW S8, 24(SP)
+BFD07F06 0FDD MOVE S8, SP
+1624: /* Stop the scheduler interrupts and call the portable scheduler end\r
+1625: routine so the original ISRs can be restored if necessary. The port\r
+1626: layer must ensure interrupts enable bit is left in the correct state. */\r
+1627: portDISABLE_INTERRUPTS();\r
+BFD07F08 4E3677E8 JALS ulPortGetCP0Status
+BFD07F0A 4E36 ADDIU S1, S1, -5
+BFD07F0C 0C00 NOP
+BFD07F0E 0010F85E SW V0, 16(S8)
+BFD07F12 0010FC7E LW V1, 16(S8)
+BFD07F16 000141A2 LUI V0, 0x1
+BFD07F1A FC005042 ORI V0, V0, -1024
+BFD07F1C 4493FC00 LW ZERO, 17555(ZERO)
+BFD07F1E 4493 AND16 V0, V1
+BFD07F20 50400042 SRL V0, V0, 10
+BFD07F22 B0425040 ORI V0, ZERO, -20414
+BFD07F24 0003B042 SLTIU V0, V0, 3
+BFD07F28 001140E2 BEQZC V0, 0xBFD07F4E
+BFD07F2C 0010FC7E LW V1, 16(S8)
+BFD07F30 FFFE41A2 LUI V0, 0xFFFE
+BFD07F32 5042FFFE LW RA, 20546(S8)
+BFD07F34 03FF5042 ORI V0, V0, 1023
+BFD07F38 4493 AND16 V0, V1
+BFD07F3A 0010F85E SW V0, 16(S8)
+BFD07F3E 0010FC5E LW V0, 16(S8)
+BFD07F42 0C005042 ORI V0, V0, 3072
+BFD07F44 0C00 NOP
+BFD07F46 0C82 MOVE A0, V0
+BFD07F48 4E4677E8 JALS vPortSetCP0Status
+BFD07F4A 4E46 ADDIU S2, S2, 3
+BFD07F4C 0C00 NOP
+1628: xSchedulerRunning = pdFALSE;\r
+BFD07F4E 8044F81C SW ZERO, -32700(GP)
+1629: vPortEndScheduler();\r
+BFD07F52 4BD477E8 JALS vPortEndScheduler
+BFD07F54 4BD4 LW S8, 80(SP)
+BFD07F56 0C00 NOP
+1630: }\r
+BFD07F58 0FBE MOVE SP, S8
+BFD07F5A 4BE7 LW RA, 28(SP)
+BFD07F5C 4BC6 LW S8, 24(SP)
+BFD07F5E 4C11 ADDIU SP, SP, 32
+BFD07F60 459F JR16 RA
+BFD07F62 0C00 NOP
+1631: /*----------------------------------------------------------*/\r
+1632: \r
+1633: void vTaskSuspendAll( void )\r
+1634: {\r
+BFD09DE8 4FB0 ADDIU SP, SP, -8
+BFD09DEA CBC1 SW S8, 4(SP)
+BFD09DEC 0FDD MOVE S8, SP
+1635: /* A critical section is not required as the variable is of type\r
+1636: BaseType_t. Please read Richard Barry's reply in the following link to a\r
+1637: post in the FreeRTOS support forum before reporting this as a bug! -\r
+1638: http://goo.gl/wu4acr */\r
+1639: ++uxSchedulerSuspended;\r
+BFD09DEE 805CFC5C LW V0, -32676(GP)
+BFD09DF2 6D20 ADDIU V0, V0, 1
+BFD09DF4 805CF85C SW V0, -32676(GP)
+1640: }\r
+BFD09DF8 0FBE MOVE SP, S8
+BFD09DFA 4BC1 LW S8, 4(SP)
+BFD09DFC 4C05 ADDIU SP, SP, 8
+BFD09DFE 459F JR16 RA
+BFD09E00 0C00 NOP
+1641: /*----------------------------------------------------------*/\r
+1642: \r
+1643: #if ( configUSE_TICKLESS_IDLE != 0 )\r
+1644: \r
+1645: static TickType_t prvGetExpectedIdleTime( void )\r
+1646: {\r
+1647: TickType_t xReturn;\r
+1648: \r
+1649: if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )\r
+1650: {\r
+1651: xReturn = 0;\r
+1652: }\r
+1653: else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )\r
+1654: {\r
+1655: /* There are other idle priority tasks in the ready state. If\r
+1656: time slicing is used then the very next tick interrupt must be\r
+1657: processed. */\r
+1658: xReturn = 0;\r
+1659: }\r
+1660: else\r
+1661: {\r
+1662: xReturn = xNextTaskUnblockTime - xTickCount;\r
+1663: }\r
+1664: \r
+1665: return xReturn;\r
+1666: }\r
+1667: \r
+1668: #endif /* configUSE_TICKLESS_IDLE */\r
+1669: /*----------------------------------------------------------*/\r
+1670: \r
+1671: BaseType_t xTaskResumeAll( void )\r
+1672: {\r
+BFD02B1C 4FED ADDIU SP, SP, -40
+BFD02B1E CBE9 SW RA, 36(SP)
+BFD02B20 CBC8 SW S8, 32(SP)
+BFD02B22 0FDD MOVE S8, SP
+1673: TCB_t *pxTCB;\r
+1674: BaseType_t xAlreadyYielded = pdFALSE;\r
+BFD02B24 0010F81E SW ZERO, 16(S8)
+1675: \r
+1676: /* If uxSchedulerSuspended is zero then this function does not match a\r
+1677: previous call to vTaskSuspendAll(). */\r
+1678: configASSERT( uxSchedulerSuspended );\r
+BFD02B28 805CFC5C LW V0, -32676(GP)
+BFD02B2C 000940A2 BNEZC V0, 0xBFD02B42
+BFD02B30 BFD141A2 LUI V0, 0xBFD1
+BFD02B32 3082BFD1 LDC1 F30, 12418(S1)
+BFD02B34 98103082 ADDIU A0, V0, -26608
+BFD02B36 30A09810 SWC1 F0, 12448(S0)
+BFD02B38 068E30A0 ADDIU A1, ZERO, 1678
+BFD02B3A 068E ADDU A1, A3, S0
+BFD02B3C 4B7E77E8 JALS vAssertCalled
+BFD02B3E 4B7E LW K1, 120(SP)
+BFD02B40 0C00 NOP
+1679: \r
+1680: /* It is possible that an ISR caused a task to be removed from an event\r
+1681: list while the scheduler was suspended. If this was the case then the\r
+1682: removed task will have been added to the xPendingReadyList. Once the\r
+1683: scheduler has been resumed it is safe to move all the pending ready\r
+1684: tasks from this list into their appropriate ready list. */\r
+1685: taskENTER_CRITICAL();\r
+BFD02B42 33B877E8 JALS vTaskEnterCritical
+BFD02B44 0C0033B8 ADDIU SP, T8, 3072
+BFD02B46 0C00 NOP
+1686: {\r
+1687: --uxSchedulerSuspended;\r
+BFD02B48 805CFC5C LW V0, -32676(GP)
+BFD02B4C 6D2E ADDIU V0, V0, -1
+BFD02B4E 805CF85C SW V0, -32676(GP)
+1688: \r
+1689: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
+BFD02B52 805CFC5C LW V0, -32676(GP)
+BFD02B56 007D40A2 BNEZC V0, 0xBFD02C54
+1690: {\r
+1691: if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )\r
+BFD02B5A 8038FC5C LW V0, -32712(GP)
+BFD02B5E 007940E2 BEQZC V0, 0xBFD02C54
+1692: {\r
+1693: /* Move any readied tasks from the pending list into the\r
+1694: appropriate ready list. */\r
+1695: while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )\r
+BFD02B62 CC42 B 0xBFD02BE8
+BFD02B64 0C00 NOP
+BFD02BE8 BFD241A2 LUI V0, 0xBFD2
+BFD02BEA FC42BFD2 LDC1 F30, -958(S2)
+BFD02BEC 80D0FC42 LW V0, -32560(V0)
+BFD02BF0 FFB940A2 BNEZC V0, 0xBFD02B66
+BFD02BF2 FC5CFFB9 LW SP, -932(T9)
+1696: {\r
+1697: pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );\r
+BFD02B66 BFD241A2 LUI V0, 0xBFD2
+BFD02B68 3042BFD2 LDC1 F30, 12354(S2)
+BFD02B6A 80D03042 ADDIU V0, V0, -32560
+BFD02B6E 6923 LW V0, 12(V0)
+BFD02B70 6923 LW V0, 12(V0)
+BFD02B72 0014F85E SW V0, 20(S8)
+1698: ( void ) uxListRemove( &( pxTCB->xEventListItem ) );\r
+BFD02B76 0014FC5E LW V0, 20(S8)
+BFD02B78 6D2C0014 EXT ZERO, S4, 20, 14
+BFD02B7A 6D2C ADDIU V0, V0, 24
+BFD02B7C 0C82 MOVE A0, V0
+BFD02B7E 00C877E8 JALS uxListRemove
+BFD02B80 0C0000C8 SLL A2, T0, 1
+BFD02B82 0C00 NOP
+1699: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
+BFD02B84 0014FC5E LW V0, 20(S8)
+BFD02B88 6D22 ADDIU V0, V0, 4
+BFD02B8A 0C82 MOVE A0, V0
+BFD02B8C 00C877E8 JALS uxListRemove
+BFD02B8E 0C0000C8 SLL A2, T0, 1
+BFD02B90 0C00 NOP
+1700: prvAddTaskToReadyList( pxTCB );\r
+BFD02B92 0014FC5E LW V0, 20(S8)
+BFD02B96 692B LW V0, 44(V0)
+BFD02B98 ED81 LI V1, 1
+BFD02B9A 18100062 SLLV V1, V0, V1
+BFD02B9C FC5C1810 SB ZERO, -932(S0)
+BFD02B9E 8040FC5C LW V0, -32704(GP)
+BFD02BA2 44D3 OR16 V0, V1
+BFD02BA4 8040F85C SW V0, -32704(GP)
+BFD02BA8 0014FC5E LW V0, 20(S8)
+BFD02BAC 692B LW V0, 44(V0)
+BFD02BAE 2524 SLL V0, V0, 2
+BFD02BB0 25A4 SLL V1, V0, 2
+BFD02BB2 05B4 ADDU V1, V0, V1
+BFD02BB4 BFD241A2 LUI V0, 0xBFD2
+BFD02BB6 3042BFD2 LDC1 F30, 12354(S2)
+BFD02BB8 806C3042 ADDIU V0, V0, -32660
+BFD02BBC 05A6 ADDU V1, V1, V0
+BFD02BBE 0014FC5E LW V0, 20(S8)
+BFD02BC2 6D22 ADDIU V0, V0, 4
+BFD02BC4 0C83 MOVE A0, V1
+BFD02BC6 0CA2 MOVE A1, V0
+BFD02BC8 3E4A77E8 JALS vListInsertEnd
+BFD02BCA 0C003E4A LH S2, 3072(T2)
+BFD02BCC 0C00 NOP
+1701: \r
+1702: /* If the moved task has a priority higher than the current\r
+1703: task then a yield must be performed. */\r
+1704: if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
+BFD02BCE 0014FC5E LW V0, 20(S8)
+BFD02BD2 69AB LW V1, 44(V0)
+BFD02BD4 8030FC5C LW V0, -32720(GP)
+BFD02BD8 692B LW V0, 44(V0)
+BFD02BDA 13900043 SLTU V0, V1, V0
+BFD02BDC 40A21390 ADDI GP, S0, 16546
+BFD02BDE 000340A2 BNEZC V0, 0xBFD02BE8
+1705: {\r
+1706: xYieldPending = pdTRUE;\r
+BFD02BE2 ED01 LI V0, 1
+BFD02BE4 804CF85C SW V0, -32692(GP)
+1707: }\r
+1708: else\r
+1709: {\r
+1710: mtCOVERAGE_TEST_MARKER();\r
+1711: }\r
+1712: }\r
+1713: \r
+1714: /* If any ticks occurred while the scheduler was suspended then\r
+1715: they should be processed now. This ensures the tick count does\r
+1716: not slip, and that any delayed tasks are resumed at the correct\r
+1717: time. */\r
+1718: if( uxPendedTicks > ( UBaseType_t ) 0U )\r
+BFD02BF4 8048FC5C LW V0, -32696(GP)
+BFD02BF8 001340E2 BEQZC V0, 0xBFD02C22
+1719: {\r
+1720: while( uxPendedTicks > ( UBaseType_t ) 0U )\r
+BFD02BFC CC0E B 0xBFD02C1A
+BFD02BFE 0C00 NOP
+BFD02C1A 8048FC5C LW V0, -32696(GP)
+BFD02C1E FFEF40A2 BNEZC V0, 0xBFD02C00
+BFD02C20 FC7CFFEF LW RA, -900(T7)
+1721: {\r
+1722: if( xTaskIncrementTick() != pdFALSE )\r
+BFD02C00 104077E8 JALS xTaskIncrementTick
+BFD02C02 0C001040 ADDI V0, ZERO, 3072
+BFD02C04 0C00 NOP
+BFD02C06 000340E2 BEQZC V0, 0xBFD02C10
+1723: {\r
+1724: xYieldPending = pdTRUE;\r
+BFD02C0A ED01 LI V0, 1
+BFD02C0C 804CF85C SW V0, -32692(GP)
+1725: }\r
+1726: else\r
+1727: {\r
+1728: mtCOVERAGE_TEST_MARKER();\r
+1729: }\r
+1730: --uxPendedTicks;\r
+BFD02C10 8048FC5C LW V0, -32696(GP)
+BFD02C14 6D2E ADDIU V0, V0, -1
+BFD02C16 8048F85C SW V0, -32696(GP)
+1731: }\r
+1732: }\r
+1733: else\r
+1734: {\r
+1735: mtCOVERAGE_TEST_MARKER();\r
+1736: }\r
+1737: \r
+1738: if( xYieldPending == pdTRUE )\r
+BFD02C22 804CFC7C LW V1, -32692(GP)
+BFD02C26 ED01 LI V0, 1
+BFD02C28 0014B443 BNE V1, V0, 0xBFD02C54
+BFD02C2A 0C000014 SLL ZERO, S4, 1
+BFD02C2C 0C00 NOP
+1739: {\r
+1740: #if( configUSE_PREEMPTION != 0 )\r
+1741: {\r
+1742: xAlreadyYielded = pdTRUE;\r
+BFD02C2E ED01 LI V0, 1
+BFD02C30 0010F85E SW V0, 16(S8)
+1743: }\r
+1744: #endif\r
+1745: taskYIELD_IF_USING_PREEMPTION();\r
+BFD02C34 4E5677E8 JALS ulPortGetCP0Cause
+BFD02C36 4E56 ADDIU S2, S2, -5
+BFD02C38 0C00 NOP
+BFD02C3A 0018F85E SW V0, 24(S8)
+BFD02C3E 0018FC5E LW V0, 24(S8)
+BFD02C42 01005042 ORI V0, V0, 256
+BFD02C46 0018F85E SW V0, 24(S8)
+BFD02C4A 0018FC9E LW A0, 24(S8)
+BFD02C4E 4E6677E8 JALS vPortSetCP0Cause
+BFD02C50 4E66 ADDIU S3, S3, 3
+BFD02C52 0C00 NOP
+1746: }\r
+1747: else\r
+1748: {\r
+1749: mtCOVERAGE_TEST_MARKER();\r
+1750: }\r
+1751: }\r
+1752: }\r
+1753: else\r
+1754: {\r
+1755: mtCOVERAGE_TEST_MARKER();\r
+1756: }\r
+1757: }\r
+1758: taskEXIT_CRITICAL();\r
+BFD02C54 40AA77E8 JALS vTaskExitCritical
+BFD02C56 0C0040AA BNEZC T2, 0xBFD0445A
+BFD02C58 0C00 NOP
+1759: \r
+1760: return xAlreadyYielded;\r
+BFD02C5A 0010FC5E LW V0, 16(S8)
+1761: }\r
+BFD02C5E 0FBE MOVE SP, S8
+BFD02C60 4BE9 LW RA, 36(SP)
+BFD02C62 4BC8 LW S8, 32(SP)
+BFD02C64 4C15 ADDIU SP, SP, 40
+BFD02C66 459F JR16 RA
+BFD02C68 0C00 NOP
+1762: /*-----------------------------------------------------------*/\r
+1763: \r
+1764: TickType_t xTaskGetTickCount( void )\r
+1765: {\r
+BFD09994 4FF1 ADDIU SP, SP, -32
+BFD09996 CBE7 SW RA, 28(SP)
+BFD09998 CBC6 SW S8, 24(SP)
+BFD0999A 0FDD MOVE S8, SP
+1766: TickType_t xTicks;\r
+1767: \r
+1768: /* Critical section required if running on a 16 bit processor. */\r
+1769: portTICK_TYPE_ENTER_CRITICAL();\r
+BFD0999C 33B877E8 JALS vTaskEnterCritical
+BFD0999E 0C0033B8 ADDIU SP, T8, 3072
+BFD099A0 0C00 NOP
+1770: {\r
+1771: xTicks = xTickCount;\r
+BFD099A2 803CFC5C LW V0, -32708(GP)
+BFD099A6 0010F85E SW V0, 16(S8)
+1772: }\r
+1773: portTICK_TYPE_EXIT_CRITICAL();\r
+BFD099AA 40AA77E8 JALS vTaskExitCritical
+BFD099AC 0C0040AA BNEZC T2, 0xBFD0B1B0
+BFD099AE 0C00 NOP
+1774: \r
+1775: return xTicks;\r
+BFD099B0 0010FC5E LW V0, 16(S8)
+1776: }\r
+BFD099B4 0FBE MOVE SP, S8
+BFD099B6 4BE7 LW RA, 28(SP)
+BFD099B8 4BC6 LW S8, 24(SP)
+BFD099BA 4C11 ADDIU SP, SP, 32
+BFD099BC 459F JR16 RA
+BFD099BE 0C00 NOP
+1777: /*-----------------------------------------------------------*/\r
+1778: \r
+1779: TickType_t xTaskGetTickCountFromISR( void )\r
+1780: {\r
+BFD09844 4FF1 ADDIU SP, SP, -32
+BFD09846 CBE7 SW RA, 28(SP)
+BFD09848 CBC6 SW S8, 24(SP)
+BFD0984A 0FDD MOVE S8, SP
+1781: TickType_t xReturn;\r
+1782: UBaseType_t uxSavedInterruptStatus;\r
+1783: \r
+1784: /* RTOS ports that support interrupt nesting have the concept of a maximum\r
+1785: system call (or maximum API call) interrupt priority. Interrupts that are\r
+1786: above the maximum system call priority are kept permanently enabled, even\r
+1787: when the RTOS kernel is in a critical section, but cannot make any calls to\r
+1788: FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h\r
+1789: then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r
+1790: failure if a FreeRTOS API function is called from an interrupt that has been\r
+1791: assigned a priority above the configured maximum system call priority.\r
+1792: Only FreeRTOS functions that end in FromISR can be called from interrupts\r
+1793: that have been assigned a priority at or (logically) below the maximum\r
+1794: system call interrupt priority. FreeRTOS maintains a separate interrupt\r
+1795: safe API to ensure interrupt entry is as fast and as simple as possible.\r
+1796: More information (albeit Cortex-M specific) is provided on the following\r
+1797: link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r
+1798: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
+1799: \r
+1800: uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();\r
+BFD0984C 475E77E8 JALS uxPortSetInterruptMaskFromISR
+BFD09850 0C00 NOP
+BFD09852 0010F85E SW V0, 16(S8)
+1801: {\r
+1802: xReturn = xTickCount;\r
+BFD09856 803CFC5C LW V0, -32708(GP)
+BFD0985A 0014F85E SW V0, 20(S8)
+1803: }\r
+1804: portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+BFD0985E 0010FC9E LW A0, 16(S8)
+BFD09862 4D5E77E8 JALS vPortClearInterruptMaskFromISR
+BFD09864 4D5E ADDIU T2, T2, -1
+BFD09866 0C00 NOP
+1805: \r
+1806: return xReturn;\r
+BFD09868 0014FC5E LW V0, 20(S8)
+1807: }\r
+BFD0986C 0FBE MOVE SP, S8
+BFD0986E 4BE7 LW RA, 28(SP)
+BFD09870 4BC6 LW S8, 24(SP)
+BFD09872 4C11 ADDIU SP, SP, 32
+BFD09874 459F JR16 RA
+BFD09876 0C00 NOP
+1808: /*-----------------------------------------------------------*/\r
+1809: \r
+1810: UBaseType_t uxTaskGetNumberOfTasks( void )\r
+1811: {\r
+BFD09E98 4FB0 ADDIU SP, SP, -8
+BFD09E9A CBC1 SW S8, 4(SP)
+BFD09E9C 0FDD MOVE S8, SP
+1812: /* A critical section is not required because the variables are of type\r
+1813: BaseType_t. */\r
+1814: return uxCurrentNumberOfTasks;\r
+BFD09E9E 8038FC5C LW V0, -32712(GP)
+1815: }\r
+BFD09EA2 0FBE MOVE SP, S8
+BFD09EA4 4BC1 LW S8, 4(SP)
+BFD09EA6 4C05 ADDIU SP, SP, 8
+BFD09EA8 459F JR16 RA
+BFD09EAA 0C00 NOP
+1816: /*-----------------------------------------------------------*/\r
+1817: \r
+1818: #if ( INCLUDE_pcTaskGetTaskName == 1 )\r
+1819: \r
+1820: char *pcTaskGetTaskName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r
+1821: {\r
+1822: TCB_t *pxTCB;\r
+1823: \r
+1824: /* If null is passed in here then the name of the calling task is being queried. */\r
+1825: pxTCB = prvGetTCBFromHandle( xTaskToQuery );\r
+1826: configASSERT( pxTCB );\r
+1827: return &( pxTCB->pcTaskName[ 0 ] );\r
+1828: }\r
+1829: \r
+1830: #endif /* INCLUDE_pcTaskGetTaskName */\r
+1831: /*-----------------------------------------------------------*/\r
+1832: \r
+1833: #if ( configUSE_TRACE_FACILITY == 1 )\r
+1834: \r
+1835: UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )\r
+1836: {\r
+1837: UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;\r
+1838: \r
+1839: vTaskSuspendAll();\r
+1840: {\r
+1841: /* Is there a space in the array for each task in the system? */\r
+1842: if( uxArraySize >= uxCurrentNumberOfTasks )\r
+1843: {\r
+1844: /* Fill in an TaskStatus_t structure with information on each\r
+1845: task in the Ready state. */\r
+1846: do\r
+1847: {\r
+1848: uxQueue--;\r
+1849: uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );\r
+1850: \r
+1851: } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
+1852: \r
+1853: /* Fill in an TaskStatus_t structure with information on each\r
+1854: task in the Blocked state. */\r
+1855: uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );\r
+1856: uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );\r
+1857: \r
+1858: #if( INCLUDE_vTaskDelete == 1 )\r
+1859: {\r
+1860: /* Fill in an TaskStatus_t structure with information on\r
+1861: each task that has been deleted but not yet cleaned up. */\r
+1862: uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );\r
+1863: }\r
+1864: #endif\r
+1865: \r
+1866: #if ( INCLUDE_vTaskSuspend == 1 )\r
+1867: {\r
+1868: /* Fill in an TaskStatus_t structure with information on\r
+1869: each task in the Suspended state. */\r
+1870: uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );\r
+1871: }\r
+1872: #endif\r
+1873: \r
+1874: #if ( configGENERATE_RUN_TIME_STATS == 1)\r
+1875: {\r
+1876: if( pulTotalRunTime != NULL )\r
+1877: {\r
+1878: #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\r
+1879: portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );\r
+1880: #else\r
+1881: *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();\r
+1882: #endif\r
+1883: }\r
+1884: }\r
+1885: #else\r
+1886: {\r
+1887: if( pulTotalRunTime != NULL )\r
+1888: {\r
+1889: *pulTotalRunTime = 0;\r
+1890: }\r
+1891: }\r
+1892: #endif\r
+1893: }\r
+1894: else\r
+1895: {\r
+1896: mtCOVERAGE_TEST_MARKER();\r
+1897: }\r
+1898: }\r
+1899: ( void ) xTaskResumeAll();\r
+1900: \r
+1901: return uxTask;\r
+1902: }\r
+1903: \r
+1904: #endif /* configUSE_TRACE_FACILITY */\r
+1905: /*----------------------------------------------------------*/\r
+1906: \r
+1907: #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
+1908: \r
+1909: TaskHandle_t xTaskGetIdleTaskHandle( void )\r
+1910: {\r
+1911: /* If xTaskGetIdleTaskHandle() is called before the scheduler has been\r
+1912: started, then xIdleTaskHandle will be NULL. */\r
+1913: configASSERT( ( xIdleTaskHandle != NULL ) );\r
+1914: return xIdleTaskHandle;\r
+1915: }\r
+1916: \r
+1917: #endif /* INCLUDE_xTaskGetIdleTaskHandle */\r
+1918: /*----------------------------------------------------------*/\r
+1919: \r
+1920: /* This conditional compilation should use inequality to 0, not equality to 1.\r
+1921: This is to ensure vTaskStepTick() is available when user defined low power mode\r
+1922: implementations require configUSE_TICKLESS_IDLE to be set to a value other than\r
+1923: 1. */\r
+1924: #if ( configUSE_TICKLESS_IDLE != 0 )\r
+1925: \r
+1926: void vTaskStepTick( const TickType_t xTicksToJump )\r
+1927: {\r
+1928: /* Correct the tick count value after a period during which the tick\r
+1929: was suppressed. Note this does *not* call the tick hook function for\r
+1930: each stepped tick. */\r
+1931: configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );\r
+1932: xTickCount += xTicksToJump;\r
+1933: traceINCREASE_TICK_COUNT( xTicksToJump );\r
+1934: }\r
+1935: \r
+1936: #endif /* configUSE_TICKLESS_IDLE */\r
+1937: /*----------------------------------------------------------*/\r
+1938: \r
+1939: BaseType_t xTaskIncrementTick( void )\r
+1940: {\r
+BFD02080 4FE9 ADDIU SP, SP, -48
+BFD02082 CBEB SW RA, 44(SP)
+BFD02084 CBCA SW S8, 40(SP)
+BFD02086 0FDD MOVE S8, SP
+1941: TCB_t * pxTCB;\r
+1942: TickType_t xItemValue;\r
+1943: BaseType_t xSwitchRequired = pdFALSE;\r
+BFD02088 0010F81E SW ZERO, 16(S8)
+1944: \r
+1945: /* Called by the portable layer each time a tick interrupt occurs.\r
+1946: Increments the tick then checks to see if the new tick value will cause any\r
+1947: tasks to be unblocked. */\r
+1948: traceTASK_INCREMENT_TICK( xTickCount );\r
+1949: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
+BFD0208C 805CFC5C LW V0, -32676(GP)
+BFD02090 00B840A2 BNEZC V0, 0xBFD02204
+1950: {\r
+1951: /* Increment the RTOS tick, switching the delayed and overflowed\r
+1952: delayed lists if it wraps to 0. */\r
+1953: ++xTickCount;\r
+BFD02094 803CFC5C LW V0, -32708(GP)
+BFD02098 6D20 ADDIU V0, V0, 1
+BFD0209A 803CF85C SW V0, -32708(GP)
+1954: \r
+1955: {\r
+1956: /* Minor optimisation. The tick count cannot change in this\r
+1957: block. */\r
+1958: const TickType_t xConstTickCount = xTickCount;\r
+BFD0209E 803CFC5C LW V0, -32708(GP)
+BFD020A2 0014F85E SW V0, 20(S8)
+1959: \r
+1960: if( xConstTickCount == ( TickType_t ) 0U )\r
+BFD020A6 0014FC5E LW V0, 20(S8)
+BFD020AA 002240A2 BNEZC V0, 0xBFD020F2
+1961: {\r
+1962: taskSWITCH_DELAYED_LISTS();\r
+BFD020AE 8074FC5C LW V0, -32652(GP)
+BFD020B2 6920 LW V0, 0(V0)
+BFD020B4 000940E2 BEQZC V0, 0xBFD020CA
+BFD020B8 BFD141A2 LUI V0, 0xBFD1
+BFD020BA 3082BFD1 LDC1 F30, 12418(S1)
+BFD020BC 98103082 ADDIU A0, V0, -26608
+BFD020BE 30A09810 SWC1 F0, 12448(S0)
+BFD020C0 07AA30A0 ADDIU A1, ZERO, 1962
+BFD020C2 07AA ADDU A3, A1, V0
+BFD020C4 4B7E77E8 JALS vAssertCalled
+BFD020C6 4B7E LW K1, 120(SP)
+BFD020C8 0C00 NOP
+BFD020CA 8074FC5C LW V0, -32652(GP)
+BFD020CE 0018F85E SW V0, 24(S8)
+BFD020D2 8078FC5C LW V0, -32648(GP)
+BFD020D6 8074F85C SW V0, -32652(GP)
+BFD020DA 0018FC5E LW V0, 24(S8)
+BFD020DE 8078F85C SW V0, -32648(GP)
+BFD020E2 8050FC5C LW V0, -32688(GP)
+BFD020E6 6D20 ADDIU V0, V0, 1
+BFD020E8 8050F85C SW V0, -32688(GP)
+BFD020EC 47CA77E8 JALS prvResetNextTaskUnblockTime
+BFD020F0 0C00 NOP
+1963: }\r
+1964: else\r
+1965: {\r
+1966: mtCOVERAGE_TEST_MARKER();\r
+1967: }\r
+1968: \r
+1969: /* See if this tick has made a timeout expire. Tasks are stored in\r
+1970: the queue in the order of their wake time - meaning once one task\r
+1971: has been found whose block time has not expired there is no need to\r
+1972: look any further down the list. */\r
+1973: if( xConstTickCount >= xNextTaskUnblockTime )\r
+BFD020F2 8058FC5C LW V0, -32680(GP)
+BFD020F6 0014FC7E LW V1, 20(S8)
+BFD020FA 13900043 SLTU V0, V1, V0
+BFD020FC 40A21390 ADDI GP, S0, 16546
+BFD020FE 006C40A2 BNEZC V0, 0xBFD021DA
+BFD02102 CC02 B 0xBFD02108
+BFD02104 0C00 NOP
+1974: {\r
+1975: for( ;; )\r
+1976: {\r
+1977: if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\r
+BFD02108 8074FC5C LW V0, -32652(GP)
+BFD0210C 6920 LW V0, 0(V0)
+BFD0210E 000340A2 BNEZC V0, 0xBFD02118
+BFD02112 ED01 LI V0, 1
+BFD02114 CC02 B 0xBFD0211A
+BFD02116 0C00 NOP
+BFD02118 0C40 MOVE V0, ZERO
+BFD0211A 000540E2 BEQZC V0, 0xBFD02128
+1978: {\r
+1979: /* The delayed list is empty. Set xNextTaskUnblockTime\r
+1980: to the maximum possible value so it is extremely\r
+1981: unlikely that the\r
+1982: if( xTickCount >= xNextTaskUnblockTime ) test will pass\r
+1983: next time through. */\r
+1984: xNextTaskUnblockTime = portMAX_DELAY;\r
+BFD0211E ED7F LI V0, -1
+BFD02120 8058F85C SW V0, -32680(GP)
+1985: break;\r
+BFD02124 CC5A B 0xBFD021DA
+BFD02126 0C00 NOP
+1986: }\r
+1987: else\r
+1988: {\r
+1989: /* The delayed list is not empty, get the value of the\r
+1990: item at the head of the delayed list. This is the time\r
+1991: at which the task at the head of the delayed list must\r
+1992: be removed from the Blocked state. */\r
+1993: pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );\r
+BFD02128 8074FC5C LW V0, -32652(GP)
+BFD0212C 6923 LW V0, 12(V0)
+BFD0212E 6923 LW V0, 12(V0)
+BFD02130 001CF85E SW V0, 28(S8)
+1994: xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) );\r
+BFD02134 001CFC5E LW V0, 28(S8)
+BFD02138 6921 LW V0, 4(V0)
+BFD0213A 0020F85E SW V0, 32(S8)
+1995: \r
+1996: if( xConstTickCount < xItemValue )\r
+BFD0213E 0014FC7E LW V1, 20(S8)
+BFD02142 0020FC5E LW V0, 32(S8)
+BFD02146 13900043 SLTU V0, V1, V0
+BFD02148 40E21390 ADDI GP, S0, 16610
+BFD0214A 000640E2 BEQZC V0, 0xBFD0215A
+1997: {\r
+1998: /* It is not time to unblock this item yet, but the\r
+1999: item value is the time at which the task at the head\r
+2000: of the blocked list must be removed from the Blocked\r
+2001: state - so record the item value in\r
+2002: xNextTaskUnblockTime. */\r
+2003: xNextTaskUnblockTime = xItemValue;\r
+BFD0214E 0020FC5E LW V0, 32(S8)
+BFD02152 8058F85C SW V0, -32680(GP)
+2004: break;\r
+BFD02156 CC41 B 0xBFD021DA
+BFD02158 0C00 NOP
+2005: }\r
+2006: else\r
+2007: {\r
+2008: mtCOVERAGE_TEST_MARKER();\r
+2009: }\r
+2010: \r
+2011: /* It is time to remove the item from the Blocked state. */\r
+2012: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
+BFD0215A 001CFC5E LW V0, 28(S8)
+BFD0215E 6D22 ADDIU V0, V0, 4
+BFD02160 0C82 MOVE A0, V0
+BFD02162 00C877E8 JALS uxListRemove
+BFD02164 0C0000C8 SLL A2, T0, 1
+BFD02166 0C00 NOP
+2013: \r
+2014: /* Is the task waiting on an event also? If so remove\r
+2015: it from the event list. */\r
+2016: if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\r
+BFD02168 001CFC5E LW V0, 28(S8)
+BFD0216C 692A LW V0, 40(V0)
+BFD0216E 000740E2 BEQZC V0, 0xBFD02180
+2017: {\r
+2018: ( void ) uxListRemove( &( pxTCB->xEventListItem ) );\r
+BFD02172 001CFC5E LW V0, 28(S8)
+BFD02174 6D2C001C EXT ZERO, GP, 20, 14
+BFD02176 6D2C ADDIU V0, V0, 24
+BFD02178 0C82 MOVE A0, V0
+BFD0217A 00C877E8 JALS uxListRemove
+BFD0217C 0C0000C8 SLL A2, T0, 1
+BFD0217E 0C00 NOP
+2019: }\r
+2020: else\r
+2021: {\r
+2022: mtCOVERAGE_TEST_MARKER();\r
+2023: }\r
+2024: \r
+2025: /* Place the unblocked task into the appropriate ready\r
+2026: list. */\r
+2027: prvAddTaskToReadyList( pxTCB );\r
+BFD02180 001CFC5E LW V0, 28(S8)
+BFD02184 692B LW V0, 44(V0)
+BFD02186 ED81 LI V1, 1
+BFD02188 18100062 SLLV V1, V0, V1
+BFD0218A FC5C1810 SB ZERO, -932(S0)
+BFD0218C 8040FC5C LW V0, -32704(GP)
+BFD02190 44D3 OR16 V0, V1
+BFD02192 8040F85C SW V0, -32704(GP)
+BFD02196 001CFC5E LW V0, 28(S8)
+BFD0219A 692B LW V0, 44(V0)
+BFD0219C 2524 SLL V0, V0, 2
+BFD0219E 25A4 SLL V1, V0, 2
+BFD021A0 05B4 ADDU V1, V0, V1
+BFD021A2 BFD241A2 LUI V0, 0xBFD2
+BFD021A4 3042BFD2 LDC1 F30, 12354(S2)
+BFD021A6 806C3042 ADDIU V0, V0, -32660
+BFD021AA 05A6 ADDU V1, V1, V0
+BFD021AC 001CFC5E LW V0, 28(S8)
+BFD021B0 6D22 ADDIU V0, V0, 4
+BFD021B2 0C83 MOVE A0, V1
+BFD021B4 0CA2 MOVE A1, V0
+BFD021B6 3E4A77E8 JALS vListInsertEnd
+BFD021B8 0C003E4A LH S2, 3072(T2)
+BFD021BA 0C00 NOP
+2028: \r
+2029: /* A task being unblocked cannot cause an immediate\r
+2030: context switch if preemption is turned off. */\r
+2031: #if ( configUSE_PREEMPTION == 1 )\r
+2032: {\r
+2033: /* Preemption is on, but a context switch should\r
+2034: only be performed if the unblocked task has a\r
+2035: priority that is equal to or higher than the\r
+2036: currently executing task. */\r
+2037: if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
+BFD021BC 001CFC5E LW V0, 28(S8)
+BFD021C0 69AB LW V1, 44(V0)
+BFD021C2 8030FC5C LW V0, -32720(GP)
+BFD021C6 692B LW V0, 44(V0)
+BFD021C8 13900043 SLTU V0, V1, V0
+BFD021CA 40A21390 ADDI GP, S0, 16546
+BFD021CC FF9B40A2 BNEZC V0, 0xBFD02106
+BFD021CE ED01FF9B LW GP, -4863(K1)
+2038: {\r
+2039: xSwitchRequired = pdTRUE;\r
+BFD021D0 ED01 LI V0, 1
+BFD021D2 0010F85E SW V0, 16(S8)
+2040: }\r
+2041: else\r
+2042: {\r
+2043: mtCOVERAGE_TEST_MARKER();\r
+2044: }\r
+2045: }\r
+2046: #endif /* configUSE_PREEMPTION */\r
+2047: }\r
+2048: }\r
+BFD02106 0C00 NOP
+BFD021D6 CF98 B 0xBFD02108
+BFD021D8 0C00 NOP
+2049: }\r
+2050: }\r
+2051: \r
+2052: /* Tasks of equal priority to the currently running task will share\r
+2053: processing time (time slice) if preemption is on, and the application\r
+2054: writer has not explicitly turned time slicing off. */\r
+2055: #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )\r
+2056: {\r
+2057: if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )\r
+BFD021DA 8030FC5C LW V0, -32720(GP)
+BFD021DE 692B LW V0, 44(V0)
+BFD021E0 2524 SLL V0, V0, 2
+BFD021E2 25A4 SLL V1, V0, 2
+BFD021E4 05B4 ADDU V1, V0, V1
+BFD021E6 BFD241A2 LUI V0, 0xBFD2
+BFD021E8 3042BFD2 LDC1 F30, 12354(S2)
+BFD021EA 806C3042 ADDIU V0, V0, -32660
+BFD021EE 0526 ADDU V0, V1, V0
+BFD021F0 6920 LW V0, 0(V0)
+BFD021F2 0002B042 SLTIU V0, V0, 2
+BFD021F6 000A40A2 BNEZC V0, 0xBFD0220E
+2058: {\r
+2059: xSwitchRequired = pdTRUE;\r
+BFD021FA ED01 LI V0, 1
+BFD021FC 0010F85E SW V0, 16(S8)
+BFD02200 CC06 B 0xBFD0220E
+BFD02202 0C00 NOP
+2060: }\r
+2061: else\r
+2062: {\r
+2063: mtCOVERAGE_TEST_MARKER();\r
+2064: }\r
+2065: }\r
+2066: #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */\r
+2067: \r
+2068: #if ( configUSE_TICK_HOOK == 1 )\r
+2069: {\r
+2070: /* Guard against the tick hook being called when the pended tick\r
+2071: count is being unwound (when the scheduler is being unlocked). */\r
+2072: if( uxPendedTicks == ( UBaseType_t ) 0U )\r
+2073: {\r
+2074: vApplicationTickHook();\r
+2075: }\r
+2076: else\r
+2077: {\r
+2078: mtCOVERAGE_TEST_MARKER();\r
+2079: }\r
+2080: }\r
+2081: #endif /* configUSE_TICK_HOOK */\r
+2082: }\r
+2083: else\r
+2084: {\r
+2085: ++uxPendedTicks;\r
+BFD02204 8048FC5C LW V0, -32696(GP)
+BFD02208 6D20 ADDIU V0, V0, 1
+BFD0220A 8048F85C SW V0, -32696(GP)
+2086: \r
+2087: /* The tick hook gets called at regular intervals, even if the\r
+2088: scheduler is locked. */\r
+2089: #if ( configUSE_TICK_HOOK == 1 )\r
+2090: {\r
+2091: vApplicationTickHook();\r
+2092: }\r
+2093: #endif\r
+2094: }\r
+2095: \r
+2096: #if ( configUSE_PREEMPTION == 1 )\r
+2097: {\r
+2098: if( xYieldPending != pdFALSE )\r
+BFD0220E 804CFC5C LW V0, -32692(GP)
+BFD02212 000340E2 BEQZC V0, 0xBFD0221C
+2099: {\r
+2100: xSwitchRequired = pdTRUE;\r
+BFD02216 ED01 LI V0, 1
+BFD02218 0010F85E SW V0, 16(S8)
+2101: }\r
+2102: else\r
+2103: {\r
+2104: mtCOVERAGE_TEST_MARKER();\r
+2105: }\r
+2106: }\r
+2107: #endif /* configUSE_PREEMPTION */\r
+2108: \r
+2109: return xSwitchRequired;\r
+BFD0221C 0010FC5E LW V0, 16(S8)
+2110: }\r
+BFD02220 0FBE MOVE SP, S8
+BFD02222 4BEB LW RA, 44(SP)
+BFD02224 4BCA LW S8, 40(SP)
+BFD02226 4C19 ADDIU SP, SP, 48
+BFD02228 459F JR16 RA
+BFD0222A 0C00 NOP
+2111: /*-----------------------------------------------------------*/\r
+2112: \r
+2113: #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+2114: \r
+2115: void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )\r
+2116: {\r
+2117: TCB_t *xTCB;\r
+2118: \r
+2119: /* If xTask is NULL then it is the task hook of the calling task that is\r
+2120: getting set. */\r
+2121: if( xTask == NULL )\r
+2122: {\r
+2123: xTCB = ( TCB_t * ) pxCurrentTCB;\r
+2124: }\r
+2125: else\r
+2126: {\r
+2127: xTCB = ( TCB_t * ) xTask;\r
+2128: }\r
+2129: \r
+2130: /* Save the hook function in the TCB. A critical section is required as\r
+2131: the value can be accessed from an interrupt. */\r
+2132: taskENTER_CRITICAL();\r
+2133: xTCB->pxTaskTag = pxHookFunction;\r
+2134: taskEXIT_CRITICAL();\r
+2135: }\r
+2136: \r
+2137: #endif /* configUSE_APPLICATION_TASK_TAG */\r
+2138: /*-----------------------------------------------------------*/\r
+2139: \r
+2140: #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+2141: \r
+2142: TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )\r
+2143: {\r
+2144: TCB_t *xTCB;\r
+2145: TaskHookFunction_t xReturn;\r
+2146: \r
+2147: /* If xTask is NULL then we are setting our own task hook. */\r
+2148: if( xTask == NULL )\r
+2149: {\r
+2150: xTCB = ( TCB_t * ) pxCurrentTCB;\r
+2151: }\r
+2152: else\r
+2153: {\r
+2154: xTCB = ( TCB_t * ) xTask;\r
+2155: }\r
+2156: \r
+2157: /* Save the hook function in the TCB. A critical section is required as\r
+2158: the value can be accessed from an interrupt. */\r
+2159: taskENTER_CRITICAL();\r
+2160: {\r
+2161: xReturn = xTCB->pxTaskTag;\r
+2162: }\r
+2163: taskEXIT_CRITICAL();\r
+2164: \r
+2165: return xReturn;\r
+2166: }\r
+2167: \r
+2168: #endif /* configUSE_APPLICATION_TASK_TAG */\r
+2169: /*-----------------------------------------------------------*/\r
+2170: \r
+2171: #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+2172: \r
+2173: BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )\r
+2174: {\r
+2175: TCB_t *xTCB;\r
+2176: BaseType_t xReturn;\r
+2177: \r
+2178: /* If xTask is NULL then we are calling our own task hook. */\r
+2179: if( xTask == NULL )\r
+2180: {\r
+2181: xTCB = ( TCB_t * ) pxCurrentTCB;\r
+2182: }\r
+2183: else\r
+2184: {\r
+2185: xTCB = ( TCB_t * ) xTask;\r
+2186: }\r
+2187: \r
+2188: if( xTCB->pxTaskTag != NULL )\r
+2189: {\r
+2190: xReturn = xTCB->pxTaskTag( pvParameter );\r
+2191: }\r
+2192: else\r
+2193: {\r
+2194: xReturn = pdFAIL;\r
+2195: }\r
+2196: \r
+2197: return xReturn;\r
+2198: }\r
+2199: \r
+2200: #endif /* configUSE_APPLICATION_TASK_TAG */\r
+2201: /*-----------------------------------------------------------*/\r
+2202: \r
+2203: void vTaskSwitchContext( void )\r
+2204: {\r
+BFD02DBC 4FE5 ADDIU SP, SP, -56
+BFD02DBE CBED SW RA, 52(SP)
+BFD02DC0 CBCC SW S8, 48(SP)
+BFD02DC2 0FDD MOVE S8, SP
+2205: if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )\r
+BFD02DC4 805CFC5C LW V0, -32676(GP)
+BFD02DC8 000540E2 BEQZC V0, 0xBFD02DD6
+2206: {\r
+2207: /* The scheduler is currently suspended - do not allow a context\r
+2208: switch. */\r
+2209: xYieldPending = pdTRUE;\r
+BFD02DCC ED01 LI V0, 1
+BFD02DCE 804CF85C SW V0, -32692(GP)
+BFD02DD2 CC91 B 0xBFD02EF6
+BFD02DD4 0C00 NOP
+2210: }\r
+2211: else\r
+2212: {\r
+2213: xYieldPending = pdFALSE;\r
+BFD02DD6 804CF81C SW ZERO, -32692(GP)
+2214: traceTASK_SWITCHED_OUT();\r
+2215: \r
+2216: #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+2217: {\r
+2218: #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\r
+2219: portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );\r
+2220: #else\r
+2221: ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();\r
+2222: #endif\r
+2223: \r
+2224: /* Add the amount of time the task has been running to the\r
+2225: accumulated time so far. The time the task started running was\r
+2226: stored in ulTaskSwitchedInTime. Note that there is no overflow\r
+2227: protection here so count values are only valid until the timer\r
+2228: overflows. The guard against negative values is to protect\r
+2229: against suspect run time stat counter implementations - which\r
+2230: are provided by the application, not the kernel. */\r
+2231: if( ulTotalRunTime > ulTaskSwitchedInTime )\r
+2232: {\r
+2233: pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );\r
+2234: }\r
+2235: else\r
+2236: {\r
+2237: mtCOVERAGE_TEST_MARKER();\r
+2238: }\r
+2239: ulTaskSwitchedInTime = ulTotalRunTime;\r
+2240: }\r
+2241: #endif /* configGENERATE_RUN_TIME_STATS */\r
+2242: \r
+2243: /* Check for stack overflow, if configured. */\r
+2244: taskFIRST_CHECK_FOR_STACK_OVERFLOW();\r
+BFD02DDA 8030FC5C LW V0, -32720(GP)
+BFD02DDE 69A0 LW V1, 0(V0)
+BFD02DE0 8030FC5C LW V0, -32720(GP)
+BFD02DE4 692C LW V0, 48(V0)
+BFD02DE6 13900062 SLTU V0, V0, V1
+BFD02DE8 40A21390 ADDI GP, S0, 16546
+BFD02DEA 000B40A2 BNEZC V0, 0xBFD02E04
+BFD02DEE 8030FC7C LW V1, -32720(GP)
+BFD02DF2 8030FC5C LW V0, -32720(GP)
+BFD02DF6 00343042 ADDIU V0, V0, 52
+BFD02DFA 0C83 MOVE A0, V1
+BFD02DFC 0CA2 MOVE A1, V0
+BFD02DFE 422277E8 JALS vApplicationStackOverflowHook
+BFD02E00 0C004222 BLTZALS V0, 0xBFD04604
+BFD02E02 0C00 NOP
+2245: taskSECOND_CHECK_FOR_STACK_OVERFLOW();\r
+BFD02E04 BFD141A2 LUI V0, 0xBFD1
+BFD02E06 FCC2BFD1 LDC1 F30, -830(S1)
+BFD02E08 9830FCC2 LW A2, -26576(V0)
+BFD02E0A 30629830 SWC1 F1, 12386(S0)
+BFD02E0C 98303062 ADDIU V1, V0, -26576
+BFD02E0E 6AB19830 SWC1 F1, 27313(S0)
+BFD02E10 6AB1 LW A1, 4(V1)
+BFD02E12 98303062 ADDIU V1, V0, -26576
+BFD02E14 6A329830 SWC1 F1, 27186(S0)
+BFD02E16 6A32 LW A0, 8(V1)
+BFD02E18 98303062 ADDIU V1, V0, -26576
+BFD02E1A 69B39830 SWC1 F1, 27059(S0)
+BFD02E1C 69B3 LW V1, 12(V1)
+BFD02E1E 98303042 ADDIU V0, V0, -26576
+BFD02E20 69249830 SWC1 F1, 26916(S0)
+BFD02E22 6924 LW V0, 16(V0)
+BFD02E24 0018F8DE SW A2, 24(S8)
+BFD02E28 001CF8BE SW A1, 28(S8)
+BFD02E2C 0020F89E SW A0, 32(S8)
+BFD02E30 0024F87E SW V1, 36(S8)
+BFD02E34 0028F85E SW V0, 40(S8)
+BFD02E38 8030FC5C LW V0, -32720(GP)
+BFD02E3C 69AC LW V1, 48(V0)
+BFD02E3E 0018305E ADDIU V0, S8, 24
+BFD02E42 0C83 MOVE A0, V1
+BFD02E44 0CA2 MOVE A1, V0
+BFD02E46 EF14 LI A2, 20
+BFD02E48 3DA677E8 JALS 0xBFD07B4C
+BFD02E4A 0C003DA6 LH T5, 3072(A2)
+BFD02E4C 0C00 NOP
+BFD02E4E 000B40E2 BEQZC V0, 0xBFD02E68
+BFD02E52 8030FC7C LW V1, -32720(GP)
+BFD02E56 8030FC5C LW V0, -32720(GP)
+BFD02E5A 00343042 ADDIU V0, V0, 52
+BFD02E5E 0C83 MOVE A0, V1
+BFD02E60 0CA2 MOVE A1, V0
+BFD02E62 422277E8 JALS vApplicationStackOverflowHook
+BFD02E64 0C004222 BLTZALS V0, 0xBFD04668
+BFD02E66 0C00 NOP
+2246: \r
+2247: /* Select a new task to run using either the generic C or port\r
+2248: optimised asm code. */\r
+2249: taskSELECT_HIGHEST_PRIORITY_TASK();\r
+BFD02E68 8040FC5C LW V0, -32704(GP)
+BFD02E6C 5B3C0042 CLZ V0, V0
+BFD02E70 ED9F LI V1, 31
+BFD02E72 0527 SUBU V0, V1, V0
+BFD02E74 0010F85E SW V0, 16(S8)
+BFD02E78 0010FC5E LW V0, 16(S8)
+BFD02E7C 2524 SLL V0, V0, 2
+BFD02E7E 25A4 SLL V1, V0, 2
+BFD02E80 05B4 ADDU V1, V0, V1
+BFD02E82 BFD241A2 LUI V0, 0xBFD2
+BFD02E84 3042BFD2 LDC1 F30, 12354(S2)
+BFD02E86 806C3042 ADDIU V0, V0, -32660
+BFD02E8A 0526 ADDU V0, V1, V0
+BFD02E8C 6920 LW V0, 0(V0)
+BFD02E8E 000940A2 BNEZC V0, 0xBFD02EA4
+BFD02E92 BFD141A2 LUI V0, 0xBFD1
+BFD02E94 3082BFD1 LDC1 F30, 12418(S1)
+BFD02E96 98103082 ADDIU A0, V0, -26608
+BFD02E98 30A09810 SWC1 F0, 12448(S0)
+BFD02E9A 08C930A0 ADDIU A1, ZERO, 2249
+BFD02E9C 08C9 LBU S1, 9(A0)
+BFD02E9E 4B7E77E8 JALS vAssertCalled
+BFD02EA0 4B7E LW K1, 120(SP)
+BFD02EA2 0C00 NOP
+BFD02EA4 0010FC5E LW V0, 16(S8)
+BFD02EA8 2524 SLL V0, V0, 2
+BFD02EAA 25A4 SLL V1, V0, 2
+BFD02EAC 05B4 ADDU V1, V0, V1
+BFD02EAE BFD241A2 LUI V0, 0xBFD2
+BFD02EB0 3042BFD2 LDC1 F30, 12354(S2)
+BFD02EB2 806C3042 ADDIU V0, V0, -32660
+BFD02EB6 0526 ADDU V0, V1, V0
+BFD02EB8 0014F85E SW V0, 20(S8)
+BFD02EBC 0014FC5E LW V0, 20(S8)
+BFD02EC0 6921 LW V0, 4(V0)
+BFD02EC2 69A1 LW V1, 4(V0)
+BFD02EC4 0014FC5E LW V0, 20(S8)
+BFD02EC8 E9A1 SW V1, 4(V0)
+BFD02ECA 0014FC5E LW V0, 20(S8)
+BFD02ECE 69A1 LW V1, 4(V0)
+BFD02ED0 0014FC5E LW V0, 20(S8)
+BFD02ED4 6D24 ADDIU V0, V0, 8
+BFD02ED6 0008B443 BNE V1, V0, 0xBFD02EEA
+BFD02ED8 0C000008 SLL ZERO, T0, 1
+BFD02EDA 0C00 NOP
+BFD02EDC 0014FC5E LW V0, 20(S8)
+BFD02EE0 6921 LW V0, 4(V0)
+BFD02EE2 69A1 LW V1, 4(V0)
+BFD02EE4 0014FC5E LW V0, 20(S8)
+BFD02EE8 E9A1 SW V1, 4(V0)
+BFD02EEA 0014FC5E LW V0, 20(S8)
+BFD02EEE 6921 LW V0, 4(V0)
+BFD02EF0 6923 LW V0, 12(V0)
+BFD02EF2 8030F85C SW V0, -32720(GP)
+2250: traceTASK_SWITCHED_IN();\r
+2251: \r
+2252: #if ( configUSE_NEWLIB_REENTRANT == 1 )\r
+2253: {\r
+2254: /* Switch Newlib's _impure_ptr variable to point to the _reent\r
+2255: structure specific to this task. */\r
+2256: _impure_ptr = &( pxCurrentTCB->xNewLib_reent );\r
+2257: }\r
+2258: #endif /* configUSE_NEWLIB_REENTRANT */\r
+2259: }\r
+2260: }\r
+BFD02EF6 0FBE MOVE SP, S8
+BFD02EF8 4BED LW RA, 52(SP)
+BFD02EFA 4BCC LW S8, 48(SP)
+BFD02EFC 4C1D ADDIU SP, SP, 56
+BFD02EFE 459F JR16 RA
+BFD02F00 0C00 NOP
+2261: /*-----------------------------------------------------------*/\r
+2262: \r
+2263: void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )\r
+2264: {\r
+BFD05E74 4FF1 ADDIU SP, SP, -32
+BFD05E76 CBE7 SW RA, 28(SP)
+BFD05E78 CBC6 SW S8, 24(SP)
+BFD05E7A 0FDD MOVE S8, SP
+BFD05E7C 0020F89E SW A0, 32(S8)
+BFD05E80 0024F8BE SW A1, 36(S8)
+2265: TickType_t xTimeToWake;\r
+2266: \r
+2267: configASSERT( pxEventList );\r
+BFD05E84 0020FC5E LW V0, 32(S8)
+BFD05E88 000940A2 BNEZC V0, 0xBFD05E9E
+BFD05E8C BFD141A2 LUI V0, 0xBFD1
+BFD05E8E 3082BFD1 LDC1 F30, 12418(S1)
+BFD05E90 98103082 ADDIU A0, V0, -26608
+BFD05E92 30A09810 SWC1 F0, 12448(S0)
+BFD05E94 08DB30A0 ADDIU A1, ZERO, 2267
+BFD05E96 08DB LBU S1, 11(A1)
+BFD05E98 4B7E77E8 JALS vAssertCalled
+BFD05E9A 4B7E LW K1, 120(SP)
+BFD05E9C 0C00 NOP
+2268: \r
+2269: /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE\r
+2270: SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */\r
+2271: \r
+2272: /* Place the event list item of the TCB in the appropriate event list.\r
+2273: This is placed in the list in priority order so the highest priority task\r
+2274: is the first to be woken by the event. The queue that contains the event\r
+2275: list is locked, preventing simultaneous access from interrupts. */\r
+2276: vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );\r
+BFD05E9E 8030FC5C LW V0, -32720(GP)
+BFD05EA2 6D2C ADDIU V0, V0, 24
+BFD05EA4 0020FC9E LW A0, 32(S8)
+BFD05EA8 0CA2 MOVE A1, V0
+BFD05EAA 304077E8 JALS vListInsert
+BFD05EAC 0C003040 ADDIU V0, ZERO, 3072
+BFD05EAE 0C00 NOP
+2277: \r
+2278: /* The task must be removed from from the ready list before it is added to\r
+2279: the blocked list as the same list item is used for both lists. Exclusive\r
+2280: access to the ready lists guaranteed because the scheduler is locked. */\r
+2281: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
+BFD05EB0 8030FC5C LW V0, -32720(GP)
+BFD05EB4 6D22 ADDIU V0, V0, 4
+BFD05EB6 0C82 MOVE A0, V0
+BFD05EB8 00C877E8 JALS uxListRemove
+BFD05EBA 0C0000C8 SLL A2, T0, 1
+BFD05EBC 0C00 NOP
+BFD05EBE 000C40A2 BNEZC V0, 0xBFD05EDA
+2282: {\r
+2283: /* The current task must be in a ready list, so there is no need to\r
+2284: check, and the port reset macro can be called directly. */\r
+2285: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
+BFD05EC2 8030FC5C LW V0, -32720(GP)
+BFD05EC6 692B LW V0, 44(V0)
+BFD05EC8 ED81 LI V1, 1
+BFD05ECA 10100062 SLLV V0, V0, V1
+BFD05ECC 441A1010 ADDI ZERO, S0, 17434
+BFD05ECE 441A NOT16 V1, V0
+BFD05ED0 8040FC5C LW V0, -32704(GP)
+BFD05ED4 4493 AND16 V0, V1
+BFD05ED6 8040F85C SW V0, -32704(GP)
+2286: }\r
+2287: else\r
+2288: {\r
+2289: mtCOVERAGE_TEST_MARKER();\r
+2290: }\r
+2291: \r
+2292: #if ( INCLUDE_vTaskSuspend == 1 )\r
+2293: {\r
+2294: if( xTicksToWait == portMAX_DELAY )\r
+BFD05EDA 0024FC7E LW V1, 36(S8)
+BFD05EDE ED7F LI V0, -1
+BFD05EE0 000EB443 BNE V1, V0, 0xBFD05F00
+BFD05EE2 0C00000E SLL ZERO, T6, 1
+BFD05EE4 0C00 NOP
+2295: {\r
+2296: /* Add the task to the suspended task list instead of a delayed task\r
+2297: list to ensure the task is not woken by a timing event. It will\r
+2298: block indefinitely. */\r
+2299: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
+BFD05EE6 8030FC5C LW V0, -32720(GP)
+BFD05EEA 6D22 ADDIU V0, V0, 4
+BFD05EEC BFD241A3 LUI V1, 0xBFD2
+BFD05EEE 3083BFD2 LDC1 F30, 12419(S2)
+BFD05EF0 80E43083 ADDIU A0, V1, -32540
+BFD05EF4 0CA2 MOVE A1, V0
+BFD05EF6 3E4A77E8 JALS vListInsertEnd
+BFD05EF8 0C003E4A LH S2, 3072(T2)
+BFD05EFA 0C00 NOP
+BFD05EFC CC0D B 0xBFD05F18
+BFD05EFE 0C00 NOP
+2300: }\r
+2301: else\r
+2302: {\r
+2303: /* Calculate the time at which the task should be woken if the event\r
+2304: does not occur. This may overflow but this doesn't matter, the\r
+2305: scheduler will handle it. */\r
+2306: xTimeToWake = xTickCount + xTicksToWait;\r
+BFD05F00 803CFC7C LW V1, -32708(GP)
+BFD05F04 0024FC5E LW V0, 36(S8)
+BFD05F08 0526 ADDU V0, V1, V0
+BFD05F0A 0010F85E SW V0, 16(S8)
+2307: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+BFD05F0E 0010FC9E LW A0, 16(S8)
+BFD05F12 373477E8 JALS prvAddCurrentTaskToDelayedList
+BFD05F14 0C003734 LHU T9, 3072(S4)
+BFD05F16 0C00 NOP
+2308: }\r
+2309: }\r
+2310: #else /* INCLUDE_vTaskSuspend */\r
+2311: {\r
+2312: /* Calculate the time at which the task should be woken if the event does\r
+2313: not occur. This may overflow but this doesn't matter, the scheduler\r
+2314: will handle it. */\r
+2315: xTimeToWake = xTickCount + xTicksToWait;\r
+2316: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+2317: }\r
+2318: #endif /* INCLUDE_vTaskSuspend */\r
+2319: }\r
+BFD05F18 0FBE MOVE SP, S8
+BFD05F1A 4BE7 LW RA, 28(SP)
+BFD05F1C 4BC6 LW S8, 24(SP)
+BFD05F1E 4C11 ADDIU SP, SP, 32
+BFD05F20 459F JR16 RA
+BFD05F22 0C00 NOP
+2320: /*-----------------------------------------------------------*/\r
+2321: \r
+2322: void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )\r
+2323: {\r
+BFD04904 4FF1 ADDIU SP, SP, -32
+BFD04906 CBE7 SW RA, 28(SP)
+BFD04908 CBC6 SW S8, 24(SP)
+BFD0490A 0FDD MOVE S8, SP
+BFD0490C 0020F89E SW A0, 32(S8)
+BFD04910 0024F8BE SW A1, 36(S8)
+BFD04914 0028F8DE SW A2, 40(S8)
+2324: TickType_t xTimeToWake;\r
+2325: \r
+2326: configASSERT( pxEventList );\r
+BFD04918 0020FC5E LW V0, 32(S8)
+BFD0491C 000940A2 BNEZC V0, 0xBFD04932
+BFD04920 BFD141A2 LUI V0, 0xBFD1
+BFD04922 3082BFD1 LDC1 F30, 12418(S1)
+BFD04924 98103082 ADDIU A0, V0, -26608
+BFD04926 30A09810 SWC1 F0, 12448(S0)
+BFD04928 091630A0 ADDIU A1, ZERO, 2326
+BFD0492A 0916 LBU V0, 6(S1)
+BFD0492C 4B7E77E8 JALS vAssertCalled
+BFD0492E 4B7E LW K1, 120(SP)
+BFD04930 0C00 NOP
+2327: \r
+2328: /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by\r
+2329: the event groups implementation. */\r
+2330: configASSERT( uxSchedulerSuspended != 0 );\r
+BFD04932 805CFC5C LW V0, -32676(GP)
+BFD04936 000940A2 BNEZC V0, 0xBFD0494C
+BFD0493A BFD141A2 LUI V0, 0xBFD1
+BFD0493C 3082BFD1 LDC1 F30, 12418(S1)
+BFD0493E 98103082 ADDIU A0, V0, -26608
+BFD04940 30A09810 SWC1 F0, 12448(S0)
+BFD04942 091A30A0 ADDIU A1, ZERO, 2330
+BFD04944 091A LBU V0, 10(S1)
+BFD04946 4B7E77E8 JALS vAssertCalled
+BFD04948 4B7E LW K1, 120(SP)
+BFD0494A 0C00 NOP
+2331: \r
+2332: /* Store the item value in the event list item. It is safe to access the\r
+2333: event list item here as interrupts won't access the event list item of a\r
+2334: task that is not in the Blocked state. */\r
+2335: listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );\r
+BFD0494C 8030FC5C LW V0, -32720(GP)
+BFD04950 0024FC9E LW A0, 36(S8)
+BFD04954 800041A3 LUI V1, 0x8000
+BFD04958 44DC OR16 V1, A0
+BFD0495A E9A6 SW V1, 24(V0)
+2336: \r
+2337: /* Place the event list item of the TCB at the end of the appropriate event\r
+2338: list. It is safe to access the event list here because it is part of an\r
+2339: event group implementation - and interrupts don't access event groups\r
+2340: directly (instead they access them indirectly by pending function calls to\r
+2341: the task level). */\r
+2342: vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );\r
+BFD0495C 8030FC5C LW V0, -32720(GP)
+BFD04960 6D2C ADDIU V0, V0, 24
+BFD04962 0020FC9E LW A0, 32(S8)
+BFD04966 0CA2 MOVE A1, V0
+BFD04968 3E4A77E8 JALS vListInsertEnd
+BFD0496A 0C003E4A LH S2, 3072(T2)
+BFD0496C 0C00 NOP
+2343: \r
+2344: /* The task must be removed from the ready list before it is added to the\r
+2345: blocked list. Exclusive access can be assured to the ready list as the\r
+2346: scheduler is locked. */\r
+2347: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
+BFD0496E 8030FC5C LW V0, -32720(GP)
+BFD04972 6D22 ADDIU V0, V0, 4
+BFD04974 0C82 MOVE A0, V0
+BFD04976 00C877E8 JALS uxListRemove
+BFD04978 0C0000C8 SLL A2, T0, 1
+BFD0497A 0C00 NOP
+BFD0497C 000C40A2 BNEZC V0, 0xBFD04998
+2348: {\r
+2349: /* The current task must be in a ready list, so there is no need to\r
+2350: check, and the port reset macro can be called directly. */\r
+2351: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
+BFD04980 8030FC5C LW V0, -32720(GP)
+BFD04984 692B LW V0, 44(V0)
+BFD04986 ED81 LI V1, 1
+BFD04988 10100062 SLLV V0, V0, V1
+BFD0498A 441A1010 ADDI ZERO, S0, 17434
+BFD0498C 441A NOT16 V1, V0
+BFD0498E 8040FC5C LW V0, -32704(GP)
+BFD04992 4493 AND16 V0, V1
+BFD04994 8040F85C SW V0, -32704(GP)
+2352: }\r
+2353: else\r
+2354: {\r
+2355: mtCOVERAGE_TEST_MARKER();\r
+2356: }\r
+2357: \r
+2358: #if ( INCLUDE_vTaskSuspend == 1 )\r
+2359: {\r
+2360: if( xTicksToWait == portMAX_DELAY )\r
+BFD04998 0028FC7E LW V1, 40(S8)
+BFD0499C ED7F LI V0, -1
+BFD0499E 000EB443 BNE V1, V0, 0xBFD049BE
+BFD049A0 0C00000E SLL ZERO, T6, 1
+BFD049A2 0C00 NOP
+2361: {\r
+2362: /* Add the task to the suspended task list instead of a delayed task\r
+2363: list to ensure it is not woken by a timing event. It will block\r
+2364: indefinitely. */\r
+2365: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
+BFD049A4 8030FC5C LW V0, -32720(GP)
+BFD049A8 6D22 ADDIU V0, V0, 4
+BFD049AA BFD241A3 LUI V1, 0xBFD2
+BFD049AC 3083BFD2 LDC1 F30, 12419(S2)
+BFD049AE 80E43083 ADDIU A0, V1, -32540
+BFD049B2 0CA2 MOVE A1, V0
+BFD049B4 3E4A77E8 JALS vListInsertEnd
+BFD049B6 0C003E4A LH S2, 3072(T2)
+BFD049B8 0C00 NOP
+BFD049BA CC0D B 0xBFD049D6
+BFD049BC 0C00 NOP
+2366: }\r
+2367: else\r
+2368: {\r
+2369: /* Calculate the time at which the task should be woken if the event\r
+2370: does not occur. This may overflow but this doesn't matter, the\r
+2371: kernel will manage it correctly. */\r
+2372: xTimeToWake = xTickCount + xTicksToWait;\r
+BFD049BE 803CFC7C LW V1, -32708(GP)
+BFD049C2 0028FC5E LW V0, 40(S8)
+BFD049C6 0526 ADDU V0, V1, V0
+BFD049C8 0010F85E SW V0, 16(S8)
+2373: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+BFD049CC 0010FC9E LW A0, 16(S8)
+BFD049D0 373477E8 JALS prvAddCurrentTaskToDelayedList
+BFD049D2 0C003734 LHU T9, 3072(S4)
+BFD049D4 0C00 NOP
+2374: }\r
+2375: }\r
+2376: #else /* INCLUDE_vTaskSuspend */\r
+2377: {\r
+2378: /* Calculate the time at which the task should be woken if the event does\r
+2379: not occur. This may overflow but this doesn't matter, the kernel\r
+2380: will manage it correctly. */\r
+2381: xTimeToWake = xTickCount + xTicksToWait;\r
+2382: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+2383: }\r
+2384: #endif /* INCLUDE_vTaskSuspend */\r
+2385: }\r
+BFD049D6 0FBE MOVE SP, S8
+BFD049D8 4BE7 LW RA, 28(SP)
+BFD049DA 4BC6 LW S8, 24(SP)
+BFD049DC 4C11 ADDIU SP, SP, 32
+BFD049DE 459F JR16 RA
+BFD049E0 0C00 NOP
+2386: /*-----------------------------------------------------------*/\r
+2387: \r
+2388: #if configUSE_TIMERS == 1\r
+2389: \r
+2390: void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, const TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )\r
+2391: {\r
+BFD05C58 4FF1 ADDIU SP, SP, -32
+BFD05C5A CBE7 SW RA, 28(SP)
+BFD05C5C CBC6 SW S8, 24(SP)
+BFD05C5E 0FDD MOVE S8, SP
+BFD05C60 0020F89E SW A0, 32(S8)
+BFD05C64 0024F8BE SW A1, 36(S8)
+BFD05C68 0028F8DE SW A2, 40(S8)
+2392: TickType_t xTimeToWake;\r
+2393: \r
+2394: configASSERT( pxEventList );\r
+BFD05C6C 0020FC5E LW V0, 32(S8)
+BFD05C70 000940A2 BNEZC V0, 0xBFD05C86
+BFD05C74 BFD141A2 LUI V0, 0xBFD1
+BFD05C76 3082BFD1 LDC1 F30, 12418(S1)
+BFD05C78 98103082 ADDIU A0, V0, -26608
+BFD05C7A 30A09810 SWC1 F0, 12448(S0)
+BFD05C7C 095A30A0 ADDIU A1, ZERO, 2394
+BFD05C7E 095A LBU V0, 10(A1)
+BFD05C80 4B7E77E8 JALS vAssertCalled
+BFD05C82 4B7E LW K1, 120(SP)
+BFD05C84 0C00 NOP
+2395: \r
+2396: /* This function should not be called by application code hence the\r
+2397: 'Restricted' in its name. It is not part of the public API. It is\r
+2398: designed for use by kernel code, and has special calling requirements -\r
+2399: it should be called with the scheduler suspended. */\r
+2400: \r
+2401: \r
+2402: /* Place the event list item of the TCB in the appropriate event list.\r
+2403: In this case it is assume that this is the only task that is going to\r
+2404: be waiting on this event list, so the faster vListInsertEnd() function\r
+2405: can be used in place of vListInsert. */\r
+2406: vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );\r
+BFD05C86 8030FC5C LW V0, -32720(GP)
+BFD05C8A 6D2C ADDIU V0, V0, 24
+BFD05C8C 0020FC9E LW A0, 32(S8)
+BFD05C90 0CA2 MOVE A1, V0
+BFD05C92 3E4A77E8 JALS vListInsertEnd
+BFD05C94 0C003E4A LH S2, 3072(T2)
+BFD05C96 0C00 NOP
+2407: \r
+2408: /* We must remove this task from the ready list before adding it to the\r
+2409: blocked list as the same list item is used for both lists. This\r
+2410: function is called with the scheduler locked so interrupts will not\r
+2411: access the lists at the same time. */\r
+2412: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
+BFD05C98 8030FC5C LW V0, -32720(GP)
+BFD05C9C 6D22 ADDIU V0, V0, 4
+BFD05C9E 0C82 MOVE A0, V0
+BFD05CA0 00C877E8 JALS uxListRemove
+BFD05CA2 0C0000C8 SLL A2, T0, 1
+BFD05CA4 0C00 NOP
+BFD05CA6 000C40A2 BNEZC V0, 0xBFD05CC2
+2413: {\r
+2414: /* The current task must be in a ready list, so there is no need to\r
+2415: check, and the port reset macro can be called directly. */\r
+2416: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
+BFD05CAA 8030FC5C LW V0, -32720(GP)
+BFD05CAE 692B LW V0, 44(V0)
+BFD05CB0 ED81 LI V1, 1
+BFD05CB2 10100062 SLLV V0, V0, V1
+BFD05CB4 441A1010 ADDI ZERO, S0, 17434
+BFD05CB6 441A NOT16 V1, V0
+BFD05CB8 8040FC5C LW V0, -32704(GP)
+BFD05CBC 4493 AND16 V0, V1
+BFD05CBE 8040F85C SW V0, -32704(GP)
+2417: }\r
+2418: else\r
+2419: {\r
+2420: mtCOVERAGE_TEST_MARKER();\r
+2421: }\r
+2422: \r
+2423: /* If vTaskSuspend() is available then the suspended task list is also\r
+2424: available and a task that is blocking indefinitely can enter the\r
+2425: suspended state (it is not really suspended as it will re-enter the\r
+2426: Ready state when the event it is waiting indefinitely for occurs).\r
+2427: Blocking indefinitely is useful when using tickless idle mode as when\r
+2428: all tasks are blocked indefinitely all timers can be turned off. */\r
+2429: #if( INCLUDE_vTaskSuspend == 1 )\r
+2430: {\r
+2431: if( xWaitIndefinitely == pdTRUE )\r
+BFD05CC2 0028FC7E LW V1, 40(S8)
+BFD05CC6 ED01 LI V0, 1
+BFD05CC8 000EB443 BNE V1, V0, 0xBFD05CE8
+BFD05CCA 0C00000E SLL ZERO, T6, 1
+BFD05CCC 0C00 NOP
+2432: {\r
+2433: /* Add the task to the suspended task list instead of a delayed\r
+2434: task list to ensure the task is not woken by a timing event. It\r
+2435: will block indefinitely. */\r
+2436: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
+BFD05CCE 8030FC5C LW V0, -32720(GP)
+BFD05CD2 6D22 ADDIU V0, V0, 4
+BFD05CD4 BFD241A3 LUI V1, 0xBFD2
+BFD05CD6 3083BFD2 LDC1 F30, 12419(S2)
+BFD05CD8 80E43083 ADDIU A0, V1, -32540
+BFD05CDC 0CA2 MOVE A1, V0
+BFD05CDE 3E4A77E8 JALS vListInsertEnd
+BFD05CE0 0C003E4A LH S2, 3072(T2)
+BFD05CE2 0C00 NOP
+BFD05CE4 CC0D B 0xBFD05D00
+BFD05CE6 0C00 NOP
+2437: }\r
+2438: else\r
+2439: {\r
+2440: /* Calculate the time at which the task should be woken if the\r
+2441: event does not occur. This may overflow but this doesn't\r
+2442: matter. */\r
+2443: xTimeToWake = xTickCount + xTicksToWait;\r
+BFD05CE8 803CFC7C LW V1, -32708(GP)
+BFD05CEC 0024FC5E LW V0, 36(S8)
+BFD05CF0 0526 ADDU V0, V1, V0
+BFD05CF2 0010F85E SW V0, 16(S8)
+2444: traceTASK_DELAY_UNTIL();\r
+2445: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+BFD05CF6 0010FC9E LW A0, 16(S8)
+BFD05CFA 373477E8 JALS prvAddCurrentTaskToDelayedList
+BFD05CFC 0C003734 LHU T9, 3072(S4)
+BFD05CFE 0C00 NOP
+2446: }\r
+2447: }\r
+2448: #else\r
+2449: {\r
+2450: /* Calculate the time at which the task should be woken if the event\r
+2451: does not occur. This may overflow but this doesn't matter. */\r
+2452: xTimeToWake = xTickCount + xTicksToWait;\r
+2453: traceTASK_DELAY_UNTIL();\r
+2454: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+2455: \r
+2456: /* Remove compiler warnings when INCLUDE_vTaskSuspend() is not\r
+2457: defined. */\r
+2458: ( void ) xWaitIndefinitely;\r
+2459: }\r
+2460: #endif\r
+2461: }\r
+BFD05D00 0FBE MOVE SP, S8
+BFD05D02 4BE7 LW RA, 28(SP)
+BFD05D04 4BC6 LW S8, 24(SP)
+BFD05D06 4C11 ADDIU SP, SP, 32
+BFD05D08 459F JR16 RA
+BFD05D0A 0C00 NOP
+2462: \r
+2463: #endif /* configUSE_TIMERS */\r
+2464: /*-----------------------------------------------------------*/\r
+2465: \r
+2466: BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )\r
+2467: {\r
+BFD04578 4FF1 ADDIU SP, SP, -32
+BFD0457A CBE7 SW RA, 28(SP)
+BFD0457C CBC6 SW S8, 24(SP)
+BFD0457E 0FDD MOVE S8, SP
+BFD04580 0020F89E SW A0, 32(S8)
+2468: TCB_t *pxUnblockedTCB;\r
+2469: BaseType_t xReturn;\r
+2470: \r
+2471: /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION. It can also be\r
+2472: called from a critical section within an ISR. */\r
+2473: \r
+2474: /* The event list is sorted in priority order, so the first in the list can\r
+2475: be removed as it is known to be the highest priority. Remove the TCB from\r
+2476: the delayed list, and add it to the ready list.\r
+2477: \r
+2478: If an event is for a queue that is locked then this function will never\r
+2479: get called - the lock count on the queue will get modified instead. This\r
+2480: means exclusive access to the event list is guaranteed here.\r
+2481: \r
+2482: This function assumes that a check has already been made to ensure that\r
+2483: pxEventList is not empty. */\r
+2484: pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );\r
+BFD04584 0020FC5E LW V0, 32(S8)
+BFD04588 6923 LW V0, 12(V0)
+BFD0458A 6923 LW V0, 12(V0)
+BFD0458C 0014F85E SW V0, 20(S8)
+2485: configASSERT( pxUnblockedTCB );\r
+BFD04590 0014FC5E LW V0, 20(S8)
+BFD04594 000940A2 BNEZC V0, 0xBFD045AA
+BFD04598 BFD141A2 LUI V0, 0xBFD1
+BFD0459A 3082BFD1 LDC1 F30, 12418(S1)
+BFD0459C 98103082 ADDIU A0, V0, -26608
+BFD0459E 30A09810 SWC1 F0, 12448(S0)
+BFD045A0 09B530A0 ADDIU A1, ZERO, 2485
+BFD045A2 09B5 LBU V1, 5(V1)
+BFD045A4 4B7E77E8 JALS vAssertCalled
+BFD045A6 4B7E LW K1, 120(SP)
+BFD045A8 0C00 NOP
+2486: ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );\r
+BFD045AA 0014FC5E LW V0, 20(S8)
+BFD045AC 6D2C0014 EXT ZERO, S4, 20, 14
+BFD045AE 6D2C ADDIU V0, V0, 24
+BFD045B0 0C82 MOVE A0, V0
+BFD045B2 00C877E8 JALS uxListRemove
+BFD045B4 0C0000C8 SLL A2, T0, 1
+BFD045B6 0C00 NOP
+2487: \r
+2488: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
+BFD045B8 805CFC5C LW V0, -32676(GP)
+BFD045BC 002740A2 BNEZC V0, 0xBFD0460E
+2489: {\r
+2490: ( void ) uxListRemove( &( pxUnblockedTCB->xGenericListItem ) );\r
+BFD045C0 0014FC5E LW V0, 20(S8)
+BFD045C4 6D22 ADDIU V0, V0, 4
+BFD045C6 0C82 MOVE A0, V0
+BFD045C8 00C877E8 JALS uxListRemove
+BFD045CA 0C0000C8 SLL A2, T0, 1
+BFD045CC 0C00 NOP
+2491: prvAddTaskToReadyList( pxUnblockedTCB );\r
+BFD045CE 0014FC5E LW V0, 20(S8)
+BFD045D2 692B LW V0, 44(V0)
+BFD045D4 ED81 LI V1, 1
+BFD045D6 18100062 SLLV V1, V0, V1
+BFD045D8 FC5C1810 SB ZERO, -932(S0)
+BFD045DA 8040FC5C LW V0, -32704(GP)
+BFD045DE 44D3 OR16 V0, V1
+BFD045E0 8040F85C SW V0, -32704(GP)
+BFD045E4 0014FC5E LW V0, 20(S8)
+BFD045E8 692B LW V0, 44(V0)
+BFD045EA 2524 SLL V0, V0, 2
+BFD045EC 25A4 SLL V1, V0, 2
+BFD045EE 05B4 ADDU V1, V0, V1
+BFD045F0 BFD241A2 LUI V0, 0xBFD2
+BFD045F2 3042BFD2 LDC1 F30, 12354(S2)
+BFD045F4 806C3042 ADDIU V0, V0, -32660
+BFD045F8 05A6 ADDU V1, V1, V0
+BFD045FA 0014FC5E LW V0, 20(S8)
+BFD045FE 6D22 ADDIU V0, V0, 4
+BFD04600 0C83 MOVE A0, V1
+BFD04602 0CA2 MOVE A1, V0
+BFD04604 3E4A77E8 JALS vListInsertEnd
+BFD04606 0C003E4A LH S2, 3072(T2)
+BFD04608 0C00 NOP
+BFD0460A CC0C B 0xBFD04624
+BFD0460C 0C00 NOP
+2492: }\r
+2493: else\r
+2494: {\r
+2495: /* The delayed and ready lists cannot be accessed, so hold this task\r
+2496: pending until the scheduler is resumed. */\r
+2497: vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );\r
+BFD0460E 0014FC5E LW V0, 20(S8)
+BFD04610 6D2C0014 EXT ZERO, S4, 20, 14
+BFD04612 6D2C ADDIU V0, V0, 24
+BFD04614 BFD241A3 LUI V1, 0xBFD2
+BFD04616 3083BFD2 LDC1 F30, 12419(S2)
+BFD04618 80D03083 ADDIU A0, V1, -32560
+BFD0461C 0CA2 MOVE A1, V0
+BFD0461E 3E4A77E8 JALS vListInsertEnd
+BFD04620 0C003E4A LH S2, 3072(T2)
+BFD04622 0C00 NOP
+2498: }\r
+2499: \r
+2500: if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )\r
+BFD04624 0014FC5E LW V0, 20(S8)
+BFD04628 69AB LW V1, 44(V0)
+BFD0462A 8030FC5C LW V0, -32720(GP)
+BFD0462E 692B LW V0, 44(V0)
+BFD04630 13900062 SLTU V0, V0, V1
+BFD04632 40E21390 ADDI GP, S0, 16610
+BFD04634 000840E2 BEQZC V0, 0xBFD04648
+2501: {\r
+2502: /* Return true if the task removed from the event list has a higher\r
+2503: priority than the calling task. This allows the calling task to know if\r
+2504: it should force a context switch now. */\r
+2505: xReturn = pdTRUE;\r
+BFD04638 ED01 LI V0, 1
+BFD0463A 0010F85E SW V0, 16(S8)
+2506: \r
+2507: /* Mark that a yield is pending in case the user is not using the\r
+2508: "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */\r
+2509: xYieldPending = pdTRUE;\r
+BFD0463E ED01 LI V0, 1
+BFD04640 804CF85C SW V0, -32692(GP)
+BFD04644 CC03 B 0xBFD0464C
+BFD04646 0C00 NOP
+2510: }\r
+2511: else\r
+2512: {\r
+2513: xReturn = pdFALSE;\r
+BFD04648 0010F81E SW ZERO, 16(S8)
+2514: }\r
+2515: \r
+2516: #if( configUSE_TICKLESS_IDLE != 0 )\r
+2517: {\r
+2518: /* If a task is blocked on a kernel object then xNextTaskUnblockTime\r
+2519: might be set to the blocked task's time out time. If the task is\r
+2520: unblocked for a reason other than a timeout xNextTaskUnblockTime is\r
+2521: normally left unchanged, because it is automatically reset to a new\r
+2522: value when the tick count equals xNextTaskUnblockTime. However if\r
+2523: tickless idling is used it might be more important to enter sleep mode\r
+2524: at the earliest possible time - so reset xNextTaskUnblockTime here to\r
+2525: ensure it is updated at the earliest possible time. */\r
+2526: prvResetNextTaskUnblockTime();\r
+2527: }\r
+2528: #endif\r
+2529: \r
+2530: return xReturn;\r
+BFD0464C 0010FC5E LW V0, 16(S8)
+2531: }\r
+BFD04650 0FBE MOVE SP, S8
+BFD04652 4BE7 LW RA, 28(SP)
+BFD04654 4BC6 LW S8, 24(SP)
+BFD04656 4C11 ADDIU SP, SP, 32
+BFD04658 459F JR16 RA
+BFD0465A 0C00 NOP
+2532: /*-----------------------------------------------------------*/\r
+2533: \r
+2534: BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )\r
+2535: {\r
+BFD042C4 4FF1 ADDIU SP, SP, -32
+BFD042C6 CBE7 SW RA, 28(SP)
+BFD042C8 CBC6 SW S8, 24(SP)
+BFD042CA 0FDD MOVE S8, SP
+BFD042CC 0020F89E SW A0, 32(S8)
+BFD042D0 0024F8BE SW A1, 36(S8)
+2536: TCB_t *pxUnblockedTCB;\r
+2537: BaseType_t xReturn;\r
+2538: \r
+2539: /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by\r
+2540: the event flags implementation. */\r
+2541: configASSERT( uxSchedulerSuspended != pdFALSE );\r
+BFD042D4 805CFC5C LW V0, -32676(GP)
+BFD042D8 000940A2 BNEZC V0, 0xBFD042EE
+BFD042DC BFD141A2 LUI V0, 0xBFD1
+BFD042DE 3082BFD1 LDC1 F30, 12418(S1)
+BFD042E0 98103082 ADDIU A0, V0, -26608
+BFD042E2 30A09810 SWC1 F0, 12448(S0)
+BFD042E4 09ED30A0 ADDIU A1, ZERO, 2541
+BFD042E6 09ED LBU V1, 13(A2)
+BFD042E8 4B7E77E8 JALS vAssertCalled
+BFD042EA 4B7E LW K1, 120(SP)
+BFD042EC 0C00 NOP
+2542: \r
+2543: /* Store the new item value in the event list. */\r
+2544: listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );\r
+BFD042EE 0024FC7E LW V1, 36(S8)
+BFD042F2 800041A2 LUI V0, 0x8000
+BFD042F6 44DA OR16 V1, V0
+BFD042F8 0020FC5E LW V0, 32(S8)
+BFD042FC E9A0 SW V1, 0(V0)
+2545: \r
+2546: /* Remove the event list form the event flag. Interrupts do not access\r
+2547: event flags. */\r
+2548: pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem );\r
+BFD042FE 0020FC5E LW V0, 32(S8)
+BFD04302 6923 LW V0, 12(V0)
+BFD04304 0014F85E SW V0, 20(S8)
+2549: configASSERT( pxUnblockedTCB );\r
+BFD04308 0014FC5E LW V0, 20(S8)
+BFD0430C 000940A2 BNEZC V0, 0xBFD04322
+BFD04310 BFD141A2 LUI V0, 0xBFD1
+BFD04312 3082BFD1 LDC1 F30, 12418(S1)
+BFD04314 98103082 ADDIU A0, V0, -26608
+BFD04316 30A09810 SWC1 F0, 12448(S0)
+BFD04318 09F530A0 ADDIU A1, ZERO, 2549
+BFD0431A 09F5 LBU V1, 5(A3)
+BFD0431C 4B7E77E8 JALS vAssertCalled
+BFD0431E 4B7E LW K1, 120(SP)
+BFD04320 0C00 NOP
+2550: ( void ) uxListRemove( pxEventListItem );\r
+BFD04322 0020FC9E LW A0, 32(S8)
+BFD04326 00C877E8 JALS uxListRemove
+BFD04328 0C0000C8 SLL A2, T0, 1
+BFD0432A 0C00 NOP
+2551: \r
+2552: /* Remove the task from the delayed list and add it to the ready list. The\r
+2553: scheduler is suspended so interrupts will not be accessing the ready\r
+2554: lists. */\r
+2555: ( void ) uxListRemove( &( pxUnblockedTCB->xGenericListItem ) );\r
+BFD0432C 0014FC5E LW V0, 20(S8)
+BFD04330 6D22 ADDIU V0, V0, 4
+BFD04332 0C82 MOVE A0, V0
+BFD04334 00C877E8 JALS uxListRemove
+BFD04336 0C0000C8 SLL A2, T0, 1
+BFD04338 0C00 NOP
+2556: prvAddTaskToReadyList( pxUnblockedTCB );\r
+BFD0433A 0014FC5E LW V0, 20(S8)
+BFD0433E 692B LW V0, 44(V0)
+BFD04340 ED81 LI V1, 1
+BFD04342 18100062 SLLV V1, V0, V1
+BFD04344 FC5C1810 SB ZERO, -932(S0)
+BFD04346 8040FC5C LW V0, -32704(GP)
+BFD0434A 44D3 OR16 V0, V1
+BFD0434C 8040F85C SW V0, -32704(GP)
+BFD04350 0014FC5E LW V0, 20(S8)
+BFD04354 692B LW V0, 44(V0)
+BFD04356 2524 SLL V0, V0, 2
+BFD04358 25A4 SLL V1, V0, 2
+BFD0435A 05B4 ADDU V1, V0, V1
+BFD0435C BFD241A2 LUI V0, 0xBFD2
+BFD0435E 3042BFD2 LDC1 F30, 12354(S2)
+BFD04360 806C3042 ADDIU V0, V0, -32660
+BFD04364 05A6 ADDU V1, V1, V0
+BFD04366 0014FC5E LW V0, 20(S8)
+BFD0436A 6D22 ADDIU V0, V0, 4
+BFD0436C 0C83 MOVE A0, V1
+BFD0436E 0CA2 MOVE A1, V0
+BFD04370 3E4A77E8 JALS vListInsertEnd
+BFD04372 0C003E4A LH S2, 3072(T2)
+BFD04374 0C00 NOP
+2557: \r
+2558: if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )\r
+BFD04376 0014FC5E LW V0, 20(S8)
+BFD0437A 69AB LW V1, 44(V0)
+BFD0437C 8030FC5C LW V0, -32720(GP)
+BFD04380 692B LW V0, 44(V0)
+BFD04382 13900062 SLTU V0, V0, V1
+BFD04384 40E21390 ADDI GP, S0, 16610
+BFD04386 000840E2 BEQZC V0, 0xBFD0439A
+2559: {\r
+2560: /* Return true if the task removed from the event list has\r
+2561: a higher priority than the calling task. This allows\r
+2562: the calling task to know if it should force a context\r
+2563: switch now. */\r
+2564: xReturn = pdTRUE;\r
+BFD0438A ED01 LI V0, 1
+BFD0438C 0010F85E SW V0, 16(S8)
+2565: \r
+2566: /* Mark that a yield is pending in case the user is not using the\r
+2567: "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */\r
+2568: xYieldPending = pdTRUE;\r
+BFD04390 ED01 LI V0, 1
+BFD04392 804CF85C SW V0, -32692(GP)
+BFD04396 CC03 B 0xBFD0439E
+BFD04398 0C00 NOP
+2569: }\r
+2570: else\r
+2571: {\r
+2572: xReturn = pdFALSE;\r
+BFD0439A 0010F81E SW ZERO, 16(S8)
+2573: }\r
+2574: \r
+2575: return xReturn;\r
+BFD0439E 0010FC5E LW V0, 16(S8)
+2576: }\r
+BFD043A2 0FBE MOVE SP, S8
+BFD043A4 4BE7 LW RA, 28(SP)
+BFD043A6 4BC6 LW S8, 24(SP)
+BFD043A8 4C11 ADDIU SP, SP, 32
+BFD043AA 459F JR16 RA
+BFD043AC 0C00 NOP
+2577: /*-----------------------------------------------------------*/\r
+2578: \r
+2579: void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )\r
+2580: {\r
+BFD08F4C 4FF5 ADDIU SP, SP, -24
+BFD08F4E CBE5 SW RA, 20(SP)
+BFD08F50 CBC4 SW S8, 16(SP)
+BFD08F52 0FDD MOVE S8, SP
+BFD08F54 0018F89E SW A0, 24(S8)
+2581: configASSERT( pxTimeOut );\r
+BFD08F58 0018FC5E LW V0, 24(S8)
+BFD08F5C 000940A2 BNEZC V0, 0xBFD08F72
+BFD08F60 BFD141A2 LUI V0, 0xBFD1
+BFD08F62 3082BFD1 LDC1 F30, 12418(S1)
+BFD08F64 98103082 ADDIU A0, V0, -26608
+BFD08F66 30A09810 SWC1 F0, 12448(S0)
+BFD08F68 0A1530A0 ADDIU A1, ZERO, 2581
+BFD08F6A 0A15 LBU A0, 5(S1)
+BFD08F6C 4B7E77E8 JALS vAssertCalled
+BFD08F6E 4B7E LW K1, 120(SP)
+BFD08F70 0C00 NOP
+2582: pxTimeOut->xOverflowCount = xNumOfOverflows;\r
+BFD08F72 8050FC7C LW V1, -32688(GP)
+BFD08F76 0018FC5E LW V0, 24(S8)
+BFD08F7A E9A0 SW V1, 0(V0)
+2583: pxTimeOut->xTimeOnEntering = xTickCount;\r
+BFD08F7C 803CFC7C LW V1, -32708(GP)
+BFD08F80 0018FC5E LW V0, 24(S8)
+BFD08F84 E9A1 SW V1, 4(V0)
+2584: }\r
+BFD08F86 0FBE MOVE SP, S8
+BFD08F88 4BE5 LW RA, 20(SP)
+BFD08F8A 4BC4 LW S8, 16(SP)
+BFD08F8C 4C0D ADDIU SP, SP, 24
+BFD08F8E 459F JR16 RA
+BFD08F90 0C00 NOP
+2585: /*-----------------------------------------------------------*/\r
+2586: \r
+2587: BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )\r
+2588: {\r
+BFD03FEC 4FF1 ADDIU SP, SP, -32
+BFD03FEE CBE7 SW RA, 28(SP)
+BFD03FF0 CBC6 SW S8, 24(SP)
+BFD03FF2 0FDD MOVE S8, SP
+BFD03FF4 0020F89E SW A0, 32(S8)
+BFD03FF8 0024F8BE SW A1, 36(S8)
+2589: BaseType_t xReturn;\r
+2590: \r
+2591: configASSERT( pxTimeOut );\r
+BFD03FFC 0020FC5E LW V0, 32(S8)
+BFD04000 000940A2 BNEZC V0, 0xBFD04016
+BFD04004 BFD141A2 LUI V0, 0xBFD1
+BFD04006 3082BFD1 LDC1 F30, 12418(S1)
+BFD04008 98103082 ADDIU A0, V0, -26608
+BFD0400A 30A09810 SWC1 F0, 12448(S0)
+BFD0400C 0A1F30A0 ADDIU A1, ZERO, 2591
+BFD0400E 0A1F LBU A0, -1(S1)
+BFD04010 4B7E77E8 JALS vAssertCalled
+BFD04012 4B7E LW K1, 120(SP)
+BFD04014 0C00 NOP
+2592: configASSERT( pxTicksToWait );\r
+BFD04016 0024FC5E LW V0, 36(S8)
+BFD0401A 000940A2 BNEZC V0, 0xBFD04030
+BFD0401E BFD141A2 LUI V0, 0xBFD1
+BFD04020 3082BFD1 LDC1 F30, 12418(S1)
+BFD04022 98103082 ADDIU A0, V0, -26608
+BFD04024 30A09810 SWC1 F0, 12448(S0)
+BFD04026 0A2030A0 ADDIU A1, ZERO, 2592
+BFD04028 0A20 LBU A0, 0(V0)
+BFD0402A 4B7E77E8 JALS vAssertCalled
+BFD0402C 4B7E LW K1, 120(SP)
+BFD0402E 0C00 NOP
+2593: \r
+2594: taskENTER_CRITICAL();\r
+BFD04030 33B877E8 JALS vTaskEnterCritical
+BFD04032 0C0033B8 ADDIU SP, T8, 3072
+BFD04034 0C00 NOP
+2595: {\r
+2596: /* Minor optimisation. The tick count cannot change in this block. */\r
+2597: const TickType_t xConstTickCount = xTickCount;\r
+BFD04036 803CFC5C LW V0, -32708(GP)
+BFD0403A 0014F85E SW V0, 20(S8)
+2598: \r
+2599: #if ( INCLUDE_vTaskSuspend == 1 )\r
+2600: /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is\r
+2601: the maximum block time then the task should block indefinitely, and\r
+2602: therefore never time out. */\r
+2603: if( *pxTicksToWait == portMAX_DELAY )\r
+BFD0403E 0024FC5E LW V0, 36(S8)
+BFD04042 69A0 LW V1, 0(V0)
+BFD04044 ED7F LI V0, -1
+BFD04046 0005B443 BNE V1, V0, 0xBFD04054
+BFD04048 0C000005 SLL ZERO, A1, 1
+BFD0404A 0C00 NOP
+2604: {\r
+2605: xReturn = pdFALSE;\r
+BFD0404C 0010F81E SW ZERO, 16(S8)
+BFD0404E CC3D0010 REPL.PH T9, 0x10
+BFD04050 CC3D B 0xBFD040CC
+BFD04052 0C00 NOP
+2606: }\r
+2607: else /* We are not blocking indefinitely, perform the checks below. */\r
+2608: #endif\r
+2609: \r
+2610: if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */\r
+BFD04054 0020FC5E LW V0, 32(S8)
+BFD04058 69A0 LW V1, 0(V0)
+BFD0405A 8050FC5C LW V0, -32688(GP)
+BFD0405E 000F9443 BEQ V1, V0, 0xBFD04080
+BFD04060 0C00000F SLL ZERO, T7, 1
+BFD04062 0C00 NOP
+BFD04064 0020FC5E LW V0, 32(S8)
+BFD04068 69A1 LW V1, 4(V0)
+BFD0406A 0014FC5E LW V0, 20(S8)
+BFD0406E 13900062 SLTU V0, V0, V1
+BFD04070 40A21390 ADDI GP, S0, 16546
+BFD04072 000540A2 BNEZC V0, 0xBFD04080
+2611: {\r
+2612: /* The tick count is greater than the time at which vTaskSetTimeout()\r
+2613: was called, but has also overflowed since vTaskSetTimeOut() was called.\r
+2614: It must have wrapped all the way around and gone past us again. This\r
+2615: passed since vTaskSetTimeout() was called. */\r
+2616: xReturn = pdTRUE;\r
+BFD04076 ED01 LI V0, 1
+BFD04078 0010F85E SW V0, 16(S8)
+BFD0407C CC27 B 0xBFD040CC
+BFD0407E 0C00 NOP
+2617: }\r
+2618: else if( ( xConstTickCount - pxTimeOut->xTimeOnEntering ) < *pxTicksToWait )\r
+BFD04080 0020FC5E LW V0, 32(S8)
+BFD04084 6921 LW V0, 4(V0)
+BFD04086 0014FC7E LW V1, 20(S8)
+BFD0408A 05A7 SUBU V1, V1, V0
+BFD0408C 0024FC5E LW V0, 36(S8)
+BFD04090 6920 LW V0, 0(V0)
+BFD04092 13900043 SLTU V0, V1, V0
+BFD04094 40E21390 ADDI GP, S0, 16610
+BFD04096 001640E2 BEQZC V0, 0xBFD040C6
+2619: {\r
+2620: /* Not a genuine timeout. Adjust parameters for time remaining. */\r
+2621: *pxTicksToWait -= ( xConstTickCount - pxTimeOut->xTimeOnEntering );\r
+BFD0409A 0024FC5E LW V0, 36(S8)
+BFD0409E 69A0 LW V1, 0(V0)
+BFD040A0 0020FC5E LW V0, 32(S8)
+BFD040A4 6A21 LW A0, 4(V0)
+BFD040A6 0014FC5E LW V0, 20(S8)
+BFD040AA 0529 SUBU V0, A0, V0
+BFD040AC 05A6 ADDU V1, V1, V0
+BFD040AE 0024FC5E LW V0, 36(S8)
+BFD040B2 E9A0 SW V1, 0(V0)
+2622: vTaskSetTimeOutState( pxTimeOut );\r
+BFD040B4 0020FC9E LW A0, 32(S8)
+BFD040B8 47A677E8 JALS vTaskSetTimeOutState
+BFD040BC 0C00 NOP
+2623: xReturn = pdFALSE;\r
+BFD040BE 0010F81E SW ZERO, 16(S8)
+BFD040C2 CC04 B 0xBFD040CC
+BFD040C4 0C00 NOP
+2624: }\r
+2625: else\r
+2626: {\r
+2627: xReturn = pdTRUE;\r
+BFD040C6 ED01 LI V0, 1
+BFD040C8 0010F85E SW V0, 16(S8)
+2628: }\r
+2629: }\r
+2630: taskEXIT_CRITICAL();\r
+BFD040CC 40AA77E8 JALS vTaskExitCritical
+BFD040CE 0C0040AA BNEZC T2, 0xBFD058D2
+BFD040D0 0C00 NOP
+2631: \r
+2632: return xReturn;\r
+BFD040D2 0010FC5E LW V0, 16(S8)
+2633: }\r
+BFD040D6 0FBE MOVE SP, S8
+BFD040D8 4BE7 LW RA, 28(SP)
+BFD040DA 4BC6 LW S8, 24(SP)
+BFD040DC 4C11 ADDIU SP, SP, 32
+BFD040DE 459F JR16 RA
+BFD040E0 0C00 NOP
+2634: /*-----------------------------------------------------------*/\r
+2635: \r
+2636: void vTaskMissedYield( void )\r
+2637: {\r
+BFD09E54 4FB0 ADDIU SP, SP, -8
+BFD09E56 CBC1 SW S8, 4(SP)
+BFD09E58 0FDD MOVE S8, SP
+2638: xYieldPending = pdTRUE;\r
+BFD09E5A ED01 LI V0, 1
+BFD09E5C 804CF85C SW V0, -32692(GP)
+2639: }\r
+BFD09E60 0FBE MOVE SP, S8
+BFD09E62 4BC1 LW S8, 4(SP)
+BFD09E64 4C05 ADDIU SP, SP, 8
+BFD09E66 459F JR16 RA
+BFD09E68 0C00 NOP
+2640: /*-----------------------------------------------------------*/\r
+2641: \r
+2642: #if ( configUSE_TRACE_FACILITY == 1 )\r
+2643: \r
+2644: UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )\r
+2645: {\r
+2646: UBaseType_t uxReturn;\r
+2647: TCB_t *pxTCB;\r
+2648: \r
+2649: if( xTask != NULL )\r
+2650: {\r
+2651: pxTCB = ( TCB_t * ) xTask;\r
+2652: uxReturn = pxTCB->uxTaskNumber;\r
+2653: }\r
+2654: else\r
+2655: {\r
+2656: uxReturn = 0U;\r
+2657: }\r
+2658: \r
+2659: return uxReturn;\r
+2660: }\r
+2661: \r
+2662: #endif /* configUSE_TRACE_FACILITY */\r
+2663: /*-----------------------------------------------------------*/\r
+2664: \r
+2665: #if ( configUSE_TRACE_FACILITY == 1 )\r
+2666: \r
+2667: void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )\r
+2668: {\r
+2669: TCB_t *pxTCB;\r
+2670: \r
+2671: if( xTask != NULL )\r
+2672: {\r
+2673: pxTCB = ( TCB_t * ) xTask;\r
+2674: pxTCB->uxTaskNumber = uxHandle;\r
+2675: }\r
+2676: }\r
+2677: \r
+2678: #endif /* configUSE_TRACE_FACILITY */\r
+2679: \r
+2680: /*\r
+2681: * -----------------------------------------------------------\r
+2682: * The Idle task.\r
+2683: * ----------------------------------------------------------\r
+2684: *\r
+2685: * The portTASK_FUNCTION() macro is used to allow port/compiler specific\r
+2686: * language extensions. The equivalent prototype for this function is:\r
+2687: *\r
+2688: * void prvIdleTask( void *pvParameters );\r
+2689: *\r
+2690: */\r
+2691: static portTASK_FUNCTION( prvIdleTask, pvParameters )\r
+2692: {\r
+BFD08BC4 4FF1 ADDIU SP, SP, -32
+BFD08BC6 CBE7 SW RA, 28(SP)
+BFD08BC8 CBC6 SW S8, 24(SP)
+BFD08BCA 0FDD MOVE S8, SP
+BFD08BCC 0020F89E SW A0, 32(S8)
+BFD08BD0 CC02 B 0xBFD08BD6
+BFD08BD2 0C00 NOP
+2693: /* Stop warnings. */\r
+2694: ( void ) pvParameters;\r
+2695: \r
+2696: for( ;; )\r
+2697: {\r
+2698: /* See if any tasks have been deleted. */\r
+2699: prvCheckTasksWaitingTermination();\r
+BFD08BD6 35AE77E8 JALS prvCheckTasksWaitingTermination
+BFD08BD8 0C0035AE LHU T5, 3072(T6)
+BFD08BDA 0C00 NOP
+2700: \r
+2701: #if ( configUSE_PREEMPTION == 0 )\r
+2702: {\r
+2703: /* If we are not using preemption we keep forcing a task switch to\r
+2704: see if any other task has become available. If we are using\r
+2705: preemption we don't need to do this as any task becoming available\r
+2706: will automatically get the processor anyway. */\r
+2707: taskYIELD();\r
+2708: }\r
+2709: #endif /* configUSE_PREEMPTION */\r
+2710: \r
+2711: #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )\r
+2712: {\r
+2713: /* When using preemption tasks of equal priority will be\r
+2714: timesliced. If a task that is sharing the idle priority is ready\r
+2715: to run then the idle task should yield before the end of the\r
+2716: timeslice.\r
+2717: \r
+2718: A critical region is not required here as we are just reading from\r
+2719: the list, and an occasional incorrect value will not matter. If\r
+2720: the ready list at the idle priority contains more than one task\r
+2721: then a task other than the idle task is ready to execute. */\r
+2722: if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )\r
+BFD08BDC BFD241A2 LUI V0, 0xBFD2
+BFD08BDE FC42BFD2 LDC1 F30, -958(S2)
+BFD08BE0 806CFC42 LW V0, -32660(V0)
+BFD08BE4 0002B042 SLTIU V0, V0, 2
+BFD08BE8 FFF440A2 BNEZC V0, 0xBFD08BD4
+BFD08BEA 77E8FFF4 LW RA, 30696(S4)
+2723: {\r
+2724: taskYIELD();\r
+BFD08BEC 4E5677E8 JALS ulPortGetCP0Cause
+BFD08BEE 4E56 ADDIU S2, S2, -5
+BFD08BF0 0C00 NOP
+BFD08BF2 0010F85E SW V0, 16(S8)
+BFD08BF6 0010FC5E LW V0, 16(S8)
+BFD08BFA 01005042 ORI V0, V0, 256
+BFD08BFE 0010F85E SW V0, 16(S8)
+BFD08C02 0010FC9E LW A0, 16(S8)
+BFD08C06 4E6677E8 JALS vPortSetCP0Cause
+BFD08C08 4E66 ADDIU S3, S3, 3
+BFD08C0A 0C00 NOP
+2725: }\r
+2726: else\r
+2727: {\r
+2728: mtCOVERAGE_TEST_MARKER();\r
+2729: }\r
+2730: }\r
+2731: #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */\r
+2732: \r
+2733: #if ( configUSE_IDLE_HOOK == 1 )\r
+2734: {\r
+2735: extern void vApplicationIdleHook( void );\r
+2736: \r
+2737: /* Call the user defined function from within the idle task. This\r
+2738: allows the application designer to add background functionality\r
+2739: without the overhead of a separate task.\r
+2740: NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,\r
+2741: CALL A FUNCTION THAT MIGHT BLOCK. */\r
+2742: vApplicationIdleHook();\r
+2743: }\r
+2744: #endif /* configUSE_IDLE_HOOK */\r
+2745: \r
+2746: /* This conditional compilation should use inequality to 0, not equality\r
+2747: to 1. This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when\r
+2748: user defined low power mode implementations require\r
+2749: configUSE_TICKLESS_IDLE to be set to a value other than 1. */\r
+2750: #if ( configUSE_TICKLESS_IDLE != 0 )\r
+2751: {\r
+2752: TickType_t xExpectedIdleTime;\r
+2753: \r
+2754: /* It is not desirable to suspend then resume the scheduler on\r
+2755: each iteration of the idle task. Therefore, a preliminary\r
+2756: test of the expected idle time is performed without the\r
+2757: scheduler suspended. The result here is not necessarily\r
+2758: valid. */\r
+2759: xExpectedIdleTime = prvGetExpectedIdleTime();\r
+2760: \r
+2761: if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )\r
+2762: {\r
+2763: vTaskSuspendAll();\r
+2764: {\r
+2765: /* Now the scheduler is suspended, the expected idle\r
+2766: time can be sampled again, and this time its value can\r
+2767: be used. */\r
+2768: configASSERT( xNextTaskUnblockTime >= xTickCount );\r
+2769: xExpectedIdleTime = prvGetExpectedIdleTime();\r
+2770: \r
+2771: if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )\r
+2772: {\r
+2773: traceLOW_POWER_IDLE_BEGIN();\r
+2774: portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );\r
+2775: traceLOW_POWER_IDLE_END();\r
+2776: }\r
+2777: else\r
+2778: {\r
+2779: mtCOVERAGE_TEST_MARKER();\r
+2780: }\r
+2781: }\r
+2782: ( void ) xTaskResumeAll();\r
+2783: }\r
+2784: else\r
+2785: {\r
+2786: mtCOVERAGE_TEST_MARKER();\r
+2787: }\r
+2788: }\r
+2789: #endif /* configUSE_TICKLESS_IDLE */\r
+2790: }\r
+BFD08BD4 0C00 NOP
+BFD08C0C CFE4 B 0xBFD08BD6
+BFD08C0E 0C00 NOP
+2791: }\r
+2792: /*-----------------------------------------------------------*/\r
+2793: \r
+2794: #if( configUSE_TICKLESS_IDLE != 0 )\r
+2795: \r
+2796: eSleepModeStatus eTaskConfirmSleepModeStatus( void )\r
+2797: {\r
+2798: /* The idle task exists in addition to the application tasks. */\r
+2799: const UBaseType_t uxNonApplicationTasks = 1;\r
+2800: eSleepModeStatus eReturn = eStandardSleep;\r
+2801: \r
+2802: if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )\r
+2803: {\r
+2804: /* A task was made ready while the scheduler was suspended. */\r
+2805: eReturn = eAbortSleep;\r
+2806: }\r
+2807: else if( xYieldPending != pdFALSE )\r
+2808: {\r
+2809: /* A yield was pended while the scheduler was suspended. */\r
+2810: eReturn = eAbortSleep;\r
+2811: }\r
+2812: else\r
+2813: {\r
+2814: /* If all the tasks are in the suspended list (which might mean they\r
+2815: have an infinite block time rather than actually being suspended)\r
+2816: then it is safe to turn all clocks off and just wait for external\r
+2817: interrupts. */\r
+2818: if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )\r
+2819: {\r
+2820: eReturn = eNoTasksWaitingTimeout;\r
+2821: }\r
+2822: else\r
+2823: {\r
+2824: mtCOVERAGE_TEST_MARKER();\r
+2825: }\r
+2826: }\r
+2827: \r
+2828: return eReturn;\r
+2829: }\r
+2830: \r
+2831: #endif /* configUSE_TICKLESS_IDLE */\r
+2832: /*-----------------------------------------------------------*/\r
+2833: \r
+2834: static void prvInitialiseTCBVariables( TCB_t * const pxTCB, const char * const pcName, UBaseType_t uxPriority, const MemoryRegion_t * const xRegions, const uint16_t usStackDepth ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r
+2835: {\r
+BFD03CE8 4FED ADDIU SP, SP, -40
+BFD03CEA CBE9 SW RA, 36(SP)
+BFD03CEC CBC8 SW S8, 32(SP)
+BFD03CEE 0FDD MOVE S8, SP
+BFD03CF0 0028F89E SW A0, 40(S8)
+BFD03CF4 002CF8BE SW A1, 44(S8)
+BFD03CF8 0030F8DE SW A2, 48(S8)
+BFD03CFC 0034F8FE SW A3, 52(S8)
+BFD03D00 0038FC5E LW V0, 56(S8)
+BFD03D04 0018385E SH V0, 24(S8)
+2836: UBaseType_t x;\r
+2837: \r
+2838: /* Store the task name in the TCB. */\r
+2839: for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )\r
+BFD03D08 0010F81E SW ZERO, 16(S8)
+BFD03D0A CC1D0010 SHILO null, 16
+BFD03D0C CC1D B 0xBFD03D48
+BFD03D0E 0C00 NOP
+BFD03D3E 0010FC5E LW V0, 16(S8)
+BFD03D42 6D20 ADDIU V0, V0, 1
+BFD03D44 0010F85E SW V0, 16(S8)
+BFD03D48 0010FC5E LW V0, 16(S8)
+BFD03D4C 0008B042 SLTIU V0, V0, 8
+BFD03D50 FFDE40A2 BNEZC V0, 0xBFD03D10
+BFD03D52 CC02FFDE LW S8, -13310(S8)
+BFD03D54 CC02 B 0xBFD03D5A
+BFD03D56 0C00 NOP
+2840: {\r
+2841: pxTCB->pcTaskName[ x ] = pcName[ x ];\r
+BFD03D10 002CFC7E LW V1, 44(S8)
+BFD03D14 0010FC5E LW V0, 16(S8)
+BFD03D18 0526 ADDU V0, V1, V0
+BFD03D1A 00001C62 LB V1, 0(V0)
+BFD03D1E 0028FC9E LW A0, 40(S8)
+BFD03D22 0010FC5E LW V0, 16(S8)
+BFD03D26 0528 ADDU V0, A0, V0
+BFD03D28 00341862 SB V1, 52(V0)
+2842: \r
+2843: /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than\r
+2844: configMAX_TASK_NAME_LEN characters just in case the memory after the\r
+2845: string is not accessible (extremely unlikely). */\r
+2846: if( pcName[ x ] == 0x00 )\r
+BFD03D2C 002CFC7E LW V1, 44(S8)
+BFD03D30 0010FC5E LW V0, 16(S8)
+BFD03D34 0526 ADDU V0, V1, V0
+BFD03D36 00001C42 LB V0, 0(V0)
+BFD03D3A 000D40E2 BEQZC V0, 0xBFD03D58
+2847: {\r
+2848: break;\r
+BFD03D58 0C00 NOP
+2849: }\r
+2850: else\r
+2851: {\r
+2852: mtCOVERAGE_TEST_MARKER();\r
+2853: }\r
+2854: }\r
+2855: \r
+2856: /* Ensure the name string is terminated in the case that the string length\r
+2857: was greater or equal to configMAX_TASK_NAME_LEN. */\r
+2858: pxTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';\r
+BFD03D5A 0028FC5E LW V0, 40(S8)
+BFD03D5E 003B1802 SB ZERO, 59(V0)
+2859: \r
+2860: /* This is used as an array index so must ensure it's not too large. First\r
+2861: remove the privilege bit if one is present. */\r
+2862: if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )\r
+BFD03D62 0030FC5E LW V0, 48(S8)
+BFD03D66 0005B042 SLTIU V0, V0, 5
+BFD03D6A 000340A2 BNEZC V0, 0xBFD03D74
+2863: {\r
+2864: uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;\r
+BFD03D6E ED04 LI V0, 4
+BFD03D70 0030F85E SW V0, 48(S8)
+2865: }\r
+2866: else\r
+2867: {\r
+2868: mtCOVERAGE_TEST_MARKER();\r
+2869: }\r
+2870: \r
+2871: pxTCB->uxPriority = uxPriority;\r
+BFD03D74 0028FC5E LW V0, 40(S8)
+BFD03D78 0030FC7E LW V1, 48(S8)
+BFD03D7C E9AB SW V1, 44(V0)
+2872: #if ( configUSE_MUTEXES == 1 )\r
+2873: {\r
+2874: pxTCB->uxBasePriority = uxPriority;\r
+BFD03D7E 0028FC5E LW V0, 40(S8)
+BFD03D82 0030FC7E LW V1, 48(S8)
+BFD03D86 0040F862 SW V1, 64(V0)
+2875: pxTCB->uxMutexesHeld = 0;\r
+BFD03D8A 0028FC5E LW V0, 40(S8)
+BFD03D8E 0044F802 SW ZERO, 68(V0)
+2876: }\r
+2877: #endif /* configUSE_MUTEXES */\r
+2878: \r
+2879: vListInitialiseItem( &( pxTCB->xGenericListItem ) );\r
+BFD03D92 0028FC5E LW V0, 40(S8)
+BFD03D96 6D22 ADDIU V0, V0, 4
+BFD03D98 0C82 MOVE A0, V0
+BFD03D9A 4EE677E8 JALS vListInitialiseItem
+BFD03D9C 4EE6 ADDIU S7, S7, 3
+BFD03D9E 0C00 NOP
+2880: vListInitialiseItem( &( pxTCB->xEventListItem ) );\r
+BFD03DA0 0028FC5E LW V0, 40(S8)
+BFD03DA2 6D2C0028 EXT AT, T0, 20, 14
+BFD03DA4 6D2C ADDIU V0, V0, 24
+BFD03DA6 0C82 MOVE A0, V0
+BFD03DA8 4EE677E8 JALS vListInitialiseItem
+BFD03DAA 4EE6 ADDIU S7, S7, 3
+BFD03DAC 0C00 NOP
+2881: \r
+2882: /* Set the pxTCB as a link back from the ListItem_t. This is so we can get\r
+2883: back to the containing TCB from a generic item in a list. */\r
+2884: listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB );\r
+BFD03DAE 0028FC5E LW V0, 40(S8)
+BFD03DB2 0028FC7E LW V1, 40(S8)
+BFD03DB6 E9A4 SW V1, 16(V0)
+2885: \r
+2886: /* Event lists are always in priority order. */\r
+2887: listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
+BFD03DB8 ED85 LI V1, 5
+BFD03DBA 0030FC5E LW V0, 48(S8)
+BFD03DBE 05A7 SUBU V1, V1, V0
+BFD03DC0 0028FC5E LW V0, 40(S8)
+BFD03DC4 E9A6 SW V1, 24(V0)
+2888: listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB );\r
+BFD03DC6 0028FC5E LW V0, 40(S8)
+BFD03DCA 0028FC7E LW V1, 40(S8)
+BFD03DCE E9A9 SW V1, 36(V0)
+2889: \r
+2890: #if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
+2891: {\r
+2892: pxTCB->uxCriticalNesting = ( UBaseType_t ) 0U;\r
+BFD03DD0 0028FC5E LW V0, 40(S8)
+BFD03DD4 E82F SW S0, 60(V0)
+2893: }\r
+2894: #endif /* portCRITICAL_NESTING_IN_TCB */\r
+2895: \r
+2896: #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+2897: {\r
+2898: pxTCB->pxTaskTag = NULL;\r
+2899: }\r
+2900: #endif /* configUSE_APPLICATION_TASK_TAG */\r
+2901: \r
+2902: #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+2903: {\r
+2904: pxTCB->ulRunTimeCounter = 0UL;\r
+2905: }\r
+2906: #endif /* configGENERATE_RUN_TIME_STATS */\r
+2907: \r
+2908: #if ( portUSING_MPU_WRAPPERS == 1 )\r
+2909: {\r
+2910: vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, pxTCB->pxStack, usStackDepth );\r
+2911: }\r
+2912: #else /* portUSING_MPU_WRAPPERS */\r
+2913: {\r
+2914: ( void ) xRegions;\r
+2915: ( void ) usStackDepth;\r
+2916: }\r
+2917: #endif /* portUSING_MPU_WRAPPERS */\r
+2918: \r
+2919: #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\r
+2920: {\r
+2921: for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )\r
+2922: {\r
+2923: pxTCB->pvThreadLocalStoragePointers[ x ] = NULL;\r
+2924: }\r
+2925: }\r
+2926: #endif\r
+2927: \r
+2928: #if ( configUSE_TASK_NOTIFICATIONS == 1 )\r
+2929: {\r
+2930: pxTCB->ulNotifiedValue = 0;\r
+BFD03DD6 0028FC5E LW V0, 40(S8)
+BFD03DDA 0048F802 SW ZERO, 72(V0)
+2931: pxTCB->eNotifyState = eNotWaitingNotification;\r
+BFD03DDE 0028FC5E LW V0, 40(S8)
+BFD03DE2 004CF802 SW ZERO, 76(V0)
+2932: }\r
+2933: #endif\r
+2934: \r
+2935: #if ( configUSE_NEWLIB_REENTRANT == 1 )\r
+2936: {\r
+2937: /* Initialise this task's Newlib reent structure. */\r
+2938: _REENT_INIT_PTR( ( &( pxTCB->xNewLib_reent ) ) );\r
+2939: }\r
+2940: #endif /* configUSE_NEWLIB_REENTRANT */\r
+2941: }\r
+BFD03DE6 0FBE MOVE SP, S8
+BFD03DE8 4BE9 LW RA, 36(SP)
+BFD03DEA 4BC8 LW S8, 32(SP)
+BFD03DEC 4C15 ADDIU SP, SP, 40
+BFD03DEE 459F JR16 RA
+BFD03DF0 0C00 NOP
+2942: /*-----------------------------------------------------------*/\r
+2943: \r
+2944: #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\r
+2945: \r
+2946: void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )\r
+2947: {\r
+2948: TCB_t *pxTCB;\r
+2949: \r
+2950: if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )\r
+2951: {\r
+2952: pxTCB = prvGetTCBFromHandle( xTaskToSet );\r
+2953: pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;\r
+2954: }\r
+2955: }\r
+2956: \r
+2957: #endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */\r
+2958: /*-----------------------------------------------------------*/\r
+2959: \r
+2960: #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\r
+2961: \r
+2962: void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )\r
+2963: {\r
+2964: void *pvReturn = NULL;\r
+2965: TCB_t *pxTCB;\r
+2966: \r
+2967: if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )\r
+2968: {\r
+2969: pxTCB = prvGetTCBFromHandle( xTaskToQuery );\r
+2970: pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];\r
+2971: }\r
+2972: else\r
+2973: {\r
+2974: pvReturn = NULL;\r
+2975: }\r
+2976: \r
+2977: return pvReturn;\r
+2978: }\r
+2979: \r
+2980: #endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */\r
+2981: /*-----------------------------------------------------------*/\r
+2982: \r
+2983: #if ( portUSING_MPU_WRAPPERS == 1 )\r
+2984: \r
+2985: void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )\r
+2986: {\r
+2987: TCB_t *pxTCB;\r
+2988: \r
+2989: /* If null is passed in here then we are modifying the MPU settings of\r
+2990: the calling task. */\r
+2991: pxTCB = prvGetTCBFromHandle( xTaskToModify );\r
+2992: \r
+2993: vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );\r
+2994: }\r
+2995: \r
+2996: #endif /* portUSING_MPU_WRAPPERS */\r
+2997: /*-----------------------------------------------------------*/\r
+2998: \r
+2999: static void prvInitialiseTaskLists( void )\r
+3000: {\r
+BFD0612C 4FF1 ADDIU SP, SP, -32
+BFD0612E CBE7 SW RA, 28(SP)
+BFD06130 CBC6 SW S8, 24(SP)
+BFD06132 0FDD MOVE S8, SP
+3001: UBaseType_t uxPriority;\r
+3002: \r
+3003: for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )\r
+BFD06134 0010F81E SW ZERO, 16(S8)
+BFD06138 CC14 B 0xBFD06162
+BFD0613A 0C00 NOP
+BFD06158 0010FC5E LW V0, 16(S8)
+BFD0615C 6D20 ADDIU V0, V0, 1
+BFD0615E 0010F85E SW V0, 16(S8)
+BFD06162 0010FC5E LW V0, 16(S8)
+BFD06166 0005B042 SLTIU V0, V0, 5
+BFD0616A FFE740A2 BNEZC V0, 0xBFD0613C
+BFD0616C 41A2FFE7 LW RA, 16802(A3)
+3004: {\r
+3005: vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );\r
+BFD0613C 0010FC5E LW V0, 16(S8)
+BFD06140 2524 SLL V0, V0, 2
+BFD06142 25A4 SLL V1, V0, 2
+BFD06144 05B4 ADDU V1, V0, V1
+BFD06146 BFD241A2 LUI V0, 0xBFD2
+BFD06148 3042BFD2 LDC1 F30, 12354(S2)
+BFD0614A 806C3042 ADDIU V0, V0, -32660
+BFD0614E 0526 ADDU V0, V1, V0
+BFD06150 0C82 MOVE A0, V0
+BFD06152 457077E8 JALS vListInitialise
+BFD06154 4570 SWM16 0x3, 0(SP)
+BFD06156 0C00 NOP
+3006: }\r
+3007: \r
+3008: vListInitialise( &xDelayedTaskList1 );\r
+BFD0616E BFD241A2 LUI V0, 0xBFD2
+BFD06170 3082BFD2 LDC1 F30, 12418(S2)
+BFD06172 80F83082 ADDIU A0, V0, -32520
+BFD06176 457077E8 JALS vListInitialise
+BFD06178 4570 SWM16 0x3, 0(SP)
+BFD0617A 0C00 NOP
+3009: vListInitialise( &xDelayedTaskList2 );\r
+BFD0617C BFD241A2 LUI V0, 0xBFD2
+BFD0617E 3082BFD2 LDC1 F30, 12418(S2)
+BFD06180 81203082 ADDIU A0, V0, -32480
+BFD06184 457077E8 JALS vListInitialise
+BFD06186 4570 SWM16 0x3, 0(SP)
+BFD06188 0C00 NOP
+3010: vListInitialise( &xPendingReadyList );\r
+BFD0618A BFD241A2 LUI V0, 0xBFD2
+BFD0618C 3082BFD2 LDC1 F30, 12418(S2)
+BFD0618E 80D03082 ADDIU A0, V0, -32560
+BFD06192 457077E8 JALS vListInitialise
+BFD06194 4570 SWM16 0x3, 0(SP)
+BFD06196 0C00 NOP
+3011: \r
+3012: #if ( INCLUDE_vTaskDelete == 1 )\r
+3013: {\r
+3014: vListInitialise( &xTasksWaitingTermination );\r
+BFD06198 BFD241A2 LUI V0, 0xBFD2
+BFD0619A 3082BFD2 LDC1 F30, 12418(S2)
+BFD0619C 810C3082 ADDIU A0, V0, -32500
+BFD061A0 457077E8 JALS vListInitialise
+BFD061A2 4570 SWM16 0x3, 0(SP)
+BFD061A4 0C00 NOP
+3015: }\r
+3016: #endif /* INCLUDE_vTaskDelete */\r
+3017: \r
+3018: #if ( INCLUDE_vTaskSuspend == 1 )\r
+3019: {\r
+3020: vListInitialise( &xSuspendedTaskList );\r
+BFD061A6 BFD241A2 LUI V0, 0xBFD2
+BFD061A8 3082BFD2 LDC1 F30, 12418(S2)
+BFD061AA 80E43082 ADDIU A0, V0, -32540
+BFD061AE 457077E8 JALS vListInitialise
+BFD061B0 4570 SWM16 0x3, 0(SP)
+BFD061B2 0C00 NOP
+3021: }\r
+3022: #endif /* INCLUDE_vTaskSuspend */\r
+3023: \r
+3024: /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList\r
+3025: using list2. */\r
+3026: pxDelayedTaskList = &xDelayedTaskList1;\r
+BFD061B4 BFD241A2 LUI V0, 0xBFD2
+BFD061B6 3042BFD2 LDC1 F30, 12354(S2)
+BFD061B8 80F83042 ADDIU V0, V0, -32520
+BFD061BC 8074F85C SW V0, -32652(GP)
+3027: pxOverflowDelayedTaskList = &xDelayedTaskList2;\r
+BFD061C0 BFD241A2 LUI V0, 0xBFD2
+BFD061C2 3042BFD2 LDC1 F30, 12354(S2)
+BFD061C4 81203042 ADDIU V0, V0, -32480
+BFD061C8 8078F85C SW V0, -32648(GP)
+3028: }\r
+BFD061CC 0FBE MOVE SP, S8
+BFD061CE 4BE7 LW RA, 28(SP)
+BFD061D0 4BC6 LW S8, 24(SP)
+BFD061D2 4C11 ADDIU SP, SP, 32
+BFD061D4 459F JR16 RA
+BFD061D6 0C00 NOP
+3029: /*-----------------------------------------------------------*/\r
+3030: \r
+3031: static void prvCheckTasksWaitingTermination( void )\r
+3032: {\r
+BFD06B5C 4FF1 ADDIU SP, SP, -32
+BFD06B5E CBE7 SW RA, 28(SP)
+BFD06B60 CBC6 SW S8, 24(SP)
+BFD06B62 0FDD MOVE S8, SP
+3033: #if ( INCLUDE_vTaskDelete == 1 )\r
+3034: {\r
+3035: BaseType_t xListIsEmpty;\r
+3036: \r
+3037: /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called\r
+3038: too often in the idle task. */\r
+3039: while( uxTasksDeleted > ( UBaseType_t ) 0U )\r
+BFD06B64 CC37 B 0xBFD06BD4
+BFD06B66 0C00 NOP
+BFD06BD4 8034FC5C LW V0, -32716(GP)
+BFD06BD8 FFC640A2 BNEZC V0, 0xBFD06B68
+BFD06BDA 0FBEFFC6 LW S8, 4030(A2)
+3040: {\r
+3041: vTaskSuspendAll();\r
+BFD06B68 4EF477E8 JALS vTaskSuspendAll
+BFD06B6A 4EF4 ADDIU S7, S7, -6
+BFD06B6C 0C00 NOP
+3042: {\r
+3043: xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination );\r
+BFD06B6E BFD241A2 LUI V0, 0xBFD2
+BFD06B70 FC42BFD2 LDC1 F30, -958(S2)
+BFD06B72 810CFC42 LW V0, -32500(V0)
+BFD06B76 0001B042 SLTIU V0, V0, 1
+BFD06B7A 0010F85E SW V0, 16(S8)
+3044: }\r
+3045: ( void ) xTaskResumeAll();\r
+BFD06B7E 158E77E8 JALS xTaskResumeAll
+BFD06B80 0C00158E LBU T4, 3072(T6)
+BFD06B82 0C00 NOP
+3046: \r
+3047: if( xListIsEmpty == pdFALSE )\r
+BFD06B84 0010FC5E LW V0, 16(S8)
+BFD06B88 002440A2 BNEZC V0, 0xBFD06BD4
+3048: {\r
+3049: TCB_t *pxTCB;\r
+3050: \r
+3051: taskENTER_CRITICAL();\r
+BFD06B8C 33B877E8 JALS vTaskEnterCritical
+BFD06B8E 0C0033B8 ADDIU SP, T8, 3072
+BFD06B90 0C00 NOP
+3052: {\r
+3053: pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );\r
+BFD06B92 BFD241A2 LUI V0, 0xBFD2
+BFD06B94 3042BFD2 LDC1 F30, 12354(S2)
+BFD06B96 810C3042 ADDIU V0, V0, -32500
+BFD06B9A 6923 LW V0, 12(V0)
+BFD06B9C 6923 LW V0, 12(V0)
+BFD06B9E 0014F85E SW V0, 20(S8)
+3054: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
+BFD06BA2 0014FC5E LW V0, 20(S8)
+BFD06BA6 6D22 ADDIU V0, V0, 4
+BFD06BA8 0C82 MOVE A0, V0
+BFD06BAA 00C877E8 JALS uxListRemove
+BFD06BAC 0C0000C8 SLL A2, T0, 1
+BFD06BAE 0C00 NOP
+3055: --uxCurrentNumberOfTasks;\r
+BFD06BB0 8038FC5C LW V0, -32712(GP)
+BFD06BB4 6D2E ADDIU V0, V0, -1
+BFD06BB6 8038F85C SW V0, -32712(GP)
+3056: --uxTasksDeleted;\r
+BFD06BBA 8034FC5C LW V0, -32716(GP)
+BFD06BBE 6D2E ADDIU V0, V0, -1
+BFD06BC0 8034F85C SW V0, -32716(GP)
+3057: }\r
+3058: taskEXIT_CRITICAL();\r
+BFD06BC4 40AA77E8 JALS vTaskExitCritical
+BFD06BC6 0C0040AA BNEZC T2, 0xBFD083CA
+BFD06BC8 0C00 NOP
+3059: \r
+3060: prvDeleteTCB( pxTCB );\r
+BFD06BCA 0014FC9E LW A0, 20(S8)
+BFD06BCE 4C6E77E8 JALS prvDeleteTCB
+BFD06BD0 4C6E ADDIU V1, V1, 7
+BFD06BD2 0C00 NOP
+3061: }\r
+3062: else\r
+3063: {\r
+3064: mtCOVERAGE_TEST_MARKER();\r
+3065: }\r
+3066: }\r
+3067: }\r
+3068: #endif /* vTaskDelete */\r
+3069: }\r
+BFD06BDC 0FBE MOVE SP, S8
+BFD06BDE 4BE7 LW RA, 28(SP)
+BFD06BE0 4BC6 LW S8, 24(SP)
+BFD06BE2 4C11 ADDIU SP, SP, 32
+BFD06BE4 459F JR16 RA
+BFD06BE6 0C00 NOP
+3070: /*-----------------------------------------------------------*/\r
+3071: \r
+3072: static void prvAddCurrentTaskToDelayedList( const TickType_t xTimeToWake )\r
+3073: {\r
+BFD06E68 4FF5 ADDIU SP, SP, -24
+BFD06E6A CBE5 SW RA, 20(SP)
+BFD06E6C CBC4 SW S8, 16(SP)
+BFD06E6E 0FDD MOVE S8, SP
+BFD06E70 0018F89E SW A0, 24(S8)
+3074: /* The list item will be inserted in wake time order. */\r
+3075: listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );\r
+BFD06E74 8030FC5C LW V0, -32720(GP)
+BFD06E78 0018FC7E LW V1, 24(S8)
+BFD06E7C E9A1 SW V1, 4(V0)
+3076: \r
+3077: if( xTimeToWake < xTickCount )\r
+BFD06E7E 803CFC5C LW V0, -32708(GP)
+BFD06E82 0018FC7E LW V1, 24(S8)
+BFD06E86 13900043 SLTU V0, V1, V0
+BFD06E88 40E21390 ADDI GP, S0, 16610
+BFD06E8A 000C40E2 BEQZC V0, 0xBFD06EA6
+3078: {\r
+3079: /* Wake time has overflowed. Place this item in the overflow list. */\r
+3080: vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
+BFD06E8E 8078FC7C LW V1, -32648(GP)
+BFD06E92 8030FC5C LW V0, -32720(GP)
+BFD06E96 6D22 ADDIU V0, V0, 4
+BFD06E98 0C83 MOVE A0, V1
+BFD06E9A 0CA2 MOVE A1, V0
+BFD06E9C 304077E8 JALS vListInsert
+BFD06E9E 0C003040 ADDIU V0, ZERO, 3072
+BFD06EA0 0C00 NOP
+BFD06EA2 CC17 B 0xBFD06ED2
+BFD06EA4 0C00 NOP
+3081: }\r
+3082: else\r
+3083: {\r
+3084: /* The wake time has not overflowed, so the current block list is used. */\r
+3085: vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
+BFD06EA6 8074FC7C LW V1, -32652(GP)
+BFD06EAA 8030FC5C LW V0, -32720(GP)
+BFD06EAE 6D22 ADDIU V0, V0, 4
+BFD06EB0 0C83 MOVE A0, V1
+BFD06EB2 0CA2 MOVE A1, V0
+BFD06EB4 304077E8 JALS vListInsert
+BFD06EB6 0C003040 ADDIU V0, ZERO, 3072
+BFD06EB8 0C00 NOP
+3086: \r
+3087: /* If the task entering the blocked state was placed at the head of the\r
+3088: list of blocked tasks then xNextTaskUnblockTime needs to be updated\r
+3089: too. */\r
+3090: if( xTimeToWake < xNextTaskUnblockTime )\r
+BFD06EBA 8058FC5C LW V0, -32680(GP)
+BFD06EBE 0018FC7E LW V1, 24(S8)
+BFD06EC2 13900043 SLTU V0, V1, V0
+BFD06EC4 40E21390 ADDI GP, S0, 16610
+BFD06EC6 000440E2 BEQZC V0, 0xBFD06ED2
+3091: {\r
+3092: xNextTaskUnblockTime = xTimeToWake;\r
+BFD06ECA 0018FC5E LW V0, 24(S8)
+BFD06ECE 8058F85C SW V0, -32680(GP)
+3093: }\r
+3094: else\r
+3095: {\r
+3096: mtCOVERAGE_TEST_MARKER();\r
+3097: }\r
+3098: }\r
+3099: }\r
+BFD06ED2 0FBE MOVE SP, S8
+BFD06ED4 4BE5 LW RA, 20(SP)
+BFD06ED6 4BC4 LW S8, 16(SP)
+BFD06ED8 4C0D ADDIU SP, SP, 24
+BFD06EDA 459F JR16 RA
+BFD06EDC 0C00 NOP
+3100: /*-----------------------------------------------------------*/\r
+3101: \r
+3102: static TCB_t *prvAllocateTCBAndStack( const uint16_t usStackDepth, StackType_t * const puxStackBuffer )\r
+3103: {\r
+BFD06328 4FF1 ADDIU SP, SP, -32
+BFD0632A CBE7 SW RA, 28(SP)
+BFD0632C CBC6 SW S8, 24(SP)
+BFD0632E 0FDD MOVE S8, SP
+BFD06330 0C44 MOVE V0, A0
+BFD06332 0024F8BE SW A1, 36(S8)
+BFD06336 0020385E SH V0, 32(S8)
+3104: TCB_t *pxNewTCB;\r
+3105: \r
+3106: /* If the stack grows down then allocate the stack then the TCB so the stack\r
+3107: does not grow into the TCB. Likewise if the stack grows up then allocate\r
+3108: the TCB then the stack. */\r
+3109: #if( portSTACK_GROWTH > 0 )\r
+3110: {\r
+3111: /* Allocate space for the TCB. Where the memory comes from depends on\r
+3112: the implementation of the port malloc function. */\r
+3113: pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );\r
+3114: \r
+3115: if( pxNewTCB != NULL )\r
+3116: {\r
+3117: /* Allocate space for the stack used by the task being created.\r
+3118: The base of the stack memory stored in the TCB so the task can\r
+3119: be deleted later if required. */\r
+3120: pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocAligned( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ), puxStackBuffer ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
+3121: \r
+3122: if( pxNewTCB->pxStack == NULL )\r
+3123: {\r
+3124: /* Could not allocate the stack. Delete the allocated TCB. */\r
+3125: vPortFree( pxNewTCB );\r
+3126: pxNewTCB = NULL;\r
+3127: }\r
+3128: }\r
+3129: }\r
+3130: #else /* portSTACK_GROWTH */\r
+3131: {\r
+3132: StackType_t *pxStack;\r
+3133: \r
+3134: /* Allocate space for the stack used by the task being created. */\r
+3135: pxStack = ( StackType_t * ) pvPortMallocAligned( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ), puxStackBuffer ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
+BFD0633A 0024FC5E LW V0, 36(S8)
+BFD0633E 000940A2 BNEZC V0, 0xBFD06354
+BFD06342 0020345E LHU V0, 32(S8)
+BFD06346 2524 SLL V0, V0, 2
+BFD06348 0C82 MOVE A0, V0
+BFD0634A 111677E8 JALS pvPortMalloc
+BFD0634C 0C001116 ADDI T0, S6, 3072
+BFD0634E 0C00 NOP
+BFD06350 CC03 B 0xBFD06358
+BFD06352 0C00 NOP
+BFD06354 0024FC5E LW V0, 36(S8)
+BFD06358 0014F85E SW V0, 20(S8)
+3136: \r
+3137: if( pxStack != NULL )\r
+BFD0635C 0014FC5E LW V0, 20(S8)
+BFD06360 001840E2 BEQZC V0, 0xBFD06394
+BFD06362 EE500018 AND SP, T8, ZERO
+3138: {\r
+3139: /* Allocate space for the TCB. Where the memory comes from depends\r
+3140: on the implementation of the port malloc function. */\r
+3141: pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );\r
+BFD06364 EE50 LI A0, 80
+BFD06366 111677E8 JALS pvPortMalloc
+BFD06368 0C001116 ADDI T0, S6, 3072
+BFD0636A 0C00 NOP
+BFD0636C 0010F85E SW V0, 16(S8)
+3142: \r
+3143: if( pxNewTCB != NULL )\r
+BFD06370 0010FC5E LW V0, 16(S8)
+BFD06374 000740E2 BEQZC V0, 0xBFD06386
+3144: {\r
+3145: /* Store the stack location in the TCB. */\r
+3146: pxNewTCB->pxStack = pxStack;\r
+BFD06378 0010FC5E LW V0, 16(S8)
+BFD0637C 0014FC7E LW V1, 20(S8)
+BFD0637E E9AC0014 EXT ZERO, S4, 6, 30
+BFD06380 E9AC SW V1, 48(V0)
+BFD06382 CC0A B 0xBFD06398
+BFD06384 0C00 NOP
+3147: }\r
+3148: else\r
+3149: {\r
+3150: /* The stack cannot be used as the TCB was not created. Free it\r
+3151: again. */\r
+3152: vPortFree( pxStack );\r
+BFD06386 0014FC9E LW A0, 20(S8)
+BFD0638A 2FEA77E8 JALS vPortFree
+BFD0638C 2FEA ANDI A3, A2, 0x20
+BFD0638E 0C00 NOP
+BFD06390 CC03 B 0xBFD06398
+BFD06392 0C00 NOP
+3153: }\r
+3154: }\r
+3155: else\r
+3156: {\r
+3157: pxNewTCB = NULL;\r
+BFD06394 0010F81E SW ZERO, 16(S8)
+3158: }\r
+3159: }\r
+3160: #endif /* portSTACK_GROWTH */\r
+3161: \r
+3162: if( pxNewTCB != NULL )\r
+BFD06398 0010FC5E LW V0, 16(S8)
+BFD0639C 000D40E2 BEQZC V0, 0xBFD063BA
+3163: {\r
+3164: /* Avoid dependency on memset() if it is not required. */\r
+3165: #if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )\r
+3166: {\r
+3167: /* Just to help debugging. */\r
+3168: ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) usStackDepth * sizeof( StackType_t ) );\r
+BFD063A0 0010FC5E LW V0, 16(S8)
+BFD063A2 69AC0010 EXT ZERO, S0, 6, 14
+BFD063A4 69AC LW V1, 48(V0)
+BFD063A6 0020345E LHU V0, 32(S8)
+BFD063AA 2524 SLL V0, V0, 2
+BFD063AC 0C83 MOVE A0, V1
+BFD063AE 00A530A0 ADDIU A1, ZERO, 165
+BFD063B2 0CC2 MOVE A2, V0
+BFD063B4 36F677E8 JALS 0xBFD06DEC
+BFD063B6 0C0036F6 LHU S7, 3072(S6)
+BFD063B8 0C00 NOP
+3169: }\r
+3170: #endif /* ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) ) */\r
+3171: }\r
+3172: \r
+3173: return pxNewTCB;\r
+BFD063BA 0010FC5E LW V0, 16(S8)
+3174: }\r
+BFD063BE 0FBE MOVE SP, S8
+BFD063C0 4BE7 LW RA, 28(SP)
+BFD063C2 4BC6 LW S8, 24(SP)
+BFD063C4 4C11 ADDIU SP, SP, 32
+BFD063C6 459F JR16 RA
+BFD063C8 0C00 NOP
+3175: /*-----------------------------------------------------------*/\r
+3176: \r
+3177: #if ( configUSE_TRACE_FACILITY == 1 )\r
+3178: \r
+3179: static UBaseType_t prvListTaskWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )\r
+3180: {\r
+3181: volatile TCB_t *pxNextTCB, *pxFirstTCB;\r
+3182: UBaseType_t uxTask = 0;\r
+3183: \r
+3184: if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )\r
+3185: {\r
+3186: listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );\r
+3187: \r
+3188: /* Populate an TaskStatus_t structure within the\r
+3189: pxTaskStatusArray array for each task that is referenced from\r
+3190: pxList. See the definition of TaskStatus_t in task.h for the\r
+3191: meaning of each TaskStatus_t structure member. */\r
+3192: do\r
+3193: {\r
+3194: listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );\r
+3195: \r
+3196: pxTaskStatusArray[ uxTask ].xHandle = ( TaskHandle_t ) pxNextTCB;\r
+3197: pxTaskStatusArray[ uxTask ].pcTaskName = ( const char * ) &( pxNextTCB->pcTaskName [ 0 ] );\r
+3198: pxTaskStatusArray[ uxTask ].xTaskNumber = pxNextTCB->uxTCBNumber;\r
+3199: pxTaskStatusArray[ uxTask ].eCurrentState = eState;\r
+3200: pxTaskStatusArray[ uxTask ].uxCurrentPriority = pxNextTCB->uxPriority;\r
+3201: \r
+3202: #if ( INCLUDE_vTaskSuspend == 1 )\r
+3203: {\r
+3204: /* If the task is in the suspended list then there is a chance\r
+3205: it is actually just blocked indefinitely - so really it should\r
+3206: be reported as being in the Blocked state. */\r
+3207: if( eState == eSuspended )\r
+3208: {\r
+3209: if( listLIST_ITEM_CONTAINER( &( pxNextTCB->xEventListItem ) ) != NULL )\r
+3210: {\r
+3211: pxTaskStatusArray[ uxTask ].eCurrentState = eBlocked;\r
+3212: }\r
+3213: }\r
+3214: }\r
+3215: #endif /* INCLUDE_vTaskSuspend */\r
+3216: \r
+3217: #if ( configUSE_MUTEXES == 1 )\r
+3218: {\r
+3219: pxTaskStatusArray[ uxTask ].uxBasePriority = pxNextTCB->uxBasePriority;\r
+3220: }\r
+3221: #else\r
+3222: {\r
+3223: pxTaskStatusArray[ uxTask ].uxBasePriority = 0;\r
+3224: }\r
+3225: #endif\r
+3226: \r
+3227: #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+3228: {\r
+3229: pxTaskStatusArray[ uxTask ].ulRunTimeCounter = pxNextTCB->ulRunTimeCounter;\r
+3230: }\r
+3231: #else\r
+3232: {\r
+3233: pxTaskStatusArray[ uxTask ].ulRunTimeCounter = 0;\r
+3234: }\r
+3235: #endif\r
+3236: \r
+3237: #if ( portSTACK_GROWTH > 0 )\r
+3238: {\r
+3239: pxTaskStatusArray[ uxTask ].usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxNextTCB->pxEndOfStack );\r
+3240: }\r
+3241: #else\r
+3242: {\r
+3243: pxTaskStatusArray[ uxTask ].usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxNextTCB->pxStack );\r
+3244: }\r
+3245: #endif\r
+3246: \r
+3247: uxTask++;\r
+3248: \r
+3249: } while( pxNextTCB != pxFirstTCB );\r
+3250: }\r
+3251: else\r
+3252: {\r
+3253: mtCOVERAGE_TEST_MARKER();\r
+3254: }\r
+3255: \r
+3256: return uxTask;\r
+3257: }\r
+3258: \r
+3259: #endif /* configUSE_TRACE_FACILITY */\r
+3260: /*-----------------------------------------------------------*/\r
+3261: \r
+3262: #if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )\r
+3263: \r
+3264: static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )\r
+3265: {\r
+BFD089A4 4FF9 ADDIU SP, SP, -16
+BFD089A6 CBC3 SW S8, 12(SP)
+BFD089A8 0FDD MOVE S8, SP
+BFD089AA 0010F89E SW A0, 16(S8)
+3266: uint32_t ulCount = 0U;\r
+BFD089AE 0000F81E SW ZERO, 0(S8)
+3267: \r
+3268: while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )\r
+BFD089B2 CC0B B 0xBFD089CA
+BFD089B4 0C00 NOP
+BFD089CA 0010FC5E LW V0, 16(S8)
+BFD089CE 09A0 LBU V1, 0(V0)
+BFD089D0 00A53040 ADDIU V0, ZERO, 165
+BFD089D4 FFEF9443 BEQ V1, V0, 0xBFD089B6
+BFD089D6 0C00FFEF LW RA, 3072(T7)
+BFD089D8 0C00 NOP
+3269: {\r
+3270: pucStackByte -= portSTACK_GROWTH;\r
+BFD089B6 0010FC5E LW V0, 16(S8)
+BFD089BA 6D20 ADDIU V0, V0, 1
+BFD089BC 0010F85E SW V0, 16(S8)
+3271: ulCount++;\r
+BFD089C0 0000FC5E LW V0, 0(S8)
+BFD089C4 6D20 ADDIU V0, V0, 1
+BFD089C6 0000F85E SW V0, 0(S8)
+3272: }\r
+3273: \r
+3274: ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */\r
+BFD089DA 0000FC5E LW V0, 0(S8)
+BFD089DE 2525 SRL V0, V0, 2
+BFD089E0 0000F85E SW V0, 0(S8)
+3275: \r
+3276: return ( uint16_t ) ulCount;\r
+BFD089E4 0000FC5E LW V0, 0(S8)
+BFD089E8 2D2F ANDI V0, V0, 0xFFFF
+3277: }\r
+BFD089EA 0FBE MOVE SP, S8
+BFD089EC 4BC3 LW S8, 12(SP)
+BFD089EE 4C09 ADDIU SP, SP, 16
+BFD089F0 459F JR16 RA
+BFD089F2 0C00 NOP
+3278: \r
+3279: #endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */\r
+3280: /*-----------------------------------------------------------*/\r
+3281: \r
+3282: #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r
+3283: \r
+3284: UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )\r
+3285: {\r
+BFD08C10 4FED ADDIU SP, SP, -40
+BFD08C12 CBE9 SW RA, 36(SP)
+BFD08C14 CBC8 SW S8, 32(SP)
+BFD08C16 0FDD MOVE S8, SP
+BFD08C18 0028F89E SW A0, 40(S8)
+3286: TCB_t *pxTCB;\r
+3287: uint8_t *pucEndOfStack;\r
+3288: UBaseType_t uxReturn;\r
+3289: \r
+3290: pxTCB = prvGetTCBFromHandle( xTask );\r
+BFD08C1C 0028FC5E LW V0, 40(S8)
+BFD08C20 000440A2 BNEZC V0, 0xBFD08C2C
+BFD08C24 8030FC5C LW V0, -32720(GP)
+BFD08C28 CC03 B 0xBFD08C30
+BFD08C2A 0C00 NOP
+BFD08C2C 0028FC5E LW V0, 40(S8)
+BFD08C30 0010F85E SW V0, 16(S8)
+3291: \r
+3292: #if portSTACK_GROWTH < 0\r
+3293: {\r
+3294: pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;\r
+BFD08C34 0010FC5E LW V0, 16(S8)
+BFD08C36 692C0010 EXT ZERO, S0, 4, 14
+BFD08C38 692C LW V0, 48(V0)
+BFD08C3A 0014F85E SW V0, 20(S8)
+3295: }\r
+3296: #else\r
+3297: {\r
+3298: pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;\r
+3299: }\r
+3300: #endif\r
+3301: \r
+3302: uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );\r
+BFD08C3E 0014FC9E LW A0, 20(S8)
+BFD08C42 44D277E8 JALS prvTaskCheckFreeStackSpace
+BFD08C44 44D2 OR16 V0, V0
+BFD08C46 0C00 NOP
+BFD08C48 0018F85E SW V0, 24(S8)
+3303: \r
+3304: return uxReturn;\r
+BFD08C4C 0018FC5E LW V0, 24(S8)
+3305: }\r
+BFD08C50 0FBE MOVE SP, S8
+BFD08C52 4BE9 LW RA, 36(SP)
+BFD08C54 4BC8 LW S8, 32(SP)
+BFD08C56 4C15 ADDIU SP, SP, 40
+BFD08C58 459F JR16 RA
+BFD08C5A 0C00 NOP
+3306: \r
+3307: #endif /* INCLUDE_uxTaskGetStackHighWaterMark */\r
+3308: /*-----------------------------------------------------------*/\r
+3309: \r
+3310: #if ( INCLUDE_vTaskDelete == 1 )\r
+3311: \r
+3312: static void prvDeleteTCB( TCB_t *pxTCB )\r
+3313: {\r
+BFD098DC 4FF5 ADDIU SP, SP, -24
+BFD098DE CBE5 SW RA, 20(SP)
+BFD098E0 CBC4 SW S8, 16(SP)
+BFD098E2 0FDD MOVE S8, SP
+BFD098E4 0018F89E SW A0, 24(S8)
+3314: /* This call is required specifically for the TriCore port. It must be\r
+3315: above the vPortFree() calls. The call is also used by ports/demos that\r
+3316: want to allocate and clean RAM statically. */\r
+3317: portCLEAN_UP_TCB( pxTCB );\r
+3318: \r
+3319: /* Free up the memory allocated by the scheduler for the task. It is up\r
+3320: to the task to free any memory allocated at the application level. */\r
+3321: #if ( configUSE_NEWLIB_REENTRANT == 1 )\r
+3322: {\r
+3323: _reclaim_reent( &( pxTCB->xNewLib_reent ) );\r
+3324: }\r
+3325: #endif /* configUSE_NEWLIB_REENTRANT */\r
+3326: \r
+3327: #if( portUSING_MPU_WRAPPERS == 1 )\r
+3328: {\r
+3329: /* Only free the stack if it was allocated dynamically in the first\r
+3330: place. */\r
+3331: if( pxTCB->xUsingStaticallyAllocatedStack == pdFALSE )\r
+3332: {\r
+3333: vPortFreeAligned( pxTCB->pxStack );\r
+3334: }\r
+3335: }\r
+3336: #else\r
+3337: {\r
+3338: vPortFreeAligned( pxTCB->pxStack );\r
+BFD098E8 0018FC5E LW V0, 24(S8)
+BFD098EA 692C0018 EXT ZERO, T8, 4, 14
+BFD098EC 692C LW V0, 48(V0)
+BFD098EE 0C82 MOVE A0, V0
+BFD098F0 2FEA77E8 JALS vPortFree
+BFD098F2 2FEA ANDI A3, A2, 0x20
+BFD098F4 0C00 NOP
+3339: }\r
+3340: #endif\r
+3341: \r
+3342: vPortFree( pxTCB );\r
+BFD098F6 0018FC9E LW A0, 24(S8)
+BFD098FA 2FEA77E8 JALS vPortFree
+BFD098FC 2FEA ANDI A3, A2, 0x20
+BFD098FE 0C00 NOP
+3343: }\r
+BFD09900 0FBE MOVE SP, S8
+BFD09902 4BE5 LW RA, 20(SP)
+BFD09904 4BC4 LW S8, 16(SP)
+BFD09906 4C0D ADDIU SP, SP, 24
+BFD09908 459F JR16 RA
+BFD0990A 0C00 NOP
+3344: \r
+3345: #endif /* INCLUDE_vTaskDelete */\r
+3346: /*-----------------------------------------------------------*/\r
+3347: \r
+3348: static void prvResetNextTaskUnblockTime( void )\r
+3349: {\r
+BFD08F94 4FF9 ADDIU SP, SP, -16
+BFD08F96 CBC3 SW S8, 12(SP)
+BFD08F98 0FDD MOVE S8, SP
+3350: TCB_t *pxTCB;\r
+3351: \r
+3352: if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\r
+BFD08F9A 8074FC5C LW V0, -32652(GP)
+BFD08F9E 6920 LW V0, 0(V0)
+BFD08FA0 000340A2 BNEZC V0, 0xBFD08FAA
+BFD08FA4 ED01 LI V0, 1
+BFD08FA6 CC02 B 0xBFD08FAC
+BFD08FA8 0C00 NOP
+BFD08FAA 0C40 MOVE V0, ZERO
+BFD08FAC 000540E2 BEQZC V0, 0xBFD08FBA
+3353: {\r
+3354: /* The new current delayed list is empty. Set xNextTaskUnblockTime to\r
+3355: the maximum possible value so it is extremely unlikely that the\r
+3356: if( xTickCount >= xNextTaskUnblockTime ) test will pass until\r
+3357: there is an item in the delayed list. */\r
+3358: xNextTaskUnblockTime = portMAX_DELAY;\r
+BFD08FB0 ED7F LI V0, -1
+BFD08FB2 8058F85C SW V0, -32680(GP)
+BFD08FB6 CC0C B 0xBFD08FD0
+BFD08FB8 0C00 NOP
+3359: }\r
+3360: else\r
+3361: {\r
+3362: /* The new current delayed list is not empty, get the value of\r
+3363: the item at the head of the delayed list. This is the time at\r
+3364: which the task at the head of the delayed list should be removed\r
+3365: from the Blocked state. */\r
+3366: ( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );\r
+BFD08FBA 8074FC5C LW V0, -32652(GP)
+BFD08FBE 6923 LW V0, 12(V0)
+BFD08FC0 6923 LW V0, 12(V0)
+BFD08FC2 0000F85E SW V0, 0(S8)
+3367: xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xGenericListItem ) );\r
+BFD08FC6 0000FC5E LW V0, 0(S8)
+BFD08FCA 6921 LW V0, 4(V0)
+BFD08FCC 8058F85C SW V0, -32680(GP)
+3368: }\r
+3369: }\r
+BFD08FD0 0FBE MOVE SP, S8
+BFD08FD2 4BC3 LW S8, 12(SP)
+BFD08FD4 4C09 ADDIU SP, SP, 16
+BFD08FD6 459F JR16 RA
+BFD08FD8 0C00 NOP
+3370: /*-----------------------------------------------------------*/\r
+3371: \r
+3372: #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )\r
+3373: \r
+3374: TaskHandle_t xTaskGetCurrentTaskHandle( void )\r
+3375: {\r
+BFD09E04 4FF9 ADDIU SP, SP, -16
+BFD09E06 CBC3 SW S8, 12(SP)
+BFD09E08 0FDD MOVE S8, SP
+3376: TaskHandle_t xReturn;\r
+3377: \r
+3378: /* A critical section is not required as this is not called from\r
+3379: an interrupt and the current TCB will always be the same for any\r
+3380: individual execution thread. */\r
+3381: xReturn = pxCurrentTCB;\r
+BFD09E0A 8030FC5C LW V0, -32720(GP)
+BFD09E0E 0000F85E SW V0, 0(S8)
+3382: \r
+3383: return xReturn;\r
+BFD09E12 0000FC5E LW V0, 0(S8)
+3384: }\r
+BFD09E16 0FBE MOVE SP, S8
+BFD09E18 4BC3 LW S8, 12(SP)
+BFD09E1A 4C09 ADDIU SP, SP, 16
+BFD09E1C 459F JR16 RA
+BFD09E1E 0C00 NOP
+3385: \r
+3386: #endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */\r
+3387: /*-----------------------------------------------------------*/\r
+3388: \r
+3389: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r
+3390: \r
+3391: BaseType_t xTaskGetSchedulerState( void )\r
+3392: {\r
+BFD0951C 4FF9 ADDIU SP, SP, -16
+BFD0951E CBC3 SW S8, 12(SP)
+BFD09520 0FDD MOVE S8, SP
+3393: BaseType_t xReturn;\r
+3394: \r
+3395: if( xSchedulerRunning == pdFALSE )\r
+BFD09522 8044FC5C LW V0, -32700(GP)
+BFD09526 000540A2 BNEZC V0, 0xBFD09534
+3396: {\r
+3397: xReturn = taskSCHEDULER_NOT_STARTED;\r
+BFD0952A ED01 LI V0, 1
+BFD0952C 0000F85E SW V0, 0(S8)
+BFD0952E CC0C0000 INS ZERO, ZERO, 16, 10
+BFD09530 CC0C B 0xBFD0954A
+BFD09532 0C00 NOP
+3398: }\r
+3399: else\r
+3400: {\r
+3401: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
+BFD09534 805CFC5C LW V0, -32676(GP)
+BFD09538 000540A2 BNEZC V0, 0xBFD09546
+3402: {\r
+3403: xReturn = taskSCHEDULER_RUNNING;\r
+BFD0953C ED02 LI V0, 2
+BFD0953E 0000F85E SW V0, 0(S8)
+BFD09542 CC03 B 0xBFD0954A
+BFD09544 0C00 NOP
+3404: }\r
+3405: else\r
+3406: {\r
+3407: xReturn = taskSCHEDULER_SUSPENDED;\r
+BFD09546 0000F81E SW ZERO, 0(S8)
+3408: }\r
+3409: }\r
+3410: \r
+3411: return xReturn;\r
+BFD0954A 0000FC5E LW V0, 0(S8)
+3412: }\r
+BFD0954E 0FBE MOVE SP, S8
+BFD09550 4BC3 LW S8, 12(SP)
+BFD09552 4C09 ADDIU SP, SP, 16
+BFD09554 459F JR16 RA
+BFD09556 0C00 NOP
+3413: \r
+3414: #endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */\r
+3415: /*-----------------------------------------------------------*/\r
+3416: \r
+3417: #if ( configUSE_MUTEXES == 1 )\r
+3418: \r
+3419: void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder )\r
+3420: {\r
+BFD03520 4FF1 ADDIU SP, SP, -32
+BFD03522 CBE7 SW RA, 28(SP)
+BFD03524 CBC6 SW S8, 24(SP)
+BFD03526 0FDD MOVE S8, SP
+BFD03528 0020F89E SW A0, 32(S8)
+3421: TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;\r
+BFD0352C 0020FC5E LW V0, 32(S8)
+BFD03530 0010F85E SW V0, 16(S8)
+3422: \r
+3423: /* If the mutex was given back by an interrupt while the queue was\r
+3424: locked then the mutex holder might now be NULL. */\r
+3425: if( pxMutexHolder != NULL )\r
+BFD03534 0020FC5E LW V0, 32(S8)
+BFD03538 007E40E2 BEQZC V0, 0xBFD03638
+3426: {\r
+3427: /* If the holder of the mutex has a priority below the priority of\r
+3428: the task attempting to obtain the mutex then it will temporarily\r
+3429: inherit the priority of the task attempting to obtain the mutex. */\r
+3430: if( pxTCB->uxPriority < pxCurrentTCB->uxPriority )\r
+BFD0353C 0010FC5E LW V0, 16(S8)
+BFD03540 69AB LW V1, 44(V0)
+BFD03542 8030FC5C LW V0, -32720(GP)
+BFD03546 692B LW V0, 44(V0)
+BFD03548 13900043 SLTU V0, V1, V0
+BFD0354A 40E21390 ADDI GP, S0, 16610
+BFD0354C 007440E2 BEQZC V0, 0xBFD03638
+3431: {\r
+3432: /* Adjust the mutex holder state to account for its new\r
+3433: priority. Only reset the event list item value if the value is\r
+3434: not being used for anything else. */\r
+3435: if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\r
+BFD03550 0010FC5E LW V0, 16(S8)
+BFD03554 6926 LW V0, 24(V0)
+BFD03556 00094002 BLTZ V0, 0xBFD0356C
+BFD03558 0C000009 SLL ZERO, T1, 1
+BFD0355A 0C00 NOP
+3436: {\r
+3437: listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
+BFD0355C 8030FC5C LW V0, -32720(GP)
+BFD03560 692B LW V0, 44(V0)
+BFD03562 ED85 LI V1, 5
+BFD03564 05A7 SUBU V1, V1, V0
+BFD03566 0010FC5E LW V0, 16(S8)
+BFD0356A E9A6 SW V1, 24(V0)
+3438: }\r
+3439: else\r
+3440: {\r
+3441: mtCOVERAGE_TEST_MARKER();\r
+3442: }\r
+3443: \r
+3444: /* If the task being modified is in the ready state it will need\r
+3445: to be moved into a new list. */\r
+3446: if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )\r
+BFD0356C 0010FC5E LW V0, 16(S8)
+BFD0356E 69A50010 LWX T5, 0(S0)
+BFD03570 69A5 LW V1, 20(V0)
+BFD03572 0010FC5E LW V0, 16(S8)
+BFD03576 692B LW V0, 44(V0)
+BFD03578 2524 SLL V0, V0, 2
+BFD0357A 2624 SLL A0, V0, 2
+BFD0357C 0644 ADDU A0, V0, A0
+BFD0357E BFD241A2 LUI V0, 0xBFD2
+BFD03580 3042BFD2 LDC1 F30, 12354(S2)
+BFD03582 806C3042 ADDIU V0, V0, -32660
+BFD03586 0528 ADDU V0, A0, V0
+BFD03588 0004B443 BNE V1, V0, 0xBFD03594
+BFD0358A 0C000004 SLL ZERO, A0, 1
+BFD0358C 0C00 NOP
+BFD0358E ED01 LI V0, 1
+BFD03590 CC02 B 0xBFD03596
+BFD03592 0C00 NOP
+BFD03594 0C40 MOVE V0, ZERO
+BFD03596 004940E2 BEQZC V0, 0xBFD0362C
+3447: {\r
+3448: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
+BFD0359A 0010FC5E LW V0, 16(S8)
+BFD0359E 6D22 ADDIU V0, V0, 4
+BFD035A0 0C82 MOVE A0, V0
+BFD035A2 00C877E8 JALS uxListRemove
+BFD035A4 0C0000C8 SLL A2, T0, 1
+BFD035A6 0C00 NOP
+BFD035A8 001A40A2 BNEZC V0, 0xBFD035E0
+3449: {\r
+3450: taskRESET_READY_PRIORITY( pxTCB->uxPriority );\r
+BFD035AC 0010FC5E LW V0, 16(S8)
+BFD035B0 692B LW V0, 44(V0)
+BFD035B2 2524 SLL V0, V0, 2
+BFD035B4 25A4 SLL V1, V0, 2
+BFD035B6 05B4 ADDU V1, V0, V1
+BFD035B8 BFD241A2 LUI V0, 0xBFD2
+BFD035BA 3042BFD2 LDC1 F30, 12354(S2)
+BFD035BC 806C3042 ADDIU V0, V0, -32660
+BFD035C0 0526 ADDU V0, V1, V0
+BFD035C2 6920 LW V0, 0(V0)
+BFD035C4 000C40A2 BNEZC V0, 0xBFD035E0
+BFD035C8 0010FC5E LW V0, 16(S8)
+BFD035CC 692B LW V0, 44(V0)
+BFD035CE ED81 LI V1, 1
+BFD035D0 10100062 SLLV V0, V0, V1
+BFD035D2 441A1010 ADDI ZERO, S0, 17434
+BFD035D4 441A NOT16 V1, V0
+BFD035D6 8040FC5C LW V0, -32704(GP)
+BFD035DA 4493 AND16 V0, V1
+BFD035DC 8040F85C SW V0, -32704(GP)
+3451: }\r
+3452: else\r
+3453: {\r
+3454: mtCOVERAGE_TEST_MARKER();\r
+3455: }\r
+3456: \r
+3457: /* Inherit the priority before being moved into the new list. */\r
+3458: pxTCB->uxPriority = pxCurrentTCB->uxPriority;\r
+BFD035E0 8030FC5C LW V0, -32720(GP)
+BFD035E4 69AB LW V1, 44(V0)
+BFD035E6 0010FC5E LW V0, 16(S8)
+BFD035EA E9AB SW V1, 44(V0)
+3459: prvAddTaskToReadyList( pxTCB );\r
+BFD035EC 0010FC5E LW V0, 16(S8)
+BFD035F0 692B LW V0, 44(V0)
+BFD035F2 ED81 LI V1, 1
+BFD035F4 18100062 SLLV V1, V0, V1
+BFD035F6 FC5C1810 SB ZERO, -932(S0)
+BFD035F8 8040FC5C LW V0, -32704(GP)
+BFD035FC 44D3 OR16 V0, V1
+BFD035FE 8040F85C SW V0, -32704(GP)
+BFD03602 0010FC5E LW V0, 16(S8)
+BFD03606 692B LW V0, 44(V0)
+BFD03608 2524 SLL V0, V0, 2
+BFD0360A 25A4 SLL V1, V0, 2
+BFD0360C 05B4 ADDU V1, V0, V1
+BFD0360E BFD241A2 LUI V0, 0xBFD2
+BFD03610 3042BFD2 LDC1 F30, 12354(S2)
+BFD03612 806C3042 ADDIU V0, V0, -32660
+BFD03616 05A6 ADDU V1, V1, V0
+BFD03618 0010FC5E LW V0, 16(S8)
+BFD0361C 6D22 ADDIU V0, V0, 4
+BFD0361E 0C83 MOVE A0, V1
+BFD03620 0CA2 MOVE A1, V0
+BFD03622 3E4A77E8 JALS vListInsertEnd
+BFD03624 0C003E4A LH S2, 3072(T2)
+BFD03626 0C00 NOP
+BFD03628 CC07 B 0xBFD03638
+BFD0362A 0C00 NOP
+3460: }\r
+3461: else\r
+3462: {\r
+3463: /* Just inherit the priority. */\r
+3464: pxTCB->uxPriority = pxCurrentTCB->uxPriority;\r
+BFD0362C 8030FC5C LW V0, -32720(GP)
+BFD03630 69AB LW V1, 44(V0)
+BFD03632 0010FC5E LW V0, 16(S8)
+BFD03636 E9AB SW V1, 44(V0)
+3465: }\r
+3466: \r
+3467: traceTASK_PRIORITY_INHERIT( pxTCB, pxCurrentTCB->uxPriority );\r
+3468: }\r
+3469: else\r
+3470: {\r
+3471: mtCOVERAGE_TEST_MARKER();\r
+3472: }\r
+3473: }\r
+3474: else\r
+3475: {\r
+3476: mtCOVERAGE_TEST_MARKER();\r
+3477: }\r
+3478: }\r
+BFD03638 0FBE MOVE SP, S8
+BFD0363A 4BE7 LW RA, 28(SP)
+BFD0363C 4BC6 LW S8, 24(SP)
+BFD0363E 4C11 ADDIU SP, SP, 32
+BFD03640 459F JR16 RA
+BFD03642 0C00 NOP
+3479: \r
+3480: #endif /* configUSE_MUTEXES */\r
+3481: /*-----------------------------------------------------------*/\r
+3482: \r
+3483: #if ( configUSE_MUTEXES == 1 )\r
+3484: \r
+3485: BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )\r
+3486: {\r
+BFD02F04 4FF1 ADDIU SP, SP, -32
+BFD02F06 CBE7 SW RA, 28(SP)
+BFD02F08 CBC6 SW S8, 24(SP)
+BFD02F0A 0FDD MOVE S8, SP
+BFD02F0C 0020F89E SW A0, 32(S8)
+3487: TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;\r
+BFD02F10 0020FC5E LW V0, 32(S8)
+BFD02F14 0014F85E SW V0, 20(S8)
+3488: BaseType_t xReturn = pdFALSE;\r
+BFD02F18 0010F81E SW ZERO, 16(S8)
+3489: \r
+3490: if( pxMutexHolder != NULL )\r
+BFD02F1C 0020FC5E LW V0, 32(S8)
+BFD02F20 008B40E2 BEQZC V0, 0xBFD0303A
+3491: {\r
+3492: /* A task can only have an inherited priority if it holds the mutex.\r
+3493: If the mutex is held by a task then it cannot be given from an\r
+3494: interrupt, and if a mutex is given by the holding task then it must\r
+3495: be the running state task. */\r
+3496: configASSERT( pxTCB == pxCurrentTCB );\r
+BFD02F24 8030FC5C LW V0, -32720(GP)
+BFD02F28 0014FC7E LW V1, 20(S8)
+BFD02F2C 000A9443 BEQ V1, V0, 0xBFD02F44
+BFD02F2E 0C00000A SLL ZERO, T2, 1
+BFD02F30 0C00 NOP
+BFD02F32 BFD141A2 LUI V0, 0xBFD1
+BFD02F34 3082BFD1 LDC1 F30, 12418(S1)
+BFD02F36 98103082 ADDIU A0, V0, -26608
+BFD02F38 30A09810 SWC1 F0, 12448(S0)
+BFD02F3A 0DA830A0 ADDIU A1, ZERO, 3496
+BFD02F3C 0DA8 MOVE T5, T0
+BFD02F3E 4B7E77E8 JALS vAssertCalled
+BFD02F40 4B7E LW K1, 120(SP)
+BFD02F42 0C00 NOP
+3497: \r
+3498: configASSERT( pxTCB->uxMutexesHeld );\r
+BFD02F44 0014FC5E LW V0, 20(S8)
+BFD02F48 0044FC42 LW V0, 68(V0)
+BFD02F4C 000940A2 BNEZC V0, 0xBFD02F62
+BFD02F50 BFD141A2 LUI V0, 0xBFD1
+BFD02F52 3082BFD1 LDC1 F30, 12418(S1)
+BFD02F54 98103082 ADDIU A0, V0, -26608
+BFD02F56 30A09810 SWC1 F0, 12448(S0)
+BFD02F58 0DAA30A0 ADDIU A1, ZERO, 3498
+BFD02F5A 0DAA MOVE T5, T2
+BFD02F5C 4B7E77E8 JALS vAssertCalled
+BFD02F5E 4B7E LW K1, 120(SP)
+BFD02F60 0C00 NOP
+3499: ( pxTCB->uxMutexesHeld )--;\r
+BFD02F62 0014FC5E LW V0, 20(S8)
+BFD02F66 0044FC42 LW V0, 68(V0)
+BFD02F6A 6DAE ADDIU V1, V0, -1
+BFD02F6C 0014FC5E LW V0, 20(S8)
+BFD02F70 0044F862 SW V1, 68(V0)
+3500: \r
+3501: /* Has the holder of the mutex inherited the priority of another\r
+3502: task? */\r
+3503: if( pxTCB->uxPriority != pxTCB->uxBasePriority )\r
+BFD02F74 0014FC5E LW V0, 20(S8)
+BFD02F78 69AB LW V1, 44(V0)
+BFD02F7A 0014FC5E LW V0, 20(S8)
+BFD02F7E 0040FC42 LW V0, 64(V0)
+BFD02F82 005A9443 BEQ V1, V0, 0xBFD0303A
+BFD02F84 0C00005A SLL V0, K0, 1
+BFD02F86 0C00 NOP
+3504: {\r
+3505: /* Only disinherit if no other mutexes are held. */\r
+3506: if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )\r
+BFD02F88 0014FC5E LW V0, 20(S8)
+BFD02F8C 0044FC42 LW V0, 68(V0)
+BFD02F90 005340A2 BNEZC V0, 0xBFD0303A
+3507: {\r
+3508: /* A task can only have an inherited priority if it holds\r
+3509: the mutex. If the mutex is held by a task then it cannot be\r
+3510: given from an interrupt, and if a mutex is given by the\r
+3511: holding task then it must be the running state task. Remove\r
+3512: the holding task from the ready list. */\r
+3513: if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
+BFD02F94 0014FC5E LW V0, 20(S8)
+BFD02F98 6D22 ADDIU V0, V0, 4
+BFD02F9A 0C82 MOVE A0, V0
+BFD02F9C 00C877E8 JALS uxListRemove
+BFD02F9E 0C0000C8 SLL A2, T0, 1
+BFD02FA0 0C00 NOP
+BFD02FA2 001A40A2 BNEZC V0, 0xBFD02FDA
+3514: {\r
+3515: taskRESET_READY_PRIORITY( pxTCB->uxPriority );\r
+BFD02FA6 0014FC5E LW V0, 20(S8)
+BFD02FAA 692B LW V0, 44(V0)
+BFD02FAC 2524 SLL V0, V0, 2
+BFD02FAE 25A4 SLL V1, V0, 2
+BFD02FB0 05B4 ADDU V1, V0, V1
+BFD02FB2 BFD241A2 LUI V0, 0xBFD2
+BFD02FB4 3042BFD2 LDC1 F30, 12354(S2)
+BFD02FB6 806C3042 ADDIU V0, V0, -32660
+BFD02FBA 0526 ADDU V0, V1, V0
+BFD02FBC 6920 LW V0, 0(V0)
+BFD02FBE 000C40A2 BNEZC V0, 0xBFD02FDA
+BFD02FC2 0014FC5E LW V0, 20(S8)
+BFD02FC6 692B LW V0, 44(V0)
+BFD02FC8 ED81 LI V1, 1
+BFD02FCA 10100062 SLLV V0, V0, V1
+BFD02FCC 441A1010 ADDI ZERO, S0, 17434
+BFD02FCE 441A NOT16 V1, V0
+BFD02FD0 8040FC5C LW V0, -32704(GP)
+BFD02FD4 4493 AND16 V0, V1
+BFD02FD6 8040F85C SW V0, -32704(GP)
+3516: }\r
+3517: else\r
+3518: {\r
+3519: mtCOVERAGE_TEST_MARKER();\r
+3520: }\r
+3521: \r
+3522: /* Disinherit the priority before adding the task into the\r
+3523: new ready list. */\r
+3524: traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );\r
+3525: pxTCB->uxPriority = pxTCB->uxBasePriority;\r
+BFD02FDA 0014FC5E LW V0, 20(S8)
+BFD02FDE 0040FC62 LW V1, 64(V0)
+BFD02FE2 0014FC5E LW V0, 20(S8)
+BFD02FE6 E9AB SW V1, 44(V0)
+3526: \r
+3527: /* Reset the event list item value. It cannot be in use for\r
+3528: any other purpose if this task is running, and it must be\r
+3529: running to give back the mutex. */\r
+3530: listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
+BFD02FE8 0014FC5E LW V0, 20(S8)
+BFD02FEC 692B LW V0, 44(V0)
+BFD02FEE ED85 LI V1, 5
+BFD02FF0 05A7 SUBU V1, V1, V0
+BFD02FF2 0014FC5E LW V0, 20(S8)
+BFD02FF6 E9A6 SW V1, 24(V0)
+3531: prvAddTaskToReadyList( pxTCB );\r
+BFD02FF8 0014FC5E LW V0, 20(S8)
+BFD02FFC 692B LW V0, 44(V0)
+BFD02FFE ED81 LI V1, 1
+BFD03000 18100062 SLLV V1, V0, V1
+BFD03002 FC5C1810 SB ZERO, -932(S0)
+BFD03004 8040FC5C LW V0, -32704(GP)
+BFD03008 44D3 OR16 V0, V1
+BFD0300A 8040F85C SW V0, -32704(GP)
+BFD0300E 0014FC5E LW V0, 20(S8)
+BFD03012 692B LW V0, 44(V0)
+BFD03014 2524 SLL V0, V0, 2
+BFD03016 25A4 SLL V1, V0, 2
+BFD03018 05B4 ADDU V1, V0, V1
+BFD0301A BFD241A2 LUI V0, 0xBFD2
+BFD0301C 3042BFD2 LDC1 F30, 12354(S2)
+BFD0301E 806C3042 ADDIU V0, V0, -32660
+BFD03022 05A6 ADDU V1, V1, V0
+BFD03024 0014FC5E LW V0, 20(S8)
+BFD03028 6D22 ADDIU V0, V0, 4
+BFD0302A 0C83 MOVE A0, V1
+BFD0302C 0CA2 MOVE A1, V0
+BFD0302E 3E4A77E8 JALS vListInsertEnd
+BFD03030 0C003E4A LH S2, 3072(T2)
+BFD03032 0C00 NOP
+3532: \r
+3533: /* Return true to indicate that a context switch is required.\r
+3534: This is only actually required in the corner case whereby\r
+3535: multiple mutexes were held and the mutexes were given back\r
+3536: in an order different to that in which they were taken.\r
+3537: If a context switch did not occur when the first mutex was\r
+3538: returned, even if a task was waiting on it, then a context\r
+3539: switch should occur when the last mutex is returned whether\r
+3540: a task is waiting on it or not. */\r
+3541: xReturn = pdTRUE;\r
+BFD03034 ED01 LI V0, 1
+BFD03036 0010F85E SW V0, 16(S8)
+3542: }\r
+3543: else\r
+3544: {\r
+3545: mtCOVERAGE_TEST_MARKER();\r
+3546: }\r
+3547: }\r
+3548: else\r
+3549: {\r
+3550: mtCOVERAGE_TEST_MARKER();\r
+3551: }\r
+3552: }\r
+3553: else\r
+3554: {\r
+3555: mtCOVERAGE_TEST_MARKER();\r
+3556: }\r
+3557: \r
+3558: return xReturn;\r
+BFD0303A 0010FC5E LW V0, 16(S8)
+3559: }\r
+BFD0303E 0FBE MOVE SP, S8
+BFD03040 4BE7 LW RA, 28(SP)
+BFD03042 4BC6 LW S8, 24(SP)
+BFD03044 4C11 ADDIU SP, SP, 32
+BFD03046 459F JR16 RA
+BFD03048 0C00 NOP
+3560: \r
+3561: #endif /* configUSE_MUTEXES */\r
+3562: /*-----------------------------------------------------------*/\r
+3563: \r
+3564: #if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
+3565: \r
+3566: void vTaskEnterCritical( void )\r
+3567: {\r
+BFD06770 4FF1 ADDIU SP, SP, -32
+BFD06772 CBE7 SW RA, 28(SP)
+BFD06774 CBC6 SW S8, 24(SP)
+BFD06776 0FDD MOVE S8, SP
+3568: portDISABLE_INTERRUPTS();\r
+BFD06778 4E3677E8 JALS ulPortGetCP0Status
+BFD0677A 4E36 ADDIU S1, S1, -5
+BFD0677C 0C00 NOP
+BFD0677E 0010F85E SW V0, 16(S8)
+BFD06782 0010FC7E LW V1, 16(S8)
+BFD06786 000141A2 LUI V0, 0x1
+BFD0678A FC005042 ORI V0, V0, -1024
+BFD0678C 4493FC00 LW ZERO, 17555(ZERO)
+BFD0678E 4493 AND16 V0, V1
+BFD06790 50400042 SRL V0, V0, 10
+BFD06792 B0425040 ORI V0, ZERO, -20414
+BFD06794 0003B042 SLTIU V0, V0, 3
+BFD06798 001140E2 BEQZC V0, 0xBFD067BE
+BFD0679C 0010FC7E LW V1, 16(S8)
+BFD067A0 FFFE41A2 LUI V0, 0xFFFE
+BFD067A2 5042FFFE LW RA, 20546(S8)
+BFD067A4 03FF5042 ORI V0, V0, 1023
+BFD067A8 4493 AND16 V0, V1
+BFD067AA 0010F85E SW V0, 16(S8)
+BFD067AE 0010FC5E LW V0, 16(S8)
+BFD067B2 0C005042 ORI V0, V0, 3072
+BFD067B4 0C00 NOP
+BFD067B6 0C82 MOVE A0, V0
+BFD067B8 4E4677E8 JALS vPortSetCP0Status
+BFD067BA 4E46 ADDIU S2, S2, 3
+BFD067BC 0C00 NOP
+3569: \r
+3570: if( xSchedulerRunning != pdFALSE )\r
+BFD067BE 8044FC5C LW V0, -32700(GP)
+BFD067C2 001940E2 BEQZC V0, 0xBFD067F8
+3571: {\r
+3572: ( pxCurrentTCB->uxCriticalNesting )++;\r
+BFD067C6 8030FC5C LW V0, -32720(GP)
+BFD067CA 69AF LW V1, 60(V0)
+BFD067CC 6DB0 ADDIU V1, V1, 1
+BFD067CE E9AF SW V1, 60(V0)
+3573: \r
+3574: /* This is not the interrupt safe version of the enter critical\r
+3575: function so assert() if it is being called from an interrupt\r
+3576: context. Only API functions that end in "FromISR" can be used in an\r
+3577: interrupt. Only assert if the critical nesting count is 1 to\r
+3578: protect against recursive calls if the assert function also uses a\r
+3579: critical section. */\r
+3580: if( pxCurrentTCB->uxCriticalNesting == 1 )\r
+BFD067D0 8030FC5C LW V0, -32720(GP)
+BFD067D4 69AF LW V1, 60(V0)
+BFD067D6 ED01 LI V0, 1
+BFD067D8 000EB443 BNE V1, V0, 0xBFD067F8
+BFD067DA 0C00000E SLL ZERO, T6, 1
+BFD067DC 0C00 NOP
+3581: {\r
+3582: portASSERT_IF_IN_ISR();\r
+BFD067DE 8014FC5C LW V0, -32748(GP)
+BFD067E2 000940E2 BEQZC V0, 0xBFD067F8
+BFD067E6 BFD141A2 LUI V0, 0xBFD1
+BFD067E8 3082BFD1 LDC1 F30, 12418(S1)
+BFD067EA 98103082 ADDIU A0, V0, -26608
+BFD067EC 30A09810 SWC1 F0, 12448(S0)
+BFD067EE 0DFE30A0 ADDIU A1, ZERO, 3582
+BFD067F0 0DFE MOVE T7, S8
+BFD067F2 4B7E77E8 JALS vAssertCalled
+BFD067F4 4B7E LW K1, 120(SP)
+BFD067F6 0C00 NOP
+3583: }\r
+3584: \r
+3585: }\r
+3586: else\r
+3587: {\r
+3588: mtCOVERAGE_TEST_MARKER();\r
+3589: }\r
+3590: }\r
+BFD067F8 0FBE MOVE SP, S8
+BFD067FA 4BE7 LW RA, 28(SP)
+BFD067FC 4BC6 LW S8, 24(SP)
+BFD067FE 4C11 ADDIU SP, SP, 32
+BFD06800 459F JR16 RA
+BFD06802 0C00 NOP
+3591: \r
+3592: #endif /* portCRITICAL_NESTING_IN_TCB */\r
+3593: /*-----------------------------------------------------------*/\r
+3594: \r
+3595: #if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
+3596: \r
+3597: void vTaskExitCritical( void )\r
+3598: {\r
+BFD08154 4FF1 ADDIU SP, SP, -32
+BFD08156 CBE7 SW RA, 28(SP)
+BFD08158 CBC6 SW S8, 24(SP)
+BFD0815A 0FDD MOVE S8, SP
+3599: if( xSchedulerRunning != pdFALSE )\r
+BFD0815C 8044FC5C LW V0, -32700(GP)
+BFD08160 002240E2 BEQZC V0, 0xBFD081A8
+3600: {\r
+3601: if( pxCurrentTCB->uxCriticalNesting > 0U )\r
+BFD08164 8030FC5C LW V0, -32720(GP)
+BFD08168 692F LW V0, 60(V0)
+BFD0816A 001D40E2 BEQZC V0, 0xBFD081A8
+3602: {\r
+3603: ( pxCurrentTCB->uxCriticalNesting )--;\r
+BFD0816E 8030FC5C LW V0, -32720(GP)
+BFD08172 69AF LW V1, 60(V0)
+BFD08174 6DBE ADDIU V1, V1, -1
+BFD08176 E9AF SW V1, 60(V0)
+3604: \r
+3605: if( pxCurrentTCB->uxCriticalNesting == 0U )\r
+BFD08178 8030FC5C LW V0, -32720(GP)
+BFD0817C 692F LW V0, 60(V0)
+BFD0817E 001340A2 BNEZC V0, 0xBFD081A8
+3606: {\r
+3607: portENABLE_INTERRUPTS();\r
+BFD08182 4E3677E8 JALS ulPortGetCP0Status
+BFD08184 4E36 ADDIU S1, S1, -5
+BFD08186 0C00 NOP
+BFD08188 0010F85E SW V0, 16(S8)
+BFD0818C 0010FC7E LW V1, 16(S8)
+BFD08190 FFFE41A2 LUI V0, 0xFFFE
+BFD08192 5042FFFE LW RA, 20546(S8)
+BFD08194 03FF5042 ORI V0, V0, 1023
+BFD08198 4493 AND16 V0, V1
+BFD0819A 0010F85E SW V0, 16(S8)
+BFD0819E 0010FC9E LW A0, 16(S8)
+BFD081A2 4E4677E8 JALS vPortSetCP0Status
+BFD081A4 4E46 ADDIU S2, S2, 3
+BFD081A6 0C00 NOP
+3608: }\r
+3609: else\r
+3610: {\r
+3611: mtCOVERAGE_TEST_MARKER();\r
+3612: }\r
+3613: }\r
+3614: else\r
+3615: {\r
+3616: mtCOVERAGE_TEST_MARKER();\r
+3617: }\r
+3618: }\r
+3619: else\r
+3620: {\r
+3621: mtCOVERAGE_TEST_MARKER();\r
+3622: }\r
+3623: }\r
+BFD081A8 0FBE MOVE SP, S8
+BFD081AA 4BE7 LW RA, 28(SP)
+BFD081AC 4BC6 LW S8, 24(SP)
+BFD081AE 4C11 ADDIU SP, SP, 32
+BFD081B0 459F JR16 RA
+BFD081B2 0C00 NOP
+3624: \r
+3625: #endif /* portCRITICAL_NESTING_IN_TCB */\r
+3626: /*-----------------------------------------------------------*/\r
+3627: \r
+3628: #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\r
+3629: \r
+3630: static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )\r
+3631: {\r
+3632: BaseType_t x;\r
+3633: \r
+3634: /* Start by copying the entire string. */\r
+3635: strcpy( pcBuffer, pcTaskName );\r
+3636: \r
+3637: /* Pad the end of the string with spaces to ensure columns line up when\r
+3638: printed out. */\r
+3639: for( x = strlen( pcBuffer ); x < ( configMAX_TASK_NAME_LEN - 1 ); x++ )\r
+3640: {\r
+3641: pcBuffer[ x ] = ' ';\r
+3642: }\r
+3643: \r
+3644: /* Terminate. */\r
+3645: pcBuffer[ x ] = 0x00;\r
+3646: \r
+3647: /* Return the new end of string. */\r
+3648: return &( pcBuffer[ x ] );\r
+3649: }\r
+3650: \r
+3651: #endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */\r
+3652: /*-----------------------------------------------------------*/\r
+3653: \r
+3654: #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\r
+3655: \r
+3656: void vTaskList( char * pcWriteBuffer )\r
+3657: {\r
+3658: TaskStatus_t *pxTaskStatusArray;\r
+3659: volatile UBaseType_t uxArraySize, x;\r
+3660: char cStatus;\r
+3661: \r
+3662: /*\r
+3663: * PLEASE NOTE:\r
+3664: *\r
+3665: * This function is provided for convenience only, and is used by many\r
+3666: * of the demo applications. Do not consider it to be part of the\r
+3667: * scheduler.\r
+3668: *\r
+3669: * vTaskList() calls uxTaskGetSystemState(), then formats part of the\r
+3670: * uxTaskGetSystemState() output into a human readable table that\r
+3671: * displays task names, states and stack usage.\r
+3672: *\r
+3673: * vTaskList() has a dependency on the sprintf() C library function that\r
+3674: * might bloat the code size, use a lot of stack, and provide different\r
+3675: * results on different platforms. An alternative, tiny, third party,\r
+3676: * and limited functionality implementation of sprintf() is provided in\r
+3677: * many of the FreeRTOS/Demo sub-directories in a file called\r
+3678: * printf-stdarg.c (note printf-stdarg.c does not provide a full\r
+3679: * snprintf() implementation!).\r
+3680: *\r
+3681: * It is recommended that production systems call uxTaskGetSystemState()\r
+3682: * directly to get access to raw stats data, rather than indirectly\r
+3683: * through a call to vTaskList().\r
+3684: */\r
+3685: \r
+3686: \r
+3687: /* Make sure the write buffer does not contain a string. */\r
+3688: *pcWriteBuffer = 0x00;\r
+3689: \r
+3690: /* Take a snapshot of the number of tasks in case it changes while this\r
+3691: function is executing. */\r
+3692: uxArraySize = uxCurrentNumberOfTasks;\r
+3693: \r
+3694: /* Allocate an array index for each task. */\r
+3695: pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );\r
+3696: \r
+3697: if( pxTaskStatusArray != NULL )\r
+3698: {\r
+3699: /* Generate the (binary) data. */\r
+3700: uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );\r
+3701: \r
+3702: /* Create a human readable table from the binary data. */\r
+3703: for( x = 0; x < uxArraySize; x++ )\r
+3704: {\r
+3705: switch( pxTaskStatusArray[ x ].eCurrentState )\r
+3706: {\r
+3707: case eReady: cStatus = tskREADY_CHAR;\r
+3708: break;\r
+3709: \r
+3710: case eBlocked: cStatus = tskBLOCKED_CHAR;\r
+3711: break;\r
+3712: \r
+3713: case eSuspended: cStatus = tskSUSPENDED_CHAR;\r
+3714: break;\r
+3715: \r
+3716: case eDeleted: cStatus = tskDELETED_CHAR;\r
+3717: break;\r
+3718: \r
+3719: default: /* Should not get here, but it is included\r
+3720: to prevent static checking errors. */\r
+3721: cStatus = 0x00;\r
+3722: break;\r
+3723: }\r
+3724: \r
+3725: /* Write the task name to the string, padding with spaces so it\r
+3726: can be printed in tabular form more easily. */\r
+3727: pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );\r
+3728: \r
+3729: /* Write the rest of the string. */\r
+3730: sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );\r
+3731: pcWriteBuffer += strlen( pcWriteBuffer );\r
+3732: }\r
+3733: \r
+3734: /* Free the array again. */\r
+3735: vPortFree( pxTaskStatusArray );\r
+3736: }\r
+3737: else\r
+3738: {\r
+3739: mtCOVERAGE_TEST_MARKER();\r
+3740: }\r
+3741: }\r
+3742: \r
+3743: #endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */\r
+3744: /*----------------------------------------------------------*/\r
+3745: \r
+3746: #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\r
+3747: \r
+3748: void vTaskGetRunTimeStats( char *pcWriteBuffer )\r
+3749: {\r
+3750: TaskStatus_t *pxTaskStatusArray;\r
+3751: volatile UBaseType_t uxArraySize, x;\r
+3752: uint32_t ulTotalTime, ulStatsAsPercentage;\r
+3753: \r
+3754: #if( configUSE_TRACE_FACILITY != 1 )\r
+3755: {\r
+3756: #error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().\r
+3757: }\r
+3758: #endif\r
+3759: \r
+3760: /*\r
+3761: * PLEASE NOTE:\r
+3762: *\r
+3763: * This function is provided for convenience only, and is used by many\r
+3764: * of the demo applications. Do not consider it to be part of the\r
+3765: * scheduler.\r
+3766: *\r
+3767: * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part\r
+3768: * of the uxTaskGetSystemState() output into a human readable table that\r
+3769: * displays the amount of time each task has spent in the Running state\r
+3770: * in both absolute and percentage terms.\r
+3771: *\r
+3772: * vTaskGetRunTimeStats() has a dependency on the sprintf() C library\r
+3773: * function that might bloat the code size, use a lot of stack, and\r
+3774: * provide different results on different platforms. An alternative,\r
+3775: * tiny, third party, and limited functionality implementation of\r
+3776: * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in\r
+3777: * a file called printf-stdarg.c (note printf-stdarg.c does not provide\r
+3778: * a full snprintf() implementation!).\r
+3779: *\r
+3780: * It is recommended that production systems call uxTaskGetSystemState()\r
+3781: * directly to get access to raw stats data, rather than indirectly\r
+3782: * through a call to vTaskGetRunTimeStats().\r
+3783: */\r
+3784: \r
+3785: /* Make sure the write buffer does not contain a string. */\r
+3786: *pcWriteBuffer = 0x00;\r
+3787: \r
+3788: /* Take a snapshot of the number of tasks in case it changes while this\r
+3789: function is executing. */\r
+3790: uxArraySize = uxCurrentNumberOfTasks;\r
+3791: \r
+3792: /* Allocate an array index for each task. */\r
+3793: pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );\r
+3794: \r
+3795: if( pxTaskStatusArray != NULL )\r
+3796: {\r
+3797: /* Generate the (binary) data. */\r
+3798: uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );\r
+3799: \r
+3800: /* For percentage calculations. */\r
+3801: ulTotalTime /= 100UL;\r
+3802: \r
+3803: /* Avoid divide by zero errors. */\r
+3804: if( ulTotalTime > 0 )\r
+3805: {\r
+3806: /* Create a human readable table from the binary data. */\r
+3807: for( x = 0; x < uxArraySize; x++ )\r
+3808: {\r
+3809: /* What percentage of the total run time has the task used?\r
+3810: This will always be rounded down to the nearest integer.\r
+3811: ulTotalRunTimeDiv100 has already been divided by 100. */\r
+3812: ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;\r
+3813: \r
+3814: /* Write the task name to the string, padding with\r
+3815: spaces so it can be printed in tabular form more\r
+3816: easily. */\r
+3817: pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );\r
+3818: \r
+3819: if( ulStatsAsPercentage > 0UL )\r
+3820: {\r
+3821: #ifdef portLU_PRINTF_SPECIFIER_REQUIRED\r
+3822: {\r
+3823: sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );\r
+3824: }\r
+3825: #else\r
+3826: {\r
+3827: /* sizeof( int ) == sizeof( long ) so a smaller\r
+3828: printf() library can be used. */\r
+3829: sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );\r
+3830: }\r
+3831: #endif\r
+3832: }\r
+3833: else\r
+3834: {\r
+3835: /* If the percentage is zero here then the task has\r
+3836: consumed less than 1% of the total run time. */\r
+3837: #ifdef portLU_PRINTF_SPECIFIER_REQUIRED\r
+3838: {\r
+3839: sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );\r
+3840: }\r
+3841: #else\r
+3842: {\r
+3843: /* sizeof( int ) == sizeof( long ) so a smaller\r
+3844: printf() library can be used. */\r
+3845: sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );\r
+3846: }\r
+3847: #endif\r
+3848: }\r
+3849: \r
+3850: pcWriteBuffer += strlen( pcWriteBuffer );\r
+3851: }\r
+3852: }\r
+3853: else\r
+3854: {\r
+3855: mtCOVERAGE_TEST_MARKER();\r
+3856: }\r
+3857: \r
+3858: /* Free the array again. */\r
+3859: vPortFree( pxTaskStatusArray );\r
+3860: }\r
+3861: else\r
+3862: {\r
+3863: mtCOVERAGE_TEST_MARKER();\r
+3864: }\r
+3865: }\r
+3866: \r
+3867: #endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */\r
+3868: /*-----------------------------------------------------------*/\r
+3869: \r
+3870: TickType_t uxTaskResetEventItemValue( void )\r
+3871: {\r
+BFD0990C 4FF9 ADDIU SP, SP, -16
+BFD0990E CBC3 SW S8, 12(SP)
+BFD09910 0FDD MOVE S8, SP
+3872: TickType_t uxReturn;\r
+3873: \r
+3874: uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );\r
+BFD09912 8030FC5C LW V0, -32720(GP)
+BFD09916 6926 LW V0, 24(V0)
+BFD09918 0000F85E SW V0, 0(S8)
+3875: \r
+3876: /* Reset the event list item to its normal value - so it can be used with\r
+3877: queues and semaphores. */\r
+3878: listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
+BFD0991C 8030FC5C LW V0, -32720(GP)
+BFD09920 8030FC7C LW V1, -32720(GP)
+BFD09924 69BB LW V1, 44(V1)
+BFD09926 EE05 LI A0, 5
+BFD09928 05B9 SUBU V1, A0, V1
+BFD0992A E9A6 SW V1, 24(V0)
+3879: \r
+3880: return uxReturn;\r
+BFD0992C 0000FC5E LW V0, 0(S8)
+3881: }\r
+BFD09930 0FBE MOVE SP, S8
+BFD09932 4BC3 LW S8, 12(SP)
+BFD09934 4C09 ADDIU SP, SP, 16
+BFD09936 459F JR16 RA
+BFD09938 0C00 NOP
+3882: /*-----------------------------------------------------------*/\r
+3883: \r
+3884: #if ( configUSE_MUTEXES == 1 )\r
+3885: \r
+3886: void *pvTaskIncrementMutexHeldCount( void )\r
+3887: {\r
+BFD099C0 4FB0 ADDIU SP, SP, -8
+BFD099C2 CBC1 SW S8, 4(SP)
+BFD099C4 0FDD MOVE S8, SP
+3888: /* If xSemaphoreCreateMutex() is called before any tasks have been created\r
+3889: then pxCurrentTCB will be NULL. */\r
+3890: if( pxCurrentTCB != NULL )\r
+BFD099C6 8030FC5C LW V0, -32720(GP)
+BFD099CA 000740E2 BEQZC V0, 0xBFD099DC
+3891: {\r
+3892: ( pxCurrentTCB->uxMutexesHeld )++;\r
+BFD099CE 8030FC5C LW V0, -32720(GP)
+BFD099D2 0044FC62 LW V1, 68(V0)
+BFD099D6 6DB0 ADDIU V1, V1, 1
+BFD099D8 0044F862 SW V1, 68(V0)
+3893: }\r
+3894: \r
+3895: return pxCurrentTCB;\r
+BFD099DC 8030FC5C LW V0, -32720(GP)
+3896: }\r
+BFD099E0 0FBE MOVE SP, S8
+BFD099E2 4BC1 LW S8, 4(SP)
+BFD099E4 4C05 ADDIU SP, SP, 8
+BFD099E6 459F JR16 RA
+BFD099E8 0C00 NOP
+3897: \r
+3898: #endif /* configUSE_MUTEXES */\r
+3899: /*-----------------------------------------------------------*/\r
+3900: \r
+3901: #if( configUSE_TASK_NOTIFICATIONS == 1 )\r
+3902: \r
+3903: uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )\r
+3904: {\r
+BFD039AC 4FED ADDIU SP, SP, -40
+BFD039AE CBE9 SW RA, 36(SP)
+BFD039B0 CBC8 SW S8, 32(SP)
+BFD039B2 0FDD MOVE S8, SP
+BFD039B4 0028F89E SW A0, 40(S8)
+BFD039B8 002CF8BE SW A1, 44(S8)
+3905: TickType_t xTimeToWake;\r
+3906: uint32_t ulReturn;\r
+3907: \r
+3908: taskENTER_CRITICAL();\r
+BFD039BC 33B877E8 JALS vTaskEnterCritical
+BFD039BE 0C0033B8 ADDIU SP, T8, 3072
+BFD039C0 0C00 NOP
+3909: {\r
+3910: /* Only block if the notification count is not already non-zero. */\r
+3911: if( pxCurrentTCB->ulNotifiedValue == 0UL )\r
+BFD039C2 8030FC5C LW V0, -32720(GP)
+BFD039C6 0048FC42 LW V0, 72(V0)
+BFD039CA 004D40A2 BNEZC V0, 0xBFD03A68
+3912: {\r
+3913: /* Mark this task as waiting for a notification. */\r
+3914: pxCurrentTCB->eNotifyState = eWaitingNotification;\r
+BFD039CE 8030FC5C LW V0, -32720(GP)
+BFD039D2 ED81 LI V1, 1
+BFD039D4 004CF862 SW V1, 76(V0)
+3915: \r
+3916: if( xTicksToWait > ( TickType_t ) 0 )\r
+BFD039D8 002CFC5E LW V0, 44(S8)
+BFD039DC 004440E2 BEQZC V0, 0xBFD03A68
+3917: {\r
+3918: /* The task is going to block. First it must be removed\r
+3919: from the ready list. */\r
+3920: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
+BFD039E0 8030FC5C LW V0, -32720(GP)
+BFD039E4 6D22 ADDIU V0, V0, 4
+BFD039E6 0C82 MOVE A0, V0
+BFD039E8 00C877E8 JALS uxListRemove
+BFD039EA 0C0000C8 SLL A2, T0, 1
+BFD039EC 0C00 NOP
+BFD039EE 000C40A2 BNEZC V0, 0xBFD03A0A
+3921: {\r
+3922: /* The current task must be in a ready list, so there is\r
+3923: no need to check, and the port reset macro can be called\r
+3924: directly. */\r
+3925: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
+BFD039F2 8030FC5C LW V0, -32720(GP)
+BFD039F6 692B LW V0, 44(V0)
+BFD039F8 ED81 LI V1, 1
+BFD039FA 10100062 SLLV V0, V0, V1
+BFD039FC 441A1010 ADDI ZERO, S0, 17434
+BFD039FE 441A NOT16 V1, V0
+BFD03A00 8040FC5C LW V0, -32704(GP)
+BFD03A04 4493 AND16 V0, V1
+BFD03A06 8040F85C SW V0, -32704(GP)
+3926: }\r
+3927: else\r
+3928: {\r
+3929: mtCOVERAGE_TEST_MARKER();\r
+3930: }\r
+3931: \r
+3932: #if ( INCLUDE_vTaskSuspend == 1 )\r
+3933: {\r
+3934: if( xTicksToWait == portMAX_DELAY )\r
+BFD03A0A 002CFC7E LW V1, 44(S8)
+BFD03A0E ED7F LI V0, -1
+BFD03A10 000EB443 BNE V1, V0, 0xBFD03A30
+BFD03A12 0C00000E SLL ZERO, T6, 1
+BFD03A14 0C00 NOP
+3935: {\r
+3936: /* Add the task to the suspended task list instead\r
+3937: of a delayed task list to ensure the task is not\r
+3938: woken by a timing event. It will block\r
+3939: indefinitely. */\r
+3940: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
+BFD03A16 8030FC5C LW V0, -32720(GP)
+BFD03A1A 6D22 ADDIU V0, V0, 4
+BFD03A1C BFD241A3 LUI V1, 0xBFD2
+BFD03A1E 3083BFD2 LDC1 F30, 12419(S2)
+BFD03A20 80E43083 ADDIU A0, V1, -32540
+BFD03A24 0CA2 MOVE A1, V0
+BFD03A26 3E4A77E8 JALS vListInsertEnd
+BFD03A28 0C003E4A LH S2, 3072(T2)
+BFD03A2A 0C00 NOP
+BFD03A2C CC0D B 0xBFD03A48
+BFD03A2E 0C00 NOP
+3941: }\r
+3942: else\r
+3943: {\r
+3944: /* Calculate the time at which the task should be\r
+3945: woken if no notification events occur. This may\r
+3946: overflow but this doesn't matter, the scheduler will\r
+3947: handle it. */\r
+3948: xTimeToWake = xTickCount + xTicksToWait;\r
+BFD03A30 803CFC7C LW V1, -32708(GP)
+BFD03A34 002CFC5E LW V0, 44(S8)
+BFD03A38 0526 ADDU V0, V1, V0
+BFD03A3A 0010F85E SW V0, 16(S8)
+3949: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+BFD03A3E 0010FC9E LW A0, 16(S8)
+BFD03A42 373477E8 JALS prvAddCurrentTaskToDelayedList
+BFD03A44 0C003734 LHU T9, 3072(S4)
+BFD03A46 0C00 NOP
+3950: }\r
+3951: }\r
+3952: #else /* INCLUDE_vTaskSuspend */\r
+3953: {\r
+3954: /* Calculate the time at which the task should be\r
+3955: woken if the event does not occur. This may\r
+3956: overflow but this doesn't matter, the scheduler will\r
+3957: handle it. */\r
+3958: xTimeToWake = xTickCount + xTicksToWait;\r
+3959: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+3960: }\r
+3961: #endif /* INCLUDE_vTaskSuspend */\r
+3962: \r
+3963: /* All ports are written to allow a yield in a critical\r
+3964: section (some will yield immediately, others wait until the\r
+3965: critical section exits) - but it is not something that\r
+3966: application code should ever do. */\r
+3967: portYIELD_WITHIN_API();\r
+BFD03A48 4E5677E8 JALS ulPortGetCP0Cause
+BFD03A4A 4E56 ADDIU S2, S2, -5
+BFD03A4C 0C00 NOP
+BFD03A4E 0014F85E SW V0, 20(S8)
+BFD03A52 0014FC5E LW V0, 20(S8)
+BFD03A56 01005042 ORI V0, V0, 256
+BFD03A5A 0014F85E SW V0, 20(S8)
+BFD03A5E 0014FC9E LW A0, 20(S8)
+BFD03A62 4E6677E8 JALS vPortSetCP0Cause
+BFD03A64 4E66 ADDIU S3, S3, 3
+BFD03A66 0C00 NOP
+3968: }\r
+3969: else\r
+3970: {\r
+3971: mtCOVERAGE_TEST_MARKER();\r
+3972: }\r
+3973: }\r
+3974: else\r
+3975: {\r
+3976: mtCOVERAGE_TEST_MARKER();\r
+3977: }\r
+3978: }\r
+3979: taskEXIT_CRITICAL();\r
+BFD03A68 40AA77E8 JALS vTaskExitCritical
+BFD03A6A 0C0040AA BNEZC T2, 0xBFD0526E
+BFD03A6C 0C00 NOP
+3980: \r
+3981: taskENTER_CRITICAL();\r
+BFD03A6E 33B877E8 JALS vTaskEnterCritical
+BFD03A70 0C0033B8 ADDIU SP, T8, 3072
+BFD03A72 0C00 NOP
+3982: {\r
+3983: ulReturn = pxCurrentTCB->ulNotifiedValue;\r
+BFD03A74 8030FC5C LW V0, -32720(GP)
+BFD03A78 0048FC42 LW V0, 72(V0)
+BFD03A7C 0018F85E SW V0, 24(S8)
+3984: \r
+3985: if( ulReturn != 0UL )\r
+BFD03A80 0018FC5E LW V0, 24(S8)
+BFD03A84 001140E2 BEQZC V0, 0xBFD03AAA
+3986: {\r
+3987: if( xClearCountOnExit != pdFALSE )\r
+BFD03A88 0028FC5E LW V0, 40(S8)
+BFD03A8C 000640E2 BEQZC V0, 0xBFD03A9C
+3988: {\r
+3989: pxCurrentTCB->ulNotifiedValue = 0UL;\r
+BFD03A90 8030FC5C LW V0, -32720(GP)
+BFD03A94 0048F802 SW ZERO, 72(V0)
+BFD03A98 CC08 B 0xBFD03AAA
+BFD03A9A 0C00 NOP
+3990: }\r
+3991: else\r
+3992: {\r
+3993: ( pxCurrentTCB->ulNotifiedValue )--;\r
+BFD03A9C 8030FC5C LW V0, -32720(GP)
+BFD03AA0 0048FC62 LW V1, 72(V0)
+BFD03AA4 6DBE ADDIU V1, V1, -1
+BFD03AA6 0048F862 SW V1, 72(V0)
+3994: }\r
+3995: }\r
+3996: else\r
+3997: {\r
+3998: mtCOVERAGE_TEST_MARKER();\r
+3999: }\r
+4000: \r
+4001: pxCurrentTCB->eNotifyState = eNotWaitingNotification;\r
+BFD03AAA 8030FC5C LW V0, -32720(GP)
+BFD03AAE 004CF802 SW ZERO, 76(V0)
+4002: }\r
+4003: taskEXIT_CRITICAL();\r
+BFD03AB2 40AA77E8 JALS vTaskExitCritical
+BFD03AB4 0C0040AA BNEZC T2, 0xBFD052B8
+BFD03AB6 0C00 NOP
+4004: \r
+4005: return ulReturn;\r
+BFD03AB8 0018FC5E LW V0, 24(S8)
+4006: }\r
+BFD03ABC 0FBE MOVE SP, S8
+BFD03ABE 4BE9 LW RA, 36(SP)
+BFD03AC0 4BC8 LW S8, 32(SP)
+BFD03AC2 4C15 ADDIU SP, SP, 40
+BFD03AC4 459F JR16 RA
+BFD03AC6 0C00 NOP
+4007: \r
+4008: #endif /* configUSE_TASK_NOTIFICATIONS */\r
+4009: /*-----------------------------------------------------------*/\r
+4010: \r
+4011: #if( configUSE_TASK_NOTIFICATIONS == 1 )\r
+4012: \r
+4013: BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )\r
+4014: {\r
+BFD02C6C 4FED ADDIU SP, SP, -40
+BFD02C6E CBE9 SW RA, 36(SP)
+BFD02C70 CBC8 SW S8, 32(SP)
+BFD02C72 0FDD MOVE S8, SP
+BFD02C74 0028F89E SW A0, 40(S8)
+BFD02C78 002CF8BE SW A1, 44(S8)
+BFD02C7C 0030F8DE SW A2, 48(S8)
+BFD02C80 0034F8FE SW A3, 52(S8)
+4015: TickType_t xTimeToWake;\r
+4016: BaseType_t xReturn;\r
+4017: \r
+4018: taskENTER_CRITICAL();\r
+BFD02C84 33B877E8 JALS vTaskEnterCritical
+BFD02C86 0C0033B8 ADDIU SP, T8, 3072
+BFD02C88 0C00 NOP
+4019: {\r
+4020: /* Only block if a notification is not already pending. */\r
+4021: if( pxCurrentTCB->eNotifyState != eNotified )\r
+BFD02C8A 8030FC5C LW V0, -32720(GP)
+BFD02C8E 004CFC62 LW V1, 76(V0)
+BFD02C92 ED02 LI V0, 2
+BFD02C94 00589443 BEQ V1, V0, 0xBFD02D48
+BFD02C96 0C000058 SLL V0, T8, 1
+BFD02C98 0C00 NOP
+4022: {\r
+4023: /* Clear bits in the task's notification value as bits may get\r
+4024: set by the notifying task or interrupt. This can be used to\r
+4025: clear the value to zero. */\r
+4026: pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;\r
+BFD02C9A 8030FC5C LW V0, -32720(GP)
+BFD02C9E 0048FC82 LW A0, 72(V0)
+BFD02CA2 0028FC7E LW V1, 40(S8)
+BFD02CA6 441B NOT16 V1, V1
+BFD02CA8 449C AND16 V1, A0
+BFD02CAA 0048F862 SW V1, 72(V0)
+4027: \r
+4028: /* Mark this task as waiting for a notification. */\r
+4029: pxCurrentTCB->eNotifyState = eWaitingNotification;\r
+BFD02CAE 8030FC5C LW V0, -32720(GP)
+BFD02CB2 ED81 LI V1, 1
+BFD02CB4 004CF862 SW V1, 76(V0)
+4030: \r
+4031: if( xTicksToWait > ( TickType_t ) 0 )\r
+BFD02CB8 0034FC5E LW V0, 52(S8)
+BFD02CBC 004440E2 BEQZC V0, 0xBFD02D48
+4032: {\r
+4033: /* The task is going to block. First it must be removed\r
+4034: from the ready list. */\r
+4035: if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r
+BFD02CC0 8030FC5C LW V0, -32720(GP)
+BFD02CC4 6D22 ADDIU V0, V0, 4
+BFD02CC6 0C82 MOVE A0, V0
+BFD02CC8 00C877E8 JALS uxListRemove
+BFD02CCA 0C0000C8 SLL A2, T0, 1
+BFD02CCC 0C00 NOP
+BFD02CCE 000C40A2 BNEZC V0, 0xBFD02CEA
+4036: {\r
+4037: /* The current task must be in a ready list, so there is\r
+4038: no need to check, and the port reset macro can be called\r
+4039: directly. */\r
+4040: portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r
+BFD02CD2 8030FC5C LW V0, -32720(GP)
+BFD02CD6 692B LW V0, 44(V0)
+BFD02CD8 ED81 LI V1, 1
+BFD02CDA 10100062 SLLV V0, V0, V1
+BFD02CDC 441A1010 ADDI ZERO, S0, 17434
+BFD02CDE 441A NOT16 V1, V0
+BFD02CE0 8040FC5C LW V0, -32704(GP)
+BFD02CE4 4493 AND16 V0, V1
+BFD02CE6 8040F85C SW V0, -32704(GP)
+4041: }\r
+4042: else\r
+4043: {\r
+4044: mtCOVERAGE_TEST_MARKER();\r
+4045: }\r
+4046: \r
+4047: #if ( INCLUDE_vTaskSuspend == 1 )\r
+4048: {\r
+4049: if( xTicksToWait == portMAX_DELAY )\r
+BFD02CEA 0034FC7E LW V1, 52(S8)
+BFD02CEE ED7F LI V0, -1
+BFD02CF0 000EB443 BNE V1, V0, 0xBFD02D10
+BFD02CF2 0C00000E SLL ZERO, T6, 1
+BFD02CF4 0C00 NOP
+4050: {\r
+4051: /* Add the task to the suspended task list instead\r
+4052: of a delayed task list to ensure the task is not\r
+4053: woken by a timing event. It will block\r
+4054: indefinitely. */\r
+4055: vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r
+BFD02CF6 8030FC5C LW V0, -32720(GP)
+BFD02CFA 6D22 ADDIU V0, V0, 4
+BFD02CFC BFD241A3 LUI V1, 0xBFD2
+BFD02CFE 3083BFD2 LDC1 F30, 12419(S2)
+BFD02D00 80E43083 ADDIU A0, V1, -32540
+BFD02D04 0CA2 MOVE A1, V0
+BFD02D06 3E4A77E8 JALS vListInsertEnd
+BFD02D08 0C003E4A LH S2, 3072(T2)
+BFD02D0A 0C00 NOP
+BFD02D0C CC0D B 0xBFD02D28
+BFD02D0E 0C00 NOP
+4056: }\r
+4057: else\r
+4058: {\r
+4059: /* Calculate the time at which the task should be\r
+4060: woken if no notification events occur. This may\r
+4061: overflow but this doesn't matter, the scheduler will\r
+4062: handle it. */\r
+4063: xTimeToWake = xTickCount + xTicksToWait;\r
+BFD02D10 803CFC7C LW V1, -32708(GP)
+BFD02D14 0034FC5E LW V0, 52(S8)
+BFD02D18 0526 ADDU V0, V1, V0
+BFD02D1A 0014F85E SW V0, 20(S8)
+4064: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+BFD02D1E 0014FC9E LW A0, 20(S8)
+BFD02D22 373477E8 JALS prvAddCurrentTaskToDelayedList
+BFD02D24 0C003734 LHU T9, 3072(S4)
+BFD02D26 0C00 NOP
+4065: }\r
+4066: }\r
+4067: #else /* INCLUDE_vTaskSuspend */\r
+4068: {\r
+4069: /* Calculate the time at which the task should be\r
+4070: woken if the event does not occur. This may\r
+4071: overflow but this doesn't matter, the scheduler will\r
+4072: handle it. */\r
+4073: xTimeToWake = xTickCount + xTicksToWait;\r
+4074: prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+4075: }\r
+4076: #endif /* INCLUDE_vTaskSuspend */\r
+4077: \r
+4078: /* All ports are written to allow a yield in a critical\r
+4079: section (some will yield immediately, others wait until the\r
+4080: critical section exits) - but it is not something that\r
+4081: application code should ever do. */\r
+4082: portYIELD_WITHIN_API();\r
+BFD02D28 4E5677E8 JALS ulPortGetCP0Cause
+BFD02D2A 4E56 ADDIU S2, S2, -5
+BFD02D2C 0C00 NOP
+BFD02D2E 0018F85E SW V0, 24(S8)
+BFD02D32 0018FC5E LW V0, 24(S8)
+BFD02D36 01005042 ORI V0, V0, 256
+BFD02D3A 0018F85E SW V0, 24(S8)
+BFD02D3E 0018FC9E LW A0, 24(S8)
+BFD02D42 4E6677E8 JALS vPortSetCP0Cause
+BFD02D44 4E66 ADDIU S3, S3, 3
+BFD02D46 0C00 NOP
+4083: }\r
+4084: else\r
+4085: {\r
+4086: mtCOVERAGE_TEST_MARKER();\r
+4087: }\r
+4088: }\r
+4089: else\r
+4090: {\r
+4091: mtCOVERAGE_TEST_MARKER();\r
+4092: }\r
+4093: }\r
+4094: taskEXIT_CRITICAL();\r
+BFD02D48 40AA77E8 JALS vTaskExitCritical
+BFD02D4A 0C0040AA BNEZC T2, 0xBFD0454E
+BFD02D4C 0C00 NOP
+4095: \r
+4096: taskENTER_CRITICAL();\r
+BFD02D4E 33B877E8 JALS vTaskEnterCritical
+BFD02D50 0C0033B8 ADDIU SP, T8, 3072
+BFD02D52 0C00 NOP
+4097: {\r
+4098: if( pulNotificationValue != NULL )\r
+BFD02D54 0030FC5E LW V0, 48(S8)
+BFD02D58 000740E2 BEQZC V0, 0xBFD02D6A
+4099: {\r
+4100: /* Output the current notification value, which may or may not\r
+4101: have changed. */\r
+4102: *pulNotificationValue = pxCurrentTCB->ulNotifiedValue;\r
+BFD02D5C 8030FC5C LW V0, -32720(GP)
+BFD02D60 0048FC62 LW V1, 72(V0)
+BFD02D64 0030FC5E LW V0, 48(S8)
+BFD02D68 E9A0 SW V1, 0(V0)
+4103: }\r
+4104: \r
+4105: /* If eNotifyValue is set then either the task never entered the\r
+4106: blocked state (because a notification was already pending) or the\r
+4107: task unblocked because of a notification. Otherwise the task\r
+4108: unblocked because of a timeout. */\r
+4109: if( pxCurrentTCB->eNotifyState == eWaitingNotification )\r
+BFD02D6A 8030FC5C LW V0, -32720(GP)
+BFD02D6E 004CFC62 LW V1, 76(V0)
+BFD02D72 ED01 LI V0, 1
+BFD02D74 0005B443 BNE V1, V0, 0xBFD02D82
+BFD02D76 0C000005 SLL ZERO, A1, 1
+BFD02D78 0C00 NOP
+4110: {\r
+4111: /* A notification was not received. */\r
+4112: xReturn = pdFALSE;\r
+BFD02D7A 0010F81E SW ZERO, 16(S8)
+BFD02D7E CC0E B 0xBFD02D9C
+BFD02D80 0C00 NOP
+4113: }\r
+4114: else\r
+4115: {\r
+4116: /* A notification was already pending or a notification was\r
+4117: received while the task was waiting. */\r
+4118: pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;\r
+BFD02D82 8030FC5C LW V0, -32720(GP)
+BFD02D86 0048FC82 LW A0, 72(V0)
+BFD02D8A 002CFC7E LW V1, 44(S8)
+BFD02D8E 441B NOT16 V1, V1
+BFD02D90 449C AND16 V1, A0
+BFD02D92 0048F862 SW V1, 72(V0)
+4119: xReturn = pdTRUE;\r
+BFD02D96 ED01 LI V0, 1
+BFD02D98 0010F85E SW V0, 16(S8)
+4120: }\r
+4121: \r
+4122: pxCurrentTCB->eNotifyState = eNotWaitingNotification;\r
+BFD02D9C 8030FC5C LW V0, -32720(GP)
+BFD02DA0 004CF802 SW ZERO, 76(V0)
+4123: }\r
+4124: taskEXIT_CRITICAL();\r
+BFD02DA4 40AA77E8 JALS vTaskExitCritical
+BFD02DA6 0C0040AA BNEZC T2, 0xBFD045AA
+BFD02DA8 0C00 NOP
+4125: \r
+4126: return xReturn;\r
+BFD02DAA 0010FC5E LW V0, 16(S8)
+4127: }\r
+BFD02DAE 0FBE MOVE SP, S8
+BFD02DB0 4BE9 LW RA, 36(SP)
+BFD02DB2 4BC8 LW S8, 32(SP)
+BFD02DB4 4C15 ADDIU SP, SP, 40
+BFD02DB6 459F JR16 RA
+BFD02DB8 0C00 NOP
+4128: \r
+4129: #endif /* configUSE_TASK_NOTIFICATIONS */\r
+4130: /*-----------------------------------------------------------*/\r
+4131: \r
+4132: #if( configUSE_TASK_NOTIFICATIONS == 1 )\r
+4133: \r
+4134: BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )\r
+4135: {\r
+BFD01CE8 4FED ADDIU SP, SP, -40
+BFD01CEA CBE9 SW RA, 36(SP)
+BFD01CEC CBC8 SW S8, 32(SP)
+BFD01CEE 0FDD MOVE S8, SP
+BFD01CF0 0028F89E SW A0, 40(S8)
+BFD01CF4 002CF8BE SW A1, 44(S8)
+BFD01CF8 0030F8DE SW A2, 48(S8)
+BFD01CFC 0034F8FE SW A3, 52(S8)
+4136: TCB_t * pxTCB;\r
+4137: eNotifyValue eOriginalNotifyState;\r
+4138: BaseType_t xReturn = pdPASS;\r
+BFD01D00 ED01 LI V0, 1
+BFD01D02 0010F85E SW V0, 16(S8)
+4139: \r
+4140: configASSERT( xTaskToNotify );\r
+BFD01D06 0028FC5E LW V0, 40(S8)
+BFD01D0A 000940A2 BNEZC V0, 0xBFD01D20
+BFD01D0E BFD141A2 LUI V0, 0xBFD1
+BFD01D10 3082BFD1 LDC1 F30, 12418(S1)
+BFD01D12 98103082 ADDIU A0, V0, -26608
+BFD01D14 30A09810 SWC1 F0, 12448(S0)
+BFD01D16 102C30A0 ADDIU A1, ZERO, 4140
+BFD01D18 77E8102C ADDI AT, T4, 30696
+BFD01D1A 4B7E77E8 JALS vAssertCalled
+BFD01D1C 4B7E LW K1, 120(SP)
+BFD01D1E 0C00 NOP
+4141: pxTCB = ( TCB_t * ) xTaskToNotify;\r
+BFD01D20 0028FC5E LW V0, 40(S8)
+BFD01D24 0014F85E SW V0, 20(S8)
+4142: \r
+4143: taskENTER_CRITICAL();\r
+BFD01D28 33B877E8 JALS vTaskEnterCritical
+BFD01D2A 0C0033B8 ADDIU SP, T8, 3072
+BFD01D2C 0C00 NOP
+4144: {\r
+4145: if( pulPreviousNotificationValue != NULL )\r
+BFD01D2E 0034FC5E LW V0, 52(S8)
+BFD01D32 000740E2 BEQZC V0, 0xBFD01D44
+4146: {\r
+4147: *pulPreviousNotificationValue = pxTCB->ulNotifiedValue;\r
+BFD01D36 0014FC5E LW V0, 20(S8)
+BFD01D3A 0048FC62 LW V1, 72(V0)
+BFD01D3E 0034FC5E LW V0, 52(S8)
+BFD01D42 E9A0 SW V1, 0(V0)
+4148: }\r
+4149: \r
+4150: eOriginalNotifyState = pxTCB->eNotifyState;\r
+BFD01D44 0014FC5E LW V0, 20(S8)
+BFD01D48 004CFC42 LW V0, 76(V0)
+BFD01D4C 0018F85E SW V0, 24(S8)
+4151: \r
+4152: pxTCB->eNotifyState = eNotified;\r
+BFD01D50 0014FC5E LW V0, 20(S8)
+BFD01D54 ED82 LI V1, 2
+BFD01D56 004CF862 SW V1, 76(V0)
+4153: \r
+4154: switch( eAction )\r
+BFD01D5A 0030FC5E LW V0, 48(S8)
+BFD01D5E 0005B042 SLTIU V0, V0, 5
+BFD01D62 004840E2 BEQZC V0, 0xBFD01DF6
+BFD01D66 0030FC5E LW V0, 48(S8)
+BFD01D6A 25A4 SLL V1, V0, 2
+BFD01D6C BFD041A2 LUI V0, 0xBFD0
+BFD01D6E 3042BFD0 LDC1 F30, 12354(S0)
+BFD01D70 1D7C3042 ADDIU V0, V0, 7548
+BFD01D72 05261D7C LB T3, 1318(GP)
+BFD01D74 0526 ADDU V0, V1, V0
+BFD01D76 6920 LW V0, 0(V0)
+BFD01D78 45A2 JRC V0
+BFD01D7A 0C00 NOP
+BFD01D7C BFD01DF5 LB T7, -16432(S5)
+BFD01D7E 1D91BFD0 LDC1 F30, 7569(S0)
+BFD01D80 BFD01D91 LB T4, -16432(S1)
+BFD01D82 1DABBFD0 LDC1 F30, 7595(S0)
+BFD01D84 BFD01DAB LB T5, -16432(T3)
+BFD01D86 1DC1BFD0 LDC1 F30, 7617(S0)
+BFD01D88 BFD01DC1 LB T6, -16432(AT)
+BFD01D8A 1DD1BFD0 LDC1 F30, 7633(S0)
+BFD01D8C BFD01DD1 LB T6, -16432(S1)
+BFD01D8E FC5EBFD0 LDC1 F30, -930(S0)
+4155: {\r
+4156: case eSetBits :\r
+4157: pxTCB->ulNotifiedValue |= ulValue;\r
+BFD01D90 0014FC5E LW V0, 20(S8)
+BFD01D94 0048FC62 LW V1, 72(V0)
+BFD01D98 002CFC5E LW V0, 44(S8)
+BFD01D9C 44DA OR16 V1, V0
+BFD01D9E 0014FC5E LW V0, 20(S8)
+BFD01DA2 0048F862 SW V1, 72(V0)
+4158: break;\r
+BFD01DA6 CC27 B 0xBFD01DF6
+BFD01DA8 0C00 NOP
+4159: \r
+4160: case eIncrement :\r
+4161: ( pxTCB->ulNotifiedValue )++;\r
+BFD01DAA 0014FC5E LW V0, 20(S8)
+BFD01DAE 0048FC42 LW V0, 72(V0)
+BFD01DB2 6DA0 ADDIU V1, V0, 1
+BFD01DB4 0014FC5E LW V0, 20(S8)
+BFD01DB8 0048F862 SW V1, 72(V0)
+4162: break;\r
+BFD01DBC CC1C B 0xBFD01DF6
+BFD01DBE 0C00 NOP
+4163: \r
+4164: case eSetValueWithOverwrite :\r
+4165: pxTCB->ulNotifiedValue = ulValue;\r
+BFD01DC0 0014FC5E LW V0, 20(S8)
+BFD01DC4 002CFC7E LW V1, 44(S8)
+BFD01DC8 0048F862 SW V1, 72(V0)
+4166: break;\r
+BFD01DCC CC14 B 0xBFD01DF6
+BFD01DCE 0C00 NOP
+4167: \r
+4168: case eSetValueWithoutOverwrite :\r
+4169: if( eOriginalNotifyState != eNotified )\r
+BFD01DD0 0018FC7E LW V1, 24(S8)
+BFD01DD4 ED02 LI V0, 2
+BFD01DD6 00099443 BEQ V1, V0, 0xBFD01DEC
+BFD01DD8 0C000009 SLL ZERO, T1, 1
+BFD01DDA 0C00 NOP
+4170: {\r
+4171: pxTCB->ulNotifiedValue = ulValue;\r
+BFD01DDC 0014FC5E LW V0, 20(S8)
+BFD01DE0 002CFC7E LW V1, 44(S8)
+BFD01DE4 0048F862 SW V1, 72(V0)
+4172: }\r
+4173: else\r
+4174: {\r
+4175: /* The value could not be written to the task. */\r
+4176: xReturn = pdFAIL;\r
+BFD01DEC 0010F81E SW ZERO, 16(S8)
+4177: }\r
+4178: break;\r
+BFD01DE8 CC06 B 0xBFD01DF6
+BFD01DEA 0C00 NOP
+BFD01DF0 CC02 B 0xBFD01DF6
+BFD01DF2 0C00 NOP
+4179: \r
+4180: case eNoAction:\r
+4181: /* The task is being notified without its notify value being\r
+4182: updated. */\r
+4183: break;\r
+BFD01DF4 0C00 NOP
+4184: }\r
+4185: \r
+4186: \r
+4187: /* If the task is in the blocked state specifically to wait for a\r
+4188: notification then unblock it now. */\r
+4189: if( eOriginalNotifyState == eWaitingNotification )\r
+BFD01DF6 0018FC7E LW V1, 24(S8)
+BFD01DFA ED01 LI V0, 1
+BFD01DFC 004EB443 BNE V1, V0, 0xBFD01E9C
+BFD01DFE 0C00004E SLL V0, T6, 1
+BFD01E00 0C00 NOP
+4190: {\r
+4191: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
+BFD01E02 0014FC5E LW V0, 20(S8)
+BFD01E06 6D22 ADDIU V0, V0, 4
+BFD01E08 0C82 MOVE A0, V0
+BFD01E0A 00C877E8 JALS uxListRemove
+BFD01E0C 0C0000C8 SLL A2, T0, 1
+BFD01E0E 0C00 NOP
+4192: prvAddTaskToReadyList( pxTCB );\r
+BFD01E10 0014FC5E LW V0, 20(S8)
+BFD01E14 692B LW V0, 44(V0)
+BFD01E16 ED81 LI V1, 1
+BFD01E18 18100062 SLLV V1, V0, V1
+BFD01E1A FC5C1810 SB ZERO, -932(S0)
+BFD01E1C 8040FC5C LW V0, -32704(GP)
+BFD01E20 44D3 OR16 V0, V1
+BFD01E22 8040F85C SW V0, -32704(GP)
+BFD01E26 0014FC5E LW V0, 20(S8)
+BFD01E2A 692B LW V0, 44(V0)
+BFD01E2C 2524 SLL V0, V0, 2
+BFD01E2E 25A4 SLL V1, V0, 2
+BFD01E30 05B4 ADDU V1, V0, V1
+BFD01E32 BFD241A2 LUI V0, 0xBFD2
+BFD01E34 3042BFD2 LDC1 F30, 12354(S2)
+BFD01E36 806C3042 ADDIU V0, V0, -32660
+BFD01E3A 05A6 ADDU V1, V1, V0
+BFD01E3C 0014FC5E LW V0, 20(S8)
+BFD01E40 6D22 ADDIU V0, V0, 4
+BFD01E42 0C83 MOVE A0, V1
+BFD01E44 0CA2 MOVE A1, V0
+BFD01E46 3E4A77E8 JALS vListInsertEnd
+BFD01E48 0C003E4A LH S2, 3072(T2)
+BFD01E4A 0C00 NOP
+4193: \r
+4194: /* The task should not have been on an event list. */\r
+4195: configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\r
+BFD01E4C 0014FC5E LW V0, 20(S8)
+BFD01E50 692A LW V0, 40(V0)
+BFD01E52 000940E2 BEQZC V0, 0xBFD01E68
+BFD01E56 BFD141A2 LUI V0, 0xBFD1
+BFD01E58 3082BFD1 LDC1 F30, 12418(S1)
+BFD01E5A 98103082 ADDIU A0, V0, -26608
+BFD01E5C 30A09810 SWC1 F0, 12448(S0)
+BFD01E5E 106330A0 ADDIU A1, ZERO, 4195
+BFD01E60 77E81063 ADDI V1, V1, 30696
+BFD01E62 4B7E77E8 JALS vAssertCalled
+BFD01E64 4B7E LW K1, 120(SP)
+BFD01E66 0C00 NOP
+4196: \r
+4197: #if( configUSE_TICKLESS_IDLE != 0 )\r
+4198: {\r
+4199: /* If a task is blocked waiting for a notification then\r
+4200: xNextTaskUnblockTime might be set to the blocked task's time\r
+4201: out time. If the task is unblocked for a reason other than\r
+4202: a timeout xNextTaskUnblockTime is normally left unchanged,\r
+4203: because it will automatically get reset to a new value when\r
+4204: the tick count equals xNextTaskUnblockTime. However if\r
+4205: tickless idling is used it might be more important to enter\r
+4206: sleep mode at the earliest possible time - so reset\r
+4207: xNextTaskUnblockTime here to ensure it is updated at the\r
+4208: earliest possible time. */\r
+4209: prvResetNextTaskUnblockTime();\r
+4210: }\r
+4211: #endif\r
+4212: \r
+4213: if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\r
+BFD01E68 0014FC5E LW V0, 20(S8)
+BFD01E6C 69AB LW V1, 44(V0)
+BFD01E6E 8030FC5C LW V0, -32720(GP)
+BFD01E72 692B LW V0, 44(V0)
+BFD01E74 13900062 SLTU V0, V0, V1
+BFD01E76 40E21390 ADDI GP, S0, 16610
+BFD01E78 001040E2 BEQZC V0, 0xBFD01E9C
+4214: {\r
+4215: /* The notified task has a priority above the currently\r
+4216: executing task so a yield is required. */\r
+4217: taskYIELD_IF_USING_PREEMPTION();\r
+BFD01E7C 4E5677E8 JALS ulPortGetCP0Cause
+BFD01E7E 4E56 ADDIU S2, S2, -5
+BFD01E80 0C00 NOP
+BFD01E82 001CF85E SW V0, 28(S8)
+BFD01E86 001CFC5E LW V0, 28(S8)
+BFD01E8A 01005042 ORI V0, V0, 256
+BFD01E8E 001CF85E SW V0, 28(S8)
+BFD01E92 001CFC9E LW A0, 28(S8)
+BFD01E96 4E6677E8 JALS vPortSetCP0Cause
+BFD01E98 4E66 ADDIU S3, S3, 3
+BFD01E9A 0C00 NOP
+4218: }\r
+4219: else\r
+4220: {\r
+4221: mtCOVERAGE_TEST_MARKER();\r
+4222: }\r
+4223: }\r
+4224: else\r
+4225: {\r
+4226: mtCOVERAGE_TEST_MARKER();\r
+4227: }\r
+4228: }\r
+4229: taskEXIT_CRITICAL();\r
+BFD01E9C 40AA77E8 JALS vTaskExitCritical
+BFD01E9E 0C0040AA BNEZC T2, 0xBFD036A2
+BFD01EA0 0C00 NOP
+4230: \r
+4231: return xReturn;\r
+BFD01EA2 0010FC5E LW V0, 16(S8)
+4232: }\r
+BFD01EA6 0FBE MOVE SP, S8
+BFD01EA8 4BE9 LW RA, 36(SP)
+BFD01EAA 4BC8 LW S8, 32(SP)
+BFD01EAC 4C15 ADDIU SP, SP, 40
+BFD01EAE 459F JR16 RA
+BFD01EB0 0C00 NOP
+4233: \r
+4234: #endif /* configUSE_TASK_NOTIFICATIONS */\r
+4235: /*-----------------------------------------------------------*/\r
+4236: \r
+4237: #if( configUSE_TASK_NOTIFICATIONS == 1 )\r
+4238: \r
+4239: BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken )\r
+4240: {\r
+BFD01EB4 4FED ADDIU SP, SP, -40
+BFD01EB6 CBE9 SW RA, 36(SP)
+BFD01EB8 CBC8 SW S8, 32(SP)
+BFD01EBA 0FDD MOVE S8, SP
+BFD01EBC 0028F89E SW A0, 40(S8)
+BFD01EC0 002CF8BE SW A1, 44(S8)
+BFD01EC4 0030F8DE SW A2, 48(S8)
+BFD01EC8 0034F8FE SW A3, 52(S8)
+4241: TCB_t * pxTCB;\r
+4242: eNotifyValue eOriginalNotifyState;\r
+4243: BaseType_t xReturn = pdPASS;\r
+BFD01ECC ED01 LI V0, 1
+BFD01ECE 0010F85E SW V0, 16(S8)
+4244: UBaseType_t uxSavedInterruptStatus;\r
+4245: \r
+4246: configASSERT( xTaskToNotify );\r
+BFD01ED2 0028FC5E LW V0, 40(S8)
+BFD01ED6 000940A2 BNEZC V0, 0xBFD01EEC
+BFD01EDA BFD141A2 LUI V0, 0xBFD1
+BFD01EDC 3082BFD1 LDC1 F30, 12418(S1)
+BFD01EDE 98103082 ADDIU A0, V0, -26608
+BFD01EE0 30A09810 SWC1 F0, 12448(S0)
+BFD01EE2 109630A0 ADDIU A1, ZERO, 4246
+BFD01EE4 77E81096 ADDI A0, S6, 30696
+BFD01EE6 4B7E77E8 JALS vAssertCalled
+BFD01EE8 4B7E LW K1, 120(SP)
+BFD01EEA 0C00 NOP
+4247: \r
+4248: /* RTOS ports that support interrupt nesting have the concept of a\r
+4249: maximum system call (or maximum API call) interrupt priority.\r
+4250: Interrupts that are above the maximum system call priority are keep\r
+4251: permanently enabled, even when the RTOS kernel is in a critical section,\r
+4252: but cannot make any calls to FreeRTOS API functions. If configASSERT()\r
+4253: is defined in FreeRTOSConfig.h then\r
+4254: portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r
+4255: failure if a FreeRTOS API function is called from an interrupt that has\r
+4256: been assigned a priority above the configured maximum system call\r
+4257: priority. Only FreeRTOS functions that end in FromISR can be called\r
+4258: from interrupts that have been assigned a priority at or (logically)\r
+4259: below the maximum system call interrupt priority. FreeRTOS maintains a\r
+4260: separate interrupt safe API to ensure interrupt entry is as fast and as\r
+4261: simple as possible. More information (albeit Cortex-M specific) is\r
+4262: provided on the following link:\r
+4263: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r
+4264: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
+4265: \r
+4266: pxTCB = ( TCB_t * ) xTaskToNotify;\r
+BFD01EEC 0028FC5E LW V0, 40(S8)
+BFD01EF0 0014F85E SW V0, 20(S8)
+4267: \r
+4268: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+BFD01EF4 475E77E8 JALS uxPortSetInterruptMaskFromISR
+BFD01EF8 0C00 NOP
+BFD01EFA 0018F85E SW V0, 24(S8)
+4269: {\r
+4270: eOriginalNotifyState = pxTCB->eNotifyState;\r
+BFD01EFE 0014FC5E LW V0, 20(S8)
+BFD01F02 004CFC42 LW V0, 76(V0)
+BFD01F06 001CF85E SW V0, 28(S8)
+4271: \r
+4272: pxTCB->eNotifyState = eNotified;\r
+BFD01F0A 0014FC5E LW V0, 20(S8)
+BFD01F0E ED82 LI V1, 2
+BFD01F10 004CF862 SW V1, 76(V0)
+4273: \r
+4274: switch( eAction )\r
+BFD01F14 0030FC5E LW V0, 48(S8)
+BFD01F18 0005B042 SLTIU V0, V0, 5
+BFD01F1C 004740E2 BEQZC V0, 0xBFD01FAE
+BFD01F20 0030FC5E LW V0, 48(S8)
+BFD01F24 25A4 SLL V1, V0, 2
+BFD01F26 BFD041A2 LUI V0, 0xBFD0
+BFD01F28 3042BFD0 LDC1 F30, 12354(S0)
+BFD01F2A 1F343042 ADDIU V0, V0, 7988
+BFD01F2C 05261F34 LB T9, 1318(S4)
+BFD01F2E 0526 ADDU V0, V1, V0
+BFD01F30 6920 LW V0, 0(V0)
+BFD01F32 45A2 JRC V0
+BFD01F34 BFD01FAD LB SP, -16432(T5)
+BFD01F36 1F49BFD0 LDC1 F30, 8009(S0)
+BFD01F38 BFD01F49 LB K0, -16432(T1)
+BFD01F3A 1F63BFD0 LDC1 F30, 8035(S0)
+BFD01F3C BFD01F63 LB K1, -16432(V1)
+BFD01F3E 1F79BFD0 LDC1 F30, 8057(S0)
+BFD01F40 BFD01F79 LB K1, -16432(T9)
+BFD01F42 1F89BFD0 LDC1 F30, 8073(S0)
+BFD01F44 BFD01F89 LB GP, -16432(T1)
+BFD01F46 FC5EBFD0 LDC1 F30, -930(S0)
+4275: {\r
+4276: case eSetBits :\r
+4277: pxTCB->ulNotifiedValue |= ulValue;\r
+BFD01F48 0014FC5E LW V0, 20(S8)
+BFD01F4C 0048FC62 LW V1, 72(V0)
+BFD01F50 002CFC5E LW V0, 44(S8)
+BFD01F54 44DA OR16 V1, V0
+BFD01F56 0014FC5E LW V0, 20(S8)
+BFD01F5A 0048F862 SW V1, 72(V0)
+4278: break;\r
+BFD01F5E CC27 B 0xBFD01FAE
+BFD01F60 0C00 NOP
+4279: \r
+4280: case eIncrement :\r
+4281: ( pxTCB->ulNotifiedValue )++;\r
+BFD01F62 0014FC5E LW V0, 20(S8)
+BFD01F66 0048FC42 LW V0, 72(V0)
+BFD01F6A 6DA0 ADDIU V1, V0, 1
+BFD01F6C 0014FC5E LW V0, 20(S8)
+BFD01F70 0048F862 SW V1, 72(V0)
+4282: break;\r
+BFD01F74 CC1C B 0xBFD01FAE
+BFD01F76 0C00 NOP
+4283: \r
+4284: case eSetValueWithOverwrite :\r
+4285: pxTCB->ulNotifiedValue = ulValue;\r
+BFD01F78 0014FC5E LW V0, 20(S8)
+BFD01F7C 002CFC7E LW V1, 44(S8)
+BFD01F80 0048F862 SW V1, 72(V0)
+4286: break;\r
+BFD01F84 CC14 B 0xBFD01FAE
+BFD01F86 0C00 NOP
+4287: \r
+4288: case eSetValueWithoutOverwrite :\r
+4289: if( eOriginalNotifyState != eNotified )\r
+BFD01F88 001CFC7E LW V1, 28(S8)
+BFD01F8C ED02 LI V0, 2
+BFD01F8E 00099443 BEQ V1, V0, 0xBFD01FA4
+BFD01F90 0C000009 SLL ZERO, T1, 1
+BFD01F92 0C00 NOP
+4290: {\r
+4291: pxTCB->ulNotifiedValue = ulValue;\r
+BFD01F94 0014FC5E LW V0, 20(S8)
+BFD01F98 002CFC7E LW V1, 44(S8)
+BFD01F9C 0048F862 SW V1, 72(V0)
+4292: }\r
+4293: else\r
+4294: {\r
+4295: /* The value could not be written to the task. */\r
+4296: xReturn = pdFAIL;\r
+BFD01FA4 0010F81E SW ZERO, 16(S8)
+4297: }\r
+4298: break;\r
+BFD01FA0 CC06 B 0xBFD01FAE
+BFD01FA2 0C00 NOP
+BFD01FA8 CC02 B 0xBFD01FAE
+BFD01FAA 0C00 NOP
+4299: \r
+4300: case eNoAction :\r
+4301: /* The task is being notified without its notify value being\r
+4302: updated. */\r
+4303: break;\r
+BFD01FAC 0C00 NOP
+4304: }\r
+4305: \r
+4306: \r
+4307: /* If the task is in the blocked state specifically to wait for a\r
+4308: notification then unblock it now. */\r
+4309: if( eOriginalNotifyState == eWaitingNotification )\r
+BFD01FAE 001CFC7E LW V1, 28(S8)
+BFD01FB2 ED01 LI V0, 1
+BFD01FB4 0057B443 BNE V1, V0, 0xBFD02066
+BFD01FB6 0C000057 SLL V0, S7, 1
+BFD01FB8 0C00 NOP
+4310: {\r
+4311: /* The task should not have been on an event list. */\r
+4312: configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\r
+BFD01FBA 0014FC5E LW V0, 20(S8)
+BFD01FBE 692A LW V0, 40(V0)
+BFD01FC0 000940E2 BEQZC V0, 0xBFD01FD6
+BFD01FC4 BFD141A2 LUI V0, 0xBFD1
+BFD01FC6 3082BFD1 LDC1 F30, 12418(S1)
+BFD01FC8 98103082 ADDIU A0, V0, -26608
+BFD01FCA 30A09810 SWC1 F0, 12448(S0)
+BFD01FCC 10D830A0 ADDIU A1, ZERO, 4312
+BFD01FCE 77E810D8 ADDI A2, T8, 30696
+BFD01FD0 4B7E77E8 JALS vAssertCalled
+BFD01FD2 4B7E LW K1, 120(SP)
+BFD01FD4 0C00 NOP
+4313: \r
+4314: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
+BFD01FD6 805CFC5C LW V0, -32676(GP)
+BFD01FDA 002740A2 BNEZC V0, 0xBFD0202C
+4315: {\r
+4316: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
+BFD01FDE 0014FC5E LW V0, 20(S8)
+BFD01FE2 6D22 ADDIU V0, V0, 4
+BFD01FE4 0C82 MOVE A0, V0
+BFD01FE6 00C877E8 JALS uxListRemove
+BFD01FE8 0C0000C8 SLL A2, T0, 1
+BFD01FEA 0C00 NOP
+4317: prvAddTaskToReadyList( pxTCB );\r
+BFD01FEC 0014FC5E LW V0, 20(S8)
+BFD01FF0 692B LW V0, 44(V0)
+BFD01FF2 ED81 LI V1, 1
+BFD01FF4 18100062 SLLV V1, V0, V1
+BFD01FF6 FC5C1810 SB ZERO, -932(S0)
+BFD01FF8 8040FC5C LW V0, -32704(GP)
+BFD01FFC 44D3 OR16 V0, V1
+BFD01FFE 8040F85C SW V0, -32704(GP)
+BFD02002 0014FC5E LW V0, 20(S8)
+BFD02006 692B LW V0, 44(V0)
+BFD02008 2524 SLL V0, V0, 2
+BFD0200A 25A4 SLL V1, V0, 2
+BFD0200C 05B4 ADDU V1, V0, V1
+BFD0200E BFD241A2 LUI V0, 0xBFD2
+BFD02010 3042BFD2 LDC1 F30, 12354(S2)
+BFD02012 806C3042 ADDIU V0, V0, -32660
+BFD02016 05A6 ADDU V1, V1, V0
+BFD02018 0014FC5E LW V0, 20(S8)
+BFD0201C 6D22 ADDIU V0, V0, 4
+BFD0201E 0C83 MOVE A0, V1
+BFD02020 0CA2 MOVE A1, V0
+BFD02022 3E4A77E8 JALS vListInsertEnd
+BFD02024 0C003E4A LH S2, 3072(T2)
+BFD02026 0C00 NOP
+BFD02028 CC0C B 0xBFD02042
+BFD0202A 0C00 NOP
+4318: }\r
+4319: else\r
+4320: {\r
+4321: /* The delayed and ready lists cannot be accessed, so hold\r
+4322: this task pending until the scheduler is resumed. */\r
+4323: vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r
+BFD0202C 0014FC5E LW V0, 20(S8)
+BFD0202E 6D2C0014 EXT ZERO, S4, 20, 14
+BFD02030 6D2C ADDIU V0, V0, 24
+BFD02032 BFD241A3 LUI V1, 0xBFD2
+BFD02034 3083BFD2 LDC1 F30, 12419(S2)
+BFD02036 80D03083 ADDIU A0, V1, -32560
+BFD0203A 0CA2 MOVE A1, V0
+BFD0203C 3E4A77E8 JALS vListInsertEnd
+BFD0203E 0C003E4A LH S2, 3072(T2)
+BFD02040 0C00 NOP
+4324: }\r
+4325: \r
+4326: if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\r
+BFD02042 0014FC5E LW V0, 20(S8)
+BFD02046 69AB LW V1, 44(V0)
+BFD02048 8030FC5C LW V0, -32720(GP)
+BFD0204C 692B LW V0, 44(V0)
+BFD0204E 13900062 SLTU V0, V0, V1
+BFD02050 40E21390 ADDI GP, S0, 16610
+BFD02052 000840E2 BEQZC V0, 0xBFD02066
+4327: {\r
+4328: /* The notified task has a priority above the currently\r
+4329: executing task so a yield is required. */\r
+4330: if( pxHigherPriorityTaskWoken != NULL )\r
+BFD02056 0034FC5E LW V0, 52(S8)
+BFD0205A 000440E2 BEQZC V0, 0xBFD02066
+4331: {\r
+4332: *pxHigherPriorityTaskWoken = pdTRUE;\r
+BFD0205E 0034FC5E LW V0, 52(S8)
+BFD02062 ED81 LI V1, 1
+BFD02064 E9A0 SW V1, 0(V0)
+4333: }\r
+4334: }\r
+4335: else\r
+4336: {\r
+4337: mtCOVERAGE_TEST_MARKER();\r
+4338: }\r
+4339: }\r
+4340: }\r
+4341: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+BFD02066 0018FC9E LW A0, 24(S8)
+BFD0206A 4D5E77E8 JALS vPortClearInterruptMaskFromISR
+BFD0206C 4D5E ADDIU T2, T2, -1
+BFD0206E 0C00 NOP
+4342: \r
+4343: return xReturn;\r
+BFD02070 0010FC5E LW V0, 16(S8)
+4344: }\r
+BFD02074 0FBE MOVE SP, S8
+BFD02076 4BE9 LW RA, 36(SP)
+BFD02078 4BC8 LW S8, 32(SP)
+BFD0207A 4C15 ADDIU SP, SP, 40
+BFD0207C 459F JR16 RA
+BFD0207E 0C00 NOP
+4345: \r
+4346: #endif /* configUSE_TASK_NOTIFICATIONS */\r
+4347: /*-----------------------------------------------------------*/\r
+4348: \r
+4349: #if( configUSE_TASK_NOTIFICATIONS == 1 )\r
+4350: \r
+4351: void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )\r
+4352: {\r
+BFD03190 4FED ADDIU SP, SP, -40
+BFD03192 CBE9 SW RA, 36(SP)
+BFD03194 CBC8 SW S8, 32(SP)
+BFD03196 0FDD MOVE S8, SP
+BFD03198 0028F89E SW A0, 40(S8)
+BFD0319C 002CF8BE SW A1, 44(S8)
+4353: TCB_t * pxTCB;\r
+4354: eNotifyValue eOriginalNotifyState;\r
+4355: UBaseType_t uxSavedInterruptStatus;\r
+4356: \r
+4357: configASSERT( xTaskToNotify );\r
+BFD031A0 0028FC5E LW V0, 40(S8)
+BFD031A4 000940A2 BNEZC V0, 0xBFD031BA
+BFD031A8 BFD141A2 LUI V0, 0xBFD1
+BFD031AA 3082BFD1 LDC1 F30, 12418(S1)
+BFD031AC 98103082 ADDIU A0, V0, -26608
+BFD031AE 30A09810 SWC1 F0, 12448(S0)
+BFD031B0 110530A0 ADDIU A1, ZERO, 4357
+BFD031B2 77E81105 ADDI T0, A1, 30696
+BFD031B4 4B7E77E8 JALS vAssertCalled
+BFD031B6 4B7E LW K1, 120(SP)
+BFD031B8 0C00 NOP
+4358: \r
+4359: /* RTOS ports that support interrupt nesting have the concept of a\r
+4360: maximum system call (or maximum API call) interrupt priority.\r
+4361: Interrupts that are above the maximum system call priority are keep\r
+4362: permanently enabled, even when the RTOS kernel is in a critical section,\r
+4363: but cannot make any calls to FreeRTOS API functions. If configASSERT()\r
+4364: is defined in FreeRTOSConfig.h then\r
+4365: portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r
+4366: failure if a FreeRTOS API function is called from an interrupt that has\r
+4367: been assigned a priority above the configured maximum system call\r
+4368: priority. Only FreeRTOS functions that end in FromISR can be called\r
+4369: from interrupts that have been assigned a priority at or (logically)\r
+4370: below the maximum system call interrupt priority. FreeRTOS maintains a\r
+4371: separate interrupt safe API to ensure interrupt entry is as fast and as\r
+4372: simple as possible. More information (albeit Cortex-M specific) is\r
+4373: provided on the following link:\r
+4374: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r
+4375: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
+4376: \r
+4377: pxTCB = ( TCB_t * ) xTaskToNotify;\r
+BFD031BA 0028FC5E LW V0, 40(S8)
+BFD031BE 0010F85E SW V0, 16(S8)
+4378: \r
+4379: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+BFD031C2 475E77E8 JALS uxPortSetInterruptMaskFromISR
+BFD031C6 0C00 NOP
+BFD031C8 0014F85E SW V0, 20(S8)
+4380: {\r
+4381: eOriginalNotifyState = pxTCB->eNotifyState;\r
+BFD031CC 0010FC5E LW V0, 16(S8)
+BFD031D0 004CFC42 LW V0, 76(V0)
+BFD031D4 0018F85E SW V0, 24(S8)
+4382: pxTCB->eNotifyState = eNotified;\r
+BFD031D8 0010FC5E LW V0, 16(S8)
+BFD031DC ED82 LI V1, 2
+BFD031DE 004CF862 SW V1, 76(V0)
+4383: \r
+4384: /* 'Giving' is equivalent to incrementing a count in a counting\r
+4385: semaphore. */\r
+4386: ( pxTCB->ulNotifiedValue )++;\r
+BFD031E2 0010FC5E LW V0, 16(S8)
+BFD031E6 0048FC42 LW V0, 72(V0)
+BFD031EA 6DA0 ADDIU V1, V0, 1
+BFD031EC 0010FC5E LW V0, 16(S8)
+BFD031F0 0048F862 SW V1, 72(V0)
+4387: \r
+4388: /* If the task is in the blocked state specifically to wait for a\r
+4389: notification then unblock it now. */\r
+4390: if( eOriginalNotifyState == eWaitingNotification )\r
+BFD031F4 0018FC7E LW V1, 24(S8)
+BFD031F8 ED01 LI V0, 1
+BFD031FA 0057B443 BNE V1, V0, 0xBFD032AC
+BFD031FC 0C000057 SLL V0, S7, 1
+BFD031FE 0C00 NOP
+4391: {\r
+4392: /* The task should not have been on an event list. */\r
+4393: configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\r
+BFD03200 0010FC5E LW V0, 16(S8)
+BFD03204 692A LW V0, 40(V0)
+BFD03206 000940E2 BEQZC V0, 0xBFD0321C
+BFD0320A BFD141A2 LUI V0, 0xBFD1
+BFD0320C 3082BFD1 LDC1 F30, 12418(S1)
+BFD0320E 98103082 ADDIU A0, V0, -26608
+BFD03210 30A09810 SWC1 F0, 12448(S0)
+BFD03212 112930A0 ADDIU A1, ZERO, 4393
+BFD03214 77E81129 ADDI T1, T1, 30696
+BFD03216 4B7E77E8 JALS vAssertCalled
+BFD03218 4B7E LW K1, 120(SP)
+BFD0321A 0C00 NOP
+4394: \r
+4395: if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r
+BFD0321C 805CFC5C LW V0, -32676(GP)
+BFD03220 002740A2 BNEZC V0, 0xBFD03272
+4396: {\r
+4397: ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r
+BFD03224 0010FC5E LW V0, 16(S8)
+BFD03228 6D22 ADDIU V0, V0, 4
+BFD0322A 0C82 MOVE A0, V0
+BFD0322C 00C877E8 JALS uxListRemove
+BFD0322E 0C0000C8 SLL A2, T0, 1
+BFD03230 0C00 NOP
+4398: prvAddTaskToReadyList( pxTCB );\r
+BFD03232 0010FC5E LW V0, 16(S8)
+BFD03236 692B LW V0, 44(V0)
+BFD03238 ED81 LI V1, 1
+BFD0323A 18100062 SLLV V1, V0, V1
+BFD0323C FC5C1810 SB ZERO, -932(S0)
+BFD0323E 8040FC5C LW V0, -32704(GP)
+BFD03242 44D3 OR16 V0, V1
+BFD03244 8040F85C SW V0, -32704(GP)
+BFD03248 0010FC5E LW V0, 16(S8)
+BFD0324C 692B LW V0, 44(V0)
+BFD0324E 2524 SLL V0, V0, 2
+BFD03250 25A4 SLL V1, V0, 2
+BFD03252 05B4 ADDU V1, V0, V1
+BFD03254 BFD241A2 LUI V0, 0xBFD2
+BFD03256 3042BFD2 LDC1 F30, 12354(S2)
+BFD03258 806C3042 ADDIU V0, V0, -32660
+BFD0325C 05A6 ADDU V1, V1, V0
+BFD0325E 0010FC5E LW V0, 16(S8)
+BFD03262 6D22 ADDIU V0, V0, 4
+BFD03264 0C83 MOVE A0, V1
+BFD03266 0CA2 MOVE A1, V0
+BFD03268 3E4A77E8 JALS vListInsertEnd
+BFD0326A 0C003E4A LH S2, 3072(T2)
+BFD0326C 0C00 NOP
+BFD0326E CC0C B 0xBFD03288
+BFD03270 0C00 NOP
+4399: }\r
+4400: else\r
+4401: {\r
+4402: /* The delayed and ready lists cannot be accessed, so hold\r
+4403: this task pending until the scheduler is resumed. */\r
+4404: vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r
+BFD03272 0010FC5E LW V0, 16(S8)
+BFD03274 6D2C0010 EXT ZERO, S0, 20, 14
+BFD03276 6D2C ADDIU V0, V0, 24
+BFD03278 BFD241A3 LUI V1, 0xBFD2
+BFD0327A 3083BFD2 LDC1 F30, 12419(S2)
+BFD0327C 80D03083 ADDIU A0, V1, -32560
+BFD03280 0CA2 MOVE A1, V0
+BFD03282 3E4A77E8 JALS vListInsertEnd
+BFD03284 0C003E4A LH S2, 3072(T2)
+BFD03286 0C00 NOP
+4405: }\r
+4406: \r
+4407: if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\r
+BFD03288 0010FC5E LW V0, 16(S8)
+BFD0328C 69AB LW V1, 44(V0)
+BFD0328E 8030FC5C LW V0, -32720(GP)
+BFD03292 692B LW V0, 44(V0)
+BFD03294 13900062 SLTU V0, V0, V1
+BFD03296 40E21390 ADDI GP, S0, 16610
+BFD03298 000840E2 BEQZC V0, 0xBFD032AC
+4408: {\r
+4409: /* The notified task has a priority above the currently\r
+4410: executing task so a yield is required. */\r
+4411: if( pxHigherPriorityTaskWoken != NULL )\r
+BFD0329C 002CFC5E LW V0, 44(S8)
+BFD032A0 000440E2 BEQZC V0, 0xBFD032AC
+4412: {\r
+4413: *pxHigherPriorityTaskWoken = pdTRUE;\r
+BFD032A4 002CFC5E LW V0, 44(S8)
+BFD032A8 ED81 LI V1, 1
+BFD032AA E9A0 SW V1, 0(V0)
+4414: }\r
+4415: }\r
+4416: else\r
+4417: {\r
+4418: mtCOVERAGE_TEST_MARKER();\r
+4419: }\r
+4420: }\r
+4421: }\r
+4422: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+BFD032AC 0014FC9E LW A0, 20(S8)
+BFD032B0 4D5E77E8 JALS vPortClearInterruptMaskFromISR
+BFD032B2 4D5E ADDIU T2, T2, -1
+BFD032B4 0C00 NOP
+4423: }\r
+BFD032B6 0FBE MOVE SP, S8
+BFD032B8 4BE9 LW RA, 36(SP)
+BFD032BA 4BC8 LW S8, 32(SP)
+BFD032BC 4C15 ADDIU SP, SP, 40
+BFD032BE 459F JR16 RA
+BFD032C0 0C00 NOP
+4424: \r
+4425: #endif /* configUSE_TASK_NOTIFICATIONS */\r
+4426: \r
+4427: /*-----------------------------------------------------------*/\r
+4428: \r
+4429: \r
+4430: #ifdef FREERTOS_MODULE_TEST\r
+4431: #include "tasks_test_access_functions.h"\r
+4432: #endif\r
+4433: \r
+--- c:/e/dev/freertos/workingcopy/freertos/source/queue.c ---------------------------------------------
+1: /*\r
+2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+3: All rights reserved\r
+4: \r
+5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+6: \r
+7: This file is part of the FreeRTOS distribution.\r
+8: \r
+9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
+10: the terms of the GNU General Public License (version 2) as published by the\r
+11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+12: \r
+13: ***************************************************************************\r
+14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+15: >>! distribute a combined work that includes FreeRTOS without being !<<\r
+16: >>! obliged to provide the source code for proprietary components !<<\r
+17: >>! outside of the FreeRTOS kernel. !<<\r
+18: ***************************************************************************\r
+19: \r
+20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+22: FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+23: link: http://www.freertos.org/a00114.html\r
+24: \r
+25: ***************************************************************************\r
+26: * *\r
+27: * FreeRTOS provides completely free yet professionally developed, *\r
+28: * robust, strictly quality controlled, supported, and cross *\r
+29: * platform software that is more than just the market leader, it *\r
+30: * is the industry's de facto standard. *\r
+31: * *\r
+32: * Help yourself get started quickly while simultaneously helping *\r
+33: * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+34: * tutorial book, reference manual, or both: *\r
+35: * http://www.FreeRTOS.org/Documentation *\r
+36: * *\r
+37: ***************************************************************************\r
+38: \r
+39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+40: the FAQ page "My application does not run, what could be wrong?". Have you\r
+41: defined configASSERT()?\r
+42: \r
+43: http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+44: embedded software for free we request you assist our global community by\r
+45: participating in the support forum.\r
+46: \r
+47: http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+48: be as productive as possible as early as possible. Now you can receive\r
+49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+50: Ltd, and the world's leading authority on the world's leading RTOS.\r
+51: \r
+52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+54: compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+55: \r
+56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+58: \r
+59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+61: licenses offer ticketed support, indemnification and commercial middleware.\r
+62: \r
+63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+64: engineered and independently SIL3 certified version for use in safety and\r
+65: mission critical applications that require provable dependability.\r
+66: \r
+67: 1 tab == 4 spaces!\r
+68: */\r
+69: \r
+70: #include <stdlib.h>\r
+71: #include <string.h>\r
+72: \r
+73: /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+74: all the API functions to use the MPU wrappers. That should only be done when\r
+75: task.h is included from an application file. */\r
+76: #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+77: \r
+78: #include "FreeRTOS.h"\r
+79: #include "task.h"\r
+80: #include "queue.h"\r
+81: \r
+82: #if ( configUSE_CO_ROUTINES == 1 )\r
+83: #include "croutine.h"\r
+84: #endif\r
+85: \r
+86: /* Lint e961 and e750 are suppressed as a MISRA exception justified because the\r
+87: MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the\r
+88: header files above, but not in this file, in order to generate the correct\r
+89: privileged Vs unprivileged linkage and placement. */\r
+90: #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */\r
+91: \r
+92: \r
+93: /* Constants used with the xRxLock and xTxLock structure members. */\r
+94: #define queueUNLOCKED ( ( BaseType_t ) -1 )\r
+95: #define queueLOCKED_UNMODIFIED ( ( BaseType_t ) 0 )\r
+96: \r
+97: /* When the Queue_t structure is used to represent a base queue its pcHead and\r
+98: pcTail members are used as pointers into the queue storage area. When the\r
+99: Queue_t structure is used to represent a mutex pcHead and pcTail pointers are\r
+100: not necessary, and the pcHead pointer is set to NULL to indicate that the\r
+101: pcTail pointer actually points to the mutex holder (if any). Map alternative\r
+102: names to the pcHead and pcTail structure members to ensure the readability of\r
+103: the code is maintained despite this dual use of two structure members. An\r
+104: alternative implementation would be to use a union, but use of a union is\r
+105: against the coding standard (although an exception to the standard has been\r
+106: permitted where the dual use also significantly changes the type of the\r
+107: structure member). */\r
+108: #define pxMutexHolder pcTail\r
+109: #define uxQueueType pcHead\r
+110: #define queueQUEUE_IS_MUTEX NULL\r
+111: \r
+112: /* Semaphores do not actually store or copy data, so have an item size of\r
+113: zero. */\r
+114: #define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )\r
+115: #define queueMUTEX_GIVE_BLOCK_TIME ( ( TickType_t ) 0U )\r
+116: \r
+117: #if( configUSE_PREEMPTION == 0 )\r
+118: /* If the cooperative scheduler is being used then a yield should not be\r
+119: performed just because a higher priority task has been woken. */\r
+120: #define queueYIELD_IF_USING_PREEMPTION()\r
+121: #else\r
+122: #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()\r
+123: #endif\r
+124: \r
+125: /*\r
+126: * Definition of the queue used by the scheduler.\r
+127: * Items are queued by copy, not reference. See the following link for the\r
+128: * rationale: http://www.freertos.org/Embedded-RTOS-Queues.html\r
+129: */\r
+130: typedef struct QueueDefinition\r
+131: {\r
+132: int8_t *pcHead; /*< Points to the beginning of the queue storage area. */\r
+133: int8_t *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */\r
+134: int8_t *pcWriteTo; /*< Points to the free next place in the storage area. */\r
+135: \r
+136: union /* Use of a union is an exception to the coding standard to ensure two mutually exclusive structure members don't appear simultaneously (wasting RAM). */\r
+137: {\r
+138: int8_t *pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */\r
+139: UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */\r
+140: } u;\r
+141: \r
+142: List_t xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */\r
+143: List_t xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */\r
+144: \r
+145: volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */\r
+146: UBaseType_t uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */\r
+147: UBaseType_t uxItemSize; /*< The size of each items that the queue will hold. */\r
+148: \r
+149: volatile BaseType_t xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */\r
+150: volatile BaseType_t xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */\r
+151: \r
+152: #if ( configUSE_TRACE_FACILITY == 1 )\r
+153: UBaseType_t uxQueueNumber;\r
+154: uint8_t ucQueueType;\r
+155: #endif\r
+156: \r
+157: #if ( configUSE_QUEUE_SETS == 1 )\r
+158: struct QueueDefinition *pxQueueSetContainer;\r
+159: #endif\r
+160: \r
+161: } xQUEUE;\r
+162: \r
+163: /* The old xQUEUE name is maintained above then typedefed to the new Queue_t\r
+164: name below to enable the use of older kernel aware debuggers. */\r
+165: typedef xQUEUE Queue_t;\r
+166: \r
+167: /*-----------------------------------------------------------*/\r
+168: \r
+169: /*\r
+170: * The queue registry is just a means for kernel aware debuggers to locate\r
+171: * queue structures. It has no other purpose so is an optional component.\r
+172: */\r
+173: #if ( configQUEUE_REGISTRY_SIZE > 0 )\r
+174: \r
+175: /* The type stored within the queue registry array. This allows a name\r
+176: to be assigned to each queue making kernel aware debugging a little\r
+177: more user friendly. */\r
+178: typedef struct QUEUE_REGISTRY_ITEM\r
+179: {\r
+180: const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r
+181: QueueHandle_t xHandle;\r
+182: } xQueueRegistryItem;\r
+183: \r
+184: /* The old xQueueRegistryItem name is maintained above then typedefed to the\r
+185: new xQueueRegistryItem name below to enable the use of older kernel aware\r
+186: debuggers. */\r
+187: typedef xQueueRegistryItem QueueRegistryItem_t;\r
+188: \r
+189: /* The queue registry is simply an array of QueueRegistryItem_t structures.\r
+190: The pcQueueName member of a structure being NULL is indicative of the\r
+191: array position being vacant. */\r
+192: PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];\r
+193: \r
+194: #endif /* configQUEUE_REGISTRY_SIZE */\r
+195: \r
+196: /*\r
+197: * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not\r
+198: * prevent an ISR from adding or removing items to the queue, but does prevent\r
+199: * an ISR from removing tasks from the queue event lists. If an ISR finds a\r
+200: * queue is locked it will instead increment the appropriate queue lock count\r
+201: * to indicate that a task may require unblocking. When the queue in unlocked\r
+202: * these lock counts are inspected, and the appropriate action taken.\r
+203: */\r
+204: static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;\r
+205: \r
+206: /*\r
+207: * Uses a critical section to determine if there is any data in a queue.\r
+208: *\r
+209: * @return pdTRUE if the queue contains no items, otherwise pdFALSE.\r
+210: */\r
+211: static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;\r
+212: \r
+213: /*\r
+214: * Uses a critical section to determine if there is any space in a queue.\r
+215: *\r
+216: * @return pdTRUE if there is no space, otherwise pdFALSE;\r
+217: */\r
+218: static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;\r
+219: \r
+220: /*\r
+221: * Copies an item into the queue, either at the front of the queue or the\r
+222: * back of the queue.\r
+223: */\r
+224: static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;\r
+225: \r
+226: /*\r
+227: * Copies an item out of a queue.\r
+228: */\r
+229: static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;\r
+230: \r
+231: #if ( configUSE_QUEUE_SETS == 1 )\r
+232: /*\r
+233: * Checks to see if a queue is a member of a queue set, and if so, notifies\r
+234: * the queue set that the queue contains data.\r
+235: */\r
+236: static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;\r
+237: #endif\r
+238: \r
+239: /*-----------------------------------------------------------*/\r
+240: \r
+241: /*\r
+242: * Macro to mark a queue as locked. Locking a queue prevents an ISR from\r
+243: * accessing the queue event lists.\r
+244: */\r
+245: #define prvLockQueue( pxQueue ) \\r
+246: taskENTER_CRITICAL(); \\r
+247: { \\r
+248: if( ( pxQueue )->xRxLock == queueUNLOCKED ) \\r
+249: { \\r
+250: ( pxQueue )->xRxLock = queueLOCKED_UNMODIFIED; \\r
+251: } \\r
+252: if( ( pxQueue )->xTxLock == queueUNLOCKED ) \\r
+253: { \\r
+254: ( pxQueue )->xTxLock = queueLOCKED_UNMODIFIED; \\r
+255: } \\r
+256: } \\r
+257: taskEXIT_CRITICAL()\r
+258: /*-----------------------------------------------------------*/\r
+259: \r
+260: BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )\r
+261: {\r
+BFD0388C 4FF1 ADDIU SP, SP, -32
+BFD0388E CBE7 SW RA, 28(SP)
+BFD03890 CBC6 SW S8, 24(SP)
+BFD03892 0FDD MOVE S8, SP
+BFD03894 0020F89E SW A0, 32(S8)
+BFD03898 0024F8BE SW A1, 36(S8)
+262: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+BFD0389C 0020FC5E LW V0, 32(S8)
+BFD038A0 0010F85E SW V0, 16(S8)
+263: \r
+264: configASSERT( pxQueue );\r
+BFD038A4 0010FC5E LW V0, 16(S8)
+BFD038A8 000940A2 BNEZC V0, 0xBFD038BE
+BFD038AC BFD141A2 LUI V0, 0xBFD1
+BFD038AE 3082BFD1 LDC1 F30, 12418(S1)
+BFD038B0 9E3C3082 ADDIU A0, V0, -25028
+BFD038B2 30A09E3C LWC1 F17, 12448(GP)
+BFD038B4 010830A0 ADDIU A1, ZERO, 264
+BFD038B8 4B7E77E8 JALS vAssertCalled
+BFD038BA 4B7E LW K1, 120(SP)
+BFD038BC 0C00 NOP
+265: \r
+266: taskENTER_CRITICAL();\r
+BFD038BE 33B877E8 JALS vTaskEnterCritical
+BFD038C0 0C0033B8 ADDIU SP, T8, 3072
+BFD038C2 0C00 NOP
+267: {\r
+268: pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );\r
+BFD038C4 0010FC5E LW V0, 16(S8)
+BFD038C8 6920 LW V0, 0(V0)
+BFD038CA 0010FC7E LW V1, 16(S8)
+BFD038CE 6A3F LW A0, 60(V1)
+BFD038D0 0010FC7E LW V1, 16(S8)
+BFD038D4 0040FC63 LW V1, 64(V1)
+BFD038D8 1A100064 MUL V1, A0, V1
+BFD038DA 05B41A10 SB S0, 1460(S0)
+BFD038DC 05B4 ADDU V1, V0, V1
+BFD038DE 0010FC5E LW V0, 16(S8)
+BFD038E2 E9A1 SW V1, 4(V0)
+269: pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;\r
+BFD038E4 0010FC5E LW V0, 16(S8)
+BFD038E8 E82E SW S0, 56(V0)
+270: pxQueue->pcWriteTo = pxQueue->pcHead;\r
+BFD038EA 0010FC5E LW V0, 16(S8)
+BFD038EE 69A0 LW V1, 0(V0)
+BFD038F0 0010FC5E LW V0, 16(S8)
+BFD038F4 E9A2 SW V1, 8(V0)
+271: pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );\r
+BFD038F6 0010FC5E LW V0, 16(S8)
+BFD038FA 6920 LW V0, 0(V0)
+BFD038FC 0010FC7E LW V1, 16(S8)
+BFD03900 69BF LW V1, 60(V1)
+BFD03902 6E3E ADDIU A0, V1, -1
+BFD03904 0010FC7E LW V1, 16(S8)
+BFD03908 0040FC63 LW V1, 64(V1)
+BFD0390C 1A100064 MUL V1, A0, V1
+BFD0390E 05B41A10 SB S0, 1460(S0)
+BFD03910 05B4 ADDU V1, V0, V1
+BFD03912 0010FC5E LW V0, 16(S8)
+BFD03916 E9A3 SW V1, 12(V0)
+272: pxQueue->xRxLock = queueUNLOCKED;\r
+BFD03918 0010FC5E LW V0, 16(S8)
+BFD0391C EDFF LI V1, -1
+BFD0391E 0044F862 SW V1, 68(V0)
+273: pxQueue->xTxLock = queueUNLOCKED;\r
+BFD03922 0010FC5E LW V0, 16(S8)
+BFD03926 EDFF LI V1, -1
+BFD03928 0048F862 SW V1, 72(V0)
+274: \r
+275: if( xNewQueue == pdFALSE )\r
+BFD0392C 0024FC5E LW V0, 36(S8)
+BFD03930 002340A2 BNEZC V0, 0xBFD0397A
+276: {\r
+277: /* If there are tasks blocked waiting to read from the queue, then\r
+278: the tasks will remain blocked as after this function exits the queue\r
+279: will still be empty. If there are tasks blocked waiting to write to\r
+280: the queue, then one should be unblocked as after this function exits\r
+281: it will be possible to write to it. */\r
+282: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+BFD03934 0010FC5E LW V0, 16(S8)
+BFD03938 6924 LW V0, 16(V0)
+BFD0393A 002D40E2 BEQZC V0, 0xBFD03998
+283: {\r
+284: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r
+BFD0393E 0010FC5E LW V0, 16(S8)
+BFD03942 6D28 ADDIU V0, V0, 16
+BFD03944 0C82 MOVE A0, V0
+BFD03946 22BC77E8 JALS xTaskRemoveFromEventList
+BFD03948 0C0022BC LWC2 S5, 3072(GP)
+BFD0394A 0C00 NOP
+BFD0394C 0C62 MOVE V1, V0
+BFD0394E ED01 LI V0, 1
+BFD03950 0022B443 BNE V1, V0, 0xBFD03998
+BFD03952 0C000022 SLL AT, V0, 1
+BFD03954 0C00 NOP
+285: {\r
+286: queueYIELD_IF_USING_PREEMPTION();\r
+BFD03956 4E1677E8 JALS ulPortGetCP0Cause
+BFD03958 4E16 ADDIU S0, S0, -5
+BFD0395A 0C00 NOP
+BFD0395C 0014F85E SW V0, 20(S8)
+BFD03960 0014FC5E LW V0, 20(S8)
+BFD03964 01005042 ORI V0, V0, 256
+BFD03968 0014F85E SW V0, 20(S8)
+BFD0396C 0014FC9E LW A0, 20(S8)
+BFD03970 4E2677E8 JALS vPortSetCP0Cause
+BFD03972 4E26 ADDIU S1, S1, 3
+BFD03974 0C00 NOP
+BFD03976 CC10 B 0xBFD03998
+BFD03978 0C00 NOP
+287: }\r
+288: else\r
+289: {\r
+290: mtCOVERAGE_TEST_MARKER();\r
+291: }\r
+292: }\r
+293: else\r
+294: {\r
+295: mtCOVERAGE_TEST_MARKER();\r
+296: }\r
+297: }\r
+298: else\r
+299: {\r
+300: /* Ensure the event queues start in the correct state. */\r
+301: vListInitialise( &( pxQueue->xTasksWaitingToSend ) );\r
+BFD0397A 0010FC5E LW V0, 16(S8)
+BFD0397E 6D28 ADDIU V0, V0, 16
+BFD03980 0C82 MOVE A0, V0
+BFD03982 457077E8 JALS vListInitialise
+BFD03984 4570 SWM16 0x3, 0(SP)
+BFD03986 0C00 NOP
+302: vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );\r
+BFD03988 0010FC5E LW V0, 16(S8)
+BFD0398C 00243042 ADDIU V0, V0, 36
+BFD03990 0C82 MOVE A0, V0
+BFD03992 457077E8 JALS vListInitialise
+BFD03994 4570 SWM16 0x3, 0(SP)
+BFD03996 0C00 NOP
+303: }\r
+304: }\r
+305: taskEXIT_CRITICAL();\r
+BFD03998 40AA77E8 JALS vTaskExitCritical
+BFD0399A 0C0040AA BNEZC T2, 0xBFD0519E
+BFD0399C 0C00 NOP
+306: \r
+307: /* A value is returned for calling semantic consistency with previous\r
+308: versions. */\r
+309: return pdPASS;\r
+BFD0399E ED01 LI V0, 1
+310: }\r
+BFD039A0 0FBE MOVE SP, S8
+BFD039A2 4BE7 LW RA, 28(SP)
+BFD039A4 4BC6 LW S8, 24(SP)
+BFD039A6 4C11 ADDIU SP, SP, 32
+BFD039A8 459F JR16 RA
+BFD039AA 0C00 NOP
+311: /*-----------------------------------------------------------*/\r
+312: \r
+313: QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )\r
+314: {\r
+BFD03DF4 4FED ADDIU SP, SP, -40
+BFD03DF6 CBE9 SW RA, 36(SP)
+BFD03DF8 CBC8 SW S8, 32(SP)
+BFD03DFA 0FDD MOVE S8, SP
+BFD03DFC 0028F89E SW A0, 40(S8)
+BFD03E00 002CF8BE SW A1, 44(S8)
+BFD03E04 0C46 MOVE V0, A2
+BFD03E06 0030185E SB V0, 48(S8)
+315: Queue_t *pxNewQueue;\r
+316: size_t xQueueSizeInBytes;\r
+317: QueueHandle_t xReturn = NULL;\r
+BFD03E0A 0014F81E SW ZERO, 20(S8)
+318: int8_t *pcAllocatedBuffer;\r
+319: \r
+320: /* Remove compiler warnings about unused parameters should\r
+321: configUSE_TRACE_FACILITY not be set to 1. */\r
+322: ( void ) ucQueueType;\r
+323: \r
+324: configASSERT( uxQueueLength > ( UBaseType_t ) 0 );\r
+BFD03E0E 0028FC5E LW V0, 40(S8)
+BFD03E12 000940A2 BNEZC V0, 0xBFD03E28
+BFD03E16 BFD141A2 LUI V0, 0xBFD1
+BFD03E18 3082BFD1 LDC1 F30, 12418(S1)
+BFD03E1A 9E3C3082 ADDIU A0, V0, -25028
+BFD03E1C 30A09E3C LWC1 F17, 12448(GP)
+BFD03E1E 014430A0 ADDIU A1, ZERO, 324
+BFD03E22 4B7E77E8 JALS vAssertCalled
+BFD03E24 4B7E LW K1, 120(SP)
+BFD03E26 0C00 NOP
+325: \r
+326: if( uxItemSize == ( UBaseType_t ) 0 )\r
+BFD03E28 002CFC5E LW V0, 44(S8)
+BFD03E2C 000440A2 BNEZC V0, 0xBFD03E38
+327: {\r
+328: /* There is not going to be a queue storage area. */\r
+329: xQueueSizeInBytes = ( size_t ) 0;\r
+BFD03E30 0010F81E SW ZERO, 16(S8)
+BFD03E34 CC0A B 0xBFD03E4A
+BFD03E36 0C00 NOP
+330: }\r
+331: else\r
+332: {\r
+333: /* The queue is one byte longer than asked for to make wrap checking\r
+334: easier/faster. */\r
+335: xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
+BFD03E38 0028FC7E LW V1, 40(S8)
+BFD03E3C 002CFC5E LW V0, 44(S8)
+BFD03E40 12100043 MUL V0, V1, V0
+BFD03E42 6D201210 ADDI S0, S0, 27936
+BFD03E44 6D20 ADDIU V0, V0, 1
+BFD03E46 0010F85E SW V0, 16(S8)
+336: }\r
+337: \r
+338: /* Allocate the new queue structure and storage area. */\r
+339: pcAllocatedBuffer = ( int8_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );\r
+BFD03E4A 0010FC5E LW V0, 16(S8)
+BFD03E4E 00503042 ADDIU V0, V0, 80
+BFD03E52 0C82 MOVE A0, V0
+BFD03E54 111677E8 JALS pvPortMalloc
+BFD03E56 0C001116 ADDI T0, S6, 3072
+BFD03E58 0C00 NOP
+BFD03E5A 0018F85E SW V0, 24(S8)
+340: \r
+341: if( pcAllocatedBuffer != NULL )\r
+BFD03E5E 0018FC5E LW V0, 24(S8)
+BFD03E62 002F40E2 BEQZC V0, 0xBFD03EC4
+342: {\r
+343: pxNewQueue = ( Queue_t * ) pcAllocatedBuffer; /*lint !e826 MISRA The buffer cannot be too small because it was dimensioned by sizeof( Queue_t ) + xQueueSizeInBytes. */\r
+BFD03E66 0018FC5E LW V0, 24(S8)
+BFD03E6A 001CF85E SW V0, 28(S8)
+344: \r
+345: if( uxItemSize == ( UBaseType_t ) 0 )\r
+BFD03E6E 002CFC5E LW V0, 44(S8)
+BFD03E72 000740A2 BNEZC V0, 0xBFD03E84
+346: {\r
+347: /* No RAM was allocated for the queue storage area, but PC head\r
+348: cannot be set to NULL because NULL is used as a key to say the queue\r
+349: is used as a mutex. Therefore just set pcHead to point to the queue\r
+350: as a benign value that is known to be within the memory map. */\r
+351: pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;\r
+BFD03E76 001CFC7E LW V1, 28(S8)
+BFD03E7A 001CFC5E LW V0, 28(S8)
+BFD03E7E E9A0 SW V1, 0(V0)
+BFD03E80 CC08 B 0xBFD03E92
+BFD03E82 0C00 NOP
+352: }\r
+353: else\r
+354: {\r
+355: /* Jump past the queue structure to find the location of the queue\r
+356: storage area - adding the padding bytes to get a better alignment. */\r
+357: pxNewQueue->pcHead = pcAllocatedBuffer + sizeof( Queue_t );\r
+BFD03E84 0018FC5E LW V0, 24(S8)
+BFD03E88 00503062 ADDIU V1, V0, 80
+BFD03E8C 001CFC5E LW V0, 28(S8)
+BFD03E90 E9A0 SW V1, 0(V0)
+358: }\r
+359: \r
+360: /* Initialise the queue members as described above where the queue type\r
+361: is defined. */\r
+362: pxNewQueue->uxLength = uxQueueLength;\r
+BFD03E92 001CFC5E LW V0, 28(S8)
+BFD03E96 0028FC7E LW V1, 40(S8)
+BFD03E9A E9AF SW V1, 60(V0)
+363: pxNewQueue->uxItemSize = uxItemSize;\r
+BFD03E9C 001CFC5E LW V0, 28(S8)
+BFD03EA0 002CFC7E LW V1, 44(S8)
+BFD03EA4 0040F862 SW V1, 64(V0)
+364: ( void ) xQueueGenericReset( pxNewQueue, pdTRUE );\r
+BFD03EA8 001CFC9E LW A0, 28(S8)
+BFD03EAC EE81 LI A1, 1
+BFD03EAE 1C4677E8 JALS xQueueGenericReset
+BFD03EB0 0C001C46 LB V0, 3072(A2)
+BFD03EB2 0C00 NOP
+365: \r
+366: #if ( configUSE_TRACE_FACILITY == 1 )\r
+367: {\r
+368: pxNewQueue->ucQueueType = ucQueueType;\r
+369: }\r
+370: #endif /* configUSE_TRACE_FACILITY */\r
+371: \r
+372: #if( configUSE_QUEUE_SETS == 1 )\r
+373: {\r
+374: pxNewQueue->pxQueueSetContainer = NULL;\r
+BFD03EB4 001CFC5E LW V0, 28(S8)
+BFD03EB8 004CF802 SW ZERO, 76(V0)
+375: }\r
+376: #endif /* configUSE_QUEUE_SETS */\r
+377: \r
+378: traceQUEUE_CREATE( pxNewQueue );\r
+379: xReturn = pxNewQueue;\r
+BFD03EBC 001CFC5E LW V0, 28(S8)
+BFD03EC0 0014F85E SW V0, 20(S8)
+380: }\r
+381: else\r
+382: {\r
+383: mtCOVERAGE_TEST_MARKER();\r
+384: }\r
+385: \r
+386: configASSERT( xReturn );\r
+BFD03EC4 0014FC5E LW V0, 20(S8)
+BFD03EC8 000940A2 BNEZC V0, 0xBFD03EDE
+BFD03ECC BFD141A2 LUI V0, 0xBFD1
+BFD03ECE 3082BFD1 LDC1 F30, 12418(S1)
+BFD03ED0 9E3C3082 ADDIU A0, V0, -25028
+BFD03ED2 30A09E3C LWC1 F17, 12448(GP)
+BFD03ED4 018230A0 ADDIU A1, ZERO, 386
+BFD03ED8 4B7E77E8 JALS vAssertCalled
+BFD03EDA 4B7E LW K1, 120(SP)
+BFD03EDC 0C00 NOP
+387: \r
+388: return xReturn;\r
+BFD03EDE 0014FC5E LW V0, 20(S8)
+389: }\r
+BFD03EE2 0FBE MOVE SP, S8
+BFD03EE4 4BE9 LW RA, 36(SP)
+BFD03EE6 4BC8 LW S8, 32(SP)
+BFD03EE8 4C15 ADDIU SP, SP, 40
+BFD03EEA 459F JR16 RA
+BFD03EEC 0C00 NOP
+390: /*-----------------------------------------------------------*/\r
+391: \r
+392: #if ( configUSE_MUTEXES == 1 )\r
+393: \r
+394: QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )\r
+395: {\r
+BFD05958 4FF1 ADDIU SP, SP, -32
+BFD0595A CBE7 SW RA, 28(SP)
+BFD0595C CBC6 SW S8, 24(SP)
+BFD0595E 0FDD MOVE S8, SP
+BFD05960 0C44 MOVE V0, A0
+BFD05962 0020185E SB V0, 32(S8)
+BFD05964 EE500020 AND SP, ZERO, AT
+396: Queue_t *pxNewQueue;\r
+397: \r
+398: /* Prevent compiler warnings about unused parameters if\r
+399: configUSE_TRACE_FACILITY does not equal 1. */\r
+400: ( void ) ucQueueType;\r
+401: \r
+402: /* Allocate the new queue structure. */\r
+403: pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) );\r
+BFD05966 EE50 LI A0, 80
+BFD05968 111677E8 JALS pvPortMalloc
+BFD0596A 0C001116 ADDI T0, S6, 3072
+BFD0596C 0C00 NOP
+BFD0596E 0010F85E SW V0, 16(S8)
+404: if( pxNewQueue != NULL )\r
+BFD05972 0010FC5E LW V0, 16(S8)
+BFD05976 003C40E2 BEQZC V0, 0xBFD059F2
+405: {\r
+406: /* Information required for priority inheritance. */\r
+407: pxNewQueue->pxMutexHolder = NULL;\r
+BFD0597A 0010FC5E LW V0, 16(S8)
+BFD0597E E821 SW S0, 4(V0)
+408: pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;\r
+BFD05980 0010FC5E LW V0, 16(S8)
+BFD05984 E820 SW S0, 0(V0)
+409: \r
+410: /* Queues used as a mutex no data is actually copied into or out\r
+411: of the queue. */\r
+412: pxNewQueue->pcWriteTo = NULL;\r
+BFD05986 0010FC5E LW V0, 16(S8)
+BFD0598A E822 SW S0, 8(V0)
+413: pxNewQueue->u.pcReadFrom = NULL;\r
+BFD0598C 0010FC5E LW V0, 16(S8)
+BFD05990 E823 SW S0, 12(V0)
+414: \r
+415: /* Each mutex has a length of 1 (like a binary semaphore) and\r
+416: an item size of 0 as nothing is actually copied into or out\r
+417: of the mutex. */\r
+418: pxNewQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;\r
+BFD05992 0010FC5E LW V0, 16(S8)
+BFD05996 E82E SW S0, 56(V0)
+419: pxNewQueue->uxLength = ( UBaseType_t ) 1U;\r
+BFD05998 0010FC5E LW V0, 16(S8)
+BFD0599C ED81 LI V1, 1
+BFD0599E E9AF SW V1, 60(V0)
+420: pxNewQueue->uxItemSize = ( UBaseType_t ) 0U;\r
+BFD059A0 0010FC5E LW V0, 16(S8)
+BFD059A4 0040F802 SW ZERO, 64(V0)
+421: pxNewQueue->xRxLock = queueUNLOCKED;\r
+BFD059A8 0010FC5E LW V0, 16(S8)
+BFD059AC EDFF LI V1, -1
+BFD059AE 0044F862 SW V1, 68(V0)
+422: pxNewQueue->xTxLock = queueUNLOCKED;\r
+BFD059B2 0010FC5E LW V0, 16(S8)
+BFD059B6 EDFF LI V1, -1
+BFD059B8 0048F862 SW V1, 72(V0)
+423: \r
+424: #if ( configUSE_TRACE_FACILITY == 1 )\r
+425: {\r
+426: pxNewQueue->ucQueueType = ucQueueType;\r
+427: }\r
+428: #endif\r
+429: \r
+430: #if ( configUSE_QUEUE_SETS == 1 )\r
+431: {\r
+432: pxNewQueue->pxQueueSetContainer = NULL;\r
+BFD059BC 0010FC5E LW V0, 16(S8)
+BFD059C0 004CF802 SW ZERO, 76(V0)
+433: }\r
+434: #endif\r
+435: \r
+436: /* Ensure the event queues start with the correct state. */\r
+437: vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );\r
+BFD059C4 0010FC5E LW V0, 16(S8)
+BFD059C8 6D28 ADDIU V0, V0, 16
+BFD059CA 0C82 MOVE A0, V0
+BFD059CC 457077E8 JALS vListInitialise
+BFD059CE 4570 SWM16 0x3, 0(SP)
+BFD059D0 0C00 NOP
+438: vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );\r
+BFD059D2 0010FC5E LW V0, 16(S8)
+BFD059D6 00243042 ADDIU V0, V0, 36
+BFD059DA 0C82 MOVE A0, V0
+BFD059DC 457077E8 JALS vListInitialise
+BFD059DE 4570 SWM16 0x3, 0(SP)
+BFD059E0 0C00 NOP
+439: \r
+440: traceCREATE_MUTEX( pxNewQueue );\r
+441: \r
+442: /* Start with the semaphore in the expected state. */\r
+443: ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );\r
+BFD059E2 0010FC9E LW A0, 16(S8)
+BFD059E6 0CA0 MOVE A1, ZERO
+BFD059E8 0CC0 MOVE A2, ZERO
+BFD059EA 0CE0 MOVE A3, ZERO
+BFD059EC 06A277E8 JALS xQueueGenericSend
+BFD059EE 06A2 ADDU A1, S1, V0
+BFD059F0 0C00 NOP
+444: }\r
+445: else\r
+446: {\r
+447: traceCREATE_MUTEX_FAILED();\r
+448: }\r
+449: \r
+450: configASSERT( pxNewQueue );\r
+BFD059F2 0010FC5E LW V0, 16(S8)
+BFD059F6 000940A2 BNEZC V0, 0xBFD05A0C
+BFD059FA BFD141A2 LUI V0, 0xBFD1
+BFD059FC 3082BFD1 LDC1 F30, 12418(S1)
+BFD059FE 9E3C3082 ADDIU A0, V0, -25028
+BFD05A00 30A09E3C LWC1 F17, 12448(GP)
+BFD05A02 01C230A0 ADDIU A1, ZERO, 450
+BFD05A06 4B7E77E8 JALS vAssertCalled
+BFD05A08 4B7E LW K1, 120(SP)
+BFD05A0A 0C00 NOP
+451: return pxNewQueue;\r
+BFD05A0C 0010FC5E LW V0, 16(S8)
+452: }\r
+BFD05A10 0FBE MOVE SP, S8
+BFD05A12 4BE7 LW RA, 28(SP)
+BFD05A14 4BC6 LW S8, 24(SP)
+BFD05A16 4C11 ADDIU SP, SP, 32
+BFD05A18 459F JR16 RA
+BFD05A1A 0C00 NOP
+453: \r
+454: #endif /* configUSE_MUTEXES */\r
+455: /*-----------------------------------------------------------*/\r
+456: \r
+457: #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\r
+458: \r
+459: void* xQueueGetMutexHolder( QueueHandle_t xSemaphore )\r
+460: {\r
+461: void *pxReturn;\r
+462: \r
+463: /* This function is called by xSemaphoreGetMutexHolder(), and should not\r
+464: be called directly. Note: This is a good way of determining if the\r
+465: calling task is the mutex holder, but not a good way of determining the\r
+466: identity of the mutex holder, as the holder may change between the\r
+467: following critical section exiting and the function returning. */\r
+468: taskENTER_CRITICAL();\r
+469: {\r
+470: if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )\r
+471: {\r
+472: pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;\r
+473: }\r
+474: else\r
+475: {\r
+476: pxReturn = NULL;\r
+477: }\r
+478: }\r
+479: taskEXIT_CRITICAL();\r
+480: \r
+481: return pxReturn;\r
+482: } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */\r
+483: \r
+484: #endif\r
+485: /*-----------------------------------------------------------*/\r
+486: \r
+487: #if ( configUSE_RECURSIVE_MUTEXES == 1 )\r
+488: \r
+489: BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )\r
+490: {\r
+BFD06AD0 4FED ADDIU SP, SP, -40
+BFD06AD2 CBE9 SW RA, 36(SP)
+BFD06AD4 CBC8 SW S8, 32(SP)
+BFD06AD6 CA07 SW S0, 28(SP)
+BFD06AD8 0FDD MOVE S8, SP
+BFD06ADA 0028F89E SW A0, 40(S8)
+491: BaseType_t xReturn;\r
+492: Queue_t * const pxMutex = ( Queue_t * ) xMutex;\r
+BFD06ADE 0028FC5E LW V0, 40(S8)
+BFD06AE2 0014F85E SW V0, 20(S8)
+493: \r
+494: configASSERT( pxMutex );\r
+BFD06AE6 0014FC5E LW V0, 20(S8)
+BFD06AEA 000940A2 BNEZC V0, 0xBFD06B00
+BFD06AEE BFD141A2 LUI V0, 0xBFD1
+BFD06AF0 3082BFD1 LDC1 F30, 12418(S1)
+BFD06AF2 9E3C3082 ADDIU A0, V0, -25028
+BFD06AF4 30A09E3C LWC1 F17, 12448(GP)
+BFD06AF6 01EE30A0 ADDIU A1, ZERO, 494
+BFD06AFA 4B7E77E8 JALS vAssertCalled
+BFD06AFC 4B7E LW K1, 120(SP)
+BFD06AFE 0C00 NOP
+495: \r
+496: /* If this is the task that holds the mutex then pxMutexHolder will not\r
+497: change outside of this task. If this task does not hold the mutex then\r
+498: pxMutexHolder can never coincidentally equal the tasks handle, and as\r
+499: this is the only condition we are interested in it does not matter if\r
+500: pxMutexHolder is accessed simultaneously by another task. Therefore no\r
+501: mutual exclusion is required to test the pxMutexHolder variable. */\r
+502: if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */\r
+BFD06B00 0014FC5E LW V0, 20(S8)
+BFD06B04 6821 LW S0, 4(V0)
+BFD06B06 4F0277E8 JALS xTaskGetCurrentTaskHandle
+BFD06B08 4F02 ADDIU T8, T8, 1
+BFD06B0A 0C00 NOP
+BFD06B0C 001AB450 BNE S0, V0, 0xBFD06B44
+BFD06B0E 0C00001A SLL ZERO, K0, 1
+BFD06B10 0C00 NOP
+503: {\r
+504: traceGIVE_MUTEX_RECURSIVE( pxMutex );\r
+505: \r
+506: /* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to\r
+507: the task handle, therefore no underflow check is required. Also,\r
+508: uxRecursiveCallCount is only modified by the mutex holder, and as\r
+509: there can only be one, no mutual exclusion is required to modify the\r
+510: uxRecursiveCallCount member. */\r
+511: ( pxMutex->u.uxRecursiveCallCount )--;\r
+BFD06B12 0014FC5E LW V0, 20(S8)
+BFD06B16 6923 LW V0, 12(V0)
+BFD06B18 6DAE ADDIU V1, V0, -1
+BFD06B1A 0014FC5E LW V0, 20(S8)
+BFD06B1E E9A3 SW V1, 12(V0)
+512: \r
+513: /* Have we unwound the call count? */\r
+514: if( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 )\r
+BFD06B20 0014FC5E LW V0, 20(S8)
+BFD06B24 6923 LW V0, 12(V0)
+BFD06B26 000840A2 BNEZC V0, 0xBFD06B3A
+515: {\r
+516: /* Return the mutex. This will automatically unblock any other\r
+517: task that might be waiting to access the mutex. */\r
+518: ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );\r
+BFD06B2A 0014FC9E LW A0, 20(S8)
+BFD06B2E 0CA0 MOVE A1, ZERO
+BFD06B30 0CC0 MOVE A2, ZERO
+BFD06B32 0CE0 MOVE A3, ZERO
+BFD06B34 06A277E8 JALS xQueueGenericSend
+BFD06B36 06A2 ADDU A1, S1, V0
+BFD06B38 0C00 NOP
+519: }\r
+520: else\r
+521: {\r
+522: mtCOVERAGE_TEST_MARKER();\r
+523: }\r
+524: \r
+525: xReturn = pdPASS;\r
+BFD06B3A ED01 LI V0, 1
+BFD06B3C 0010F85E SW V0, 16(S8)
+BFD06B40 CC03 B 0xBFD06B48
+BFD06B42 0C00 NOP
+526: }\r
+527: else\r
+528: {\r
+529: /* The mutex cannot be given because the calling task is not the\r
+530: holder. */\r
+531: xReturn = pdFAIL;\r
+BFD06B44 0010F81E SW ZERO, 16(S8)
+532: \r
+533: traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );\r
+534: }\r
+535: \r
+536: return xReturn;\r
+BFD06B48 0010FC5E LW V0, 16(S8)
+537: }\r
+BFD06B4C 0FBE MOVE SP, S8
+BFD06B4E 4BE9 LW RA, 36(SP)
+BFD06B50 4BC8 LW S8, 32(SP)
+BFD06B52 4A07 LW S0, 28(SP)
+BFD06B54 4C15 ADDIU SP, SP, 40
+BFD06B56 459F JR16 RA
+BFD06B58 0C00 NOP
+538: \r
+539: #endif /* configUSE_RECURSIVE_MUTEXES */\r
+540: /*-----------------------------------------------------------*/\r
+541: \r
+542: #if ( configUSE_RECURSIVE_MUTEXES == 1 )\r
+543: \r
+544: BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )\r
+545: {\r
+BFD063CC 4FED ADDIU SP, SP, -40
+BFD063CE CBE9 SW RA, 36(SP)
+BFD063D0 CBC8 SW S8, 32(SP)
+BFD063D2 CA07 SW S0, 28(SP)
+BFD063D4 0FDD MOVE S8, SP
+BFD063D6 0028F89E SW A0, 40(S8)
+BFD063DA 002CF8BE SW A1, 44(S8)
+546: BaseType_t xReturn;\r
+547: Queue_t * const pxMutex = ( Queue_t * ) xMutex;\r
+BFD063DE 0028FC5E LW V0, 40(S8)
+BFD063E2 0014F85E SW V0, 20(S8)
+548: \r
+549: configASSERT( pxMutex );\r
+BFD063E6 0014FC5E LW V0, 20(S8)
+BFD063EA 000940A2 BNEZC V0, 0xBFD06400
+BFD063EE BFD141A2 LUI V0, 0xBFD1
+BFD063F0 3082BFD1 LDC1 F30, 12418(S1)
+BFD063F2 9E3C3082 ADDIU A0, V0, -25028
+BFD063F4 30A09E3C LWC1 F17, 12448(GP)
+BFD063F6 022530A0 ADDIU A1, ZERO, 549
+BFD063FA 4B7E77E8 JALS vAssertCalled
+BFD063FC 4B7E LW K1, 120(SP)
+BFD063FE 0C00 NOP
+550: \r
+551: /* Comments regarding mutual exclusion as per those within\r
+552: xQueueGiveMutexRecursive(). */\r
+553: \r
+554: traceTAKE_MUTEX_RECURSIVE( pxMutex );\r
+555: \r
+556: if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */\r
+BFD06400 0014FC5E LW V0, 20(S8)
+BFD06404 6821 LW S0, 4(V0)
+BFD06406 4F0277E8 JALS xTaskGetCurrentTaskHandle
+BFD06408 4F02 ADDIU T8, T8, 1
+BFD0640A 0C00 NOP
+BFD0640C 000DB450 BNE S0, V0, 0xBFD0642A
+BFD0640E 0C00000D SLL ZERO, T5, 1
+BFD06410 0C00 NOP
+557: {\r
+558: ( pxMutex->u.uxRecursiveCallCount )++;\r
+BFD06412 0014FC5E LW V0, 20(S8)
+BFD06416 6923 LW V0, 12(V0)
+BFD06418 6DA0 ADDIU V1, V0, 1
+BFD0641A 0014FC5E LW V0, 20(S8)
+BFD0641E E9A3 SW V1, 12(V0)
+559: xReturn = pdPASS;\r
+BFD06420 ED01 LI V0, 1
+BFD06422 0010F85E SW V0, 16(S8)
+BFD06426 CC19 B 0xBFD0645A
+BFD06428 0C00 NOP
+560: }\r
+561: else\r
+562: {\r
+563: xReturn = xQueueGenericReceive( pxMutex, NULL, xTicksToWait, pdFALSE );\r
+BFD0642A 0014FC9E LW A0, 20(S8)
+BFD0642E 0CA0 MOVE A1, ZERO
+BFD06430 002CFCDE LW A2, 44(S8)
+BFD06434 0CE0 MOVE A3, ZERO
+BFD06436 081E77E8 JALS xQueueGenericReceive
+BFD06438 081E LBU S0, 14(S1)
+BFD0643A 0C00 NOP
+BFD0643C 0010F85E SW V0, 16(S8)
+564: \r
+565: /* pdPASS will only be returned if the mutex was successfully\r
+566: obtained. The calling task may have entered the Blocked state\r
+567: before reaching here. */\r
+568: if( xReturn == pdPASS )\r
+BFD06440 0010FC7E LW V1, 16(S8)
+BFD06444 ED01 LI V0, 1
+BFD06446 0008B443 BNE V1, V0, 0xBFD0645A
+BFD06448 0C000008 SLL ZERO, T0, 1
+BFD0644A 0C00 NOP
+569: {\r
+570: ( pxMutex->u.uxRecursiveCallCount )++;\r
+BFD0644C 0014FC5E LW V0, 20(S8)
+BFD06450 6923 LW V0, 12(V0)
+BFD06452 6DA0 ADDIU V1, V0, 1
+BFD06454 0014FC5E LW V0, 20(S8)
+BFD06458 E9A3 SW V1, 12(V0)
+571: }\r
+572: else\r
+573: {\r
+574: traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );\r
+575: }\r
+576: }\r
+577: \r
+578: return xReturn;\r
+BFD0645A 0010FC5E LW V0, 16(S8)
+579: }\r
+BFD0645E 0FBE MOVE SP, S8
+BFD06460 4BE9 LW RA, 36(SP)
+BFD06462 4BC8 LW S8, 32(SP)
+BFD06464 4A07 LW S0, 28(SP)
+BFD06466 4C15 ADDIU SP, SP, 40
+BFD06468 459F JR16 RA
+BFD0646A 0C00 NOP
+580: \r
+581: #endif /* configUSE_RECURSIVE_MUTEXES */\r
+582: /*-----------------------------------------------------------*/\r
+583: \r
+584: #if ( configUSE_COUNTING_SEMAPHORES == 1 )\r
+585: \r
+586: QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )\r
+587: {\r
+BFD0650C 4FF1 ADDIU SP, SP, -32
+BFD0650E CBE7 SW RA, 28(SP)
+BFD06510 CBC6 SW S8, 24(SP)
+BFD06512 0FDD MOVE S8, SP
+BFD06514 0020F89E SW A0, 32(S8)
+BFD06518 0024F8BE SW A1, 36(S8)
+588: QueueHandle_t xHandle;\r
+589: \r
+590: configASSERT( uxMaxCount != 0 );\r
+BFD0651C 0020FC5E LW V0, 32(S8)
+BFD06520 000940A2 BNEZC V0, 0xBFD06536
+BFD06524 BFD141A2 LUI V0, 0xBFD1
+BFD06526 3082BFD1 LDC1 F30, 12418(S1)
+BFD06528 9E3C3082 ADDIU A0, V0, -25028
+BFD0652A 30A09E3C LWC1 F17, 12448(GP)
+BFD0652C 024E30A0 ADDIU A1, ZERO, 590
+BFD06530 4B7E77E8 JALS vAssertCalled
+BFD06532 4B7E LW K1, 120(SP)
+BFD06534 0C00 NOP
+591: configASSERT( uxInitialCount <= uxMaxCount );\r
+BFD06536 0024FC7E LW V1, 36(S8)
+BFD0653A 0020FC5E LW V0, 32(S8)
+BFD0653E 13900062 SLTU V0, V0, V1
+BFD06540 40E21390 ADDI GP, S0, 16610
+BFD06542 000940E2 BEQZC V0, 0xBFD06558
+BFD06546 BFD141A2 LUI V0, 0xBFD1
+BFD06548 3082BFD1 LDC1 F30, 12418(S1)
+BFD0654A 9E3C3082 ADDIU A0, V0, -25028
+BFD0654C 30A09E3C LWC1 F17, 12448(GP)
+BFD0654E 024F30A0 ADDIU A1, ZERO, 591
+BFD06552 4B7E77E8 JALS vAssertCalled
+BFD06554 4B7E LW K1, 120(SP)
+BFD06556 0C00 NOP
+592: \r
+593: xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );\r
+BFD06558 0020FC9E LW A0, 32(S8)
+BFD0655C 0CA0 MOVE A1, ZERO
+BFD0655E EF02 LI A2, 2
+BFD06560 1EFA77E8 JALS xQueueGenericCreate
+BFD06562 0C001EFA LB S7, 3072(K0)
+BFD06564 0C00 NOP
+BFD06566 0010F85E SW V0, 16(S8)
+594: \r
+595: if( xHandle != NULL )\r
+BFD0656A 0010FC5E LW V0, 16(S8)
+BFD0656E 000540E2 BEQZC V0, 0xBFD0657C
+596: {\r
+597: ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;\r
+BFD06572 0010FC5E LW V0, 16(S8)
+BFD06576 0024FC7E LW V1, 36(S8)
+BFD0657A E9AE SW V1, 56(V0)
+598: \r
+599: traceCREATE_COUNTING_SEMAPHORE();\r
+600: }\r
+601: else\r
+602: {\r
+603: traceCREATE_COUNTING_SEMAPHORE_FAILED();\r
+604: }\r
+605: \r
+606: configASSERT( xHandle );\r
+BFD0657C 0010FC5E LW V0, 16(S8)
+BFD06580 000940A2 BNEZC V0, 0xBFD06596
+BFD06584 BFD141A2 LUI V0, 0xBFD1
+BFD06586 3082BFD1 LDC1 F30, 12418(S1)
+BFD06588 9E3C3082 ADDIU A0, V0, -25028
+BFD0658A 30A09E3C LWC1 F17, 12448(GP)
+BFD0658C 025E30A0 ADDIU A1, ZERO, 606
+BFD06590 4B7E77E8 JALS vAssertCalled
+BFD06592 4B7E LW K1, 120(SP)
+BFD06594 0C00 NOP
+607: return xHandle;\r
+BFD06596 0010FC5E LW V0, 16(S8)
+608: }\r
+BFD0659A 0FBE MOVE SP, S8
+BFD0659C 4BE7 LW RA, 28(SP)
+BFD0659E 4BC6 LW S8, 24(SP)
+BFD065A0 4C11 ADDIU SP, SP, 32
+BFD065A2 459F JR16 RA
+BFD065A4 0C00 NOP
+609: \r
+610: #endif /* configUSE_COUNTING_SEMAPHORES */\r
+611: /*-----------------------------------------------------------*/\r
+612: \r
+613: BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )\r
+614: {\r
+BFD00D44 4FE1 ADDIU SP, SP, -64
+BFD00D46 CBEF SW RA, 60(SP)
+BFD00D48 CBCE SW S8, 56(SP)
+BFD00D4A 0FDD MOVE S8, SP
+BFD00D4C 0040F89E SW A0, 64(S8)
+BFD00D50 0044F8BE SW A1, 68(S8)
+BFD00D54 0048F8DE SW A2, 72(S8)
+BFD00D58 004CF8FE SW A3, 76(S8)
+615: BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;\r
+BFD00D5C 0010F81E SW ZERO, 16(S8)
+616: TimeOut_t xTimeOut;\r
+617: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+BFD00D60 0040FC5E LW V0, 64(S8)
+BFD00D64 0014F85E SW V0, 20(S8)
+618: \r
+619: configASSERT( pxQueue );\r
+BFD00D68 0014FC5E LW V0, 20(S8)
+BFD00D6C 000940A2 BNEZC V0, 0xBFD00D82
+BFD00D70 BFD141A2 LUI V0, 0xBFD1
+BFD00D72 3082BFD1 LDC1 F30, 12418(S1)
+BFD00D74 9E3C3082 ADDIU A0, V0, -25028
+BFD00D76 30A09E3C LWC1 F17, 12448(GP)
+BFD00D78 026B30A0 ADDIU A1, ZERO, 619
+BFD00D7C 4B7E77E8 JALS vAssertCalled
+BFD00D7E 4B7E LW K1, 120(SP)
+BFD00D80 0C00 NOP
+620: configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r
+BFD00D82 0044FC5E LW V0, 68(S8)
+BFD00D86 000640A2 BNEZC V0, 0xBFD00D96
+BFD00D8A 0014FC5E LW V0, 20(S8)
+BFD00D8E 0040FC42 LW V0, 64(V0)
+BFD00D92 000340A2 BNEZC V0, 0xBFD00D9C
+BFD00D96 ED01 LI V0, 1
+BFD00D98 CC02 B 0xBFD00D9E
+BFD00D9A 0C00 NOP
+BFD00D9C 0C40 MOVE V0, ZERO
+BFD00D9E 000940A2 BNEZC V0, 0xBFD00DB4
+BFD00DA2 BFD141A2 LUI V0, 0xBFD1
+BFD00DA4 3082BFD1 LDC1 F30, 12418(S1)
+BFD00DA6 9E3C3082 ADDIU A0, V0, -25028
+BFD00DA8 30A09E3C LWC1 F17, 12448(GP)
+BFD00DAA 026C30A0 ADDIU A1, ZERO, 620
+BFD00DAE 4B7E77E8 JALS vAssertCalled
+BFD00DB0 4B7E LW K1, 120(SP)
+BFD00DB2 0C00 NOP
+621: configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );\r
+BFD00DB4 004CFC7E LW V1, 76(S8)
+BFD00DB8 ED02 LI V0, 2
+BFD00DBA 0008B443 BNE V1, V0, 0xBFD00DCE
+BFD00DBC 0C000008 SLL ZERO, T0, 1
+BFD00DBE 0C00 NOP
+BFD00DC0 0014FC5E LW V0, 20(S8)
+BFD00DC4 69AF LW V1, 60(V0)
+BFD00DC6 ED01 LI V0, 1
+BFD00DC8 0004B443 BNE V1, V0, 0xBFD00DD4
+BFD00DCA 0C000004 SLL ZERO, A0, 1
+BFD00DCC 0C00 NOP
+BFD00DCE ED01 LI V0, 1
+BFD00DD0 CC02 B 0xBFD00DD6
+BFD00DD2 0C00 NOP
+BFD00DD4 0C40 MOVE V0, ZERO
+BFD00DD6 000940A2 BNEZC V0, 0xBFD00DEC
+BFD00DDA BFD141A2 LUI V0, 0xBFD1
+BFD00DDC 3082BFD1 LDC1 F30, 12418(S1)
+BFD00DDE 9E3C3082 ADDIU A0, V0, -25028
+BFD00DE0 30A09E3C LWC1 F17, 12448(GP)
+BFD00DE2 026D30A0 ADDIU A1, ZERO, 621
+BFD00DE6 4B7E77E8 JALS vAssertCalled
+BFD00DE8 4B7E LW K1, 120(SP)
+BFD00DEA 0C00 NOP
+622: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r
+623: {\r
+624: configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\r
+BFD00DEC 4A8E77E8 JALS xTaskGetSchedulerState
+BFD00DEE 4A8E LW S4, 56(SP)
+BFD00DF0 0C00 NOP
+BFD00DF2 000440A2 BNEZC V0, 0xBFD00DFE
+BFD00DF6 0048FC5E LW V0, 72(S8)
+BFD00DFA 000340A2 BNEZC V0, 0xBFD00E04
+BFD00DFE ED01 LI V0, 1
+BFD00E00 CC02 B 0xBFD00E06
+BFD00E02 0C00 NOP
+BFD00E04 0C40 MOVE V0, ZERO
+BFD00E06 000C40A2 BNEZC V0, 0xBFD00E22
+BFD00E0A BFD141A2 LUI V0, 0xBFD1
+BFD00E0C 3082BFD1 LDC1 F30, 12418(S1)
+BFD00E0E 9E3C3082 ADDIU A0, V0, -25028
+BFD00E10 30A09E3C LWC1 F17, 12448(GP)
+BFD00E12 027030A0 ADDIU A1, ZERO, 624
+BFD00E16 4B7E77E8 JALS vAssertCalled
+BFD00E18 4B7E LW K1, 120(SP)
+BFD00E1A 0C00 NOP
+BFD00E1C CC02 B 0xBFD00E22
+BFD00E1E 0C00 NOP
+625: }\r
+626: #endif\r
+627: \r
+628: \r
+629: /* This function relaxes the coding standard somewhat to allow return\r
+630: statements within the function itself. This is done in the interest\r
+631: of execution time efficiency. */\r
+632: for( ;; )\r
+633: {\r
+634: taskENTER_CRITICAL();\r
+BFD00E22 33B877E8 JALS vTaskEnterCritical
+BFD00E24 0C0033B8 ADDIU SP, T8, 3072
+BFD00E26 0C00 NOP
+635: {\r
+636: /* Is there room on the queue now? The running task must be the\r
+637: highest priority task wanting to access the queue. If the head item\r
+638: in the queue is to be overwritten then it does not matter if the\r
+639: queue is full. */\r
+640: if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )\r
+BFD00E28 0014FC5E LW V0, 20(S8)
+BFD00E2C 69AE LW V1, 56(V0)
+BFD00E2E 0014FC5E LW V0, 20(S8)
+BFD00E32 692F LW V0, 60(V0)
+BFD00E34 13900043 SLTU V0, V1, V0
+BFD00E36 40A21390 ADDI GP, S0, 16546
+BFD00E38 000640A2 BNEZC V0, 0xBFD00E48
+BFD00E3C 004CFC7E LW V1, 76(S8)
+BFD00E40 ED02 LI V0, 2
+BFD00E42 006EB443 BNE V1, V0, 0xBFD00F22
+BFD00E44 0C00006E SLL V1, T6, 1
+BFD00E46 0C00 NOP
+641: {\r
+642: traceQUEUE_SEND( pxQueue );\r
+643: xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r
+BFD00E48 0014FC9E LW A0, 20(S8)
+BFD00E4C 0044FCBE LW A1, 68(S8)
+BFD00E50 004CFCDE LW A2, 76(S8)
+BFD00E54 14E677E8 JALS prvCopyDataToQueue
+BFD00E56 0C0014E6 LBU A3, 3072(A2)
+BFD00E58 0C00 NOP
+BFD00E5A 001CF85E SW V0, 28(S8)
+644: \r
+645: #if ( configUSE_QUEUE_SETS == 1 )\r
+646: {\r
+647: if( pxQueue->pxQueueSetContainer != NULL )\r
+BFD00E5E 0014FC5E LW V0, 20(S8)
+BFD00E62 004CFC42 LW V0, 76(V0)
+BFD00E66 001E40E2 BEQZC V0, 0xBFD00EA6
+648: {\r
+649: if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )\r
+BFD00E6A 0014FC9E LW A0, 20(S8)
+BFD00E6E 004CFCBE LW A1, 76(S8)
+BFD00E72 21D877E8 JALS prvNotifyQueueSetContainer
+BFD00E74 0C0021D8 LWC2 T6, 3072(T8)
+BFD00E76 0C00 NOP
+BFD00E78 0C62 MOVE V1, V0
+BFD00E7A ED01 LI V0, 1
+BFD00E7C 004BB443 BNE V1, V0, 0xBFD00F16
+BFD00E7E 0C00004B SLL V0, T3, 1
+BFD00E80 0C00 NOP
+650: {\r
+651: /* The queue is a member of a queue set, and posting\r
+652: to the queue set caused a higher priority task to\r
+653: unblock. A context switch is required. */\r
+654: queueYIELD_IF_USING_PREEMPTION();\r
+BFD00E82 4E1677E8 JALS ulPortGetCP0Cause
+BFD00E84 4E16 ADDIU S0, S0, -5
+BFD00E86 0C00 NOP
+BFD00E88 0020F85E SW V0, 32(S8)
+BFD00E8C 0020FC5E LW V0, 32(S8)
+BFD00E90 01005042 ORI V0, V0, 256
+BFD00E94 0020F85E SW V0, 32(S8)
+BFD00E98 0020FC9E LW A0, 32(S8)
+BFD00E9C 4E2677E8 JALS vPortSetCP0Cause
+BFD00E9E 4E26 ADDIU S1, S1, 3
+BFD00EA0 0C00 NOP
+BFD00EA2 CC39 B 0xBFD00F16
+BFD00EA4 0C00 NOP
+655: }\r
+656: else\r
+657: {\r
+658: mtCOVERAGE_TEST_MARKER();\r
+659: }\r
+660: }\r
+661: else\r
+662: {\r
+663: /* If there was a task waiting for data to arrive on the\r
+664: queue then unblock it now. */\r
+665: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+BFD00EA6 0014FC5E LW V0, 20(S8)
+BFD00EAA 6929 LW V0, 36(V0)
+BFD00EAC 001F40E2 BEQZC V0, 0xBFD00EEE
+666: {\r
+667: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )\r
+BFD00EB0 0014FC5E LW V0, 20(S8)
+BFD00EB4 00243042 ADDIU V0, V0, 36
+BFD00EB8 0C82 MOVE A0, V0
+BFD00EBA 22BC77E8 JALS xTaskRemoveFromEventList
+BFD00EBC 0C0022BC LWC2 S5, 3072(GP)
+BFD00EBE 0C00 NOP
+BFD00EC0 0C62 MOVE V1, V0
+BFD00EC2 ED01 LI V0, 1
+BFD00EC4 0027B443 BNE V1, V0, 0xBFD00F16
+BFD00EC6 0C000027 SLL AT, A3, 1
+BFD00EC8 0C00 NOP
+668: {\r
+669: /* The unblocked task has a priority higher than\r
+670: our own so yield immediately. Yes it is ok to\r
+671: do this from within the critical section - the\r
+672: kernel takes care of that. */\r
+673: queueYIELD_IF_USING_PREEMPTION();\r
+BFD00ECA 4E1677E8 JALS ulPortGetCP0Cause
+BFD00ECC 4E16 ADDIU S0, S0, -5
+BFD00ECE 0C00 NOP
+BFD00ED0 0024F85E SW V0, 36(S8)
+BFD00ED4 0024FC5E LW V0, 36(S8)
+BFD00ED8 01005042 ORI V0, V0, 256
+BFD00EDC 0024F85E SW V0, 36(S8)
+BFD00EE0 0024FC9E LW A0, 36(S8)
+BFD00EE4 4E2677E8 JALS vPortSetCP0Cause
+BFD00EE6 4E26 ADDIU S1, S1, 3
+BFD00EE8 0C00 NOP
+BFD00EEA CC15 B 0xBFD00F16
+BFD00EEC 0C00 NOP
+674: }\r
+675: else\r
+676: {\r
+677: mtCOVERAGE_TEST_MARKER();\r
+678: }\r
+679: }\r
+680: else if( xYieldRequired != pdFALSE )\r
+BFD00EEE 001CFC5E LW V0, 28(S8)
+BFD00EF2 001040E2 BEQZC V0, 0xBFD00F16
+681: {\r
+682: /* This path is a special case that will only get\r
+683: executed if the task was holding multiple mutexes\r
+684: and the mutexes were given back in an order that is\r
+685: different to that in which they were taken. */\r
+686: queueYIELD_IF_USING_PREEMPTION();\r
+BFD00EF6 4E1677E8 JALS ulPortGetCP0Cause
+BFD00EF8 4E16 ADDIU S0, S0, -5
+BFD00EFA 0C00 NOP
+BFD00EFC 0028F85E SW V0, 40(S8)
+BFD00F00 0028FC5E LW V0, 40(S8)
+BFD00F04 01005042 ORI V0, V0, 256
+BFD00F08 0028F85E SW V0, 40(S8)
+BFD00F0C 0028FC9E LW A0, 40(S8)
+BFD00F10 4E2677E8 JALS vPortSetCP0Cause
+BFD00F12 4E26 ADDIU S1, S1, 3
+BFD00F14 0C00 NOP
+687: }\r
+688: else\r
+689: {\r
+690: mtCOVERAGE_TEST_MARKER();\r
+691: }\r
+692: }\r
+693: }\r
+694: #else /* configUSE_QUEUE_SETS */\r
+695: {\r
+696: /* If there was a task waiting for data to arrive on the\r
+697: queue then unblock it now. */\r
+698: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+699: {\r
+700: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )\r
+701: {\r
+702: /* The unblocked task has a priority higher than\r
+703: our own so yield immediately. Yes it is ok to do\r
+704: this from within the critical section - the kernel\r
+705: takes care of that. */\r
+706: queueYIELD_IF_USING_PREEMPTION();\r
+707: }\r
+708: else\r
+709: {\r
+710: mtCOVERAGE_TEST_MARKER();\r
+711: }\r
+712: }\r
+713: else if( xYieldRequired != pdFALSE )\r
+714: {\r
+715: /* This path is a special case that will only get\r
+716: executed if the task was holding multiple mutexes and\r
+717: the mutexes were given back in an order that is\r
+718: different to that in which they were taken. */\r
+719: queueYIELD_IF_USING_PREEMPTION();\r
+720: }\r
+721: else\r
+722: {\r
+723: mtCOVERAGE_TEST_MARKER();\r
+724: }\r
+725: }\r
+726: #endif /* configUSE_QUEUE_SETS */\r
+727: \r
+728: taskEXIT_CRITICAL();\r
+BFD00F16 40AA77E8 JALS vTaskExitCritical
+BFD00F18 0C0040AA BNEZC T2, 0xBFD0271C
+BFD00F1A 0C00 NOP
+729: return pdPASS;\r
+BFD00F1C ED01 LI V0, 1
+BFD00F1E CC87 B 0xBFD0102E
+BFD00F20 0C00 NOP
+730: }\r
+731: else\r
+732: {\r
+733: if( xTicksToWait == ( TickType_t ) 0 )\r
+BFD00F22 0048FC5E LW V0, 72(S8)
+BFD00F26 000640A2 BNEZC V0, 0xBFD00F36
+734: {\r
+735: /* The queue was full and no block time is specified (or\r
+736: the block time has expired) so leave now. */\r
+737: taskEXIT_CRITICAL();\r
+BFD00F2A 40AA77E8 JALS vTaskExitCritical
+BFD00F2C 0C0040AA BNEZC T2, 0xBFD02730
+BFD00F2E 0C00 NOP
+738: \r
+739: /* Return to the original privilege level before exiting\r
+740: the function. */\r
+741: traceQUEUE_SEND_FAILED( pxQueue );\r
+742: return errQUEUE_FULL;\r
+BFD00F30 0C40 MOVE V0, ZERO
+BFD00F32 CC7D B 0xBFD0102E
+BFD00F34 0C00 NOP
+743: }\r
+744: else if( xEntryTimeSet == pdFALSE )\r
+BFD00F36 0010FC5E LW V0, 16(S8)
+BFD00F3A 000940A2 BNEZC V0, 0xBFD00F50
+745: {\r
+746: /* The queue was full and a block time was specified so\r
+747: configure the timeout structure. */\r
+748: vTaskSetTimeOutState( &xTimeOut );\r
+BFD00F3E 002C305E ADDIU V0, S8, 44
+BFD00F42 0C82 MOVE A0, V0
+BFD00F44 47A677E8 JALS vTaskSetTimeOutState
+BFD00F48 0C00 NOP
+749: xEntryTimeSet = pdTRUE;\r
+BFD00F4A ED01 LI V0, 1
+BFD00F4C 0010F85E SW V0, 16(S8)
+750: }\r
+751: else\r
+752: {\r
+753: /* Entry time was already set. */\r
+754: mtCOVERAGE_TEST_MARKER();\r
+755: }\r
+756: }\r
+757: }\r
+758: taskEXIT_CRITICAL();\r
+BFD00F50 40AA77E8 JALS vTaskExitCritical
+BFD00F52 0C0040AA BNEZC T2, 0xBFD02756
+BFD00F54 0C00 NOP
+759: \r
+760: /* Interrupts and other tasks can send to and receive from the queue\r
+761: now the critical section has been exited. */\r
+762: \r
+763: vTaskSuspendAll();\r
+BFD00F56 4EF477E8 JALS vTaskSuspendAll
+BFD00F58 4EF4 ADDIU S7, S7, -6
+BFD00F5A 0C00 NOP
+764: prvLockQueue( pxQueue );\r
+BFD00F5C 33B877E8 JALS vTaskEnterCritical
+BFD00F5E 0C0033B8 ADDIU SP, T8, 3072
+BFD00F60 0C00 NOP
+BFD00F62 0014FC5E LW V0, 20(S8)
+BFD00F66 0044FC62 LW V1, 68(V0)
+BFD00F6A ED7F LI V0, -1
+BFD00F6C 0005B443 BNE V1, V0, 0xBFD00F7A
+BFD00F6E 0C000005 SLL ZERO, A1, 1
+BFD00F70 0C00 NOP
+BFD00F72 0014FC5E LW V0, 20(S8)
+BFD00F76 0044F802 SW ZERO, 68(V0)
+BFD00F7A 0014FC5E LW V0, 20(S8)
+BFD00F7E 0048FC62 LW V1, 72(V0)
+BFD00F82 ED7F LI V0, -1
+BFD00F84 0005B443 BNE V1, V0, 0xBFD00F92
+BFD00F86 0C000005 SLL ZERO, A1, 1
+BFD00F88 0C00 NOP
+BFD00F8A 0014FC5E LW V0, 20(S8)
+BFD00F8E 0048F802 SW ZERO, 72(V0)
+BFD00F92 40AA77E8 JALS vTaskExitCritical
+BFD00F94 0C0040AA BNEZC T2, 0xBFD02798
+BFD00F96 0C00 NOP
+765: \r
+766: /* Update the timeout state to see if it has expired yet. */\r
+767: if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
+BFD00F98 002C307E ADDIU V1, S8, 44
+BFD00F9C 0048305E ADDIU V0, S8, 72
+BFD00FA0 0C83 MOVE A0, V1
+BFD00FA2 0CA2 MOVE A1, V0
+BFD00FA4 1FF677E8 JALS xTaskCheckForTimeOut
+BFD00FA6 0C001FF6 LB RA, 3072(S6)
+BFD00FA8 0C00 NOP
+BFD00FAA 003740A2 BNEZC V0, 0xBFD0101C
+768: {\r
+769: if( prvIsQueueFull( pxQueue ) != pdFALSE )\r
+BFD00FAE 0014FC9E LW A0, 20(S8)
+BFD00FB2 478277E8 JALS prvIsQueueFull
+BFD00FB6 0C00 NOP
+BFD00FB8 002640E2 BEQZC V0, 0xBFD01008
+770: {\r
+771: traceBLOCKING_ON_QUEUE_SEND( pxQueue );\r
+772: vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\r
+BFD00FBC 0014FC5E LW V0, 20(S8)
+BFD00FC0 6DA8 ADDIU V1, V0, 16
+BFD00FC2 0048FC5E LW V0, 72(S8)
+BFD00FC6 0C83 MOVE A0, V1
+BFD00FC8 0CA2 MOVE A1, V0
+BFD00FCA 2F3A77E8 JALS vTaskPlaceOnEventList
+BFD00FCC 2F3A ANDI A2, V1, 0x20
+BFD00FCE 0C00 NOP
+773: \r
+774: /* Unlocking the queue means queue events can effect the\r
+775: event list. It is possible that interrupts occurring now\r
+776: remove this task from the event list again - but as the\r
+777: scheduler is suspended the task will go onto the pending\r
+778: ready last instead of the actual ready list. */\r
+779: prvUnlockQueue( pxQueue );\r
+BFD00FD0 0014FC9E LW A0, 20(S8)
+BFD00FD4 1DEE77E8 JALS prvUnlockQueue
+BFD00FD6 0C001DEE LB T7, 3072(T6)
+BFD00FD8 0C00 NOP
+780: \r
+781: /* Resuming the scheduler will move tasks from the pending\r
+782: ready list into the ready list - so it is feasible that this\r
+783: task is already in a ready list before it yields - in which\r
+784: case the yield will not cause a context switch unless there\r
+785: is also a higher priority task in the pending ready list. */\r
+786: if( xTaskResumeAll() == pdFALSE )\r
+BFD00FDA 158E77E8 JALS xTaskResumeAll
+BFD00FDC 0C00158E LBU T4, 3072(T6)
+BFD00FDE 0C00 NOP
+BFD00FE0 FF1E40A2 BNEZC V0, 0xBFD00E20
+BFD00FE2 77E8FF1E LW T8, 30696(S8)
+787: {\r
+788: portYIELD_WITHIN_API();\r
+BFD00FE4 4E1677E8 JALS ulPortGetCP0Cause
+BFD00FE6 4E16 ADDIU S0, S0, -5
+BFD00FE8 0C00 NOP
+BFD00FEA 0018F85E SW V0, 24(S8)
+BFD00FEE 0018FC5E LW V0, 24(S8)
+BFD00FF2 01005042 ORI V0, V0, 256
+BFD00FF6 0018F85E SW V0, 24(S8)
+BFD00FFA 0018FC9E LW A0, 24(S8)
+BFD00FFE 4E2677E8 JALS vPortSetCP0Cause
+BFD01000 4E26 ADDIU S1, S1, 3
+BFD01002 0C00 NOP
+789: }\r
+790: }\r
+791: else\r
+792: {\r
+793: /* Try again. */\r
+794: prvUnlockQueue( pxQueue );\r
+BFD01008 0014FC9E LW A0, 20(S8)
+BFD0100C 1DEE77E8 JALS prvUnlockQueue
+BFD0100E 0C001DEE LB T7, 3072(T6)
+BFD01010 0C00 NOP
+795: ( void ) xTaskResumeAll();\r
+BFD01012 158E77E8 JALS xTaskResumeAll
+BFD01014 0C00158E LBU T4, 3072(T6)
+BFD01016 0C00 NOP
+796: }\r
+797: }\r
+798: else\r
+799: {\r
+800: /* The timeout has expired. */\r
+801: prvUnlockQueue( pxQueue );\r
+BFD0101C 0014FC9E LW A0, 20(S8)
+BFD01020 1DEE77E8 JALS prvUnlockQueue
+BFD01022 0C001DEE LB T7, 3072(T6)
+BFD01024 0C00 NOP
+802: ( void ) xTaskResumeAll();\r
+BFD01026 158E77E8 JALS xTaskResumeAll
+BFD01028 0C00158E LBU T4, 3072(T6)
+BFD0102A 0C00 NOP
+803: \r
+804: /* Return to the original privilege level before exiting the\r
+805: function. */\r
+806: traceQUEUE_SEND_FAILED( pxQueue );\r
+807: return errQUEUE_FULL;\r
+BFD0102C 0C40 MOVE V0, ZERO
+808: }\r
+809: }\r
+BFD00E20 0C00 NOP
+BFD01004 CF0E B 0xBFD00E22
+BFD01006 0C00 NOP
+BFD01018 CF04 B 0xBFD00E22
+BFD0101A 0C00 NOP
+810: }\r
+BFD0102E 0FBE MOVE SP, S8
+BFD01030 4BEF LW RA, 60(SP)
+BFD01032 4BCE LW S8, 56(SP)
+BFD01034 4C21 ADDIU SP, SP, 64
+BFD01036 459F JR16 RA
+BFD01038 0C00 NOP
+811: /*-----------------------------------------------------------*/\r
+812: \r
+813: #if ( configUSE_ALTERNATIVE_API == 1 )\r
+814: \r
+815: BaseType_t xQueueAltGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition )\r
+816: {\r
+817: BaseType_t xEntryTimeSet = pdFALSE;\r
+818: TimeOut_t xTimeOut;\r
+819: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+820: \r
+821: configASSERT( pxQueue );\r
+822: configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r
+823: \r
+824: for( ;; )\r
+825: {\r
+826: taskENTER_CRITICAL();\r
+827: {\r
+828: /* Is there room on the queue now? To be running we must be\r
+829: the highest priority task wanting to access the queue. */\r
+830: if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+831: {\r
+832: traceQUEUE_SEND( pxQueue );\r
+833: prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r
+834: \r
+835: /* If there was a task waiting for data to arrive on the\r
+836: queue then unblock it now. */\r
+837: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+838: {\r
+839: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )\r
+840: {\r
+841: /* The unblocked task has a priority higher than\r
+842: our own so yield immediately. */\r
+843: portYIELD_WITHIN_API();\r
+844: }\r
+845: else\r
+846: {\r
+847: mtCOVERAGE_TEST_MARKER();\r
+848: }\r
+849: }\r
+850: else\r
+851: {\r
+852: mtCOVERAGE_TEST_MARKER();\r
+853: }\r
+854: \r
+855: taskEXIT_CRITICAL();\r
+856: return pdPASS;\r
+857: }\r
+858: else\r
+859: {\r
+860: if( xTicksToWait == ( TickType_t ) 0 )\r
+861: {\r
+862: taskEXIT_CRITICAL();\r
+863: return errQUEUE_FULL;\r
+864: }\r
+865: else if( xEntryTimeSet == pdFALSE )\r
+866: {\r
+867: vTaskSetTimeOutState( &xTimeOut );\r
+868: xEntryTimeSet = pdTRUE;\r
+869: }\r
+870: }\r
+871: }\r
+872: taskEXIT_CRITICAL();\r
+873: \r
+874: taskENTER_CRITICAL();\r
+875: {\r
+876: if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
+877: {\r
+878: if( prvIsQueueFull( pxQueue ) != pdFALSE )\r
+879: {\r
+880: traceBLOCKING_ON_QUEUE_SEND( pxQueue );\r
+881: vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\r
+882: portYIELD_WITHIN_API();\r
+883: }\r
+884: else\r
+885: {\r
+886: mtCOVERAGE_TEST_MARKER();\r
+887: }\r
+888: }\r
+889: else\r
+890: {\r
+891: taskEXIT_CRITICAL();\r
+892: traceQUEUE_SEND_FAILED( pxQueue );\r
+893: return errQUEUE_FULL;\r
+894: }\r
+895: }\r
+896: taskEXIT_CRITICAL();\r
+897: }\r
+898: }\r
+899: \r
+900: #endif /* configUSE_ALTERNATIVE_API */\r
+901: /*-----------------------------------------------------------*/\r
+902: \r
+903: #if ( configUSE_ALTERNATIVE_API == 1 )\r
+904: \r
+905: BaseType_t xQueueAltGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking )\r
+906: {\r
+907: BaseType_t xEntryTimeSet = pdFALSE;\r
+908: TimeOut_t xTimeOut;\r
+909: int8_t *pcOriginalReadPosition;\r
+910: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+911: \r
+912: configASSERT( pxQueue );\r
+913: configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r
+914: \r
+915: for( ;; )\r
+916: {\r
+917: taskENTER_CRITICAL();\r
+918: {\r
+919: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r
+920: {\r
+921: /* Remember our read position in case we are just peeking. */\r
+922: pcOriginalReadPosition = pxQueue->u.pcReadFrom;\r
+923: \r
+924: prvCopyDataFromQueue( pxQueue, pvBuffer );\r
+925: \r
+926: if( xJustPeeking == pdFALSE )\r
+927: {\r
+928: traceQUEUE_RECEIVE( pxQueue );\r
+929: \r
+930: /* Data is actually being removed (not just peeked). */\r
+931: --( pxQueue->uxMessagesWaiting );\r
+932: \r
+933: #if ( configUSE_MUTEXES == 1 )\r
+934: {\r
+935: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+936: {\r
+937: /* Record the information required to implement\r
+938: priority inheritance should it become necessary. */\r
+939: pxQueue->pxMutexHolder = ( int8_t * ) xTaskGetCurrentTaskHandle();\r
+940: }\r
+941: else\r
+942: {\r
+943: mtCOVERAGE_TEST_MARKER();\r
+944: }\r
+945: }\r
+946: #endif\r
+947: \r
+948: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+949: {\r
+950: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r
+951: {\r
+952: portYIELD_WITHIN_API();\r
+953: }\r
+954: else\r
+955: {\r
+956: mtCOVERAGE_TEST_MARKER();\r
+957: }\r
+958: }\r
+959: }\r
+960: else\r
+961: {\r
+962: traceQUEUE_PEEK( pxQueue );\r
+963: \r
+964: /* The data is not being removed, so reset our read\r
+965: pointer. */\r
+966: pxQueue->u.pcReadFrom = pcOriginalReadPosition;\r
+967: \r
+968: /* The data is being left in the queue, so see if there are\r
+969: any other tasks waiting for the data. */\r
+970: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+971: {\r
+972: /* Tasks that are removed from the event list will get added to\r
+973: the pending ready list as the scheduler is still suspended. */\r
+974: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+975: {\r
+976: /* The task waiting has a higher priority than this task. */\r
+977: portYIELD_WITHIN_API();\r
+978: }\r
+979: else\r
+980: {\r
+981: mtCOVERAGE_TEST_MARKER();\r
+982: }\r
+983: }\r
+984: else\r
+985: {\r
+986: mtCOVERAGE_TEST_MARKER();\r
+987: }\r
+988: }\r
+989: \r
+990: taskEXIT_CRITICAL();\r
+991: return pdPASS;\r
+992: }\r
+993: else\r
+994: {\r
+995: if( xTicksToWait == ( TickType_t ) 0 )\r
+996: {\r
+997: taskEXIT_CRITICAL();\r
+998: traceQUEUE_RECEIVE_FAILED( pxQueue );\r
+999: return errQUEUE_EMPTY;\r
+1000: }\r
+1001: else if( xEntryTimeSet == pdFALSE )\r
+1002: {\r
+1003: vTaskSetTimeOutState( &xTimeOut );\r
+1004: xEntryTimeSet = pdTRUE;\r
+1005: }\r
+1006: }\r
+1007: }\r
+1008: taskEXIT_CRITICAL();\r
+1009: \r
+1010: taskENTER_CRITICAL();\r
+1011: {\r
+1012: if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
+1013: {\r
+1014: if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\r
+1015: {\r
+1016: traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\r
+1017: \r
+1018: #if ( configUSE_MUTEXES == 1 )\r
+1019: {\r
+1020: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+1021: {\r
+1022: taskENTER_CRITICAL();\r
+1023: {\r
+1024: vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );\r
+1025: }\r
+1026: taskEXIT_CRITICAL();\r
+1027: }\r
+1028: else\r
+1029: {\r
+1030: mtCOVERAGE_TEST_MARKER();\r
+1031: }\r
+1032: }\r
+1033: #endif\r
+1034: \r
+1035: vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r
+1036: portYIELD_WITHIN_API();\r
+1037: }\r
+1038: else\r
+1039: {\r
+1040: mtCOVERAGE_TEST_MARKER();\r
+1041: }\r
+1042: }\r
+1043: else\r
+1044: {\r
+1045: taskEXIT_CRITICAL();\r
+1046: traceQUEUE_RECEIVE_FAILED( pxQueue );\r
+1047: return errQUEUE_EMPTY;\r
+1048: }\r
+1049: }\r
+1050: taskEXIT_CRITICAL();\r
+1051: }\r
+1052: }\r
+1053: \r
+1054: \r
+1055: #endif /* configUSE_ALTERNATIVE_API */\r
+1056: /*-----------------------------------------------------------*/\r
+1057: \r
+1058: BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )\r
+1059: {\r
+BFD023D4 4FED ADDIU SP, SP, -40
+BFD023D6 CBE9 SW RA, 36(SP)
+BFD023D8 CBC8 SW S8, 32(SP)
+BFD023DA 0FDD MOVE S8, SP
+BFD023DC 0028F89E SW A0, 40(S8)
+BFD023E0 002CF8BE SW A1, 44(S8)
+BFD023E4 0030F8DE SW A2, 48(S8)
+BFD023E8 0034F8FE SW A3, 52(S8)
+1060: BaseType_t xReturn;\r
+1061: UBaseType_t uxSavedInterruptStatus;\r
+1062: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+BFD023EC 0028FC5E LW V0, 40(S8)
+BFD023F0 0014F85E SW V0, 20(S8)
+1063: \r
+1064: configASSERT( pxQueue );\r
+BFD023F4 0014FC5E LW V0, 20(S8)
+BFD023F8 000940A2 BNEZC V0, 0xBFD0240E
+BFD023FC BFD141A2 LUI V0, 0xBFD1
+BFD023FE 3082BFD1 LDC1 F30, 12418(S1)
+BFD02400 9E3C3082 ADDIU A0, V0, -25028
+BFD02402 30A09E3C LWC1 F17, 12448(GP)
+BFD02404 042830A0 ADDIU A1, ZERO, 1064
+BFD02406 0428 ADDU S0, A0, V0
+BFD02408 4B7E77E8 JALS vAssertCalled
+BFD0240A 4B7E LW K1, 120(SP)
+BFD0240C 0C00 NOP
+1065: configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r
+BFD0240E 002CFC5E LW V0, 44(S8)
+BFD02412 000640A2 BNEZC V0, 0xBFD02422
+BFD02416 0014FC5E LW V0, 20(S8)
+BFD0241A 0040FC42 LW V0, 64(V0)
+BFD0241E 000340A2 BNEZC V0, 0xBFD02428
+BFD02422 ED01 LI V0, 1
+BFD02424 CC02 B 0xBFD0242A
+BFD02426 0C00 NOP
+BFD02428 0C40 MOVE V0, ZERO
+BFD0242A 000940A2 BNEZC V0, 0xBFD02440
+BFD0242E BFD141A2 LUI V0, 0xBFD1
+BFD02430 3082BFD1 LDC1 F30, 12418(S1)
+BFD02432 9E3C3082 ADDIU A0, V0, -25028
+BFD02434 30A09E3C LWC1 F17, 12448(GP)
+BFD02436 042930A0 ADDIU A1, ZERO, 1065
+BFD02438 0429 SUBU S0, A0, V0
+BFD0243A 4B7E77E8 JALS vAssertCalled
+BFD0243C 4B7E LW K1, 120(SP)
+BFD0243E 0C00 NOP
+1066: configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );\r
+BFD02440 0034FC7E LW V1, 52(S8)
+BFD02444 ED02 LI V0, 2
+BFD02446 0008B443 BNE V1, V0, 0xBFD0245A
+BFD02448 0C000008 SLL ZERO, T0, 1
+BFD0244A 0C00 NOP
+BFD0244C 0014FC5E LW V0, 20(S8)
+BFD02450 69AF LW V1, 60(V0)
+BFD02452 ED01 LI V0, 1
+BFD02454 0004B443 BNE V1, V0, 0xBFD02460
+BFD02456 0C000004 SLL ZERO, A0, 1
+BFD02458 0C00 NOP
+BFD0245A ED01 LI V0, 1
+BFD0245C CC02 B 0xBFD02462
+BFD0245E 0C00 NOP
+BFD02460 0C40 MOVE V0, ZERO
+BFD02462 000940A2 BNEZC V0, 0xBFD02478
+BFD02466 BFD141A2 LUI V0, 0xBFD1
+BFD02468 3082BFD1 LDC1 F30, 12418(S1)
+BFD0246A 9E3C3082 ADDIU A0, V0, -25028
+BFD0246C 30A09E3C LWC1 F17, 12448(GP)
+BFD0246E 042A30A0 ADDIU A1, ZERO, 1066
+BFD02470 042A ADDU S0, A1, V0
+BFD02472 4B7E77E8 JALS vAssertCalled
+BFD02474 4B7E LW K1, 120(SP)
+BFD02476 0C00 NOP
+1067: \r
+1068: /* RTOS ports that support interrupt nesting have the concept of a maximum\r
+1069: system call (or maximum API call) interrupt priority. Interrupts that are\r
+1070: above the maximum system call priority are kept permanently enabled, even\r
+1071: when the RTOS kernel is in a critical section, but cannot make any calls to\r
+1072: FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h\r
+1073: then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r
+1074: failure if a FreeRTOS API function is called from an interrupt that has been\r
+1075: assigned a priority above the configured maximum system call priority.\r
+1076: Only FreeRTOS functions that end in FromISR can be called from interrupts\r
+1077: that have been assigned a priority at or (logically) below the maximum\r
+1078: system call interrupt priority. FreeRTOS maintains a separate interrupt\r
+1079: safe API to ensure interrupt entry is as fast and as simple as possible.\r
+1080: More information (albeit Cortex-M specific) is provided on the following\r
+1081: link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r
+1082: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
+1083: \r
+1084: /* Similar to xQueueGenericSend, except without blocking if there is no room\r
+1085: in the queue. Also don't directly wake a task that was blocked on a queue\r
+1086: read, instead return a flag to say whether a context switch is required or\r
+1087: not (i.e. has a task with a higher priority than us been woken by this\r
+1088: post). */\r
+1089: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+BFD02478 475E77E8 JALS uxPortSetInterruptMaskFromISR
+BFD0247C 0C00 NOP
+BFD0247E 0018F85E SW V0, 24(S8)
+1090: {\r
+1091: if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )\r
+BFD02482 0014FC5E LW V0, 20(S8)
+BFD02486 69AE LW V1, 56(V0)
+BFD02488 0014FC5E LW V0, 20(S8)
+BFD0248C 692F LW V0, 60(V0)
+BFD0248E 13900043 SLTU V0, V1, V0
+BFD02490 40A21390 ADDI GP, S0, 16546
+BFD02492 000640A2 BNEZC V0, 0xBFD024A2
+BFD02496 0034FC7E LW V1, 52(S8)
+BFD0249A ED02 LI V0, 2
+BFD0249C 0055B443 BNE V1, V0, 0xBFD0254A
+BFD0249E 0C000055 SLL V0, S5, 1
+BFD024A0 0C00 NOP
+1092: {\r
+1093: traceQUEUE_SEND_FROM_ISR( pxQueue );\r
+1094: \r
+1095: /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a\r
+1096: semaphore or mutex. That means prvCopyDataToQueue() cannot result\r
+1097: in a task disinheriting a priority and prvCopyDataToQueue() can be\r
+1098: called here even though the disinherit function does not check if\r
+1099: the scheduler is suspended before accessing the ready lists. */\r
+1100: ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r
+BFD024A2 0014FC9E LW A0, 20(S8)
+BFD024A6 002CFCBE LW A1, 44(S8)
+BFD024AA 0034FCDE LW A2, 52(S8)
+BFD024AE 14E677E8 JALS prvCopyDataToQueue
+BFD024B0 0C0014E6 LBU A3, 3072(A2)
+BFD024B2 0C00 NOP
+1101: \r
+1102: /* The event list is not altered if the queue is locked. This will\r
+1103: be done when the queue is unlocked later. */\r
+1104: if( pxQueue->xTxLock == queueUNLOCKED )\r
+BFD024B4 0014FC5E LW V0, 20(S8)
+BFD024B8 0048FC62 LW V1, 72(V0)
+BFD024BC ED7F LI V0, -1
+BFD024BE 0036B443 BNE V1, V0, 0xBFD0252E
+BFD024C0 0C000036 SLL AT, S6, 1
+BFD024C2 0C00 NOP
+1105: {\r
+1106: #if ( configUSE_QUEUE_SETS == 1 )\r
+1107: {\r
+1108: if( pxQueue->pxQueueSetContainer != NULL )\r
+BFD024C4 0014FC5E LW V0, 20(S8)
+BFD024C8 004CFC42 LW V0, 76(V0)
+BFD024CC 001640E2 BEQZC V0, 0xBFD024FC
+1109: {\r
+1110: if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )\r
+BFD024D0 0014FC9E LW A0, 20(S8)
+BFD024D4 0034FCBE LW A1, 52(S8)
+BFD024D8 21D877E8 JALS prvNotifyQueueSetContainer
+BFD024DA 0C0021D8 LWC2 T6, 3072(T8)
+BFD024DC 0C00 NOP
+BFD024DE 0C62 MOVE V1, V0
+BFD024E0 ED01 LI V0, 1
+BFD024E2 002DB443 BNE V1, V0, 0xBFD02540
+BFD024E4 0C00002D SLL AT, T5, 1
+BFD024E6 0C00 NOP
+1111: {\r
+1112: /* The queue is a member of a queue set, and posting\r
+1113: to the queue set caused a higher priority task to\r
+1114: unblock. A context switch is required. */\r
+1115: if( pxHigherPriorityTaskWoken != NULL )\r
+BFD024E8 0030FC5E LW V0, 48(S8)
+BFD024EC 002840E2 BEQZC V0, 0xBFD02540
+1116: {\r
+1117: *pxHigherPriorityTaskWoken = pdTRUE;\r
+BFD024F0 0030FC5E LW V0, 48(S8)
+BFD024F4 ED81 LI V1, 1
+BFD024F6 E9A0 SW V1, 0(V0)
+BFD024F8 CC23 B 0xBFD02540
+BFD024FA 0C00 NOP
+1118: }\r
+1119: else\r
+1120: {\r
+1121: mtCOVERAGE_TEST_MARKER();\r
+1122: }\r
+1123: }\r
+1124: else\r
+1125: {\r
+1126: mtCOVERAGE_TEST_MARKER();\r
+1127: }\r
+1128: }\r
+1129: else\r
+1130: {\r
+1131: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+BFD024FC 0014FC5E LW V0, 20(S8)
+BFD02500 6929 LW V0, 36(V0)
+BFD02502 001D40E2 BEQZC V0, 0xBFD02540
+1132: {\r
+1133: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+BFD02506 0014FC5E LW V0, 20(S8)
+BFD0250A 00243042 ADDIU V0, V0, 36
+BFD0250E 0C82 MOVE A0, V0
+BFD02510 22BC77E8 JALS xTaskRemoveFromEventList
+BFD02512 0C0022BC LWC2 S5, 3072(GP)
+BFD02514 0C00 NOP
+BFD02516 001340E2 BEQZC V0, 0xBFD02540
+1134: {\r
+1135: /* The task waiting has a higher priority so\r
+1136: record that a context switch is required. */\r
+1137: if( pxHigherPriorityTaskWoken != NULL )\r
+BFD0251A 0030FC5E LW V0, 48(S8)
+BFD0251E 000F40E2 BEQZC V0, 0xBFD02540
+1138: {\r
+1139: *pxHigherPriorityTaskWoken = pdTRUE;\r
+BFD02522 0030FC5E LW V0, 48(S8)
+BFD02526 ED81 LI V1, 1
+BFD02528 E9A0 SW V1, 0(V0)
+BFD0252A CC0A B 0xBFD02540
+BFD0252C 0C00 NOP
+1140: }\r
+1141: else\r
+1142: {\r
+1143: mtCOVERAGE_TEST_MARKER();\r
+1144: }\r
+1145: }\r
+1146: else\r
+1147: {\r
+1148: mtCOVERAGE_TEST_MARKER();\r
+1149: }\r
+1150: }\r
+1151: else\r
+1152: {\r
+1153: mtCOVERAGE_TEST_MARKER();\r
+1154: }\r
+1155: }\r
+1156: }\r
+1157: #else /* configUSE_QUEUE_SETS */\r
+1158: {\r
+1159: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+1160: {\r
+1161: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+1162: {\r
+1163: /* The task waiting has a higher priority so record that a\r
+1164: context switch is required. */\r
+1165: if( pxHigherPriorityTaskWoken != NULL )\r
+1166: {\r
+1167: *pxHigherPriorityTaskWoken = pdTRUE;\r
+1168: }\r
+1169: else\r
+1170: {\r
+1171: mtCOVERAGE_TEST_MARKER();\r
+1172: }\r
+1173: }\r
+1174: else\r
+1175: {\r
+1176: mtCOVERAGE_TEST_MARKER();\r
+1177: }\r
+1178: }\r
+1179: else\r
+1180: {\r
+1181: mtCOVERAGE_TEST_MARKER();\r
+1182: }\r
+1183: }\r
+1184: #endif /* configUSE_QUEUE_SETS */\r
+1185: }\r
+1186: else\r
+1187: {\r
+1188: /* Increment the lock count so the task that unlocks the queue\r
+1189: knows that data was posted while it was locked. */\r
+1190: ++( pxQueue->xTxLock );\r
+BFD0252E 0014FC5E LW V0, 20(S8)
+BFD02532 0048FC42 LW V0, 72(V0)
+BFD02536 6DA0 ADDIU V1, V0, 1
+BFD02538 0014FC5E LW V0, 20(S8)
+BFD0253C 0048F862 SW V1, 72(V0)
+1191: }\r
+1192: \r
+1193: xReturn = pdPASS;\r
+BFD02540 ED01 LI V0, 1
+BFD02542 0010F85E SW V0, 16(S8)
+BFD02546 CC03 B 0xBFD0254E
+BFD02548 0C00 NOP
+1194: }\r
+1195: else\r
+1196: {\r
+1197: traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\r
+1198: xReturn = errQUEUE_FULL;\r
+BFD0254A 0010F81E SW ZERO, 16(S8)
+1199: }\r
+1200: }\r
+1201: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+BFD0254E 0018FC9E LW A0, 24(S8)
+BFD02552 4D5E77E8 JALS vPortClearInterruptMaskFromISR
+BFD02554 4D5E ADDIU T2, T2, -1
+BFD02556 0C00 NOP
+1202: \r
+1203: return xReturn;\r
+BFD02558 0010FC5E LW V0, 16(S8)
+1204: }\r
+BFD0255C 0FBE MOVE SP, S8
+BFD0255E 4BE9 LW RA, 36(SP)
+BFD02560 4BC8 LW S8, 32(SP)
+BFD02562 4C15 ADDIU SP, SP, 40
+BFD02564 459F JR16 RA
+BFD02566 0C00 NOP
+1205: /*-----------------------------------------------------------*/\r
+1206: \r
+1207: BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )\r
+1208: {\r
+BFD0286C 4FED ADDIU SP, SP, -40
+BFD0286E CBE9 SW RA, 36(SP)
+BFD02870 CBC8 SW S8, 32(SP)
+BFD02872 0FDD MOVE S8, SP
+BFD02874 0028F89E SW A0, 40(S8)
+BFD02878 002CF8BE SW A1, 44(S8)
+1209: BaseType_t xReturn;\r
+1210: UBaseType_t uxSavedInterruptStatus;\r
+1211: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+BFD0287C 0028FC5E LW V0, 40(S8)
+BFD02880 0014F85E SW V0, 20(S8)
+1212: \r
+1213: /* Similar to xQueueGenericSendFromISR() but used with semaphores where the\r
+1214: item size is 0. Don't directly wake a task that was blocked on a queue\r
+1215: read, instead return a flag to say whether a context switch is required or\r
+1216: not (i.e. has a task with a higher priority than us been woken by this\r
+1217: post). */\r
+1218: \r
+1219: configASSERT( pxQueue );\r
+BFD02884 0014FC5E LW V0, 20(S8)
+BFD02888 000940A2 BNEZC V0, 0xBFD0289E
+BFD0288C BFD141A2 LUI V0, 0xBFD1
+BFD0288E 3082BFD1 LDC1 F30, 12418(S1)
+BFD02890 9E3C3082 ADDIU A0, V0, -25028
+BFD02892 30A09E3C LWC1 F17, 12448(GP)
+BFD02894 04C330A0 ADDIU A1, ZERO, 1219
+BFD02896 04C3 SUBU S1, S1, A0
+BFD02898 4B7E77E8 JALS vAssertCalled
+BFD0289A 4B7E LW K1, 120(SP)
+BFD0289C 0C00 NOP
+1220: \r
+1221: /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()\r
+1222: if the item size is not 0. */\r
+1223: configASSERT( pxQueue->uxItemSize == 0 );\r
+BFD0289E 0014FC5E LW V0, 20(S8)
+BFD028A2 0040FC42 LW V0, 64(V0)
+BFD028A6 000940E2 BEQZC V0, 0xBFD028BC
+BFD028AA BFD141A2 LUI V0, 0xBFD1
+BFD028AC 3082BFD1 LDC1 F30, 12418(S1)
+BFD028AE 9E3C3082 ADDIU A0, V0, -25028
+BFD028B0 30A09E3C LWC1 F17, 12448(GP)
+BFD028B2 04C730A0 ADDIU A1, ZERO, 1223
+BFD028B4 04C7 SUBU S1, V1, A0
+BFD028B6 4B7E77E8 JALS vAssertCalled
+BFD028B8 4B7E LW K1, 120(SP)
+BFD028BA 0C00 NOP
+1224: \r
+1225: /* Normally a mutex would not be given from an interrupt, and doing so is\r
+1226: definitely wrong if there is a mutex holder as priority inheritance makes no\r
+1227: sense for an interrupts, only tasks. */\r
+1228: configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->pxMutexHolder != NULL ) ) );\r
+BFD028BC 0014FC5E LW V0, 20(S8)
+BFD028C0 6920 LW V0, 0(V0)
+BFD028C2 000540A2 BNEZC V0, 0xBFD028D0
+BFD028C6 0014FC5E LW V0, 20(S8)
+BFD028CA 6921 LW V0, 4(V0)
+BFD028CC 000340A2 BNEZC V0, 0xBFD028D6
+BFD028D0 ED01 LI V0, 1
+BFD028D2 CC02 B 0xBFD028D8
+BFD028D4 0C00 NOP
+BFD028D6 0C40 MOVE V0, ZERO
+BFD028D8 000940A2 BNEZC V0, 0xBFD028EE
+BFD028DC BFD141A2 LUI V0, 0xBFD1
+BFD028DE 3082BFD1 LDC1 F30, 12418(S1)
+BFD028E0 9E3C3082 ADDIU A0, V0, -25028
+BFD028E2 30A09E3C LWC1 F17, 12448(GP)
+BFD028E4 04CC30A0 ADDIU A1, ZERO, 1228
+BFD028E6 04CC ADDU S1, A2, A0
+BFD028E8 4B7E77E8 JALS vAssertCalled
+BFD028EA 4B7E LW K1, 120(SP)
+BFD028EC 0C00 NOP
+1229: \r
+1230: /* RTOS ports that support interrupt nesting have the concept of a maximum\r
+1231: system call (or maximum API call) interrupt priority. Interrupts that are\r
+1232: above the maximum system call priority are kept permanently enabled, even\r
+1233: when the RTOS kernel is in a critical section, but cannot make any calls to\r
+1234: FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h\r
+1235: then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r
+1236: failure if a FreeRTOS API function is called from an interrupt that has been\r
+1237: assigned a priority above the configured maximum system call priority.\r
+1238: Only FreeRTOS functions that end in FromISR can be called from interrupts\r
+1239: that have been assigned a priority at or (logically) below the maximum\r
+1240: system call interrupt priority. FreeRTOS maintains a separate interrupt\r
+1241: safe API to ensure interrupt entry is as fast and as simple as possible.\r
+1242: More information (albeit Cortex-M specific) is provided on the following\r
+1243: link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r
+1244: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
+1245: \r
+1246: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+BFD028EE 475E77E8 JALS uxPortSetInterruptMaskFromISR
+BFD028F2 0C00 NOP
+BFD028F4 0018F85E SW V0, 24(S8)
+1247: {\r
+1248: /* When the queue is used to implement a semaphore no data is ever\r
+1249: moved through the queue but it is still valid to see if the queue 'has\r
+1250: space'. */\r
+1251: if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+BFD028F8 0014FC5E LW V0, 20(S8)
+BFD028FC 69AE LW V1, 56(V0)
+BFD028FE 0014FC5E LW V0, 20(S8)
+BFD02902 692F LW V0, 60(V0)
+BFD02904 13900043 SLTU V0, V1, V0
+BFD02906 40E21390 ADDI GP, S0, 16610
+BFD02908 005140E2 BEQZC V0, 0xBFD029AE
+1252: {\r
+1253: traceQUEUE_SEND_FROM_ISR( pxQueue );\r
+1254: \r
+1255: /* A task can only have an inherited priority if it is a mutex\r
+1256: holder - and if there is a mutex holder then the mutex cannot be\r
+1257: given from an ISR. As this is the ISR version of the function it\r
+1258: can be assumed there is no mutex holder and no need to determine if\r
+1259: priority disinheritance is needed. Simply increase the count of\r
+1260: messages (semaphores) available. */\r
+1261: ++( pxQueue->uxMessagesWaiting );\r
+BFD0290C 0014FC5E LW V0, 20(S8)
+BFD02910 692E LW V0, 56(V0)
+BFD02912 6DA0 ADDIU V1, V0, 1
+BFD02914 0014FC5E LW V0, 20(S8)
+BFD02918 E9AE SW V1, 56(V0)
+1262: \r
+1263: /* The event list is not altered if the queue is locked. This will\r
+1264: be done when the queue is unlocked later. */\r
+1265: if( pxQueue->xTxLock == queueUNLOCKED )\r
+BFD0291A 0014FC5E LW V0, 20(S8)
+BFD0291E 0048FC62 LW V1, 72(V0)
+BFD02922 ED7F LI V0, -1
+BFD02924 0035B443 BNE V1, V0, 0xBFD02992
+BFD02926 0C000035 SLL AT, S5, 1
+BFD02928 0C00 NOP
+1266: {\r
+1267: #if ( configUSE_QUEUE_SETS == 1 )\r
+1268: {\r
+1269: if( pxQueue->pxQueueSetContainer != NULL )\r
+BFD0292A 0014FC5E LW V0, 20(S8)
+BFD0292E 004CFC42 LW V0, 76(V0)
+BFD02932 001540E2 BEQZC V0, 0xBFD02960
+1270: {\r
+1271: if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )\r
+BFD02936 0014FC9E LW A0, 20(S8)
+BFD0293A 0CA0 MOVE A1, ZERO
+BFD0293C 21D877E8 JALS prvNotifyQueueSetContainer
+BFD0293E 0C0021D8 LWC2 T6, 3072(T8)
+BFD02940 0C00 NOP
+BFD02942 0C62 MOVE V1, V0
+BFD02944 ED01 LI V0, 1
+BFD02946 002DB443 BNE V1, V0, 0xBFD029A4
+BFD02948 0C00002D SLL AT, T5, 1
+BFD0294A 0C00 NOP
+1272: {\r
+1273: /* The semaphore is a member of a queue set, and\r
+1274: posting to the queue set caused a higher priority\r
+1275: task to unblock. A context switch is required. */\r
+1276: if( pxHigherPriorityTaskWoken != NULL )\r
+BFD0294C 002CFC5E LW V0, 44(S8)
+BFD02950 002840E2 BEQZC V0, 0xBFD029A4
+1277: {\r
+1278: *pxHigherPriorityTaskWoken = pdTRUE;\r
+BFD02954 002CFC5E LW V0, 44(S8)
+BFD02958 ED81 LI V1, 1
+BFD0295A E9A0 SW V1, 0(V0)
+BFD0295C CC23 B 0xBFD029A4
+BFD0295E 0C00 NOP
+1279: }\r
+1280: else\r
+1281: {\r
+1282: mtCOVERAGE_TEST_MARKER();\r
+1283: }\r
+1284: }\r
+1285: else\r
+1286: {\r
+1287: mtCOVERAGE_TEST_MARKER();\r
+1288: }\r
+1289: }\r
+1290: else\r
+1291: {\r
+1292: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+BFD02960 0014FC5E LW V0, 20(S8)
+BFD02964 6929 LW V0, 36(V0)
+BFD02966 001D40E2 BEQZC V0, 0xBFD029A4
+1293: {\r
+1294: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+BFD0296A 0014FC5E LW V0, 20(S8)
+BFD0296E 00243042 ADDIU V0, V0, 36
+BFD02972 0C82 MOVE A0, V0
+BFD02974 22BC77E8 JALS xTaskRemoveFromEventList
+BFD02976 0C0022BC LWC2 S5, 3072(GP)
+BFD02978 0C00 NOP
+BFD0297A 001340E2 BEQZC V0, 0xBFD029A4
+1295: {\r
+1296: /* The task waiting has a higher priority so\r
+1297: record that a context switch is required. */\r
+1298: if( pxHigherPriorityTaskWoken != NULL )\r
+BFD0297E 002CFC5E LW V0, 44(S8)
+BFD02982 000F40E2 BEQZC V0, 0xBFD029A4
+1299: {\r
+1300: *pxHigherPriorityTaskWoken = pdTRUE;\r
+BFD02986 002CFC5E LW V0, 44(S8)
+BFD0298A ED81 LI V1, 1
+BFD0298C E9A0 SW V1, 0(V0)
+BFD0298E CC0A B 0xBFD029A4
+BFD02990 0C00 NOP
+1301: }\r
+1302: else\r
+1303: {\r
+1304: mtCOVERAGE_TEST_MARKER();\r
+1305: }\r
+1306: }\r
+1307: else\r
+1308: {\r
+1309: mtCOVERAGE_TEST_MARKER();\r
+1310: }\r
+1311: }\r
+1312: else\r
+1313: {\r
+1314: mtCOVERAGE_TEST_MARKER();\r
+1315: }\r
+1316: }\r
+1317: }\r
+1318: #else /* configUSE_QUEUE_SETS */\r
+1319: {\r
+1320: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+1321: {\r
+1322: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+1323: {\r
+1324: /* The task waiting has a higher priority so record that a\r
+1325: context switch is required. */\r
+1326: if( pxHigherPriorityTaskWoken != NULL )\r
+1327: {\r
+1328: *pxHigherPriorityTaskWoken = pdTRUE;\r
+1329: }\r
+1330: else\r
+1331: {\r
+1332: mtCOVERAGE_TEST_MARKER();\r
+1333: }\r
+1334: }\r
+1335: else\r
+1336: {\r
+1337: mtCOVERAGE_TEST_MARKER();\r
+1338: }\r
+1339: }\r
+1340: else\r
+1341: {\r
+1342: mtCOVERAGE_TEST_MARKER();\r
+1343: }\r
+1344: }\r
+1345: #endif /* configUSE_QUEUE_SETS */\r
+1346: }\r
+1347: else\r
+1348: {\r
+1349: /* Increment the lock count so the task that unlocks the queue\r
+1350: knows that data was posted while it was locked. */\r
+1351: ++( pxQueue->xTxLock );\r
+BFD02992 0014FC5E LW V0, 20(S8)
+BFD02996 0048FC42 LW V0, 72(V0)
+BFD0299A 6DA0 ADDIU V1, V0, 1
+BFD0299C 0014FC5E LW V0, 20(S8)
+BFD029A0 0048F862 SW V1, 72(V0)
+1352: }\r
+1353: \r
+1354: xReturn = pdPASS;\r
+BFD029A4 ED01 LI V0, 1
+BFD029A6 0010F85E SW V0, 16(S8)
+BFD029AA CC03 B 0xBFD029B2
+BFD029AC 0C00 NOP
+1355: }\r
+1356: else\r
+1357: {\r
+1358: traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\r
+1359: xReturn = errQUEUE_FULL;\r
+BFD029AE 0010F81E SW ZERO, 16(S8)
+1360: }\r
+1361: }\r
+1362: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+BFD029B2 0018FC9E LW A0, 24(S8)
+BFD029B6 4D5E77E8 JALS vPortClearInterruptMaskFromISR
+BFD029B8 4D5E ADDIU T2, T2, -1
+BFD029BA 0C00 NOP
+1363: \r
+1364: return xReturn;\r
+BFD029BC 0010FC5E LW V0, 16(S8)
+1365: }\r
+BFD029C0 0FBE MOVE SP, S8
+BFD029C2 4BE9 LW RA, 36(SP)
+BFD029C4 4BC8 LW S8, 32(SP)
+BFD029C6 4C15 ADDIU SP, SP, 40
+BFD029C8 459F JR16 RA
+BFD029CA 0C00 NOP
+1366: /*-----------------------------------------------------------*/\r
+1367: \r
+1368: BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeeking )\r
+1369: {\r
+BFD0103C 4FE5 ADDIU SP, SP, -56
+BFD0103E CBED SW RA, 52(SP)
+BFD01040 CBCC SW S8, 48(SP)
+BFD01042 0FDD MOVE S8, SP
+BFD01044 0038F89E SW A0, 56(S8)
+BFD01048 003CF8BE SW A1, 60(S8)
+BFD0104C 0040F8DE SW A2, 64(S8)
+BFD01050 0044F8FE SW A3, 68(S8)
+1370: BaseType_t xEntryTimeSet = pdFALSE;\r
+BFD01054 0010F81E SW ZERO, 16(S8)
+1371: TimeOut_t xTimeOut;\r
+1372: int8_t *pcOriginalReadPosition;\r
+1373: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+BFD01058 0038FC5E LW V0, 56(S8)
+BFD0105C 0014F85E SW V0, 20(S8)
+1374: \r
+1375: configASSERT( pxQueue );\r
+BFD01060 0014FC5E LW V0, 20(S8)
+BFD01064 000940A2 BNEZC V0, 0xBFD0107A
+BFD01068 BFD141A2 LUI V0, 0xBFD1
+BFD0106A 3082BFD1 LDC1 F30, 12418(S1)
+BFD0106C 9E3C3082 ADDIU A0, V0, -25028
+BFD0106E 30A09E3C LWC1 F17, 12448(GP)
+BFD01070 055F30A0 ADDIU A1, ZERO, 1375
+BFD01072 055F SUBU V0, A3, A1
+BFD01074 4B7E77E8 JALS vAssertCalled
+BFD01076 4B7E LW K1, 120(SP)
+BFD01078 0C00 NOP
+1376: configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r
+BFD0107A 003CFC5E LW V0, 60(S8)
+BFD0107E 000640A2 BNEZC V0, 0xBFD0108E
+BFD01082 0014FC5E LW V0, 20(S8)
+BFD01086 0040FC42 LW V0, 64(V0)
+BFD0108A 000340A2 BNEZC V0, 0xBFD01094
+BFD0108E ED01 LI V0, 1
+BFD01090 CC02 B 0xBFD01096
+BFD01092 0C00 NOP
+BFD01094 0C40 MOVE V0, ZERO
+BFD01096 000940A2 BNEZC V0, 0xBFD010AC
+BFD0109A BFD141A2 LUI V0, 0xBFD1
+BFD0109C 3082BFD1 LDC1 F30, 12418(S1)
+BFD0109E 9E3C3082 ADDIU A0, V0, -25028
+BFD010A0 30A09E3C LWC1 F17, 12448(GP)
+BFD010A2 056030A0 ADDIU A1, ZERO, 1376
+BFD010A4 0560 ADDU V0, S0, A2
+BFD010A6 4B7E77E8 JALS vAssertCalled
+BFD010A8 4B7E LW K1, 120(SP)
+BFD010AA 0C00 NOP
+1377: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r
+1378: {\r
+1379: configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\r
+BFD010AC 4A8E77E8 JALS xTaskGetSchedulerState
+BFD010AE 4A8E LW S4, 56(SP)
+BFD010B0 0C00 NOP
+BFD010B2 000440A2 BNEZC V0, 0xBFD010BE
+BFD010B6 0040FC5E LW V0, 64(S8)
+BFD010BA 000340A2 BNEZC V0, 0xBFD010C4
+BFD010BE ED01 LI V0, 1
+BFD010C0 CC02 B 0xBFD010C6
+BFD010C2 0C00 NOP
+BFD010C4 0C40 MOVE V0, ZERO
+BFD010C6 000C40A2 BNEZC V0, 0xBFD010E2
+BFD010CA BFD141A2 LUI V0, 0xBFD1
+BFD010CC 3082BFD1 LDC1 F30, 12418(S1)
+BFD010CE 9E3C3082 ADDIU A0, V0, -25028
+BFD010D0 30A09E3C LWC1 F17, 12448(GP)
+BFD010D2 056330A0 ADDIU A1, ZERO, 1379
+BFD010D4 0563 SUBU V0, S1, A2
+BFD010D6 4B7E77E8 JALS vAssertCalled
+BFD010D8 4B7E LW K1, 120(SP)
+BFD010DA 0C00 NOP
+BFD010DC CC02 B 0xBFD010E2
+BFD010DE 0C00 NOP
+1380: }\r
+1381: #endif\r
+1382: \r
+1383: /* This function relaxes the coding standard somewhat to allow return\r
+1384: statements within the function itself. This is done in the interest\r
+1385: of execution time efficiency. */\r
+1386: \r
+1387: for( ;; )\r
+1388: {\r
+1389: taskENTER_CRITICAL();\r
+BFD010E2 33B877E8 JALS vTaskEnterCritical
+BFD010E4 0C0033B8 ADDIU SP, T8, 3072
+BFD010E6 0C00 NOP
+1390: {\r
+1391: /* Is there data in the queue now? To be running the calling task\r
+1392: must be the highest priority task wanting to access the queue. */\r
+1393: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r
+BFD010E8 0014FC5E LW V0, 20(S8)
+BFD010EC 692E LW V0, 56(V0)
+BFD010EE 007040E2 BEQZC V0, 0xBFD011D2
+1394: {\r
+1395: /* Remember the read position in case the queue is only being\r
+1396: peeked. */\r
+1397: pcOriginalReadPosition = pxQueue->u.pcReadFrom;\r
+BFD010F2 0014FC5E LW V0, 20(S8)
+BFD010F6 6923 LW V0, 12(V0)
+BFD010F8 0018F85E SW V0, 24(S8)
+1398: \r
+1399: prvCopyDataFromQueue( pxQueue, pvBuffer );\r
+BFD010FC 0014FC9E LW A0, 20(S8)
+BFD01100 003CFCBE LW A1, 60(S8)
+BFD01104 367A77E8 JALS prvCopyDataFromQueue
+BFD01106 0C00367A LHU S3, 3072(K0)
+BFD01108 0C00 NOP
+1400: \r
+1401: if( xJustPeeking == pdFALSE )\r
+BFD0110A 0044FC5E LW V0, 68(S8)
+BFD0110E 003640A2 BNEZC V0, 0xBFD0117E
+1402: {\r
+1403: traceQUEUE_RECEIVE( pxQueue );\r
+1404: \r
+1405: /* Actually removing data, not just peeking. */\r
+1406: --( pxQueue->uxMessagesWaiting );\r
+BFD01112 0014FC5E LW V0, 20(S8)
+BFD01116 692E LW V0, 56(V0)
+BFD01118 6DAE ADDIU V1, V0, -1
+BFD0111A 0014FC5E LW V0, 20(S8)
+BFD0111E E9AE SW V1, 56(V0)
+1407: \r
+1408: #if ( configUSE_MUTEXES == 1 )\r
+1409: {\r
+1410: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+BFD01120 0014FC5E LW V0, 20(S8)
+BFD01124 6920 LW V0, 0(V0)
+BFD01126 000740A2 BNEZC V0, 0xBFD01138
+1411: {\r
+1412: /* Record the information required to implement\r
+1413: priority inheritance should it become necessary. */\r
+1414: pxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */\r
+BFD0112A 4CE077E8 JALS pvTaskIncrementMutexHeldCount
+BFD0112C 4CE0 ADDIU A3, A3, 0
+BFD0112E 0C00 NOP
+BFD01130 0C62 MOVE V1, V0
+BFD01132 0014FC5E LW V0, 20(S8)
+BFD01136 E9A1 SW V1, 4(V0)
+1415: }\r
+1416: else\r
+1417: {\r
+1418: mtCOVERAGE_TEST_MARKER();\r
+1419: }\r
+1420: }\r
+1421: #endif /* configUSE_MUTEXES */\r
+1422: \r
+1423: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+BFD01138 0014FC5E LW V0, 20(S8)
+BFD0113C 6924 LW V0, 16(V0)
+BFD0113E 004240E2 BEQZC V0, 0xBFD011C6
+1424: {\r
+1425: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r
+BFD01142 0014FC5E LW V0, 20(S8)
+BFD01146 6D28 ADDIU V0, V0, 16
+BFD01148 0C82 MOVE A0, V0
+BFD0114A 22BC77E8 JALS xTaskRemoveFromEventList
+BFD0114C 0C0022BC LWC2 S5, 3072(GP)
+BFD0114E 0C00 NOP
+BFD01150 0C62 MOVE V1, V0
+BFD01152 ED01 LI V0, 1
+BFD01154 0037B443 BNE V1, V0, 0xBFD011C6
+BFD01156 0C000037 SLL AT, S7, 1
+BFD01158 0C00 NOP
+1426: {\r
+1427: queueYIELD_IF_USING_PREEMPTION();\r
+BFD0115A 4E1677E8 JALS ulPortGetCP0Cause
+BFD0115C 4E16 ADDIU S0, S0, -5
+BFD0115E 0C00 NOP
+BFD01160 001CF85E SW V0, 28(S8)
+BFD01164 001CFC5E LW V0, 28(S8)
+BFD01168 01005042 ORI V0, V0, 256
+BFD0116C 001CF85E SW V0, 28(S8)
+BFD01170 001CFC9E LW A0, 28(S8)
+BFD01174 4E2677E8 JALS vPortSetCP0Cause
+BFD01176 4E26 ADDIU S1, S1, 3
+BFD01178 0C00 NOP
+BFD0117A CC25 B 0xBFD011C6
+BFD0117C 0C00 NOP
+1428: }\r
+1429: else\r
+1430: {\r
+1431: mtCOVERAGE_TEST_MARKER();\r
+1432: }\r
+1433: }\r
+1434: else\r
+1435: {\r
+1436: mtCOVERAGE_TEST_MARKER();\r
+1437: }\r
+1438: }\r
+1439: else\r
+1440: {\r
+1441: traceQUEUE_PEEK( pxQueue );\r
+1442: \r
+1443: /* The data is not being removed, so reset the read\r
+1444: pointer. */\r
+1445: pxQueue->u.pcReadFrom = pcOriginalReadPosition;\r
+BFD0117E 0014FC5E LW V0, 20(S8)
+BFD01182 0018FC7E LW V1, 24(S8)
+BFD01186 E9A3 SW V1, 12(V0)
+1446: \r
+1447: /* The data is being left in the queue, so see if there are\r
+1448: any other tasks waiting for the data. */\r
+1449: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+BFD01188 0014FC5E LW V0, 20(S8)
+BFD0118C 6929 LW V0, 36(V0)
+BFD0118E 001A40E2 BEQZC V0, 0xBFD011C6
+1450: {\r
+1451: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+BFD01192 0014FC5E LW V0, 20(S8)
+BFD01196 00243042 ADDIU V0, V0, 36
+BFD0119A 0C82 MOVE A0, V0
+BFD0119C 22BC77E8 JALS xTaskRemoveFromEventList
+BFD0119E 0C0022BC LWC2 S5, 3072(GP)
+BFD011A0 0C00 NOP
+BFD011A2 001040E2 BEQZC V0, 0xBFD011C6
+1452: {\r
+1453: /* The task waiting has a higher priority than this task. */\r
+1454: queueYIELD_IF_USING_PREEMPTION();\r
+BFD011A6 4E1677E8 JALS ulPortGetCP0Cause
+BFD011A8 4E16 ADDIU S0, S0, -5
+BFD011AA 0C00 NOP
+BFD011AC 0020F85E SW V0, 32(S8)
+BFD011B0 0020FC5E LW V0, 32(S8)
+BFD011B4 01005042 ORI V0, V0, 256
+BFD011B8 0020F85E SW V0, 32(S8)
+BFD011BC 0020FC9E LW A0, 32(S8)
+BFD011C0 4E2677E8 JALS vPortSetCP0Cause
+BFD011C2 4E26 ADDIU S1, S1, 3
+BFD011C4 0C00 NOP
+1455: }\r
+1456: else\r
+1457: {\r
+1458: mtCOVERAGE_TEST_MARKER();\r
+1459: }\r
+1460: }\r
+1461: else\r
+1462: {\r
+1463: mtCOVERAGE_TEST_MARKER();\r
+1464: }\r
+1465: }\r
+1466: \r
+1467: taskEXIT_CRITICAL();\r
+BFD011C6 40AA77E8 JALS vTaskExitCritical
+BFD011C8 0C0040AA BNEZC T2, prvCopyDataToQueue
+BFD011CA 0C00 NOP
+1468: return pdPASS;\r
+BFD011CC ED01 LI V0, 1
+BFD011CE CC9A B 0xBFD01304
+BFD011D0 0C00 NOP
+1469: }\r
+1470: else\r
+1471: {\r
+1472: if( xTicksToWait == ( TickType_t ) 0 )\r
+BFD011D2 0040FC5E LW V0, 64(S8)
+BFD011D6 000640A2 BNEZC V0, 0xBFD011E6
+1473: {\r
+1474: /* The queue was empty and no block time is specified (or\r
+1475: the block time has expired) so leave now. */\r
+1476: taskEXIT_CRITICAL();\r
+BFD011DA 40AA77E8 JALS vTaskExitCritical
+BFD011DC 0C0040AA BNEZC T2, 0xBFD029E0
+BFD011DE 0C00 NOP
+1477: traceQUEUE_RECEIVE_FAILED( pxQueue );\r
+1478: return errQUEUE_EMPTY;\r
+BFD011E0 0C40 MOVE V0, ZERO
+BFD011E2 CC90 B 0xBFD01304
+BFD011E4 0C00 NOP
+1479: }\r
+1480: else if( xEntryTimeSet == pdFALSE )\r
+BFD011E6 0010FC5E LW V0, 16(S8)
+BFD011EA 000940A2 BNEZC V0, 0xBFD01200
+1481: {\r
+1482: /* The queue was empty and a block time was specified so\r
+1483: configure the timeout structure. */\r
+1484: vTaskSetTimeOutState( &xTimeOut );\r
+BFD011EE 0028305E ADDIU V0, S8, 40
+BFD011F2 0C82 MOVE A0, V0
+BFD011F4 47A677E8 JALS vTaskSetTimeOutState
+BFD011F8 0C00 NOP
+1485: xEntryTimeSet = pdTRUE;\r
+BFD011FA ED01 LI V0, 1
+BFD011FC 0010F85E SW V0, 16(S8)
+1486: }\r
+1487: else\r
+1488: {\r
+1489: /* Entry time was already set. */\r
+1490: mtCOVERAGE_TEST_MARKER();\r
+1491: }\r
+1492: }\r
+1493: }\r
+1494: taskEXIT_CRITICAL();\r
+BFD01200 40AA77E8 JALS vTaskExitCritical
+BFD01202 0C0040AA BNEZC T2, 0xBFD02A06
+BFD01204 0C00 NOP
+1495: \r
+1496: /* Interrupts and other tasks can send to and receive from the queue\r
+1497: now the critical section has been exited. */\r
+1498: \r
+1499: vTaskSuspendAll();\r
+BFD01206 4EF477E8 JALS vTaskSuspendAll
+BFD01208 4EF4 ADDIU S7, S7, -6
+BFD0120A 0C00 NOP
+1500: prvLockQueue( pxQueue );\r
+BFD0120C 33B877E8 JALS vTaskEnterCritical
+BFD0120E 0C0033B8 ADDIU SP, T8, 3072
+BFD01210 0C00 NOP
+BFD01212 0014FC5E LW V0, 20(S8)
+BFD01216 0044FC62 LW V1, 68(V0)
+BFD0121A ED7F LI V0, -1
+BFD0121C 0005B443 BNE V1, V0, 0xBFD0122A
+BFD0121E 0C000005 SLL ZERO, A1, 1
+BFD01220 0C00 NOP
+BFD01222 0014FC5E LW V0, 20(S8)
+BFD01226 0044F802 SW ZERO, 68(V0)
+BFD0122A 0014FC5E LW V0, 20(S8)
+BFD0122E 0048FC62 LW V1, 72(V0)
+BFD01232 ED7F LI V0, -1
+BFD01234 0005B443 BNE V1, V0, 0xBFD01242
+BFD01236 0C000005 SLL ZERO, A1, 1
+BFD01238 0C00 NOP
+BFD0123A 0014FC5E LW V0, 20(S8)
+BFD0123E 0048F802 SW ZERO, 72(V0)
+BFD01242 40AA77E8 JALS vTaskExitCritical
+BFD01244 0C0040AA BNEZC T2, 0xBFD02A48
+BFD01246 0C00 NOP
+1501: \r
+1502: /* Update the timeout state to see if it has expired yet. */\r
+1503: if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
+BFD01248 0028307E ADDIU V1, S8, 40
+BFD0124C 0040305E ADDIU V0, S8, 64
+BFD01250 0C83 MOVE A0, V1
+BFD01252 0CA2 MOVE A1, V0
+BFD01254 1FF677E8 JALS xTaskCheckForTimeOut
+BFD01256 0C001FF6 LB RA, 3072(S6)
+BFD01258 0C00 NOP
+BFD0125A 004A40A2 BNEZC V0, 0xBFD012F2
+1504: {\r
+1505: if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\r
+BFD0125E 0014FC9E LW A0, 20(S8)
+BFD01262 49D077E8 JALS prvIsQueueEmpty
+BFD01264 49D0 LW T6, 64(SP)
+BFD01266 0C00 NOP
+BFD01268 003940E2 BEQZC V0, 0xBFD012DE
+1506: {\r
+1507: traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\r
+1508: \r
+1509: #if ( configUSE_MUTEXES == 1 )\r
+1510: {\r
+1511: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+BFD0126C 0014FC5E LW V0, 20(S8)
+BFD01270 6920 LW V0, 0(V0)
+BFD01272 000D40A2 BNEZC V0, 0xBFD01290
+1512: {\r
+1513: taskENTER_CRITICAL();\r
+BFD01276 33B877E8 JALS vTaskEnterCritical
+BFD01278 0C0033B8 ADDIU SP, T8, 3072
+BFD0127A 0C00 NOP
+1514: {\r
+1515: vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );\r
+BFD0127C 0014FC5E LW V0, 20(S8)
+BFD01280 6921 LW V0, 4(V0)
+BFD01282 0C82 MOVE A0, V0
+BFD01284 1A9077E8 JALS vTaskPriorityInherit
+BFD01286 0C001A90 SB S4, 3072(S0)
+BFD01288 0C00 NOP
+1516: }\r
+1517: taskEXIT_CRITICAL();\r
+BFD0128A 40AA77E8 JALS vTaskExitCritical
+BFD0128C 0C0040AA BNEZC T2, 0xBFD02A90
+BFD0128E 0C00 NOP
+1518: }\r
+1519: else\r
+1520: {\r
+1521: mtCOVERAGE_TEST_MARKER();\r
+1522: }\r
+1523: }\r
+1524: #endif\r
+1525: \r
+1526: vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r
+BFD01290 0014FC5E LW V0, 20(S8)
+BFD01294 00243062 ADDIU V1, V0, 36
+BFD01298 0040FC5E LW V0, 64(S8)
+BFD0129C 0C83 MOVE A0, V1
+BFD0129E 0CA2 MOVE A1, V0
+BFD012A0 2F3A77E8 JALS vTaskPlaceOnEventList
+BFD012A2 2F3A ANDI A2, V1, 0x20
+BFD012A4 0C00 NOP
+1527: prvUnlockQueue( pxQueue );\r
+BFD012A6 0014FC9E LW A0, 20(S8)
+BFD012AA 1DEE77E8 JALS prvUnlockQueue
+BFD012AC 0C001DEE LB T7, 3072(T6)
+BFD012AE 0C00 NOP
+1528: if( xTaskResumeAll() == pdFALSE )\r
+BFD012B0 158E77E8 JALS xTaskResumeAll
+BFD012B2 0C00158E LBU T4, 3072(T6)
+BFD012B4 0C00 NOP
+BFD012B6 FF1340A2 BNEZC V0, 0xBFD010E0
+BFD012B8 77E8FF13 LW T8, 30696(S3)
+1529: {\r
+1530: portYIELD_WITHIN_API();\r
+BFD012BA 4E1677E8 JALS ulPortGetCP0Cause
+BFD012BC 4E16 ADDIU S0, S0, -5
+BFD012BE 0C00 NOP
+BFD012C0 0024F85E SW V0, 36(S8)
+BFD012C4 0024FC5E LW V0, 36(S8)
+BFD012C8 01005042 ORI V0, V0, 256
+BFD012CC 0024F85E SW V0, 36(S8)
+BFD012D0 0024FC9E LW A0, 36(S8)
+BFD012D4 4E2677E8 JALS vPortSetCP0Cause
+BFD012D6 4E26 ADDIU S1, S1, 3
+BFD012D8 0C00 NOP
+1531: }\r
+1532: else\r
+1533: {\r
+1534: mtCOVERAGE_TEST_MARKER();\r
+1535: }\r
+1536: }\r
+1537: else\r
+1538: {\r
+1539: /* Try again. */\r
+1540: prvUnlockQueue( pxQueue );\r
+BFD012DE 0014FC9E LW A0, 20(S8)
+BFD012E2 1DEE77E8 JALS prvUnlockQueue
+BFD012E4 0C001DEE LB T7, 3072(T6)
+BFD012E6 0C00 NOP
+1541: ( void ) xTaskResumeAll();\r
+BFD012E8 158E77E8 JALS xTaskResumeAll
+BFD012EA 0C00158E LBU T4, 3072(T6)
+BFD012EC 0C00 NOP
+1542: }\r
+1543: }\r
+1544: else\r
+1545: {\r
+1546: prvUnlockQueue( pxQueue );\r
+BFD012F2 0014FC9E LW A0, 20(S8)
+BFD012F6 1DEE77E8 JALS prvUnlockQueue
+BFD012F8 0C001DEE LB T7, 3072(T6)
+BFD012FA 0C00 NOP
+1547: ( void ) xTaskResumeAll();\r
+BFD012FC 158E77E8 JALS xTaskResumeAll
+BFD012FE 0C00158E LBU T4, 3072(T6)
+BFD01300 0C00 NOP
+1548: traceQUEUE_RECEIVE_FAILED( pxQueue );\r
+1549: return errQUEUE_EMPTY;\r
+BFD01302 0C40 MOVE V0, ZERO
+1550: }\r
+1551: }\r
+BFD010E0 0C00 NOP
+BFD012DA CF03 B 0xBFD010E2
+BFD012DC 0C00 NOP
+BFD012EE CEF9 B 0xBFD010E2
+BFD012F0 0C00 NOP
+1552: }\r
+BFD01304 0FBE MOVE SP, S8
+BFD01306 4BED LW RA, 52(SP)
+BFD01308 4BCC LW S8, 48(SP)
+BFD0130A 4C1D ADDIU SP, SP, 56
+BFD0130C 459F JR16 RA
+BFD0130E 0C00 NOP
+1553: /*-----------------------------------------------------------*/\r
+1554: \r
+1555: BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )\r
+1556: {\r
+BFD03AC8 4FED ADDIU SP, SP, -40
+BFD03ACA CBE9 SW RA, 36(SP)
+BFD03ACC CBC8 SW S8, 32(SP)
+BFD03ACE 0FDD MOVE S8, SP
+BFD03AD0 0028F89E SW A0, 40(S8)
+BFD03AD4 002CF8BE SW A1, 44(S8)
+BFD03AD8 0030F8DE SW A2, 48(S8)
+1557: BaseType_t xReturn;\r
+1558: UBaseType_t uxSavedInterruptStatus;\r
+1559: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+BFD03ADC 0028FC5E LW V0, 40(S8)
+BFD03AE0 0014F85E SW V0, 20(S8)
+1560: \r
+1561: configASSERT( pxQueue );\r
+BFD03AE4 0014FC5E LW V0, 20(S8)
+BFD03AE8 000940A2 BNEZC V0, 0xBFD03AFE
+BFD03AEC BFD141A2 LUI V0, 0xBFD1
+BFD03AEE 3082BFD1 LDC1 F30, 12418(S1)
+BFD03AF0 9E3C3082 ADDIU A0, V0, -25028
+BFD03AF2 30A09E3C LWC1 F17, 12448(GP)
+BFD03AF4 061930A0 ADDIU A1, ZERO, 1561
+BFD03AF6 0619 SUBU A0, A0, S1
+BFD03AF8 4B7E77E8 JALS vAssertCalled
+BFD03AFA 4B7E LW K1, 120(SP)
+BFD03AFC 0C00 NOP
+1562: configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r
+BFD03AFE 002CFC5E LW V0, 44(S8)
+BFD03B02 000640A2 BNEZC V0, 0xBFD03B12
+BFD03B06 0014FC5E LW V0, 20(S8)
+BFD03B0A 0040FC42 LW V0, 64(V0)
+BFD03B0E 000340A2 BNEZC V0, 0xBFD03B18
+BFD03B12 ED01 LI V0, 1
+BFD03B14 CC02 B 0xBFD03B1A
+BFD03B16 0C00 NOP
+BFD03B18 0C40 MOVE V0, ZERO
+BFD03B1A 000940A2 BNEZC V0, 0xBFD03B30
+BFD03B1E BFD141A2 LUI V0, 0xBFD1
+BFD03B20 3082BFD1 LDC1 F30, 12418(S1)
+BFD03B22 9E3C3082 ADDIU A0, V0, -25028
+BFD03B24 30A09E3C LWC1 F17, 12448(GP)
+BFD03B26 061A30A0 ADDIU A1, ZERO, 1562
+BFD03B28 061A ADDU A0, A1, S1
+BFD03B2A 4B7E77E8 JALS vAssertCalled
+BFD03B2C 4B7E LW K1, 120(SP)
+BFD03B2E 0C00 NOP
+1563: \r
+1564: /* RTOS ports that support interrupt nesting have the concept of a maximum\r
+1565: system call (or maximum API call) interrupt priority. Interrupts that are\r
+1566: above the maximum system call priority are kept permanently enabled, even\r
+1567: when the RTOS kernel is in a critical section, but cannot make any calls to\r
+1568: FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h\r
+1569: then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r
+1570: failure if a FreeRTOS API function is called from an interrupt that has been\r
+1571: assigned a priority above the configured maximum system call priority.\r
+1572: Only FreeRTOS functions that end in FromISR can be called from interrupts\r
+1573: that have been assigned a priority at or (logically) below the maximum\r
+1574: system call interrupt priority. FreeRTOS maintains a separate interrupt\r
+1575: safe API to ensure interrupt entry is as fast and as simple as possible.\r
+1576: More information (albeit Cortex-M specific) is provided on the following\r
+1577: link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r
+1578: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
+1579: \r
+1580: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+BFD03B30 475E77E8 JALS uxPortSetInterruptMaskFromISR
+BFD03B34 0C00 NOP
+BFD03B36 0018F85E SW V0, 24(S8)
+1581: {\r
+1582: /* Cannot block in an ISR, so check there is data available. */\r
+1583: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r
+BFD03B3A 0014FC5E LW V0, 20(S8)
+BFD03B3E 692E LW V0, 56(V0)
+BFD03B40 003C40E2 BEQZC V0, 0xBFD03BBC
+1584: {\r
+1585: traceQUEUE_RECEIVE_FROM_ISR( pxQueue );\r
+1586: \r
+1587: prvCopyDataFromQueue( pxQueue, pvBuffer );\r
+BFD03B44 0014FC9E LW A0, 20(S8)
+BFD03B48 002CFCBE LW A1, 44(S8)
+BFD03B4C 367A77E8 JALS prvCopyDataFromQueue
+BFD03B4E 0C00367A LHU S3, 3072(K0)
+BFD03B50 0C00 NOP
+1588: --( pxQueue->uxMessagesWaiting );\r
+BFD03B52 0014FC5E LW V0, 20(S8)
+BFD03B56 692E LW V0, 56(V0)
+BFD03B58 6DAE ADDIU V1, V0, -1
+BFD03B5A 0014FC5E LW V0, 20(S8)
+BFD03B5E E9AE SW V1, 56(V0)
+1589: \r
+1590: /* If the queue is locked the event list will not be modified.\r
+1591: Instead update the lock count so the task that unlocks the queue\r
+1592: will know that an ISR has removed data while the queue was\r
+1593: locked. */\r
+1594: if( pxQueue->xRxLock == queueUNLOCKED )\r
+BFD03B60 0014FC5E LW V0, 20(S8)
+BFD03B64 0044FC62 LW V1, 68(V0)
+BFD03B68 ED7F LI V0, -1
+BFD03B6A 0019B443 BNE V1, V0, 0xBFD03BA0
+BFD03B6C 0C000019 SLL ZERO, T9, 1
+BFD03B6E 0C00 NOP
+1595: {\r
+1596: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+BFD03B70 0014FC5E LW V0, 20(S8)
+BFD03B74 6924 LW V0, 16(V0)
+BFD03B76 001C40E2 BEQZC V0, 0xBFD03BB2
+1597: {\r
+1598: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+BFD03B7A 0014FC5E LW V0, 20(S8)
+BFD03B7E 6D28 ADDIU V0, V0, 16
+BFD03B80 0C82 MOVE A0, V0
+BFD03B82 22BC77E8 JALS xTaskRemoveFromEventList
+BFD03B84 0C0022BC LWC2 S5, 3072(GP)
+BFD03B86 0C00 NOP
+BFD03B88 001340E2 BEQZC V0, 0xBFD03BB2
+1599: {\r
+1600: /* The task waiting has a higher priority than us so\r
+1601: force a context switch. */\r
+1602: if( pxHigherPriorityTaskWoken != NULL )\r
+BFD03B8C 0030FC5E LW V0, 48(S8)
+BFD03B90 000F40E2 BEQZC V0, 0xBFD03BB2
+1603: {\r
+1604: *pxHigherPriorityTaskWoken = pdTRUE;\r
+BFD03B94 0030FC5E LW V0, 48(S8)
+BFD03B98 ED81 LI V1, 1
+BFD03B9A E9A0 SW V1, 0(V0)
+BFD03B9C CC0A B 0xBFD03BB2
+BFD03B9E 0C00 NOP
+1605: }\r
+1606: else\r
+1607: {\r
+1608: mtCOVERAGE_TEST_MARKER();\r
+1609: }\r
+1610: }\r
+1611: else\r
+1612: {\r
+1613: mtCOVERAGE_TEST_MARKER();\r
+1614: }\r
+1615: }\r
+1616: else\r
+1617: {\r
+1618: mtCOVERAGE_TEST_MARKER();\r
+1619: }\r
+1620: }\r
+1621: else\r
+1622: {\r
+1623: /* Increment the lock count so the task that unlocks the queue\r
+1624: knows that data was removed while it was locked. */\r
+1625: ++( pxQueue->xRxLock );\r
+BFD03BA0 0014FC5E LW V0, 20(S8)
+BFD03BA4 0044FC42 LW V0, 68(V0)
+BFD03BA8 6DA0 ADDIU V1, V0, 1
+BFD03BAA 0014FC5E LW V0, 20(S8)
+BFD03BAE 0044F862 SW V1, 68(V0)
+1626: }\r
+1627: \r
+1628: xReturn = pdPASS;\r
+BFD03BB2 ED01 LI V0, 1
+BFD03BB4 0010F85E SW V0, 16(S8)
+BFD03BB8 CC03 B 0xBFD03BC0
+BFD03BBA 0C00 NOP
+1629: }\r
+1630: else\r
+1631: {\r
+1632: xReturn = pdFAIL;\r
+BFD03BBC 0010F81E SW ZERO, 16(S8)
+1633: traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );\r
+1634: }\r
+1635: }\r
+1636: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+BFD03BC0 0018FC9E LW A0, 24(S8)
+BFD03BC4 4D5E77E8 JALS vPortClearInterruptMaskFromISR
+BFD03BC6 4D5E ADDIU T2, T2, -1
+BFD03BC8 0C00 NOP
+1637: \r
+1638: return xReturn;\r
+BFD03BCA 0010FC5E LW V0, 16(S8)
+1639: }\r
+BFD03BCE 0FBE MOVE SP, S8
+BFD03BD0 4BE9 LW RA, 36(SP)
+BFD03BD2 4BC8 LW S8, 32(SP)
+BFD03BD4 4C15 ADDIU SP, SP, 40
+BFD03BD6 459F JR16 RA
+BFD03BD8 0C00 NOP
+1640: /*-----------------------------------------------------------*/\r
+1641: \r
+1642: BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer )\r
+1643: {\r
+BFD04824 4FED ADDIU SP, SP, -40
+BFD04826 CBE9 SW RA, 36(SP)
+BFD04828 CBC8 SW S8, 32(SP)
+BFD0482A 0FDD MOVE S8, SP
+BFD0482C 0028F89E SW A0, 40(S8)
+BFD04830 002CF8BE SW A1, 44(S8)
+1644: BaseType_t xReturn;\r
+1645: UBaseType_t uxSavedInterruptStatus;\r
+1646: int8_t *pcOriginalReadPosition;\r
+1647: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+BFD04834 0028FC5E LW V0, 40(S8)
+BFD04838 0014F85E SW V0, 20(S8)
+1648: \r
+1649: configASSERT( pxQueue );\r
+BFD0483C 0014FC5E LW V0, 20(S8)
+BFD04840 000940A2 BNEZC V0, 0xBFD04856
+BFD04844 BFD141A2 LUI V0, 0xBFD1
+BFD04846 3082BFD1 LDC1 F30, 12418(S1)
+BFD04848 9E3C3082 ADDIU A0, V0, -25028
+BFD0484A 30A09E3C LWC1 F17, 12448(GP)
+BFD0484C 067130A0 ADDIU A1, ZERO, 1649
+BFD0484E 0671 SUBU A0, S0, A3
+BFD04850 4B7E77E8 JALS vAssertCalled
+BFD04852 4B7E LW K1, 120(SP)
+BFD04854 0C00 NOP
+1650: configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r
+BFD04856 002CFC5E LW V0, 44(S8)
+BFD0485A 000640A2 BNEZC V0, 0xBFD0486A
+BFD0485E 0014FC5E LW V0, 20(S8)
+BFD04862 0040FC42 LW V0, 64(V0)
+BFD04866 000340A2 BNEZC V0, 0xBFD04870
+BFD0486A ED01 LI V0, 1
+BFD0486C CC02 B 0xBFD04872
+BFD0486E 0C00 NOP
+BFD04870 0C40 MOVE V0, ZERO
+BFD04872 000940A2 BNEZC V0, 0xBFD04888
+BFD04876 BFD141A2 LUI V0, 0xBFD1
+BFD04878 3082BFD1 LDC1 F30, 12418(S1)
+BFD0487A 9E3C3082 ADDIU A0, V0, -25028
+BFD0487C 30A09E3C LWC1 F17, 12448(GP)
+BFD0487E 067230A0 ADDIU A1, ZERO, 1650
+BFD04880 0672 ADDU A0, S1, A3
+BFD04882 4B7E77E8 JALS vAssertCalled
+BFD04884 4B7E LW K1, 120(SP)
+BFD04886 0C00 NOP
+1651: configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */\r
+BFD04888 0014FC5E LW V0, 20(S8)
+BFD0488C 0040FC42 LW V0, 64(V0)
+BFD04890 000940A2 BNEZC V0, 0xBFD048A6
+BFD04894 BFD141A2 LUI V0, 0xBFD1
+BFD04896 3082BFD1 LDC1 F30, 12418(S1)
+BFD04898 9E3C3082 ADDIU A0, V0, -25028
+BFD0489A 30A09E3C LWC1 F17, 12448(GP)
+BFD0489C 067330A0 ADDIU A1, ZERO, 1651
+BFD0489E 0673 SUBU A0, S1, A3
+BFD048A0 4B7E77E8 JALS vAssertCalled
+BFD048A2 4B7E LW K1, 120(SP)
+BFD048A4 0C00 NOP
+1652: \r
+1653: /* RTOS ports that support interrupt nesting have the concept of a maximum\r
+1654: system call (or maximum API call) interrupt priority. Interrupts that are\r
+1655: above the maximum system call priority are kept permanently enabled, even\r
+1656: when the RTOS kernel is in a critical section, but cannot make any calls to\r
+1657: FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h\r
+1658: then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r
+1659: failure if a FreeRTOS API function is called from an interrupt that has been\r
+1660: assigned a priority above the configured maximum system call priority.\r
+1661: Only FreeRTOS functions that end in FromISR can be called from interrupts\r
+1662: that have been assigned a priority at or (logically) below the maximum\r
+1663: system call interrupt priority. FreeRTOS maintains a separate interrupt\r
+1664: safe API to ensure interrupt entry is as fast and as simple as possible.\r
+1665: More information (albeit Cortex-M specific) is provided on the following\r
+1666: link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r
+1667: portASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r
+1668: \r
+1669: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+BFD048A6 475E77E8 JALS uxPortSetInterruptMaskFromISR
+BFD048AA 0C00 NOP
+BFD048AC 0018F85E SW V0, 24(S8)
+1670: {\r
+1671: /* Cannot block in an ISR, so check there is data available. */\r
+1672: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r
+BFD048B0 0014FC5E LW V0, 20(S8)
+BFD048B4 692E LW V0, 56(V0)
+BFD048B6 001640E2 BEQZC V0, 0xBFD048E6
+1673: {\r
+1674: traceQUEUE_PEEK_FROM_ISR( pxQueue );\r
+1675: \r
+1676: /* Remember the read position so it can be reset as nothing is\r
+1677: actually being removed from the queue. */\r
+1678: pcOriginalReadPosition = pxQueue->u.pcReadFrom;\r
+BFD048BA 0014FC5E LW V0, 20(S8)
+BFD048BE 6923 LW V0, 12(V0)
+BFD048C0 001CF85E SW V0, 28(S8)
+1679: prvCopyDataFromQueue( pxQueue, pvBuffer );\r
+BFD048C4 0014FC9E LW A0, 20(S8)
+BFD048C8 002CFCBE LW A1, 44(S8)
+BFD048CC 367A77E8 JALS prvCopyDataFromQueue
+BFD048CE 0C00367A LHU S3, 3072(K0)
+BFD048D0 0C00 NOP
+1680: pxQueue->u.pcReadFrom = pcOriginalReadPosition;\r
+BFD048D2 0014FC5E LW V0, 20(S8)
+BFD048D6 001CFC7E LW V1, 28(S8)
+BFD048DA E9A3 SW V1, 12(V0)
+1681: \r
+1682: xReturn = pdPASS;\r
+BFD048DC ED01 LI V0, 1
+BFD048DE 0010F85E SW V0, 16(S8)
+BFD048E2 CC03 B 0xBFD048EA
+BFD048E4 0C00 NOP
+1683: }\r
+1684: else\r
+1685: {\r
+1686: xReturn = pdFAIL;\r
+BFD048E6 0010F81E SW ZERO, 16(S8)
+1687: traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );\r
+1688: }\r
+1689: }\r
+1690: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+BFD048EA 0018FC9E LW A0, 24(S8)
+BFD048EE 4D5E77E8 JALS vPortClearInterruptMaskFromISR
+BFD048F0 4D5E ADDIU T2, T2, -1
+BFD048F2 0C00 NOP
+1691: \r
+1692: return xReturn;\r
+BFD048F4 0010FC5E LW V0, 16(S8)
+1693: }\r
+BFD048F8 0FBE MOVE SP, S8
+BFD048FA 4BE9 LW RA, 36(SP)
+BFD048FC 4BC8 LW S8, 32(SP)
+BFD048FE 4C15 ADDIU SP, SP, 40
+BFD04900 459F JR16 RA
+BFD04902 0C00 NOP
+1694: /*-----------------------------------------------------------*/\r
+1695: \r
+1696: UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )\r
+1697: {\r
+BFD08B2C 4FF1 ADDIU SP, SP, -32
+BFD08B2E CBE7 SW RA, 28(SP)
+BFD08B30 CBC6 SW S8, 24(SP)
+BFD08B32 0FDD MOVE S8, SP
+BFD08B34 0020F89E SW A0, 32(S8)
+1698: UBaseType_t uxReturn;\r
+1699: \r
+1700: configASSERT( xQueue );\r
+BFD08B38 0020FC5E LW V0, 32(S8)
+BFD08B3C 000940A2 BNEZC V0, 0xBFD08B52
+BFD08B40 BFD141A2 LUI V0, 0xBFD1
+BFD08B42 3082BFD1 LDC1 F30, 12418(S1)
+BFD08B44 9E3C3082 ADDIU A0, V0, -25028
+BFD08B46 30A09E3C LWC1 F17, 12448(GP)
+BFD08B48 06A430A0 ADDIU A1, ZERO, 1700
+BFD08B4A 06A4 ADDU A1, V0, V0
+BFD08B4C 4B7E77E8 JALS vAssertCalled
+BFD08B4E 4B7E LW K1, 120(SP)
+BFD08B50 0C00 NOP
+1701: \r
+1702: taskENTER_CRITICAL();\r
+BFD08B52 33B877E8 JALS vTaskEnterCritical
+BFD08B54 0C0033B8 ADDIU SP, T8, 3072
+BFD08B56 0C00 NOP
+1703: {\r
+1704: uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;\r
+BFD08B58 0020FC5E LW V0, 32(S8)
+BFD08B5C 692E LW V0, 56(V0)
+BFD08B5E 0010F85E SW V0, 16(S8)
+1705: }\r
+1706: taskEXIT_CRITICAL();\r
+BFD08B62 40AA77E8 JALS vTaskExitCritical
+BFD08B64 0C0040AA BNEZC T2, 0xBFD0A368
+BFD08B66 0C00 NOP
+1707: \r
+1708: return uxReturn;\r
+BFD08B68 0010FC5E LW V0, 16(S8)
+1709: } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\r
+BFD08B6C 0FBE MOVE SP, S8
+BFD08B6E 4BE7 LW RA, 28(SP)
+BFD08B70 4BC6 LW S8, 24(SP)
+BFD08B72 4C11 ADDIU SP, SP, 32
+BFD08B74 459F JR16 RA
+BFD08B76 0C00 NOP
+1710: /*-----------------------------------------------------------*/\r
+1711: \r
+1712: UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )\r
+1713: {\r
+BFD082D4 4FF1 ADDIU SP, SP, -32
+BFD082D6 CBE7 SW RA, 28(SP)
+BFD082D8 CBC6 SW S8, 24(SP)
+BFD082DA 0FDD MOVE S8, SP
+BFD082DC 0020F89E SW A0, 32(S8)
+1714: UBaseType_t uxReturn;\r
+1715: Queue_t *pxQueue;\r
+1716: \r
+1717: pxQueue = ( Queue_t * ) xQueue;\r
+BFD082E0 0020FC5E LW V0, 32(S8)
+BFD082E4 0010F85E SW V0, 16(S8)
+1718: configASSERT( pxQueue );\r
+BFD082E8 0010FC5E LW V0, 16(S8)
+BFD082EC 000940A2 BNEZC V0, 0xBFD08302
+BFD082F0 BFD141A2 LUI V0, 0xBFD1
+BFD082F2 3082BFD1 LDC1 F30, 12418(S1)
+BFD082F4 9E3C3082 ADDIU A0, V0, -25028
+BFD082F6 30A09E3C LWC1 F17, 12448(GP)
+BFD082F8 06B630A0 ADDIU A1, ZERO, 1718
+BFD082FA 06B6 ADDU A1, V1, V1
+BFD082FC 4B7E77E8 JALS vAssertCalled
+BFD082FE 4B7E LW K1, 120(SP)
+BFD08300 0C00 NOP
+1719: \r
+1720: taskENTER_CRITICAL();\r
+BFD08302 33B877E8 JALS vTaskEnterCritical
+BFD08304 0C0033B8 ADDIU SP, T8, 3072
+BFD08306 0C00 NOP
+1721: {\r
+1722: uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;\r
+BFD08308 0010FC5E LW V0, 16(S8)
+BFD0830C 69AF LW V1, 60(V0)
+BFD0830E 0010FC5E LW V0, 16(S8)
+BFD08312 692E LW V0, 56(V0)
+BFD08314 0527 SUBU V0, V1, V0
+BFD08316 0014F85E SW V0, 20(S8)
+1723: }\r
+1724: taskEXIT_CRITICAL();\r
+BFD0831A 40AA77E8 JALS vTaskExitCritical
+BFD0831C 0C0040AA BNEZC T2, 0xBFD09B20
+BFD0831E 0C00 NOP
+1725: \r
+1726: return uxReturn;\r
+BFD08320 0014FC5E LW V0, 20(S8)
+1727: } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\r
+BFD08324 0FBE MOVE SP, S8
+BFD08326 4BE7 LW RA, 28(SP)
+BFD08328 4BC6 LW S8, 24(SP)
+BFD0832A 4C11 ADDIU SP, SP, 32
+BFD0832C 459F JR16 RA
+BFD0832E 0C00 NOP
+1728: /*-----------------------------------------------------------*/\r
+1729: \r
+1730: UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )\r
+1731: {\r
+BFD09360 4FF1 ADDIU SP, SP, -32
+BFD09362 CBE7 SW RA, 28(SP)
+BFD09364 CBC6 SW S8, 24(SP)
+BFD09366 0FDD MOVE S8, SP
+BFD09368 0020F89E SW A0, 32(S8)
+1732: UBaseType_t uxReturn;\r
+1733: \r
+1734: configASSERT( xQueue );\r
+BFD0936C 0020FC5E LW V0, 32(S8)
+BFD09370 000940A2 BNEZC V0, 0xBFD09386
+BFD09374 BFD141A2 LUI V0, 0xBFD1
+BFD09376 3082BFD1 LDC1 F30, 12418(S1)
+BFD09378 9E3C3082 ADDIU A0, V0, -25028
+BFD0937A 30A09E3C LWC1 F17, 12448(GP)
+BFD0937C 06C630A0 ADDIU A1, ZERO, 1734
+BFD0937E 06C6 ADDU A1, V1, A0
+BFD09380 4B7E77E8 JALS vAssertCalled
+BFD09382 4B7E LW K1, 120(SP)
+BFD09384 0C00 NOP
+1735: \r
+1736: uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;\r
+BFD09386 0020FC5E LW V0, 32(S8)
+BFD0938A 692E LW V0, 56(V0)
+BFD0938C 0010F85E SW V0, 16(S8)
+1737: \r
+1738: return uxReturn;\r
+BFD09390 0010FC5E LW V0, 16(S8)
+1739: } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\r
+BFD09394 0FBE MOVE SP, S8
+BFD09396 4BE7 LW RA, 28(SP)
+BFD09398 4BC6 LW S8, 24(SP)
+BFD0939A 4C11 ADDIU SP, SP, 32
+BFD0939C 459F JR16 RA
+BFD0939E 0C00 NOP
+1740: /*-----------------------------------------------------------*/\r
+1741: \r
+1742: void vQueueDelete( QueueHandle_t xQueue )\r
+1743: {\r
+BFD09188 4FF1 ADDIU SP, SP, -32
+BFD0918A CBE7 SW RA, 28(SP)
+BFD0918C CBC6 SW S8, 24(SP)
+BFD0918E 0FDD MOVE S8, SP
+BFD09190 0020F89E SW A0, 32(S8)
+1744: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+BFD09194 0020FC5E LW V0, 32(S8)
+BFD09198 0010F85E SW V0, 16(S8)
+1745: \r
+1746: configASSERT( pxQueue );\r
+BFD0919C 0010FC5E LW V0, 16(S8)
+BFD091A0 000940A2 BNEZC V0, 0xBFD091B6
+BFD091A4 BFD141A2 LUI V0, 0xBFD1
+BFD091A6 3082BFD1 LDC1 F30, 12418(S1)
+BFD091A8 9E3C3082 ADDIU A0, V0, -25028
+BFD091AA 30A09E3C LWC1 F17, 12448(GP)
+BFD091AC 06D230A0 ADDIU A1, ZERO, 1746
+BFD091AE 06D2 ADDU A1, S1, A1
+BFD091B0 4B7E77E8 JALS vAssertCalled
+BFD091B2 4B7E LW K1, 120(SP)
+BFD091B4 0C00 NOP
+1747: \r
+1748: traceQUEUE_DELETE( pxQueue );\r
+1749: #if ( configQUEUE_REGISTRY_SIZE > 0 )\r
+1750: {\r
+1751: vQueueUnregisterQueue( pxQueue );\r
+1752: }\r
+1753: #endif\r
+1754: vPortFree( pxQueue );\r
+BFD091B6 0010FC9E LW A0, 16(S8)
+BFD091BA 2FEA77E8 JALS vPortFree
+BFD091BC 2FEA ANDI A3, A2, 0x20
+BFD091BE 0C00 NOP
+1755: }\r
+BFD091C0 0FBE MOVE SP, S8
+BFD091C2 4BE7 LW RA, 28(SP)
+BFD091C4 4BC6 LW S8, 24(SP)
+BFD091C6 4C11 ADDIU SP, SP, 32
+BFD091C8 459F JR16 RA
+BFD091CA 0C00 NOP
+1756: /*-----------------------------------------------------------*/\r
+1757: \r
+1758: #if ( configUSE_TRACE_FACILITY == 1 )\r
+1759: \r
+1760: UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )\r
+1761: {\r
+1762: return ( ( Queue_t * ) xQueue )->uxQueueNumber;\r
+1763: }\r
+1764: \r
+1765: #endif /* configUSE_TRACE_FACILITY */\r
+1766: /*-----------------------------------------------------------*/\r
+1767: \r
+1768: #if ( configUSE_TRACE_FACILITY == 1 )\r
+1769: \r
+1770: void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )\r
+1771: {\r
+1772: ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;\r
+1773: }\r
+1774: \r
+1775: #endif /* configUSE_TRACE_FACILITY */\r
+1776: /*-----------------------------------------------------------*/\r
+1777: \r
+1778: #if ( configUSE_TRACE_FACILITY == 1 )\r
+1779: \r
+1780: uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )\r
+1781: {\r
+1782: return ( ( Queue_t * ) xQueue )->ucQueueType;\r
+1783: }\r
+1784: \r
+1785: #endif /* configUSE_TRACE_FACILITY */\r
+1786: /*-----------------------------------------------------------*/\r
+1787: \r
+1788: static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )\r
+1789: {\r
+BFD029CC 4FF1 ADDIU SP, SP, -32
+BFD029CE CBE7 SW RA, 28(SP)
+BFD029D0 CBC6 SW S8, 24(SP)
+BFD029D2 0FDD MOVE S8, SP
+BFD029D4 0020F89E SW A0, 32(S8)
+BFD029D8 0024F8BE SW A1, 36(S8)
+BFD029DC 0028F8DE SW A2, 40(S8)
+1790: BaseType_t xReturn = pdFALSE;\r
+BFD029E0 0010F81E SW ZERO, 16(S8)
+1791: \r
+1792: if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )\r
+BFD029E4 0020FC5E LW V0, 32(S8)
+BFD029E8 0040FC42 LW V0, 64(V0)
+BFD029EC 001340A2 BNEZC V0, 0xBFD02A16
+1793: {\r
+1794: #if ( configUSE_MUTEXES == 1 )\r
+1795: {\r
+1796: if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+BFD029F0 0020FC5E LW V0, 32(S8)
+BFD029F4 6920 LW V0, 0(V0)
+BFD029F6 008140A2 BNEZC V0, 0xBFD02AFC
+1797: {\r
+1798: /* The mutex is no longer being held. */\r
+1799: xReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );\r
+BFD029FA 0020FC5E LW V0, 32(S8)
+BFD029FE 6921 LW V0, 4(V0)
+BFD02A00 0C82 MOVE A0, V0
+BFD02A02 178277E8 JALS xTaskPriorityDisinherit
+BFD02A04 0C001782 LBU GP, 3072(V0)
+BFD02A06 0C00 NOP
+BFD02A08 0010F85E SW V0, 16(S8)
+1800: pxQueue->pxMutexHolder = NULL;\r
+BFD02A0C 0020FC5E LW V0, 32(S8)
+BFD02A10 E821 SW S0, 4(V0)
+BFD02A12 CC74 B 0xBFD02AFC
+BFD02A14 0C00 NOP
+1801: }\r
+1802: else\r
+1803: {\r
+1804: mtCOVERAGE_TEST_MARKER();\r
+1805: }\r
+1806: }\r
+1807: #endif /* configUSE_MUTEXES */\r
+1808: }\r
+1809: else if( xPosition == queueSEND_TO_BACK )\r
+BFD02A16 0028FC5E LW V0, 40(S8)
+BFD02A1A 002B40A2 BNEZC V0, 0xBFD02A74
+1810: {\r
+1811: ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */\r
+BFD02A1E 0020FC5E LW V0, 32(S8)
+BFD02A22 69A2 LW V1, 8(V0)
+BFD02A24 0020FC5E LW V0, 32(S8)
+BFD02A28 0040FC42 LW V0, 64(V0)
+BFD02A2C 0C83 MOVE A0, V1
+BFD02A2E 0024FCBE LW A1, 36(S8)
+BFD02A32 0CC2 MOVE A2, V0
+BFD02A34 1BB477E8 JALS 0xBFD03768
+BFD02A36 0C001BB4 SB SP, 3072(S4)
+BFD02A38 0C00 NOP
+1812: pxQueue->pcWriteTo += pxQueue->uxItemSize;\r
+BFD02A3A 0020FC5E LW V0, 32(S8)
+BFD02A3E 69A2 LW V1, 8(V0)
+BFD02A40 0020FC5E LW V0, 32(S8)
+BFD02A44 0040FC42 LW V0, 64(V0)
+BFD02A48 05A6 ADDU V1, V1, V0
+BFD02A4A 0020FC5E LW V0, 32(S8)
+BFD02A4E E9A2 SW V1, 8(V0)
+1813: if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */\r
+BFD02A50 0020FC5E LW V0, 32(S8)
+BFD02A54 69A2 LW V1, 8(V0)
+BFD02A56 0020FC5E LW V0, 32(S8)
+BFD02A5A 6921 LW V0, 4(V0)
+BFD02A5C 13900043 SLTU V0, V1, V0
+BFD02A5E 40A21390 ADDI GP, S0, 16546
+BFD02A60 004C40A2 BNEZC V0, 0xBFD02AFC
+1814: {\r
+1815: pxQueue->pcWriteTo = pxQueue->pcHead;\r
+BFD02A64 0020FC5E LW V0, 32(S8)
+BFD02A68 69A0 LW V1, 0(V0)
+BFD02A6A 0020FC5E LW V0, 32(S8)
+BFD02A6E E9A2 SW V1, 8(V0)
+BFD02A70 CC45 B 0xBFD02AFC
+BFD02A72 0C00 NOP
+1816: }\r
+1817: else\r
+1818: {\r
+1819: mtCOVERAGE_TEST_MARKER();\r
+1820: }\r
+1821: }\r
+1822: else\r
+1823: {\r
+1824: ( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r
+BFD02A74 0020FC5E LW V0, 32(S8)
+BFD02A78 69A3 LW V1, 12(V0)
+BFD02A7A 0020FC5E LW V0, 32(S8)
+BFD02A7E 0040FC42 LW V0, 64(V0)
+BFD02A82 0C83 MOVE A0, V1
+BFD02A84 0024FCBE LW A1, 36(S8)
+BFD02A88 0CC2 MOVE A2, V0
+BFD02A8A 1BB477E8 JALS 0xBFD03768
+BFD02A8C 0C001BB4 SB SP, 3072(S4)
+BFD02A8E 0C00 NOP
+1825: pxQueue->u.pcReadFrom -= pxQueue->uxItemSize;\r
+BFD02A90 0020FC5E LW V0, 32(S8)
+BFD02A94 69A3 LW V1, 12(V0)
+BFD02A96 0020FC5E LW V0, 32(S8)
+BFD02A9A 0040FC42 LW V0, 64(V0)
+BFD02A9C 00400040 SRL V0, ZERO, 0
+BFD02A9E 11D00040 SUBU V0, ZERO, V0
+BFD02AA0 05A611D0 ADDI T6, S0, 1446
+BFD02AA2 05A6 ADDU V1, V1, V0
+BFD02AA4 0020FC5E LW V0, 32(S8)
+BFD02AA8 E9A3 SW V1, 12(V0)
+1826: if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */\r
+BFD02AAA 0020FC5E LW V0, 32(S8)
+BFD02AAE 69A3 LW V1, 12(V0)
+BFD02AB0 0020FC5E LW V0, 32(S8)
+BFD02AB4 6920 LW V0, 0(V0)
+BFD02AB6 13900043 SLTU V0, V1, V0
+BFD02AB8 40E21390 ADDI GP, S0, 16610
+BFD02ABA 000D40E2 BEQZC V0, 0xBFD02AD8
+1827: {\r
+1828: pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );\r
+BFD02ABE 0020FC5E LW V0, 32(S8)
+BFD02AC2 69A1 LW V1, 4(V0)
+BFD02AC4 0020FC5E LW V0, 32(S8)
+BFD02AC8 0040FC42 LW V0, 64(V0)
+BFD02ACA 00400040 SRL V0, ZERO, 0
+BFD02ACC 11D00040 SUBU V0, ZERO, V0
+BFD02ACE 05A611D0 ADDI T6, S0, 1446
+BFD02AD0 05A6 ADDU V1, V1, V0
+BFD02AD2 0020FC5E LW V0, 32(S8)
+BFD02AD6 E9A3 SW V1, 12(V0)
+1829: }\r
+1830: else\r
+1831: {\r
+1832: mtCOVERAGE_TEST_MARKER();\r
+1833: }\r
+1834: \r
+1835: if( xPosition == queueOVERWRITE )\r
+BFD02AD8 0028FC7E LW V1, 40(S8)
+BFD02ADC ED02 LI V0, 2
+BFD02ADE 000DB443 BNE V1, V0, 0xBFD02AFC
+BFD02AE0 0C00000D SLL ZERO, T5, 1
+BFD02AE2 0C00 NOP
+1836: {\r
+1837: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r
+BFD02AE4 0020FC5E LW V0, 32(S8)
+BFD02AE8 692E LW V0, 56(V0)
+BFD02AEA 000740E2 BEQZC V0, 0xBFD02AFC
+1838: {\r
+1839: /* An item is not being added but overwritten, so subtract\r
+1840: one from the recorded number of items in the queue so when\r
+1841: one is added again below the number of recorded items remains\r
+1842: correct. */\r
+1843: --( pxQueue->uxMessagesWaiting );\r
+BFD02AEE 0020FC5E LW V0, 32(S8)
+BFD02AF2 692E LW V0, 56(V0)
+BFD02AF4 6DAE ADDIU V1, V0, -1
+BFD02AF6 0020FC5E LW V0, 32(S8)
+BFD02AFA E9AE SW V1, 56(V0)
+1844: }\r
+1845: else\r
+1846: {\r
+1847: mtCOVERAGE_TEST_MARKER();\r
+1848: }\r
+1849: }\r
+1850: else\r
+1851: {\r
+1852: mtCOVERAGE_TEST_MARKER();\r
+1853: }\r
+1854: }\r
+1855: \r
+1856: ++( pxQueue->uxMessagesWaiting );\r
+BFD02AFC 0020FC5E LW V0, 32(S8)
+BFD02B00 692E LW V0, 56(V0)
+BFD02B02 6DA0 ADDIU V1, V0, 1
+BFD02B04 0020FC5E LW V0, 32(S8)
+BFD02B08 E9AE SW V1, 56(V0)
+1857: \r
+1858: return xReturn;\r
+BFD02B0A 0010FC5E LW V0, 16(S8)
+1859: }\r
+BFD02B0E 0FBE MOVE SP, S8
+BFD02B10 4BE7 LW RA, 28(SP)
+BFD02B12 4BC6 LW S8, 24(SP)
+BFD02B14 4C11 ADDIU SP, SP, 32
+BFD02B16 459F JR16 RA
+BFD02B18 0C00 NOP
+1860: /*-----------------------------------------------------------*/\r
+1861: \r
+1862: static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )\r
+1863: {\r
+BFD06CF4 4FF5 ADDIU SP, SP, -24
+BFD06CF6 CBE5 SW RA, 20(SP)
+BFD06CF8 CBC4 SW S8, 16(SP)
+BFD06CFA 0FDD MOVE S8, SP
+BFD06CFC 0018F89E SW A0, 24(S8)
+BFD06D00 001CF8BE SW A1, 28(S8)
+1864: if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )\r
+BFD06D04 0018FC5E LW V0, 24(S8)
+BFD06D08 0040FC42 LW V0, 64(V0)
+BFD06D0C 002940E2 BEQZC V0, 0xBFD06D62
+1865: {\r
+1866: pxQueue->u.pcReadFrom += pxQueue->uxItemSize;\r
+BFD06D10 0018FC5E LW V0, 24(S8)
+BFD06D14 69A3 LW V1, 12(V0)
+BFD06D16 0018FC5E LW V0, 24(S8)
+BFD06D1A 0040FC42 LW V0, 64(V0)
+BFD06D1E 05A6 ADDU V1, V1, V0
+BFD06D20 0018FC5E LW V0, 24(S8)
+BFD06D24 E9A3 SW V1, 12(V0)
+1867: if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */\r
+BFD06D26 0018FC5E LW V0, 24(S8)
+BFD06D2A 69A3 LW V1, 12(V0)
+BFD06D2C 0018FC5E LW V0, 24(S8)
+BFD06D30 6921 LW V0, 4(V0)
+BFD06D32 13900043 SLTU V0, V1, V0
+BFD06D34 40A21390 ADDI GP, S0, 16546
+BFD06D36 000640A2 BNEZC V0, 0xBFD06D46
+1868: {\r
+1869: pxQueue->u.pcReadFrom = pxQueue->pcHead;\r
+BFD06D3A 0018FC5E LW V0, 24(S8)
+BFD06D3E 69A0 LW V1, 0(V0)
+BFD06D40 0018FC5E LW V0, 24(S8)
+BFD06D44 E9A3 SW V1, 12(V0)
+1870: }\r
+1871: else\r
+1872: {\r
+1873: mtCOVERAGE_TEST_MARKER();\r
+1874: }\r
+1875: ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */\r
+BFD06D46 0018FC5E LW V0, 24(S8)
+BFD06D4A 69A3 LW V1, 12(V0)
+BFD06D4C 0018FC5E LW V0, 24(S8)
+BFD06D50 0040FC42 LW V0, 64(V0)
+BFD06D54 001CFC9E LW A0, 28(S8)
+BFD06D58 0CA3 MOVE A1, V1
+BFD06D5A 0CC2 MOVE A2, V0
+BFD06D5C 1BB477E8 JALS 0xBFD03768
+BFD06D5E 0C001BB4 SB SP, 3072(S4)
+BFD06D60 0C00 NOP
+1876: }\r
+1877: }\r
+BFD06D62 0FBE MOVE SP, S8
+BFD06D64 4BE5 LW RA, 20(SP)
+BFD06D66 4BC4 LW S8, 16(SP)
+BFD06D68 4C0D ADDIU SP, SP, 24
+BFD06D6A 459F JR16 RA
+BFD06D6C 0C00 NOP
+1878: /*-----------------------------------------------------------*/\r
+1879: \r
+1880: static void prvUnlockQueue( Queue_t * const pxQueue )\r
+1881: {\r
+BFD03BDC 4FF5 ADDIU SP, SP, -24
+BFD03BDE CBE5 SW RA, 20(SP)
+BFD03BE0 CBC4 SW S8, 16(SP)
+BFD03BE2 0FDD MOVE S8, SP
+BFD03BE4 0018F89E SW A0, 24(S8)
+1882: /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */\r
+1883: \r
+1884: /* The lock counts contains the number of extra data items placed or\r
+1885: removed from the queue while the queue was locked. When a queue is\r
+1886: locked items can be added or removed, but the event lists cannot be\r
+1887: updated. */\r
+1888: taskENTER_CRITICAL();\r
+BFD03BE8 33B877E8 JALS vTaskEnterCritical
+BFD03BEA 0C0033B8 ADDIU SP, T8, 3072
+BFD03BEC 0C00 NOP
+1889: {\r
+1890: /* See if data was added to the queue while it was locked. */\r
+1891: while( pxQueue->xTxLock > queueLOCKED_UNMODIFIED )\r
+BFD03BEE CC32 B 0xBFD03C54
+BFD03BF0 0C00 NOP
+BFD03C54 0018FC5E LW V0, 24(S8)
+BFD03C58 0048FC42 LW V0, 72(V0)
+BFD03C5C FFC940C2 BGTZ V0, 0xBFD03BF2
+BFD03C5E 0C00FFC9 LW S8, 3072(T1)
+BFD03C60 0C00 NOP
+BFD03C62 CC02 B 0xBFD03C68
+BFD03C64 0C00 NOP
+1892: {\r
+1893: /* Data was posted while the queue was locked. Are any tasks\r
+1894: blocked waiting for data to become available? */\r
+1895: #if ( configUSE_QUEUE_SETS == 1 )\r
+1896: {\r
+1897: if( pxQueue->pxQueueSetContainer != NULL )\r
+BFD03BF2 0018FC5E LW V0, 24(S8)
+BFD03BF6 004CFC42 LW V0, 76(V0)
+BFD03BFA 001040E2 BEQZC V0, 0xBFD03C1E
+1898: {\r
+1899: if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )\r
+BFD03BFE 0018FC9E LW A0, 24(S8)
+BFD03C02 0CA0 MOVE A1, ZERO
+BFD03C04 21D877E8 JALS prvNotifyQueueSetContainer
+BFD03C06 0C0021D8 LWC2 T6, 3072(T8)
+BFD03C08 0C00 NOP
+BFD03C0A 0C62 MOVE V1, V0
+BFD03C0C ED01 LI V0, 1
+BFD03C0E 0018B443 BNE V1, V0, 0xBFD03C42
+BFD03C10 0C000018 SLL ZERO, T8, 1
+BFD03C12 0C00 NOP
+1900: {\r
+1901: /* The queue is a member of a queue set, and posting to\r
+1902: the queue set caused a higher priority task to unblock.\r
+1903: A context switch is required. */\r
+1904: vTaskMissedYield();\r
+BFD03C14 4F2A77E8 JALS vTaskMissedYield
+BFD03C16 4F2A ADDIU T9, T9, 5
+BFD03C18 0C00 NOP
+BFD03C1A CC13 B 0xBFD03C42
+BFD03C1C 0C00 NOP
+1905: }\r
+1906: else\r
+1907: {\r
+1908: mtCOVERAGE_TEST_MARKER();\r
+1909: }\r
+1910: }\r
+1911: else\r
+1912: {\r
+1913: /* Tasks that are removed from the event list will get added to\r
+1914: the pending ready list as the scheduler is still suspended. */\r
+1915: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+BFD03C1E 0018FC5E LW V0, 24(S8)
+BFD03C22 6929 LW V0, 36(V0)
+BFD03C24 001F40E2 BEQZC V0, 0xBFD03C66
+1916: {\r
+1917: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+BFD03C28 0018FC5E LW V0, 24(S8)
+BFD03C2C 00243042 ADDIU V0, V0, 36
+BFD03C30 0C82 MOVE A0, V0
+BFD03C32 22BC77E8 JALS xTaskRemoveFromEventList
+BFD03C34 0C0022BC LWC2 S5, 3072(GP)
+BFD03C36 0C00 NOP
+BFD03C38 000340E2 BEQZC V0, 0xBFD03C42
+1918: {\r
+1919: /* The task waiting has a higher priority so record that a\r
+1920: context switch is required. */\r
+1921: vTaskMissedYield();\r
+BFD03C3C 4F2A77E8 JALS vTaskMissedYield
+BFD03C3E 4F2A ADDIU T9, T9, 5
+BFD03C40 0C00 NOP
+1922: }\r
+1923: else\r
+1924: {\r
+1925: mtCOVERAGE_TEST_MARKER();\r
+1926: }\r
+1927: }\r
+1928: else\r
+1929: {\r
+1930: break;\r
+BFD03C66 0C00 NOP
+1931: }\r
+1932: }\r
+1933: }\r
+1934: #else /* configUSE_QUEUE_SETS */\r
+1935: {\r
+1936: /* Tasks that are removed from the event list will get added to\r
+1937: the pending ready list as the scheduler is still suspended. */\r
+1938: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+1939: {\r
+1940: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+1941: {\r
+1942: /* The task waiting has a higher priority so record that a\r
+1943: context switch is required. */\r
+1944: vTaskMissedYield();\r
+1945: }\r
+1946: else\r
+1947: {\r
+1948: mtCOVERAGE_TEST_MARKER();\r
+1949: }\r
+1950: }\r
+1951: else\r
+1952: {\r
+1953: break;\r
+1954: }\r
+1955: }\r
+1956: #endif /* configUSE_QUEUE_SETS */\r
+1957: \r
+1958: --( pxQueue->xTxLock );\r
+BFD03C42 0018FC5E LW V0, 24(S8)
+BFD03C46 0048FC42 LW V0, 72(V0)
+BFD03C4A 6DAE ADDIU V1, V0, -1
+BFD03C4C 0018FC5E LW V0, 24(S8)
+BFD03C50 0048F862 SW V1, 72(V0)
+1959: }\r
+1960: \r
+1961: pxQueue->xTxLock = queueUNLOCKED;\r
+BFD03C68 0018FC5E LW V0, 24(S8)
+BFD03C6C EDFF LI V1, -1
+BFD03C6E 0048F862 SW V1, 72(V0)
+1962: }\r
+1963: taskEXIT_CRITICAL();\r
+BFD03C72 40AA77E8 JALS vTaskExitCritical
+BFD03C74 0C0040AA BNEZC T2, 0xBFD05478
+BFD03C76 0C00 NOP
+1964: \r
+1965: /* Do the same for the Rx lock. */\r
+1966: taskENTER_CRITICAL();\r
+BFD03C78 33B877E8 JALS vTaskEnterCritical
+BFD03C7A 0C0033B8 ADDIU SP, T8, 3072
+BFD03C7C 0C00 NOP
+1967: {\r
+1968: while( pxQueue->xRxLock > queueLOCKED_UNMODIFIED )\r
+BFD03C7E CC1B B 0xBFD03CB6
+BFD03C80 0C00 NOP
+BFD03CB6 0018FC5E LW V0, 24(S8)
+BFD03CBA 0044FC42 LW V0, 68(V0)
+BFD03CBE FFE040C2 BGTZ V0, 0xBFD03C82
+BFD03CC0 0C00FFE0 LW RA, 3072(ZERO)
+BFD03CC2 0C00 NOP
+BFD03CC4 CC02 B 0xBFD03CCA
+BFD03CC6 0C00 NOP
+1969: {\r
+1970: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+BFD03C82 0018FC5E LW V0, 24(S8)
+BFD03C86 6924 LW V0, 16(V0)
+BFD03C88 001E40E2 BEQZC V0, 0xBFD03CC8
+1971: {\r
+1972: if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+BFD03C8C 0018FC5E LW V0, 24(S8)
+BFD03C90 6D28 ADDIU V0, V0, 16
+BFD03C92 0C82 MOVE A0, V0
+BFD03C94 22BC77E8 JALS xTaskRemoveFromEventList
+BFD03C96 0C0022BC LWC2 S5, 3072(GP)
+BFD03C98 0C00 NOP
+BFD03C9A 000340E2 BEQZC V0, 0xBFD03CA4
+1973: {\r
+1974: vTaskMissedYield();\r
+BFD03C9E 4F2A77E8 JALS vTaskMissedYield
+BFD03CA0 4F2A ADDIU T9, T9, 5
+BFD03CA2 0C00 NOP
+1975: }\r
+1976: else\r
+1977: {\r
+1978: mtCOVERAGE_TEST_MARKER();\r
+1979: }\r
+1980: \r
+1981: --( pxQueue->xRxLock );\r
+BFD03CA4 0018FC5E LW V0, 24(S8)
+BFD03CA8 0044FC42 LW V0, 68(V0)
+BFD03CAC 6DAE ADDIU V1, V0, -1
+BFD03CAE 0018FC5E LW V0, 24(S8)
+BFD03CB2 0044F862 SW V1, 68(V0)
+1982: }\r
+1983: else\r
+1984: {\r
+1985: break;\r
+BFD03CC8 0C00 NOP
+1986: }\r
+1987: }\r
+1988: \r
+1989: pxQueue->xRxLock = queueUNLOCKED;\r
+BFD03CCA 0018FC5E LW V0, 24(S8)
+BFD03CCE EDFF LI V1, -1
+BFD03CD0 0044F862 SW V1, 68(V0)
+1990: }\r
+1991: taskEXIT_CRITICAL();\r
+BFD03CD4 40AA77E8 JALS vTaskExitCritical
+BFD03CD6 0C0040AA BNEZC T2, 0xBFD054DA
+BFD03CD8 0C00 NOP
+1992: }\r
+BFD03CDA 0FBE MOVE SP, S8
+BFD03CDC 4BE5 LW RA, 20(SP)
+BFD03CDE 4BC4 LW S8, 16(SP)
+BFD03CE0 4C0D ADDIU SP, SP, 24
+BFD03CE2 459F JR16 RA
+BFD03CE4 0C00 NOP
+1993: /*-----------------------------------------------------------*/\r
+1994: \r
+1995: static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )\r
+1996: {\r
+BFD093A0 4FF1 ADDIU SP, SP, -32
+BFD093A2 CBE7 SW RA, 28(SP)
+BFD093A4 CBC6 SW S8, 24(SP)
+BFD093A6 0FDD MOVE S8, SP
+BFD093A8 0020F89E SW A0, 32(S8)
+1997: BaseType_t xReturn;\r
+1998: \r
+1999: taskENTER_CRITICAL();\r
+BFD093AC 33B877E8 JALS vTaskEnterCritical
+BFD093AE 0C0033B8 ADDIU SP, T8, 3072
+BFD093B0 0C00 NOP
+2000: {\r
+2001: if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )\r
+BFD093B2 0020FC5E LW V0, 32(S8)
+BFD093B6 692E LW V0, 56(V0)
+BFD093B8 000540A2 BNEZC V0, 0xBFD093C6
+2002: {\r
+2003: xReturn = pdTRUE;\r
+BFD093BC ED01 LI V0, 1
+BFD093BE 0010F85E SW V0, 16(S8)
+BFD093C2 CC03 B 0xBFD093CA
+BFD093C4 0C00 NOP
+2004: }\r
+2005: else\r
+2006: {\r
+2007: xReturn = pdFALSE;\r
+BFD093C6 0010F81E SW ZERO, 16(S8)
+2008: }\r
+2009: }\r
+2010: taskEXIT_CRITICAL();\r
+BFD093CA 40AA77E8 JALS vTaskExitCritical
+BFD093CC 0C0040AA BNEZC T2, 0xBFD0ABD0
+BFD093CE 0C00 NOP
+2011: \r
+2012: return xReturn;\r
+BFD093D0 0010FC5E LW V0, 16(S8)
+2013: }\r
+BFD093D4 0FBE MOVE SP, S8
+BFD093D6 4BE7 LW RA, 28(SP)
+BFD093D8 4BC6 LW S8, 24(SP)
+BFD093DA 4C11 ADDIU SP, SP, 32
+BFD093DC 459F JR16 RA
+BFD093DE 0C00 NOP
+2014: /*-----------------------------------------------------------*/\r
+2015: \r
+2016: BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )\r
+2017: {\r
+BFD08954 4FF1 ADDIU SP, SP, -32
+BFD08956 CBE7 SW RA, 28(SP)
+BFD08958 CBC6 SW S8, 24(SP)
+BFD0895A 0FDD MOVE S8, SP
+BFD0895C 0020F89E SW A0, 32(S8)
+2018: BaseType_t xReturn;\r
+2019: \r
+2020: configASSERT( xQueue );\r
+BFD08960 0020FC5E LW V0, 32(S8)
+BFD08964 000940A2 BNEZC V0, 0xBFD0897A
+BFD08968 BFD141A2 LUI V0, 0xBFD1
+BFD0896A 3082BFD1 LDC1 F30, 12418(S1)
+BFD0896C 9E3C3082 ADDIU A0, V0, -25028
+BFD0896E 30A09E3C LWC1 F17, 12448(GP)
+BFD08970 07E430A0 ADDIU A1, ZERO, 2020
+BFD08972 07E4 ADDU A3, V0, A2
+BFD08974 4B7E77E8 JALS vAssertCalled
+BFD08976 4B7E LW K1, 120(SP)
+BFD08978 0C00 NOP
+2021: if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 )\r
+BFD0897A 0020FC5E LW V0, 32(S8)
+BFD0897E 692E LW V0, 56(V0)
+BFD08980 000540A2 BNEZC V0, 0xBFD0898E
+2022: {\r
+2023: xReturn = pdTRUE;\r
+BFD08984 ED01 LI V0, 1
+BFD08986 0010F85E SW V0, 16(S8)
+BFD0898A CC03 B 0xBFD08992
+BFD0898C 0C00 NOP
+2024: }\r
+2025: else\r
+2026: {\r
+2027: xReturn = pdFALSE;\r
+BFD0898E 0010F81E SW ZERO, 16(S8)
+2028: }\r
+2029: \r
+2030: return xReturn;\r
+BFD08992 0010FC5E LW V0, 16(S8)
+2031: } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\r
+BFD08996 0FBE MOVE SP, S8
+BFD08998 4BE7 LW RA, 28(SP)
+BFD0899A 4BC6 LW S8, 24(SP)
+BFD0899C 4C11 ADDIU SP, SP, 32
+BFD0899E 459F JR16 RA
+BFD089A0 0C00 NOP
+2032: /*-----------------------------------------------------------*/\r
+2033: \r
+2034: static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )\r
+2035: {\r
+BFD08F04 4FF1 ADDIU SP, SP, -32
+BFD08F06 CBE7 SW RA, 28(SP)
+BFD08F08 CBC6 SW S8, 24(SP)
+BFD08F0A 0FDD MOVE S8, SP
+BFD08F0C 0020F89E SW A0, 32(S8)
+2036: BaseType_t xReturn;\r
+2037: \r
+2038: taskENTER_CRITICAL();\r
+BFD08F10 33B877E8 JALS vTaskEnterCritical
+BFD08F12 0C0033B8 ADDIU SP, T8, 3072
+BFD08F14 0C00 NOP
+2039: {\r
+2040: if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )\r
+BFD08F16 0020FC5E LW V0, 32(S8)
+BFD08F1A 69AE LW V1, 56(V0)
+BFD08F1C 0020FC5E LW V0, 32(S8)
+BFD08F20 692F LW V0, 60(V0)
+BFD08F22 0006B443 BNE V1, V0, 0xBFD08F32
+BFD08F24 0C000006 SLL ZERO, A2, 1
+BFD08F26 0C00 NOP
+2041: {\r
+2042: xReturn = pdTRUE;\r
+BFD08F28 ED01 LI V0, 1
+BFD08F2A 0010F85E SW V0, 16(S8)
+BFD08F2E CC03 B 0xBFD08F36
+BFD08F30 0C00 NOP
+2043: }\r
+2044: else\r
+2045: {\r
+2046: xReturn = pdFALSE;\r
+BFD08F32 0010F81E SW ZERO, 16(S8)
+2047: }\r
+2048: }\r
+2049: taskEXIT_CRITICAL();\r
+BFD08F36 40AA77E8 JALS vTaskExitCritical
+BFD08F38 0C0040AA BNEZC T2, 0xBFD0A73C
+BFD08F3A 0C00 NOP
+2050: \r
+2051: return xReturn;\r
+BFD08F3C 0010FC5E LW V0, 16(S8)
+2052: }\r
+BFD08F40 0FBE MOVE SP, S8
+BFD08F42 4BE7 LW RA, 28(SP)
+BFD08F44 4BC6 LW S8, 24(SP)
+BFD08F46 4C11 ADDIU SP, SP, 32
+BFD08F48 459F JR16 RA
+BFD08F4A 0C00 NOP
+2053: /*-----------------------------------------------------------*/\r
+2054: \r
+2055: BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )\r
+2056: {\r
+BFD084F8 4FF1 ADDIU SP, SP, -32
+BFD084FA CBE7 SW RA, 28(SP)
+BFD084FC CBC6 SW S8, 24(SP)
+BFD084FE 0FDD MOVE S8, SP
+BFD08500 0020F89E SW A0, 32(S8)
+2057: BaseType_t xReturn;\r
+2058: \r
+2059: configASSERT( xQueue );\r
+BFD08504 0020FC5E LW V0, 32(S8)
+BFD08508 000940A2 BNEZC V0, 0xBFD0851E
+BFD0850C BFD141A2 LUI V0, 0xBFD1
+BFD0850E 3082BFD1 LDC1 F30, 12418(S1)
+BFD08510 9E3C3082 ADDIU A0, V0, -25028
+BFD08512 30A09E3C LWC1 F17, 12448(GP)
+BFD08514 080B30A0 ADDIU A1, ZERO, 2059
+BFD08516 080B LBU S0, 11(S0)
+BFD08518 4B7E77E8 JALS vAssertCalled
+BFD0851A 4B7E LW K1, 120(SP)
+BFD0851C 0C00 NOP
+2060: if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength )\r
+BFD0851E 0020FC5E LW V0, 32(S8)
+BFD08522 69AE LW V1, 56(V0)
+BFD08524 0020FC5E LW V0, 32(S8)
+BFD08528 692F LW V0, 60(V0)
+BFD0852A 0006B443 BNE V1, V0, 0xBFD0853A
+BFD0852C 0C000006 SLL ZERO, A2, 1
+BFD0852E 0C00 NOP
+2061: {\r
+2062: xReturn = pdTRUE;\r
+BFD08530 ED01 LI V0, 1
+BFD08532 0010F85E SW V0, 16(S8)
+BFD08536 CC03 B 0xBFD0853E
+BFD08538 0C00 NOP
+2063: }\r
+2064: else\r
+2065: {\r
+2066: xReturn = pdFALSE;\r
+BFD0853A 0010F81E SW ZERO, 16(S8)
+2067: }\r
+2068: \r
+2069: return xReturn;\r
+BFD0853E 0010FC5E LW V0, 16(S8)
+2070: } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\r
+BFD08542 0FBE MOVE SP, S8
+BFD08544 4BE7 LW RA, 28(SP)
+BFD08546 4BC6 LW S8, 24(SP)
+BFD08548 4C11 ADDIU SP, SP, 32
+BFD0854A 459F JR16 RA
+BFD0854C 0C00 NOP
+2071: /*-----------------------------------------------------------*/\r
+2072: \r
+2073: #if ( configUSE_CO_ROUTINES == 1 )\r
+2074: \r
+2075: BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )\r
+2076: {\r
+2077: BaseType_t xReturn;\r
+2078: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+2079: \r
+2080: /* If the queue is already full we may have to block. A critical section\r
+2081: is required to prevent an interrupt removing something from the queue\r
+2082: between the check to see if the queue is full and blocking on the queue. */\r
+2083: portDISABLE_INTERRUPTS();\r
+2084: {\r
+2085: if( prvIsQueueFull( pxQueue ) != pdFALSE )\r
+2086: {\r
+2087: /* The queue is full - do we want to block or just leave without\r
+2088: posting? */\r
+2089: if( xTicksToWait > ( TickType_t ) 0 )\r
+2090: {\r
+2091: /* As this is called from a coroutine we cannot block directly, but\r
+2092: return indicating that we need to block. */\r
+2093: vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );\r
+2094: portENABLE_INTERRUPTS();\r
+2095: return errQUEUE_BLOCKED;\r
+2096: }\r
+2097: else\r
+2098: {\r
+2099: portENABLE_INTERRUPTS();\r
+2100: return errQUEUE_FULL;\r
+2101: }\r
+2102: }\r
+2103: }\r
+2104: portENABLE_INTERRUPTS();\r
+2105: \r
+2106: portDISABLE_INTERRUPTS();\r
+2107: {\r
+2108: if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+2109: {\r
+2110: /* There is room in the queue, copy the data into the queue. */\r
+2111: prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\r
+2112: xReturn = pdPASS;\r
+2113: \r
+2114: /* Were any co-routines waiting for data to become available? */\r
+2115: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+2116: {\r
+2117: /* In this instance the co-routine could be placed directly\r
+2118: into the ready list as we are within a critical section.\r
+2119: Instead the same pending ready list mechanism is used as if\r
+2120: the event were caused from within an interrupt. */\r
+2121: if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+2122: {\r
+2123: /* The co-routine waiting has a higher priority so record\r
+2124: that a yield might be appropriate. */\r
+2125: xReturn = errQUEUE_YIELD;\r
+2126: }\r
+2127: else\r
+2128: {\r
+2129: mtCOVERAGE_TEST_MARKER();\r
+2130: }\r
+2131: }\r
+2132: else\r
+2133: {\r
+2134: mtCOVERAGE_TEST_MARKER();\r
+2135: }\r
+2136: }\r
+2137: else\r
+2138: {\r
+2139: xReturn = errQUEUE_FULL;\r
+2140: }\r
+2141: }\r
+2142: portENABLE_INTERRUPTS();\r
+2143: \r
+2144: return xReturn;\r
+2145: }\r
+2146: \r
+2147: #endif /* configUSE_CO_ROUTINES */\r
+2148: /*-----------------------------------------------------------*/\r
+2149: \r
+2150: #if ( configUSE_CO_ROUTINES == 1 )\r
+2151: \r
+2152: BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )\r
+2153: {\r
+2154: BaseType_t xReturn;\r
+2155: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+2156: \r
+2157: /* If the queue is already empty we may have to block. A critical section\r
+2158: is required to prevent an interrupt adding something to the queue\r
+2159: between the check to see if the queue is empty and blocking on the queue. */\r
+2160: portDISABLE_INTERRUPTS();\r
+2161: {\r
+2162: if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )\r
+2163: {\r
+2164: /* There are no messages in the queue, do we want to block or just\r
+2165: leave with nothing? */\r
+2166: if( xTicksToWait > ( TickType_t ) 0 )\r
+2167: {\r
+2168: /* As this is a co-routine we cannot block directly, but return\r
+2169: indicating that we need to block. */\r
+2170: vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );\r
+2171: portENABLE_INTERRUPTS();\r
+2172: return errQUEUE_BLOCKED;\r
+2173: }\r
+2174: else\r
+2175: {\r
+2176: portENABLE_INTERRUPTS();\r
+2177: return errQUEUE_FULL;\r
+2178: }\r
+2179: }\r
+2180: else\r
+2181: {\r
+2182: mtCOVERAGE_TEST_MARKER();\r
+2183: }\r
+2184: }\r
+2185: portENABLE_INTERRUPTS();\r
+2186: \r
+2187: portDISABLE_INTERRUPTS();\r
+2188: {\r
+2189: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r
+2190: {\r
+2191: /* Data is available from the queue. */\r
+2192: pxQueue->u.pcReadFrom += pxQueue->uxItemSize;\r
+2193: if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )\r
+2194: {\r
+2195: pxQueue->u.pcReadFrom = pxQueue->pcHead;\r
+2196: }\r
+2197: else\r
+2198: {\r
+2199: mtCOVERAGE_TEST_MARKER();\r
+2200: }\r
+2201: --( pxQueue->uxMessagesWaiting );\r
+2202: ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r
+2203: \r
+2204: xReturn = pdPASS;\r
+2205: \r
+2206: /* Were any co-routines waiting for space to become available? */\r
+2207: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+2208: {\r
+2209: /* In this instance the co-routine could be placed directly\r
+2210: into the ready list as we are within a critical section.\r
+2211: Instead the same pending ready list mechanism is used as if\r
+2212: the event were caused from within an interrupt. */\r
+2213: if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+2214: {\r
+2215: xReturn = errQUEUE_YIELD;\r
+2216: }\r
+2217: else\r
+2218: {\r
+2219: mtCOVERAGE_TEST_MARKER();\r
+2220: }\r
+2221: }\r
+2222: else\r
+2223: {\r
+2224: mtCOVERAGE_TEST_MARKER();\r
+2225: }\r
+2226: }\r
+2227: else\r
+2228: {\r
+2229: xReturn = pdFAIL;\r
+2230: }\r
+2231: }\r
+2232: portENABLE_INTERRUPTS();\r
+2233: \r
+2234: return xReturn;\r
+2235: }\r
+2236: \r
+2237: #endif /* configUSE_CO_ROUTINES */\r
+2238: /*-----------------------------------------------------------*/\r
+2239: \r
+2240: #if ( configUSE_CO_ROUTINES == 1 )\r
+2241: \r
+2242: BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )\r
+2243: {\r
+2244: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+2245: \r
+2246: /* Cannot block within an ISR so if there is no space on the queue then\r
+2247: exit without doing anything. */\r
+2248: if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+2249: {\r
+2250: prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\r
+2251: \r
+2252: /* We only want to wake one co-routine per ISR, so check that a\r
+2253: co-routine has not already been woken. */\r
+2254: if( xCoRoutinePreviouslyWoken == pdFALSE )\r
+2255: {\r
+2256: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+2257: {\r
+2258: if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+2259: {\r
+2260: return pdTRUE;\r
+2261: }\r
+2262: else\r
+2263: {\r
+2264: mtCOVERAGE_TEST_MARKER();\r
+2265: }\r
+2266: }\r
+2267: else\r
+2268: {\r
+2269: mtCOVERAGE_TEST_MARKER();\r
+2270: }\r
+2271: }\r
+2272: else\r
+2273: {\r
+2274: mtCOVERAGE_TEST_MARKER();\r
+2275: }\r
+2276: }\r
+2277: else\r
+2278: {\r
+2279: mtCOVERAGE_TEST_MARKER();\r
+2280: }\r
+2281: \r
+2282: return xCoRoutinePreviouslyWoken;\r
+2283: }\r
+2284: \r
+2285: #endif /* configUSE_CO_ROUTINES */\r
+2286: /*-----------------------------------------------------------*/\r
+2287: \r
+2288: #if ( configUSE_CO_ROUTINES == 1 )\r
+2289: \r
+2290: BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )\r
+2291: {\r
+2292: BaseType_t xReturn;\r
+2293: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+2294: \r
+2295: /* We cannot block from an ISR, so check there is data available. If\r
+2296: not then just leave without doing anything. */\r
+2297: if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r
+2298: {\r
+2299: /* Copy the data from the queue. */\r
+2300: pxQueue->u.pcReadFrom += pxQueue->uxItemSize;\r
+2301: if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )\r
+2302: {\r
+2303: pxQueue->u.pcReadFrom = pxQueue->pcHead;\r
+2304: }\r
+2305: else\r
+2306: {\r
+2307: mtCOVERAGE_TEST_MARKER();\r
+2308: }\r
+2309: --( pxQueue->uxMessagesWaiting );\r
+2310: ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r
+2311: \r
+2312: if( ( *pxCoRoutineWoken ) == pdFALSE )\r
+2313: {\r
+2314: if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+2315: {\r
+2316: if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+2317: {\r
+2318: *pxCoRoutineWoken = pdTRUE;\r
+2319: }\r
+2320: else\r
+2321: {\r
+2322: mtCOVERAGE_TEST_MARKER();\r
+2323: }\r
+2324: }\r
+2325: else\r
+2326: {\r
+2327: mtCOVERAGE_TEST_MARKER();\r
+2328: }\r
+2329: }\r
+2330: else\r
+2331: {\r
+2332: mtCOVERAGE_TEST_MARKER();\r
+2333: }\r
+2334: \r
+2335: xReturn = pdPASS;\r
+2336: }\r
+2337: else\r
+2338: {\r
+2339: xReturn = pdFAIL;\r
+2340: }\r
+2341: \r
+2342: return xReturn;\r
+2343: }\r
+2344: \r
+2345: #endif /* configUSE_CO_ROUTINES */\r
+2346: /*-----------------------------------------------------------*/\r
+2347: \r
+2348: #if ( configQUEUE_REGISTRY_SIZE > 0 )\r
+2349: \r
+2350: void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r
+2351: {\r
+2352: UBaseType_t ux;\r
+2353: \r
+2354: /* See if there is an empty space in the registry. A NULL name denotes\r
+2355: a free slot. */\r
+2356: for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\r
+2357: {\r
+2358: if( xQueueRegistry[ ux ].pcQueueName == NULL )\r
+2359: {\r
+2360: /* Store the information on this queue. */\r
+2361: xQueueRegistry[ ux ].pcQueueName = pcQueueName;\r
+2362: xQueueRegistry[ ux ].xHandle = xQueue;\r
+2363: \r
+2364: traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );\r
+2365: break;\r
+2366: }\r
+2367: else\r
+2368: {\r
+2369: mtCOVERAGE_TEST_MARKER();\r
+2370: }\r
+2371: }\r
+2372: }\r
+2373: \r
+2374: #endif /* configQUEUE_REGISTRY_SIZE */\r
+2375: /*-----------------------------------------------------------*/\r
+2376: \r
+2377: #if ( configQUEUE_REGISTRY_SIZE > 0 )\r
+2378: \r
+2379: void vQueueUnregisterQueue( QueueHandle_t xQueue )\r
+2380: {\r
+2381: UBaseType_t ux;\r
+2382: \r
+2383: /* See if the handle of the queue being unregistered in actually in the\r
+2384: registry. */\r
+2385: for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\r
+2386: {\r
+2387: if( xQueueRegistry[ ux ].xHandle == xQueue )\r
+2388: {\r
+2389: /* Set the name to NULL to show that this slot if free again. */\r
+2390: xQueueRegistry[ ux ].pcQueueName = NULL;\r
+2391: break;\r
+2392: }\r
+2393: else\r
+2394: {\r
+2395: mtCOVERAGE_TEST_MARKER();\r
+2396: }\r
+2397: }\r
+2398: \r
+2399: } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\r
+2400: \r
+2401: #endif /* configQUEUE_REGISTRY_SIZE */\r
+2402: /*-----------------------------------------------------------*/\r
+2403: \r
+2404: #if ( configUSE_TIMERS == 1 )\r
+2405: \r
+2406: void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )\r
+2407: {\r
+BFD06928 4FF1 ADDIU SP, SP, -32
+BFD0692A CBE7 SW RA, 28(SP)
+BFD0692C CBC6 SW S8, 24(SP)
+BFD0692E 0FDD MOVE S8, SP
+BFD06930 0020F89E SW A0, 32(S8)
+BFD06934 0024F8BE SW A1, 36(S8)
+BFD06938 0028F8DE SW A2, 40(S8)
+2408: Queue_t * const pxQueue = ( Queue_t * ) xQueue;\r
+BFD0693C 0020FC5E LW V0, 32(S8)
+BFD06940 0010F85E SW V0, 16(S8)
+2409: \r
+2410: /* This function should not be called by application code hence the\r
+2411: 'Restricted' in its name. It is not part of the public API. It is\r
+2412: designed for use by kernel code, and has special calling requirements.\r
+2413: It can result in vListInsert() being called on a list that can only\r
+2414: possibly ever have one item in it, so the list will be fast, but even\r
+2415: so it should be called with the scheduler locked and not from a critical\r
+2416: section. */\r
+2417: \r
+2418: /* Only do anything if there are no messages in the queue. This function\r
+2419: will not actually cause the task to block, just place it on a blocked\r
+2420: list. It will not block until the scheduler is unlocked - at which\r
+2421: time a yield will be performed. If an item is added to the queue while\r
+2422: the queue is locked, and the calling task blocks on the queue, then the\r
+2423: calling task will be immediately unblocked when the queue is unlocked. */\r
+2424: prvLockQueue( pxQueue );\r
+BFD06944 33B877E8 JALS vTaskEnterCritical
+BFD06946 0C0033B8 ADDIU SP, T8, 3072
+BFD06948 0C00 NOP
+BFD0694A 0010FC5E LW V0, 16(S8)
+BFD0694E 0044FC62 LW V1, 68(V0)
+BFD06952 ED7F LI V0, -1
+BFD06954 0005B443 BNE V1, V0, 0xBFD06962
+BFD06956 0C000005 SLL ZERO, A1, 1
+BFD06958 0C00 NOP
+BFD0695A 0010FC5E LW V0, 16(S8)
+BFD0695E 0044F802 SW ZERO, 68(V0)
+BFD06962 0010FC5E LW V0, 16(S8)
+BFD06966 0048FC62 LW V1, 72(V0)
+BFD0696A ED7F LI V0, -1
+BFD0696C 0005B443 BNE V1, V0, 0xBFD0697A
+BFD0696E 0C000005 SLL ZERO, A1, 1
+BFD06970 0C00 NOP
+BFD06972 0010FC5E LW V0, 16(S8)
+BFD06976 0048F802 SW ZERO, 72(V0)
+BFD0697A 40AA77E8 JALS vTaskExitCritical
+BFD0697C 0C0040AA BNEZC T2, 0xBFD08180
+BFD0697E 0C00 NOP
+2425: if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )\r
+BFD06980 0010FC5E LW V0, 16(S8)
+BFD06984 692E LW V0, 56(V0)
+BFD06986 000C40A2 BNEZC V0, 0xBFD069A2
+2426: {\r
+2427: /* There is nothing in the queue, block for the specified period. */\r
+2428: vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );\r
+BFD0698A 0010FC5E LW V0, 16(S8)
+BFD0698E 00243042 ADDIU V0, V0, 36
+BFD06992 0C82 MOVE A0, V0
+BFD06994 0024FCBE LW A1, 36(S8)
+BFD06998 0028FCDE LW A2, 40(S8)
+BFD0699C 2E2C77E8 JALS vTaskPlaceOnEventListRestricted
+BFD0699E 2E2C ANDI A0, V0, 0x40
+BFD069A0 0C00 NOP
+2429: }\r
+2430: else\r
+2431: {\r
+2432: mtCOVERAGE_TEST_MARKER();\r
+2433: }\r
+2434: prvUnlockQueue( pxQueue );\r
+BFD069A2 0010FC9E LW A0, 16(S8)
+BFD069A6 1DEE77E8 JALS prvUnlockQueue
+BFD069A8 0C001DEE LB T7, 3072(T6)
+BFD069AA 0C00 NOP
+2435: }\r
+BFD069AC 0FBE MOVE SP, S8
+BFD069AE 4BE7 LW RA, 28(SP)
+BFD069B0 4BC6 LW S8, 24(SP)
+BFD069B2 4C11 ADDIU SP, SP, 32
+BFD069B4 459F JR16 RA
+BFD069B6 0C00 NOP
+2436: \r
+2437: #endif /* configUSE_TIMERS */\r
+2438: /*-----------------------------------------------------------*/\r
+2439: \r
+2440: #if ( configUSE_QUEUE_SETS == 1 )\r
+2441: \r
+2442: QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )\r
+2443: {\r
+BFD098AC 4FF1 ADDIU SP, SP, -32
+BFD098AE CBE7 SW RA, 28(SP)
+BFD098B0 CBC6 SW S8, 24(SP)
+BFD098B2 0FDD MOVE S8, SP
+BFD098B4 0020F89E SW A0, 32(S8)
+2444: QueueSetHandle_t pxQueue;\r
+2445: \r
+2446: pxQueue = xQueueGenericCreate( uxEventQueueLength, sizeof( Queue_t * ), queueQUEUE_TYPE_SET );\r
+BFD098B8 0020FC9E LW A0, 32(S8)
+BFD098BC EE84 LI A1, 4
+BFD098BE 0CC0 MOVE A2, ZERO
+BFD098C0 1EFA77E8 JALS xQueueGenericCreate
+BFD098C2 0C001EFA LB S7, 3072(K0)
+BFD098C4 0C00 NOP
+BFD098C6 0010F85E SW V0, 16(S8)
+2447: \r
+2448: return pxQueue;\r
+BFD098CA 0010FC5E LW V0, 16(S8)
+2449: }\r
+BFD098CE 0FBE MOVE SP, S8
+BFD098D0 4BE7 LW RA, 28(SP)
+BFD098D2 4BC6 LW S8, 24(SP)
+BFD098D4 4C11 ADDIU SP, SP, 32
+BFD098D6 459F JR16 RA
+BFD098D8 0C00 NOP
+2450: \r
+2451: #endif /* configUSE_QUEUE_SETS */\r
+2452: /*-----------------------------------------------------------*/\r
+2453: \r
+2454: #if ( configUSE_QUEUE_SETS == 1 )\r
+2455: \r
+2456: BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r
+2457: {\r
+BFD07E9C 4FF1 ADDIU SP, SP, -32
+BFD07E9E CBE7 SW RA, 28(SP)
+BFD07EA0 CBC6 SW S8, 24(SP)
+BFD07EA2 0FDD MOVE S8, SP
+BFD07EA4 0020F89E SW A0, 32(S8)
+BFD07EA8 0024F8BE SW A1, 36(S8)
+2458: BaseType_t xReturn;\r
+2459: \r
+2460: taskENTER_CRITICAL();\r
+BFD07EAC 33B877E8 JALS vTaskEnterCritical
+BFD07EAE 0C0033B8 ADDIU SP, T8, 3072
+BFD07EB0 0C00 NOP
+2461: {\r
+2462: if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )\r
+BFD07EB2 0020FC5E LW V0, 32(S8)
+BFD07EB6 004CFC42 LW V0, 76(V0)
+BFD07EBA 000440E2 BEQZC V0, 0xBFD07EC6
+2463: {\r
+2464: /* Cannot add a queue/semaphore to more than one queue set. */\r
+2465: xReturn = pdFAIL;\r
+BFD07EBE 0010F81E SW ZERO, 16(S8)
+BFD07EC2 CC13 B 0xBFD07EEA
+BFD07EC4 0C00 NOP
+2466: }\r
+2467: else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )\r
+BFD07EC6 0020FC5E LW V0, 32(S8)
+BFD07ECA 692E LW V0, 56(V0)
+BFD07ECC 000440E2 BEQZC V0, 0xBFD07ED8
+2468: {\r
+2469: /* Cannot add a queue/semaphore to a queue set if there are already\r
+2470: items in the queue/semaphore. */\r
+2471: xReturn = pdFAIL;\r
+BFD07ED0 0010F81E SW ZERO, 16(S8)
+BFD07ED4 CC0A B 0xBFD07EEA
+BFD07ED6 0C00 NOP
+2472: }\r
+2473: else\r
+2474: {\r
+2475: ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;\r
+BFD07ED8 0020FC5E LW V0, 32(S8)
+BFD07EDC 0024FC7E LW V1, 36(S8)
+BFD07EE0 004CF862 SW V1, 76(V0)
+2476: xReturn = pdPASS;\r
+BFD07EE4 ED01 LI V0, 1
+BFD07EE6 0010F85E SW V0, 16(S8)
+2477: }\r
+2478: }\r
+2479: taskEXIT_CRITICAL();\r
+BFD07EEA 40AA77E8 JALS vTaskExitCritical
+BFD07EEC 0C0040AA BNEZC T2, 0xBFD096F0
+BFD07EEE 0C00 NOP
+2480: \r
+2481: return xReturn;\r
+BFD07EF0 0010FC5E LW V0, 16(S8)
+2482: }\r
+BFD07EF4 0FBE MOVE SP, S8
+BFD07EF6 4BE7 LW RA, 28(SP)
+BFD07EF8 4BC6 LW S8, 24(SP)
+BFD07EFA 4C11 ADDIU SP, SP, 32
+BFD07EFC 459F JR16 RA
+BFD07EFE 0C00 NOP
+2483: \r
+2484: #endif /* configUSE_QUEUE_SETS */\r
+2485: /*-----------------------------------------------------------*/\r
+2486: \r
+2487: #if ( configUSE_QUEUE_SETS == 1 )\r
+2488: \r
+2489: BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r
+2490: {\r
+BFD079FC 4FF1 ADDIU SP, SP, -32
+BFD079FE CBE7 SW RA, 28(SP)
+BFD07A00 CBC6 SW S8, 24(SP)
+BFD07A02 0FDD MOVE S8, SP
+BFD07A04 0020F89E SW A0, 32(S8)
+BFD07A08 0024F8BE SW A1, 36(S8)
+2491: BaseType_t xReturn;\r
+2492: Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;\r
+BFD07A0C 0020FC5E LW V0, 32(S8)
+BFD07A10 0014F85E SW V0, 20(S8)
+2493: \r
+2494: if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )\r
+BFD07A14 0014FC5E LW V0, 20(S8)
+BFD07A18 004CFC62 LW V1, 76(V0)
+BFD07A1C 0024FC5E LW V0, 36(S8)
+BFD07A20 00059443 BEQ V1, V0, 0xBFD07A2E
+BFD07A22 0C000005 SLL ZERO, A1, 1
+BFD07A24 0C00 NOP
+2495: {\r
+2496: /* The queue was not a member of the set. */\r
+2497: xReturn = pdFAIL;\r
+BFD07A26 0010F81E SW ZERO, 16(S8)
+BFD07A2A CC17 B 0xBFD07A5A
+BFD07A2C 0C00 NOP
+2498: }\r
+2499: else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )\r
+BFD07A2E 0014FC5E LW V0, 20(S8)
+BFD07A32 692E LW V0, 56(V0)
+BFD07A34 000440E2 BEQZC V0, 0xBFD07A40
+2500: {\r
+2501: /* It is dangerous to remove a queue from a set when the queue is\r
+2502: not empty because the queue set will still hold pending events for\r
+2503: the queue. */\r
+2504: xReturn = pdFAIL;\r
+BFD07A38 0010F81E SW ZERO, 16(S8)
+BFD07A3C CC0E B 0xBFD07A5A
+BFD07A3E 0C00 NOP
+2505: }\r
+2506: else\r
+2507: {\r
+2508: taskENTER_CRITICAL();\r
+BFD07A40 33B877E8 JALS vTaskEnterCritical
+BFD07A42 0C0033B8 ADDIU SP, T8, 3072
+BFD07A44 0C00 NOP
+2509: {\r
+2510: /* The queue is no longer contained in the set. */\r
+2511: pxQueueOrSemaphore->pxQueueSetContainer = NULL;\r
+BFD07A46 0014FC5E LW V0, 20(S8)
+BFD07A4A 004CF802 SW ZERO, 76(V0)
+2512: }\r
+2513: taskEXIT_CRITICAL();\r
+BFD07A4E 40AA77E8 JALS vTaskExitCritical
+BFD07A50 0C0040AA BNEZC T2, gpio_port_bitmaps
+BFD07A52 0C00 NOP
+2514: xReturn = pdPASS;\r
+BFD07A54 ED01 LI V0, 1
+BFD07A56 0010F85E SW V0, 16(S8)
+2515: }\r
+2516: \r
+2517: return xReturn;\r
+BFD07A5A 0010FC5E LW V0, 16(S8)
+2518: } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */\r
+BFD07A5E 0FBE MOVE SP, S8
+BFD07A60 4BE7 LW RA, 28(SP)
+BFD07A62 4BC6 LW S8, 24(SP)
+BFD07A64 4C11 ADDIU SP, SP, 32
+BFD07A66 459F JR16 RA
+BFD07A68 0C00 NOP
+2519: \r
+2520: #endif /* configUSE_QUEUE_SETS */\r
+2521: /*-----------------------------------------------------------*/\r
+2522: \r
+2523: #if ( configUSE_QUEUE_SETS == 1 )\r
+2524: \r
+2525: QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )\r
+2526: {\r
+BFD094E0 4FF1 ADDIU SP, SP, -32
+BFD094E2 CBE7 SW RA, 28(SP)
+BFD094E4 CBC6 SW S8, 24(SP)
+BFD094E6 0FDD MOVE S8, SP
+BFD094E8 0020F89E SW A0, 32(S8)
+BFD094EC 0024F8BE SW A1, 36(S8)
+2527: QueueSetMemberHandle_t xReturn = NULL;\r
+BFD094F0 0010F81E SW ZERO, 16(S8)
+2528: \r
+2529: ( void ) xQueueGenericReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait, pdFALSE ); /*lint !e961 Casting from one typedef to another is not redundant. */\r
+BFD094F4 0020FC9E LW A0, 32(S8)
+BFD094F8 0010305E ADDIU V0, S8, 16
+BFD094FC 0CA2 MOVE A1, V0
+BFD094FE 0024FCDE LW A2, 36(S8)
+BFD09502 0CE0 MOVE A3, ZERO
+BFD09504 081E77E8 JALS xQueueGenericReceive
+BFD09506 081E LBU S0, 14(S1)
+BFD09508 0C00 NOP
+2530: return xReturn;\r
+BFD0950A 0010FC5E LW V0, 16(S8)
+2531: }\r
+BFD0950E 0FBE MOVE SP, S8
+BFD09510 4BE7 LW RA, 28(SP)
+BFD09512 4BC6 LW S8, 24(SP)
+BFD09514 4C11 ADDIU SP, SP, 32
+BFD09516 459F JR16 RA
+BFD09518 0C00 NOP
+2532: \r
+2533: #endif /* configUSE_QUEUE_SETS */\r
+2534: /*-----------------------------------------------------------*/\r
+2535: \r
+2536: #if ( configUSE_QUEUE_SETS == 1 )\r
+2537: \r
+2538: QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )\r
+2539: {\r
+BFD097DC 4FF1 ADDIU SP, SP, -32
+BFD097DE CBE7 SW RA, 28(SP)
+BFD097E0 CBC6 SW S8, 24(SP)
+BFD097E2 0FDD MOVE S8, SP
+BFD097E4 0020F89E SW A0, 32(S8)
+2540: QueueSetMemberHandle_t xReturn = NULL;\r
+BFD097E8 0010F81E SW ZERO, 16(S8)
+2541: \r
+2542: ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */\r
+BFD097EC 0020FC9E LW A0, 32(S8)
+BFD097F0 0010305E ADDIU V0, S8, 16
+BFD097F4 0CA2 MOVE A1, V0
+BFD097F6 0CC0 MOVE A2, ZERO
+BFD097F8 1D6477E8 JALS xQueueReceiveFromISR
+BFD097FA 0C001D64 LB T3, 3072(A0)
+BFD097FC 0C00 NOP
+2543: return xReturn;\r
+BFD097FE 0010FC5E LW V0, 16(S8)
+2544: }\r
+BFD09802 0FBE MOVE SP, S8
+BFD09804 4BE7 LW RA, 28(SP)
+BFD09806 4BC6 LW S8, 24(SP)
+BFD09808 4C11 ADDIU SP, SP, 32
+BFD0980A 459F JR16 RA
+BFD0980C 0C00 NOP
+2545: \r
+2546: #endif /* configUSE_QUEUE_SETS */\r
+2547: /*-----------------------------------------------------------*/\r
+2548: \r
+2549: #if ( configUSE_QUEUE_SETS == 1 )\r
+2550: \r
+2551: static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )\r
+2552: {\r
+BFD043B0 4FF1 ADDIU SP, SP, -32
+BFD043B2 CBE7 SW RA, 28(SP)
+BFD043B4 CBC6 SW S8, 24(SP)
+BFD043B6 0FDD MOVE S8, SP
+BFD043B8 0020F89E SW A0, 32(S8)
+BFD043BC 0024F8BE SW A1, 36(S8)
+2553: Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;\r
+BFD043C0 0020FC5E LW V0, 32(S8)
+BFD043C4 004CFC42 LW V0, 76(V0)
+BFD043C8 0014F85E SW V0, 20(S8)
+2554: BaseType_t xReturn = pdFALSE;\r
+BFD043CC 0010F81E SW ZERO, 16(S8)
+2555: \r
+2556: /* This function must be called form a critical section. */\r
+2557: \r
+2558: configASSERT( pxQueueSetContainer );\r
+BFD043D0 0014FC5E LW V0, 20(S8)
+BFD043D4 000940A2 BNEZC V0, 0xBFD043EA
+BFD043D8 BFD141A2 LUI V0, 0xBFD1
+BFD043DA 3082BFD1 LDC1 F30, 12418(S1)
+BFD043DC 9E3C3082 ADDIU A0, V0, -25028
+BFD043DE 30A09E3C LWC1 F17, 12448(GP)
+BFD043E0 09FE30A0 ADDIU A1, ZERO, 2558
+BFD043E2 09FE LBU V1, 14(A3)
+BFD043E4 4B7E77E8 JALS vAssertCalled
+BFD043E6 4B7E LW K1, 120(SP)
+BFD043E8 0C00 NOP
+2559: configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );\r
+BFD043EA 0014FC5E LW V0, 20(S8)
+BFD043EE 69AE LW V1, 56(V0)
+BFD043F0 0014FC5E LW V0, 20(S8)
+BFD043F4 692F LW V0, 60(V0)
+BFD043F6 13900043 SLTU V0, V1, V0
+BFD043F8 40A21390 ADDI GP, S0, 16546
+BFD043FA 000940A2 BNEZC V0, 0xBFD04410
+BFD043FE BFD141A2 LUI V0, 0xBFD1
+BFD04400 3082BFD1 LDC1 F30, 12418(S1)
+BFD04402 9E3C3082 ADDIU A0, V0, -25028
+BFD04404 30A09E3C LWC1 F17, 12448(GP)
+BFD04406 09FF30A0 ADDIU A1, ZERO, 2559
+BFD04408 09FF LBU V1, -1(A3)
+BFD0440A 4B7E77E8 JALS vAssertCalled
+BFD0440C 4B7E LW K1, 120(SP)
+BFD0440E 0C00 NOP
+2560: \r
+2561: if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )\r
+BFD04410 0014FC5E LW V0, 20(S8)
+BFD04414 69AE LW V1, 56(V0)
+BFD04416 0014FC5E LW V0, 20(S8)
+BFD0441A 692F LW V0, 60(V0)
+BFD0441C 13900043 SLTU V0, V1, V0
+BFD0441E 40E21390 ADDI GP, S0, 16610
+BFD04420 003040E2 BEQZC V0, 0xBFD04484
+2562: {\r
+2563: traceQUEUE_SEND( pxQueueSetContainer );\r
+2564: \r
+2565: /* The data copied is the handle of the queue that contains data. */\r
+2566: xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );\r
+BFD04424 0014FC9E LW A0, 20(S8)
+BFD04428 002030BE ADDIU A1, S8, 32
+BFD0442C 0024FCDE LW A2, 36(S8)
+BFD04430 14E677E8 JALS prvCopyDataToQueue
+BFD04432 0C0014E6 LBU A3, 3072(A2)
+BFD04434 0C00 NOP
+BFD04436 0010F85E SW V0, 16(S8)
+2567: \r
+2568: if( pxQueueSetContainer->xTxLock == queueUNLOCKED )\r
+BFD0443A 0014FC5E LW V0, 20(S8)
+BFD0443E 0048FC62 LW V1, 72(V0)
+BFD04442 ED7F LI V0, -1
+BFD04444 0015B443 BNE V1, V0, 0xBFD04472
+BFD04446 0C000015 SLL ZERO, S5, 1
+BFD04448 0C00 NOP
+2569: {\r
+2570: if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )\r
+BFD0444A 0014FC5E LW V0, 20(S8)
+BFD0444E 6929 LW V0, 36(V0)
+BFD04450 001840E2 BEQZC V0, 0xBFD04484
+2571: {\r
+2572: if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )\r
+BFD04454 0014FC5E LW V0, 20(S8)
+BFD04458 00243042 ADDIU V0, V0, 36
+BFD0445C 0C82 MOVE A0, V0
+BFD0445E 22BC77E8 JALS xTaskRemoveFromEventList
+BFD04460 0C0022BC LWC2 S5, 3072(GP)
+BFD04462 0C00 NOP
+BFD04464 000E40E2 BEQZC V0, 0xBFD04484
+2573: {\r
+2574: /* The task waiting has a higher priority. */\r
+2575: xReturn = pdTRUE;\r
+BFD04468 ED01 LI V0, 1
+BFD0446A 0010F85E SW V0, 16(S8)
+BFD0446E CC0A B 0xBFD04484
+BFD04470 0C00 NOP
+2576: }\r
+2577: else\r
+2578: {\r
+2579: mtCOVERAGE_TEST_MARKER();\r
+2580: }\r
+2581: }\r
+2582: else\r
+2583: {\r
+2584: mtCOVERAGE_TEST_MARKER();\r
+2585: }\r
+2586: }\r
+2587: else\r
+2588: {\r
+2589: ( pxQueueSetContainer->xTxLock )++;\r
+BFD04472 0014FC5E LW V0, 20(S8)
+BFD04476 0048FC42 LW V0, 72(V0)
+BFD0447A 6DA0 ADDIU V1, V0, 1
+BFD0447C 0014FC5E LW V0, 20(S8)
+BFD04480 0048F862 SW V1, 72(V0)
+2590: }\r
+2591: }\r
+2592: else\r
+2593: {\r
+2594: mtCOVERAGE_TEST_MARKER();\r
+2595: }\r
+2596: \r
+2597: return xReturn;\r
+BFD04484 0010FC5E LW V0, 16(S8)
+2598: }\r
+BFD04488 0FBE MOVE SP, S8
+BFD0448A 4BE7 LW RA, 28(SP)
+BFD0448C 4BC6 LW S8, 24(SP)
+BFD0448E 4C11 ADDIU SP, SP, 32
+BFD04490 459F JR16 RA
+BFD04492 0C00 NOP
+2599: \r
+2600: #endif /* configUSE_QUEUE_SETS */\r
+2601: \r
+2602: \r
+2603: \r
+2604: \r
+2605: \r
+2606: \r
+2607: \r
+2608: \r
+2609: \r
+2610: \r
+2611: \r
+2612: \r
+--- c:/e/dev/freertos/workingcopy/freertos/source/portable/mplab/pic32mec14xx/portmacro.h -------------
+1: /*\r
+2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+3: All rights reserved\r
+4: \r
+5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+6: \r
+7: This file is part of the FreeRTOS distribution.\r
+8: \r
+9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
+10: the terms of the GNU General Public License (version 2) as published by the\r
+11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+12: \r
+13: ***************************************************************************\r
+14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+15: >>! distribute a combined work that includes FreeRTOS without being !<<\r
+16: >>! obliged to provide the source code for proprietary components !<<\r
+17: >>! outside of the FreeRTOS kernel. !<<\r
+18: ***************************************************************************\r
+19: \r
+20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+22: FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+23: link: http://www.freertos.org/a00114.html\r
+24: \r
+25: ***************************************************************************\r
+26: * *\r
+27: * FreeRTOS provides completely free yet professionally developed, *\r
+28: * robust, strictly quality controlled, supported, and cross *\r
+29: * platform software that is more than just the market leader, it *\r
+30: * is the industry's de facto standard. *\r
+31: * *\r
+32: * Help yourself get started quickly while simultaneously helping *\r
+33: * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+34: * tutorial book, reference manual, or both: *\r
+35: * http://www.FreeRTOS.org/Documentation *\r
+36: * *\r
+37: ***************************************************************************\r
+38: \r
+39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+40: the FAQ page "My application does not run, what could be wrong?". Have you\r
+41: defined configASSERT()?\r
+42: \r
+43: http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+44: embedded software for free we request you assist our global community by\r
+45: participating in the support forum.\r
+46: \r
+47: http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+48: be as productive as possible as early as possible. Now you can receive\r
+49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+50: Ltd, and the world's leading authority on the world's leading RTOS.\r
+51: \r
+52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+54: compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+55: \r
+56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+58: \r
+59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+61: licenses offer ticketed support, indemnification and commercial middleware.\r
+62: \r
+63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+64: engineered and independently SIL3 certified version for use in safety and\r
+65: mission critical applications that require provable dependability.\r
+66: \r
+67: 1 tab == 4 spaces!\r
+68: */\r
+69: \r
+70: #ifndef PORTMACRO_H\r
+71: #define PORTMACRO_H\r
+72: \r
+73: #ifdef __cplusplus\r
+74: extern "C" {\r
+75: #endif\r
+76: \r
+77: /*-----------------------------------------------------------\r
+78: * Port specific definitions.\r
+79: *\r
+80: * The settings in this file configure FreeRTOS correctly for the\r
+81: * given hardware and compiler.\r
+82: *\r
+83: * These settings should not be altered.\r
+84: *-----------------------------------------------------------\r
+85: */\r
+86: \r
+87: /* Type definitions. */\r
+88: #define portCHAR char\r
+89: #define portFLOAT float\r
+90: #define portDOUBLE double\r
+91: #define portLONG long\r
+92: #define portSHORT short\r
+93: #define portSTACK_TYPE uint32_t\r
+94: #define portBASE_TYPE long\r
+95: \r
+96: typedef portSTACK_TYPE StackType_t;\r
+97: typedef long BaseType_t;\r
+98: typedef unsigned long UBaseType_t;\r
+99: \r
+100: #if( configUSE_16_BIT_TICKS == 1 )\r
+101: typedef uint16_t TickType_t;\r
+102: #define portMAX_DELAY ( TickType_t ) 0xffff\r
+103: #else\r
+104: typedef uint32_t TickType_t;\r
+105: #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+106: #endif\r
+107: /*-----------------------------------------------------------*/\r
+108: \r
+109: /* Hardware specifics. */\r
+110: #define portBYTE_ALIGNMENT 8\r
+111: #define portSTACK_GROWTH -1\r
+112: #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+113: /*-----------------------------------------------------------*/\r
+114: \r
+115: /* Critical section management. */\r
+116: #define portIPL_SHIFT ( 10UL )\r
+117: /* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should\r
+118: never have higher IPL bits set anyway. */\r
+119: #define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )\r
+120: #define portSW0_BIT ( 0x01 << 8 )\r
+121: \r
+122: /*-----------------------------------------------------------*/\r
+123: \r
+124: static inline uint32_t ulPortGetCP0Status( void )\r
+125: {\r
+BFD09B4C 4FF9 ADDIU SP, SP, -16
+BFD09B4E CBC3 SW S8, 12(SP)
+BFD09B50 CA02 SW S0, 8(SP)
+BFD09B52 0FDD MOVE S8, SP
+BFD09C6C 4FF9 ADDIU SP, SP, -16
+BFD09C6E CBC3 SW S8, 12(SP)
+BFD09C70 CA02 SW S0, 8(SP)
+BFD09C72 0FDD MOVE S8, SP
+BFD09D6C 4FF9 ADDIU SP, SP, -16
+BFD09D6E CBC3 SW S8, 12(SP)
+BFD09D70 CA02 SW S0, 8(SP)
+BFD09D72 0FDD MOVE S8, SP
+126: uint32_t rv;\r
+127: \r
+128: __asm volatile(\r
+BFD09B54 00FC020C MFC0 S0, Status
+BFD09B58 0000FA1E SW S0, 0(S8)
+BFD09C74 00FC020C MFC0 S0, Status
+BFD09C78 0000FA1E SW S0, 0(S8)
+BFD09D74 00FC020C MFC0 S0, Status
+BFD09D78 0000FA1E SW S0, 0(S8)
+129: "\n\t"\r
+130: "mfc0 %0,$12,0 \n\t"\r
+131: : "=r" ( rv ) :: );\r
+132: \r
+133: return rv;\r
+BFD09B5C 0000FC5E LW V0, 0(S8)
+BFD09C7C 0000FC5E LW V0, 0(S8)
+BFD09D7C 0000FC5E LW V0, 0(S8)
+134: }\r
+BFD09B60 0FBE MOVE SP, S8
+BFD09B62 4BC3 LW S8, 12(SP)
+BFD09B64 4A02 LW S0, 8(SP)
+BFD09B66 459F JR16 RA
+BFD09B68 4C09 ADDIU SP, SP, 16
+BFD09C80 0FBE MOVE SP, S8
+BFD09C82 4BC3 LW S8, 12(SP)
+BFD09C84 4A02 LW S0, 8(SP)
+BFD09C86 459F JR16 RA
+BFD09C88 4C09 ADDIU SP, SP, 16
+BFD09D80 0FBE MOVE SP, S8
+BFD09D82 4BC3 LW S8, 12(SP)
+BFD09D84 4A02 LW S0, 8(SP)
+BFD09D86 459F JR16 RA
+BFD09D88 4C09 ADDIU SP, SP, 16
+135: /*-----------------------------------------------------------*/\r
+136: \r
+137: static inline void vPortSetCP0Status( uint32_t new_status)\r
+138: {\r
+BFD09B6C 4FB0 ADDIU SP, SP, -8
+BFD09B6E CBC1 SW S8, 4(SP)
+BFD09B70 0FDD MOVE S8, SP
+BFD09B72 0008F89E SW A0, 8(S8)
+BFD09C8C 4FB0 ADDIU SP, SP, -8
+BFD09C8E CBC1 SW S8, 4(SP)
+BFD09C90 0FDD MOVE S8, SP
+BFD09C92 0008F89E SW A0, 8(S8)
+BFD09D8C 4FB0 ADDIU SP, SP, -8
+BFD09D8E CBC1 SW S8, 4(SP)
+BFD09D90 0FDD MOVE S8, SP
+BFD09D92 0008F89E SW A0, 8(S8)
+139: ( void ) new_status;\r
+140: \r
+141: __asm__ __volatile__(\r
+BFD09B76 0008FC5E LW V0, 8(S8)
+BFD09B78 004C0008 INS ZERO, T0, 1, 0
+BFD09B7A 02FC004C MTC0 V0, Status
+BFD09B7C 000002FC SLL S7, GP, 0
+BFD09B7E 18000000 SLL ZERO, ZERO, 3
+BFD09B80 0FBE1800 SB ZERO, 4030(ZERO)
+BFD09C96 0008FC5E LW V0, 8(S8)
+BFD09C98 004C0008 INS ZERO, T0, 1, 0
+BFD09C9A 02FC004C MTC0 V0, Status
+BFD09C9C 000002FC SLL S7, GP, 0
+BFD09C9E 18000000 SLL ZERO, ZERO, 3
+BFD09CA0 0FBE1800 SB ZERO, 4030(ZERO)
+BFD09D96 0008FC5E LW V0, 8(S8)
+BFD09D98 004C0008 INS ZERO, T0, 1, 0
+BFD09D9A 02FC004C MTC0 V0, Status
+BFD09D9C 000002FC SLL S7, GP, 0
+BFD09D9E 18000000 SLL ZERO, ZERO, 3
+BFD09DA0 0FBE1800 SB ZERO, 4030(ZERO)
+142: "\n\t"\r
+143: "mtc0 %0,$12,0 \n\t"\r
+144: "ehb \n\t"\r
+145: :\r
+146: :"r" ( new_status ) : );\r
+147: }\r
+BFD09B82 0FBE MOVE SP, S8
+BFD09B84 4BC1 LW S8, 4(SP)
+BFD09B86 459F JR16 RA
+BFD09B88 4C05 ADDIU SP, SP, 8
+BFD09CA2 0FBE MOVE SP, S8
+BFD09CA4 4BC1 LW S8, 4(SP)
+BFD09CA6 459F JR16 RA
+BFD09CA8 4C05 ADDIU SP, SP, 8
+BFD09DA2 0FBE MOVE SP, S8
+BFD09DA4 4BC1 LW S8, 4(SP)
+BFD09DA6 459F JR16 RA
+BFD09DA8 4C05 ADDIU SP, SP, 8
+148: /*-----------------------------------------------------------*/\r
+149: \r
+150: static inline uint32_t ulPortGetCP0Cause( void )\r
+151: {\r
+BFD09B8C 4FF9 ADDIU SP, SP, -16
+BFD09B8E CBC3 SW S8, 12(SP)
+BFD09B90 CA02 SW S0, 8(SP)
+BFD09B92 0FDD MOVE S8, SP
+BFD09BCC 4FF9 ADDIU SP, SP, -16
+BFD09BCE CBC3 SW S8, 12(SP)
+BFD09BD0 CA02 SW S0, 8(SP)
+BFD09BD2 0FDD MOVE S8, SP
+BFD09C2C 4FF9 ADDIU SP, SP, -16
+BFD09C2E CBC3 SW S8, 12(SP)
+BFD09C30 CA02 SW S0, 8(SP)
+BFD09C32 0FDD MOVE S8, SP
+BFD09CAC 4FF9 ADDIU SP, SP, -16
+BFD09CAE CBC3 SW S8, 12(SP)
+BFD09CB0 CA02 SW S0, 8(SP)
+BFD09CB2 0FDD MOVE S8, SP
+BFD09CEC 4FF9 ADDIU SP, SP, -16
+BFD09CEE CBC3 SW S8, 12(SP)
+BFD09CF0 CA02 SW S0, 8(SP)
+BFD09CF2 0FDD MOVE S8, SP
+152: uint32_t rv;\r
+153: \r
+154: __asm volatile(\r
+BFD09B94 00FC020D MFC0 S0, Cause
+BFD09B98 0000FA1E SW S0, 0(S8)
+BFD09BD4 00FC020D MFC0 S0, Cause
+BFD09BD8 0000FA1E SW S0, 0(S8)
+BFD09C34 00FC020D MFC0 S0, Cause
+BFD09C38 0000FA1E SW S0, 0(S8)
+BFD09CB4 00FC020D MFC0 S0, Cause
+BFD09CB8 0000FA1E SW S0, 0(S8)
+BFD09CF4 00FC020D MFC0 S0, Cause
+BFD09CF8 0000FA1E SW S0, 0(S8)
+155: "\n\t"\r
+156: "mfc0 %0,$13,0 \n\t"\r
+157: : "=r" ( rv ) :: );\r
+158: \r
+159: return rv;\r
+BFD09B9C 0000FC5E LW V0, 0(S8)
+BFD09BDC 0000FC5E LW V0, 0(S8)
+BFD09C3C 0000FC5E LW V0, 0(S8)
+BFD09CBC 0000FC5E LW V0, 0(S8)
+BFD09CFC 0000FC5E LW V0, 0(S8)
+160: }\r
+BFD09BA0 0FBE MOVE SP, S8
+BFD09BA2 4BC3 LW S8, 12(SP)
+BFD09BA4 4A02 LW S0, 8(SP)
+BFD09BA6 459F JR16 RA
+BFD09BA8 4C09 ADDIU SP, SP, 16
+BFD09BE0 0FBE MOVE SP, S8
+BFD09BE2 4BC3 LW S8, 12(SP)
+BFD09BE4 4A02 LW S0, 8(SP)
+BFD09BE6 459F JR16 RA
+BFD09BE8 4C09 ADDIU SP, SP, 16
+BFD09C40 0FBE MOVE SP, S8
+BFD09C42 4BC3 LW S8, 12(SP)
+BFD09C44 4A02 LW S0, 8(SP)
+BFD09C46 459F JR16 RA
+BFD09C48 4C09 ADDIU SP, SP, 16
+BFD09CC0 0FBE MOVE SP, S8
+BFD09CC2 4BC3 LW S8, 12(SP)
+BFD09CC4 4A02 LW S0, 8(SP)
+BFD09CC6 459F JR16 RA
+BFD09CC8 4C09 ADDIU SP, SP, 16
+BFD09D00 0FBE MOVE SP, S8
+BFD09D02 4BC3 LW S8, 12(SP)
+BFD09D04 4A02 LW S0, 8(SP)
+BFD09D06 459F JR16 RA
+BFD09D08 4C09 ADDIU SP, SP, 16
+161: /*-----------------------------------------------------------*/\r
+162: \r
+163: static inline void vPortSetCP0Cause( uint32_t new_cause )\r
+164: {\r
+BFD09BAC 4FB0 ADDIU SP, SP, -8
+BFD09BAE CBC1 SW S8, 4(SP)
+BFD09BB0 0FDD MOVE S8, SP
+BFD09BB2 0008F89E SW A0, 8(S8)
+BFD09BEC 4FB0 ADDIU SP, SP, -8
+BFD09BEE CBC1 SW S8, 4(SP)
+BFD09BF0 0FDD MOVE S8, SP
+BFD09BF2 0008F89E SW A0, 8(S8)
+BFD09C4C 4FB0 ADDIU SP, SP, -8
+BFD09C4E CBC1 SW S8, 4(SP)
+BFD09C50 0FDD MOVE S8, SP
+BFD09C52 0008F89E SW A0, 8(S8)
+BFD09CCC 4FB0 ADDIU SP, SP, -8
+BFD09CCE CBC1 SW S8, 4(SP)
+BFD09CD0 0FDD MOVE S8, SP
+BFD09CD2 0008F89E SW A0, 8(S8)
+BFD09D0C 4FB0 ADDIU SP, SP, -8
+BFD09D0E CBC1 SW S8, 4(SP)
+BFD09D10 0FDD MOVE S8, SP
+BFD09D12 0008F89E SW A0, 8(S8)
+165: ( void ) new_cause;\r
+166: \r
+167: __asm__ __volatile__(\r
+BFD09BB6 0008FC5E LW V0, 8(S8)
+BFD09BB8 004D0008 ADDQH.PH ZERO, T0, ZERO
+BFD09BBA 02FC004D MTC0 V0, Cause
+BFD09BBC 000002FC SLL S7, GP, 0
+BFD09BBE 18000000 SLL ZERO, ZERO, 3
+BFD09BC0 0FBE1800 SB ZERO, 4030(ZERO)
+BFD09BF6 0008FC5E LW V0, 8(S8)
+BFD09BF8 004D0008 ADDQH.PH ZERO, T0, ZERO
+BFD09BFA 02FC004D MTC0 V0, Cause
+BFD09BFC 000002FC SLL S7, GP, 0
+BFD09BFE 18000000 SLL ZERO, ZERO, 3
+BFD09C00 0FBE1800 SB ZERO, 4030(ZERO)
+BFD09C56 0008FC5E LW V0, 8(S8)
+BFD09C58 004D0008 ADDQH.PH ZERO, T0, ZERO
+BFD09C5A 02FC004D MTC0 V0, Cause
+BFD09C5C 000002FC SLL S7, GP, 0
+BFD09C5E 18000000 SLL ZERO, ZERO, 3
+BFD09C60 0FBE1800 SB ZERO, 4030(ZERO)
+BFD09CD6 0008FC5E LW V0, 8(S8)
+BFD09CD8 004D0008 ADDQH.PH ZERO, T0, ZERO
+BFD09CDA 02FC004D MTC0 V0, Cause
+BFD09CDC 000002FC SLL S7, GP, 0
+BFD09CDE 18000000 SLL ZERO, ZERO, 3
+BFD09CE0 0FBE1800 SB ZERO, 4030(ZERO)
+BFD09D16 0008FC5E LW V0, 8(S8)
+BFD09D18 004D0008 ADDQH.PH ZERO, T0, ZERO
+BFD09D1A 02FC004D MTC0 V0, Cause
+BFD09D1C 000002FC SLL S7, GP, 0
+BFD09D1E 18000000 SLL ZERO, ZERO, 3
+BFD09D20 0FBE1800 SB ZERO, 4030(ZERO)
+168: "\n\t"\r
+169: "mtc0 %0,$13,0 \n\t"\r
+170: "ehb \n\t"\r
+171: :\r
+172: :"r" ( new_cause ) : );\r
+173: }\r
+BFD09BC2 0FBE MOVE SP, S8
+BFD09BC4 4BC1 LW S8, 4(SP)
+BFD09BC6 459F JR16 RA
+BFD09BC8 4C05 ADDIU SP, SP, 8
+BFD09C02 0FBE MOVE SP, S8
+BFD09C04 4BC1 LW S8, 4(SP)
+BFD09C06 459F JR16 RA
+BFD09C08 4C05 ADDIU SP, SP, 8
+BFD09C62 0FBE MOVE SP, S8
+BFD09C64 4BC1 LW S8, 4(SP)
+BFD09C66 459F JR16 RA
+BFD09C68 4C05 ADDIU SP, SP, 8
+BFD09CE2 0FBE MOVE SP, S8
+BFD09CE4 4BC1 LW S8, 4(SP)
+BFD09CE6 459F JR16 RA
+BFD09CE8 4C05 ADDIU SP, SP, 8
+BFD09D22 0FBE MOVE SP, S8
+BFD09D24 4BC1 LW S8, 4(SP)
+BFD09D26 459F JR16 RA
+BFD09D28 4C05 ADDIU SP, SP, 8
+174: /*-----------------------------------------------------------*/\r
+175: \r
+176: /* This clears the IPL bits, then sets them to\r
+177: configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if\r
+178: configASSERT() is defined to ensure an assertion handler does not inadvertently\r
+179: attempt to lower the IPL when the call to assert was triggered because the IPL\r
+180: value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR\r
+181: safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are\r
+182: those that end in FromISR. FreeRTOS maintains a separate interrupt API to\r
+183: ensure API function and interrupt entry is as fast and as simple as possible. */\r
+184: #ifdef configASSERT\r
+185: #define portDISABLE_INTERRUPTS() \\r
+186: { \\r
+187: uint32_t ulStatus; \\r
+188: /* Mask interrupts at and below the kernel interrupt priority. */ \\r
+189: ulStatus = ulPortGetCP0Status(); \\r
+190: /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \\r
+191: if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \\r
+192: { \\r
+193: ulStatus &= ~portALL_IPL_BITS; \\r
+194: vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \\r
+195: } \\r
+196: }\r
+197: #else /* configASSERT */\r
+198: #define portDISABLE_INTERRUPTS() \\r
+199: { \\r
+200: uint32_t ulStatus; \\r
+201: /* Mask interrupts at and below the kernel interrupt priority. */ \\r
+202: ulStatus = ulPortGetCP0Status(); \\r
+203: ulStatus &= ~portALL_IPL_BITS; \\r
+204: vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \\r
+205: }\r
+206: #endif /* configASSERT */\r
+207: \r
+208: #define portENABLE_INTERRUPTS() \\r
+209: { \\r
+210: uint32_t ulStatus; \\r
+211: /* Unmask all interrupts. */ \\r
+212: ulStatus = ulPortGetCP0Status(); \\r
+213: ulStatus &= ~portALL_IPL_BITS; \\r
+214: vPortSetCP0Status( ulStatus ); \\r
+215: }\r
+216: \r
+217: \r
+218: extern void vTaskEnterCritical( void );\r
+219: extern void vTaskExitCritical( void );\r
+220: #define portCRITICAL_NESTING_IN_TCB 1\r
+221: #define portENTER_CRITICAL() vTaskEnterCritical()\r
+222: #define portEXIT_CRITICAL() vTaskExitCritical()\r
+223: \r
+224: extern UBaseType_t uxPortSetInterruptMaskFromISR();\r
+225: extern void vPortClearInterruptMaskFromISR( UBaseType_t );\r
+226: #define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()\r
+227: #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )\r
+228: \r
+229: #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
+230: #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+231: #endif\r
+232: \r
+233: #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+234: \r
+235: /* Check the configuration. */\r
+236: #if( configMAX_PRIORITIES > 32 )\r
+237: #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+238: #endif\r
+239: \r
+240: /* Store/clear the ready priorities in a bit map. */\r
+241: #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+242: #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+243: \r
+244: /*-----------------------------------------------------------*/\r
+245: \r
+246: #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )\r
+247: \r
+248: #endif /* taskRECORD_READY_PRIORITY */\r
+249: \r
+250: /*-----------------------------------------------------------*/\r
+251: \r
+252: /* Task utilities. */\r
+253: \r
+254: #define portYIELD() \\r
+255: { \\r
+256: uint32_t ulCause; \\r
+257: /* Trigger software interrupt. */ \\r
+258: ulCause = ulPortGetCP0Cause(); \\r
+259: ulCause |= portSW0_BIT; \\r
+260: vPortSetCP0Cause( ulCause ); \\r
+261: }\r
+262: \r
+263: extern volatile UBaseType_t uxInterruptNesting;\r
+264: #define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )\r
+265: \r
+266: #define portNOP() __asm volatile ( "nop" )\r
+267: \r
+268: /*-----------------------------------------------------------*/\r
+269: \r
+270: /* Task function macros as described on the FreeRTOS.org WEB site. */\r
+271: #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))\r
+272: #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+273: /*-----------------------------------------------------------*/\r
+274: \r
+275: #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) \\r
+276: { \\r
+277: portYIELD(); \\r
+278: }\r
+279: \r
+280: /* Required by the kernel aware debugger. */\r
+281: #ifdef __DEBUG\r
+282: #define portREMOVE_STATIC_QUALIFIER\r
+283: #endif\r
+284: \r
+285: #ifdef __cplusplus\r
+286: }\r
+287: #endif\r
+288: \r
+289: #endif /* PORTMACRO_H */\r
+290: \r
+--- c:/e/dev/freertos/workingcopy/freertos/source/portable/mplab/pic32mec14xx/port.c ------------------
+1: /*\r
+2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+3: All rights reserved\r
+4: \r
+5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+6: \r
+7: This file is part of the FreeRTOS distribution.\r
+8: \r
+9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
+10: the terms of the GNU General Public License (version 2) as published by the\r
+11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+12: \r
+13: ***************************************************************************\r
+14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+15: >>! distribute a combined work that includes FreeRTOS without being !<<\r
+16: >>! obliged to provide the source code for proprietary components !<<\r
+17: >>! outside of the FreeRTOS kernel. !<<\r
+18: ***************************************************************************\r
+19: \r
+20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+22: FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+23: link: http://www.freertos.org/a00114.html\r
+24: \r
+25: ***************************************************************************\r
+26: * *\r
+27: * FreeRTOS provides completely free yet professionally developed, *\r
+28: * robust, strictly quality controlled, supported, and cross *\r
+29: * platform software that is more than just the market leader, it *\r
+30: * is the industry's de facto standard. *\r
+31: * *\r
+32: * Help yourself get started quickly while simultaneously helping *\r
+33: * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+34: * tutorial book, reference manual, or both: *\r
+35: * http://www.FreeRTOS.org/Documentation *\r
+36: * *\r
+37: ***************************************************************************\r
+38: \r
+39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+40: the FAQ page "My application does not run, what could be wrong?". Have you\r
+41: defined configASSERT()?\r
+42: \r
+43: http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+44: embedded software for free we request you assist our global community by\r
+45: participating in the support forum.\r
+46: \r
+47: http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+48: be as productive as possible as early as possible. Now you can receive\r
+49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+50: Ltd, and the world's leading authority on the world's leading RTOS.\r
+51: \r
+52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+54: compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+55: \r
+56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+58: \r
+59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+61: licenses offer ticketed support, indemnification and commercial middleware.\r
+62: \r
+63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+64: engineered and independently SIL3 certified version for use in safety and\r
+65: mission critical applications that require provable dependability.\r
+66: \r
+67: 1 tab == 4 spaces!\r
+68: */\r
+69: \r
+70: /*-----------------------------------------------------------\r
+71: * Implementation of functions defined in portable.h for the PIC32MZ port.\r
+72: *----------------------------------------------------------*/\r
+73: \r
+74: #include <xc.h>\r
+75: #include <cp0defs.h>\r
+76: \r
+77: /* Scheduler include files. */\r
+78: #include "FreeRTOS.h"\r
+79: #include "task.h"\r
+80: \r
+81: #if !defined(__MEC__)\r
+82: #error This port is designed to work with XC32 on MEC14xx. Please update your C compiler version or settings.\r
+83: #endif\r
+84: \r
+85: #if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )\r
+86: #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0\r
+87: #endif\r
+88: \r
+89: /* Hardware specifics. */\r
+90: #define portTIMER_PRESCALE 8\r
+91: #define portPRESCALE_BITS 1\r
+92: \r
+93: /* Bits within various registers. */\r
+94: #define portIE_BIT ( 0x00000001 )\r
+95: #define portEXL_BIT ( 0x00000002 )\r
+96: #define portMX_BIT ( 0x01000000 ) /* Allow access to DSP instructions. */\r
+97: \r
+98: /* Bits within the CAUSE register. */\r
+99: #define portCORE_SW_0 ( 0x00000100 )\r
+100: #define portCORE_SW_1 ( 0x00000200 )\r
+101: \r
+102: /* The EXL bit is set to ensure interrupts do not occur while the context of\r
+103: the first task is being restored. */\r
+104: /* MEC14xx does not have DSP HW */\r
+105: #define portINITIAL_SR ( portIE_BIT | portEXL_BIT )\r
+106: \r
+107: /* MEC14xx RTOS Timer MMCR's */\r
+108: #define portMMCR_RTMR_PRELOAD *((volatile uint32_t *)(0xA0007404ul))\r
+109: #define portMMCR_RTMR_CONTROL *((volatile uint32_t *)(0xA0007408ul))\r
+110: \r
+111: /* MEC14xx JTVIC external interrupt controller\r
+112: * is mapped to M14K closely-coupled peripheral space.\r
+113: */\r
+114: #define portGIRQ23_RTOS_TIMER_BITPOS (4)\r
+115: #define portGIRQ23_RTOS_TIMER_MASK (1ul << (portGIRQ23_RTOS_TIMER_BITPOS))\r
+116: #define portMMCR_JTVIC_GIRQ23_SRC *((volatile uint32_t *)(0xBFFFC0F0ul))\r
+117: #define portMMCR_JTVIC_GIRQ23_SETEN *((volatile uint32_t *)(0xBFFFC0F4ul))\r
+118: #define portMMCR_JTVIC_GIRQ23_CLREN *((volatile uint32_t *)(0xBFFFC0F8ul))\r
+119: #define portMMCR_JTVIC_GIRQ23_RESULT *((volatile uint32_t *)(0xBFFFC0FCul))\r
+120: #define portMMCR_JTVIC_GIRQ23_AGCTRL *((volatile uint32_t *)(0xBFFFC23Cul))\r
+121: #define portMMCR_JTVIC_GIRQ23_PRIA *((volatile uint32_t *)(0xBFFFC3F0ul))\r
+122: #define portMMCR_JTVIC_GIRQ23_PRIB *((volatile uint32_t *)(0xBFFFC3F4ul))\r
+123: #define portMMCR_JTVIC_GIRQ23_PRIC *((volatile uint32_t *)(0xBFFFC3F8ul))\r
+124: #define portMMCR_JTVIC_GIRQ23_PRID *((volatile uint32_t *)(0xBFFFC3FCul))\r
+125: \r
+126: /* MIPS Software Interrupts are routed through JTVIC GIRQ24 */\r
+127: #define portGIRQ24_M14K_SOFTIRQ0_BITPOS (1)\r
+128: #define portGIRQ24_M14K_SOFTIRQ0_MASK (1ul << (portGIRQ24_M14K_SOFTIRQ0_BITPOS))\r
+129: #define portMMCR_JTVIC_GIRQ24_SRC *((volatile uint32_t *)(0xBFFFC100ul))\r
+130: #define portMMCR_JTVIC_GIRQ24_SETEN *((volatile uint32_t *)(0xBFFFC104ul))\r
+131: #define portMMCR_JTVIC_GIRQ24_CLREN *((volatile uint32_t *)(0xBFFFC108ul))\r
+132: #define portMMCR_JTVIC_GIRQ24_RESULT *((volatile uint32_t *)(0xBFFFC10Cul))\r
+133: #define portMMCR_JTVIC_GIRQ24_AGCTRL *((volatile uint32_t *)(0xBFFFC240ul))\r
+134: #define portMMCR_JTVIC_GIRQ24_PRIA *((volatile uint32_t *)(0xBFFFC400ul))\r
+135: #define portMMCR_JTVIC_GIRQ24_PRIB *((volatile uint32_t *)(0xBFFFC404ul))\r
+136: #define portMMCR_JTVIC_GIRQ24_PRIC *((volatile uint32_t *)(0xBFFFC408ul))\r
+137: #define portMMCR_JTVIC_GIRQ24_PRID *((volatile uint32_t *)(0xBFFFC40Cul))\r
+138: \r
+139: /*\r
+140: By default port.c generates its tick interrupt from TIMER1. The user can\r
+141: override this behaviour by:\r
+142: 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),\r
+143: which is the function that configures the timer. The function is defined\r
+144: as a weak symbol in this file so if the same function name is used in the\r
+145: application code then the version in the application code will be linked\r
+146: into the application in preference to the version defined in this file.\r
+147: 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used\r
+148: to generate the tick interrupt. For example, when timer 1 is used then\r
+149: configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.\r
+150: configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.\r
+151: 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the\r
+152: timer used to generate the tick interrupt. For example, when timer 1 is\r
+153: used configCLEAR_TICK_TIMER_INTERRUPT() is defined to\r
+154: IFS0CLR = _IFS0_T1IF_MASK.\r
+155: */\r
+156: #ifndef configTICK_INTERRUPT_VECTOR\r
+157: #define configTICK_INTERRUPT_VECTOR girq23_b4\r
+158: #define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK\r
+159: #else\r
+160: #ifndef configCLEAR_TICK_TIMER_INTERRUPT\r
+161: #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.\r
+162: #endif\r
+163: #endif\r
+164: \r
+165: /* Let the user override the pre-loading of the initial RA with the address of\r
+166: prvTaskExitError() in case is messes up unwinding of the stack in the\r
+167: debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */\r
+168: #ifdef configTASK_RETURN_ADDRESS\r
+169: #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+170: #else\r
+171: #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+172: #endif\r
+173: \r
+174: /* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task\r
+175: stack checking. A problem in the ISR stack will trigger an assert, not call the\r
+176: stack overflow hook function (because the stack overflow hook is specific to a\r
+177: task stack, not the ISR stack). */\r
+178: #if( configCHECK_FOR_STACK_OVERFLOW > 2 )\r
+179: \r
+180: /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for\r
+181: the task stacks, and so will legitimately appear in many positions within\r
+182: the ISR stack. */\r
+183: #define portISR_STACK_FILL_BYTE 0xee\r
+184: \r
+185: static const uint8_t ucExpectedStackBytes[] = {\r
+186: portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \\r
+187: portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \\r
+188: portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \\r
+189: portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \\r
+190: portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \\r
+191: \r
+192: #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )\r
+193: #else\r
+194: /* Define the function away. */\r
+195: #define portCHECK_ISR_STACK()\r
+196: #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */\r
+197: \r
+198: \r
+199: /*-----------------------------------------------------------*/\r
+200: \r
+201: /*\r
+202: * Used to catch tasks that attempt to return from their implementing function.\r
+203: */\r
+204: static void prvTaskExitError( void );\r
+205: \r
+206: /*-----------------------------------------------------------*/\r
+207: \r
+208: /* Records the interrupt nesting depth. This is initialised to one as it is\r
+209: decremented to 0 when the first task starts. */\r
+210: volatile UBaseType_t uxInterruptNesting = 0x01;\r
+211: \r
+212: /* Stores the task stack pointer when a switch is made to use the system stack. */\r
+213: UBaseType_t uxSavedTaskStackPointer = 0;\r
+214: \r
+215: /* The stack used by interrupt service routines that cause a context switch. */\r
+216: StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };\r
+217: \r
+218: /* The top of stack value ensures there is enough space to store 6 registers on\r
+219: the callers stack, as some functions seem to want to do this. */\r
+220: const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );\r
+221: \r
+222: /*-----------------------------------------------------------*/\r
+223: \r
+224: /* Local inline assembly routines to read/write MIPS M14K CP0 registers. Avoids\r
+225: the need for compiler intrinsics which vary with compiler. */\r
+226: static uint32_t prvDisableInterrupt( void )\r
+227: {\r
+BFD09A98 4FF9 ADDIU SP, SP, -16
+BFD09A9A CBC3 SW S8, 12(SP)
+BFD09A9C CA02 SW S0, 8(SP)
+BFD09A9E 0FDD MOVE S8, SP
+228: uint32_t prev_state;\r
+229: \r
+230: __asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );\r
+BFD09AA0 477C0010 DI S0
+BFD09AA4 18000000 SLL ZERO, ZERO, 3
+BFD09AA6 FA1E1800 SB ZERO, -1506(ZERO)
+BFD09AA8 0000FA1E SW S0, 0(S8)
+231: return prev_state;\r
+BFD09AAC 0000FC5E LW V0, 0(S8)
+232: }\r
+BFD09AB0 0FBE MOVE SP, S8
+BFD09AB2 4BC3 LW S8, 12(SP)
+BFD09AB4 4A02 LW S0, 8(SP)
+BFD09AB6 459F JR16 RA
+BFD09AB8 4C09 ADDIU SP, SP, 16
+233: \r
+234: \r
+235: /*\r
+236: * See header file for description.\r
+237: */\r
+238: StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
+239: {\r
+BFD05630 4FF5 ADDIU SP, SP, -24
+BFD05632 CBE5 SW RA, 20(SP)
+BFD05634 CBC4 SW S8, 16(SP)
+BFD05636 0FDD MOVE S8, SP
+BFD05638 0018F89E SW A0, 24(S8)
+BFD0563C 001CF8BE SW A1, 28(S8)
+BFD05640 0020F8DE SW A2, 32(S8)
+240: /* Ensure byte alignment is maintained when leaving this function. */\r
+241: pxTopOfStack--;\r
+BFD05644 0018FC5E LW V0, 24(S8)
+BFD05646 4C580018 MOVZ T1, T8, ZERO
+BFD05648 4C58 ADDIU V0, V0, -4
+BFD0564A 0018F85E SW V0, 24(S8)
+242: \r
+243: *pxTopOfStack = (StackType_t) 0xDEADBEEF;\r
+BFD0564E 0018FC5E LW V0, 24(S8)
+BFD05652 DEAD41A3 LUI V1, 0xDEAD
+BFD05656 BEEF5063 ORI V1, V1, -16657
+BFD05658 E9A0BEEF LDC1 F23, -5728(T7)
+BFD0565A E9A0 SW V1, 0(V0)
+244: pxTopOfStack--;\r
+BFD0565C 0018FC5E LW V0, 24(S8)
+BFD0565E 4C580018 MOVZ T1, T8, ZERO
+BFD05660 4C58 ADDIU V0, V0, -4
+BFD05662 0018F85E SW V0, 24(S8)
+245: \r
+246: *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */\r
+BFD05666 0018FC5E LW V0, 24(S8)
+BFD0566A 123441A3 LUI V1, 0x1234
+BFD0566C 50631234 ADDI S1, S4, 20579
+BFD0566E 56785063 ORI V1, V1, 22136
+BFD05670 E9A05678 PREFX 29, 19(T8)
+BFD05672 E9A0 SW V1, 0(V0)
+247: pxTopOfStack--;\r
+BFD05674 0018FC5E LW V0, 24(S8)
+BFD05676 4C580018 MOVZ T1, T8, ZERO
+BFD05678 4C58 ADDIU V0, V0, -4
+BFD0567A 0018F85E SW V0, 24(S8)
+248: \r
+249: *pxTopOfStack = (StackType_t) ulPortGetCP0Cause();\r
+BFD0567E 4DC677E8 JALS ulPortGetCP0Cause
+BFD05680 4DC6 ADDIU T6, T6, 3
+BFD05682 0C00 NOP
+BFD05684 0C62 MOVE V1, V0
+BFD05686 0018FC5E LW V0, 24(S8)
+BFD0568A E9A0 SW V1, 0(V0)
+250: pxTopOfStack--;\r
+BFD0568C 0018FC5E LW V0, 24(S8)
+BFD0568E 4C580018 MOVZ T1, T8, ZERO
+BFD05690 4C58 ADDIU V0, V0, -4
+BFD05692 0018F85E SW V0, 24(S8)
+251: \r
+252: *pxTopOfStack = (StackType_t) portINITIAL_SR; /* CP0_STATUS */\r
+BFD05696 0018FC5E LW V0, 24(S8)
+BFD0569A ED83 LI V1, 3
+BFD0569C E9A0 SW V1, 0(V0)
+253: pxTopOfStack--;\r
+BFD0569E 0018FC5E LW V0, 24(S8)
+BFD056A0 4C580018 MOVZ T1, T8, ZERO
+BFD056A2 4C58 ADDIU V0, V0, -4
+BFD056A4 0018F85E SW V0, 24(S8)
+254: \r
+255: *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */\r
+BFD056A8 001CFC7E LW V1, 28(S8)
+BFD056AC 0018FC5E LW V0, 24(S8)
+BFD056B0 E9A0 SW V1, 0(V0)
+256: pxTopOfStack--;\r
+BFD056B2 0018FC5E LW V0, 24(S8)
+BFD056B4 4C580018 MOVZ T1, T8, ZERO
+BFD056B6 4C58 ADDIU V0, V0, -4
+BFD056B8 0018F85E SW V0, 24(S8)
+257: \r
+258: *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */\r
+BFD056BC BFD041A2 LUI V0, 0xBFD0
+BFD056BE 3062BFD0 LDC1 F30, 12386(S0)
+BFD056C0 7BBD3062 ADDIU V1, V0, 31677
+BFD056C2 FC5E7BBD ADDIUPC A3, 4062302
+BFD056C4 0018FC5E LW V0, 24(S8)
+BFD056C8 E9A0 SW V1, 0(V0)
+259: pxTopOfStack -= 15;\r
+BFD056CA 0018FC5E LW V0, 24(S8)
+BFD056CE FFC43042 ADDIU V0, V0, -60
+BFD056D0 F85EFFC4 LW S8, -1954(A0)
+BFD056D2 0018F85E SW V0, 24(S8)
+260: \r
+261: *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */\r
+BFD056D6 0020FC7E LW V1, 32(S8)
+BFD056DA 0018FC5E LW V0, 24(S8)
+BFD056DE E9A0 SW V1, 0(V0)
+262: pxTopOfStack -= 15;\r
+BFD056E0 0018FC5E LW V0, 24(S8)
+BFD056E4 FFC43042 ADDIU V0, V0, -60
+BFD056E6 F85EFFC4 LW S8, -1954(A0)
+BFD056E8 0018F85E SW V0, 24(S8)
+263: \r
+264: return pxTopOfStack;\r
+BFD056EC 0018FC5E LW V0, 24(S8)
+265: }\r
+BFD056F0 0FBE MOVE SP, S8
+BFD056F2 4BE5 LW RA, 20(SP)
+BFD056F4 4BC4 LW S8, 16(SP)
+BFD056F6 4C0D ADDIU SP, SP, 24
+BFD056F8 459F JR16 RA
+BFD056FA 0C00 NOP
+266: /*-----------------------------------------------------------*/\r
+267: \r
+268: static void prvTaskExitError( void )\r
+269: {\r
+BFD07BBC 4FF1 ADDIU SP, SP, -32
+BFD07BBE CBE7 SW RA, 28(SP)
+BFD07BC0 CBC6 SW S8, 24(SP)
+BFD07BC2 0FDD MOVE S8, SP
+270: /* A function that implements a task must not exit or attempt to return to\r
+271: its caller as there is nothing to return to. If a task wants to exit it\r
+272: should instead call vTaskDelete( NULL ).\r
+273: \r
+274: Artificially force an assert() to be triggered if configASSERT() is\r
+275: defined, then stop here so application writers can catch the error. */\r
+276: configASSERT( uxSavedTaskStackPointer == 0UL );\r
+BFD07BC4 802CFC5C LW V0, -32724(GP)
+BFD07BC8 000940E2 BEQZC V0, 0xBFD07BDE
+BFD07BCC BFD141A2 LUI V0, 0xBFD1
+BFD07BCE 3082BFD1 LDC1 F30, 12418(S1)
+BFD07BD0 8AAC3082 ADDIU A0, V0, -30036
+BFD07BD2 8AAC SB A1, 12(V0)
+BFD07BD4 011430A0 ADDIU A1, ZERO, 276
+BFD07BD8 4B7E77E8 JALS vAssertCalled
+BFD07BDA 4B7E LW K1, 120(SP)
+BFD07BDC 0C00 NOP
+277: portDISABLE_INTERRUPTS();\r
+BFD07BDE 4DA677E8 JALS ulPortGetCP0Status
+BFD07BE0 4DA6 ADDIU T5, T5, 3
+BFD07BE2 0C00 NOP
+BFD07BE4 0010F85E SW V0, 16(S8)
+BFD07BE8 0010FC7E LW V1, 16(S8)
+BFD07BEC 000141A2 LUI V0, 0x1
+BFD07BF0 FC005042 ORI V0, V0, -1024
+BFD07BF2 4493FC00 LW ZERO, 17555(ZERO)
+BFD07BF4 4493 AND16 V0, V1
+BFD07BF6 50400042 SRL V0, V0, 10
+BFD07BF8 B0425040 ORI V0, ZERO, -20414
+BFD07BFA 0003B042 SLTIU V0, V0, 3
+BFD07BFE 001140E2 BEQZC V0, 0xBFD07C24
+BFD07C02 0010FC7E LW V1, 16(S8)
+BFD07C06 FFFE41A2 LUI V0, 0xFFFE
+BFD07C08 5042FFFE LW RA, 20546(S8)
+BFD07C0A 03FF5042 ORI V0, V0, 1023
+BFD07C0E 4493 AND16 V0, V1
+BFD07C10 0010F85E SW V0, 16(S8)
+BFD07C14 0010FC5E LW V0, 16(S8)
+BFD07C18 0C005042 ORI V0, V0, 3072
+BFD07C1A 0C00 NOP
+BFD07C1C 0C82 MOVE A0, V0
+BFD07C1E 4DB677E8 JALS vPortSetCP0Status
+BFD07C20 4DB6 ADDIU T5, T5, -5
+BFD07C22 0C00 NOP
+278: for( ;; );\r
+BFD07C24 CFFF B 0xBFD07C24
+BFD07C26 0C00 NOP
+279: }\r
+280: /*-----------------------------------------------------------*/\r
+281: \r
+282: /*\r
+283: * Setup a timer for a regular tick. This function uses peripheral timer 1.\r
+284: * The function is declared weak so an application writer can use a different\r
+285: * timer by redefining this implementation. If a different timer is used then\r
+286: * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to\r
+287: * ensure the RTOS provided tick interrupt handler is installed on the correct\r
+288: * vector number. When Timer 1 is used the vector number is defined as\r
+289: * _TIMER_1_VECTOR.\r
+290: */\r
+291: __attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )\r
+292: {\r
+BFD06284 4FF1 ADDIU SP, SP, -32
+BFD06286 CBE7 SW RA, 28(SP)
+BFD06288 CBC6 SW S8, 24(SP)
+BFD0628A 0FDD MOVE S8, SP
+293: /* MEC14xx RTOS Timer whose input clock is 32KHz */\r
+294: const uint32_t preload = ( 32768ul / ( configTICK_RATE_HZ ) );\r
+BFD0628C ED20 LI V0, 32
+BFD0628E 0010F85E SW V0, 16(S8)
+295: configASSERT( preload != 0UL );\r
+BFD06292 0010FC5E LW V0, 16(S8)
+BFD06296 000940A2 BNEZC V0, 0xBFD062AC
+BFD0629A BFD141A2 LUI V0, 0xBFD1
+BFD0629C 3082BFD1 LDC1 F30, 12418(S1)
+BFD0629E 8AAC3082 ADDIU A0, V0, -30036
+BFD062A0 8AAC SB A1, 12(V0)
+BFD062A2 012730A0 ADDIU A1, ZERO, 295
+BFD062A6 4B7E77E8 JALS vAssertCalled
+BFD062A8 4B7E LW K1, 120(SP)
+BFD062AA 0C00 NOP
+296: \r
+297: portMMCR_RTMR_CONTROL = 0ul;\r
+BFD062AC A00041A2 LUI V0, 0xA000
+BFD062B0 74085042 ORI V0, V0, 29704
+BFD062B2 E8207408 JALS 0xB811D040
+BFD062B4 E820 SW S0, 0(V0)
+298: portMMCR_RTMR_PRELOAD = preload;\r
+BFD062B6 A00041A2 LUI V0, 0xA000
+BFD062BA 74045042 ORI V0, V0, 29700
+BFD062BC FC7E7404 JALS 0xB809F8FC
+BFD062BE 0010FC7E LW V1, 16(S8)
+BFD062C2 E9A0 SW V1, 0(V0)
+299: \r
+300: portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );\r
+BFD062C4 BFFF41A2 LUI V0, 0xBFFF
+BFD062C6 5042BFFF LDC1 F31, 20546(RA)
+BFD062C8 C0F05042 ORI V0, V0, -16144
+BFD062CC ED90 LI V1, 16
+BFD062CE E9A0 SW V1, 0(V0)
+301: portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );\r
+BFD062D0 BFFF41A2 LUI V0, 0xBFFF
+BFD062D2 5042BFFF LDC1 F31, 20546(RA)
+BFD062D4 C3F05042 ORI V0, V0, -15376
+BFD062D8 BFFF41A3 LUI V1, 0xBFFF
+BFD062DA 5063BFFF LDC1 F31, 20579(RA)
+BFD062DC C3F05063 ORI V1, V1, -15376
+BFD062E0 6A30 LW A0, 0(V1)
+BFD062E2 FFF041A3 LUI V1, 0xFFF0
+BFD062E4 5063FFF0 LW RA, 20579(S0)
+BFD062E6 FFFF5063 ORI V1, V1, -1
+BFD062E8 449CFFFF LW RA, 17564(RA)
+BFD062EA 449C AND16 V1, A0
+BFD062EC E9A0 SW V1, 0(V0)
+302: portMMCR_JTVIC_GIRQ23_PRIA |= ( ( configKERNEL_INTERRUPT_PRIORITY ) << 16 );\r
+BFD062EE BFFF41A2 LUI V0, 0xBFFF
+BFD062F0 5042BFFF LDC1 F31, 20546(RA)
+BFD062F2 C3F05042 ORI V0, V0, -15376
+BFD062F6 BFFF41A3 LUI V1, 0xBFFF
+BFD062F8 5063BFFF LDC1 F31, 20579(RA)
+BFD062FA C3F05063 ORI V1, V1, -15376
+BFD062FE 69B0 LW V1, 0(V1)
+BFD06300 E9A0 SW V1, 0(V0)
+303: portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );\r
+BFD06302 BFFF41A2 LUI V0, 0xBFFF
+BFD06304 5042BFFF LDC1 F31, 20546(RA)
+BFD06306 C0F45042 ORI V0, V0, -16140
+BFD0630A ED90 LI V1, 16
+BFD0630C E9A0 SW V1, 0(V0)
+304: \r
+305: portMMCR_RTMR_CONTROL = 0x0Fu;\r
+BFD0630E A00041A2 LUI V0, 0xA000
+BFD06312 74085042 ORI V0, V0, 29704
+BFD06314 ED8F7408 JALS 0xB811DB1E
+BFD06316 ED8F LI V1, 15
+BFD06318 E9A0 SW V1, 0(V0)
+306: }\r
+BFD0631A 0FBE MOVE SP, S8
+BFD0631C 4BE7 LW RA, 28(SP)
+BFD0631E 4BC6 LW S8, 24(SP)
+BFD06320 4C11 ADDIU SP, SP, 32
+BFD06322 459F JR16 RA
+BFD06324 0C00 NOP
+307: /*-----------------------------------------------------------*/\r
+308: \r
+309: void vPortEndScheduler(void)\r
+310: {\r
+BFD097A8 4FF5 ADDIU SP, SP, -24
+BFD097AA CBE5 SW RA, 20(SP)
+BFD097AC CBC4 SW S8, 16(SP)
+BFD097AE 0FDD MOVE S8, SP
+311: /* Not implemented in ports where there is nothing to return to.\r
+312: Artificially force an assert. */\r
+313: configASSERT( uxInterruptNesting == 1000UL );\r
+BFD097B0 8014FC7C LW V1, -32748(GP)
+BFD097B4 03E83040 ADDIU V0, ZERO, 1000
+BFD097B8 000A9443 BEQ V1, V0, 0xBFD097D0
+BFD097BA 0C00000A SLL ZERO, T2, 1
+BFD097BC 0C00 NOP
+BFD097BE BFD141A2 LUI V0, 0xBFD1
+BFD097C0 3082BFD1 LDC1 F30, 12418(S1)
+BFD097C2 8AAC3082 ADDIU A0, V0, -30036
+BFD097C4 8AAC SB A1, 12(V0)
+BFD097C6 013930A0 ADDIU A1, ZERO, 313
+BFD097CA 4B7E77E8 JALS vAssertCalled
+BFD097CC 4B7E LW K1, 120(SP)
+BFD097CE 0C00 NOP
+314: }\r
+BFD097D0 0FBE MOVE SP, S8
+BFD097D2 4BE5 LW RA, 20(SP)
+BFD097D4 4BC4 LW S8, 16(SP)
+BFD097D6 4C0D ADDIU SP, SP, 24
+BFD097D8 459F JR16 RA
+BFD097DA 0C00 NOP
+315: /*-----------------------------------------------------------*/\r
+316: \r
+317: BaseType_t xPortStartScheduler( void )\r
+318: {\r
+BFD06898 4FF5 ADDIU SP, SP, -24
+BFD0689A CBE5 SW RA, 20(SP)
+BFD0689C CBC4 SW S8, 16(SP)
+BFD0689E 0FDD MOVE S8, SP
+319: extern void vPortStartFirstTask( void );\r
+320: extern void *pxCurrentTCB;\r
+321: \r
+322: #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )\r
+323: {\r
+324: /* Fill the ISR stack to make it easy to asses how much is being used. */\r
+325: memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );\r
+BFD068A0 BFD241A2 LUI V0, 0xBFD2
+BFD068A2 3082BFD2 LDC1 F30, 12418(S2)
+BFD068A4 AD683082 ADDIU A0, V0, -21144
+BFD068A6 AD68 BNEZ V0, 0xBFD06978
+BFD068A8 00EE30A0 ADDIU A1, ZERO, 238
+BFD068AA 30C000EE ROTR A3, T6, 6
+BFD068AC 0BE030C0 ADDIU A2, ZERO, 3040
+BFD068AE 0BE0 LBU A3, 0(A2)
+BFD068B0 36F677E8 JALS 0xBFD06DEC
+BFD068B2 0C0036F6 LHU S7, 3072(S6)
+BFD068B4 0C00 NOP
+326: }\r
+327: #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */\r
+328: \r
+329: /* Clear the software interrupt flag. */\r
+330: portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);\r
+BFD068B6 BFFF41A2 LUI V0, 0xBFFF
+BFD068B8 5042BFFF LDC1 F31, 20546(RA)
+BFD068BA C1005042 ORI V0, V0, -16128
+BFD068BE ED82 LI V1, 2
+BFD068C0 E9A0 SW V1, 0(V0)
+331: \r
+332: /* Set software timer priority.\r
+333: Each GIRQn has one nibble containing its priority */\r
+334: portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);\r
+BFD068C2 BFFF41A2 LUI V0, 0xBFFF
+BFD068C4 5042BFFF LDC1 F31, 20546(RA)
+BFD068C6 C4005042 ORI V0, V0, -15360
+BFD068CA BFFF41A3 LUI V1, 0xBFFF
+BFD068CC 5063BFFF LDC1 F31, 20579(RA)
+BFD068CE C4005063 ORI V1, V1, -15360
+BFD068D2 6A30 LW A0, 0(V1)
+BFD068D4 FF0F3060 ADDIU V1, ZERO, -241
+BFD068D6 449CFF0F LW T8, 17564(T7)
+BFD068D8 449C AND16 V1, A0
+BFD068DA E9A0 SW V1, 0(V0)
+335: portMMCR_JTVIC_GIRQ24_PRIA |= ( configKERNEL_INTERRUPT_PRIORITY << 4 );\r
+BFD068DC BFFF41A2 LUI V0, 0xBFFF
+BFD068DE 5042BFFF LDC1 F31, 20546(RA)
+BFD068E0 C4005042 ORI V0, V0, -15360
+BFD068E4 BFFF41A3 LUI V1, 0xBFFF
+BFD068E6 5063BFFF LDC1 F31, 20579(RA)
+BFD068E8 C4005063 ORI V1, V1, -15360
+BFD068EC 69B0 LW V1, 0(V1)
+BFD068EE E9A0 SW V1, 0(V0)
+336: \r
+337: /* Enable software interrupt. */\r
+338: portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );\r
+BFD068F0 BFFF41A2 LUI V0, 0xBFFF
+BFD068F2 5042BFFF LDC1 F31, 20546(RA)
+BFD068F4 C1045042 ORI V0, V0, -16124
+BFD068F8 ED82 LI V1, 2
+BFD068FA E9A0 SW V1, 0(V0)
+339: \r
+340: /* Setup the timer to generate the tick. Interrupts will have been\r
+341: disabled by the time we get here. */\r
+342: vApplicationSetupTickTimerInterrupt();\r
+BFD068FC 314277E8 JALS vApplicationSetupTickTimerInterrupt
+BFD068FE 0C003142 ADDIU T2, V0, 3072
+BFD06900 0C00 NOP
+343: \r
+344: /* Kick off the highest priority task that has been created so far.\r
+345: Its stack location is loaded into uxSavedTaskStackPointer. */\r
+346: uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;\r
+BFD06902 8030FC5C LW V0, -32720(GP)
+BFD06906 6920 LW V0, 0(V0)
+BFD06908 802CF85C SW V0, -32724(GP)
+347: vPortStartFirstTask();\r
+BFD0690C 055A77E8 JALS 0xBFD00AB4
+BFD0690E 055A ADDU V0, A1, A1
+BFD06910 0C00 NOP
+348: \r
+349: /* Should never get here as the tasks will now be executing! Call the task\r
+350: exit error function to prevent compiler warnings about a static function\r
+351: not being called in the case that the application writer overrides this\r
+352: functionality by defining configTASK_RETURN_ADDRESS. */\r
+353: prvTaskExitError();\r
+BFD06912 3DDE77E8 JALS prvTaskExitError
+BFD06914 0C003DDE LH T6, 3072(S8)
+BFD06916 0C00 NOP
+354: \r
+355: return pdFALSE;\r
+BFD06918 0C40 MOVE V0, ZERO
+356: }\r
+BFD0691A 0FBE MOVE SP, S8
+BFD0691C 4BE5 LW RA, 20(SP)
+BFD0691E 4BC4 LW S8, 16(SP)
+BFD06920 4C0D ADDIU SP, SP, 24
+BFD06922 459F JR16 RA
+BFD06924 0C00 NOP
+357: /*-----------------------------------------------------------*/\r
+358: \r
+359: void vPortIncrementTick( void )\r
+360: {\r
+BFD069B8 4FF1 ADDIU SP, SP, -32
+BFD069BA CBE7 SW RA, 28(SP)
+BFD069BC CBC6 SW S8, 24(SP)
+BFD069BE 0FDD MOVE S8, SP
+361: UBaseType_t uxSavedStatus;\r
+362: uint32_t ulCause;\r
+363: \r
+364: uxSavedStatus = uxPortSetInterruptMaskFromISR();\r
+BFD069C0 475E77E8 JALS uxPortSetInterruptMaskFromISR
+BFD069C4 0C00 NOP
+BFD069C6 0010F85E SW V0, 16(S8)
+365: {\r
+366: if( xTaskIncrementTick() != pdFALSE )\r
+BFD069CA 104077E8 JALS xTaskIncrementTick
+BFD069CC 0C001040 ADDI V0, ZERO, 3072
+BFD069CE 0C00 NOP
+BFD069D0 001040E2 BEQZC V0, 0xBFD069F4
+367: {\r
+368: /* Pend a context switch. */\r
+369: ulCause = ulPortGetCP0Cause();\r
+BFD069D4 4DC677E8 JALS ulPortGetCP0Cause
+BFD069D6 4DC6 ADDIU T6, T6, 3
+BFD069D8 0C00 NOP
+BFD069DA 0014F85E SW V0, 20(S8)
+370: ulCause |= ( 1ul << 8UL );\r
+BFD069DE 0014FC5E LW V0, 20(S8)
+BFD069E2 01005042 ORI V0, V0, 256
+BFD069E6 0014F85E SW V0, 20(S8)
+371: vPortSetCP0Cause( ulCause );\r
+BFD069EA 0014FC9E LW A0, 20(S8)
+BFD069EE 4DD677E8 JALS vPortSetCP0Cause
+BFD069F0 4DD6 ADDIU T6, T6, -5
+BFD069F2 0C00 NOP
+372: }\r
+373: }\r
+374: vPortClearInterruptMaskFromISR( uxSavedStatus );\r
+BFD069F4 0010FC9E LW A0, 16(S8)
+BFD069F8 4D5E77E8 JALS vPortClearInterruptMaskFromISR
+BFD069FA 4D5E ADDIU T2, T2, -1
+BFD069FC 0C00 NOP
+375: \r
+376: /* Look for the ISR stack getting near or past its limit. */\r
+377: portCHECK_ISR_STACK();\r
+BFD069FE BFD241A2 LUI V0, 0xBFD2
+BFD06A00 3082BFD2 LDC1 F30, 12418(S2)
+BFD06A02 AD683082 ADDIU A0, V0, -21144
+BFD06A04 AD68 BNEZ V0, 0xBFD06AD6
+BFD06A06 BFD141A2 LUI V0, 0xBFD1
+BFD06A08 30A2BFD1 LDC1 F30, 12450(S1)
+BFD06A0A 8A9430A2 ADDIU A1, V0, -30060
+BFD06A0C 8A94 SB A1, 4(S1)
+BFD06A0E EF14 LI A2, 20
+BFD06A10 3DA677E8 JALS 0xBFD07B4C
+BFD06A12 0C003DA6 LH T5, 3072(A2)
+BFD06A14 0C00 NOP
+BFD06A16 000940E2 BEQZC V0, 0xBFD06A2C
+BFD06A1A BFD141A2 LUI V0, 0xBFD1
+BFD06A1C 3082BFD1 LDC1 F30, 12418(S1)
+BFD06A1E 8AAC3082 ADDIU A0, V0, -30036
+BFD06A20 8AAC SB A1, 12(V0)
+BFD06A22 017930A0 ADDIU A1, ZERO, 377
+BFD06A26 4B7E77E8 JALS vAssertCalled
+BFD06A28 4B7E LW K1, 120(SP)
+BFD06A2A 0C00 NOP
+378: \r
+379: /* Clear timer interrupt. */\r
+380: configCLEAR_TICK_TIMER_INTERRUPT();\r
+BFD06A2C BFFF41A2 LUI V0, 0xBFFF
+BFD06A2E 5042BFFF LDC1 F31, 20546(RA)
+BFD06A30 C0F05042 ORI V0, V0, -16144
+BFD06A34 ED90 LI V1, 16
+BFD06A36 E9A0 SW V1, 0(V0)
+381: }\r
+BFD06A38 0FBE MOVE SP, S8
+BFD06A3A 4BE7 LW RA, 28(SP)
+BFD06A3C 4BC6 LW S8, 24(SP)
+BFD06A3E 4C11 ADDIU SP, SP, 32
+BFD06A40 459F JR16 RA
+BFD06A42 0C00 NOP
+382: /*-----------------------------------------------------------*/\r
+383: \r
+384: UBaseType_t uxPortSetInterruptMaskFromISR( void )\r
+385: {\r
+BFD08EBC 4FF1 ADDIU SP, SP, -32
+BFD08EBE CBE7 SW RA, 28(SP)
+BFD08EC0 CBC6 SW S8, 24(SP)
+BFD08EC2 0FDD MOVE S8, SP
+386: UBaseType_t uxSavedStatusRegister;\r
+387: \r
+388: prvDisableInterrupt();\r
+BFD08EC4 4D4C77E8 JALS prvDisableInterrupt
+BFD08EC6 4D4C ADDIU T2, T2, 6
+BFD08EC8 0C00 NOP
+389: uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;\r
+BFD08ECA 4DA677E8 JALS ulPortGetCP0Status
+BFD08ECC 4DA6 ADDIU T5, T5, 3
+BFD08ECE 0C00 NOP
+BFD08ED0 00015042 ORI V0, V0, 1
+BFD08ED4 0010F85E SW V0, 16(S8)
+390: \r
+391: /* This clears the IPL bits, then sets them to\r
+392: configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called\r
+393: from an interrupt that has a priority above\r
+394: configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action\r
+395: can only result in the IPL being unchanged or raised, and therefore never\r
+396: lowered. */\r
+397: vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );\r
+BFD08ED8 0010FC7E LW V1, 16(S8)
+BFD08EDC FFFE41A2 LUI V0, 0xFFFE
+BFD08EDE 5042FFFE LW RA, 20546(S8)
+BFD08EE0 03FF5042 ORI V0, V0, 1023
+BFD08EE4 4493 AND16 V0, V1
+BFD08EE6 0C005042 ORI V0, V0, 3072
+BFD08EE8 0C00 NOP
+BFD08EEA 0C82 MOVE A0, V0
+BFD08EEC 4DB677E8 JALS vPortSetCP0Status
+BFD08EEE 4DB6 ADDIU T5, T5, -5
+BFD08EF0 0C00 NOP
+398: \r
+399: return uxSavedStatusRegister;\r
+BFD08EF2 0010FC5E LW V0, 16(S8)
+400: }\r
+BFD08EF6 0FBE MOVE SP, S8
+BFD08EF8 4BE7 LW RA, 28(SP)
+BFD08EFA 4BC6 LW S8, 24(SP)
+BFD08EFC 4C11 ADDIU SP, SP, 32
+BFD08EFE 459F JR16 RA
+BFD08F00 0C00 NOP
+401: /*-----------------------------------------------------------*/\r
+402: \r
+403: void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )\r
+404: {\r
+BFD09ABC 4FF5 ADDIU SP, SP, -24
+BFD09ABE CBE5 SW RA, 20(SP)
+BFD09AC0 CBC4 SW S8, 16(SP)
+BFD09AC2 0FDD MOVE S8, SP
+BFD09AC4 0018F89E SW A0, 24(S8)
+405: vPortSetCP0Status( uxSavedStatusRegister );\r
+BFD09AC8 0018FC9E LW A0, 24(S8)
+BFD09ACC 4DB677E8 JALS vPortSetCP0Status
+BFD09ACE 4DB6 ADDIU T5, T5, -5
+BFD09AD0 0C00 NOP
+406: }\r
+BFD09AD2 0FBE MOVE SP, S8
+BFD09AD4 4BE5 LW RA, 20(SP)
+BFD09AD6 4BC4 LW S8, 16(SP)
+BFD09AD8 4C0D ADDIU SP, SP, 24
+BFD09ADA 459F JR16 RA
+BFD09ADC 0C00 NOP
+407: /*-----------------------------------------------------------*/\r
+408: \r
+409: \r
+410: \r
+411: \r
+412: \r
+--- c:/e/dev/freertos/workingcopy/freertos/source/portable/memmang/heap_2.c ---------------------------
+1: /*\r
+2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+3: All rights reserved\r
+4: \r
+5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+6: \r
+7: This file is part of the FreeRTOS distribution.\r
+8: \r
+9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
+10: the terms of the GNU General Public License (version 2) as published by the\r
+11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+12: \r
+13: ***************************************************************************\r
+14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+15: >>! distribute a combined work that includes FreeRTOS without being !<<\r
+16: >>! obliged to provide the source code for proprietary components !<<\r
+17: >>! outside of the FreeRTOS kernel. !<<\r
+18: ***************************************************************************\r
+19: \r
+20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+22: FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+23: link: http://www.freertos.org/a00114.html\r
+24: \r
+25: ***************************************************************************\r
+26: * *\r
+27: * FreeRTOS provides completely free yet professionally developed, *\r
+28: * robust, strictly quality controlled, supported, and cross *\r
+29: * platform software that is more than just the market leader, it *\r
+30: * is the industry's de facto standard. *\r
+31: * *\r
+32: * Help yourself get started quickly while simultaneously helping *\r
+33: * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+34: * tutorial book, reference manual, or both: *\r
+35: * http://www.FreeRTOS.org/Documentation *\r
+36: * *\r
+37: ***************************************************************************\r
+38: \r
+39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+40: the FAQ page "My application does not run, what could be wrong?". Have you\r
+41: defined configASSERT()?\r
+42: \r
+43: http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+44: embedded software for free we request you assist our global community by\r
+45: participating in the support forum.\r
+46: \r
+47: http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+48: be as productive as possible as early as possible. Now you can receive\r
+49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+50: Ltd, and the world's leading authority on the world's leading RTOS.\r
+51: \r
+52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+54: compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+55: \r
+56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+58: \r
+59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+61: licenses offer ticketed support, indemnification and commercial middleware.\r
+62: \r
+63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+64: engineered and independently SIL3 certified version for use in safety and\r
+65: mission critical applications that require provable dependability.\r
+66: \r
+67: 1 tab == 4 spaces!\r
+68: */\r
+69: \r
+70: /*\r
+71: * A sample implementation of pvPortMalloc() and vPortFree() that permits\r
+72: * allocated blocks to be freed, but does not combine adjacent free blocks\r
+73: * into a single larger block (and so will fragment memory). See heap_4.c for\r
+74: * an equivalent that does combine adjacent blocks into single larger blocks.\r
+75: *\r
+76: * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the\r
+77: * memory management pages of http://www.FreeRTOS.org for more information.\r
+78: */\r
+79: #include <stdlib.h>\r
+80: \r
+81: /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+82: all the API functions to use the MPU wrappers. That should only be done when\r
+83: task.h is included from an application file. */\r
+84: #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+85: \r
+86: #include "FreeRTOS.h"\r
+87: #include "task.h"\r
+88: \r
+89: #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+90: \r
+91: /* A few bytes might be lost to byte aligning the heap start address. */\r
+92: #define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )\r
+93: \r
+94: /*\r
+95: * Initialises the heap structures before their first use.\r
+96: */\r
+97: static void prvHeapInit( void );\r
+98: \r
+99: /* Allocate the memory for the heap. */\r
+100: static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\r
+101: \r
+102: /* Define the linked list structure. This is used to link free blocks in order\r
+103: of their size. */\r
+104: typedef struct A_BLOCK_LINK\r
+105: {\r
+106: struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */\r
+107: size_t xBlockSize; /*<< The size of the free block. */\r
+108: } BlockLink_t;\r
+109: \r
+110: \r
+111: static const uint16_t heapSTRUCT_SIZE = ( ( sizeof ( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );\r
+112: #define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )\r
+113: \r
+114: /* Create a couple of list links to mark the start and end of the list. */\r
+115: static BlockLink_t xStart, xEnd;\r
+116: \r
+117: /* Keeps track of the number of free bytes remaining, but says nothing about\r
+118: fragmentation. */\r
+119: static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;\r
+120: \r
+121: /* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */\r
+122: \r
+123: /*\r
+124: * Insert a block into the list of free blocks - which is ordered by size of\r
+125: * the block. Small blocks at the start of the list and large blocks at the end\r
+126: * of the list.\r
+127: */\r
+128: #define prvInsertBlockIntoFreeList( pxBlockToInsert ) \\r
+129: { \\r
+130: BlockLink_t *pxIterator; \\r
+131: size_t xBlockSize; \\r
+132: \\r
+133: xBlockSize = pxBlockToInsert->xBlockSize; \\r
+134: \\r
+135: /* Iterate through the list until a block is found that has a larger size */ \\r
+136: /* than the block we are inserting. */ \\r
+137: for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \\r
+138: { \\r
+139: /* There is nothing to do here - just iterate to the correct position. */ \\r
+140: } \\r
+141: \\r
+142: /* Update the list to include the block being inserted in the correct */ \\r
+143: /* position. */ \\r
+144: pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \\r
+145: pxIterator->pxNextFreeBlock = pxBlockToInsert; \\r
+146: }\r
+147: /*-----------------------------------------------------------*/\r
+148: \r
+149: void *pvPortMalloc( size_t xWantedSize )\r
+150: {\r
+BFD0222C 4FE9 ADDIU SP, SP, -48
+BFD0222E CBEB SW RA, 44(SP)
+BFD02230 CBCA SW S8, 40(SP)
+BFD02232 0FDD MOVE S8, SP
+BFD02234 0030F89E SW A0, 48(S8)
+151: BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
+152: static BaseType_t xHeapHasBeenInitialised = pdFALSE;\r
+153: void *pvReturn = NULL;\r
+BFD02238 0018F81E SW ZERO, 24(S8)
+154: \r
+155: vTaskSuspendAll();\r
+BFD0223C 4EF477E8 JALS vTaskSuspendAll
+BFD0223E 4EF4 ADDIU S7, S7, -6
+BFD02240 0C00 NOP
+156: {\r
+157: /* If this is the first call to malloc then the heap will require\r
+158: initialisation to setup the list of free blocks. */\r
+159: if( xHeapHasBeenInitialised == pdFALSE )\r
+BFD02242 8028FC5C LW V0, -32728(GP)
+BFD02246 000640A2 BNEZC V0, 0xBFD02256
+160: {\r
+161: prvHeapInit();\r
+BFD0224A 425077E8 JALS prvHeapInit
+BFD0224E 0C00 NOP
+162: xHeapHasBeenInitialised = pdTRUE;\r
+BFD02250 ED01 LI V0, 1
+BFD02252 8028F85C SW V0, -32728(GP)
+163: }\r
+164: \r
+165: /* The wanted size is increased so it can contain a BlockLink_t\r
+166: structure in addition to the requested amount of bytes. */\r
+167: if( xWantedSize > 0 )\r
+BFD02256 0030FC5E LW V0, 48(S8)
+BFD0225A 001640E2 BEQZC V0, 0xBFD0228A
+168: {\r
+169: xWantedSize += heapSTRUCT_SIZE;\r
+BFD0225E BFD141A2 LUI V0, 0xBFD1
+BFD02260 3442BFD1 LDC1 F30, 13378(S1)
+BFD02262 9F2C3442 LHU V0, -24788(V0)
+BFD02264 FC7E9F2C LWC1 F25, -898(T4)
+BFD02266 0030FC7E LW V1, 48(S8)
+BFD0226A 0526 ADDU V0, V1, V0
+BFD0226C 0030F85E SW V0, 48(S8)
+170: \r
+171: /* Ensure that blocks are always aligned to the required number of bytes. */\r
+172: if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0 )\r
+BFD02270 0030FC5E LW V0, 48(S8)
+BFD02274 2D25 ANDI V0, V0, 0x7
+BFD02276 000840E2 BEQZC V0, 0xBFD0228A
+173: {\r
+174: /* Byte alignment required. */\r
+175: xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );\r
+BFD0227A 0030FC7E LW V1, 48(S8)
+BFD0227C 30400030 SRL AT, S0, 6
+BFD0227E FFF83040 ADDIU V0, ZERO, -8
+BFD02280 4493FFF8 LW RA, 17555(T8)
+BFD02282 4493 AND16 V0, V1
+BFD02284 6D24 ADDIU V0, V0, 8
+BFD02286 0030F85E SW V0, 48(S8)
+176: }\r
+177: }\r
+178: \r
+179: if( ( xWantedSize > 0 ) && ( xWantedSize < configADJUSTED_HEAP_SIZE ) )\r
+BFD0228A 0030FC5E LW V0, 48(S8)
+BFD0228E 008F40E2 BEQZC V0, 0xBFD023B0
+BFD02292 0030FC5E LW V0, 48(S8)
+BFD02296 1FF8B042 SLTIU V0, V0, 8184
+BFD02298 40E21FF8 LB RA, 16610(T8)
+BFD0229A 008940E2 BEQZC V0, 0xBFD023B0
+180: {\r
+181: /* Blocks are stored in byte order - traverse the list from the start\r
+182: (smallest) block until one of adequate size is found. */\r
+183: pxPreviousBlock = &xStart;\r
+BFD0229E 8018305C ADDIU V0, GP, -32744
+BFD022A2 0014F85E SW V0, 20(S8)
+184: pxBlock = xStart.pxNextFreeBlock;\r
+BFD022A6 8018FC5C LW V0, -32744(GP)
+BFD022AA 0010F85E SW V0, 16(S8)
+185: while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
+BFD022AE CC0A B 0xBFD022C4
+BFD022B0 0C00 NOP
+BFD022C4 0010FC5E LW V0, 16(S8)
+BFD022C8 69A1 LW V1, 4(V0)
+BFD022CA 0030FC5E LW V0, 48(S8)
+BFD022CE 13900043 SLTU V0, V1, V0
+BFD022D0 40E21390 ADDI GP, S0, 16610
+BFD022D2 000540E2 BEQZC V0, 0xBFD022E0
+BFD022D6 0010FC5E LW V0, 16(S8)
+BFD022DA 6920 LW V0, 0(V0)
+BFD022DC FFE940A2 BNEZC V0, 0xBFD022B2
+BFD022DE FC7EFFE9 LW RA, -898(T1)
+186: {\r
+187: pxPreviousBlock = pxBlock;\r
+BFD022B2 0010FC5E LW V0, 16(S8)
+BFD022B6 0014F85E SW V0, 20(S8)
+188: pxBlock = pxBlock->pxNextFreeBlock;\r
+BFD022BA 0010FC5E LW V0, 16(S8)
+BFD022BE 6920 LW V0, 0(V0)
+BFD022C0 0010F85E SW V0, 16(S8)
+189: }\r
+190: \r
+191: /* If we found the end marker then a block of adequate size was not found. */\r
+192: if( pxBlock != &xEnd )\r
+BFD022E0 0010FC7E LW V1, 16(S8)
+BFD022E4 8020305C ADDIU V0, GP, -32736
+BFD022E8 00629443 BEQ V1, V0, 0xBFD023B0
+BFD022EA 0C000062 SLL V1, V0, 1
+BFD022EC 0C00 NOP
+193: {\r
+194: /* Return the memory space - jumping over the BlockLink_t structure\r
+195: at its start. */\r
+196: pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );\r
+BFD022EE 0014FC5E LW V0, 20(S8)
+BFD022F2 69A0 LW V1, 0(V0)
+BFD022F4 BFD141A2 LUI V0, 0xBFD1
+BFD022F6 3442BFD1 LDC1 F30, 13378(S1)
+BFD022F8 9F2C3442 LHU V0, -24788(V0)
+BFD022FA 05269F2C LWC1 F25, 1318(T4)
+BFD022FC 0526 ADDU V0, V1, V0
+BFD022FE 0018F85E SW V0, 24(S8)
+197: \r
+198: /* This block is being returned for use so must be taken out of the\r
+199: list of free blocks. */\r
+200: pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
+BFD02302 0010FC5E LW V0, 16(S8)
+BFD02306 69A0 LW V1, 0(V0)
+BFD02308 0014FC5E LW V0, 20(S8)
+BFD0230C E9A0 SW V1, 0(V0)
+201: \r
+202: /* If the block is larger than required it can be split into two. */\r
+203: if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )\r
+BFD0230E 0010FC5E LW V0, 16(S8)
+BFD02312 69A1 LW V1, 4(V0)
+BFD02314 0030FC5E LW V0, 48(S8)
+BFD02318 05A7 SUBU V1, V1, V0
+BFD0231A BFD141A2 LUI V0, 0xBFD1
+BFD0231C 3442BFD1 LDC1 F30, 13378(S1)
+BFD0231E 9F2C3442 LHU V0, -24788(V0)
+BFD02320 25229F2C LWC1 F25, 9506(T4)
+BFD02322 2522 SLL V0, V0, 1
+BFD02324 13900062 SLTU V0, V0, V1
+BFD02326 40E21390 ADDI GP, S0, 16610
+BFD02328 003A40E2 BEQZC V0, 0xBFD023A0
+204: {\r
+205: /* This block is to be split into two. Create a new block\r
+206: following the number of bytes requested. The void cast is\r
+207: used to prevent byte alignment warnings from the compiler. */\r
+208: pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
+BFD0232C 0010FC7E LW V1, 16(S8)
+BFD02330 0030FC5E LW V0, 48(S8)
+BFD02334 0526 ADDU V0, V1, V0
+BFD02336 0020F85E SW V0, 32(S8)
+209: \r
+210: /* Calculate the sizes of two blocks split from the single\r
+211: block. */\r
+212: pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
+BFD0233A 0010FC5E LW V0, 16(S8)
+BFD0233E 69A1 LW V1, 4(V0)
+BFD02340 0030FC5E LW V0, 48(S8)
+BFD02344 05A7 SUBU V1, V1, V0
+BFD02346 0020FC5E LW V0, 32(S8)
+BFD0234A E9A1 SW V1, 4(V0)
+213: pxBlock->xBlockSize = xWantedSize;\r
+BFD0234C 0010FC5E LW V0, 16(S8)
+BFD02350 0030FC7E LW V1, 48(S8)
+BFD02354 E9A1 SW V1, 4(V0)
+214: \r
+215: /* Insert the new block into the list of free blocks. */\r
+216: prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );\r
+BFD02356 0020FC5E LW V0, 32(S8)
+BFD0235A 6921 LW V0, 4(V0)
+BFD0235C 0024F85E SW V0, 36(S8)
+BFD02360 8018305C ADDIU V0, GP, -32744
+BFD02364 001CF85E SW V0, 28(S8)
+BFD02368 CC06 B 0xBFD02376
+BFD0236A 0C00 NOP
+BFD0236C 001CFC5E LW V0, 28(S8)
+BFD02370 6920 LW V0, 0(V0)
+BFD02372 001CF85E SW V0, 28(S8)
+BFD02376 001CFC5E LW V0, 28(S8)
+BFD0237A 6920 LW V0, 0(V0)
+BFD0237C 69A1 LW V1, 4(V0)
+BFD0237E 0024FC5E LW V0, 36(S8)
+BFD02382 13900043 SLTU V0, V1, V0
+BFD02384 40A21390 ADDI GP, S0, 16546
+BFD02386 FFF140A2 BNEZC V0, 0xBFD0236C
+BFD02388 FC5EFFF1 LW RA, -930(S1)
+BFD0238A 001CFC5E LW V0, 28(S8)
+BFD0238E 69A0 LW V1, 0(V0)
+BFD02390 0020FC5E LW V0, 32(S8)
+BFD02394 E9A0 SW V1, 0(V0)
+BFD02396 001CFC5E LW V0, 28(S8)
+BFD0239A 0020FC7E LW V1, 32(S8)
+BFD0239E E9A0 SW V1, 0(V0)
+217: }\r
+218: \r
+219: xFreeBytesRemaining -= pxBlock->xBlockSize;\r
+BFD023A0 8010FC7C LW V1, -32752(GP)
+BFD023A4 0010FC5E LW V0, 16(S8)
+BFD023A8 6921 LW V0, 4(V0)
+BFD023AA 0527 SUBU V0, V1, V0
+BFD023AC 8010F85C SW V0, -32752(GP)
+220: }\r
+221: }\r
+222: \r
+223: traceMALLOC( pvReturn, xWantedSize );\r
+224: }\r
+225: ( void ) xTaskResumeAll();\r
+BFD023B0 158E77E8 JALS xTaskResumeAll
+BFD023B2 0C00158E LBU T4, 3072(T6)
+BFD023B4 0C00 NOP
+226: \r
+227: #if( configUSE_MALLOC_FAILED_HOOK == 1 )\r
+228: {\r
+229: if( pvReturn == NULL )\r
+BFD023B6 0018FC5E LW V0, 24(S8)
+BFD023BA 000340A2 BNEZC V0, 0xBFD023C4
+230: {\r
+231: extern void vApplicationMallocFailedHook( void );\r
+232: vApplicationMallocFailedHook();\r
+BFD023BE 448077E8 JALS vApplicationMallocFailedHook
+BFD023C0 4480 AND16 S0, S0
+BFD023C2 0C00 NOP
+233: }\r
+234: }\r
+235: #endif\r
+236: \r
+237: return pvReturn;\r
+BFD023C4 0018FC5E LW V0, 24(S8)
+238: }\r
+BFD023C8 0FBE MOVE SP, S8
+BFD023CA 4BEB LW RA, 44(SP)
+BFD023CC 4BCA LW S8, 40(SP)
+BFD023CE 4C19 ADDIU SP, SP, 48
+BFD023D0 459F JR16 RA
+BFD023D2 0C00 NOP
+239: /*-----------------------------------------------------------*/\r
+240: \r
+241: void vPortFree( void *pv )\r
+242: {\r
+BFD05FD4 4FED ADDIU SP, SP, -40
+BFD05FD6 CBE9 SW RA, 36(SP)
+BFD05FD8 CBC8 SW S8, 32(SP)
+BFD05FDA 0FDD MOVE S8, SP
+BFD05FDC 0028F89E SW A0, 40(S8)
+243: uint8_t *puc = ( uint8_t * ) pv;\r
+BFD05FE0 0028FC5E LW V0, 40(S8)
+BFD05FE4 0014F85E SW V0, 20(S8)
+244: BlockLink_t *pxLink;\r
+245: \r
+246: if( pv != NULL )\r
+BFD05FE8 0028FC5E LW V0, 40(S8)
+BFD05FEC 004240E2 BEQZC V0, 0xBFD06074
+247: {\r
+248: /* The memory being freed will have an BlockLink_t structure immediately\r
+249: before it. */\r
+250: puc -= heapSTRUCT_SIZE;\r
+BFD05FF0 BFD141A2 LUI V0, 0xBFD1
+BFD05FF2 3442BFD1 LDC1 F30, 13378(S1)
+BFD05FF4 9F2C3442 LHU V0, -24788(V0)
+BFD05FF6 00409F2C LWC1 F25, 64(T4)
+BFD05FF8 11D00040 SUBU V0, ZERO, V0
+BFD05FFA FC7E11D0 ADDI T6, S0, -898
+BFD05FFC 0014FC7E LW V1, 20(S8)
+BFD06000 0526 ADDU V0, V1, V0
+BFD06002 0014F85E SW V0, 20(S8)
+251: \r
+252: /* This unexpected casting is to keep some compilers from issuing\r
+253: byte alignment warnings. */\r
+254: pxLink = ( void * ) puc;\r
+BFD06006 0014FC5E LW V0, 20(S8)
+BFD0600A 0018F85E SW V0, 24(S8)
+255: \r
+256: vTaskSuspendAll();\r
+BFD0600E 4EF477E8 JALS vTaskSuspendAll
+BFD06010 4EF4 ADDIU S7, S7, -6
+BFD06012 0C00 NOP
+257: {\r
+258: /* Add this block to the list of free blocks. */\r
+259: prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
+BFD06014 0018FC5E LW V0, 24(S8)
+BFD06018 6921 LW V0, 4(V0)
+BFD0601A 001CF85E SW V0, 28(S8)
+BFD0601E 8018305C ADDIU V0, GP, -32744
+BFD06022 0010F85E SW V0, 16(S8)
+BFD06026 CC06 B 0xBFD06034
+BFD06028 0C00 NOP
+BFD0602A 0010FC5E LW V0, 16(S8)
+BFD0602E 6920 LW V0, 0(V0)
+BFD06030 0010F85E SW V0, 16(S8)
+BFD06034 0010FC5E LW V0, 16(S8)
+BFD06038 6920 LW V0, 0(V0)
+BFD0603A 69A1 LW V1, 4(V0)
+BFD0603C 001CFC5E LW V0, 28(S8)
+BFD06040 13900043 SLTU V0, V1, V0
+BFD06042 40A21390 ADDI GP, S0, 16546
+BFD06044 FFF140A2 BNEZC V0, 0xBFD0602A
+BFD06046 FC5EFFF1 LW RA, -930(S1)
+BFD06048 0010FC5E LW V0, 16(S8)
+BFD0604C 69A0 LW V1, 0(V0)
+BFD0604E 0018FC5E LW V0, 24(S8)
+BFD06052 E9A0 SW V1, 0(V0)
+BFD06054 0010FC5E LW V0, 16(S8)
+BFD06058 0018FC7E LW V1, 24(S8)
+BFD0605C E9A0 SW V1, 0(V0)
+260: xFreeBytesRemaining += pxLink->xBlockSize;\r
+BFD0605E 0018FC5E LW V0, 24(S8)
+BFD06062 69A1 LW V1, 4(V0)
+BFD06064 8010FC5C LW V0, -32752(GP)
+BFD06068 0526 ADDU V0, V1, V0
+BFD0606A 8010F85C SW V0, -32752(GP)
+261: traceFREE( pv, pxLink->xBlockSize );\r
+262: }\r
+263: ( void ) xTaskResumeAll();\r
+BFD0606E 158E77E8 JALS xTaskResumeAll
+BFD06070 0C00158E LBU T4, 3072(T6)
+BFD06072 0C00 NOP
+264: }\r
+265: }\r
+BFD06074 0FBE MOVE SP, S8
+BFD06076 4BE9 LW RA, 36(SP)
+BFD06078 4BC8 LW S8, 32(SP)
+BFD0607A 4C15 ADDIU SP, SP, 40
+BFD0607C 459F JR16 RA
+BFD0607E 0C00 NOP
+266: /*-----------------------------------------------------------*/\r
+267: \r
+268: size_t xPortGetFreeHeapSize( void )\r
+269: {\r
+BFD09E84 4FB0 ADDIU SP, SP, -8
+BFD09E86 CBC1 SW S8, 4(SP)
+BFD09E88 0FDD MOVE S8, SP
+270: return xFreeBytesRemaining;\r
+BFD09E8A 8010FC5C LW V0, -32752(GP)
+271: }\r
+BFD09E8E 0FBE MOVE SP, S8
+BFD09E90 4BC1 LW S8, 4(SP)
+BFD09E92 4C05 ADDIU SP, SP, 8
+BFD09E94 459F JR16 RA
+BFD09E96 0C00 NOP
+272: /*-----------------------------------------------------------*/\r
+273: \r
+274: void vPortInitialiseBlocks( void )\r
+275: {\r
+BFD09ED4 4FB0 ADDIU SP, SP, -8
+BFD09ED6 CBC1 SW S8, 4(SP)
+BFD09ED8 0FDD MOVE S8, SP
+276: /* This just exists to keep the linker quiet. */\r
+277: }\r
+BFD09EDA 0FBE MOVE SP, S8
+BFD09EDC 4BC1 LW S8, 4(SP)
+BFD09EDE 4C05 ADDIU SP, SP, 8
+BFD09EE0 459F JR16 RA
+BFD09EE2 0C00 NOP
+278: /*-----------------------------------------------------------*/\r
+279: \r
+280: static void prvHeapInit( void )\r
+281: {\r
+BFD084A0 4FF9 ADDIU SP, SP, -16
+BFD084A2 CBC3 SW S8, 12(SP)
+BFD084A4 0FDD MOVE S8, SP
+282: BlockLink_t *pxFirstFreeBlock;\r
+283: uint8_t *pucAlignedHeap;\r
+284: \r
+285: /* Ensure the heap starts on a correctly aligned boundary. */\r
+286: pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );\r
+BFD084A6 BFD241A2 LUI V0, 0xBFD2
+BFD084A8 3062BFD2 LDC1 F30, 12386(S2)
+BFD084AA 8D703062 ADDIU V1, V0, -29328
+BFD084AC 8D70 BEQZ V0, 0xBFD0858E
+BFD084AE FFF83040 ADDIU V0, ZERO, -8
+BFD084B0 4493FFF8 LW RA, 17555(T8)
+BFD084B2 4493 AND16 V0, V1
+BFD084B4 0000F85E SW V0, 0(S8)
+287: \r
+288: /* xStart is used to hold a pointer to the first item in the list of free\r
+289: blocks. The void cast is used to prevent compiler warnings. */\r
+290: xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
+BFD084B8 0000FC5E LW V0, 0(S8)
+BFD084BC 8018F85C SW V0, -32744(GP)
+291: xStart.xBlockSize = ( size_t ) 0;\r
+BFD084C0 801CF81C SW ZERO, -32740(GP)
+292: \r
+293: /* xEnd is used to mark the end of the list of free blocks. */\r
+294: xEnd.xBlockSize = configADJUSTED_HEAP_SIZE;\r
+BFD084C4 1FF83040 ADDIU V0, ZERO, 8184
+BFD084C6 F85C1FF8 LB RA, -1956(T8)
+BFD084C8 8024F85C SW V0, -32732(GP)
+295: xEnd.pxNextFreeBlock = NULL;\r
+BFD084CC 8020F81C SW ZERO, -32736(GP)
+296: \r
+297: /* To start with there is a single free block that is sized to take up the\r
+298: entire heap space. */\r
+299: pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
+BFD084D0 0000FC5E LW V0, 0(S8)
+BFD084D4 0004F85E SW V0, 4(S8)
+300: pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;\r
+BFD084D8 0004FC5E LW V0, 4(S8)
+BFD084DC 1FF83060 ADDIU V1, ZERO, 8184
+BFD084DE E9A11FF8 LB RA, -5727(T8)
+BFD084E0 E9A1 SW V1, 4(V0)
+301: pxFirstFreeBlock->pxNextFreeBlock = &xEnd;\r
+BFD084E2 0004FC5E LW V0, 4(S8)
+BFD084E4 307C0004 MTLO A0, 0
+BFD084E6 8020307C ADDIU V1, GP, -32736
+BFD084EA E9A0 SW V1, 0(V0)
+302: }\r
+BFD084EC 0FBE MOVE SP, S8
+BFD084EE 4BC3 LW S8, 12(SP)
+BFD084F0 4C09 ADDIU SP, SP, 16
+BFD084F2 459F JR16 RA
+BFD084F4 0C00 NOP
+303: /*-----------------------------------------------------------*/\r
+--- c:/e/dev/freertos/workingcopy/freertos/source/list.c ----------------------------------------------
+1: /*\r
+2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+3: All rights reserved\r
+4: \r
+5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+6: \r
+7: This file is part of the FreeRTOS distribution.\r
+8: \r
+9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
+10: the terms of the GNU General Public License (version 2) as published by the\r
+11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+12: \r
+13: ***************************************************************************\r
+14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+15: >>! distribute a combined work that includes FreeRTOS without being !<<\r
+16: >>! obliged to provide the source code for proprietary components !<<\r
+17: >>! outside of the FreeRTOS kernel. !<<\r
+18: ***************************************************************************\r
+19: \r
+20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+22: FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+23: link: http://www.freertos.org/a00114.html\r
+24: \r
+25: ***************************************************************************\r
+26: * *\r
+27: * FreeRTOS provides completely free yet professionally developed, *\r
+28: * robust, strictly quality controlled, supported, and cross *\r
+29: * platform software that is more than just the market leader, it *\r
+30: * is the industry's de facto standard. *\r
+31: * *\r
+32: * Help yourself get started quickly while simultaneously helping *\r
+33: * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+34: * tutorial book, reference manual, or both: *\r
+35: * http://www.FreeRTOS.org/Documentation *\r
+36: * *\r
+37: ***************************************************************************\r
+38: \r
+39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+40: the FAQ page "My application does not run, what could be wrong?". Have you\r
+41: defined configASSERT()?\r
+42: \r
+43: http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+44: embedded software for free we request you assist our global community by\r
+45: participating in the support forum.\r
+46: \r
+47: http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+48: be as productive as possible as early as possible. Now you can receive\r
+49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+50: Ltd, and the world's leading authority on the world's leading RTOS.\r
+51: \r
+52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+54: compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+55: \r
+56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+58: \r
+59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+61: licenses offer ticketed support, indemnification and commercial middleware.\r
+62: \r
+63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+64: engineered and independently SIL3 certified version for use in safety and\r
+65: mission critical applications that require provable dependability.\r
+66: \r
+67: 1 tab == 4 spaces!\r
+68: */\r
+69: \r
+70: \r
+71: #include <stdlib.h>\r
+72: #include "FreeRTOS.h"\r
+73: #include "list.h"\r
+74: \r
+75: /*-----------------------------------------------------------\r
+76: * PUBLIC LIST API documented in list.h\r
+77: *----------------------------------------------------------*/\r
+78: \r
+79: void vListInitialise( List_t * const pxList )\r
+80: {\r
+BFD08AE0 4FB0 ADDIU SP, SP, -8
+BFD08AE2 CBC1 SW S8, 4(SP)
+BFD08AE4 0FDD MOVE S8, SP
+BFD08AE6 0008F89E SW A0, 8(S8)
+81: /* The list structure contains a list item which is used to mark the\r
+82: end of the list. To initialise the list the list end is inserted\r
+83: as the only list entry. */\r
+84: pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */\r
+BFD08AEA 0008FC5E LW V0, 8(S8)
+BFD08AEE 6D24 ADDIU V0, V0, 8
+BFD08AF0 0C62 MOVE V1, V0
+BFD08AF2 0008FC5E LW V0, 8(S8)
+BFD08AF6 E9A1 SW V1, 4(V0)
+85: \r
+86: /* The list end value is the highest possible value in the list to\r
+87: ensure it remains at the end of the list. */\r
+88: pxList->xListEnd.xItemValue = portMAX_DELAY;\r
+BFD08AF8 0008FC5E LW V0, 8(S8)
+BFD08AFC EDFF LI V1, -1
+BFD08AFE E9A2 SW V1, 8(V0)
+89: \r
+90: /* The list end next and previous pointers point to itself so we know\r
+91: when the list is empty. */\r
+92: pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */\r
+BFD08B00 0008FC5E LW V0, 8(S8)
+BFD08B04 6D24 ADDIU V0, V0, 8
+BFD08B06 0C62 MOVE V1, V0
+BFD08B08 0008FC5E LW V0, 8(S8)
+BFD08B0C E9A3 SW V1, 12(V0)
+93: pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */\r
+BFD08B0E 0008FC5E LW V0, 8(S8)
+BFD08B12 6D24 ADDIU V0, V0, 8
+BFD08B14 0C62 MOVE V1, V0
+BFD08B16 0008FC5E LW V0, 8(S8)
+BFD08B1A E9A4 SW V1, 16(V0)
+94: \r
+95: pxList->uxNumberOfItems = ( UBaseType_t ) 0U;\r
+BFD08B1C 0008FC5E LW V0, 8(S8)
+BFD08B20 E820 SW S0, 0(V0)
+96: \r
+97: /* Write known values into the list if\r
+98: configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\r
+99: listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );\r
+100: listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );\r
+101: }\r
+BFD08B22 0FBE MOVE SP, S8
+BFD08B24 4BC1 LW S8, 4(SP)
+BFD08B26 4C05 ADDIU SP, SP, 8
+BFD08B28 459F JR16 RA
+BFD08B2A 0C00 NOP
+102: /*-----------------------------------------------------------*/\r
+103: \r
+104: void vListInitialiseItem( ListItem_t * const pxItem )\r
+105: {\r
+BFD09DCC 4FB0 ADDIU SP, SP, -8
+BFD09DCE CBC1 SW S8, 4(SP)
+BFD09DD0 0FDD MOVE S8, SP
+BFD09DD2 0008F89E SW A0, 8(S8)
+106: /* Make sure the list item is not recorded as being on a list. */\r
+107: pxItem->pvContainer = NULL;\r
+BFD09DD6 0008FC5E LW V0, 8(S8)
+BFD09DDA E824 SW S0, 16(V0)
+108: \r
+109: /* Write known values into the list item if\r
+110: configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\r
+111: listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );\r
+112: listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );\r
+113: }\r
+BFD09DDC 0FBE MOVE SP, S8
+BFD09DDE 4BC1 LW S8, 4(SP)
+BFD09DE0 4C05 ADDIU SP, SP, 8
+BFD09DE2 459F JR16 RA
+BFD09DE4 0C00 NOP
+114: /*-----------------------------------------------------------*/\r
+115: \r
+116: void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )\r
+117: {\r
+BFD07C94 4FF9 ADDIU SP, SP, -16
+BFD07C96 CBC3 SW S8, 12(SP)
+BFD07C98 0FDD MOVE S8, SP
+BFD07C9A 0010F89E SW A0, 16(S8)
+BFD07C9E 0014F8BE SW A1, 20(S8)
+118: ListItem_t * const pxIndex = pxList->pxIndex;\r
+BFD07CA2 0010FC5E LW V0, 16(S8)
+BFD07CA6 6921 LW V0, 4(V0)
+BFD07CA8 0000F85E SW V0, 0(S8)
+119: \r
+120: /* Only effective when configASSERT() is also defined, these tests may catch\r
+121: the list data structures being overwritten in memory. They will not catch\r
+122: data errors caused by incorrect configuration or use of FreeRTOS. */\r
+123: listTEST_LIST_INTEGRITY( pxList );\r
+124: listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );\r
+125: \r
+126: /* Insert a new list item into pxList, but rather than sort the list,\r
+127: makes the new list item the last item to be removed by a call to\r
+128: listGET_OWNER_OF_NEXT_ENTRY(). */\r
+129: pxNewListItem->pxNext = pxIndex;\r
+BFD07CAC 0014FC5E LW V0, 20(S8)
+BFD07CB0 0000FC7E LW V1, 0(S8)
+BFD07CB4 E9A1 SW V1, 4(V0)
+130: pxNewListItem->pxPrevious = pxIndex->pxPrevious;\r
+BFD07CB6 0000FC5E LW V0, 0(S8)
+BFD07CBA 69A2 LW V1, 8(V0)
+BFD07CBC 0014FC5E LW V0, 20(S8)
+BFD07CC0 E9A2 SW V1, 8(V0)
+131: \r
+132: /* Only used during decision coverage testing. */\r
+133: mtCOVERAGE_TEST_DELAY();\r
+134: \r
+135: pxIndex->pxPrevious->pxNext = pxNewListItem;\r
+BFD07CC2 0000FC5E LW V0, 0(S8)
+BFD07CC6 6922 LW V0, 8(V0)
+BFD07CC8 0014FC7E LW V1, 20(S8)
+BFD07CCC E9A1 SW V1, 4(V0)
+136: pxIndex->pxPrevious = pxNewListItem;\r
+BFD07CCE 0000FC5E LW V0, 0(S8)
+BFD07CD2 0014FC7E LW V1, 20(S8)
+BFD07CD6 E9A2 SW V1, 8(V0)
+137: \r
+138: /* Remember which list the item is in. */\r
+139: pxNewListItem->pvContainer = ( void * ) pxList;\r
+BFD07CD8 0014FC5E LW V0, 20(S8)
+BFD07CDC 0010FC7E LW V1, 16(S8)
+BFD07CE0 E9A4 SW V1, 16(V0)
+140: \r
+141: ( pxList->uxNumberOfItems )++;\r
+BFD07CE2 0010FC5E LW V0, 16(S8)
+BFD07CE6 6920 LW V0, 0(V0)
+BFD07CE8 6DA0 ADDIU V1, V0, 1
+BFD07CEA 0010FC5E LW V0, 16(S8)
+BFD07CEE E9A0 SW V1, 0(V0)
+142: }\r
+BFD07CF0 0FBE MOVE SP, S8
+BFD07CF2 4BC3 LW S8, 12(SP)
+BFD07CF4 4C09 ADDIU SP, SP, 16
+BFD07CF6 459F JR16 RA
+BFD07CF8 0C00 NOP
+143: /*-----------------------------------------------------------*/\r
+144: \r
+145: void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )\r
+146: {\r
+BFD06080 4FF9 ADDIU SP, SP, -16
+BFD06082 CBC3 SW S8, 12(SP)
+BFD06084 0FDD MOVE S8, SP
+BFD06086 0010F89E SW A0, 16(S8)
+BFD0608A 0014F8BE SW A1, 20(S8)
+147: ListItem_t *pxIterator;\r
+148: const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;\r
+BFD0608E 0014FC5E LW V0, 20(S8)
+BFD06092 6920 LW V0, 0(V0)
+BFD06094 0004F85E SW V0, 4(S8)
+149: \r
+150: /* Only effective when configASSERT() is also defined, these tests may catch\r
+151: the list data structures being overwritten in memory. They will not catch\r
+152: data errors caused by incorrect configuration or use of FreeRTOS. */\r
+153: listTEST_LIST_INTEGRITY( pxList );\r
+154: listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );\r
+155: \r
+156: /* Insert the new list item into the list, sorted in xItemValue order.\r
+157: \r
+158: If the list already contains a list item with the same item value then the\r
+159: new list item should be placed after it. This ensures that TCB's which are\r
+160: stored in ready lists (all of which have the same xItemValue value) get a\r
+161: share of the CPU. However, if the xItemValue is the same as the back marker\r
+162: the iteration loop below will not end. Therefore the value is checked\r
+163: first, and the algorithm slightly modified if necessary. */\r
+164: if( xValueOfInsertion == portMAX_DELAY )\r
+BFD06098 0004FC7E LW V1, 4(S8)
+BFD0609C ED7F LI V0, -1
+BFD0609E 0008B443 BNE V1, V0, 0xBFD060B2
+BFD060A0 0C000008 SLL ZERO, T0, 1
+BFD060A2 0C00 NOP
+165: {\r
+166: pxIterator = pxList->xListEnd.pxPrevious;\r
+BFD060A4 0010FC5E LW V0, 16(S8)
+BFD060A8 6924 LW V0, 16(V0)
+BFD060AA 0000F85E SW V0, 0(S8)
+BFD060AE CC17 B 0xBFD060DE
+BFD060B0 0C00 NOP
+167: }\r
+168: else\r
+169: {\r
+170: /* *** NOTE ***********************************************************\r
+171: If you find your application is crashing here then likely causes are\r
+172: listed below. In addition see http://www.freertos.org/FAQHelp.html for\r
+173: more tips, and ensure configASSERT() is defined!\r
+174: http://www.freertos.org/a00110.html#configASSERT\r
+175: \r
+176: 1) Stack overflow -\r
+177: see http://www.freertos.org/Stacks-and-stack-overflow-checking.html\r
+178: 2) Incorrect interrupt priority assignment, especially on Cortex-M\r
+179: parts where numerically high priority values denote low actual\r
+180: interrupt priorities, which can seem counter intuitive. See\r
+181: http://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition\r
+182: of configMAX_SYSCALL_INTERRUPT_PRIORITY on\r
+183: http://www.freertos.org/a00110.html\r
+184: 3) Calling an API function from within a critical section or when\r
+185: the scheduler is suspended, or calling an API function that does\r
+186: not end in "FromISR" from an interrupt.\r
+187: 4) Using a queue or semaphore before it has been initialised or\r
+188: before the scheduler has been started (are interrupts firing\r
+189: before vTaskStartScheduler() has been called?).\r
+190: **********************************************************************/\r
+191: \r
+192: for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */\r
+BFD060B2 0010FC5E LW V0, 16(S8)
+BFD060B6 6D24 ADDIU V0, V0, 8
+BFD060B8 0000F85E SW V0, 0(S8)
+BFD060BC CC06 B 0xBFD060CA
+BFD060BE 0C00 NOP
+BFD060C0 0000FC5E LW V0, 0(S8)
+BFD060C4 6921 LW V0, 4(V0)
+BFD060C6 0000F85E SW V0, 0(S8)
+BFD060CA 0000FC5E LW V0, 0(S8)
+BFD060CE 6921 LW V0, 4(V0)
+BFD060D0 69A0 LW V1, 0(V0)
+BFD060D2 0004FC5E LW V0, 4(S8)
+BFD060D6 13900062 SLTU V0, V0, V1
+BFD060D8 40E21390 ADDI GP, S0, 16610
+BFD060DA FFF140E2 BEQZC V0, 0xBFD060C0
+BFD060DC FC5EFFF1 LW RA, -930(S1)
+193: {\r
+194: /* There is nothing to do here, just iterating to the wanted\r
+195: insertion position. */\r
+196: }\r
+197: }\r
+198: \r
+199: pxNewListItem->pxNext = pxIterator->pxNext;\r
+BFD060DE 0000FC5E LW V0, 0(S8)
+BFD060E2 69A1 LW V1, 4(V0)
+BFD060E4 0014FC5E LW V0, 20(S8)
+BFD060E8 E9A1 SW V1, 4(V0)
+200: pxNewListItem->pxNext->pxPrevious = pxNewListItem;\r
+BFD060EA 0014FC5E LW V0, 20(S8)
+BFD060EE 6921 LW V0, 4(V0)
+BFD060F0 0014FC7E LW V1, 20(S8)
+BFD060F4 E9A2 SW V1, 8(V0)
+201: pxNewListItem->pxPrevious = pxIterator;\r
+BFD060F6 0014FC5E LW V0, 20(S8)
+BFD060FA 0000FC7E LW V1, 0(S8)
+BFD060FE E9A2 SW V1, 8(V0)
+202: pxIterator->pxNext = pxNewListItem;\r
+BFD06100 0000FC5E LW V0, 0(S8)
+BFD06104 0014FC7E LW V1, 20(S8)
+BFD06108 E9A1 SW V1, 4(V0)
+203: \r
+204: /* Remember which list the item is in. This allows fast removal of the\r
+205: item later. */\r
+206: pxNewListItem->pvContainer = ( void * ) pxList;\r
+BFD0610A 0014FC5E LW V0, 20(S8)
+BFD0610E 0010FC7E LW V1, 16(S8)
+BFD06112 E9A4 SW V1, 16(V0)
+207: \r
+208: ( pxList->uxNumberOfItems )++;\r
+BFD06114 0010FC5E LW V0, 16(S8)
+BFD06118 6920 LW V0, 0(V0)
+BFD0611A 6DA0 ADDIU V1, V0, 1
+BFD0611C 0010FC5E LW V0, 16(S8)
+BFD06120 E9A0 SW V1, 0(V0)
+209: }\r
+BFD06122 0FBE MOVE SP, S8
+BFD06124 4BC3 LW S8, 12(SP)
+BFD06126 4C09 ADDIU SP, SP, 16
+BFD06128 459F JR16 RA
+BFD0612A 0C00 NOP
+210: /*-----------------------------------------------------------*/\r
+211: \r
+212: UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )\r
+213: {\r
+BFD00190 4FF9 ADDIU SP, SP, -16
+BFD00192 CBC3 SW S8, 12(SP)
+BFD00194 0FDD MOVE S8, SP
+BFD00196 0010F89E SW A0, 16(S8)
+214: /* The list item knows which list it is in. Obtain the list from the list\r
+215: item. */\r
+216: List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;\r
+BFD0019A 0010FC5E LW V0, 16(S8)
+BFD0019E 6924 LW V0, 16(V0)
+BFD001A0 0000F85E SW V0, 0(S8)
+217: \r
+218: pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;\r
+BFD001A4 0010FC5E LW V0, 16(S8)
+BFD001A8 6921 LW V0, 4(V0)
+BFD001AA 0010FC7E LW V1, 16(S8)
+BFD001AE 69B2 LW V1, 8(V1)
+BFD001B0 E9A2 SW V1, 8(V0)
+219: pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;\r
+BFD001B2 0010FC5E LW V0, 16(S8)
+BFD001B6 6922 LW V0, 8(V0)
+BFD001B8 0010FC7E LW V1, 16(S8)
+BFD001BC 69B1 LW V1, 4(V1)
+BFD001BE E9A1 SW V1, 4(V0)
+220: \r
+221: /* Only used during decision coverage testing. */\r
+222: mtCOVERAGE_TEST_DELAY();\r
+223: \r
+224: /* Make sure the index is left pointing to a valid item. */\r
+225: if( pxList->pxIndex == pxItemToRemove )\r
+BFD001C0 0000FC5E LW V0, 0(S8)
+BFD001C4 69A1 LW V1, 4(V0)
+BFD001C6 0010FC5E LW V0, 16(S8)
+BFD001CA 0007B443 BNE V1, V0, 0xBFD001DC
+BFD001CC 0C000007 SLL ZERO, A3, 1
+BFD001CE 0C00 NOP
+226: {\r
+227: pxList->pxIndex = pxItemToRemove->pxPrevious;\r
+BFD001D0 0010FC5E LW V0, 16(S8)
+BFD001D4 69A2 LW V1, 8(V0)
+BFD001D6 0000FC5E LW V0, 0(S8)
+BFD001DA E9A1 SW V1, 4(V0)
+228: }\r
+229: else\r
+230: {\r
+231: mtCOVERAGE_TEST_MARKER();\r
+232: }\r
+233: \r
+234: pxItemToRemove->pvContainer = NULL;\r
+BFD001DC 0010FC5E LW V0, 16(S8)
+BFD001E0 E824 SW S0, 16(V0)
+235: ( pxList->uxNumberOfItems )--;\r
+BFD001E2 0000FC5E LW V0, 0(S8)
+BFD001E6 6920 LW V0, 0(V0)
+BFD001E8 6DAE ADDIU V1, V0, -1
+BFD001EA 0000FC5E LW V0, 0(S8)
+BFD001EE E9A0 SW V1, 0(V0)
+236: \r
+237: return pxList->uxNumberOfItems;\r
+BFD001F0 0000FC5E LW V0, 0(S8)
+BFD001F4 6920 LW V0, 0(V0)
+238: }\r
+BFD001F6 0FBE MOVE SP, S8
+BFD001F8 4BC3 LW S8, 12(SP)
+BFD001FA 4C09 ADDIU SP, SP, 16
+BFD001FC 459F JR16 RA
+BFD001FE 0C00 NOP
+239: /*-----------------------------------------------------------*/\r
+240: \r
+--- c:/e/dev/freertos/workingcopy/freertos/source/event_groups.c --------------------------------------
+1: /*\r
+2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+3: All rights reserved\r
+4: \r
+5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+6: \r
+7: This file is part of the FreeRTOS distribution.\r
+8: \r
+9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
+10: the terms of the GNU General Public License (version 2) as published by the\r
+11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+12: \r
+13: ***************************************************************************\r
+14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+15: >>! distribute a combined work that includes FreeRTOS without being !<<\r
+16: >>! obliged to provide the source code for proprietary components !<<\r
+17: >>! outside of the FreeRTOS kernel. !<<\r
+18: ***************************************************************************\r
+19: \r
+20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+22: FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+23: link: http://www.freertos.org/a00114.html\r
+24: \r
+25: ***************************************************************************\r
+26: * *\r
+27: * FreeRTOS provides completely free yet professionally developed, *\r
+28: * robust, strictly quality controlled, supported, and cross *\r
+29: * platform software that is more than just the market leader, it *\r
+30: * is the industry's de facto standard. *\r
+31: * *\r
+32: * Help yourself get started quickly while simultaneously helping *\r
+33: * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+34: * tutorial book, reference manual, or both: *\r
+35: * http://www.FreeRTOS.org/Documentation *\r
+36: * *\r
+37: ***************************************************************************\r
+38: \r
+39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+40: the FAQ page "My application does not run, what could be wrong?". Have you\r
+41: defined configASSERT()?\r
+42: \r
+43: http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+44: embedded software for free we request you assist our global community by\r
+45: participating in the support forum.\r
+46: \r
+47: http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+48: be as productive as possible as early as possible. Now you can receive\r
+49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+50: Ltd, and the world's leading authority on the world's leading RTOS.\r
+51: \r
+52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+54: compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+55: \r
+56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+58: \r
+59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+61: licenses offer ticketed support, indemnification and commercial middleware.\r
+62: \r
+63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+64: engineered and independently SIL3 certified version for use in safety and\r
+65: mission critical applications that require provable dependability.\r
+66: \r
+67: 1 tab == 4 spaces!\r
+68: */\r
+69: \r
+70: /* Standard includes. */\r
+71: #include <stdlib.h>\r
+72: \r
+73: /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+74: all the API functions to use the MPU wrappers. That should only be done when\r
+75: task.h is included from an application file. */\r
+76: #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+77: \r
+78: /* FreeRTOS includes. */\r
+79: #include "FreeRTOS.h"\r
+80: #include "task.h"\r
+81: #include "timers.h"\r
+82: #include "event_groups.h"\r
+83: \r
+84: /* Lint e961 and e750 are suppressed as a MISRA exception justified because the\r
+85: MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the\r
+86: header files above, but not in this file, in order to generate the correct\r
+87: privileged Vs unprivileged linkage and placement. */\r
+88: #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */\r
+89: \r
+90: #if ( INCLUDE_xEventGroupSetBitFromISR == 1 ) && ( configUSE_TIMERS == 0 )\r
+91: #error configUSE_TIMERS must be set to 1 to make the xEventGroupSetBitFromISR() function available.\r
+92: #endif\r
+93: \r
+94: #if ( INCLUDE_xEventGroupSetBitFromISR == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 0 )\r
+95: #error INCLUDE_xTimerPendFunctionCall must also be set to one to make the xEventGroupSetBitFromISR() function available.\r
+96: #endif\r
+97: \r
+98: /* The following bit fields convey control information in a task's event list\r
+99: item value. It is important they don't clash with the\r
+100: taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */\r
+101: #if configUSE_16_BIT_TICKS == 1\r
+102: #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U\r
+103: #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U\r
+104: #define eventWAIT_FOR_ALL_BITS 0x0400U\r
+105: #define eventEVENT_BITS_CONTROL_BYTES 0xff00U\r
+106: #else\r
+107: #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL\r
+108: #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL\r
+109: #define eventWAIT_FOR_ALL_BITS 0x04000000UL\r
+110: #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL\r
+111: #endif\r
+112: \r
+113: typedef struct xEventGroupDefinition\r
+114: {\r
+115: EventBits_t uxEventBits;\r
+116: List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */\r
+117: \r
+118: #if( configUSE_TRACE_FACILITY == 1 )\r
+119: UBaseType_t uxEventGroupNumber;\r
+120: #endif\r
+121: \r
+122: } EventGroup_t;\r
+123: \r
+124: /*-----------------------------------------------------------*/\r
+125: \r
+126: /*\r
+127: * Test the bits set in uxCurrentEventBits to see if the wait condition is met.\r
+128: * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is\r
+129: * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor\r
+130: * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the\r
+131: * wait condition is met if any of the bits set in uxBitsToWait for are also set\r
+132: * in uxCurrentEventBits.\r
+133: */\r
+134: static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits );\r
+135: \r
+136: /*-----------------------------------------------------------*/\r
+137: \r
+138: EventGroupHandle_t xEventGroupCreate( void )\r
+139: {\r
+BFD09320 4FF1 ADDIU SP, SP, -32
+BFD09322 CBE7 SW RA, 28(SP)
+BFD09324 CBC6 SW S8, 24(SP)
+BFD09326 0FDD MOVE S8, SP
+140: EventGroup_t *pxEventBits;\r
+141: \r
+142: pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );\r
+BFD09328 EE18 LI A0, 24
+BFD0932A 111677E8 JALS pvPortMalloc
+BFD0932C 0C001116 ADDI T0, S6, 3072
+BFD0932E 0C00 NOP
+BFD09330 0010F85E SW V0, 16(S8)
+143: if( pxEventBits != NULL )\r
+BFD09334 0010FC5E LW V0, 16(S8)
+BFD09338 000A40E2 BEQZC V0, 0xBFD09350
+144: {\r
+145: pxEventBits->uxEventBits = 0;\r
+BFD0933C 0010FC5E LW V0, 16(S8)
+BFD09340 E820 SW S0, 0(V0)
+146: vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );\r
+BFD09342 0010FC5E LW V0, 16(S8)
+BFD09346 6D22 ADDIU V0, V0, 4
+BFD09348 0C82 MOVE A0, V0
+BFD0934A 457077E8 JALS vListInitialise
+BFD0934C 4570 SWM16 0x3, 0(SP)
+BFD0934E 0C00 NOP
+147: traceEVENT_GROUP_CREATE( pxEventBits );\r
+148: }\r
+149: else\r
+150: {\r
+151: traceEVENT_GROUP_CREATE_FAILED();\r
+152: }\r
+153: \r
+154: return ( EventGroupHandle_t ) pxEventBits;\r
+BFD09350 0010FC5E LW V0, 16(S8)
+155: }\r
+BFD09354 0FBE MOVE SP, S8
+BFD09356 4BE7 LW RA, 28(SP)
+BFD09358 4BC6 LW S8, 24(SP)
+BFD0935A 4C11 ADDIU SP, SP, 32
+BFD0935C 459F JR16 RA
+BFD0935E 0C00 NOP
+156: /*-----------------------------------------------------------*/\r
+157: \r
+158: EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )\r
+159: {\r
+BFD01B0C 4FE9 ADDIU SP, SP, -48
+BFD01B0E CBEB SW RA, 44(SP)
+BFD01B10 CBCA SW S8, 40(SP)
+BFD01B12 0FDD MOVE S8, SP
+BFD01B14 0030F89E SW A0, 48(S8)
+BFD01B18 0034F8BE SW A1, 52(S8)
+BFD01B1C 0038F8DE SW A2, 56(S8)
+BFD01B20 003CF8FE SW A3, 60(S8)
+160: EventBits_t uxOriginalBitValue, uxReturn;\r
+161: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
+BFD01B24 0030FC5E LW V0, 48(S8)
+BFD01B28 0014F85E SW V0, 20(S8)
+162: BaseType_t xAlreadyYielded;\r
+163: BaseType_t xTimeoutOccurred = pdFALSE;\r
+BFD01B2C 0018F81E SW ZERO, 24(S8)
+164: \r
+165: configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\r
+BFD01B30 0038FC7E LW V1, 56(S8)
+BFD01B34 FF0041A2 LUI V0, 0xFF00
+BFD01B36 4493FF00 LW T8, 17555(ZERO)
+BFD01B38 4493 AND16 V0, V1
+BFD01B3A 000940E2 BEQZC V0, 0xBFD01B50
+BFD01B3E BFD141A2 LUI V0, 0xBFD1
+BFD01B40 3082BFD1 LDC1 F30, 12418(S1)
+BFD01B42 9C0C3082 ADDIU A0, V0, -25588
+BFD01B44 30A09C0C LWC1 F0, 12448(T4)
+BFD01B46 00A530A0 ADDIU A1, ZERO, 165
+BFD01B4A 4B7E77E8 JALS vAssertCalled
+BFD01B4C 4B7E LW K1, 120(SP)
+BFD01B4E 0C00 NOP
+166: configASSERT( uxBitsToWaitFor != 0 );\r
+BFD01B50 0038FC5E LW V0, 56(S8)
+BFD01B54 000940A2 BNEZC V0, 0xBFD01B6A
+BFD01B58 BFD141A2 LUI V0, 0xBFD1
+BFD01B5A 3082BFD1 LDC1 F30, 12418(S1)
+BFD01B5C 9C0C3082 ADDIU A0, V0, -25588
+BFD01B5E 30A09C0C LWC1 F0, 12448(T4)
+BFD01B60 00A630A0 ADDIU A1, ZERO, 166
+BFD01B64 4B7E77E8 JALS vAssertCalled
+BFD01B66 4B7E LW K1, 120(SP)
+BFD01B68 0C00 NOP
+167: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r
+168: {\r
+169: configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\r
+BFD01B6A 4A8E77E8 JALS xTaskGetSchedulerState
+BFD01B6C 4A8E LW S4, 56(SP)
+BFD01B6E 0C00 NOP
+BFD01B70 000440A2 BNEZC V0, 0xBFD01B7C
+BFD01B74 003CFC5E LW V0, 60(S8)
+BFD01B78 000340A2 BNEZC V0, 0xBFD01B82
+BFD01B7C ED01 LI V0, 1
+BFD01B7E CC02 B 0xBFD01B84
+BFD01B80 0C00 NOP
+BFD01B82 0C40 MOVE V0, ZERO
+BFD01B84 000940A2 BNEZC V0, 0xBFD01B9A
+BFD01B88 BFD141A2 LUI V0, 0xBFD1
+BFD01B8A 3082BFD1 LDC1 F30, 12418(S1)
+BFD01B8C 9C0C3082 ADDIU A0, V0, -25588
+BFD01B8E 30A09C0C LWC1 F0, 12448(T4)
+BFD01B90 00A930A0 ADDIU A1, ZERO, 169
+BFD01B94 4B7E77E8 JALS vAssertCalled
+BFD01B96 4B7E LW K1, 120(SP)
+BFD01B98 0C00 NOP
+170: }\r
+171: #endif\r
+172: \r
+173: vTaskSuspendAll();\r
+BFD01B9A 4EF477E8 JALS vTaskSuspendAll
+BFD01B9C 4EF4 ADDIU S7, S7, -6
+BFD01B9E 0C00 NOP
+174: {\r
+175: uxOriginalBitValue = pxEventBits->uxEventBits;\r
+BFD01BA0 0014FC5E LW V0, 20(S8)
+BFD01BA4 6920 LW V0, 0(V0)
+BFD01BA6 001CF85E SW V0, 28(S8)
+176: \r
+177: ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );\r
+BFD01BAA 0030FC9E LW A0, 48(S8)
+BFD01BAE 0034FCBE LW A1, 52(S8)
+BFD01BB2 12B477E8 JALS xEventGroupSetBits
+BFD01BB4 0C0012B4 ADDI S5, S4, 3072
+BFD01BB6 0C00 NOP
+178: \r
+179: if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )\r
+BFD01BB8 001CFC7E LW V1, 28(S8)
+BFD01BBC 0034FC5E LW V0, 52(S8)
+BFD01BC0 44DA OR16 V1, V0
+BFD01BC2 0038FC5E LW V0, 56(S8)
+BFD01BC6 449A AND16 V1, V0
+BFD01BC8 0038FC5E LW V0, 56(S8)
+BFD01BCC 0016B443 BNE V1, V0, 0xBFD01BFC
+BFD01BCE 0C000016 SLL ZERO, S6, 1
+BFD01BD0 0C00 NOP
+180: {\r
+181: /* All the rendezvous bits are now set - no need to block. */\r
+182: uxReturn = ( uxOriginalBitValue | uxBitsToSet );\r
+BFD01BD2 001CFC7E LW V1, 28(S8)
+BFD01BD6 0034FC5E LW V0, 52(S8)
+BFD01BDA 44D3 OR16 V0, V1
+BFD01BDC 0010F85E SW V0, 16(S8)
+183: \r
+184: /* Rendezvous always clear the bits. They will have been cleared\r
+185: already unless this is the only task in the rendezvous. */\r
+186: pxEventBits->uxEventBits &= ~uxBitsToWaitFor;\r
+BFD01BE0 0014FC5E LW V0, 20(S8)
+BFD01BE4 69A0 LW V1, 0(V0)
+BFD01BE6 0038FC5E LW V0, 56(S8)
+BFD01BEA 4412 NOT16 V0, V0
+BFD01BEC 449A AND16 V1, V0
+BFD01BEE 0014FC5E LW V0, 20(S8)
+BFD01BF2 E9A0 SW V1, 0(V0)
+187: \r
+188: xTicksToWait = 0;\r
+BFD01BF4 003CF81E SW ZERO, 60(S8)
+BFD01BF6 CC1D003C SHILO null, 60
+BFD01BF8 CC1D B 0xBFD01C34
+BFD01BFA 0C00 NOP
+189: }\r
+190: else\r
+191: {\r
+192: if( xTicksToWait != ( TickType_t ) 0 )\r
+BFD01BFC 003CFC5E LW V0, 60(S8)
+BFD01C00 001340E2 BEQZC V0, 0xBFD01C2A
+193: {\r
+194: traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );\r
+195: \r
+196: /* Store the bits that the calling task is waiting for in the\r
+197: task's event list item so the kernel knows when a match is\r
+198: found. Then enter the blocked state. */\r
+199: vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );\r
+BFD01C04 0014FC5E LW V0, 20(S8)
+BFD01C08 6DA2 ADDIU V1, V0, 4
+BFD01C0A 0038FC9E LW A0, 56(S8)
+BFD01C0E 050041A2 LUI V0, 0x500
+BFD01C10 0500 ADDU V0, S0, S0
+BFD01C12 44D4 OR16 V0, A0
+BFD01C14 0C83 MOVE A0, V1
+BFD01C16 0CA2 MOVE A1, V0
+BFD01C18 003CFCDE LW A2, 60(S8)
+BFD01C1C 248277E8 JALS vTaskPlaceOnUnorderedEventList
+BFD01C1E 2482 SLL S1, S0, 1
+BFD01C20 0C00 NOP
+200: \r
+201: /* This assignment is obsolete as uxReturn will get set after\r
+202: the task unblocks, but some compilers mistakenly generate a\r
+203: warning about uxReturn being returned without being set if the\r
+204: assignment is omitted. */\r
+205: uxReturn = 0;\r
+BFD01C22 0010F81E SW ZERO, 16(S8)
+BFD01C26 CC06 B 0xBFD01C34
+BFD01C28 0C00 NOP
+206: }\r
+207: else\r
+208: {\r
+209: /* The rendezvous bits were not set, but no block time was\r
+210: specified - just return the current event bit value. */\r
+211: uxReturn = pxEventBits->uxEventBits;\r
+BFD01C2A 0014FC5E LW V0, 20(S8)
+BFD01C2E 6920 LW V0, 0(V0)
+BFD01C30 0010F85E SW V0, 16(S8)
+212: }\r
+213: }\r
+214: }\r
+215: xAlreadyYielded = xTaskResumeAll();\r
+BFD01C34 158E77E8 JALS xTaskResumeAll
+BFD01C36 0C00158E LBU T4, 3072(T6)
+BFD01C38 0C00 NOP
+BFD01C3A 0020F85E SW V0, 32(S8)
+216: \r
+217: if( xTicksToWait != ( TickType_t ) 0 )\r
+BFD01C3E 003CFC5E LW V0, 60(S8)
+BFD01C42 004840E2 BEQZC V0, 0xBFD01CD6
+218: {\r
+219: if( xAlreadyYielded == pdFALSE )\r
+BFD01C46 0020FC5E LW V0, 32(S8)
+BFD01C4A 001040A2 BNEZC V0, 0xBFD01C6E
+220: {\r
+221: portYIELD_WITHIN_API();\r
+BFD01C4E 4DE677E8 JALS ulPortGetCP0Cause
+BFD01C50 4DE6 ADDIU T7, T7, 3
+BFD01C52 0C00 NOP
+BFD01C54 0024F85E SW V0, 36(S8)
+BFD01C58 0024FC5E LW V0, 36(S8)
+BFD01C5C 01005042 ORI V0, V0, 256
+BFD01C60 0024F85E SW V0, 36(S8)
+BFD01C64 0024FC9E LW A0, 36(S8)
+BFD01C68 4DF677E8 JALS vPortSetCP0Cause
+BFD01C6A 4DF6 ADDIU T7, T7, -5
+BFD01C6C 0C00 NOP
+222: }\r
+223: else\r
+224: {\r
+225: mtCOVERAGE_TEST_MARKER();\r
+226: }\r
+227: \r
+228: /* The task blocked to wait for its required bits to be set - at this\r
+229: point either the required bits were set or the block time expired. If\r
+230: the required bits were set they will have been stored in the task's\r
+231: event list item, and they should now be retrieved then cleared. */\r
+232: uxReturn = uxTaskResetEventItemValue();\r
+BFD01C6E 4C8677E8 JALS uxTaskResetEventItemValue
+BFD01C70 4C86 ADDIU A0, A0, 3
+BFD01C72 0C00 NOP
+BFD01C74 0010F85E SW V0, 16(S8)
+233: \r
+234: if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )\r
+BFD01C78 0010FC7E LW V1, 16(S8)
+BFD01C7C 020041A2 LUI V0, 0x200
+BFD01C80 4493 AND16 V0, V1
+BFD01C82 002240A2 BNEZC V0, 0xBFD01CCA
+235: {\r
+236: /* The task timed out, just return the current event bit value. */\r
+237: taskENTER_CRITICAL();\r
+BFD01C86 33B877E8 JALS vTaskEnterCritical
+BFD01C88 0C0033B8 ADDIU SP, T8, 3072
+BFD01C8A 0C00 NOP
+238: {\r
+239: uxReturn = pxEventBits->uxEventBits;\r
+BFD01C8C 0014FC5E LW V0, 20(S8)
+BFD01C90 6920 LW V0, 0(V0)
+BFD01C92 0010F85E SW V0, 16(S8)
+240: \r
+241: /* Although the task got here because it timed out before the\r
+242: bits it was waiting for were set, it is possible that since it\r
+243: unblocked another task has set the bits. If this is the case\r
+244: then it needs to clear the bits before exiting. */\r
+245: if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )\r
+BFD01C96 0010FC7E LW V1, 16(S8)
+BFD01C9A 0038FC5E LW V0, 56(S8)
+BFD01C9E 449A AND16 V1, V0
+BFD01CA0 0038FC5E LW V0, 56(S8)
+BFD01CA4 000BB443 BNE V1, V0, 0xBFD01CBE
+BFD01CA6 0C00000B SLL ZERO, T3, 1
+BFD01CA8 0C00 NOP
+246: {\r
+247: pxEventBits->uxEventBits &= ~uxBitsToWaitFor;\r
+BFD01CAA 0014FC5E LW V0, 20(S8)
+BFD01CAE 69A0 LW V1, 0(V0)
+BFD01CB0 0038FC5E LW V0, 56(S8)
+BFD01CB4 4412 NOT16 V0, V0
+BFD01CB6 449A AND16 V1, V0
+BFD01CB8 0014FC5E LW V0, 20(S8)
+BFD01CBC E9A0 SW V1, 0(V0)
+248: }\r
+249: else\r
+250: {\r
+251: mtCOVERAGE_TEST_MARKER();\r
+252: }\r
+253: }\r
+254: taskEXIT_CRITICAL();\r
+BFD01CBE 40AA77E8 JALS vTaskExitCritical
+BFD01CC0 0C0040AA BNEZC T2, 0xBFD034C4
+BFD01CC2 0C00 NOP
+255: \r
+256: xTimeoutOccurred = pdTRUE;\r
+BFD01CC4 ED01 LI V0, 1
+BFD01CC6 0018F85E SW V0, 24(S8)
+257: }\r
+258: else\r
+259: {\r
+260: /* The task unblocked because the bits were set. */\r
+261: }\r
+262: \r
+263: /* Control bits might be set as the task had blocked should not be\r
+264: returned. */\r
+265: uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;\r
+BFD01CCA 0010FC5E LW V0, 16(S8)
+BFD01CCE B82C0042 EXT V0, V0, 0, 24
+BFD01CD0 F85EB82C SDC1 F1, -1954(T4)
+BFD01CD2 0010F85E SW V0, 16(S8)
+266: }\r
+267: \r
+268: traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );\r
+269: \r
+270: return uxReturn;\r
+BFD01CD6 0010FC5E LW V0, 16(S8)
+271: }\r
+BFD01CDA 0FBE MOVE SP, S8
+BFD01CDC 4BEB LW RA, 44(SP)
+BFD01CDE 4BCA LW S8, 40(SP)
+BFD01CE0 4C19 ADDIU SP, SP, 48
+BFD01CE2 459F JR16 RA
+BFD01CE4 0C00 NOP
+272: /*-----------------------------------------------------------*/\r
+273: \r
+274: EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )\r
+275: {\r
+BFD01310 4FE5 ADDIU SP, SP, -56
+BFD01312 CBED SW RA, 52(SP)
+BFD01314 CBCC SW S8, 48(SP)
+BFD01316 0FDD MOVE S8, SP
+BFD01318 0038F89E SW A0, 56(S8)
+BFD0131C 003CF8BE SW A1, 60(S8)
+BFD01320 0040F8DE SW A2, 64(S8)
+BFD01324 0044F8FE SW A3, 68(S8)
+276: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
+BFD01328 0038FC5E LW V0, 56(S8)
+BFD0132C 0018F85E SW V0, 24(S8)
+277: EventBits_t uxReturn, uxControlBits = 0;\r
+BFD01330 0014F81E SW ZERO, 20(S8)
+278: BaseType_t xWaitConditionMet, xAlreadyYielded;\r
+279: BaseType_t xTimeoutOccurred = pdFALSE;\r
+BFD01334 001CF81E SW ZERO, 28(S8)
+280: \r
+281: /* Check the user is not attempting to wait on the bits used by the kernel\r
+282: itself, and that at least one bit is being requested. */\r
+283: configASSERT( xEventGroup );\r
+BFD01338 0038FC5E LW V0, 56(S8)
+BFD0133C 000940A2 BNEZC V0, 0xBFD01352
+BFD01340 BFD141A2 LUI V0, 0xBFD1
+BFD01342 3082BFD1 LDC1 F30, 12418(S1)
+BFD01344 9C0C3082 ADDIU A0, V0, -25588
+BFD01346 30A09C0C LWC1 F0, 12448(T4)
+BFD01348 011B30A0 ADDIU A1, ZERO, 283
+BFD0134C 4B7E77E8 JALS vAssertCalled
+BFD0134E 4B7E LW K1, 120(SP)
+BFD01350 0C00 NOP
+284: configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\r
+BFD01352 003CFC7E LW V1, 60(S8)
+BFD01356 FF0041A2 LUI V0, 0xFF00
+BFD01358 4493FF00 LW T8, 17555(ZERO)
+BFD0135A 4493 AND16 V0, V1
+BFD0135C 000940E2 BEQZC V0, 0xBFD01372
+BFD01360 BFD141A2 LUI V0, 0xBFD1
+BFD01362 3082BFD1 LDC1 F30, 12418(S1)
+BFD01364 9C0C3082 ADDIU A0, V0, -25588
+BFD01366 30A09C0C LWC1 F0, 12448(T4)
+BFD01368 011C30A0 ADDIU A1, ZERO, 284
+BFD0136C 4B7E77E8 JALS vAssertCalled
+BFD0136E 4B7E LW K1, 120(SP)
+BFD01370 0C00 NOP
+285: configASSERT( uxBitsToWaitFor != 0 );\r
+BFD01372 003CFC5E LW V0, 60(S8)
+BFD01376 000940A2 BNEZC V0, 0xBFD0138C
+BFD0137A BFD141A2 LUI V0, 0xBFD1
+BFD0137C 3082BFD1 LDC1 F30, 12418(S1)
+BFD0137E 9C0C3082 ADDIU A0, V0, -25588
+BFD01380 30A09C0C LWC1 F0, 12448(T4)
+BFD01382 011D30A0 ADDIU A1, ZERO, 285
+BFD01386 4B7E77E8 JALS vAssertCalled
+BFD01388 4B7E LW K1, 120(SP)
+BFD0138A 0C00 NOP
+286: #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r
+287: {\r
+288: configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\r
+BFD0138C 4A8E77E8 JALS xTaskGetSchedulerState
+BFD0138E 4A8E LW S4, 56(SP)
+BFD01390 0C00 NOP
+BFD01392 000440A2 BNEZC V0, 0xBFD0139E
+BFD01396 0048FC5E LW V0, 72(S8)
+BFD0139A 000340A2 BNEZC V0, 0xBFD013A4
+BFD0139E ED01 LI V0, 1
+BFD013A0 CC02 B 0xBFD013A6
+BFD013A2 0C00 NOP
+BFD013A4 0C40 MOVE V0, ZERO
+BFD013A6 000940A2 BNEZC V0, 0xBFD013BC
+BFD013AA BFD141A2 LUI V0, 0xBFD1
+BFD013AC 3082BFD1 LDC1 F30, 12418(S1)
+BFD013AE 9C0C3082 ADDIU A0, V0, -25588
+BFD013B0 30A09C0C LWC1 F0, 12448(T4)
+BFD013B2 012030A0 ADDIU A1, ZERO, 288
+BFD013B6 4B7E77E8 JALS vAssertCalled
+BFD013B8 4B7E LW K1, 120(SP)
+BFD013BA 0C00 NOP
+289: }\r
+290: #endif\r
+291: \r
+292: vTaskSuspendAll();\r
+BFD013BC 4EF477E8 JALS vTaskSuspendAll
+BFD013BE 4EF4 ADDIU S7, S7, -6
+BFD013C0 0C00 NOP
+293: {\r
+294: const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;\r
+BFD013C2 0018FC5E LW V0, 24(S8)
+BFD013C6 6920 LW V0, 0(V0)
+BFD013C8 0020F85E SW V0, 32(S8)
+295: \r
+296: /* Check to see if the wait condition is already met or not. */\r
+297: xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );\r
+BFD013CC 0020FC9E LW A0, 32(S8)
+BFD013D0 003CFCBE LW A1, 60(S8)
+BFD013D4 0044FCDE LW A2, 68(S8)
+BFD013D8 407A77E8 JALS prvTestWaitCondition
+BFD013DA 0C00407A BGEZAL K0, 0xBFD02BDE
+BFD013DC 0C00 NOP
+BFD013DE 0024F85E SW V0, 36(S8)
+298: \r
+299: if( xWaitConditionMet != pdFALSE )\r
+BFD013E2 0024FC5E LW V0, 36(S8)
+BFD013E6 001640E2 BEQZC V0, 0xBFD01416
+300: {\r
+301: /* The wait condition has already been met so there is no need to\r
+302: block. */\r
+303: uxReturn = uxCurrentEventBits;\r
+BFD013EA 0020FC5E LW V0, 32(S8)
+BFD013EE 0010F85E SW V0, 16(S8)
+304: xTicksToWait = ( TickType_t ) 0;\r
+BFD013F2 0048F81E SW ZERO, 72(S8)
+305: \r
+306: /* Clear the wait bits if requested to do so. */\r
+307: if( xClearOnExit != pdFALSE )\r
+BFD013F6 0040FC5E LW V0, 64(S8)
+BFD013FA 003D40E2 BEQZC V0, 0xBFD01478
+308: {\r
+309: pxEventBits->uxEventBits &= ~uxBitsToWaitFor;\r
+BFD013FE 0018FC5E LW V0, 24(S8)
+BFD01402 69A0 LW V1, 0(V0)
+BFD01404 003CFC5E LW V0, 60(S8)
+BFD01408 4412 NOT16 V0, V0
+BFD0140A 449A AND16 V1, V0
+BFD0140C 0018FC5E LW V0, 24(S8)
+BFD01410 E9A0 SW V1, 0(V0)
+BFD01412 CC32 B 0xBFD01478
+BFD01414 0C00 NOP
+310: }\r
+311: else\r
+312: {\r
+313: mtCOVERAGE_TEST_MARKER();\r
+314: }\r
+315: }\r
+316: else if( xTicksToWait == ( TickType_t ) 0 )\r
+BFD01416 0048FC5E LW V0, 72(S8)
+BFD0141A 000640A2 BNEZC V0, 0xBFD0142A
+317: {\r
+318: /* The wait condition has not been met, but no block time was\r
+319: specified, so just return the current value. */\r
+320: uxReturn = uxCurrentEventBits;\r
+BFD0141E 0020FC5E LW V0, 32(S8)
+BFD01422 0010F85E SW V0, 16(S8)
+BFD01426 CC28 B 0xBFD01478
+BFD01428 0C00 NOP
+321: }\r
+322: else\r
+323: {\r
+324: /* The task is going to block to wait for its required bits to be\r
+325: set. uxControlBits are used to remember the specified behaviour of\r
+326: this call to xEventGroupWaitBits() - for use when the event bits\r
+327: unblock the task. */\r
+328: if( xClearOnExit != pdFALSE )\r
+BFD0142A 0040FC5E LW V0, 64(S8)
+BFD0142E 000740E2 BEQZC V0, 0xBFD01440
+329: {\r
+330: uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;\r
+BFD01432 0014FC7E LW V1, 20(S8)
+BFD01436 010041A2 LUI V0, 0x100
+BFD0143A 44D3 OR16 V0, V1
+BFD0143C 0014F85E SW V0, 20(S8)
+331: }\r
+332: else\r
+333: {\r
+334: mtCOVERAGE_TEST_MARKER();\r
+335: }\r
+336: \r
+337: if( xWaitForAllBits != pdFALSE )\r
+BFD01440 0044FC5E LW V0, 68(S8)
+BFD01444 000740E2 BEQZC V0, 0xBFD01456
+338: {\r
+339: uxControlBits |= eventWAIT_FOR_ALL_BITS;\r
+BFD01448 0014FC7E LW V1, 20(S8)
+BFD0144C 040041A2 LUI V0, 0x400
+BFD0144E 0400 ADDU S0, S0, S0
+BFD01450 44D3 OR16 V0, V1
+BFD01452 0014F85E SW V0, 20(S8)
+340: }\r
+341: else\r
+342: {\r
+343: mtCOVERAGE_TEST_MARKER();\r
+344: }\r
+345: \r
+346: /* Store the bits that the calling task is waiting for in the\r
+347: task's event list item so the kernel knows when a match is\r
+348: found. Then enter the blocked state. */\r
+349: vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );\r
+BFD01456 0018FC5E LW V0, 24(S8)
+BFD0145A 6DA2 ADDIU V1, V0, 4
+BFD0145C 003CFC9E LW A0, 60(S8)
+BFD01460 0014FC5E LW V0, 20(S8)
+BFD01464 44D4 OR16 V0, A0
+BFD01466 0C83 MOVE A0, V1
+BFD01468 0CA2 MOVE A1, V0
+BFD0146A 0048FCDE LW A2, 72(S8)
+BFD0146E 248277E8 JALS vTaskPlaceOnUnorderedEventList
+BFD01470 2482 SLL S1, S0, 1
+BFD01472 0C00 NOP
+350: \r
+351: /* This is obsolete as it will get set after the task unblocks, but\r
+352: some compilers mistakenly generate a warning about the variable\r
+353: being returned without being set if it is not done. */\r
+354: uxReturn = 0;\r
+BFD01474 0010F81E SW ZERO, 16(S8)
+355: \r
+356: traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );\r
+357: }\r
+358: }\r
+359: xAlreadyYielded = xTaskResumeAll();\r
+BFD01478 158E77E8 JALS xTaskResumeAll
+BFD0147A 0C00158E LBU T4, 3072(T6)
+BFD0147C 0C00 NOP
+BFD0147E 0028F85E SW V0, 40(S8)
+360: \r
+361: if( xTicksToWait != ( TickType_t ) 0 )\r
+BFD01482 0048FC5E LW V0, 72(S8)
+BFD01486 004C40E2 BEQZC V0, 0xBFD01522
+362: {\r
+363: if( xAlreadyYielded == pdFALSE )\r
+BFD0148A 0028FC5E LW V0, 40(S8)
+BFD0148E 001040A2 BNEZC V0, 0xBFD014B2
+364: {\r
+365: portYIELD_WITHIN_API();\r
+BFD01492 4DE677E8 JALS ulPortGetCP0Cause
+BFD01494 4DE6 ADDIU T7, T7, 3
+BFD01496 0C00 NOP
+BFD01498 002CF85E SW V0, 44(S8)
+BFD0149C 002CFC5E LW V0, 44(S8)
+BFD014A0 01005042 ORI V0, V0, 256
+BFD014A4 002CF85E SW V0, 44(S8)
+BFD014A8 002CFC9E LW A0, 44(S8)
+BFD014AC 4DF677E8 JALS vPortSetCP0Cause
+BFD014AE 4DF6 ADDIU T7, T7, -5
+BFD014B0 0C00 NOP
+366: }\r
+367: else\r
+368: {\r
+369: mtCOVERAGE_TEST_MARKER();\r
+370: }\r
+371: \r
+372: /* The task blocked to wait for its required bits to be set - at this\r
+373: point either the required bits were set or the block time expired. If\r
+374: the required bits were set they will have been stored in the task's\r
+375: event list item, and they should now be retrieved then cleared. */\r
+376: uxReturn = uxTaskResetEventItemValue();\r
+BFD014B2 4C8677E8 JALS uxTaskResetEventItemValue
+BFD014B4 4C86 ADDIU A0, A0, 3
+BFD014B6 0C00 NOP
+BFD014B8 0010F85E SW V0, 16(S8)
+377: \r
+378: if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )\r
+BFD014BC 0010FC7E LW V1, 16(S8)
+BFD014C0 020041A2 LUI V0, 0x200
+BFD014C4 4493 AND16 V0, V1
+BFD014C6 002640A2 BNEZC V0, 0xBFD01516
+379: {\r
+380: taskENTER_CRITICAL();\r
+BFD014CA 33B877E8 JALS vTaskEnterCritical
+BFD014CC 0C0033B8 ADDIU SP, T8, 3072
+BFD014CE 0C00 NOP
+381: {\r
+382: /* The task timed out, just return the current event bit value. */\r
+383: uxReturn = pxEventBits->uxEventBits;\r
+BFD014D0 0018FC5E LW V0, 24(S8)
+BFD014D4 6920 LW V0, 0(V0)
+BFD014D6 0010F85E SW V0, 16(S8)
+384: \r
+385: /* It is possible that the event bits were updated between this\r
+386: task leaving the Blocked state and running again. */\r
+387: if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )\r
+BFD014DA 0010FC9E LW A0, 16(S8)
+BFD014DE 003CFCBE LW A1, 60(S8)
+BFD014E2 0044FCDE LW A2, 68(S8)
+BFD014E6 407A77E8 JALS prvTestWaitCondition
+BFD014E8 0C00407A BGEZAL K0, 0xBFD02CEC
+BFD014EA 0C00 NOP
+BFD014EC 000E40E2 BEQZC V0, 0xBFD0150C
+388: {\r
+389: if( xClearOnExit != pdFALSE )\r
+BFD014F0 0040FC5E LW V0, 64(S8)
+BFD014F4 000A40E2 BEQZC V0, 0xBFD0150C
+390: {\r
+391: pxEventBits->uxEventBits &= ~uxBitsToWaitFor;\r
+BFD014F8 0018FC5E LW V0, 24(S8)
+BFD014FC 69A0 LW V1, 0(V0)
+BFD014FE 003CFC5E LW V0, 60(S8)
+BFD01502 4412 NOT16 V0, V0
+BFD01504 449A AND16 V1, V0
+BFD01506 0018FC5E LW V0, 24(S8)
+BFD0150A E9A0 SW V1, 0(V0)
+392: }\r
+393: else\r
+394: {\r
+395: mtCOVERAGE_TEST_MARKER();\r
+396: }\r
+397: }\r
+398: else\r
+399: {\r
+400: mtCOVERAGE_TEST_MARKER();\r
+401: }\r
+402: }\r
+403: taskEXIT_CRITICAL();\r
+BFD0150C 40AA77E8 JALS vTaskExitCritical
+BFD0150E 0C0040AA BNEZC T2, 0xBFD02D12
+BFD01510 0C00 NOP
+404: \r
+405: /* Prevent compiler warnings when trace macros are not used. */\r
+406: xTimeoutOccurred = pdFALSE;\r
+BFD01512 001CF81E SW ZERO, 28(S8)
+407: }\r
+408: else\r
+409: {\r
+410: /* The task unblocked because the bits were set. */\r
+411: }\r
+412: \r
+413: /* The task blocked so control bits may have been set. */\r
+414: uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;\r
+BFD01516 0010FC5E LW V0, 16(S8)
+BFD0151A B82C0042 EXT V0, V0, 0, 24
+BFD0151C F85EB82C SDC1 F1, -1954(T4)
+BFD0151E 0010F85E SW V0, 16(S8)
+415: }\r
+416: traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );\r
+417: \r
+418: return uxReturn;\r
+BFD01522 0010FC5E LW V0, 16(S8)
+419: }\r
+BFD01526 0FBE MOVE SP, S8
+BFD01528 4BED LW RA, 52(SP)
+BFD0152A 4BCC LW S8, 48(SP)
+BFD0152C 4C1D ADDIU SP, SP, 56
+BFD0152E 459F JR16 RA
+BFD01530 0C00 NOP
+420: /*-----------------------------------------------------------*/\r
+421: \r
+422: EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )\r
+423: {\r
+BFD06A44 4FF1 ADDIU SP, SP, -32
+BFD06A46 CBE7 SW RA, 28(SP)
+BFD06A48 CBC6 SW S8, 24(SP)
+BFD06A4A 0FDD MOVE S8, SP
+BFD06A4C 0020F89E SW A0, 32(S8)
+BFD06A50 0024F8BE SW A1, 36(S8)
+424: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
+BFD06A54 0020FC5E LW V0, 32(S8)
+BFD06A58 0010F85E SW V0, 16(S8)
+425: EventBits_t uxReturn;\r
+426: \r
+427: /* Check the user is not attempting to clear the bits used by the kernel\r
+428: itself. */\r
+429: configASSERT( xEventGroup );\r
+BFD06A5C 0020FC5E LW V0, 32(S8)
+BFD06A60 000940A2 BNEZC V0, 0xBFD06A76
+BFD06A64 BFD141A2 LUI V0, 0xBFD1
+BFD06A66 3082BFD1 LDC1 F30, 12418(S1)
+BFD06A68 9C0C3082 ADDIU A0, V0, -25588
+BFD06A6A 30A09C0C LWC1 F0, 12448(T4)
+BFD06A6C 01AD30A0 ADDIU A1, ZERO, 429
+BFD06A70 4B7E77E8 JALS vAssertCalled
+BFD06A72 4B7E LW K1, 120(SP)
+BFD06A74 0C00 NOP
+430: configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\r
+BFD06A76 0024FC7E LW V1, 36(S8)
+BFD06A7A FF0041A2 LUI V0, 0xFF00
+BFD06A7C 4493FF00 LW T8, 17555(ZERO)
+BFD06A7E 4493 AND16 V0, V1
+BFD06A80 000940E2 BEQZC V0, 0xBFD06A96
+BFD06A84 BFD141A2 LUI V0, 0xBFD1
+BFD06A86 3082BFD1 LDC1 F30, 12418(S1)
+BFD06A88 9C0C3082 ADDIU A0, V0, -25588
+BFD06A8A 30A09C0C LWC1 F0, 12448(T4)
+BFD06A8C 01AE30A0 ADDIU A1, ZERO, 430
+BFD06A90 4B7E77E8 JALS vAssertCalled
+BFD06A92 4B7E LW K1, 120(SP)
+BFD06A94 0C00 NOP
+431: \r
+432: taskENTER_CRITICAL();\r
+BFD06A96 33B877E8 JALS vTaskEnterCritical
+BFD06A98 0C0033B8 ADDIU SP, T8, 3072
+BFD06A9A 0C00 NOP
+433: {\r
+434: traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );\r
+435: \r
+436: /* The value returned is the event group value prior to the bits being\r
+437: cleared. */\r
+438: uxReturn = pxEventBits->uxEventBits;\r
+BFD06A9C 0010FC5E LW V0, 16(S8)
+BFD06AA0 6920 LW V0, 0(V0)
+BFD06AA2 0014F85E SW V0, 20(S8)
+439: \r
+440: /* Clear the bits. */\r
+441: pxEventBits->uxEventBits &= ~uxBitsToClear;\r
+BFD06AA6 0010FC5E LW V0, 16(S8)
+BFD06AAA 69A0 LW V1, 0(V0)
+BFD06AAC 0024FC5E LW V0, 36(S8)
+BFD06AB0 4412 NOT16 V0, V0
+BFD06AB2 449A AND16 V1, V0
+BFD06AB4 0010FC5E LW V0, 16(S8)
+BFD06AB8 E9A0 SW V1, 0(V0)
+442: }\r
+443: taskEXIT_CRITICAL();\r
+BFD06ABA 40AA77E8 JALS vTaskExitCritical
+BFD06ABC 0C0040AA BNEZC T2, 0xBFD082C0
+BFD06ABE 0C00 NOP
+444: \r
+445: return uxReturn;\r
+BFD06AC0 0014FC5E LW V0, 20(S8)
+446: }\r
+BFD06AC4 0FBE MOVE SP, S8
+BFD06AC6 4BE7 LW RA, 28(SP)
+BFD06AC8 4BC6 LW S8, 24(SP)
+BFD06ACA 4C11 ADDIU SP, SP, 32
+BFD06ACC 459F JR16 RA
+BFD06ACE 0C00 NOP
+447: /*-----------------------------------------------------------*/\r
+448: \r
+449: #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\r
+450: \r
+451: BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )\r
+452: {\r
+453: BaseType_t xReturn;\r
+454: \r
+455: traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );\r
+456: xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );\r
+457: \r
+458: return xReturn;\r
+459: }\r
+460: \r
+461: #endif\r
+462: /*-----------------------------------------------------------*/\r
+463: \r
+464: EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )\r
+465: {\r
+BFD09144 4FED ADDIU SP, SP, -40
+BFD09146 CBE9 SW RA, 36(SP)
+BFD09148 CBC8 SW S8, 32(SP)
+BFD0914A 0FDD MOVE S8, SP
+BFD0914C 0028F89E SW A0, 40(S8)
+466: UBaseType_t uxSavedInterruptStatus;\r
+467: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
+BFD09150 0028FC5E LW V0, 40(S8)
+BFD09154 0010F85E SW V0, 16(S8)
+468: EventBits_t uxReturn;\r
+469: \r
+470: uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+BFD09158 475E77E8 JALS uxPortSetInterruptMaskFromISR
+BFD0915C 0C00 NOP
+BFD0915E 0014F85E SW V0, 20(S8)
+471: {\r
+472: uxReturn = pxEventBits->uxEventBits;\r
+BFD09162 0010FC5E LW V0, 16(S8)
+BFD09166 6920 LW V0, 0(V0)
+BFD09168 0018F85E SW V0, 24(S8)
+473: }\r
+474: portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+BFD0916C 0014FC9E LW A0, 20(S8)
+BFD09170 4D5E77E8 JALS vPortClearInterruptMaskFromISR
+BFD09172 4D5E ADDIU T2, T2, -1
+BFD09174 0C00 NOP
+475: \r
+476: return uxReturn;\r
+BFD09176 0018FC5E LW V0, 24(S8)
+477: }\r
+BFD0917A 0FBE MOVE SP, S8
+BFD0917C 4BE9 LW RA, 36(SP)
+BFD0917E 4BC8 LW S8, 32(SP)
+BFD09180 4C15 ADDIU SP, SP, 40
+BFD09182 459F JR16 RA
+BFD09184 0C00 NOP
+478: /*-----------------------------------------------------------*/\r
+479: \r
+480: EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )\r
+481: {\r
+BFD02568 4FE1 ADDIU SP, SP, -64
+BFD0256A CBEF SW RA, 60(SP)
+BFD0256C CBCE SW S8, 56(SP)
+BFD0256E 0FDD MOVE S8, SP
+BFD02570 0040F89E SW A0, 64(S8)
+BFD02574 0044F8BE SW A1, 68(S8)
+482: ListItem_t *pxListItem, *pxNext;\r
+483: ListItem_t const *pxListEnd;\r
+484: List_t *pxList;\r
+485: EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;\r
+BFD02578 0014F81E SW ZERO, 20(S8)
+486: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
+BFD0257C 0040FC5E LW V0, 64(S8)
+BFD02580 001CF85E SW V0, 28(S8)
+487: BaseType_t xMatchFound = pdFALSE;\r
+BFD02584 0018F81E SW ZERO, 24(S8)
+488: \r
+489: /* Check the user is not attempting to set the bits used by the kernel\r
+490: itself. */\r
+491: configASSERT( xEventGroup );\r
+BFD02588 0040FC5E LW V0, 64(S8)
+BFD0258C 000940A2 BNEZC V0, 0xBFD025A2
+BFD02590 BFD141A2 LUI V0, 0xBFD1
+BFD02592 3082BFD1 LDC1 F30, 12418(S1)
+BFD02594 9C0C3082 ADDIU A0, V0, -25588
+BFD02596 30A09C0C LWC1 F0, 12448(T4)
+BFD02598 01EB30A0 ADDIU A1, ZERO, 491
+BFD0259C 4B7E77E8 JALS vAssertCalled
+BFD0259E 4B7E LW K1, 120(SP)
+BFD025A0 0C00 NOP
+492: configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\r
+BFD025A2 0044FC7E LW V1, 68(S8)
+BFD025A6 FF0041A2 LUI V0, 0xFF00
+BFD025A8 4493FF00 LW T8, 17555(ZERO)
+BFD025AA 4493 AND16 V0, V1
+BFD025AC 000940E2 BEQZC V0, 0xBFD025C2
+BFD025B0 BFD141A2 LUI V0, 0xBFD1
+BFD025B2 3082BFD1 LDC1 F30, 12418(S1)
+BFD025B4 9C0C3082 ADDIU A0, V0, -25588
+BFD025B6 30A09C0C LWC1 F0, 12448(T4)
+BFD025B8 01EC30A0 ADDIU A1, ZERO, 492
+BFD025BC 4B7E77E8 JALS vAssertCalled
+BFD025BE 4B7E LW K1, 120(SP)
+BFD025C0 0C00 NOP
+493: \r
+494: pxList = &( pxEventBits->xTasksWaitingForBits );\r
+BFD025C2 001CFC5E LW V0, 28(S8)
+BFD025C6 6D22 ADDIU V0, V0, 4
+BFD025C8 0020F85E SW V0, 32(S8)
+495: pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */\r
+BFD025CC 0020FC5E LW V0, 32(S8)
+BFD025D0 6D24 ADDIU V0, V0, 8
+BFD025D2 0024F85E SW V0, 36(S8)
+496: vTaskSuspendAll();\r
+BFD025D6 4EF477E8 JALS vTaskSuspendAll
+BFD025D8 4EF4 ADDIU S7, S7, -6
+BFD025DA 0C00 NOP
+497: {\r
+498: traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );\r
+499: \r
+500: pxListItem = listGET_HEAD_ENTRY( pxList );\r
+BFD025DC 0020FC5E LW V0, 32(S8)
+BFD025E0 6923 LW V0, 12(V0)
+BFD025E2 0010F85E SW V0, 16(S8)
+501: \r
+502: /* Set the bits. */\r
+503: pxEventBits->uxEventBits |= uxBitsToSet;\r
+BFD025E6 001CFC5E LW V0, 28(S8)
+BFD025EA 69A0 LW V1, 0(V0)
+BFD025EC 0044FC5E LW V0, 68(S8)
+BFD025F0 44DA OR16 V1, V0
+BFD025F2 001CFC5E LW V0, 28(S8)
+BFD025F6 E9A0 SW V1, 0(V0)
+504: \r
+505: /* See if the new bit value should unblock any tasks. */\r
+506: while( pxListItem != pxListEnd )\r
+BFD025F8 CC5E B 0xBFD026B6
+BFD025FA 0C00 NOP
+BFD026B6 0010FC7E LW V1, 16(S8)
+BFD026BA 0024FC5E LW V0, 36(S8)
+BFD026BE FF9DB443 BNE V1, V0, 0xBFD025FC
+BFD026C0 0C00FF9D LW GP, 3072(SP)
+BFD026C2 0C00 NOP
+507: {\r
+508: pxNext = listGET_NEXT( pxListItem );\r
+BFD025FC 0010FC5E LW V0, 16(S8)
+BFD02600 6921 LW V0, 4(V0)
+BFD02602 0028F85E SW V0, 40(S8)
+509: uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );\r
+BFD02606 0010FC5E LW V0, 16(S8)
+BFD0260A 6920 LW V0, 0(V0)
+BFD0260C 002CF85E SW V0, 44(S8)
+510: xMatchFound = pdFALSE;\r
+BFD02610 0018F81E SW ZERO, 24(S8)
+511: \r
+512: /* Split the bits waited for from the control bits. */\r
+513: uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;\r
+BFD02614 002CFC7E LW V1, 44(S8)
+BFD02618 FF0041A2 LUI V0, 0xFF00
+BFD0261A 4493FF00 LW T8, 17555(ZERO)
+BFD0261C 4493 AND16 V0, V1
+BFD0261E 0030F85E SW V0, 48(S8)
+514: uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;\r
+BFD02622 002CFC5E LW V0, 44(S8)
+BFD02626 B82C0042 EXT V0, V0, 0, 24
+BFD02628 F85EB82C SDC1 F1, -1954(T4)
+BFD0262A 002CF85E SW V0, 44(S8)
+515: \r
+516: if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )\r
+BFD0262E 0030FC7E LW V1, 48(S8)
+BFD02632 040041A2 LUI V0, 0x400
+BFD02634 0400 ADDU S0, S0, S0
+BFD02636 4493 AND16 V0, V1
+BFD02638 000D40A2 BNEZC V0, 0xBFD02656
+517: {\r
+518: /* Just looking for single bit being set. */\r
+519: if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )\r
+BFD0263C 001CFC5E LW V0, 28(S8)
+BFD02640 69A0 LW V1, 0(V0)
+BFD02642 002CFC5E LW V0, 44(S8)
+BFD02646 4493 AND16 V0, V1
+BFD02648 001340E2 BEQZC V0, 0xBFD02672
+520: {\r
+521: xMatchFound = pdTRUE;\r
+BFD0264C ED01 LI V0, 1
+BFD0264E 0018F85E SW V0, 24(S8)
+BFD02652 CC0F B 0xBFD02672
+BFD02654 0C00 NOP
+522: }\r
+523: else\r
+524: {\r
+525: mtCOVERAGE_TEST_MARKER();\r
+526: }\r
+527: }\r
+528: else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )\r
+BFD02656 001CFC5E LW V0, 28(S8)
+BFD0265A 69A0 LW V1, 0(V0)
+BFD0265C 002CFC5E LW V0, 44(S8)
+BFD02660 449A AND16 V1, V0
+BFD02662 002CFC5E LW V0, 44(S8)
+BFD02666 0004B443 BNE V1, V0, 0xBFD02672
+BFD02668 0C000004 SLL ZERO, A0, 1
+BFD0266A 0C00 NOP
+529: {\r
+530: /* All bits are set. */\r
+531: xMatchFound = pdTRUE;\r
+BFD0266C ED01 LI V0, 1
+BFD0266E 0018F85E SW V0, 24(S8)
+532: }\r
+533: else\r
+534: {\r
+535: /* Need all bits to be set, but not all the bits were set. */\r
+536: }\r
+537: \r
+538: if( xMatchFound != pdFALSE )\r
+BFD02672 0018FC5E LW V0, 24(S8)
+BFD02676 001A40E2 BEQZC V0, 0xBFD026AE
+539: {\r
+540: /* The bits match. Should the bits be cleared on exit? */\r
+541: if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )\r
+BFD0267A 0030FC7E LW V1, 48(S8)
+BFD0267E 010041A2 LUI V0, 0x100
+BFD02682 4493 AND16 V0, V1
+BFD02684 000740E2 BEQZC V0, 0xBFD02696
+542: {\r
+543: uxBitsToClear |= uxBitsWaitedFor;\r
+BFD02688 0014FC7E LW V1, 20(S8)
+BFD0268C 002CFC5E LW V0, 44(S8)
+BFD02690 44D3 OR16 V0, V1
+BFD02692 0014F85E SW V0, 20(S8)
+544: }\r
+545: else\r
+546: {\r
+547: mtCOVERAGE_TEST_MARKER();\r
+548: }\r
+549: \r
+550: /* Store the actual event flag value in the task's event list\r
+551: item before removing the task from the event list. The\r
+552: eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows\r
+553: that is was unblocked due to its required bits matching, rather\r
+554: than because it timed out. */\r
+555: ( void ) xTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );\r
+BFD02696 001CFC5E LW V0, 28(S8)
+BFD0269A 69A0 LW V1, 0(V0)
+BFD0269C 020041A2 LUI V0, 0x200
+BFD026A0 44D3 OR16 V0, V1
+BFD026A2 0010FC9E LW A0, 16(S8)
+BFD026A6 0CA2 MOVE A1, V0
+BFD026A8 216277E8 JALS xTaskRemoveFromUnorderedEventList
+BFD026AA 0C002162 LWC2 T3, 3072(V0)
+BFD026AC 0C00 NOP
+556: }\r
+557: \r
+558: /* Move onto the next list item. Note pxListItem->pxNext is not\r
+559: used here as the list item may have been removed from the event list\r
+560: and inserted into the ready/pending reading list. */\r
+561: pxListItem = pxNext;\r
+BFD026AE 0028FC5E LW V0, 40(S8)
+BFD026B2 0010F85E SW V0, 16(S8)
+562: }\r
+563: \r
+564: /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT\r
+565: bit was set in the control word. */\r
+566: pxEventBits->uxEventBits &= ~uxBitsToClear;\r
+BFD026C4 001CFC5E LW V0, 28(S8)
+BFD026C8 69A0 LW V1, 0(V0)
+BFD026CA 0014FC5E LW V0, 20(S8)
+BFD026CE 4412 NOT16 V0, V0
+BFD026D0 449A AND16 V1, V0
+BFD026D2 001CFC5E LW V0, 28(S8)
+BFD026D6 E9A0 SW V1, 0(V0)
+567: }\r
+568: ( void ) xTaskResumeAll();\r
+BFD026D8 158E77E8 JALS xTaskResumeAll
+BFD026DA 0C00158E LBU T4, 3072(T6)
+BFD026DC 0C00 NOP
+569: \r
+570: return pxEventBits->uxEventBits;\r
+BFD026DE 001CFC5E LW V0, 28(S8)
+BFD026E2 6920 LW V0, 0(V0)
+571: }\r
+BFD026E4 0FBE MOVE SP, S8
+BFD026E6 4BEF LW RA, 60(SP)
+BFD026E8 4BCE LW S8, 56(SP)
+BFD026EA 4C21 ADDIU SP, SP, 64
+BFD026EC 459F JR16 RA
+BFD026EE 0C00 NOP
+572: /*-----------------------------------------------------------*/\r
+573: \r
+574: void vEventGroupDelete( EventGroupHandle_t xEventGroup )\r
+575: {\r
+BFD06C70 4FF1 ADDIU SP, SP, -32
+BFD06C72 CBE7 SW RA, 28(SP)
+BFD06C74 CBC6 SW S8, 24(SP)
+BFD06C76 0FDD MOVE S8, SP
+BFD06C78 0020F89E SW A0, 32(S8)
+576: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
+BFD06C7C 0020FC5E LW V0, 32(S8)
+BFD06C80 0010F85E SW V0, 16(S8)
+577: const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );\r
+BFD06C84 0010FC5E LW V0, 16(S8)
+BFD06C88 6D22 ADDIU V0, V0, 4
+BFD06C8A 0014F85E SW V0, 20(S8)
+578: \r
+579: vTaskSuspendAll();\r
+BFD06C8E 4EF477E8 JALS vTaskSuspendAll
+BFD06C90 4EF4 ADDIU S7, S7, -6
+BFD06C92 0C00 NOP
+580: {\r
+581: traceEVENT_GROUP_DELETE( xEventGroup );\r
+582: \r
+583: while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )\r
+BFD06C94 CC1C B 0xBFD06CCE
+BFD06C96 0C00 NOP
+BFD06CCE 0014FC5E LW V0, 20(S8)
+BFD06CD2 6920 LW V0, 0(V0)
+BFD06CD4 FFE040A2 BNEZC V0, 0xBFD06C98
+BFD06CD6 FC9EFFE0 LW RA, -866(ZERO)
+584: {\r
+585: /* Unblock the task, returning 0 as the event list is being deleted\r
+586: and cannot therefore have any bits set. */\r
+587: configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );\r
+BFD06C98 0014FC5E LW V0, 20(S8)
+BFD06C9C 69A3 LW V1, 12(V0)
+BFD06C9E 0014FC5E LW V0, 20(S8)
+BFD06CA2 6D24 ADDIU V0, V0, 8
+BFD06CA4 000AB443 BNE V1, V0, 0xBFD06CBC
+BFD06CA6 0C00000A SLL ZERO, T2, 1
+BFD06CA8 0C00 NOP
+BFD06CAA BFD141A2 LUI V0, 0xBFD1
+BFD06CAC 3082BFD1 LDC1 F30, 12418(S1)
+BFD06CAE 9C0C3082 ADDIU A0, V0, -25588
+BFD06CB0 30A09C0C LWC1 F0, 12448(T4)
+BFD06CB2 024B30A0 ADDIU A1, ZERO, 587
+BFD06CB6 4B7E77E8 JALS vAssertCalled
+BFD06CB8 4B7E LW K1, 120(SP)
+BFD06CBA 0C00 NOP
+588: ( void ) xTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );\r
+BFD06CBC 0014FC5E LW V0, 20(S8)
+BFD06CC0 6923 LW V0, 12(V0)
+BFD06CC2 0C82 MOVE A0, V0
+BFD06CC4 020041A5 LUI A1, 0x200
+BFD06CC8 216277E8 JALS xTaskRemoveFromUnorderedEventList
+BFD06CCA 0C002162 LWC2 T3, 3072(V0)
+BFD06CCC 0C00 NOP
+589: }\r
+590: \r
+591: vPortFree( pxEventBits );\r
+BFD06CD8 0010FC9E LW A0, 16(S8)
+BFD06CDC 2FEA77E8 JALS vPortFree
+BFD06CDE 2FEA ANDI A3, A2, 0x20
+BFD06CE0 0C00 NOP
+592: }\r
+593: ( void ) xTaskResumeAll();\r
+BFD06CE2 158E77E8 JALS xTaskResumeAll
+BFD06CE4 0C00158E LBU T4, 3072(T6)
+BFD06CE6 0C00 NOP
+594: }\r
+BFD06CE8 0FBE MOVE SP, S8
+BFD06CEA 4BE7 LW RA, 28(SP)
+BFD06CEC 4BC6 LW S8, 24(SP)
+BFD06CEE 4C11 ADDIU SP, SP, 32
+BFD06CF0 459F JR16 RA
+BFD06CF2 0C00 NOP
+595: /*-----------------------------------------------------------*/\r
+596: \r
+597: /* For internal use only - execute a 'set bits' command that was pended from\r
+598: an interrupt. */\r
+599: void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )\r
+600: {\r
+BFD0993C 4FF5 ADDIU SP, SP, -24
+BFD0993E CBE5 SW RA, 20(SP)
+BFD09940 CBC4 SW S8, 16(SP)
+BFD09942 0FDD MOVE S8, SP
+BFD09944 0018F89E SW A0, 24(S8)
+BFD09948 001CF8BE SW A1, 28(S8)
+601: ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );\r
+BFD0994C 0018FC9E LW A0, 24(S8)
+BFD09950 001CFCBE LW A1, 28(S8)
+BFD09954 12B477E8 JALS xEventGroupSetBits
+BFD09956 0C0012B4 ADDI S5, S4, 3072
+BFD09958 0C00 NOP
+602: }\r
+BFD0995A 0FBE MOVE SP, S8
+BFD0995C 4BE5 LW RA, 20(SP)
+BFD0995E 4BC4 LW S8, 16(SP)
+BFD09960 4C0D ADDIU SP, SP, 24
+BFD09962 459F JR16 RA
+BFD09964 0C00 NOP
+603: /*-----------------------------------------------------------*/\r
+604: \r
+605: /* For internal use only - execute a 'clear bits' command that was pended from\r
+606: an interrupt. */\r
+607: void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )\r
+608: {\r
+BFD09968 4FF5 ADDIU SP, SP, -24
+BFD0996A CBE5 SW RA, 20(SP)
+BFD0996C CBC4 SW S8, 16(SP)
+BFD0996E 0FDD MOVE S8, SP
+BFD09970 0018F89E SW A0, 24(S8)
+BFD09974 001CF8BE SW A1, 28(S8)
+609: ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );\r
+BFD09978 0018FC9E LW A0, 24(S8)
+BFD0997C 001CFCBE LW A1, 28(S8)
+BFD09980 352277E8 JALS xEventGroupClearBits
+BFD09982 0C003522 LHU T1, 3072(V0)
+BFD09984 0C00 NOP
+610: }\r
+BFD09986 0FBE MOVE SP, S8
+BFD09988 4BE5 LW RA, 20(SP)
+BFD0998A 4BC4 LW S8, 16(SP)
+BFD0998C 4C0D ADDIU SP, SP, 24
+BFD0998E 459F JR16 RA
+BFD09990 0C00 NOP
+611: /*-----------------------------------------------------------*/\r
+612: \r
+613: static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )\r
+614: {\r
+BFD080F4 4FF9 ADDIU SP, SP, -16
+BFD080F6 CBC3 SW S8, 12(SP)
+BFD080F8 0FDD MOVE S8, SP
+BFD080FA 0010F89E SW A0, 16(S8)
+BFD080FE 0014F8BE SW A1, 20(S8)
+BFD08102 0018F8DE SW A2, 24(S8)
+615: BaseType_t xWaitConditionMet = pdFALSE;\r
+BFD08106 0000F81E SW ZERO, 0(S8)
+616: \r
+617: if( xWaitForAllBits == pdFALSE )\r
+BFD0810A 0018FC5E LW V0, 24(S8)
+BFD0810E 000C40A2 BNEZC V0, 0xBFD0812A
+618: {\r
+619: /* Task only has to wait for one bit within uxBitsToWaitFor to be\r
+620: set. Is one already set? */\r
+621: if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )\r
+BFD08112 0010FC7E LW V1, 16(S8)
+BFD08116 0014FC5E LW V0, 20(S8)
+BFD0811A 4493 AND16 V0, V1
+BFD0811C 001240E2 BEQZC V0, 0xBFD08144
+622: {\r
+623: xWaitConditionMet = pdTRUE;\r
+BFD08120 ED01 LI V0, 1
+BFD08122 0000F85E SW V0, 0(S8)
+BFD08126 CC0E B 0xBFD08144
+BFD08128 0C00 NOP
+624: }\r
+625: else\r
+626: {\r
+627: mtCOVERAGE_TEST_MARKER();\r
+628: }\r
+629: }\r
+630: else\r
+631: {\r
+632: /* Task has to wait for all the bits in uxBitsToWaitFor to be set.\r
+633: Are they set already? */\r
+634: if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )\r
+BFD0812A 0010FC7E LW V1, 16(S8)
+BFD0812E 0014FC5E LW V0, 20(S8)
+BFD08132 449A AND16 V1, V0
+BFD08134 0014FC5E LW V0, 20(S8)
+BFD08138 0004B443 BNE V1, V0, 0xBFD08144
+BFD0813A 0C000004 SLL ZERO, A0, 1
+BFD0813C 0C00 NOP
+635: {\r
+636: xWaitConditionMet = pdTRUE;\r
+BFD0813E ED01 LI V0, 1
+BFD08140 0000F85E SW V0, 0(S8)
+637: }\r
+638: else\r
+639: {\r
+640: mtCOVERAGE_TEST_MARKER();\r
+641: }\r
+642: }\r
+643: \r
+644: return xWaitConditionMet;\r
+BFD08144 0000FC5E LW V0, 0(S8)
+645: }\r
+BFD08148 0FBE MOVE SP, S8
+BFD0814A 4BC3 LW S8, 12(SP)
+BFD0814C 4C09 ADDIU SP, SP, 16
+BFD0814E 459F JR16 RA
+BFD08150 0C00 NOP
+646: /*-----------------------------------------------------------*/\r
+647: \r
+648: #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\r
+649: \r
+650: BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )\r
+651: {\r
+652: BaseType_t xReturn;\r
+653: \r
+654: traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );\r
+655: xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );\r
+656: \r
+657: return xReturn;\r
+658: }\r
+659: \r
+660: #endif\r
+661: /*-----------------------------------------------------------*/\r
+662: \r
+663: #if (configUSE_TRACE_FACILITY == 1)\r
+664: \r
+665: UBaseType_t uxEventGroupGetNumber( void* xEventGroup )\r
+666: {\r
+667: UBaseType_t xReturn;\r
+668: EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r
+669: \r
+670: if( xEventGroup == NULL )\r
+671: {\r
+672: xReturn = 0;\r
+673: }\r
+674: else\r
+675: {\r
+676: xReturn = pxEventBits->uxEventGroupNumber;\r
+677: }\r
+678: \r
+679: return xReturn;\r
+680: }\r
+681: \r
+682: #endif\r
+683: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/startup/mplab/on_reset.c
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file on_reset.c\r
+22: *MEC14xx XC32 M14K Startup code _on_reset handler\r
+23: */\r
+24: /** @defgroup MEC14xx Startup\r
+25: * @{\r
+26: */\r
+27: \r
+28: \r
+29: #include "appcfg.h"\r
+30: #include "platform.h"\r
+31: #include "MEC14xx/mec14xx.h"\r
+32: #include "MEC14xx/mec14xx_pcr.h"\r
+33: \r
+34: /*\r
+35: * From linker command file\r
+36: */\r
+37: extern uint32_t _ebase_address[];\r
+38: \r
+39: \r
+40: /** _on_reset - Very early HW initialization.\r
+41: * @note XC32 startup code has initialized SP & GP. No other\r
+42: * C features have been initialized (before .bss clear and\r
+43: * global data init.) NOTE: MIPS M14K is still in Boot-Strap \r
+44: * mode and EBASE has not been programmed. Any exception or \r
+45: * interrupts will vector to the BEV Exception handler! \r
+46: */\r
+47: void\r
+48: __attribute__((nomips16)) _on_reset (void)\r
+49: {\r
+BFD091CC 4FB0 ADDIU SP, SP, -8
+BFD091CE CBC1 SW S8, 4(SP)
+BFD091D0 0FDD MOVE S8, SP
+50: /* Enable JTAG */\r
+51: ECS_REG->JTAG_ENABLE |= 1u;\r
+BFD091D2 A00041A2 LUI V0, 0xA000
+BFD091D6 FC205042 ORI V0, V0, -992
+BFD091D8 41A3FC20 LW AT, 16803(ZERO)
+BFD091DA A00041A3 LUI V1, 0xA000
+BFD091DE FC205063 ORI V1, V1, -992
+BFD091E0 69B0FC20 LW AT, 27056(ZERO)
+BFD091E2 69B0 LW V1, 0(V1)
+BFD091E4 00015063 ORI V1, V1, 1
+BFD091E8 E9A0 SW V1, 0(V0)
+52: \r
+53: /* Disable WDT */\r
+54: WDT->CONTROL = 0u;\r
+BFD091EA A00041A2 LUI V0, 0xA000
+BFD091EE 04005042 ORI V0, V0, 1024
+BFD091F0 0400 ADDU S0, S0, S0
+BFD091F2 8824 SB S0, 4(V0)
+55: \r
+56: /* Set CPU clock divider specified in appcfg.h */\r
+57: PCR->PROC_CLOCK_CNTRL = ( PCR_CLOCK_DIVIDER );\r
+BFD091F4 A00841A2 LUI V0, 0xA008
+BFD091F8 01005042 ORI V0, V0, 256
+BFD091FC ED81 LI V1, 1
+BFD091FE E9A8 SW V1, 32(V0)
+58: __EHB();\r
+BFD09200 18000000 SLL ZERO, ZERO, 3
+BFD09202 00001800 SB ZERO, 0(ZERO)
+59: CPU_NOP();\r
+BFD09204 08000000 SSNOP
+BFD09206 0800 LBU S0, 0(S0)
+60: \r
+61: }\r
+BFD09208 0FBE MOVE SP, S8
+BFD0920A 4BC1 LW S8, 4(SP)
+BFD0920C 459F JR16 RA
+BFD0920E 4C05 ADDIU SP, SP, 8
+62: \r
+63: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/startup/mplab/default-on-bootstrap.c
+1: /*********************************************************************\r
+2: *\r
+3: * Default _on_bootstrap Implementation\r
+4: *\r
+5: *********************************************************************\r
+6: * Filename: default-on-bootstrap.c\r
+7: *\r
+8: * Processor: PIC32\r
+9: *\r
+10: * Compiler: MPLAB C Compiler for PIC32 MCUs\r
+11: * MPLAB IDE\r
+12: * Company: Microchip Technology Inc.\r
+13: *\r
+14: * Software License Agreement\r
+15: *\r
+16: * The software supplied herewith by Microchip Technology Incorporated\r
+17: * (the 'Company') for its PIC32/PIC24F Microcontroller is intended\r
+18: * and supplied to you, the Company's customer, for use solely and\r
+19: * exclusively on Microchip PIC32/PIC24F Microcontroller products.\r
+20: * The software is owned by the Company and/or its supplier, and is\r
+21: * protected under applicable copyright laws. All rights are reserved.\r
+22: * Any use in violation of the foregoing restrictions may subject the\r
+23: * user to criminal sanctions under applicable laws, as well as to\r
+24: * civil liability for the breach of the terms and conditions of this\r
+25: * license.\r
+26: *\r
+27: * THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,\r
+28: * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED\r
+29: * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
+30: * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,\r
+31: * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR\r
+32: * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+33: *\r
+34: ********************************************************************/\r
+35: /* This is a default definition of an _on_bootstrap() function.\r
+36: * It does nothing and just goes returns. If the user\r
+37: * application supplies a handler function, this function will not be\r
+38: * referenced and thus not pulled in from the library.\r
+39: */\r
+40: void \r
+41: _on_bootstrap (void)\r
+42: {\r
+BFD09EE4 4FB0 ADDIU SP, SP, -8
+BFD09EE6 CBC1 SW S8, 4(SP)
+BFD09EE8 0FDD MOVE S8, SP
+43: }\r
+BFD09EEA 0FBE MOVE SP, S8
+BFD09EEC 4BC1 LW S8, 4(SP)
+BFD09EEE 4C05 ADDIU SP, SP, 8
+BFD09EF0 459F JR16 RA
+BFD09EF2 0C00 NOP
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_timers.c -------
+1: /*****************************************************************************\r
+2: * © 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: \r
+22: /** @file mec14xx_timers.c\r
+23: *MEC14xx Timers \r
+24: */\r
+25: /** @defgroup MEC14xx Peripherals Timers\r
+26: * @{\r
+27: */\r
+28: \r
+29: \r
+30: #include "appcfg.h"\r
+31: #include "platform.h"\r
+32: #include "MEC14xx/mec14xx.h"\r
+33: #include "MEC14xx/mec14xx_pcr.h"\r
+34: #include "MEC14xx/mec14xx_timers.h"\r
+35: \r
+36: \r
+37: // pairs of bytes (sleep reg, bit position)\r
+38: // sleep reg = 0 for EC_SLEEP_EN or 1 for EC_SLEEP_EN2\r
+39: //\r
+40: struct btmr_sleep_info_s {\r
+41: uint8_t slp_reg;\r
+42: uint8_t bit_pos;\r
+43: };\r
+44: \r
+45: static const struct btmr_sleep_info_s btmr_slp_info[BTMR_MAX_INSTANCE] = {\r
+46: { 0, PCR_EC_TIMER0_SLP_BITPOS },\r
+47: { 0, PCR_EC_TIMER1_SLP_BITPOS },\r
+48: { 1, PCR_EC2_TIMER2_SLP_BITPOS },\r
+49: { 1, PCR_EC2_TIMER3_SLP_BITPOS }\r
+50: };\r
+51: \r
+52: \r
+53: #ifdef MEC14XX_BTIMER_CHECK_ID\r
+54: \r
+55: /**\r
+56: * tmr_valid - Local helper that checks if logical Timer ID is \r
+57: * valid. \r
+58: * \r
+59: * @author sworley \r
+60: * \r
+61: * @param tmr_id 0-based Timer ID\r
+62: * \r
+63: * @return uint8_t Non-zero(VALID), 0(Invalid)\r
+64: */\r
+65: static uint8_t btmr_valid(uint8_t tmr_id)\r
+66: {\r
+BFD09A44 4FB0 ADDIU SP, SP, -8
+BFD09A46 CBC1 SW S8, 4(SP)
+BFD09A48 0FDD MOVE S8, SP
+BFD09A4A 0C44 MOVE V0, A0
+BFD09A4C 0008185E SB V0, 8(S8)
+67: if ( tmr_id < (BTMR_ID_MAX ) ) {\r
+BFD09A50 0008145E LBU V0, 8(S8)
+BFD09A54 0004B042 SLTIU V0, V0, 4
+BFD09A58 000340E2 BEQZC V0, 0xBFD09A62
+68: return true;\r
+BFD09A5C ED01 LI V0, 1
+BFD09A5E CC02 B 0xBFD09A64
+BFD09A60 0C00 NOP
+69: }\r
+70: return false;\r
+BFD09A62 0C40 MOVE V0, ZERO
+71: }\r
+BFD09A64 0FBE MOVE SP, S8
+BFD09A66 4BC1 LW S8, 4(SP)
+BFD09A68 4C05 ADDIU SP, SP, 8
+BFD09A6A 459F JR16 RA
+BFD09A6C 0C00 NOP
+72: \r
+73: #else\r
+74: \r
+75: /**\r
+76: * @brief - This version of tmr_valid skips checking always \r
+77: * returning TRUE. Compiler may optimize it out.\r
+78: * \r
+79: */\r
+80: static uint8_t btmr_valid(uint8_t tmr_id) \r
+81: { \r
+82: (void) tmr_id;\r
+83: return true; \r
+84: }\r
+85: \r
+86: #endif\r
+87: \r
+88: uint32_t btmr_get_hw_addr(uint8_t btmr_id)\r
+89: {\r
+BFD09A70 4FB0 ADDIU SP, SP, -8
+BFD09A72 CBC1 SW S8, 4(SP)
+BFD09A74 0FDD MOVE S8, SP
+BFD09A76 0C44 MOVE V0, A0
+BFD09A78 0008185E SB V0, 8(S8)
+90: return (uint32_t)(BTMR0_BASE) + \r
+BFD09A82 A00041A2 LUI V0, 0xA000
+BFD09A86 0C005042 ORI V0, V0, 3072
+BFD09A88 0C00 NOP
+BFD09A8A 0526 ADDU V0, V1, V0
+91: ((uint32_t)(btmr_id) << (BTMR_INSTANCE_BITPOS));\r
+BFD09A7C 0008145E LBU V0, 8(S8)
+BFD09A80 25AA SLL V1, V0, 5
+92: }\r
+BFD09A8C 0FBE MOVE SP, S8
+BFD09A8E 4BC1 LW S8, 4(SP)
+BFD09A90 4C05 ADDIU SP, SP, 8
+BFD09A92 459F JR16 RA
+BFD09A94 0C00 NOP
+93: \r
+94: /**\r
+95: * btmr_sleep_en - Enable/Disable clock gating on idle of a \r
+96: * timer \r
+97: * \r
+98: * @author sworley (8/16/2013)\r
+99: * \r
+100: * @param tmr_id zero based timer ID.\r
+101: * @param pwr_on boolean true=ON, false=OFF\r
+102: */\r
+103: void btmr_sleep_en(uint8_t tmr_id, uint8_t sleep_en)\r
+104: {\r
+BFD05DC0 4FF1 ADDIU SP, SP, -32
+BFD05DC2 CBE7 SW RA, 28(SP)
+BFD05DC4 CBC6 SW S8, 24(SP)
+BFD05DC6 0FDD MOVE S8, SP
+BFD05DC8 0C64 MOVE V1, A0
+BFD05DCA 0C45 MOVE V0, A1
+BFD05DCC 0020187E SB V1, 32(S8)
+BFD05DD0 0024185E SB V0, 36(S8)
+105: uint32_t sleep_mask;\r
+106: uint32_t volatile * p;\r
+107: \r
+108: sleep_mask = 0ul;\r
+BFD05DD4 0014F81E SW ZERO, 20(S8)
+109: if ( btmr_valid(tmr_id) ) {\r
+BFD05DD8 0020145E LBU V0, 32(S8)
+BFD05DDC 0C82 MOVE A0, V0
+BFD05DDE 4D2277E8 JALS btmr_valid
+BFD05DE0 4D22 ADDIU T1, T1, 1
+BFD05DE2 0C00 NOP
+BFD05DE4 004040E2 BEQZC V0, 0xBFD05E68
+110: if (btmr_slp_info[tmr_id].slp_reg) {\r
+BFD05DE8 0020147E LBU V1, 32(S8)
+BFD05DEC BFD141A2 LUI V0, 0xBFD1
+BFD05DEE 25B2BFD1 LDC1 F30, 9650(S1)
+BFD05DF0 25B2 SLL V1, V1, 1
+BFD05DF2 9F243042 ADDIU V0, V0, -24796
+BFD05DF4 05269F24 LWC1 F25, 1318(A0)
+BFD05DF6 0526 ADDU V0, V1, V0
+BFD05DF8 0920 LBU V0, 0(V0)
+BFD05DFA 000840E2 BEQZC V0, 0xBFD05E0E
+111: p = (uint32_t volatile *)&(PCR->EC_SLEEP_EN2);\r
+BFD05DFE A00841A2 LUI V0, 0xA008
+BFD05E02 01245042 ORI V0, V0, 292
+BFD05E06 0010F85E SW V0, 16(S8)
+BFD05E08 CC070010 BREAK
+BFD05E0A CC07 B 0xBFD05E1A
+BFD05E0C 0C00 NOP
+112: } else {\r
+113: p = (uint32_t volatile *)&(PCR->EC_SLEEP_EN);\r
+BFD05E0E A00841A2 LUI V0, 0xA008
+BFD05E12 01085042 ORI V0, V0, 264
+BFD05E16 0010F85E SW V0, 16(S8)
+114: }\r
+115: sleep_mask = (1ul << btmr_slp_info[tmr_id].bit_pos);\r
+BFD05E1A 0020147E LBU V1, 32(S8)
+BFD05E1E BFD141A2 LUI V0, 0xBFD1
+BFD05E20 25B2BFD1 LDC1 F30, 9650(S1)
+BFD05E22 25B2 SLL V1, V1, 1
+BFD05E24 9F243042 ADDIU V0, V0, -24796
+BFD05E26 05269F24 LWC1 F25, 1318(A0)
+BFD05E28 0526 ADDU V0, V1, V0
+BFD05E2A 0921 LBU V0, 1(V0)
+BFD05E2C ED81 LI V1, 1
+BFD05E2E 10100062 SLLV V0, V0, V1
+BFD05E30 F85E1010 ADDI ZERO, S0, -1954
+BFD05E32 0014F85E SW V0, 20(S8)
+116: if (sleep_en) {\r
+BFD05E36 0024145E LBU V0, 36(S8)
+BFD05E3A 000B40E2 BEQZC V0, 0xBFD05E54
+117: *p |= (sleep_mask);\r
+BFD05E3E 0010FC5E LW V0, 16(S8)
+BFD05E42 69A0 LW V1, 0(V0)
+BFD05E44 0014FC5E LW V0, 20(S8)
+BFD05E48 44DA OR16 V1, V0
+BFD05E4A 0010FC5E LW V0, 16(S8)
+BFD05E4E E9A0 SW V1, 0(V0)
+BFD05E50 CC0B B 0xBFD05E68
+BFD05E52 0C00 NOP
+118: } else {\r
+119: *p &= ~(sleep_mask);\r
+BFD05E54 0010FC5E LW V0, 16(S8)
+BFD05E58 69A0 LW V1, 0(V0)
+BFD05E5A 0014FC5E LW V0, 20(S8)
+BFD05E5E 4412 NOT16 V0, V0
+BFD05E60 449A AND16 V1, V0
+BFD05E62 0010FC5E LW V0, 16(S8)
+BFD05E66 E9A0 SW V1, 0(V0)
+120: }\r
+121: }\r
+122: }\r
+BFD05E68 0FBE MOVE SP, S8
+BFD05E6A 4BE7 LW RA, 28(SP)
+BFD05E6C 4BC6 LW S8, 24(SP)
+BFD05E6E 4C11 ADDIU SP, SP, 32
+BFD05E70 459F JR16 RA
+BFD05E72 0C00 NOP
+123: \r
+124: /**\r
+125: * btmr_reset - Peform soft reset of specified timer.\r
+126: * \r
+127: * @author sworley \r
+128: * \r
+129: * @param tmr_id 0-based Timer ID \r
+130: * @note Soft reset set all registers to POR values.\r
+131: * Spins 256 times waiting on hardware to clear reset bit. \r
+132: */\r
+133: void btmr_reset(uint8_t tmr_id)\r
+134: {\r
+BFD07988 4FF1 ADDIU SP, SP, -32
+BFD0798A CBE7 SW RA, 28(SP)
+BFD0798C CBC6 SW S8, 24(SP)
+BFD0798E 0FDD MOVE S8, SP
+BFD07990 0C44 MOVE V0, A0
+BFD07992 0020185E SB V0, 32(S8)
+135: BTMR_TypeDef * p;\r
+136: uint32_t wait_cnt;\r
+137: \r
+138: if (btmr_valid(tmr_id)) {\r
+BFD07996 0020145E LBU V0, 32(S8)
+BFD0799A 0C82 MOVE A0, V0
+BFD0799C 4D2277E8 JALS btmr_valid
+BFD0799E 4D22 ADDIU T1, T1, 1
+BFD079A0 0C00 NOP
+BFD079A2 002540E2 BEQZC V0, 0xBFD079F0
+139: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
+BFD079A6 0020145E LBU V0, 32(S8)
+BFD079AA 0C82 MOVE A0, V0
+BFD079AC 4D3877E8 JALS btmr_get_hw_addr
+BFD079AE 4D38 ADDIU T1, T1, -4
+BFD079B0 0C00 NOP
+BFD079B2 0014F85E SW V0, 20(S8)
+140: \r
+141: p->CONTROL = (BTMR_CNTL_SOFT_RESET);\r
+BFD079B6 0014FC5E LW V0, 20(S8)
+BFD079B8 ED900014 SUB SP, S4, ZERO
+BFD079BA ED90 LI V1, 16
+BFD079BC E9A4 SW V1, 16(V0)
+142: \r
+143: wait_cnt = 256ul;\r
+BFD079BE 01003040 ADDIU V0, ZERO, 256
+BFD079C2 0010F85E SW V0, 16(S8)
+144: do {\r
+145: if ( 0ul == (p->CONTROL & BTMR_CNTL_SOFT_RESET) ) {\r
+BFD079C6 0014FC5E LW V0, 20(S8)
+BFD079CA 6924 LW V0, 16(V0)
+BFD079CC 2D28 ANDI V0, V0, 0x10
+BFD079CE 000E40E2 BEQZC V0, 0xBFD079EE
+146: break;\r
+BFD079EE 0C00 NOP
+147: }\r
+148: } \r
+149: while ( wait_cnt-- ); \r
+BFD079D2 0010FC5E LW V0, 16(S8)
+BFD079D4 00400010 SRL ZERO, S0, 0
+BFD079D6 13900040 SLTU V0, ZERO, V0
+BFD079D8 2D2D1390 ADDI GP, S0, 11565
+BFD079DA 2D2D ANDI V0, V0, 0xFF
+BFD079DC 0010FC7E LW V1, 16(S8)
+BFD079E0 6DBE ADDIU V1, V1, -1
+BFD079E2 0010F87E SW V1, 16(S8)
+BFD079E6 FFEE40A2 BNEZC V0, 0xBFD079C6
+BFD079E8 CC02FFEE LW RA, -13310(T6)
+BFD079EA CC02 B 0xBFD079F0
+BFD079EC 0C00 NOP
+150: } \r
+151: }\r
+BFD079F0 0FBE MOVE SP, S8
+BFD079F2 4BE7 LW RA, 28(SP)
+BFD079F4 4BC6 LW S8, 24(SP)
+BFD079F6 4C11 ADDIU SP, SP, 32
+BFD079F8 459F JR16 RA
+BFD079FA 0C00 NOP
+152: \r
+153: /**\r
+154: * btmr_init - Initialize specified timer\r
+155: * @param zero based timer ID\r
+156: * @param tmr_cntl b[15:0] = timer configuration flags.\r
+157: * @param initial_count \r
+158: * @param preload_count \r
+159: * @note performs a soft reset of the timer before \r
+160: * configuration.\r
+161: */\r
+162: void btmr_init(uint8_t tmr_id, \r
+163: uint16_t tmr_cntl,\r
+164: uint16_t prescaler,\r
+165: uint32_t initial_count,\r
+166: uint32_t preload_count)\r
+167: {\r
+BFD056FC 4FF1 ADDIU SP, SP, -32
+BFD056FE CBE7 SW RA, 28(SP)
+BFD05700 CBC6 SW S8, 24(SP)
+BFD05702 0FDD MOVE S8, SP
+BFD05704 0C65 MOVE V1, A1
+BFD05706 0C46 MOVE V0, A2
+BFD05708 002CF8FE SW A3, 44(S8)
+BFD0570C 0020189E SB A0, 32(S8)
+BFD05710 0024387E SH V1, 36(S8)
+BFD05714 0028385E SH V0, 40(S8)
+168: BTMR_TypeDef * pTMR;\r
+169: \r
+170: pTMR = NULL;\r
+BFD05718 0010F81E SW ZERO, 16(S8)
+171: \r
+172: if (btmr_valid(tmr_id)) {\r
+BFD0571C 0020145E LBU V0, 32(S8)
+BFD05720 0C82 MOVE A0, V0
+BFD05722 4D2277E8 JALS btmr_valid
+BFD05724 4D22 ADDIU T1, T1, 1
+BFD05726 0C00 NOP
+BFD05728 004840E2 BEQZC V0, 0xBFD057BC
+173: btmr_reset(tmr_id);\r
+BFD0572C 0020145E LBU V0, 32(S8)
+BFD05730 0C82 MOVE A0, V0
+BFD05732 3CC477E8 JALS btmr_reset
+BFD05734 0C003CC4 LH A2, 3072(A0)
+BFD05736 0C00 NOP
+174: \r
+175: pTMR = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
+BFD05738 0020145E LBU V0, 32(S8)
+BFD0573C 0C82 MOVE A0, V0
+BFD0573E 4D3877E8 JALS btmr_get_hw_addr
+BFD05740 4D38 ADDIU T1, T1, -4
+BFD05742 0C00 NOP
+BFD05744 0010F85E SW V0, 16(S8)
+176: \r
+177: // Ungate timer clocks and program prescale\r
+178: pTMR->CONTROL = ((uint32_t)prescaler << 16) + (BTMR_CNTL_ENABLE);\r
+BFD05748 0028345E LHU V0, 40(S8)
+BFD0574C 80000042 SLL V0, V0, 16
+BFD05750 6DA0 ADDIU V1, V0, 1
+BFD05752 0010FC5E LW V0, 16(S8)
+BFD05756 E9A4 SW V1, 16(V0)
+179: \r
+180: // Program Preload & initial counter value\r
+181: pTMR->PRELOAD = preload_count;\r
+BFD05758 0010FC5E LW V0, 16(S8)
+BFD0575C 0030FC7E LW V1, 48(S8)
+BFD05760 E9A1 SW V1, 4(V0)
+182: pTMR->COUNT = initial_count;\r
+BFD05762 0010FC5E LW V0, 16(S8)
+BFD05766 002CFC7E LW V1, 44(S8)
+BFD0576A E9A0 SW V1, 0(V0)
+183: \r
+184: // Program control register, interrupt enable, and clear status\r
+185: if (tmr_cntl & BTMR_COUNT_UP) {\r
+BFD0576C 0024345E LHU V0, 36(S8)
+BFD05770 2D24 ANDI V0, V0, 0x4
+BFD05772 000840E2 BEQZC V0, 0xBFD05786
+186: pTMR->CONTROL |= BTMR_CNTL_COUNT_UP; \r
+BFD05776 0010FC5E LW V0, 16(S8)
+BFD0577A 6924 LW V0, 16(V0)
+BFD0577C 00045062 ORI V1, V0, 4
+BFD05780 0010FC5E LW V0, 16(S8)
+BFD05784 E9A4 SW V1, 16(V0)
+187: }\r
+188: if (tmr_cntl & BTMR_AUTO_RESTART) {\r
+BFD05786 0024345E LHU V0, 36(S8)
+BFD0578A 2D26 ANDI V0, V0, 0x8
+BFD0578C 000840E2 BEQZC V0, 0xBFD057A0
+189: pTMR->CONTROL |= BTMR_CNTL_AUTO_RESTART; \r
+BFD05790 0010FC5E LW V0, 16(S8)
+BFD05794 6924 LW V0, 16(V0)
+BFD05796 00085062 ORI V1, V0, 8
+BFD0579A 0010FC5E LW V0, 16(S8)
+BFD0579E E9A4 SW V1, 16(V0)
+190: }\r
+191: \r
+192: if (tmr_cntl & BTMR_INT_EN) {\r
+BFD057A0 0024345E LHU V0, 36(S8)
+BFD057A4 2D21 ANDI V0, V0, 0x1
+BFD057A6 2D2D ANDI V0, V0, 0xFF
+BFD057A8 000840E2 BEQZC V0, 0xBFD057BC
+193: pTMR->INTEN = 0x01u; // enable first\r
+BFD057AC 0010FC5E LW V0, 16(S8)
+BFD057B0 ED81 LI V1, 1
+BFD057B2 89AC SB V1, 12(V0)
+194: pTMR->STATUS = 0x01u; // clear status\r
+BFD057B4 0010FC5E LW V0, 16(S8)
+BFD057B8 ED81 LI V1, 1
+BFD057BA 89A8 SB V1, 8(V0)
+195: }\r
+196: }\r
+197: }\r
+BFD057BC 0FBE MOVE SP, S8
+BFD057BE 4BE7 LW RA, 28(SP)
+BFD057C0 4BC6 LW S8, 24(SP)
+BFD057C2 4C11 ADDIU SP, SP, 32
+BFD057C4 459F JR16 RA
+BFD057C6 0C00 NOP
+198: \r
+199: /**\r
+200: * btmr_ien - Enable specified timer's interrupt.\r
+201: * \r
+202: * @author sworley \r
+203: * \r
+204: * @param tmr_id zero based timer ID.\r
+205: * @param ien Non-zero enable interrupt in timer block, 0 \r
+206: * disable.\r
+207: * @note Write 0 or 1 to timer's INTEN register.\r
+208: */\r
+209: void btmr_ien(uint8_t tmr_id, uint8_t ien)\r
+210: {\r
+BFD08330 4FF1 ADDIU SP, SP, -32
+BFD08332 CBE7 SW RA, 28(SP)
+BFD08334 CBC6 SW S8, 24(SP)
+BFD08336 0FDD MOVE S8, SP
+BFD08338 0C64 MOVE V1, A0
+BFD0833A 0C45 MOVE V0, A1
+BFD0833C 0020187E SB V1, 32(S8)
+BFD08340 0024185E SB V0, 36(S8)
+211: BTMR_TypeDef * p;\r
+212: \r
+213: if (btmr_valid(tmr_id)) {\r
+BFD08344 0020145E LBU V0, 32(S8)
+BFD08348 0C82 MOVE A0, V0
+BFD0834A 4D2277E8 JALS btmr_valid
+BFD0834C 4D22 ADDIU T1, T1, 1
+BFD0834E 0C00 NOP
+BFD08350 001540E2 BEQZC V0, 0xBFD0837E
+214: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
+BFD08354 0020145E LBU V0, 32(S8)
+BFD08358 0C82 MOVE A0, V0
+BFD0835A 4D3877E8 JALS btmr_get_hw_addr
+BFD0835C 4D38 ADDIU T1, T1, -4
+BFD0835E 0C00 NOP
+BFD08360 0010F85E SW V0, 16(S8)
+215: \r
+216: if (ien) {\r
+BFD08364 0024145E LBU V0, 36(S8)
+BFD08368 000640E2 BEQZC V0, 0xBFD08378
+217: p->INTEN = (BTMR_INTEN); \r
+BFD0836C 0010FC5E LW V0, 16(S8)
+BFD08370 ED81 LI V1, 1
+BFD08372 89AC SB V1, 12(V0)
+BFD08374 CC04 B 0xBFD0837E
+BFD08376 0C00 NOP
+218: } else {\r
+219: p->INTEN = (BTMR_INTDIS); \r
+BFD08378 0010FC5E LW V0, 16(S8)
+BFD0837A 882C0010 EXT ZERO, S0, 0, 18
+BFD0837C 882C SB S0, 12(V0)
+220: }\r
+221: }\r
+222: }\r
+BFD0837E 0FBE MOVE SP, S8
+BFD08380 4BE7 LW RA, 28(SP)
+BFD08382 4BC6 LW S8, 24(SP)
+BFD08384 4C11 ADDIU SP, SP, 32
+BFD08386 459F JR16 RA
+BFD08388 0C00 NOP
+223: \r
+224: /**\r
+225: * tmr_get_clr_ists - Read Timer interrupt status and clear if\r
+226: * set. \r
+227: * \r
+228: * @author sworley \r
+229: * \r
+230: * @param tmr_id zero based timer ID.\r
+231: * \r
+232: * @return uint8_t true (Timer interrupt status set) else false. \r
+233: * @note If timer interrupt status is set then clear it before \r
+234: * returning.\r
+235: */\r
+236: uint8_t btmr_get_clr_ists(uint8_t tmr_id)\r
+237: {\r
+BFD0838C 4FF1 ADDIU SP, SP, -32
+BFD0838E CBE7 SW RA, 28(SP)
+BFD08390 CBC6 SW S8, 24(SP)
+BFD08392 0FDD MOVE S8, SP
+BFD08394 0C44 MOVE V0, A0
+BFD08396 0020185E SB V0, 32(S8)
+238: BTMR_TypeDef * p;\r
+239: uint8_t rc;\r
+240: \r
+241: rc = (MEC14XX_FALSE);\r
+BFD0839A 0010181E SB ZERO, 16(S8)
+242: if (btmr_valid(tmr_id)) {\r
+BFD0839E 0020145E LBU V0, 32(S8)
+BFD083A2 0C82 MOVE A0, V0
+BFD083A4 4D2277E8 JALS btmr_valid
+BFD083A6 4D22 ADDIU T1, T1, 1
+BFD083A8 0C00 NOP
+BFD083AA 001540E2 BEQZC V0, 0xBFD083D8
+243: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
+BFD083AE 0020145E LBU V0, 32(S8)
+BFD083B2 0C82 MOVE A0, V0
+BFD083B4 4D3877E8 JALS btmr_get_hw_addr
+BFD083B6 4D38 ADDIU T1, T1, -4
+BFD083B8 0C00 NOP
+BFD083BA 0014F85E SW V0, 20(S8)
+244: \r
+245: if ( p->STATUS ) {\r
+BFD083BE 0014FC5E LW V0, 20(S8)
+BFD083C2 0928 LBU V0, 8(V0)
+BFD083C4 2D2D ANDI V0, V0, 0xFF
+BFD083C6 000740E2 BEQZC V0, 0xBFD083D8
+246: p->STATUS = (BTMR_STATUS_ACTIVE);\r
+BFD083CA 0014FC5E LW V0, 20(S8)
+BFD083CE ED81 LI V1, 1
+BFD083D0 89A8 SB V1, 8(V0)
+247: rc = true;\r
+BFD083D2 ED01 LI V0, 1
+BFD083D4 0010185E SB V0, 16(S8)
+248: }\r
+249: }\r
+250: return rc;\r
+BFD083D8 0010145E LBU V0, 16(S8)
+251: }\r
+BFD083DC 0FBE MOVE SP, S8
+BFD083DE 4BE7 LW RA, 28(SP)
+BFD083E0 4BC6 LW S8, 24(SP)
+BFD083E2 4C11 ADDIU SP, SP, 32
+BFD083E4 459F JR16 RA
+BFD083E6 0C00 NOP
+252: \r
+253: /**\r
+254: * btmr_reload - Force timer to reload counter from preload \r
+255: * register. \r
+256: * \r
+257: * @param tmr_id zero based timer ID. \r
+258: * @note Hardware will only reload counter if timer is running. \r
+259: */\r
+260: void btmr_reload(uint8_t tmr_id)\r
+261: {\r
+BFD086B0 4FF1 ADDIU SP, SP, -32
+BFD086B2 CBE7 SW RA, 28(SP)
+BFD086B4 CBC6 SW S8, 24(SP)
+BFD086B6 0FDD MOVE S8, SP
+BFD086B8 0C44 MOVE V0, A0
+BFD086BA 0020185E SB V0, 32(S8)
+262: BTMR_TypeDef * p;\r
+263: \r
+264: if ( btmr_valid(tmr_id) ) {\r
+BFD086BE 0020145E LBU V0, 32(S8)
+BFD086C2 0C82 MOVE A0, V0
+BFD086C4 4D2277E8 JALS btmr_valid
+BFD086C6 4D22 ADDIU T1, T1, 1
+BFD086C8 0C00 NOP
+BFD086CA 001640E2 BEQZC V0, 0xBFD086FA
+265: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
+BFD086CE 0020145E LBU V0, 32(S8)
+BFD086D2 0C82 MOVE A0, V0
+BFD086D4 4D3877E8 JALS btmr_get_hw_addr
+BFD086D6 4D38 ADDIU T1, T1, -4
+BFD086D8 0C00 NOP
+BFD086DA 0010F85E SW V0, 16(S8)
+266: \r
+267: if (p->CONTROL & BTMR_CNTL_START) {\r
+BFD086DE 0010FC5E LW V0, 16(S8)
+BFD086E2 6924 LW V0, 16(V0)
+BFD086E4 2D2A ANDI V0, V0, 0x20
+BFD086E6 000840E2 BEQZC V0, 0xBFD086FA
+268: p->CONTROL |= BTMR_CNTL_RELOAD;\r
+BFD086EA 0010FC5E LW V0, 16(S8)
+BFD086EE 6924 LW V0, 16(V0)
+BFD086F0 00405062 ORI V1, V0, 64
+BFD086F4 0010FC5E LW V0, 16(S8)
+BFD086F8 E9A4 SW V1, 16(V0)
+269: }\r
+270: }\r
+271: }\r
+BFD086FA 0FBE MOVE SP, S8
+BFD086FC 4BE7 LW RA, 28(SP)
+BFD086FE 4BC6 LW S8, 24(SP)
+BFD08700 4C11 ADDIU SP, SP, 32
+BFD08702 459F JR16 RA
+BFD08704 0C00 NOP
+272: \r
+273: /**\r
+274: * btmr_set_count - Program timer's counter register.\r
+275: * \r
+276: * @author sworley \r
+277: * \r
+278: * @param tmr_id zero based timer ID\r
+279: * @param count new counter value \r
+280: * @note Timer hardware may implement a 16-bit or 32-bit \r
+281: * hardware counter. If the timer is 16-bit only the lower\r
+282: * 16-bits of the count paramter are used.\r
+283: */\r
+284: void btmr_set_count(uint8_t tmr_id, uint32_t count)\r
+285: {\r
+BFD090FC 4FF1 ADDIU SP, SP, -32
+BFD090FE CBE7 SW RA, 28(SP)
+BFD09100 CBC6 SW S8, 24(SP)
+BFD09102 0FDD MOVE S8, SP
+BFD09104 0C44 MOVE V0, A0
+BFD09106 0024F8BE SW A1, 36(S8)
+BFD0910A 0020185E SB V0, 32(S8)
+286: BTMR_TypeDef * p;\r
+287: \r
+288: if (btmr_valid(tmr_id)) {\r
+BFD0910E 0020145E LBU V0, 32(S8)
+BFD09112 0C82 MOVE A0, V0
+BFD09114 4D2277E8 JALS btmr_valid
+BFD09116 4D22 ADDIU T1, T1, 1
+BFD09118 0C00 NOP
+BFD0911A 000D40E2 BEQZC V0, 0xBFD09138
+289: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
+BFD0911E 0020145E LBU V0, 32(S8)
+BFD09122 0C82 MOVE A0, V0
+BFD09124 4D3877E8 JALS btmr_get_hw_addr
+BFD09126 4D38 ADDIU T1, T1, -4
+BFD09128 0C00 NOP
+BFD0912A 0010F85E SW V0, 16(S8)
+290: \r
+291: p->COUNT = count;\r
+BFD0912E 0010FC5E LW V0, 16(S8)
+BFD09132 0024FC7E LW V1, 36(S8)
+BFD09136 E9A0 SW V1, 0(V0)
+292: }\r
+293: }\r
+BFD09138 0FBE MOVE SP, S8
+BFD0913A 4BE7 LW RA, 28(SP)
+BFD0913C 4BC6 LW S8, 24(SP)
+BFD0913E 4C11 ADDIU SP, SP, 32
+BFD09140 459F JR16 RA
+BFD09142 0C00 NOP
+294: \r
+295: /**\r
+296: * btmr_count - Return current value of timer's count register.\r
+297: * \r
+298: * @author sworley \r
+299: * \r
+300: * @param tmr_id zero based timer ID.\r
+301: * \r
+302: * @return uint32_t timer count may be 32 or 16 bits depending \r
+303: * upon the hardware. On MEC1322 Timers 0-3 are 16-bit\r
+304: * and Timers 4-5 are 32-bit.\r
+305: */\r
+306: uint32_t btmr_count(uint8_t tmr_id)\r
+307: {\r
+BFD08D40 4FF1 ADDIU SP, SP, -32
+BFD08D42 CBE7 SW RA, 28(SP)
+BFD08D44 CBC6 SW S8, 24(SP)
+BFD08D46 0FDD MOVE S8, SP
+BFD08D48 0C44 MOVE V0, A0
+BFD08D4A 0020185E SB V0, 32(S8)
+308: BTMR_TypeDef * p;\r
+309: uint32_t cnt;\r
+310: \r
+311: cnt = 0ul;\r
+BFD08D4E 0010F81E SW ZERO, 16(S8)
+312: if ( btmr_valid(tmr_id) ) {\r
+BFD08D52 0020145E LBU V0, 32(S8)
+BFD08D56 0C82 MOVE A0, V0
+BFD08D58 4D2277E8 JALS btmr_valid
+BFD08D5A 4D22 ADDIU T1, T1, 1
+BFD08D5C 0C00 NOP
+BFD08D5E 000D40E2 BEQZC V0, 0xBFD08D7C
+313: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
+BFD08D62 0020145E LBU V0, 32(S8)
+BFD08D66 0C82 MOVE A0, V0
+BFD08D68 4D3877E8 JALS btmr_get_hw_addr
+BFD08D6A 4D38 ADDIU T1, T1, -4
+BFD08D6C 0C00 NOP
+BFD08D6E 0014F85E SW V0, 20(S8)
+314: cnt = (uint32_t)(p->COUNT);\r
+BFD08D72 0014FC5E LW V0, 20(S8)
+BFD08D76 6920 LW V0, 0(V0)
+BFD08D78 0010F85E SW V0, 16(S8)
+315: }\r
+316: \r
+317: return cnt;\r
+BFD08D7C 0010FC5E LW V0, 16(S8)
+318: }\r
+BFD08D80 0FBE MOVE SP, S8
+BFD08D82 4BE7 LW RA, 28(SP)
+BFD08D84 4BC6 LW S8, 24(SP)
+BFD08D86 4C11 ADDIU SP, SP, 32
+BFD08D88 459F JR16 RA
+BFD08D8A 0C00 NOP
+319: \r
+320: /**\r
+321: * btmr_start - Start timer counting.\r
+322: * \r
+323: * @author sworley \r
+324: * \r
+325: * @param tmr_id zero based timer ID.\r
+326: */\r
+327: void btmr_start(uint8_t btmr_id)\r
+328: {\r
+BFD08D8C 4FF1 ADDIU SP, SP, -32
+BFD08D8E CBE7 SW RA, 28(SP)
+BFD08D90 CBC6 SW S8, 24(SP)
+BFD08D92 0FDD MOVE S8, SP
+BFD08D94 0C44 MOVE V0, A0
+BFD08D96 0020185E SB V0, 32(S8)
+329: BTMR_TypeDef * p;\r
+330: \r
+331: if ( btmr_valid(btmr_id) ) {\r
+BFD08D9A 0020145E LBU V0, 32(S8)
+BFD08D9E 0C82 MOVE A0, V0
+BFD08DA0 4D2277E8 JALS btmr_valid
+BFD08DA2 4D22 ADDIU T1, T1, 1
+BFD08DA4 0C00 NOP
+BFD08DA6 001040E2 BEQZC V0, 0xBFD08DCA
+332: p = (BTMR_TypeDef *)btmr_get_hw_addr(btmr_id);\r
+BFD08DAA 0020145E LBU V0, 32(S8)
+BFD08DAE 0C82 MOVE A0, V0
+BFD08DB0 4D3877E8 JALS btmr_get_hw_addr
+BFD08DB2 4D38 ADDIU T1, T1, -4
+BFD08DB4 0C00 NOP
+BFD08DB6 0010F85E SW V0, 16(S8)
+333: p->CONTROL |= BTMR_CNTL_START;\r
+BFD08DBA 0010FC5E LW V0, 16(S8)
+BFD08DBE 6924 LW V0, 16(V0)
+BFD08DC0 00205062 ORI V1, V0, 32
+BFD08DC4 0010FC5E LW V0, 16(S8)
+BFD08DC8 E9A4 SW V1, 16(V0)
+334: }\r
+335: }\r
+BFD08DCA 0FBE MOVE SP, S8
+BFD08DCC 4BE7 LW RA, 28(SP)
+BFD08DCE 4BC6 LW S8, 24(SP)
+BFD08DD0 4C11 ADDIU SP, SP, 32
+BFD08DD2 459F JR16 RA
+BFD08DD4 0C00 NOP
+336: \r
+337: /**\r
+338: * btmr_stop - Stop timer.\r
+339: * \r
+340: * @author sworley \r
+341: * \r
+342: * @param tmr_id zero based timer ID. \r
+343: * @note When a stopped timer is started again it will reload \r
+344: * the count register from preload value.\r
+345: */\r
+346: void btmr_stop(uint8_t tmr_id)\r
+347: {\r
+BFD08DD8 4FF1 ADDIU SP, SP, -32
+BFD08DDA CBE7 SW RA, 28(SP)
+BFD08DDC CBC6 SW S8, 24(SP)
+BFD08DDE 0FDD MOVE S8, SP
+BFD08DE0 0C44 MOVE V0, A0
+BFD08DE2 0020185E SB V0, 32(S8)
+348: BTMR_TypeDef * p;\r
+349: \r
+350: if (btmr_valid(tmr_id)) {\r
+BFD08DE6 0020145E LBU V0, 32(S8)
+BFD08DEA 0C82 MOVE A0, V0
+BFD08DEC 4D2277E8 JALS btmr_valid
+BFD08DEE 4D22 ADDIU T1, T1, 1
+BFD08DF0 0C00 NOP
+BFD08DF2 001140E2 BEQZC V0, 0xBFD08E18
+351: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
+BFD08DF6 0020145E LBU V0, 32(S8)
+BFD08DFA 0C82 MOVE A0, V0
+BFD08DFC 4D3877E8 JALS btmr_get_hw_addr
+BFD08DFE 4D38 ADDIU T1, T1, -4
+BFD08E00 0C00 NOP
+BFD08E02 0010F85E SW V0, 16(S8)
+352: p->CONTROL &= ~(BTMR_CNTL_START);\r
+BFD08E06 0010FC5E LW V0, 16(S8)
+BFD08E0A 69A4 LW V1, 16(V0)
+BFD08E0C FFDF3040 ADDIU V0, ZERO, -33
+BFD08E0E 449AFFDF LW S8, 17562(RA)
+BFD08E10 449A AND16 V1, V0
+BFD08E12 0010FC5E LW V0, 16(S8)
+BFD08E16 E9A4 SW V1, 16(V0)
+353: }\r
+354: }\r
+BFD08E18 0FBE MOVE SP, S8
+BFD08E1A 4BE7 LW RA, 28(SP)
+BFD08E1C 4BC6 LW S8, 24(SP)
+BFD08E1E 4C11 ADDIU SP, SP, 32
+BFD08E20 459F JR16 RA
+BFD08E22 0C00 NOP
+355: \r
+356: /**\r
+357: * btmr_is_stopped - Return state of timer's START bit.\r
+358: * \r
+359: * @author sworley \r
+360: * \r
+361: * @param tmr_id zero based timer ID.\r
+362: * \r
+363: * @return uint8_t false(timer not started), true(timer started)\r
+364: */\r
+365: uint8_t btmr_is_stopped(uint8_t tmr_id)\r
+366: {\r
+BFD083E8 4FF1 ADDIU SP, SP, -32
+BFD083EA CBE7 SW RA, 28(SP)
+BFD083EC CBC6 SW S8, 24(SP)
+BFD083EE 0FDD MOVE S8, SP
+BFD083F0 0C44 MOVE V0, A0
+BFD083F2 0020185E SB V0, 32(S8)
+367: BTMR_TypeDef * p;\r
+368: uint8_t rc;\r
+369: \r
+370: rc = (MEC14XX_TRUE);\r
+BFD083F6 ED01 LI V0, 1
+BFD083F8 0010185E SB V0, 16(S8)
+371: if (btmr_valid(tmr_id)) {\r
+BFD083FC 0020145E LBU V0, 32(S8)
+BFD08400 0C82 MOVE A0, V0
+BFD08402 4D2277E8 JALS btmr_valid
+BFD08404 4D22 ADDIU T1, T1, 1
+BFD08406 0C00 NOP
+BFD08408 001340E2 BEQZC V0, 0xBFD08432
+372: rc = (MEC14XX_FALSE);\r
+BFD0840C 0010181E SB ZERO, 16(S8)
+373: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
+BFD08410 0020145E LBU V0, 32(S8)
+BFD08414 0C82 MOVE A0, V0
+BFD08416 4D3877E8 JALS btmr_get_hw_addr
+BFD08418 4D38 ADDIU T1, T1, -4
+BFD0841A 0C00 NOP
+BFD0841C 0014F85E SW V0, 20(S8)
+374: if ((p->CONTROL & BTMR_CNTL_START) == 0) {\r
+BFD08420 0014FC5E LW V0, 20(S8)
+BFD08424 6924 LW V0, 16(V0)
+BFD08426 2D2A ANDI V0, V0, 0x20
+BFD08428 000340A2 BNEZC V0, 0xBFD08432
+375: rc = (MEC14XX_TRUE);\r
+BFD0842C ED01 LI V0, 1
+BFD0842E 0010185E SB V0, 16(S8)
+376: }\r
+377: }\r
+378: return rc;\r
+BFD08432 0010145E LBU V0, 16(S8)
+379: }\r
+BFD08436 0FBE MOVE SP, S8
+BFD08438 4BE7 LW RA, 28(SP)
+BFD0843A 4BC6 LW S8, 24(SP)
+BFD0843C 4C11 ADDIU SP, SP, 32
+BFD0843E 459F JR16 RA
+BFD08440 0C00 NOP
+380: \r
+381: \r
+382: /**\r
+383: * btmr_halt - Halt timer counting with no reload on unhalt. \r
+384: * \r
+385: * @author sworley \r
+386: * \r
+387: * @param tmr_id zero based timer ID. \r
+388: * @note A halted timer will not reload the count register when \r
+389: * unhalted, it will continue counting from the current\r
+390: * count value.\r
+391: */\r
+392: void btmr_halt(uint8_t tmr_id)\r
+393: {\r
+BFD08E24 4FF1 ADDIU SP, SP, -32
+BFD08E26 CBE7 SW RA, 28(SP)
+BFD08E28 CBC6 SW S8, 24(SP)
+BFD08E2A 0FDD MOVE S8, SP
+BFD08E2C 0C44 MOVE V0, A0
+BFD08E2E 0020185E SB V0, 32(S8)
+394: BTMR_TypeDef * p;\r
+395: \r
+396: if ( btmr_valid(tmr_id) ) {\r
+BFD08E32 0020145E LBU V0, 32(S8)
+BFD08E36 0C82 MOVE A0, V0
+BFD08E38 4D2277E8 JALS btmr_valid
+BFD08E3A 4D22 ADDIU T1, T1, 1
+BFD08E3C 0C00 NOP
+BFD08E3E 001040E2 BEQZC V0, 0xBFD08E62
+397: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
+BFD08E42 0020145E LBU V0, 32(S8)
+BFD08E46 0C82 MOVE A0, V0
+BFD08E48 4D3877E8 JALS btmr_get_hw_addr
+BFD08E4A 4D38 ADDIU T1, T1, -4
+BFD08E4C 0C00 NOP
+BFD08E4E 0010F85E SW V0, 16(S8)
+398: p->CONTROL |= (BTMR_CNTL_HALT);\r
+BFD08E52 0010FC5E LW V0, 16(S8)
+BFD08E56 6924 LW V0, 16(V0)
+BFD08E58 00805062 ORI V1, V0, 128
+BFD08E5C 0010FC5E LW V0, 16(S8)
+BFD08E60 E9A4 SW V1, 16(V0)
+399: }\r
+400: }\r
+BFD08E62 0FBE MOVE SP, S8
+BFD08E64 4BE7 LW RA, 28(SP)
+BFD08E66 4BC6 LW S8, 24(SP)
+BFD08E68 4C11 ADDIU SP, SP, 32
+BFD08E6A 459F JR16 RA
+BFD08E6C 0C00 NOP
+401: \r
+402: \r
+403: /**\r
+404: * btmr_unhalt - Unhalt timer counting.\r
+405: * \r
+406: * @author sworley \r
+407: * \r
+408: * @param tmr_id zero based timer ID.\r
+409: */\r
+410: void btmr_unhalt(uint8_t tmr_id)\r
+411: {\r
+BFD08E70 4FF1 ADDIU SP, SP, -32
+BFD08E72 CBE7 SW RA, 28(SP)
+BFD08E74 CBC6 SW S8, 24(SP)
+BFD08E76 0FDD MOVE S8, SP
+BFD08E78 0C44 MOVE V0, A0
+BFD08E7A 0020185E SB V0, 32(S8)
+412: BTMR_TypeDef * p;\r
+413: \r
+414: if ( btmr_valid(tmr_id) ) {\r
+BFD08E7E 0020145E LBU V0, 32(S8)
+BFD08E82 0C82 MOVE A0, V0
+BFD08E84 4D2277E8 JALS btmr_valid
+BFD08E86 4D22 ADDIU T1, T1, 1
+BFD08E88 0C00 NOP
+BFD08E8A 001140E2 BEQZC V0, 0xBFD08EB0
+415: p = (BTMR_TypeDef *)btmr_get_hw_addr(tmr_id);\r
+BFD08E8E 0020145E LBU V0, 32(S8)
+BFD08E92 0C82 MOVE A0, V0
+BFD08E94 4D3877E8 JALS btmr_get_hw_addr
+BFD08E96 4D38 ADDIU T1, T1, -4
+BFD08E98 0C00 NOP
+BFD08E9A 0010F85E SW V0, 16(S8)
+416: p->CONTROL &= ~(BTMR_CNTL_HALT);\r
+BFD08E9E 0010FC5E LW V0, 16(S8)
+BFD08EA2 69A4 LW V1, 16(V0)
+BFD08EA4 FF7F3040 ADDIU V0, ZERO, -129
+BFD08EA6 449AFF7F LW K1, 17562(RA)
+BFD08EA8 449A AND16 V1, V0
+BFD08EAA 0010FC5E LW V0, 16(S8)
+BFD08EAE E9A4 SW V1, 16(V0)
+417: }\r
+418: }\r
+BFD08EB0 0FBE MOVE SP, S8
+BFD08EB2 4BE7 LW RA, 28(SP)
+BFD08EB4 4BC6 LW S8, 24(SP)
+BFD08EB6 4C11 ADDIU SP, SP, 32
+BFD08EB8 459F JR16 RA
+BFD08EBA 0C00 NOP
+419: \r
+420: \r
+421: /* end mec14xx_timers.c */\r
+422: /** @}\r
+423: */\r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_tfdp.c ---------
+1: /*****************************************************************************\r
+2: * © 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file mec14xx_tfdp.c\r
+22: *MEC14xx Trace FIFO Data Port hardware access\r
+23: */\r
+24: /** @defgroup MEC14xx Peripherals TFDP\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_pcr.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_trace_func.h"\r
+34: \r
+35: \r
+36: #ifdef ENABLE_TFDP_TRACE\r
+37: \r
+38: #undef TFDP_PIN_1\r
+39: #undef TFDP_PIN_2\r
+40: \r
+41: \r
+42: #define TFDP_PIN_1 (GPIO_0116_ID) // Func1 PullUp enabled\r
+43: #define TFDP_PIN_2 (GPIO_0117_ID) // Func1 PullUp enabled\r
+44: \r
+45: \r
+46: \r
+47: static void tfdp_xmit_header(uint16_t nbr)\r
+48: {\r
+BFD0906C 4FB0 ADDIU SP, SP, -8
+BFD0906E CBC1 SW S8, 4(SP)
+BFD09070 0FDD MOVE S8, SP
+BFD09072 0C44 MOVE V0, A0
+BFD09074 0008385E SH V0, 8(S8)
+49: TFDP->DATA = TFDP_FRAME_START;\r
+BFD09078 A00041A2 LUI V0, 0xA000
+BFD0907C 8C005042 ORI V0, V0, -29696
+BFD0907E 8C00 BEQZ S0, 0xBFD09080
+BFD09080 FFFD3060 ADDIU V1, ZERO, -3
+BFD09082 89A0FFFD LW RA, -30304(SP)
+BFD09084 89A0 SB V1, 0(V0)
+50: TFDP_DELAY();\r
+51: \r
+52: TFDP->DATA = (uint8_t)nbr;\r
+BFD09086 A00041A2 LUI V0, 0xA000
+BFD0908A 8C005042 ORI V0, V0, -29696
+BFD0908C 8C00 BEQZ S0, 0xBFD0908E
+BFD0908E 0008347E LHU V1, 8(S8)
+BFD09092 2DBD ANDI V1, V1, 0xFF
+BFD09094 89A0 SB V1, 0(V0)
+53: TFDP_DELAY();\r
+54: TFDP->DATA = (uint8_t)(nbr >> 8);\r
+BFD09096 A00041A2 LUI V0, 0xA000
+BFD0909A 8C005042 ORI V0, V0, -29696
+BFD0909C 8C00 BEQZ S0, 0xBFD0909E
+BFD0909E 0008347E LHU V1, 8(S8)
+BFD090A2 25B1 SRL V1, V1, 8
+BFD090A4 2DBF ANDI V1, V1, 0xFFFF
+BFD090A6 2DBD ANDI V1, V1, 0xFF
+BFD090A8 89A0 SB V1, 0(V0)
+55: TFDP_DELAY();\r
+56: }\r
+BFD090AA 0FBE MOVE SP, S8
+BFD090AC 4BC1 LW S8, 4(SP)
+BFD090AE 4C05 ADDIU SP, SP, 8
+BFD090B0 459F JR16 RA
+BFD090B2 0C00 NOP
+57: \r
+58: \r
+59: static void tfdp_xmit_hword(uint16_t hword)\r
+60: {\r
+BFD09648 4FB0 ADDIU SP, SP, -8
+BFD0964A CBC1 SW S8, 4(SP)
+BFD0964C 0FDD MOVE S8, SP
+BFD0964E 0C44 MOVE V0, A0
+BFD09650 0008385E SH V0, 8(S8)
+61: TFDP->DATA = (uint8_t)hword;\r
+BFD09654 A00041A2 LUI V0, 0xA000
+BFD09658 8C005042 ORI V0, V0, -29696
+BFD0965A 8C00 BEQZ S0, 0xBFD0965C
+BFD0965C 0008347E LHU V1, 8(S8)
+BFD09660 2DBD ANDI V1, V1, 0xFF
+BFD09662 89A0 SB V1, 0(V0)
+62: TFDP_DELAY();\r
+63: TFDP->DATA = (uint8_t)(hword >> 8);\r
+BFD09664 A00041A2 LUI V0, 0xA000
+BFD09668 8C005042 ORI V0, V0, -29696
+BFD0966A 8C00 BEQZ S0, 0xBFD0966C
+BFD0966C 0008347E LHU V1, 8(S8)
+BFD09670 25B1 SRL V1, V1, 8
+BFD09672 2DBF ANDI V1, V1, 0xFFFF
+BFD09674 2DBD ANDI V1, V1, 0xFF
+BFD09676 89A0 SB V1, 0(V0)
+64: TFDP_DELAY();\r
+65: }\r
+BFD09678 0FBE MOVE SP, S8
+BFD0967A 4BC1 LW S8, 4(SP)
+BFD0967C 4C05 ADDIU SP, SP, 8
+BFD0967E 459F JR16 RA
+BFD09680 0C00 NOP
+66: \r
+67: \r
+68: static void tfdp_xmit_word(uint32_t word)\r
+69: {\r
+BFD08CF4 4FF9 ADDIU SP, SP, -16
+BFD08CF6 CBC3 SW S8, 12(SP)
+BFD08CF8 0FDD MOVE S8, SP
+BFD08CFA 0010F89E SW A0, 16(S8)
+70: uint8_t i;\r
+71: \r
+72: for (i = 0u; i < 4; i++) {\r
+BFD08CFE 0000181E SB ZERO, 0(S8)
+BFD08D02 CC13 B 0xBFD08D2A
+BFD08D04 0C00 NOP
+BFD08D20 0000145E LBU V0, 0(S8)
+BFD08D24 6D20 ADDIU V0, V0, 1
+BFD08D26 0000185E SB V0, 0(S8)
+BFD08D2A 0000145E LBU V0, 0(S8)
+BFD08D2E 0004B042 SLTIU V0, V0, 4
+BFD08D32 FFE840A2 BNEZC V0, 0xBFD08D06
+BFD08D34 0FBEFFE8 LW RA, 4030(T0)
+73: TFDP->DATA = (uint8_t)word;\r
+BFD08D06 A00041A2 LUI V0, 0xA000
+BFD08D0A 8C005042 ORI V0, V0, -29696
+BFD08D0C 8C00 BEQZ S0, 0xBFD08D0E
+BFD08D0E 0010FC7E LW V1, 16(S8)
+BFD08D12 2DBD ANDI V1, V1, 0xFF
+BFD08D14 89A0 SB V1, 0(V0)
+74: word >>= 8; \r
+BFD08D16 0010FC5E LW V0, 16(S8)
+BFD08D1A 2521 SRL V0, V0, 8
+BFD08D1C 0010F85E SW V0, 16(S8)
+75: TFDP_DELAY();\r
+76: }\r
+77: }\r
+BFD08D36 0FBE MOVE SP, S8
+BFD08D38 4BC3 LW S8, 12(SP)
+BFD08D3A 4C09 ADDIU SP, SP, 16
+BFD08D3C 459F JR16 RA
+BFD08D3E 0C00 NOP
+78: \r
+79: \r
+80: /**\r
+81: * tfdp_sleep_en - Gate clocks On/Off to TFDP block when idle\r
+82: * \r
+83: * @author C21969 (2/4/2014)\r
+84: * \r
+85: * @param sleep_en (1=Gate clocks when idle), (0=Do not gate \r
+86: * clocks when idle)\r
+87: */\r
+88: void tfdp_sleep_en(uint8_t sleep_en)\r
+89: {\r
+BFD088AC 4FB0 ADDIU SP, SP, -8
+BFD088AE CBC1 SW S8, 4(SP)
+BFD088B0 0FDD MOVE S8, SP
+BFD088B2 0C44 MOVE V0, A0
+BFD088B4 0008185E SB V0, 8(S8)
+90: if ( sleep_en ) {\r
+BFD088B8 0008145E LBU V0, 8(S8)
+BFD088BC 000E40E2 BEQZC V0, 0xBFD088DC
+91: PCR->EC_SLEEP_EN |= (PCR_EC_TFDP_SLP_CLK);\r
+BFD088C0 A00841A2 LUI V0, 0xA008
+BFD088C4 01005042 ORI V0, V0, 256
+BFD088C8 A00841A3 LUI V1, 0xA008
+BFD088CC 01005063 ORI V1, V1, 256
+BFD088D0 69B2 LW V1, 8(V1)
+BFD088D2 00805063 ORI V1, V1, 128
+BFD088D6 E9A2 SW V1, 8(V0)
+BFD088D8 CC0E B 0xBFD088F6
+BFD088DA 0C00 NOP
+92: } else {\r
+93: PCR->EC_SLEEP_EN &= ~(PCR_EC_TFDP_SLP_CLK);\r
+BFD088DC A00841A2 LUI V0, 0xA008
+BFD088E0 01005042 ORI V0, V0, 256
+BFD088E4 A00841A3 LUI V1, 0xA008
+BFD088E8 01005063 ORI V1, V1, 256
+BFD088EC 6A32 LW A0, 8(V1)
+BFD088EE FF7F3060 ADDIU V1, ZERO, -129
+BFD088F0 449CFF7F LW K1, 17564(RA)
+BFD088F2 449C AND16 V1, A0
+BFD088F4 E9A2 SW V1, 8(V0)
+94: }\r
+95: }\r
+BFD088F6 0FBE MOVE SP, S8
+BFD088F8 4BC1 LW S8, 4(SP)
+BFD088FA 4C05 ADDIU SP, SP, 8
+BFD088FC 459F JR16 RA
+BFD088FE 0C00 NOP
+96: \r
+97: \r
+98: /**\r
+99: * tfdp_enable - Init Trace FIFO Data Port\r
+100: * @param boolean true=enable TFDP, false=disable TFDP \r
+101: * @param boolean true=change TFDP pin configuration. \r
+102: * If TFDP is enabled then GPIO103/104 set to Alt. Func. 1 \r
+103: * Else GPIO103/104 set to GPIO input, internal PU enabled. \r
+104: * @note - \r
+105: */\r
+106: void tfdp_enable(uint8_t en, uint8_t pin_cfg)\r
+107: {\r
+BFD032C4 4FF9 ADDIU SP, SP, -16
+BFD032C6 CBC3 SW S8, 12(SP)
+BFD032C8 0FDD MOVE S8, SP
+BFD032CA 0C64 MOVE V1, A0
+BFD032CC 0C45 MOVE V0, A1
+BFD032CE 0010187E SB V1, 16(S8)
+BFD032D2 0014185E SB V0, 20(S8)
+108: uint32_t delay;\r
+109: \r
+110: if (en) {\r
+BFD032D6 0010145E LBU V0, 16(S8)
+BFD032DA 007240E2 BEQZC V0, 0xBFD033C2
+111: \r
+112: if (pin_cfg) {\r
+BFD032DE 0014145E LBU V0, 20(S8)
+BFD032E2 006740E2 BEQZC V0, 0xBFD033B4
+113: // Input with AltOut=1 to drive high when switched to output\r
+114: GPIO_CTRL->REG[TFDP_PIN_1].w = (1ul << 16);\r
+BFD032E6 A00841A2 LUI V0, 0xA008
+BFD032EA 10005042 ORI V0, V0, 4096
+BFD032EC 41A31000 ADDI ZERO, ZERO, 16803
+BFD032EE 000141A3 LUI V1, 0x1
+BFD032F2 0138F862 SW V1, 312(V0)
+115: GPIO_CTRL->REG[TFDP_PIN_2].w = (1ul << 16);\r
+BFD032F6 A00841A2 LUI V0, 0xA008
+BFD032FA 10005042 ORI V0, V0, 4096
+BFD032FC 41A31000 ADDI ZERO, ZERO, 16803
+BFD032FE 000141A3 LUI V1, 0x1
+BFD03302 013CF862 SW V1, 316(V0)
+BFD03304 3040013C SRL T1, GP, 6
+116: \r
+117: delay = 128;\r
+BFD03306 00803040 ADDIU V0, ZERO, 128
+BFD0330A 0000F85E SW V0, 0(S8)
+118: while ( delay-- )\r
+BFD0330E CC03 B 0xBFD03316
+BFD03310 0C00 NOP
+BFD03316 0000FC5E LW V0, 0(S8)
+BFD03318 00400000 SRL ZERO, ZERO, 0
+BFD0331A 13900040 SLTU V0, ZERO, V0
+BFD0331C 2D2D1390 ADDI GP, S0, 11565
+BFD0331E 2D2D ANDI V0, V0, 0xFF
+BFD03320 0000FC7E LW V1, 0(S8)
+BFD03324 6DBE ADDIU V1, V1, -1
+BFD03326 0000F87E SW V1, 0(S8)
+BFD0332A FFF240A2 BNEZC V0, 0xBFD03312
+BFD0332C 41A2FFF2 LW RA, 16802(S2)
+119: {\r
+120: CPU_NOP();\r
+BFD03312 08000000 SSNOP
+BFD03314 0800 LBU S0, 0(S0)
+121: }\r
+122: \r
+123: // GPIO Output enabled (drive based on above settings)\r
+124: GPIO_CTRL->REG[TFDP_PIN_1].w |= (1ul << 9);\r
+BFD0332E A00841A2 LUI V0, 0xA008
+BFD03332 10005042 ORI V0, V0, 4096
+BFD03334 41A31000 ADDI ZERO, ZERO, 16803
+BFD03336 A00841A3 LUI V1, 0xA008
+BFD0333A 10005063 ORI V1, V1, 4096
+BFD0333C FC631000 ADDI ZERO, ZERO, -925
+BFD0333E 0138FC63 LW V1, 312(V1)
+BFD03342 02005063 ORI V1, V1, 512
+BFD03346 0138F862 SW V1, 312(V0)
+125: GPIO_CTRL->REG[TFDP_PIN_2].w |= (1ul << 9);\r
+BFD0334A A00841A2 LUI V0, 0xA008
+BFD0334E 10005042 ORI V0, V0, 4096
+BFD03350 41A31000 ADDI ZERO, ZERO, 16803
+BFD03352 A00841A3 LUI V1, 0xA008
+BFD03356 10005063 ORI V1, V1, 4096
+BFD03358 FC631000 ADDI ZERO, ZERO, -925
+BFD0335A 013CFC63 LW V1, 316(V1)
+BFD0335E 02005063 ORI V1, V1, 512
+BFD03362 013CF862 SW V1, 316(V0)
+BFD03364 3040013C SRL T1, GP, 6
+126: \r
+127: delay = 128;\r
+BFD03366 00803040 ADDIU V0, ZERO, 128
+128: while ( delay-- )\r
+BFD0336A CC04 B 0xBFD03374
+BFD0336C 0000F85E SW V0, 0(S8)
+BFD0336E 00000000 NOP
+BFD03374 0000FC5E LW V0, 0(S8)
+BFD03376 00400000 SRL ZERO, ZERO, 0
+BFD03378 13900040 SLTU V0, ZERO, V0
+BFD0337A 2D2D1390 ADDI GP, S0, 11565
+BFD0337C 2D2D ANDI V0, V0, 0xFF
+BFD0337E 0000FC7E LW V1, 0(S8)
+BFD03382 6DBE ADDIU V1, V1, -1
+BFD03384 0000F87E SW V1, 0(S8)
+BFD03388 FFF240A2 BNEZC V0, 0xBFD03370
+BFD0338A 41A2FFF2 LW RA, 16802(S2)
+129: {\r
+130: CPU_NOP();\r
+BFD03370 08000000 SSNOP
+BFD03372 0800 LBU S0, 0(S0)
+131: }\r
+132: \r
+133: // Switch to Function 1 (TFDP mode b[13:12]=01b)\r
+134: GPIO_CTRL->REG[TFDP_PIN_1].w = (1ul << 16) + (1ul << 12);\r
+BFD0338C A00841A2 LUI V0, 0xA008
+BFD03390 10005042 ORI V0, V0, 4096
+BFD03392 41A31000 ADDI ZERO, ZERO, 16803
+BFD03394 000141A3 LUI V1, 0x1
+BFD03398 10005063 ORI V1, V1, 4096
+BFD0339A F8621000 ADDI ZERO, ZERO, -1950
+BFD0339C 0138F862 SW V1, 312(V0)
+135: GPIO_CTRL->REG[TFDP_PIN_2].w = (1ul << 16) + (1ul << 12);\r
+BFD033A0 A00841A2 LUI V0, 0xA008
+BFD033A4 10005042 ORI V0, V0, 4096
+BFD033A6 41A31000 ADDI ZERO, ZERO, 16803
+BFD033A8 000141A3 LUI V1, 0x1
+BFD033AC 10005063 ORI V1, V1, 4096
+BFD033AE F8621000 ADDI ZERO, ZERO, -1950
+BFD033B0 013CF862 SW V1, 316(V0)
+136: \r
+137: }\r
+138: /* b[0]=1(Enable)\r
+139: * b[1]=0(Shift data out on rising edge) \r
+140: * b[3:2]=00b TFDP shift clocks = AHB_CLK/2\r
+141: * b[6:4]=000b 1 clock inter-packet delay\r
+142: */\r
+143: TFDP->CONTROL = 0x01u;\r
+BFD033B4 A00041A2 LUI V0, 0xA000
+BFD033B8 8C005042 ORI V0, V0, -29696
+BFD033BA 8C00 BEQZ S0, 0xBFD033BC
+BFD033BC ED81 LI V1, 1
+BFD033BE CC16 B 0xBFD033EC
+BFD033C0 89A4 SB V1, 4(V0)
+144: \r
+145: } \r
+146: else\r
+147: {\r
+148: TFDP->CONTROL = 0x00u;\r
+BFD033C2 A00041A2 LUI V0, 0xA000
+BFD033C6 8C005042 ORI V0, V0, -29696
+BFD033C8 8C00 BEQZ S0, 0xBFD033CA
+BFD033CA 8824 SB S0, 4(V0)
+149: if (pin_cfg) \r
+BFD033CC 0014145E LBU V0, 20(S8)
+BFD033D0 000C40E2 BEQZC V0, 0xBFD033EC
+150: { /* Set to POR value (tri-stated input) */\r
+151: GPIO_CTRL->REG[TFDP_PIN_1].w = 0;\r
+BFD033D4 A00841A2 LUI V0, 0xA008
+BFD033D8 10005042 ORI V0, V0, 4096
+BFD033DA F8021000 ADDI ZERO, ZERO, -2046
+BFD033DC 0138F802 SW ZERO, 312(V0)
+152: GPIO_CTRL->REG[TFDP_PIN_2].w = 0;\r
+BFD033E0 A00841A2 LUI V0, 0xA008
+BFD033E4 10005042 ORI V0, V0, 4096
+BFD033E6 F8021000 ADDI ZERO, ZERO, -2046
+BFD033E8 013CF802 SW ZERO, 316(V0)
+153: }\r
+154: }\r
+155: } // end tfdp_enable()\r
+BFD033EC 0FBE MOVE SP, S8
+BFD033EE 4BC3 LW S8, 12(SP)
+BFD033F0 459F JR16 RA
+BFD033F2 4C09 ADDIU SP, SP, 16
+156: \r
+157: \r
+158: /**\r
+159: * TFDPTrace0 - TRACE0: transmit 16-bit trace number lsb first \r
+160: * over TFDP. \r
+161: * \r
+162: * @author sworley \r
+163: * \r
+164: * @param nbr 16-bit trace number \r
+165: * @param b unused\r
+166: * \r
+167: * @return uint8_t always TRUE \r
+168: * @note Function implements critical section. \r
+169: * Uses tool kit __disable_irq()/__enable_irq() pair which may use \r
+170: * priviledged Cortex-Mx instructions. \r
+171: */\r
+172: void TFDPTrace0 ( uint16_t nbr, uint8_t b )\r
+173: {\r
+BFD09A18 4FF5 ADDIU SP, SP, -24
+BFD09A1A CBE5 SW RA, 20(SP)
+BFD09A1C CBC4 SW S8, 16(SP)
+BFD09A1E 0FDD MOVE S8, SP
+BFD09A20 0C64 MOVE V1, A0
+BFD09A22 0C45 MOVE V0, A1
+BFD09A24 0018387E SH V1, 24(S8)
+BFD09A28 001C185E SB V0, 28(S8)
+174: #ifdef ENABLE_TRACE_MASK_IRQ\r
+175: uint32_t isave;\r
+176: \r
+177: isave = mips32r2_dis_intr();\r
+178: #endif\r
+179: \r
+180: (void)b;\r
+181: tfdp_xmit_header(nbr);\r
+BFD09A2C 0018345E LHU V0, 24(S8)
+BFD09A30 0C82 MOVE A0, V0
+BFD09A32 483677E8 JALS tfdp_xmit_header
+BFD09A34 4836 LW AT, 88(SP)
+BFD09A36 0C00 NOP
+182: \r
+183: #ifdef ENABLE_TRACE_MASK_IRQ\r
+184: mips32r2_restore_intr(isave);\r
+185: #endif\r
+186: }\r
+BFD09A38 0FBE MOVE SP, S8
+BFD09A3A 4BE5 LW RA, 20(SP)
+BFD09A3C 4BC4 LW S8, 16(SP)
+BFD09A3E 4C0D ADDIU SP, SP, 24
+BFD09A40 459F JR16 RA
+BFD09A42 0C00 NOP
+187: \r
+188: \r
+189: /**\r
+190: * TRDPTrace1 - TRACE1: transmit 16-bit trace number lsb first \r
+191: * and 16-bit data lsb first over TFDP. \r
+192: * \r
+193: * @author sworley \r
+194: * \r
+195: * @param nbr 16-bit trace number \r
+196: * @param b unused \r
+197: * @param uint32_t p1 16-bit data1 in b[15:0]\r
+198: * \r
+199: * @return uint8_t always TRUE \r
+200: * @note Function implements critical section. \r
+201: * Uses tool kit __disable_irq()/__enable_irq() pair which may use \r
+202: * priviledged Cortex-Mx instructions. \r
+203: */\r
+204: void TFDPTrace1 ( uint16_t nbr, uint8_t b, uint32_t p1 )\r
+205: {\r
+BFD094A0 4FF5 ADDIU SP, SP, -24
+BFD094A2 CBE5 SW RA, 20(SP)
+BFD094A4 CBC4 SW S8, 16(SP)
+BFD094A6 0FDD MOVE S8, SP
+BFD094A8 0C64 MOVE V1, A0
+BFD094AA 0C45 MOVE V0, A1
+BFD094AC 0020F8DE SW A2, 32(S8)
+BFD094B0 0018387E SH V1, 24(S8)
+BFD094B4 001C185E SB V0, 28(S8)
+206: #ifdef ENABLE_TRACE_MASK_IRQ\r
+207: uint32_t isave;\r
+208: \r
+209: isave = mips32r2_dis_intr();\r
+210: #endif\r
+211: (void)b;\r
+212: tfdp_xmit_header(nbr);\r
+BFD094B8 0018345E LHU V0, 24(S8)
+BFD094BC 0C82 MOVE A0, V0
+BFD094BE 483677E8 JALS tfdp_xmit_header
+BFD094C0 4836 LW AT, 88(SP)
+BFD094C2 0C00 NOP
+213: tfdp_xmit_hword(p1);\r
+BFD094C4 0020FC5E LW V0, 32(S8)
+BFD094C8 2D2F ANDI V0, V0, 0xFFFF
+BFD094CA 0C82 MOVE A0, V0
+BFD094CC 4B2477E8 JALS tfdp_xmit_hword
+BFD094CE 4B24 LW T9, 16(SP)
+BFD094D0 0C00 NOP
+214: \r
+215: #ifdef ENABLE_TRACE_MASK_IRQ\r
+216: mips32r2_restore_intr(isave);\r
+217: #endif\r
+218: }\r
+BFD094D2 0FBE MOVE SP, S8
+BFD094D4 4BE5 LW RA, 20(SP)
+BFD094D6 4BC4 LW S8, 16(SP)
+BFD094D8 4C0D ADDIU SP, SP, 24
+BFD094DA 459F JR16 RA
+BFD094DC 0C00 NOP
+219: \r
+220: \r
+221: /**\r
+222: * TFDPTrace2 - TRACE2: transmit 16-bit trace number lsb first \r
+223: * and two 16-bit data parameters lsb first over TFDP.\r
+224: * \r
+225: * @author sworley \r
+226: * \r
+227: * @param nbr trace number\r
+228: * @param b unused\r
+229: * @param uint32_t p1 16-bit data1 in b[15:0]\r
+230: * @param uint32_t p2 16-bit data2 in b[15:0]\r
+231: * \r
+232: * @return uint8_t always TRUE \r
+233: * @note Uses tool kit functions to save/disable/restore \r
+234: * interrupts for critical section. These may use\r
+235: * priviledged instructions.\r
+236: */\r
+237: void TFDPTrace2 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2 )\r
+238: {\r
+BFD08A44 4FF5 ADDIU SP, SP, -24
+BFD08A46 CBE5 SW RA, 20(SP)
+BFD08A48 CBC4 SW S8, 16(SP)
+BFD08A4A 0FDD MOVE S8, SP
+BFD08A4C 0C64 MOVE V1, A0
+BFD08A4E 0C45 MOVE V0, A1
+BFD08A50 0020F8DE SW A2, 32(S8)
+BFD08A54 0024F8FE SW A3, 36(S8)
+BFD08A58 0018387E SH V1, 24(S8)
+BFD08A5C 001C185E SB V0, 28(S8)
+239: #ifdef ENABLE_TRACE_MASK_IRQ\r
+240: uint32_t isave;\r
+241: \r
+242: isave = mips32r2_dis_intr();\r
+243: #endif\r
+244: (void)b;\r
+245: tfdp_xmit_header(nbr);\r
+BFD08A60 0018345E LHU V0, 24(S8)
+BFD08A64 0C82 MOVE A0, V0
+BFD08A66 483677E8 JALS tfdp_xmit_header
+BFD08A68 4836 LW AT, 88(SP)
+BFD08A6A 0C00 NOP
+246: tfdp_xmit_hword(p1);\r
+BFD08A6C 0020FC5E LW V0, 32(S8)
+BFD08A70 2D2F ANDI V0, V0, 0xFFFF
+BFD08A72 0C82 MOVE A0, V0
+BFD08A74 4B2477E8 JALS tfdp_xmit_hword
+BFD08A76 4B24 LW T9, 16(SP)
+BFD08A78 0C00 NOP
+247: tfdp_xmit_hword(p2);\r
+BFD08A7A 0024FC5E LW V0, 36(S8)
+BFD08A7E 2D2F ANDI V0, V0, 0xFFFF
+BFD08A80 0C82 MOVE A0, V0
+BFD08A82 4B2477E8 JALS tfdp_xmit_hword
+BFD08A84 4B24 LW T9, 16(SP)
+BFD08A86 0C00 NOP
+248: \r
+249: #ifdef ENABLE_TRACE_MASK_IRQ\r
+250: mips32r2_restore_intr(isave);\r
+251: #endif\r
+252: }\r
+BFD08A88 0FBE MOVE SP, S8
+BFD08A8A 4BE5 LW RA, 20(SP)
+BFD08A8C 4BC4 LW S8, 16(SP)
+BFD08A8E 4C0D ADDIU SP, SP, 24
+BFD08A90 459F JR16 RA
+BFD08A92 0C00 NOP
+253: \r
+254: \r
+255: /**\r
+256: * TFDPTrace3 - TRACE3: transmit 16-bit trace number lsb first \r
+257: * and three 16-bit data parameters lsb first over TFDP.\r
+258: * \r
+259: * @author sworley \r
+260: * \r
+261: * @param nbr trace number\r
+262: * @param b unused\r
+263: * @param uint32_t p1 16-bit data1 in b[15:0]\r
+264: * @param uint32_t p2 16-bit data2 in b[15:0]\r
+265: * @param uint32_t p3 16-bit data3 in b[15:0]\r
+266: * \r
+267: * @return uint8_t always TRUE \r
+268: * @note Uses tool kit functions to save/disable/restore \r
+269: * interrupts for critical section. These may use\r
+270: * priviledged instructions. \r
+271: */\r
+272: void TFDPTrace3 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3)\r
+273: {\r
+BFD08274 4FF5 ADDIU SP, SP, -24
+BFD08276 CBE5 SW RA, 20(SP)
+BFD08278 CBC4 SW S8, 16(SP)
+BFD0827A 0FDD MOVE S8, SP
+BFD0827C 0C64 MOVE V1, A0
+BFD0827E 0C45 MOVE V0, A1
+BFD08280 0020F8DE SW A2, 32(S8)
+BFD08284 0024F8FE SW A3, 36(S8)
+BFD08288 0018387E SH V1, 24(S8)
+BFD0828C 001C185E SB V0, 28(S8)
+274: #ifdef ENABLE_TRACE_MASK_IRQ\r
+275: uint32_t isave;\r
+276: \r
+277: isave = mips32r2_dis_intr();\r
+278: #endif \r
+279: (void)b;\r
+280: tfdp_xmit_header(nbr);\r
+BFD08290 0018345E LHU V0, 24(S8)
+BFD08294 0C82 MOVE A0, V0
+BFD08296 483677E8 JALS tfdp_xmit_header
+BFD08298 4836 LW AT, 88(SP)
+BFD0829A 0C00 NOP
+281: tfdp_xmit_hword(p1);\r
+BFD0829C 0020FC5E LW V0, 32(S8)
+BFD082A0 2D2F ANDI V0, V0, 0xFFFF
+BFD082A2 0C82 MOVE A0, V0
+BFD082A4 4B2477E8 JALS tfdp_xmit_hword
+BFD082A6 4B24 LW T9, 16(SP)
+BFD082A8 0C00 NOP
+282: tfdp_xmit_hword(p2);\r
+BFD082AA 0024FC5E LW V0, 36(S8)
+BFD082AE 2D2F ANDI V0, V0, 0xFFFF
+BFD082B0 0C82 MOVE A0, V0
+BFD082B2 4B2477E8 JALS tfdp_xmit_hword
+BFD082B4 4B24 LW T9, 16(SP)
+BFD082B6 0C00 NOP
+283: tfdp_xmit_hword(p3);\r
+BFD082B8 0028FC5E LW V0, 40(S8)
+BFD082BC 2D2F ANDI V0, V0, 0xFFFF
+BFD082BE 0C82 MOVE A0, V0
+BFD082C0 4B2477E8 JALS tfdp_xmit_hword
+BFD082C2 4B24 LW T9, 16(SP)
+BFD082C4 0C00 NOP
+284: \r
+285: #ifdef ENABLE_TRACE_MASK_IRQ\r
+286: if ( isave & (1ul<<0) )\r
+287: {\r
+288: mips32r2_en_intr();\r
+289: }\r
+290: #endif\r
+291: }\r
+BFD082C6 0FBE MOVE SP, S8
+BFD082C8 4BE5 LW RA, 20(SP)
+BFD082CA 4BC4 LW S8, 16(SP)
+BFD082CC 4C0D ADDIU SP, SP, 24
+BFD082CE 459F JR16 RA
+BFD082D0 0C00 NOP
+292: \r
+293: \r
+294: /**\r
+295: * TFDPTrace4 - TRACE3: transmit 16-bit trace number lsb first \r
+296: * and four 16-bit data parameters lsb first over TFDP.\r
+297: * \r
+298: * @author sworley \r
+299: * \r
+300: * @param nbr trace number\r
+301: * @param b unused\r
+302: * @param uint32_t p1 16-bit data1 in b[15:0]\r
+303: * @param uint32_t p2 16-bit data2 in b[15:0]\r
+304: * @param uint32_t p3 16-bit data3 in b[15:0]\r
+305: * @param uint32_t p4 16-bit data4 in b[15:0]\r
+306: * \r
+307: * @return uint8_t always TRUE \r
+308: * @note Uses tool kit functions to save/disable/restore \r
+309: * interrupts for critical section. These may use\r
+310: * priviledged instructions. \r
+311: */\r
+312: void TFDPTrace4 ( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4)\r
+313: {\r
+BFD07C28 4FF5 ADDIU SP, SP, -24
+BFD07C2A CBE5 SW RA, 20(SP)
+BFD07C2C CBC4 SW S8, 16(SP)
+BFD07C2E 0FDD MOVE S8, SP
+BFD07C30 0C64 MOVE V1, A0
+BFD07C32 0C45 MOVE V0, A1
+BFD07C34 0020F8DE SW A2, 32(S8)
+BFD07C38 0024F8FE SW A3, 36(S8)
+BFD07C3C 0018387E SH V1, 24(S8)
+BFD07C40 001C185E SB V0, 28(S8)
+314: #ifdef ENABLE_TRACE_MASK_IRQ\r
+315: uint32_t isave;\r
+316: \r
+317: isave = mips32r2_dis_intr();\r
+318: #endif\r
+319: (void)b;\r
+320: tfdp_xmit_header(nbr);\r
+BFD07C44 0018345E LHU V0, 24(S8)
+BFD07C48 0C82 MOVE A0, V0
+BFD07C4A 483677E8 JALS tfdp_xmit_header
+BFD07C4C 4836 LW AT, 88(SP)
+BFD07C4E 0C00 NOP
+321: tfdp_xmit_hword(p1);\r
+BFD07C50 0020FC5E LW V0, 32(S8)
+BFD07C54 2D2F ANDI V0, V0, 0xFFFF
+BFD07C56 0C82 MOVE A0, V0
+BFD07C58 4B2477E8 JALS tfdp_xmit_hword
+BFD07C5A 4B24 LW T9, 16(SP)
+BFD07C5C 0C00 NOP
+322: tfdp_xmit_hword(p2);\r
+BFD07C5E 0024FC5E LW V0, 36(S8)
+BFD07C62 2D2F ANDI V0, V0, 0xFFFF
+BFD07C64 0C82 MOVE A0, V0
+BFD07C66 4B2477E8 JALS tfdp_xmit_hword
+BFD07C68 4B24 LW T9, 16(SP)
+BFD07C6A 0C00 NOP
+323: tfdp_xmit_hword(p3);\r
+BFD07C6C 0028FC5E LW V0, 40(S8)
+BFD07C70 2D2F ANDI V0, V0, 0xFFFF
+BFD07C72 0C82 MOVE A0, V0
+BFD07C74 4B2477E8 JALS tfdp_xmit_hword
+BFD07C76 4B24 LW T9, 16(SP)
+BFD07C78 0C00 NOP
+324: tfdp_xmit_hword(p4);\r
+BFD07C7A 002CFC5E LW V0, 44(S8)
+BFD07C7E 2D2F ANDI V0, V0, 0xFFFF
+BFD07C80 0C82 MOVE A0, V0
+BFD07C82 4B2477E8 JALS tfdp_xmit_hword
+BFD07C84 4B24 LW T9, 16(SP)
+BFD07C86 0C00 NOP
+325: \r
+326: #ifdef ENABLE_TRACE_MASK_IRQ\r
+327: if ( isave & (1ul<<0) )\r
+328: {\r
+329: mips32r2_en_intr();\r
+330: }\r
+331: #endif\r
+332: }\r
+BFD07C88 0FBE MOVE SP, S8
+BFD07C8A 4BE5 LW RA, 20(SP)
+BFD07C8C 4BC4 LW S8, 16(SP)
+BFD07C8E 4C0D ADDIU SP, SP, 24
+BFD07C90 459F JR16 RA
+BFD07C92 0C00 NOP
+333: \r
+334: \r
+335: /** \r
+336: * TFDPTrace11 - Transmit one 32-bit data item over TFDP \r
+337: * \r
+338: * @param nbr trace number\r
+339: * @param b unused \r
+340: * @param uint32_t p1 32-bit data to be transmitted\r
+341: * \r
+342: */\r
+343: void TFDPTrace11( uint16_t nbr, uint8_t b, uint32_t p1)\r
+344: {\r
+BFD09684 4FF5 ADDIU SP, SP, -24
+BFD09686 CBE5 SW RA, 20(SP)
+BFD09688 CBC4 SW S8, 16(SP)
+BFD0968A 0FDD MOVE S8, SP
+BFD0968C 0C64 MOVE V1, A0
+BFD0968E 0C45 MOVE V0, A1
+BFD09690 0020F8DE SW A2, 32(S8)
+BFD09694 0018387E SH V1, 24(S8)
+BFD09698 001C185E SB V0, 28(S8)
+345: #ifdef ENABLE_TRACE_MASK_IRQ\r
+346: uint32_t isave;\r
+347: \r
+348: isave = mips32r2_dis_intr();\r
+349: #endif \r
+350: (void)b;\r
+351: tfdp_xmit_header(nbr);\r
+BFD0969C 0018345E LHU V0, 24(S8)
+BFD096A0 0C82 MOVE A0, V0
+BFD096A2 483677E8 JALS tfdp_xmit_header
+BFD096A4 4836 LW AT, 88(SP)
+BFD096A6 0C00 NOP
+352: tfdp_xmit_word(p1);\r
+BFD096A8 0020FC9E LW A0, 32(S8)
+BFD096AC 467A77E8 JALS tfdp_xmit_word
+BFD096B0 0C00 NOP
+353: \r
+354: #ifdef ENABLE_TRACE_MASK_IRQ\r
+355: if ( isave & (1ul<<0) )\r
+356: {\r
+357: mips32r2_en_intr();\r
+358: }\r
+359: #endif\r
+360: }\r
+BFD096B2 0FBE MOVE SP, S8
+BFD096B4 4BE5 LW RA, 20(SP)
+BFD096B6 4BC4 LW S8, 16(SP)
+BFD096B8 4C0D ADDIU SP, SP, 24
+BFD096BA 459F JR16 RA
+BFD096BC 0C00 NOP
+361: \r
+362: \r
+363: /** \r
+364: * TFDPTrace12 - Transmit two 32-bit data items over TFDP \r
+365: * \r
+366: * @param nbr trace number\r
+367: * @param b unused \r
+368: * @param uint32_t p1 32-bit data1 to be transmitted\r
+369: * @param uint32_t p2 32-bit data2 to be transmitted\r
+370: * \r
+371: */\r
+372: void TFDPTrace12( uint16_t nbr, uint8_t b, uint32_t p1, uint32_t p2 )\r
+373: {\r
+BFD090B4 4FF5 ADDIU SP, SP, -24
+BFD090B6 CBE5 SW RA, 20(SP)
+BFD090B8 CBC4 SW S8, 16(SP)
+BFD090BA 0FDD MOVE S8, SP
+BFD090BC 0C64 MOVE V1, A0
+BFD090BE 0C45 MOVE V0, A1
+BFD090C0 0020F8DE SW A2, 32(S8)
+BFD090C4 0024F8FE SW A3, 36(S8)
+BFD090C8 0018387E SH V1, 24(S8)
+BFD090CC 001C185E SB V0, 28(S8)
+374: #ifdef ENABLE_TRACE_MASK_IRQ\r
+375: uint32_t isave;\r
+376: \r
+377: isave = mips32r2_dis_intr();\r
+378: #endif \r
+379: (void)b;\r
+380: tfdp_xmit_header(nbr);\r
+BFD090D0 0018345E LHU V0, 24(S8)
+BFD090D4 0C82 MOVE A0, V0
+BFD090D6 483677E8 JALS tfdp_xmit_header
+BFD090D8 4836 LW AT, 88(SP)
+BFD090DA 0C00 NOP
+381: tfdp_xmit_word(p1);\r
+BFD090DC 0020FC9E LW A0, 32(S8)
+BFD090E0 467A77E8 JALS tfdp_xmit_word
+BFD090E4 0C00 NOP
+382: tfdp_xmit_word(p2);\r
+BFD090E6 0024FC9E LW A0, 36(S8)
+BFD090EA 467A77E8 JALS tfdp_xmit_word
+BFD090EE 0C00 NOP
+383: \r
+384: #ifdef ENABLE_TRACE_MASK_IRQ\r
+385: if ( isave & (1ul<<0) )\r
+386: {\r
+387: mips32r2_en_intr();\r
+388: }\r
+389: #endif\r
+390: }\r
+BFD090F0 0FBE MOVE SP, S8
+BFD090F2 4BE5 LW RA, 20(SP)
+BFD090F4 4BC4 LW S8, 16(SP)
+BFD090F6 4C0D ADDIU SP, SP, 24
+BFD090F8 459F JR16 RA
+BFD090FA 0C00 NOP
+391: \r
+392: #endif // #ifdef ENABLE_TFDP_TRACE\r
+393: \r
+394: \r
+395: /* end mec14xx_tfdp.c */\r
+396: /** @}\r
+397: */\r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_system.c -------
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file mec14xx_system.c\r
+22: *MEC14xx system functions\r
+23: */\r
+24: /** @defgroup MEC14xx System\r
+25: * @{\r
+26: */\r
+27: \r
+28: \r
+29: \r
+30: #include "appcfg.h"\r
+31: #include "platform.h"\r
+32: #include "MEC14xx/mec14xx.h"\r
+33: #include "MEC14xx/mec14xx_system.h"\r
+34: #include "MEC14xx/mec14xx_jtvic.h"\r
+35: \r
+36: \r
+37: \r
+38: \r
+39: /**\r
+40: * Initialize the system\r
+41: *\r
+42: * @param none\r
+43: * @return none\r
+44: *\r
+45: * @brief Setup the microcontroller system.\r
+46: * Initialize the System.\r
+47: */\r
+48: void SystemInit (void)\r
+49: {\r
+BFD09E20 4FB0 ADDIU SP, SP, -8
+BFD09E22 CBC1 SW S8, 4(SP)
+BFD09E24 0FDD MOVE S8, SP
+50: \r
+51: PCR->PROC_CLOCK_CNTRL = (PCR_CLOCK_DIVIDER);\r
+BFD09E26 A00841A2 LUI V0, 0xA008
+BFD09E2A 01005042 ORI V0, V0, 256
+BFD09E2E ED81 LI V1, 1
+BFD09E30 E9A8 SW V1, 32(V0)
+52: \r
+53: }\r
+BFD09E32 0FBE MOVE SP, S8
+BFD09E34 4BC1 LW S8, 4(SP)
+BFD09E36 4C05 ADDIU SP, SP, 8
+BFD09E38 459F JR16 RA
+BFD09E3A 0C00 NOP
+54: /*---------------------------------------------------------------------------*/\r
+55: \r
+56: uint32_t sys_code_sram_base(void)\r
+57: {\r
+BFD09EAC 4FB0 ADDIU SP, SP, -8
+BFD09EAE CBC1 SW S8, 4(SP)
+BFD09EB0 0FDD MOVE S8, SP
+58: #if MEC14XX_DEVID == MEC1418_DEVID\r
+59: return (uint32_t)(MEC1418_ICODE_PSRAM_BASE);\r
+60: #else\r
+61: return (uint32_t)(MEC1404_ICODE_PSRAM_BASE);\r
+BFD09EB2 1FD041A2 LUI V0, 0x1FD0
+BFD09EB4 0FBE1FD0 LB S8, 4030(S0)
+62: #endif\r
+63: }\r
+BFD09EB6 0FBE MOVE SP, S8
+BFD09EB8 4BC1 LW S8, 4(SP)
+BFD09EBA 4C05 ADDIU SP, SP, 8
+BFD09EBC 459F JR16 RA
+BFD09EBE 0C00 NOP
+64: /*---------------------------------------------------------------------------*/\r
+65: \r
+66: uint8_t sys_valid_sram_addr(void * const p)\r
+67: {\r
+BFD08CA8 4FF1 ADDIU SP, SP, -32
+BFD08CAA CBE7 SW RA, 28(SP)
+BFD08CAC CBC6 SW S8, 24(SP)
+BFD08CAE 0FDD MOVE S8, SP
+BFD08CB0 0020F89E SW A0, 32(S8)
+68: uint32_t base;\r
+69: \r
+70: base = sys_code_sram_base();\r
+BFD08CB4 4F5677E8 JALS sys_code_sram_base
+BFD08CB6 4F56 ADDIU K0, K0, -5
+BFD08CB8 0C00 NOP
+BFD08CBA 0010F85E SW V0, 16(S8)
+71: \r
+72: if ((uint32_t)p >= base) {\r
+BFD08CBE 0020FC7E LW V1, 32(S8)
+BFD08CC2 0010FC5E LW V0, 16(S8)
+BFD08CC6 13900043 SLTU V0, V1, V0
+BFD08CC8 40A21390 ADDI GP, S0, 16546
+BFD08CCA 000B40A2 BNEZC V0, 0xBFD08CE4
+73: if ((uint32_t)p < (MEC14XX_DCODE_VSRAM_LIMIT)) {\r
+BFD08CCE 0020FC7E LW V1, 32(S8)
+BFD08CD2 BFD241A2 LUI V0, 0xBFD2
+BFD08CD4 0043BFD2 LDC1 F30, 67(S2)
+BFD08CD6 13900043 SLTU V0, V1, V0
+BFD08CD8 40E21390 ADDI GP, S0, 16610
+BFD08CDA 000340E2 BEQZC V0, 0xBFD08CE4
+74: return 1u;\r
+BFD08CDE ED01 LI V0, 1
+BFD08CE0 CC02 B 0xBFD08CE6
+BFD08CE2 0C00 NOP
+75: }\r
+76: }\r
+77: return 0u;\r
+BFD08CE4 0C40 MOVE V0, ZERO
+78: }\r
+BFD08CE6 0FBE MOVE SP, S8
+BFD08CE8 4BE7 LW RA, 28(SP)
+BFD08CEA 4BC6 LW S8, 24(SP)
+BFD08CEC 4C11 ADDIU SP, SP, 32
+BFD08CEE 459F JR16 RA
+BFD08CF0 0C00 NOP
+79: /*---------------------------------------------------------------------------*/\r
+80: \r
+81: uint8_t sys_valid_sram_range(void * const p, const uint32_t byte_len)\r
+82: {\r
+BFD08858 4FF1 ADDIU SP, SP, -32
+BFD0885A CBE7 SW RA, 28(SP)
+BFD0885C CBC6 SW S8, 24(SP)
+BFD0885E 0FDD MOVE S8, SP
+BFD08860 0020F89E SW A0, 32(S8)
+BFD08864 0024F8BE SW A1, 36(S8)
+83: uint32_t base;\r
+84: \r
+85: base = sys_code_sram_base();\r
+BFD08868 4F5677E8 JALS sys_code_sram_base
+BFD0886A 4F56 ADDIU K0, K0, -5
+BFD0886C 0C00 NOP
+BFD0886E 0010F85E SW V0, 16(S8)
+86: \r
+87: if ((uint32_t)p >= base) {\r
+BFD08872 0020FC7E LW V1, 32(S8)
+BFD08876 0010FC5E LW V0, 16(S8)
+BFD0887A 13900043 SLTU V0, V1, V0
+BFD0887C 40A21390 ADDI GP, S0, 16546
+BFD0887E 000E40A2 BNEZC V0, 0xBFD0889E
+88: if (((uint32_t)p + byte_len) < (MEC14XX_DCODE_VSRAM_LIMIT)) {\r
+BFD08882 0020FC7E LW V1, 32(S8)
+BFD08886 0024FC5E LW V0, 36(S8)
+BFD0888A 05A6 ADDU V1, V1, V0
+BFD0888C BFD241A2 LUI V0, 0xBFD2
+BFD0888E 0043BFD2 LDC1 F30, 67(S2)
+BFD08890 13900043 SLTU V0, V1, V0
+BFD08892 40E21390 ADDI GP, S0, 16610
+BFD08894 000340E2 BEQZC V0, 0xBFD0889E
+89: return 1u;\r
+BFD08898 ED01 LI V0, 1
+BFD0889A CC02 B 0xBFD088A0
+BFD0889C 0C00 NOP
+90: }\r
+91: }\r
+92: return 0u;\r
+BFD0889E 0C40 MOVE V0, ZERO
+93: }\r
+BFD088A0 0FBE MOVE SP, S8
+BFD088A2 4BE7 LW RA, 28(SP)
+BFD088A4 4BC6 LW S8, 24(SP)
+BFD088A6 4C11 ADDIU SP, SP, 32
+BFD088A8 459F JR16 RA
+BFD088AA 0C00 NOP
+94: /*---------------------------------------------------------------------------*/\r
+95: \r
+96: void sys_cpu_en_timer(uint32_t counts, uint8_t ien)\r
+97: {\r
+BFD07570 4FF5 ADDIU SP, SP, -24
+BFD07572 CBE5 SW RA, 20(SP)
+BFD07574 CBC4 SW S8, 16(SP)
+BFD07576 0FDD MOVE S8, SP
+BFD07578 0018F89E SW A0, 24(S8)
+BFD0757A 0C450018 CMP.LT.PH ZERO, T8
+BFD0757C 0C45 MOVE V0, A1
+BFD0757E 001C185E SB V0, 28(S8)
+98: /* Disable Counter by setting DC bit to 1 in CP0.Cause */\r
+99: _CP0_BIS_CAUSE(_CP0_CAUSE_DC_MASK);\r
+BFD07582 080041A2 LUI V0, 0x800
+BFD07584 0800 LBU S0, 0(S0)
+BFD07586 00FC006D MFC0 V1, Cause
+BFD07588 0C0000FC SLL A3, GP, 1
+BFD0758A 0C00 NOP
+BFD0758C 44D3 OR16 V0, V1
+BFD0758E 02FC004D MTC0 V0, Cause
+BFD07590 000002FC SLL S7, GP, 0
+BFD07592 18000000 SLL ZERO, ZERO, 3
+BFD07594 FC5E1800 SB ZERO, -930(ZERO)
+100: \r
+101: _CP0_SET_COUNT(counts);\r
+BFD07596 0018FC5E LW V0, 24(S8)
+BFD0759A 02FC0049 MTC0 V0, Count
+BFD0759C 000002FC SLL S7, GP, 0
+BFD0759E 18000000 SLL ZERO, ZERO, 3
+BFD075A0 145E1800 SB ZERO, 5214(ZERO)
+102: if (ien) {\r
+BFD075A2 001C145E LBU V0, 28(S8)
+BFD075A6 000840E2 BEQZC V0, 0xBFD075BA
+BFD075A8 EE100008 MUL SP, T0, ZERO
+103: jtvic_en_source(MEC14xx_GIRQ24_ID, 0, 0);\r
+BFD075AA EE10 LI A0, 16
+BFD075AC 0CA0 MOVE A1, ZERO
+BFD075AE 0CC0 MOVE A2, ZERO
+BFD075B0 3A7C77E8 JALS jtvic_en_source
+BFD075B2 0C003A7C SH S3, 3072(GP)
+BFD075B4 0C00 NOP
+BFD075B6 CC07 B 0xBFD075C6
+BFD075B8 0C00 NOP
+104: } else {\r
+105: jtvic_dis_clr_source(MEC14xx_GIRQ24_ID, 0, 1);\r
+BFD075BA EE10 LI A0, 16
+BFD075BC 0CA0 MOVE A1, ZERO
+BFD075BE EF01 LI A2, 1
+BFD075C0 3A4077E8 JALS jtvic_dis_clr_source
+BFD075C2 0C003A40 SH S2, 3072(ZERO)
+BFD075C4 0C00 NOP
+106: }\r
+107: \r
+108: /* Enable Counter */\r
+109: _CP0_BIC_CAUSE(_CP0_CAUSE_DC_MASK);\r
+BFD075C6 080041A2 LUI V0, 0x800
+BFD075C8 0800 LBU S0, 0(S0)
+BFD075CA 00FC006D MFC0 V1, Cause
+BFD075CC 0C0000FC SLL A3, GP, 1
+BFD075CE 0C00 NOP
+BFD075D0 4412 NOT16 V0, V0
+BFD075D2 4493 AND16 V0, V1
+BFD075D4 02FC004D MTC0 V0, Cause
+BFD075D6 000002FC SLL S7, GP, 0
+BFD075D8 18000000 SLL ZERO, ZERO, 3
+BFD075DA 0FBE1800 SB ZERO, 4030(ZERO)
+110: \r
+111: }\r
+BFD075DC 0FBE MOVE SP, S8
+BFD075DE 4BE5 LW RA, 20(SP)
+BFD075E0 4BC4 LW S8, 16(SP)
+BFD075E2 4C0D ADDIU SP, SP, 24
+BFD075E4 459F JR16 RA
+BFD075E6 0C00 NOP
+112: /*---------------------------------------------------------------------------*/\r
+113: \r
+114: uint32_t cpu_microsecond_count(void)\r
+115: {\r
+BFD09EC0 4FB0 ADDIU SP, SP, -8
+BFD09EC2 CBC1 SW S8, 4(SP)
+BFD09EC4 0FDD MOVE S8, SP
+116: return _CP0_GET_COUNT();\r
+BFD09EC6 00FC0049 MFC0 V0, Count
+117: }\r
+BFD09ECA 0FBE MOVE SP, S8
+BFD09ECC 4BC1 LW S8, 4(SP)
+BFD09ECE 4C05 ADDIU SP, SP, 8
+BFD09ED0 459F JR16 RA
+BFD09ED2 0C00 NOP
+118: /*---------------------------------------------------------------------------*/\r
+119: \r
+120: /*\r
+121: * Assumes M14K CPU is running at clock divide by 1 (48MHz)\r
+122: * 1us = 48 counts. \r
+123: * NOTE: We need to find out from DE what the pipeline rate is. \r
+124: * M14K counter ticks at pipeline rate. \r
+125: */\r
+126: uint32_t cpu_microsecond_interval(uint32_t start_count)\r
+127: {\r
+BFD07DCC 4FF9 ADDIU SP, SP, -16
+BFD07DCE CBC3 SW S8, 12(SP)
+BFD07DD0 0FDD MOVE S8, SP
+BFD07DD2 0010F89E SW A0, 16(S8)
+128: uint32_t curr_count;\r
+129: \r
+130: curr_count = _CP0_GET_COUNT();\r
+BFD07DD6 00FC0049 MFC0 V0, Count
+BFD07DDA 0000F85E SW V0, 0(S8)
+131: if (curr_count >= start_count) {\r
+BFD07DDE 0000FC7E LW V1, 0(S8)
+BFD07DE2 0010FC5E LW V0, 16(S8)
+BFD07DE6 13900043 SLTU V0, V1, V0
+BFD07DE8 40A21390 ADDI GP, S0, 16546
+BFD07DEA 000F40A2 BNEZC V0, 0xBFD07E0C
+132: return ((curr_count - start_count) >> 4)/ 3ul;\r
+BFD07DEE 0000FC7E LW V1, 0(S8)
+BFD07DF2 0010FC5E LW V0, 16(S8)
+BFD07DF6 0527 SUBU V0, V1, V0
+BFD07DF8 25A9 SRL V1, V0, 4
+BFD07DFA ED03 LI V0, 3
+BFD07DFC BB3C0043 DIVU V0, V1
+BFD07DFE 0002BB3C SDC1 F25, 2(GP)
+BFD07E00 703C0002 TEQ V0, ZERO
+BFD07E02 4603703C XORI AT, GP, 17923
+BFD07E04 4603 MFHI V1
+BFD07E06 4642 MFLO V0
+BFD07E08 CC0F B 0xBFD07E28
+BFD07E0A 0C00 NOP
+133: } else {\r
+134: return (((0xFFFFFFFFul - start_count) + curr_count) >> 4) / 3ul;\r
+BFD07E0C 0010FC5E LW V0, 16(S8)
+BFD07E10 441A NOT16 V1, V0
+BFD07E12 0000FC5E LW V0, 0(S8)
+BFD07E16 0526 ADDU V0, V1, V0
+BFD07E18 25A9 SRL V1, V0, 4
+BFD07E1A ED03 LI V0, 3
+BFD07E1C BB3C0043 DIVU V0, V1
+BFD07E1E 0002BB3C SDC1 F25, 2(GP)
+BFD07E20 703C0002 TEQ V0, ZERO
+BFD07E22 4603703C XORI AT, GP, 17923
+BFD07E24 4603 MFHI V1
+BFD07E26 4642 MFLO V0
+135: }\r
+136: }\r
+BFD07E28 0FBE MOVE SP, S8
+BFD07E2A 4BC3 LW S8, 12(SP)
+BFD07E2C 4C09 ADDIU SP, SP, 16
+BFD07E2E 459F JR16 RA
+BFD07E30 0C00 NOP
+137: /*---------------------------------------------------------------------------*/\r
+138: \r
+139: /* end mec14xx_system.c */\r
+140: /** @}\r
+141: */\r
+142: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_jtvic.c --------
+1: /*****************************************************************************\r
+2: * © 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file mec14xx_jtvic.c\r
+22: *MEC14xx JTVIC\r
+23: */\r
+24: /** @defgroup MEC14xx Peripherals JTVIC\r
+25: * @{\r
+26: */\r
+27: \r
+28: \r
+29: #include "appcfg.h"\r
+30: #include "platform.h"\r
+31: #include "MEC14xx/mec14xx.h"\r
+32: #include "MEC14xx/mec14xx_jtvic.h"\r
+33: \r
+34: \r
+35: void jtvic_init(const JTVIC_CFG *ih_table, uint32_t disagg_bitmap, uint32_t cflags)\r
+36: {\r
+BFD03644 4FF9 ADDIU SP, SP, -16
+BFD03646 CBC3 SW S8, 12(SP)
+BFD03648 0FDD MOVE S8, SP
+BFD0364A 0010F89E SW A0, 16(S8)
+BFD0364E 0014F8BE SW A1, 20(S8)
+BFD03652 0018F8DE SW A2, 24(S8)
+37: uint32_t d;\r
+38: uint8_t i, j, pidx;\r
+39: \r
+40: JTVIC_CTRL->w = (1ul << 0); // Soft-Reset\r
+BFD03656 BFFF41A2 LUI V0, 0xBFFF
+BFD03658 5042BFFF LDC1 F31, 20546(RA)
+BFD0365A C5005042 ORI V0, V0, -15104
+BFD0365E ED81 LI V1, 1
+BFD03660 E9A0 SW V1, 0(V0)
+41: d = 0ul;\r
+BFD03662 0000F81E SW ZERO, 0(S8)
+42: if ( cflags & (1ul << 0) ) \r
+BFD03666 0018FC5E LW V0, 24(S8)
+BFD0366A 2D21 ANDI V0, V0, 0x1
+BFD0366C 2D2D ANDI V0, V0, 0xFF
+BFD0366E 000440E2 BEQZC V0, 0xBFD0367A
+BFD03670 30400004 SRL ZERO, A0, 6
+43: {\r
+44: d = (1ul << 8);\r
+BFD03672 01003040 ADDIU V0, ZERO, 256
+BFD03676 0000F85E SW V0, 0(S8)
+45: }\r
+46: JTVIC_CTRL->w = d; // HW does not automatically clear Soft-Reset\r
+BFD0367A BFFF41A2 LUI V0, 0xBFFF
+BFD0367C 5042BFFF LDC1 F31, 20546(RA)
+BFD0367E C5005042 ORI V0, V0, -15104
+BFD03682 0000FC7E LW V1, 0(S8)
+BFD03686 E9A0 SW V1, 0(V0)
+47: \r
+48: for (i = 0u; i < (MEC14xx_NUM_JTVIC_INTS); i++) {\r
+BFD03688 0004181E SB ZERO, 4(S8)
+BFD0368C CC5C B 0xBFD03746
+BFD0368E 0C00 NOP
+BFD0373C 0004145E LBU V0, 4(S8)
+BFD03740 6D20 ADDIU V0, V0, 1
+BFD03742 0004185E SB V0, 4(S8)
+BFD03746 0004145E LBU V0, 4(S8)
+BFD0374A 0013B042 SLTIU V0, V0, 19
+BFD0374E FF9F40A2 BNEZC V0, 0xBFD03690
+BFD03750 41A2FF9F LW GP, 16802(RA)
+49: pidx = i << 2;\r
+BFD03690 0004145E LBU V0, 4(S8)
+BFD03694 2524 SLL V0, V0, 2
+BFD03696 0006185E SB V0, 6(S8)
+50: for (j = 0u; j < 4u; j++) {\r
+BFD0369A 0005181E SB ZERO, 5(S8)
+BFD0369E CC1F B 0xBFD036DE
+BFD036A0 0C00 NOP
+BFD036D4 0005145E LBU V0, 5(S8)
+BFD036D8 6D20 ADDIU V0, V0, 1
+BFD036DA 0005185E SB V0, 5(S8)
+BFD036DE 0005145E LBU V0, 5(S8)
+BFD036E2 0004B042 SLTIU V0, V0, 4
+BFD036E6 FFDC40A2 BNEZC V0, 0xBFD036A2
+BFD036E8 145EFFDC LW S8, 5214(GP)
+51: JTVIC_PRI->REG32[pidx+j] = (uint32_t)(ih_table[i].pri[j]);\r
+BFD036A2 BFFF41A2 LUI V0, 0xBFFF
+BFD036A4 5082BFFF LDC1 F31, 20610(RA)
+BFD036A6 C3005082 ORI A0, V0, -15616
+BFD036AA 0006147E LBU V1, 6(S8)
+BFD036AE 0005145E LBU V0, 5(S8)
+BFD036B2 06A6 ADDU A1, V1, V0
+BFD036B4 0004145E LBU V0, 4(S8)
+BFD036B8 2524 SLL V0, V0, 2
+BFD036BA 25A4 SLL V1, V0, 2
+BFD036BC 0534 ADDU V0, V0, V1
+BFD036BE 0010FC7E LW V1, 16(S8)
+BFD036C2 05A6 ADDU V1, V1, V0
+BFD036C4 0005145E LBU V0, 5(S8)
+BFD036C8 2524 SLL V0, V0, 2
+BFD036CA 0526 ADDU V0, V1, V0
+BFD036CC 69A1 LW V1, 4(V0)
+BFD036CE 2554 SLL V0, A1, 2
+BFD036D0 0528 ADDU V0, A0, V0
+BFD036D2 E9A0 SW V1, 0(V0)
+52: }\r
+53: d = ih_table[i].isr_addr & ~(1ul << 0);\r
+BFD036EA 0004145E LBU V0, 4(S8)
+BFD036EE 2524 SLL V0, V0, 2
+BFD036F0 25A4 SLL V1, V0, 2
+BFD036F2 0534 ADDU V0, V0, V1
+BFD036F4 0010FC7E LW V1, 16(S8)
+BFD036F8 0526 ADDU V0, V1, V0
+BFD036FA 69A0 LW V1, 0(V0)
+BFD036FC FFFE3040 ADDIU V0, ZERO, -2
+BFD036FE 4493FFFE LW RA, 17555(S8)
+BFD03700 4493 AND16 V0, V1
+BFD03702 0000F85E SW V0, 0(S8)
+54: if (disagg_bitmap & (1ul << i)) {\r
+BFD03706 0004145E LBU V0, 4(S8)
+BFD0370A 0014FC7E LW V1, 20(S8)
+BFD0370E 10500062 SRLV V0, V0, V1
+BFD03710 2D211050 ADDI V0, S0, 11553
+BFD03712 2D21 ANDI V0, V0, 0x1
+BFD03714 2D2D ANDI V0, V0, 0xFF
+BFD03716 000640E2 BEQZC V0, 0xBFD03726
+55: d |= (1ul << 0); // dis-aggregate this GIRQ\r
+BFD0371A 0000FC5E LW V0, 0(S8)
+BFD0371E 00015042 ORI V0, V0, 1
+BFD03722 0000F85E SW V0, 0(S8)
+56: }\r
+57: JTVIC_ACTRL->REG32[i] = d;\r
+BFD03726 BFFF41A2 LUI V0, 0xBFFF
+BFD03728 5062BFFF LDC1 F31, 20578(RA)
+BFD0372A C2005062 ORI V1, V0, -15872
+BFD0372E 0004145E LBU V0, 4(S8)
+BFD03732 2524 SLL V0, V0, 2
+BFD03734 0526 ADDU V0, V1, V0
+BFD03736 0000FC7E LW V1, 0(S8)
+BFD0373A E9A0 SW V1, 0(V0)
+58: }\r
+59: \r
+60: JTVIC_GROUP_EN_SET->w = 0xFFFFFFFFul; // Enable GIRQ08 - GIRQ18 (all)\r
+BFD03752 BFFF41A2 LUI V0, 0xBFFF
+BFD03754 5042BFFF LDC1 F31, 20546(RA)
+BFD03756 C5085042 ORI V0, V0, -15096
+BFD0375A EDFF LI V1, -1
+BFD0375C E9A0 SW V1, 0(V0)
+61: \r
+62: }\r
+BFD0375E 0FBE MOVE SP, S8
+BFD03760 4BC3 LW S8, 12(SP)
+BFD03762 4C09 ADDIU SP, SP, 16
+BFD03764 459F JR16 RA
+BFD03766 0C00 NOP
+63: \r
+64: /* Clear JTVIC GIRQn source bit\r
+65: *\r
+66: */\r
+67: void jtvic_clr_source(uint8_t girq_num, uint8_t bit_num)\r
+68: {\r
+BFD089F4 4FB0 ADDIU SP, SP, -8
+BFD089F6 CBC1 SW S8, 4(SP)
+BFD089F8 0FDD MOVE S8, SP
+BFD089FA 0C64 MOVE V1, A0
+BFD089FC 0C45 MOVE V0, A1
+BFD089FE 0008187E SB V1, 8(S8)
+BFD08A02 000C185E SB V0, 12(S8)
+69: if (girq_num < (MEC14xx_NUM_JTVIC_INTS))\r
+BFD08A06 0008145E LBU V0, 8(S8)
+BFD08A0A 0013B042 SLTIU V0, V0, 19
+BFD08A0E 001340E2 BEQZC V0, 0xBFD08A38
+70: {\r
+71: bit_num &= 0x1Fu;\r
+BFD08A12 000C145E LBU V0, 12(S8)
+BFD08A16 2D29 ANDI V0, V0, 0x1F
+BFD08A18 000C185E SB V0, 12(S8)
+72: JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);\r
+BFD08A1C BFFF41A2 LUI V0, 0xBFFF
+BFD08A1E 5082BFFF LDC1 F31, 20610(RA)
+BFD08A20 C0005082 ORI A0, V0, -16384
+BFD08A24 0008145E LBU V0, 8(S8)
+BFD08A28 000C147E LBU V1, 12(S8)
+BFD08A2C EE81 LI A1, 1
+BFD08A2E 181000A3 SLLV V1, V1, A1
+BFD08A30 25281810 SB ZERO, 9512(S0)
+BFD08A32 2528 SLL V0, V0, 4
+BFD08A34 0528 ADDU V0, A0, V0
+BFD08A36 E9A0 SW V1, 0(V0)
+73: }\r
+74: }\r
+BFD08A38 0FBE MOVE SP, S8
+BFD08A3A 4BC1 LW S8, 4(SP)
+BFD08A3C 4C05 ADDIU SP, SP, 8
+BFD08A3E 459F JR16 RA
+BFD08A40 0C00 NOP
+75: \r
+76: \r
+77: /* Disable GIRQn source with optional clearing of source.\r
+78: * girq_num = [0, 18], 0=GIRQ08, 1=GIRQ09, ..., 18=GIRQ26\r
+79: * bit_num = [0, 31]\r
+80: */\r
+81: void jtvic_dis_clr_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src)\r
+82: {\r
+BFD07480 4FB0 ADDIU SP, SP, -8
+BFD07482 CBC1 SW S8, 4(SP)
+BFD07484 0FDD MOVE S8, SP
+BFD07486 0C65 MOVE V1, A1
+BFD07488 0C46 MOVE V0, A2
+BFD0748A 0008189E SB A0, 8(S8)
+BFD0748E 000C187E SB V1, 12(S8)
+BFD07492 0010185E SB V0, 16(S8)
+83: if (girq_num < (MEC14xx_NUM_JTVIC_INTS))\r
+BFD07496 0008145E LBU V0, 8(S8)
+BFD0749A 0013B042 SLTIU V0, V0, 19
+BFD0749E 002540E2 BEQZC V0, 0xBFD074EC
+84: {\r
+85: bit_num &= 0x1Fu;\r
+BFD074A2 000C145E LBU V0, 12(S8)
+BFD074A6 2D29 ANDI V0, V0, 0x1F
+BFD074A8 000C185E SB V0, 12(S8)
+86: JTVIC_GIRQ->REGS[girq_num].EN_CLR = (1ul << bit_num);\r
+BFD074AC BFFF41A2 LUI V0, 0xBFFF
+BFD074AE 5082BFFF LDC1 F31, 20610(RA)
+BFD074B0 C0005082 ORI A0, V0, -16384
+BFD074B4 0008145E LBU V0, 8(S8)
+BFD074B8 000C147E LBU V1, 12(S8)
+BFD074BC EE81 LI A1, 1
+BFD074BE 181000A3 SLLV V1, V1, A1
+BFD074C0 25281810 SB ZERO, 9512(S0)
+BFD074C2 2528 SLL V0, V0, 4
+BFD074C4 0528 ADDU V0, A0, V0
+BFD074C6 E9A2 SW V1, 8(V0)
+87: if ( 0 != clr_src )\r
+BFD074C8 0010145E LBU V0, 16(S8)
+BFD074CC 000E40E2 BEQZC V0, 0xBFD074EC
+88: {\r
+89: JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);\r
+BFD074D0 BFFF41A2 LUI V0, 0xBFFF
+BFD074D2 5082BFFF LDC1 F31, 20610(RA)
+BFD074D4 C0005082 ORI A0, V0, -16384
+BFD074D8 0008145E LBU V0, 8(S8)
+BFD074DC 000C147E LBU V1, 12(S8)
+BFD074E0 EE81 LI A1, 1
+BFD074E2 181000A3 SLLV V1, V1, A1
+BFD074E4 25281810 SB ZERO, 9512(S0)
+BFD074E6 2528 SLL V0, V0, 4
+BFD074E8 0528 ADDU V0, A0, V0
+BFD074EA E9A0 SW V1, 0(V0)
+90: }\r
+91: }\r
+92: }\r
+BFD074EC 0FBE MOVE SP, S8
+BFD074EE 4BC1 LW S8, 4(SP)
+BFD074F0 4C05 ADDIU SP, SP, 8
+BFD074F2 459F JR16 RA
+BFD074F4 0C00 NOP
+93: \r
+94: \r
+95: /* Enable with optional source clear before enable.\r
+96: * girq_num = [0, 18], 0=GIRQ08, 1=GIRQ09, ..., 18=GIRQ26\r
+97: * bit_num = [0, 31]\r
+98: */\r
+99: void jtvic_en_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src)\r
+100: {\r
+BFD074F8 4FB0 ADDIU SP, SP, -8
+BFD074FA CBC1 SW S8, 4(SP)
+BFD074FC 0FDD MOVE S8, SP
+BFD074FE 0C65 MOVE V1, A1
+BFD07500 0C46 MOVE V0, A2
+BFD07502 0008189E SB A0, 8(S8)
+BFD07506 000C187E SB V1, 12(S8)
+BFD0750A 0010185E SB V0, 16(S8)
+101: if (girq_num < (MEC14xx_NUM_JTVIC_INTS))\r
+BFD0750E 0008145E LBU V0, 8(S8)
+BFD07512 0013B042 SLTIU V0, V0, 19
+BFD07516 002540E2 BEQZC V0, 0xBFD07564
+102: {\r
+103: bit_num &= 0x1Fu;\r
+BFD0751A 000C145E LBU V0, 12(S8)
+BFD0751E 2D29 ANDI V0, V0, 0x1F
+BFD07520 000C185E SB V0, 12(S8)
+104: if ( 0 != clr_src )\r
+BFD07524 0010145E LBU V0, 16(S8)
+BFD07528 000E40E2 BEQZC V0, 0xBFD07548
+105: {\r
+106: JTVIC_GIRQ->REGS[girq_num].SOURCE = (1ul << bit_num);\r
+BFD0752C BFFF41A2 LUI V0, 0xBFFF
+BFD0752E 5082BFFF LDC1 F31, 20610(RA)
+BFD07530 C0005082 ORI A0, V0, -16384
+BFD07534 0008145E LBU V0, 8(S8)
+BFD07538 000C147E LBU V1, 12(S8)
+BFD0753C EE81 LI A1, 1
+BFD0753E 181000A3 SLLV V1, V1, A1
+BFD07540 25281810 SB ZERO, 9512(S0)
+BFD07542 2528 SLL V0, V0, 4
+BFD07544 0528 ADDU V0, A0, V0
+BFD07546 E9A0 SW V1, 0(V0)
+107: }\r
+108: JTVIC_GIRQ->REGS[girq_num].EN_SET = (1ul << bit_num);\r
+BFD07548 BFFF41A2 LUI V0, 0xBFFF
+BFD0754A 5082BFFF LDC1 F31, 20610(RA)
+BFD0754C C0005082 ORI A0, V0, -16384
+BFD07550 0008145E LBU V0, 8(S8)
+BFD07554 000C147E LBU V1, 12(S8)
+BFD07558 EE81 LI A1, 1
+BFD0755A 181000A3 SLLV V1, V1, A1
+BFD0755C 25281810 SB ZERO, 9512(S0)
+BFD0755E 2528 SLL V0, V0, 4
+BFD07560 0528 ADDU V0, A0, V0
+BFD07562 E9A1 SW V1, 4(V0)
+109: }\r
+110: }\r
+BFD07564 0FBE MOVE SP, S8
+BFD07566 4BC1 LW S8, 4(SP)
+BFD07568 4C05 ADDIU SP, SP, 8
+BFD0756A 459F JR16 RA
+BFD0756C 0C00 NOP
+111: \r
+112: \r
+113: /* end mec14xx_jtvic.c */\r
+114: /** @}\r
+115: */\r
+116: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_gpio.c ---------
+1: /*****************************************************************************\r
+2: * © 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: \r
+22: /** @file mec14xx_gpio.c\r
+23: *MEC14xx GPIO hardware access\r
+24: */\r
+25: /** @defgroup MEC14xx Peripherals GPIO\r
+26: * @{\r
+27: */\r
+28: \r
+29: \r
+30: #include "appcfg.h"\r
+31: #include "platform.h"\r
+32: #include "MEC14xx/mec14xx.h"\r
+33: #include "MEC14xx/mec14xx_gpio.h"\r
+34: \r
+35: \r
+36: \r
+37: static uint32_t gpio_has_drv_str ( enum gpio_id_t gpio_id );\r
+38: \r
+39: \r
+40: #ifdef ENABLE_GPIO_PIN_VALIDATION\r
+41: \r
+42: static const uint32_t gpio_port_bitmaps[NUM_GPIO_PORTS] = \r
+43: {\r
+44: (GPIO_PORT_A_BITMAP),\r
+45: (GPIO_PORT_B_BITMAP),\r
+46: (GPIO_PORT_C_BITMAP),\r
+47: (GPIO_PORT_D_BITMAP)\r
+48: };\r
+49: \r
+50: #endif\r
+51: \r
+52: // \r
+53: // Drive Strength Register bitmap\r
+54: //\r
+55: static const uint32_t gpio_drv_str_bitmap[NUM_GPIO_PORTS] = \r
+56: {\r
+57: (GPIO_PORT_A_DRVSTR_BITMAP),\r
+58: (GPIO_PORT_B_DRVSTR_BITMAP),\r
+59: (GPIO_PORT_C_DRVSTR_BITMAP),\r
+60: (GPIO_PORT_D_DRVSTR_BITMAP)\r
+61: };\r
+62: \r
+63: \r
+64: struct gpio_cfg \r
+65: {\r
+66: uint16_t bit_mask;\r
+67: uint8_t bit_pos;\r
+68: };\r
+69: \r
+70: static const struct gpio_cfg gpio_cfg_tbl[GPIO_PROP_MAX] = \r
+71: {\r
+72: { 0x0003u, 0x00u },\r
+73: { 0x000Cu, 0x02u },\r
+74: { 0x00F0u, 0x04u },\r
+75: { 0x0100u, 0x08u },\r
+76: { 0x0200u, 0x09u },\r
+77: { 0x0400u, 0x0Au },\r
+78: { 0x0800u, 0x0Bu },\r
+79: { 0x3000u, 0x0Cu },\r
+80: { 0x3FFFu, 0x00u }\r
+81: };\r
+82: \r
+83: static uint32_t gpio_pin_ctrl_addr(enum gpio_id_t gpio_id)\r
+84: {\r
+BFD09B28 4FB0 ADDIU SP, SP, -8
+BFD09B2A CBC1 SW S8, 4(SP)
+BFD09B2C 0FDD MOVE S8, SP
+BFD09B2E 0008F89E SW A0, 8(S8)
+85: return ((uint32_t)(GPIO_BASE) + (uint32_t)(gpio_id << 2));\r
+BFD09B32 0008FC5E LW V0, 8(S8)
+BFD09B36 25A4 SLL V1, V0, 2
+BFD09B38 A00841A2 LUI V0, 0xA008
+BFD09B3C 10005042 ORI V0, V0, 4096
+BFD09B3E 05261000 ADDI ZERO, ZERO, 1318
+BFD09B40 0526 ADDU V0, V1, V0
+86: }\r
+BFD09B42 0FBE MOVE SP, S8
+BFD09B44 4BC1 LW S8, 4(SP)
+BFD09B46 4C05 ADDIU SP, SP, 8
+BFD09B48 459F JR16 RA
+BFD09B4A 0C00 NOP
+87: \r
+88: #ifdef ENABLE_GPIO_PIN_VALIDATION\r
+89: \r
+90: /**\r
+91: * gpio_is_valid - local helper checks if GPIO pin is \r
+92: * implemented in this hardware. \r
+93: * \r
+94: * @author sworley \r
+95: * \r
+96: * @param gpio_id 0-based GPIO ID\r
+97: * \r
+98: * @return uint8_t Non-zero(GPIO Pin implemented), 0(not \r
+99: * implemented).\r
+100: */\r
+101: static uint8_t gpio_is_valid ( enum gpio_id_t gpio_id )\r
+102: {\r
+BFD081B4 4FF9 ADDIU SP, SP, -16
+BFD081B6 CBC3 SW S8, 12(SP)
+BFD081B8 0FDD MOVE S8, SP
+BFD081BA 0010F89E SW A0, 16(S8)
+103: uint16_t gp_bank;\r
+104: \r
+105: gp_bank = 0;\r
+BFD081BE 0000381E SH ZERO, 0(S8)
+106: \r
+107: if ( (uint16_t)gpio_id < (uint16_t)(MAX_GPIO_ID) )\r
+BFD081C2 0010FC5E LW V0, 16(S8)
+BFD081C6 2D2F ANDI V0, V0, 0xFFFF
+BFD081C8 0078B042 SLTIU V0, V0, 120
+BFD081CC 001B40E2 BEQZC V0, 0xBFD08206
+108: {\r
+109: gp_bank = (uint16_t)gpio_id >> 5;\r
+BFD081D0 0010FC5E LW V0, 16(S8)
+BFD081D4 2D2F ANDI V0, V0, 0xFFFF
+BFD081D6 252B SRL V0, V0, 5
+BFD081D8 0000385E SH V0, 0(S8)
+110: if ( gpio_port_bitmaps[gp_bank] & (1 << (gpio_id & 0x001Fu)) )\r
+BFD081DC 0000347E LHU V1, 0(S8)
+BFD081E0 BFD141A2 LUI V0, 0xBFD1
+BFD081E2 25B4BFD1 LDC1 F30, 9652(S1)
+BFD081E4 25B4 SLL V1, V1, 2
+BFD081E6 92543042 ADDIU V0, V0, -28076
+BFD081E8 05269254 SLTI S2, S4, 1318
+BFD081EA 0526 ADDU V0, V1, V0
+BFD081EC 69A0 LW V1, 0(V0)
+BFD081EE 0010FC5E LW V0, 16(S8)
+BFD081F2 2D29 ANDI V0, V0, 0x1F
+BFD081F4 EE01 LI A0, 1
+BFD081F6 10100082 SLLV V0, V0, A0
+BFD081F8 44931010 ADDI ZERO, S0, 17555
+BFD081FA 4493 AND16 V0, V1
+BFD081FC 000340E2 BEQZC V0, 0xBFD08206
+111: { \r
+112: return true;\r
+BFD08200 ED01 LI V0, 1
+BFD08202 CC02 B 0xBFD08208
+BFD08204 0C00 NOP
+113: }\r
+114: }\r
+115: \r
+116: return false;\r
+BFD08206 0C40 MOVE V0, ZERO
+117: }\r
+BFD08208 0FBE MOVE SP, S8
+BFD0820A 4BC3 LW S8, 12(SP)
+BFD0820C 4C09 ADDIU SP, SP, 16
+BFD0820E 459F JR16 RA
+BFD08210 0C00 NOP
+118: \r
+119: #else\r
+120: static uint32_t gpio_is_valid(enum gpio_id_t gpio_id) { return true; }\r
+121: \r
+122: #endif\r
+123: \r
+124: static uint8_t gpio_bank_num(enum gpio_id_t gpio_id)\r
+125: {\r
+BFD09D2C 4FB0 ADDIU SP, SP, -8
+BFD09D2E CBC1 SW S8, 4(SP)
+BFD09D30 0FDD MOVE S8, SP
+BFD09D32 0008F89E SW A0, 8(S8)
+126: return (uint8_t)(gpio_id) >> 5;\r
+BFD09D36 0008FC5E LW V0, 8(S8)
+BFD09D3A 2D2D ANDI V0, V0, 0xFF
+BFD09D3C 252B SRL V0, V0, 5
+BFD09D3E 2D2D ANDI V0, V0, 0xFF
+127: }\r
+BFD09D40 0FBE MOVE SP, S8
+BFD09D42 4BC1 LW S8, 4(SP)
+BFD09D44 4C05 ADDIU SP, SP, 8
+BFD09D46 459F JR16 RA
+BFD09D48 0C00 NOP
+128: \r
+129: \r
+130: static uint8_t gpio_pin_num(enum gpio_id_t gpio_id)\r
+131: {\r
+BFD09D4C 4FB0 ADDIU SP, SP, -8
+BFD09D4E CBC1 SW S8, 4(SP)
+BFD09D50 0FDD MOVE S8, SP
+BFD09D52 0008F89E SW A0, 8(S8)
+132: return (uint8_t)(gpio_id) & 0x1Fu;\r
+BFD09D56 0008FC5E LW V0, 8(S8)
+BFD09D5A 2D2D ANDI V0, V0, 0xFF
+BFD09D5C 2D29 ANDI V0, V0, 0x1F
+BFD09D5E 2D2D ANDI V0, V0, 0xFF
+133: }\r
+BFD09D60 0FBE MOVE SP, S8
+BFD09D62 4BC1 LW S8, 4(SP)
+BFD09D64 4C05 ADDIU SP, SP, 8
+BFD09D66 459F JR16 RA
+BFD09D68 0C00 NOP
+134: \r
+135: \r
+136: /**\r
+137: * gpio_has_drv_str - Local helper to check if GPIO pin has \r
+138: * associated drive strength register. \r
+139: * \r
+140: * @author sworley \r
+141: * \r
+142: * @param gpio_id 0-based GPIO ID\r
+143: * \r
+144: * @return uint32_t 0(No Drive Strength), Non-zero(Physical \r
+145: * address of Drive Strength Register).\r
+146: */\r
+147: static uint32_t gpio_has_drv_str ( enum gpio_id_t gpio_id )\r
+148: {\r
+BFD06644 4FED ADDIU SP, SP, -40
+BFD06646 CBE9 SW RA, 36(SP)
+BFD06648 CBC8 SW S8, 32(SP)
+BFD0664A 0FDD MOVE S8, SP
+BFD0664C 0028F89E SW A0, 40(S8)
+149: uint32_t bank, bitpos, addr;\r
+150: \r
+151: addr = 0ul;\r
+BFD06650 0010F81E SW ZERO, 16(S8)
+152: if ( gpio_id < MAX_GPIO_ID )\r
+BFD06654 0028FC5E LW V0, 40(S8)
+BFD06658 0078B042 SLTIU V0, V0, 120
+BFD0665C 003540E2 BEQZC V0, 0xBFD066CA
+153: {\r
+154: bank = gpio_bank_num(gpio_id);\r
+BFD06660 0028FC9E LW A0, 40(S8)
+BFD06664 4E9677E8 JALS gpio_bank_num
+BFD06666 4E96 ADDIU S4, S4, -5
+BFD06668 0C00 NOP
+BFD0666A 0014F85E SW V0, 20(S8)
+155: bitpos = gpio_pin_num(gpio_id);\r
+BFD0666E 0028FC9E LW A0, 40(S8)
+BFD06672 4EA677E8 JALS gpio_pin_num
+BFD06674 4EA6 ADDIU S5, S5, 3
+BFD06676 0C00 NOP
+BFD06678 0018F85E SW V0, 24(S8)
+156: if ( gpio_drv_str_bitmap[bank] & (1ul << bitpos) )\r
+BFD0667C BFD141A2 LUI V0, 0xBFD1
+BFD0667E FC7EBFD1 LDC1 F30, -898(S1)
+BFD06680 0014FC7E LW V1, 20(S8)
+BFD06684 25B4 SLL V1, V1, 2
+BFD06686 92643042 ADDIU V0, V0, -28060
+BFD06688 05269264 SLTI S3, A0, 1318
+BFD0668A 0526 ADDU V0, V1, V0
+BFD0668C 69A0 LW V1, 0(V0)
+BFD0668E 0018FC5E LW V0, 24(S8)
+BFD06692 10500062 SRLV V0, V0, V1
+BFD06694 2D211050 ADDI V0, S0, 11553
+BFD06696 2D21 ANDI V0, V0, 0x1
+BFD06698 2D2D ANDI V0, V0, 0xFF
+BFD0669A 001640E2 BEQZC V0, 0xBFD066CA
+157: {\r
+158: addr = (GPIO_PCTRL2_BASE) + ((uint32_t)(gpio_id) << 2);\r
+BFD0669E 0028FC5E LW V0, 40(S8)
+BFD066A2 25A4 SLL V1, V0, 2
+BFD066A4 A00841A2 LUI V0, 0xA008
+BFD066A8 15005042 ORI V0, V0, 5376
+BFD066AA 05261500 LBU T0, 1318(ZERO)
+BFD066AC 0526 ADDU V0, V1, V0
+BFD066AE 0010F85E SW V0, 16(S8)
+159: if ( gpio_id > GPIO_0077_ID )\r
+BFD066B2 0028FC5E LW V0, 40(S8)
+BFD066B6 0040B042 SLTIU V0, V0, 64
+BFD066BA 000640A2 BNEZC V0, 0xBFD066CA
+160: {\r
+161: addr -= 0x20ul;\r
+BFD066BE 0010FC5E LW V0, 16(S8)
+BFD066C2 FFE03042 ADDIU V0, V0, -32
+BFD066C4 F85EFFE0 LW RA, -1954(ZERO)
+BFD066C6 0010F85E SW V0, 16(S8)
+162: }\r
+163: }\r
+164: }\r
+165: \r
+166: return addr;\r
+BFD066CA 0010FC5E LW V0, 16(S8)
+167: }\r
+BFD066CE 0FBE MOVE SP, S8
+BFD066D0 4BE9 LW RA, 36(SP)
+BFD066D2 4BC8 LW S8, 32(SP)
+BFD066D4 4C15 ADDIU SP, SP, 40
+BFD066D6 459F JR16 RA
+BFD066D8 0C00 NOP
+168: \r
+169: \r
+170: uint16_t GPIOGetConfig(enum gpio_id_t gpio_id)\r
+171: {\r
+BFD09558 4FF5 ADDIU SP, SP, -24
+BFD0955A CBE5 SW RA, 20(SP)
+BFD0955C CBC4 SW S8, 16(SP)
+BFD0955E 0FDD MOVE S8, SP
+BFD09560 0018F89E SW A0, 24(S8)
+172: if (gpio_is_valid(gpio_id)) {\r
+BFD09564 0018FC9E LW A0, 24(S8)
+BFD09568 40DA77E8 JALS gpio_is_valid
+BFD0956A 0C0040DA BGTZ K0, 0xBFD0AD6E
+BFD0956C 0C00 NOP
+BFD0956E 000940E2 BEQZC V0, 0xBFD09584
+173: return *((volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id));\r
+BFD09572 0018FC9E LW A0, 24(S8)
+BFD09576 4D9477E8 JALS gpio_pin_ctrl_addr
+BFD09578 4D94 ADDIU T4, T4, -6
+BFD0957A 0C00 NOP
+BFD0957C 2920 LHU V0, 0(V0)
+BFD0957E 2D2F ANDI V0, V0, 0xFFFF
+BFD09580 CC02 B 0xBFD09586
+BFD09582 0C00 NOP
+174: } else {\r
+175: return 0u;\r
+BFD09584 0C40 MOVE V0, ZERO
+176: }\r
+177: }\r
+BFD09586 0FBE MOVE SP, S8
+BFD09588 4BE5 LW RA, 20(SP)
+BFD0958A 4BC4 LW S8, 16(SP)
+BFD0958C 4C0D ADDIU SP, SP, 24
+BFD0958E 459F JR16 RA
+BFD09590 0C00 NOP
+178: \r
+179: \r
+180: void GPIOSetConfig(enum gpio_id_t gpio_id, uint16_t config)\r
+181: {\r
+BFD09298 4FF1 ADDIU SP, SP, -32
+BFD0929A CBE7 SW RA, 28(SP)
+BFD0929C CBC6 SW S8, 24(SP)
+BFD0929E 0FDD MOVE S8, SP
+BFD092A0 0020F89E SW A0, 32(S8)
+BFD092A2 0C450020 CMP.LT.PH AT, ZERO
+BFD092A4 0C45 MOVE V0, A1
+BFD092A6 0024385E SH V0, 36(S8)
+182: volatile uint16_t * p;\r
+183: \r
+184: if (gpio_is_valid(gpio_id)) {\r
+BFD092AA 0020FC9E LW A0, 32(S8)
+BFD092AE 40DA77E8 JALS gpio_is_valid
+BFD092B0 0C0040DA BGTZ K0, 0xBFD0AAB4
+BFD092B2 0C00 NOP
+BFD092B4 000C40E2 BEQZC V0, 0xBFD092D0
+185: p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);\r
+BFD092B8 0020FC9E LW A0, 32(S8)
+BFD092BC 4D9477E8 JALS gpio_pin_ctrl_addr
+BFD092BE 4D94 ADDIU T4, T4, -6
+BFD092C0 0C00 NOP
+BFD092C2 0010F85E SW V0, 16(S8)
+186: *p = config;\r
+BFD092C6 0010FC5E LW V0, 16(S8)
+BFD092CA 0024347E LHU V1, 36(S8)
+BFD092CE A9A0 SH V1, 0(V0)
+187: }\r
+188: }\r
+BFD092D0 0FBE MOVE SP, S8
+BFD092D2 4BE7 LW RA, 28(SP)
+BFD092D4 4BC6 LW S8, 24(SP)
+BFD092D6 4C11 ADDIU SP, SP, 32
+BFD092D8 459F JR16 RA
+BFD092DA 0C00 NOP
+189: \r
+190: \r
+191: void GPIOConfigAndOr(enum gpio_id_t gpio_id, uint16_t and_mask, uint16_t or_mask)\r
+192: {\r
+BFD08214 4FF1 ADDIU SP, SP, -32
+BFD08216 CBE7 SW RA, 28(SP)
+BFD08218 CBC6 SW S8, 24(SP)
+BFD0821A 0FDD MOVE S8, SP
+BFD0821C 0020F89E SW A0, 32(S8)
+BFD0821E 0C650020 MULEQ_S.W.PHR AT, ZERO, AT
+BFD08220 0C65 MOVE V1, A1
+BFD08222 0C46 MOVE V0, A2
+BFD08224 0024387E SH V1, 36(S8)
+BFD08228 0028385E SH V0, 40(S8)
+193: volatile uint16_t * p;\r
+194: \r
+195: \r
+196: if (gpio_is_valid(gpio_id)) {\r
+BFD0822C 0020FC9E LW A0, 32(S8)
+BFD08230 40DA77E8 JALS gpio_is_valid
+BFD08232 0C0040DA BGTZ K0, 0xBFD09A36
+BFD08234 0C00 NOP
+BFD08236 001640E2 BEQZC V0, 0xBFD08266
+197: p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);\r
+BFD0823A 0020FC9E LW A0, 32(S8)
+BFD0823E 4D9477E8 JALS gpio_pin_ctrl_addr
+BFD08240 4D94 ADDIU T4, T4, -6
+BFD08242 0C00 NOP
+BFD08244 0010F85E SW V0, 16(S8)
+198: *p = (*p & and_mask) | or_mask;\r
+BFD08248 0010FC5E LW V0, 16(S8)
+BFD0824C 2920 LHU V0, 0(V0)
+BFD0824E 2DAF ANDI V1, V0, 0xFFFF
+BFD08250 0024345E LHU V0, 36(S8)
+BFD08254 4493 AND16 V0, V1
+BFD08256 2DAF ANDI V1, V0, 0xFFFF
+BFD08258 0028345E LHU V0, 40(S8)
+BFD0825C 44D3 OR16 V0, V1
+BFD0825E 2DAF ANDI V1, V0, 0xFFFF
+BFD08260 0010FC5E LW V0, 16(S8)
+BFD08264 A9A0 SH V1, 0(V0)
+199: }\r
+200: }\r
+BFD08266 0FBE MOVE SP, S8
+BFD08268 4BE7 LW RA, 28(SP)
+BFD0826A 4BC6 LW S8, 24(SP)
+BFD0826C 4C11 ADDIU SP, SP, 32
+BFD0826E 459F JR16 RA
+BFD08270 0C00 NOP
+201: \r
+202: \r
+203: uint32_t GPIOGetControl(enum gpio_id_t gpio_id)\r
+204: {\r
+BFD09770 4FF5 ADDIU SP, SP, -24
+BFD09772 CBE5 SW RA, 20(SP)
+BFD09774 CBC4 SW S8, 16(SP)
+BFD09776 0FDD MOVE S8, SP
+BFD09778 0018F89E SW A0, 24(S8)
+205: if (gpio_is_valid(gpio_id)) {\r
+BFD0977C 0018FC9E LW A0, 24(S8)
+BFD09780 40DA77E8 JALS gpio_is_valid
+BFD09782 0C0040DA BGTZ K0, 0xBFD0AF86
+BFD09784 0C00 NOP
+BFD09786 000840E2 BEQZC V0, 0xBFD0979A
+206: return *((volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id));\r
+BFD0978A 0018FC9E LW A0, 24(S8)
+BFD0978E 4D9477E8 JALS gpio_pin_ctrl_addr
+BFD09790 4D94 ADDIU T4, T4, -6
+BFD09792 0C00 NOP
+BFD09794 6920 LW V0, 0(V0)
+BFD09796 CC02 B 0xBFD0979C
+BFD09798 0C00 NOP
+207: } else {\r
+208: return 0xFFFFFFFFul;\r
+BFD0979A ED7F LI V0, -1
+209: }\r
+210: }\r
+BFD0979C 0FBE MOVE SP, S8
+BFD0979E 4BE5 LW RA, 20(SP)
+BFD097A0 4BC4 LW S8, 16(SP)
+BFD097A2 4C0D ADDIU SP, SP, 24
+BFD097A4 459F JR16 RA
+BFD097A6 0C00 NOP
+211: \r
+212: \r
+213: void GPIOSetControl(enum gpio_id_t gpio_id, uint32_t ctrl_val)\r
+214: {\r
+BFD092DC 4FF1 ADDIU SP, SP, -32
+BFD092DE CBE7 SW RA, 28(SP)
+BFD092E0 CBC6 SW S8, 24(SP)
+BFD092E2 0FDD MOVE S8, SP
+BFD092E4 0020F89E SW A0, 32(S8)
+BFD092E8 0024F8BE SW A1, 36(S8)
+215: volatile uint32_t * p;\r
+216: \r
+217: if (gpio_is_valid(gpio_id)) {\r
+BFD092EC 0020FC9E LW A0, 32(S8)
+BFD092F0 40DA77E8 JALS gpio_is_valid
+BFD092F2 0C0040DA BGTZ K0, 0xBFD0AAF6
+BFD092F4 0C00 NOP
+BFD092F6 000C40E2 BEQZC V0, 0xBFD09312
+218: p = (volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id);\r
+BFD092FA 0020FC9E LW A0, 32(S8)
+BFD092FE 4D9477E8 JALS gpio_pin_ctrl_addr
+BFD09300 4D94 ADDIU T4, T4, -6
+BFD09302 0C00 NOP
+BFD09304 0010F85E SW V0, 16(S8)
+219: *p = ctrl_val;\r
+BFD09308 0010FC5E LW V0, 16(S8)
+BFD0930C 0024FC7E LW V1, 36(S8)
+BFD09310 E9A0 SW V1, 0(V0)
+220: }\r
+221: }\r
+BFD09312 0FBE MOVE SP, S8
+BFD09314 4BE7 LW RA, 28(SP)
+BFD09316 4BC6 LW S8, 24(SP)
+BFD09318 4C11 ADDIU SP, SP, 32
+BFD0931A 459F JR16 RA
+BFD0931C 0C00 NOP
+222: \r
+223: \r
+224: void GPIOControlAndOr(enum gpio_id_t gpio_id, uint32_t and_mask, uint32_t or_mask)\r
+225: {\r
+BFD08804 4FF1 ADDIU SP, SP, -32
+BFD08806 CBE7 SW RA, 28(SP)
+BFD08808 CBC6 SW S8, 24(SP)
+BFD0880A 0FDD MOVE S8, SP
+BFD0880C 0020F89E SW A0, 32(S8)
+BFD08810 0024F8BE SW A1, 36(S8)
+BFD08814 0028F8DE SW A2, 40(S8)
+226: volatile uint32_t * p;\r
+227: \r
+228: if (gpio_is_valid(gpio_id)) {\r
+BFD08818 0020FC9E LW A0, 32(S8)
+BFD0881C 40DA77E8 JALS gpio_is_valid
+BFD0881E 0C0040DA BGTZ K0, 0xBFD0A022
+BFD08820 0C00 NOP
+BFD08822 001340E2 BEQZC V0, 0xBFD0884C
+229: p = (volatile uint32_t *)gpio_pin_ctrl_addr(gpio_id);\r
+BFD08826 0020FC9E LW A0, 32(S8)
+BFD0882A 4D9477E8 JALS gpio_pin_ctrl_addr
+BFD0882C 4D94 ADDIU T4, T4, -6
+BFD0882E 0C00 NOP
+BFD08830 0010F85E SW V0, 16(S8)
+230: *p = (*p & and_mask) | or_mask;\r
+BFD08834 0010FC5E LW V0, 16(S8)
+BFD08838 69A0 LW V1, 0(V0)
+BFD0883A 0024FC5E LW V0, 36(S8)
+BFD0883E 449A AND16 V1, V0
+BFD08840 0028FC5E LW V0, 40(S8)
+BFD08844 44DA OR16 V1, V0
+BFD08846 0010FC5E LW V0, 16(S8)
+BFD0884A E9A0 SW V1, 0(V0)
+231: }\r
+232: }\r
+BFD0884C 0FBE MOVE SP, S8
+BFD0884E 4BE7 LW RA, 28(SP)
+BFD08850 4BC6 LW S8, 24(SP)
+BFD08852 4C11 ADDIU SP, SP, 32
+BFD08854 459F JR16 RA
+BFD08856 0C00 NOP
+233: \r
+234: \r
+235: /**\r
+236: * GPIOPropertySet - Program specified GPIO Pin configuration \r
+237: * item. \r
+238: * \r
+239: * @author sworley \r
+240: * \r
+241: * @param gpio_id 0-based GPIO ID\r
+242: * @param gpio_prop enumerated GPIO Property(configuration item)\r
+243: * @param prop_val new property value\r
+244: */\r
+245: void GPIOPropertySet ( enum gpio_id_t gpio_id, \r
+246: enum gpio_prop_t gpio_prop,\r
+247: uint16_t prop_val\r
+248: )\r
+249: {\r
+BFD04B98 4FF1 ADDIU SP, SP, -32
+BFD04B9A CBE7 SW RA, 28(SP)
+BFD04B9C CBC6 SW S8, 24(SP)
+BFD04B9E 0FDD MOVE S8, SP
+BFD04BA0 0020F89E SW A0, 32(S8)
+BFD04BA4 0024F8BE SW A1, 36(S8)
+BFD04BA8 0C46 MOVE V0, A2
+BFD04BAA 0028385E SH V0, 40(S8)
+250: volatile uint16_t * p;\r
+251: uint16_t gp_cfg;\r
+252: \r
+253: gp_cfg = 0u;\r
+BFD04BAE 0010381E SH ZERO, 16(S8)
+254: \r
+255: if ( gpio_is_valid(gpio_id) && ((uint16_t)gpio_prop < (uint16_t)GPIO_PROP_MAX) )\r
+BFD04BB2 0020FC9E LW A0, 32(S8)
+BFD04BB6 40DA77E8 JALS gpio_is_valid
+BFD04BB8 0C0040DA BGTZ K0, 0xBFD063BC
+BFD04BBA 0C00 NOP
+BFD04BBC 005140E2 BEQZC V0, 0xBFD04C62
+BFD04BC0 0024FC5E LW V0, 36(S8)
+BFD04BC4 2D2F ANDI V0, V0, 0xFFFF
+BFD04BC6 0009B042 SLTIU V0, V0, 9
+BFD04BCA 004A40E2 BEQZC V0, 0xBFD04C62
+256: {\r
+257: p = (volatile uint16_t *)gpio_pin_ctrl_addr(gpio_id);\r
+BFD04BCE 0020FC9E LW A0, 32(S8)
+BFD04BD2 4D9477E8 JALS gpio_pin_ctrl_addr
+BFD04BD4 4D94 ADDIU T4, T4, -6
+BFD04BD6 0C00 NOP
+BFD04BD8 0014F85E SW V0, 20(S8)
+258: gp_cfg = *p;\r
+BFD04BDC 0014FC5E LW V0, 20(S8)
+BFD04BE0 2920 LHU V0, 0(V0)
+BFD04BE2 0010385E SH V0, 16(S8)
+259: gp_cfg &= ~(gpio_cfg_tbl[gpio_prop].bit_mask);\r
+BFD04BE6 BFD141A2 LUI V0, 0xBFD1
+BFD04BE8 FC7EBFD1 LDC1 F30, -898(S1)
+BFD04BEA 0024FC7E LW V1, 36(S8)
+BFD04BEE 25B4 SLL V1, V1, 2
+BFD04BF0 92743042 ADDIU V0, V0, -28044
+BFD04BF2 05269274 SLTI S3, S4, 1318
+BFD04BF4 0526 ADDU V0, V1, V0
+BFD04BF6 2920 LHU V0, 0(V0)
+BFD04BF8 3B3C0042 SEH V0, V0
+BFD04BFA 44123B3C SH T9, 17426(GP)
+BFD04BFC 4412 NOT16 V0, V0
+BFD04BFE 3B3C0062 SEH V1, V0
+BFD04C00 3C5E3B3C SH T9, 15454(GP)
+BFD04C02 00103C5E LH V0, 16(S8)
+BFD04C06 4493 AND16 V0, V1
+BFD04C08 3B3C0042 SEH V0, V0
+BFD04C0A 385E3B3C SH T9, 14430(GP)
+BFD04C0C 0010385E SH V0, 16(S8)
+260: gp_cfg |= (prop_val << gpio_cfg_tbl[gpio_prop].bit_pos) & \r
+BFD04C10 0028347E LHU V1, 40(S8)
+BFD04C14 BFD141A2 LUI V0, 0xBFD1
+BFD04C16 FC9EBFD1 LDC1 F30, -866(S1)
+BFD04C18 0024FC9E LW A0, 36(S8)
+BFD04C1C 2644 SLL A0, A0, 2
+BFD04C1E 92743042 ADDIU V0, V0, -28044
+BFD04C20 05289274 SLTI S3, S4, 1320
+BFD04C22 0528 ADDU V0, A0, V0
+BFD04C24 0922 LBU V0, 2(V0)
+BFD04C26 10100062 SLLV V0, V0, V1
+BFD04C28 00621010 ADDI ZERO, S0, 98
+BFD04C2A 3B3C0062 SEH V1, V0
+BFD04C2C 41A23B3C SH T9, 16802(GP)
+BFD04C40 3B3C0042 SEH V0, V0
+BFD04C42 44933B3C SH T9, 17555(GP)
+BFD04C44 4493 AND16 V0, V1
+BFD04C46 3B3C0062 SEH V1, V0
+BFD04C48 3C5E3B3C SH T9, 15454(GP)
+BFD04C4A 00103C5E LH V0, 16(S8)
+BFD04C4E 44D3 OR16 V0, V1
+BFD04C50 3B3C0042 SEH V0, V0
+BFD04C52 385E3B3C SH T9, 14430(GP)
+BFD04C54 0010385E SH V0, 16(S8)
+261: gpio_cfg_tbl[gpio_prop].bit_mask; \r
+BFD04C2E BFD141A2 LUI V0, 0xBFD1
+BFD04C30 FC9EBFD1 LDC1 F30, -866(S1)
+BFD04C32 0024FC9E LW A0, 36(S8)
+BFD04C36 2644 SLL A0, A0, 2
+BFD04C38 92743042 ADDIU V0, V0, -28044
+BFD04C3A 05289274 SLTI S3, S4, 1320
+BFD04C3C 0528 ADDU V0, A0, V0
+BFD04C3E 2920 LHU V0, 0(V0)
+262: *p = gp_cfg;\r
+BFD04C58 0014FC5E LW V0, 20(S8)
+BFD04C5C 0010347E LHU V1, 16(S8)
+BFD04C60 A9A0 SH V1, 0(V0)
+263: }\r
+264: }\r
+BFD04C62 0FBE MOVE SP, S8
+BFD04C64 4BE7 LW RA, 28(SP)
+BFD04C66 4BC6 LW S8, 24(SP)
+BFD04C68 4C11 ADDIU SP, SP, 32
+BFD04C6A 459F JR16 RA
+BFD04C6C 0C00 NOP
+265: \r
+266: \r
+267: /**\r
+268: * GPIOGetSlewRate - Return GPIO Pin Slew Rate\r
+269: * \r
+270: * @author sworley \r
+271: * \r
+272: * @param gpio_id 0-based GPIO ID\r
+273: * \r
+274: * @return uint8_t GPIO Pin Slew Rate: 0(Slow) or 1(Fast)\r
+275: */\r
+276: uint8_t GPIOGetSlewRate( enum gpio_id_t gpio_id )\r
+277: {\r
+BFD09024 4FF1 ADDIU SP, SP, -32
+BFD09026 CBE7 SW RA, 28(SP)
+BFD09028 CBC6 SW S8, 24(SP)
+BFD0902A 0FDD MOVE S8, SP
+BFD0902C 0020F89E SW A0, 32(S8)
+278: uint32_t addr;\r
+279: uint8_t slew;\r
+280: \r
+281: addr = gpio_has_drv_str(gpio_id);\r
+BFD09030 0020FC9E LW A0, 32(S8)
+BFD09034 332277E8 JALS gpio_has_drv_str
+BFD09036 0C003322 ADDIU T9, V0, 3072
+BFD09038 0C00 NOP
+BFD0903A 0014F85E SW V0, 20(S8)
+282: if ( 0ul != addr )\r
+BFD0903E 0014FC5E LW V0, 20(S8)
+BFD09042 000940E2 BEQZC V0, 0xBFD09058
+283: {\r
+284: slew = ((*(volatile uint8_t *)addr) >> GPIO_DRV_SLEW_BITPOS) & 0x01u;\r
+BFD09046 0014FC5E LW V0, 20(S8)
+BFD0904A 0920 LBU V0, 0(V0)
+BFD0904C 2D2D ANDI V0, V0, 0xFF
+BFD0904E 2D21 ANDI V0, V0, 0x1
+BFD09050 0010185E SB V0, 16(S8)
+BFD09054 CC03 B 0xBFD0905C
+BFD09056 0C00 NOP
+285: }\r
+286: else\r
+287: {\r
+288: slew = 0u;\r
+BFD09058 0010181E SB ZERO, 16(S8)
+289: }\r
+290: \r
+291: return slew;\r
+BFD0905C 0010145E LBU V0, 16(S8)
+292: }\r
+BFD09060 0FBE MOVE SP, S8
+BFD09062 4BE7 LW RA, 28(SP)
+BFD09064 4BC6 LW S8, 24(SP)
+BFD09066 4C11 ADDIU SP, SP, 32
+BFD09068 459F JR16 RA
+BFD0906A 0C00 NOP
+293: \r
+294: \r
+295: /**\r
+296: * GPIOSetSlewRate - Program GPIO Pin's Slew Rate\r
+297: * \r
+298: * @author sworley \r
+299: * \r
+300: * @param gpio_id 0-based GPIO ID\r
+301: * @param slew_rate new slew rate: 0(Slow), Non-zero(Fast)\r
+302: */\r
+303: void GPIOSetSlewRate ( enum gpio_id_t gpio_id,\r
+304: enum gpio_slew_rate_t slew_rate )\r
+305: {\r
+BFD08600 4FF1 ADDIU SP, SP, -32
+BFD08602 CBE7 SW RA, 28(SP)
+BFD08604 CBC6 SW S8, 24(SP)
+BFD08606 0FDD MOVE S8, SP
+BFD08608 0020F89E SW A0, 32(S8)
+BFD0860C 0024F8BE SW A1, 36(S8)
+306: uint32_t addr;\r
+307: \r
+308: addr = gpio_has_drv_str(gpio_id );\r
+BFD08610 0020FC9E LW A0, 32(S8)
+BFD08614 332277E8 JALS gpio_has_drv_str
+BFD08616 0C003322 ADDIU T9, V0, 3072
+BFD08618 0C00 NOP
+BFD0861A 0010F85E SW V0, 16(S8)
+309: if ( addr )\r
+BFD0861E 0010FC5E LW V0, 16(S8)
+BFD08622 001240E2 BEQZC V0, 0xBFD0864A
+310: {\r
+311: *(volatile uint8_t *)addr = (*(volatile uint8_t *)addr & \r
+BFD08626 0010FC5E LW V0, 16(S8)
+BFD0862A 0010FC7E LW V1, 16(S8)
+BFD0862E 09B0 LBU V1, 0(V1)
+BFD08630 2E3D ANDI A0, V1, 0xFF
+BFD08632 FFFE3060 ADDIU V1, ZERO, -2
+BFD08634 449CFFFE LW RA, 17564(S8)
+BFD08636 449C AND16 V1, A0
+BFD08638 2E3D ANDI A0, V1, 0xFF
+BFD0863A 0024FC7E LW V1, 36(S8)
+BFD0863E 2DBD ANDI V1, V1, 0xFF
+BFD08640 2DB1 ANDI V1, V1, 0x1
+BFD08642 2DBD ANDI V1, V1, 0xFF
+BFD08644 44DC OR16 V1, A0
+BFD08646 2DBD ANDI V1, V1, 0xFF
+BFD08648 89A0 SB V1, 0(V0)
+312: ~(GPIO_DRV_SLEW_MASK)) | \r
+313: ((slew_rate << (GPIO_DRV_SLEW_BITPOS)) & (GPIO_DRV_SLEW_MASK));\r
+314: }\r
+315: }\r
+BFD0864A 0FBE MOVE SP, S8
+BFD0864C 4BE7 LW RA, 28(SP)
+BFD0864E 4BC6 LW S8, 24(SP)
+BFD08650 4C11 ADDIU SP, SP, 32
+BFD08652 459F JR16 RA
+BFD08654 0C00 NOP
+316: \r
+317: \r
+318: /**\r
+319: * GPIOGetDriveStr - Get GPIO Pin's Drive Strength \r
+320: * \r
+321: * @author sworley \r
+322: * \r
+323: * @param gpio_id 0-based GPIO ID\r
+324: * \r
+325: * @return uint8_t Pin Drive Strength: 0=2mA, 1=4mA, 2=8mA, \r
+326: * 3=12mA.\r
+327: */\r
+328: uint8_t GPIOGetDriveStr ( enum gpio_id_t gpio_id )\r
+329: {\r
+BFD09594 4FF1 ADDIU SP, SP, -32
+BFD09596 CBE7 SW RA, 28(SP)
+BFD09598 CBC6 SW S8, 24(SP)
+BFD0959A 0FDD MOVE S8, SP
+BFD0959C 0020F89E SW A0, 32(S8)
+330: uint32_t addr;\r
+331: \r
+332: addr = gpio_has_drv_str(gpio_id );\r
+BFD095A0 0020FC9E LW A0, 32(S8)
+BFD095A4 332277E8 JALS gpio_has_drv_str
+BFD095A6 0C003322 ADDIU T9, V0, 3072
+BFD095A8 0C00 NOP
+BFD095AA 0010F85E SW V0, 16(S8)
+333: if ( addr )\r
+BFD095AE 0010FC5E LW V0, 16(S8)
+BFD095B2 000640E2 BEQZC V0, 0xBFD095C2
+334: {\r
+335: return ((*(volatile uint8_t *)addr) >> GPIO_DRV_STR_BITPOS) & (GPIO_DRV_STR_MASK);\r
+BFD095B6 0010FC5E LW V0, 16(S8)
+BFD095BA 0920 LBU V0, 0(V0)
+BFD095BC 0C40 MOVE V0, ZERO
+BFD095BE CC02 B 0xBFD095C4
+BFD095C0 0C00 NOP
+336: }\r
+337: else\r
+338: {\r
+339: return 0u;\r
+BFD095C2 0C40 MOVE V0, ZERO
+340: }\r
+341: }\r
+BFD095C4 0FBE MOVE SP, S8
+BFD095C6 4BE7 LW RA, 28(SP)
+BFD095C8 4BC6 LW S8, 24(SP)
+BFD095CA 4C11 ADDIU SP, SP, 32
+BFD095CC 459F JR16 RA
+BFD095CE 0C00 NOP
+342: \r
+343: \r
+344: /**\r
+345: * GPIOSetDriveStr - Program GPIO Pin's Drive Strength\r
+346: * \r
+347: * @author sworley \r
+348: * \r
+349: * @param gpio_id 0-based GPIO ID\r
+350: * @param drv_str enumerated drive strength: 0=2mA, 1=4mA, \r
+351: * 2=8mA, 3=12mA\r
+352: */\r
+353: void GPIOSetDriveStr ( enum gpio_id_t gpio_id,\r
+354: enum gpio_drv_str_t drv_str )\r
+355: {\r
+BFD07D64 4FF1 ADDIU SP, SP, -32
+BFD07D66 CBE7 SW RA, 28(SP)
+BFD07D68 CBC6 SW S8, 24(SP)
+BFD07D6A 0FDD MOVE S8, SP
+BFD07D6C 0020F89E SW A0, 32(S8)
+BFD07D70 0024F8BE SW A1, 36(S8)
+356: uint32_t addr;\r
+357: uint8_t r8;\r
+358: \r
+359: addr = gpio_has_drv_str(gpio_id);\r
+BFD07D74 0020FC9E LW A0, 32(S8)
+BFD07D78 332277E8 JALS gpio_has_drv_str
+BFD07D7A 0C003322 ADDIU T9, V0, 3072
+BFD07D7C 0C00 NOP
+BFD07D7E 0010F85E SW V0, 16(S8)
+360: if ( addr )\r
+BFD07D82 0010FC5E LW V0, 16(S8)
+BFD07D86 001B40E2 BEQZC V0, 0xBFD07DC0
+361: {\r
+362: r8 = *(volatile uint8_t *)addr & ~(GPIO_DRV_STR_MASK);\r
+BFD07D8A 0010FC5E LW V0, 16(S8)
+BFD07D8E 0920 LBU V0, 0(V0)
+BFD07D90 2DAD ANDI V1, V0, 0xFF
+BFD07D92 FFCF3040 ADDIU V0, ZERO, -49
+BFD07D94 4493FFCF LW S8, 17555(T7)
+BFD07D96 4493 AND16 V0, V1
+BFD07D98 0014185E SB V0, 20(S8)
+363: r8 += ((drv_str << GPIO_DRV_STR_BITPOS) & GPIO_DRV_STR_MASK);\r
+BFD07D9C 0024FC5E LW V0, 36(S8)
+BFD07DA0 2D2D ANDI V0, V0, 0xFF
+BFD07DA2 2528 SLL V0, V0, 4
+BFD07DA4 2D2D ANDI V0, V0, 0xFF
+BFD07DA6 0030D042 ANDI V0, V0, 48
+BFD07DAA 2DAD ANDI V1, V0, 0xFF
+BFD07DAC 0014145E LBU V0, 20(S8)
+BFD07DB0 0526 ADDU V0, V1, V0
+BFD07DB2 0014185E SB V0, 20(S8)
+364: *(volatile uint8_t *)addr = r8;\r
+BFD07DB6 0010FC5E LW V0, 16(S8)
+BFD07DBA 0014147E LBU V1, 20(S8)
+BFD07DBE 89A0 SB V1, 0(V0)
+365: }\r
+366: }\r
+BFD07DC0 0FBE MOVE SP, S8
+BFD07DC2 4BE7 LW RA, 28(SP)
+BFD07DC4 4BC6 LW S8, 24(SP)
+BFD07DC6 4C11 ADDIU SP, SP, 32
+BFD07DC8 459F JR16 RA
+BFD07DCA 0C00 NOP
+367: \r
+368: \r
+369: /**\r
+370: * GPIOGetDriveStrAndSlew - Return combined value representing \r
+371: * Drive Strength and Slew Rate. \r
+372: * \r
+373: * @author sworley \r
+374: * \r
+375: * @param gpio_id 0-based GPIO ID\r
+376: * \r
+377: * @return uint8_t bit[0] = Slew Rate, bits[3:1]=0(Reserved), \r
+378: * bits[5:4]=Drive Strength, bits[7:6]=0(Reserved)\r
+379: */\r
+380: uint8_t GPIOGetDriveStrAndSlew ( enum gpio_id_t gpio_id )\r
+381: {\r
+BFD095D0 4FF1 ADDIU SP, SP, -32
+BFD095D2 CBE7 SW RA, 28(SP)
+BFD095D4 CBC6 SW S8, 24(SP)
+BFD095D6 0FDD MOVE S8, SP
+BFD095D8 0020F89E SW A0, 32(S8)
+382: uint32_t addr;\r
+383: \r
+384: addr = gpio_has_drv_str(gpio_id );\r
+BFD095DC 0020FC9E LW A0, 32(S8)
+BFD095E0 332277E8 JALS gpio_has_drv_str
+BFD095E2 0C003322 ADDIU T9, V0, 3072
+BFD095E4 0C00 NOP
+BFD095E6 0010F85E SW V0, 16(S8)
+385: if ( addr )\r
+BFD095EA 0010FC5E LW V0, 16(S8)
+BFD095EE 000640E2 BEQZC V0, 0xBFD095FE
+386: {\r
+387: return (*(volatile uint8_t *)addr);\r
+BFD095F2 0010FC5E LW V0, 16(S8)
+BFD095F6 0920 LBU V0, 0(V0)
+BFD095F8 2D2D ANDI V0, V0, 0xFF
+BFD095FA CC02 B 0xBFD09600
+BFD095FC 0C00 NOP
+388: }\r
+389: else\r
+390: {\r
+391: return 0u;\r
+BFD095FE 0C40 MOVE V0, ZERO
+392: }\r
+393: }\r
+BFD09600 0FBE MOVE SP, S8
+BFD09602 4BE7 LW RA, 28(SP)
+BFD09604 4BC6 LW S8, 24(SP)
+BFD09606 4C11 ADDIU SP, SP, 32
+BFD09608 459F JR16 RA
+BFD0960A 0C00 NOP
+394: \r
+395: \r
+396: /**\r
+397: * GPIOSetDriveStrAndSlew - Program GPIO Pin's drive strength \r
+398: * and slew rate. \r
+399: * \r
+400: * @author sworley \r
+401: * \r
+402: * @param gpio_id 0-based GPIO ID\r
+403: * @param drv_and_slew bit[0] = Slew Rate, bits[3:1]=0(Reserved), \r
+404: * bits[5:4]=Drive Strength, bits[7:6]=0(Reserved)\r
+405: */\r
+406: void GPIOSetDriveStrAndSlew ( enum gpio_id_t gpio_id,\r
+407: uint8_t drv_and_slew )\r
+408: {\r
+BFD0802C 4FF1 ADDIU SP, SP, -32
+BFD0802E CBE7 SW RA, 28(SP)
+BFD08030 CBC6 SW S8, 24(SP)
+BFD08032 0FDD MOVE S8, SP
+BFD08034 0020F89E SW A0, 32(S8)
+BFD08036 0C450020 CMP.LT.PH AT, ZERO
+BFD08038 0C45 MOVE V0, A1
+BFD0803A 0024185E SB V0, 36(S8)
+409: uint32_t addr;\r
+410: uint8_t r8;\r
+411: \r
+412: addr = gpio_has_drv_str(gpio_id);\r
+BFD0803E 0020FC9E LW A0, 32(S8)
+BFD08042 332277E8 JALS gpio_has_drv_str
+BFD08044 0C003322 ADDIU T9, V0, 3072
+BFD08046 0C00 NOP
+BFD08048 0010F85E SW V0, 16(S8)
+413: if ( addr )\r
+BFD0804C 0010FC5E LW V0, 16(S8)
+BFD08050 001840E2 BEQZC V0, 0xBFD08084
+414: {\r
+415: r8 = *(volatile uint8_t *)addr & ~(GPIO_DRV_SLEW_MASK + GPIO_DRV_STR_MASK);\r
+BFD08054 0010FC5E LW V0, 16(S8)
+BFD08058 0920 LBU V0, 0(V0)
+BFD0805A 2DAD ANDI V1, V0, 0xFF
+BFD0805C FFCE3040 ADDIU V0, ZERO, -50
+BFD0805E 4493FFCE LW S8, 17555(T6)
+BFD08060 4493 AND16 V0, V1
+BFD08062 0014185E SB V0, 20(S8)
+416: r8 |= (drv_and_slew & (GPIO_DRV_SLEW_MASK + GPIO_DRV_STR_MASK));\r
+BFD08066 0024145E LBU V0, 36(S8)
+BFD0806A 0031D042 ANDI V0, V0, 49
+BFD0806E 2DAD ANDI V1, V0, 0xFF
+BFD08070 0014145E LBU V0, 20(S8)
+BFD08074 44D3 OR16 V0, V1
+BFD08076 0014185E SB V0, 20(S8)
+417: *(volatile uint8_t *)addr = r8;\r
+BFD0807A 0010FC5E LW V0, 16(S8)
+BFD0807E 0014147E LBU V1, 20(S8)
+BFD08082 89A0 SB V1, 0(V0)
+418: }\r
+419: }\r
+BFD08084 0FBE MOVE SP, S8
+BFD08086 4BE7 LW RA, 28(SP)
+BFD08088 4BC6 LW S8, 24(SP)
+BFD0808A 4C11 ADDIU SP, SP, 32
+BFD0808C 459F JR16 RA
+BFD0808E 0C00 NOP
+420: \r
+421: \r
+422: /**\r
+423: * GPIOSetOutput - Program GPIO Pin's output state using Pin \r
+424: * configuration register (not parallel output register). \r
+425: * \r
+426: * @author sworley \r
+427: * \r
+428: * @param gpio_id 0-based GPIO ID\r
+429: * @param gpio_state pin state: actual pin state at pad will \r
+430: * depend upon GPIO Output invert\r
+431: * configuration.\r
+432: * @note peforms a byte wide write to byte offset 2 of the GPIO \r
+433: * Pin's 32-bit configuration register. No\r
+434: * read-modify-write.\r
+435: */\r
+436: void GPIOSetOutput ( enum gpio_id_t gpio_id, \r
+437: uint8_t gpio_state\r
+438: )\r
+439: {\r
+BFD08658 4FF1 ADDIU SP, SP, -32
+BFD0865A CBE7 SW RA, 28(SP)
+BFD0865C CBC6 SW S8, 24(SP)
+BFD0865E 0FDD MOVE S8, SP
+BFD08660 0020F89E SW A0, 32(S8)
+BFD08662 0C450020 CMP.LT.PH AT, ZERO
+BFD08664 0C45 MOVE V0, A1
+BFD08666 0024185E SB V0, 36(S8)
+440: volatile uint8_t * p;\r
+441: \r
+442: if ( gpio_is_valid(gpio_id) )\r
+BFD0866A 0020FC9E LW A0, 32(S8)
+BFD0866E 40DA77E8 JALS gpio_is_valid
+BFD08670 0C0040DA BGTZ K0, 0xBFD09E74
+BFD08672 0C00 NOP
+BFD08674 001540E2 BEQZC V0, 0xBFD086A2
+443: {\r
+444: p = (volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 2ul);\r
+BFD08678 0020FC9E LW A0, 32(S8)
+BFD0867C 4D9477E8 JALS gpio_pin_ctrl_addr
+BFD0867E 4D94 ADDIU T4, T4, -6
+BFD08680 0C00 NOP
+BFD08682 4C44 ADDIU V0, V0, 2
+BFD08684 0010F85E SW V0, 16(S8)
+445: if (gpio_state) {\r
+BFD08688 0024145E LBU V0, 36(S8)
+BFD0868C 000640E2 BEQZC V0, 0xBFD0869C
+446: *p = 0x01u;\r
+BFD08690 0010FC5E LW V0, 16(S8)
+BFD08694 ED81 LI V1, 1
+BFD08696 89A0 SB V1, 0(V0)
+BFD08698 CC04 B 0xBFD086A2
+BFD0869A 0C00 NOP
+447: } else {\r
+448: *p = 0u;\r
+BFD0869C 0010FC5E LW V0, 16(S8)
+BFD086A0 8820 SB S0, 0(V0)
+449: }\r
+450: }\r
+451: }\r
+BFD086A2 0FBE MOVE SP, S8
+BFD086A4 4BE7 LW RA, 28(SP)
+BFD086A6 4BC6 LW S8, 24(SP)
+BFD086A8 4C11 ADDIU SP, SP, 32
+BFD086AA 459F JR16 RA
+BFD086AC 0C00 NOP
+452: \r
+453: \r
+454: void GPIOToggleOutput ( enum gpio_id_t gpio_id )\r
+455: {\r
+BFD08C5C 4FF1 ADDIU SP, SP, -32
+BFD08C5E CBE7 SW RA, 28(SP)
+BFD08C60 CBC6 SW S8, 24(SP)
+BFD08C62 0FDD MOVE S8, SP
+BFD08C64 0020F89E SW A0, 32(S8)
+456: volatile uint8_t * p;\r
+457: \r
+458: if ( gpio_is_valid(gpio_id) )\r
+BFD08C68 0020FC9E LW A0, 32(S8)
+BFD08C6C 40DA77E8 JALS gpio_is_valid
+BFD08C6E 0C0040DA BGTZ K0, 0xBFD0A472
+BFD08C70 0C00 NOP
+BFD08C72 001240E2 BEQZC V0, 0xBFD08C9A
+459: {\r
+460: p = (volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 2ul);\r
+BFD08C76 0020FC9E LW A0, 32(S8)
+BFD08C7A 4D9477E8 JALS gpio_pin_ctrl_addr
+BFD08C7C 4D94 ADDIU T4, T4, -6
+BFD08C7E 0C00 NOP
+BFD08C80 4C44 ADDIU V0, V0, 2
+BFD08C82 0010F85E SW V0, 16(S8)
+461: *p ^= 0x01u;\r
+BFD08C86 0010FC5E LW V0, 16(S8)
+BFD08C8A 0920 LBU V0, 0(V0)
+BFD08C8C 2D2D ANDI V0, V0, 0xFF
+BFD08C8E 00017042 XORI V0, V0, 1
+BFD08C92 2DAD ANDI V1, V0, 0xFF
+BFD08C94 0010FC5E LW V0, 16(S8)
+BFD08C98 89A0 SB V1, 0(V0)
+462: }\r
+463: }\r
+BFD08C9A 0FBE MOVE SP, S8
+BFD08C9C 4BE7 LW RA, 28(SP)
+BFD08C9E 4BC6 LW S8, 24(SP)
+BFD08CA0 4C11 ADDIU SP, SP, 32
+BFD08CA2 459F JR16 RA
+BFD08CA4 0C00 NOP
+464: \r
+465: \r
+466: /**\r
+467: * GPIOReadPin - Read GPIO Pin's Pad Input from configuration \r
+468: * register. \r
+469: * \r
+470: * @author sworley \r
+471: * \r
+472: * @param gpio_id 0-based GPIO ID.\r
+473: * \r
+474: * @return uint8_t 0 or 1 depending upon the state of the GPIO \r
+475: * pad.\r
+476: * @note performs a byte read of offset 3 of the GPIO Pin's \r
+477: * 32-bit configuration register.\r
+478: */\r
+479: uint8_t GPIOReadPin( enum gpio_id_t gpio_id )\r
+480: {\r
+BFD0960C 4FF5 ADDIU SP, SP, -24
+BFD0960E CBE5 SW RA, 20(SP)
+BFD09610 CBC4 SW S8, 16(SP)
+BFD09612 0FDD MOVE S8, SP
+BFD09614 0018F89E SW A0, 24(S8)
+481: if ( gpio_is_valid(gpio_id) )\r
+BFD09618 0018FC9E LW A0, 24(S8)
+BFD0961C 40DA77E8 JALS gpio_is_valid
+BFD0961E 0C0040DA BGTZ K0, 0xBFD0AE22
+BFD09620 0C00 NOP
+BFD09622 000A40E2 BEQZC V0, 0xBFD0963A
+482: {\r
+483: return *((volatile uint8_t *)(gpio_pin_ctrl_addr(gpio_id) + 3ul));\r
+BFD09626 0018FC9E LW A0, 24(S8)
+BFD0962A 4D9477E8 JALS gpio_pin_ctrl_addr
+BFD0962C 4D94 ADDIU T4, T4, -6
+BFD0962E 0C00 NOP
+BFD09630 4C46 ADDIU V0, V0, 3
+BFD09632 0920 LBU V0, 0(V0)
+BFD09634 2D2D ANDI V0, V0, 0xFF
+BFD09636 CC02 B 0xBFD0963C
+BFD09638 0C00 NOP
+484: } \r
+485: else \r
+486: {\r
+487: return 0u;\r
+BFD0963A 0C40 MOVE V0, ZERO
+488: }\r
+489: }\r
+BFD0963C 0FBE MOVE SP, S8
+BFD0963E 4BE5 LW RA, 20(SP)
+BFD09640 4BC4 LW S8, 16(SP)
+BFD09642 4C0D ADDIU SP, SP, 24
+BFD09644 459F JR16 RA
+BFD09646 0C00 NOP
+490: \r
+491: \r
+492: /** GPIOPinLock - Lock specified GPIO's control register.\r
+493: * @param enum gpio_id_t zero based GPIO ID\r
+494: * @note Lock bit is only cleared on POR. Lock registers\r
+495: * are in reverse order, first register is at top address.\r
+496: * GPIO_LOCK_BASE defined to top(first) register address.\r
+497: * */ \r
+498: void GPIOPinLock(enum gpio_id_t gpio_id)\r
+499: {\r
+BFD07ADC 4FF1 ADDIU SP, SP, -32
+BFD07ADE CBE7 SW RA, 28(SP)
+BFD07AE0 CBC6 SW S8, 24(SP)
+BFD07AE2 0FDD MOVE S8, SP
+BFD07AE4 0020F89E SW A0, 32(S8)
+500: uint32_t addr;\r
+501: uint8_t bank, bitpos;\r
+502: \r
+503: if (gpio_is_valid(gpio_id)) {\r
+BFD07AE8 0020FC9E LW A0, 32(S8)
+BFD07AEC 40DA77E8 JALS gpio_is_valid
+BFD07AEE 0C0040DA BGTZ K0, 0xBFD092F2
+BFD07AF0 0C00 NOP
+BFD07AF2 002440E2 BEQZC V0, 0xBFD07B3E
+504: bank = gpio_bank_num(gpio_id); // 0 - 4\r
+BFD07AF6 0020FC9E LW A0, 32(S8)
+BFD07AFA 4E9677E8 JALS gpio_bank_num
+BFD07AFC 4E96 ADDIU S4, S4, -5
+BFD07AFE 0C00 NOP
+BFD07B00 0010185E SB V0, 16(S8)
+505: bitpos = gpio_pin_num(gpio_id); // 0 - 31\r
+BFD07B04 0020FC9E LW A0, 32(S8)
+BFD07B08 4EA677E8 JALS gpio_pin_num
+BFD07B0A 4EA6 ADDIU S5, S5, 3
+BFD07B0C 0C00 NOP
+BFD07B0E 0011185E SB V0, 17(S8)
+506: addr = (uint32_t)(GPIO_LOCK_BASE) - (bank << 2);\r
+BFD07B12 0010145E LBU V0, 16(S8)
+BFD07B16 2524 SLL V0, V0, 2
+BFD07B18 A00841A3 LUI V1, 0xA008
+BFD07B1C 13F05063 ORI V1, V1, 5104
+BFD07B1E 052713F0 ADDI RA, S0, 1319
+BFD07B20 0527 SUBU V0, V1, V0
+BFD07B22 0014F85E SW V0, 20(S8)
+507: *(volatile uint32_t *)addr |= (1ul << bitpos);\r
+BFD07B26 0014FC5E LW V0, 20(S8)
+BFD07B2A 0014FC7E LW V1, 20(S8)
+BFD07B2E 6A30 LW A0, 0(V1)
+BFD07B30 0011147E LBU V1, 17(S8)
+BFD07B34 EE81 LI A1, 1
+BFD07B36 181000A3 SLLV V1, V1, A1
+BFD07B38 44DC1810 SB ZERO, 17628(S0)
+BFD07B3A 44DC OR16 V1, A0
+BFD07B3C E9A0 SW V1, 0(V0)
+508: } \r
+509: }\r
+BFD07B3E 0FBE MOVE SP, S8
+BFD07B40 4BE7 LW RA, 28(SP)
+BFD07B42 4BC6 LW S8, 24(SP)
+BFD07B44 4C11 ADDIU SP, SP, 32
+BFD07B46 459F JR16 RA
+BFD07B48 0C00 NOP
+510: \r
+511: \r
+512: /* end mec14xx_gpio.c */\r
+513: /** @}\r
+514: */\r
+515: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/mec14xx_bbled.c --------
+1: /*****************************************************************************\r
+2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file mec14xx_bbled.c\r
+22: *MEC14xx Breating-Blinking LED definitions\r
+23: */\r
+24: /** @defgroup MEC14xx Peripherals BBLED\r
+25: */\r
+26: \r
+27: #include "appcfg.h"\r
+28: #include "platform.h"\r
+29: #include "MEC14xx/mec14xx.h"\r
+30: #include "MEC14xx/mec14xx_pcr.h"\r
+31: #include "MEC14xx/mec14xx_bbled.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_bbled.h"\r
+34: \r
+35: #ifdef __cplusplus\r
+36: extern "C" {\r
+37: #endif\r
+38: \r
+39: \r
+40: static uint32_t led_addr(uint8_t led_id) \r
+41: {\r
+BFD09420 4FB0 ADDIU SP, SP, -8
+BFD09422 CBC1 SW S8, 4(SP)
+BFD09424 0FDD MOVE S8, SP
+BFD09426 0C44 MOVE V0, A0
+BFD09428 0008185E SB V0, 8(S8)
+42: if (led_id < (LED_ID_MAX) )\r
+BFD0942C 0008145E LBU V0, 8(S8)
+BFD09430 0003B042 SLTIU V0, V0, 3
+BFD09434 000B40E2 BEQZC V0, 0xBFD0944E
+43: {\r
+44: return ((LED0_BASE) + (led_id << 8));\r
+BFD09438 0008145E LBU V0, 8(S8)
+BFD0943C 2520 SLL V0, V0, 8
+BFD0943E 0C62 MOVE V1, V0
+BFD09440 A00041A2 LUI V0, 0xA000
+BFD09444 B8005042 ORI V0, V0, -18432
+BFD09446 0526B800 SDC1 F0, 1318(ZERO)
+BFD09448 0526 ADDU V0, V1, V0
+BFD0944A CC05 B 0xBFD09456
+BFD0944C 0C00 NOP
+45: }\r
+46: else\r
+47: {\r
+48: return (LED0_BASE);\r
+BFD0944E A00041A2 LUI V0, 0xA000
+BFD09452 B8005042 ORI V0, V0, -18432
+BFD09454 0FBEB800 SDC1 F0, 4030(ZERO)
+49: }\r
+50: }\r
+BFD09456 0FBE MOVE SP, S8
+BFD09458 4BC1 LW S8, 4(SP)
+BFD0945A 4C05 ADDIU SP, SP, 8
+BFD0945C 459F JR16 RA
+BFD0945E 0C00 NOP
+51: \r
+52: #ifdef LED_ENABLE_VALID_CHECK\r
+53: \r
+54: static uint8_t led_is_valid(uint8_t led_id)\r
+55: {\r
+56: if (led_id < (LED_ID_MAX)) {\r
+57: return true;\r
+58: }\r
+59: return false;\r
+60: }\r
+61: \r
+62: #else\r
+63: \r
+64: static uint8_t led_is_valid(uint8_t led_id) { ( void ) led_id; return (MEC14XX_TRUE); }\r
+BFD09E6C 4FB0 ADDIU SP, SP, -8
+BFD09E6E CBC1 SW S8, 4(SP)
+BFD09E70 0FDD MOVE S8, SP
+BFD09E72 0C44 MOVE V0, A0
+BFD09E74 0008185E SB V0, 8(S8)
+BFD09E78 ED01 LI V0, 1
+BFD09E7A 0FBE MOVE SP, S8
+BFD09E7C 4BC1 LW S8, 4(SP)
+BFD09E7E 4C05 ADDIU SP, SP, 8
+BFD09E80 459F JR16 RA
+BFD09E82 0C00 NOP
+65: \r
+66: #endif\r
+67: \r
+68: \r
+69: /** \r
+70: @brief MEC1404 LED are alternate functions of GPIO pins. \r
+71: @note - \r
+72: LED0 is GPIO157 Function 1\r
+73: LED1 is GPIO156 Function 1\r
+74: LED2 is GPIO104 Function 1\r
+75: */\r
+76: \r
+77: static const uint8_t led_pcr_slp2_bitpos[LED_ID_MAX] = {\r
+78: (PCR_EC2_LED0_SLP_BITPOS),\r
+79: (PCR_EC2_LED1_SLP_BITPOS),\r
+80: (PCR_EC2_LED2_SLP_BITPOS)\r
+81: };\r
+82: \r
+83: \r
+84: static const uint16_t led_gpio_tbl[LED_ID_MAX] = {\r
+85: (((uint16_t)(GPIO_FUNC_1)<<8) + (uint16_t)GPIO_0157_ID),\r
+86: (((uint16_t)(GPIO_FUNC_1)<<8) + (uint16_t)GPIO_0156_ID),\r
+87: (((uint16_t)(GPIO_FUNC_1)<<8) + (uint16_t)GPIO_0104_ID)\r
+88: };\r
+89: \r
+90: \r
+91: \r
+92: /**\r
+93: * led_sleep_en - Enable/Disable gating of clocks on idle to the\r
+94: * BBLED block \r
+95: * \r
+96: *\r
+97: * @param uint8_t sleep_en (1=Enable sleep on idle), (0=No sleep\r
+98: * on idle).\r
+99: * @param uint8_t LED ID (0-3)\r
+100: * @note if LED ID > 3 no action taken.\r
+101: */\r
+102: void led_sleep_en(uint8_t led_id, uint8_t sleep_en)\r
+103: {\r
+BFD05D0C 4FF1 ADDIU SP, SP, -32
+BFD05D0E CBE7 SW RA, 28(SP)
+BFD05D10 CBC6 SW S8, 24(SP)
+BFD05D12 0FDD MOVE S8, SP
+BFD05D14 0C64 MOVE V1, A0
+BFD05D16 0C45 MOVE V0, A1
+BFD05D18 0020187E SB V1, 32(S8)
+BFD05D1C 0024185E SB V0, 36(S8)
+104: uint32_t slp_mask;\r
+105: uint32_t laddr;\r
+106: \r
+107: slp_mask = 0ul;\r
+BFD05D20 0010F81E SW ZERO, 16(S8)
+108: if ( led_is_valid(led_id) ) {\r
+BFD05D24 0020145E LBU V0, 32(S8)
+BFD05D28 0C82 MOVE A0, V0
+BFD05D2A 4F3677E8 JALS led_is_valid
+BFD05D2C 4F36 ADDIU T9, T9, -5
+BFD05D2E 0C00 NOP
+BFD05D30 003F40E2 BEQZC V0, 0xBFD05DB2
+109: slp_mask = (1ul << led_pcr_slp2_bitpos[led_id]);\r
+BFD05D34 0020147E LBU V1, 32(S8)
+BFD05D38 BFD041A2 LUI V0, 0xBFD0
+BFD05D3A 3042BFD0 LDC1 F30, 12354(S0)
+BFD05D3C 01743042 ADDIU V0, V0, 372
+BFD05D40 0526 ADDU V0, V1, V0
+BFD05D42 0920 LBU V0, 0(V0)
+BFD05D44 ED81 LI V1, 1
+BFD05D46 10100062 SLLV V0, V0, V1
+BFD05D48 F85E1010 ADDI ZERO, S0, -1954
+BFD05D4A 0010F85E SW V0, 16(S8)
+110: if ( sleep_en ) {\r
+BFD05D4E 0024145E LBU V0, 36(S8)
+BFD05D52 002040E2 BEQZC V0, 0xBFD05D96
+111: PCR->EC_SLEEP_EN2 |= slp_mask;\r
+BFD05D56 A00841A2 LUI V0, 0xA008
+BFD05D5A 01005042 ORI V0, V0, 256
+BFD05D5E A00841A3 LUI V1, 0xA008
+BFD05D62 01005063 ORI V1, V1, 256
+BFD05D66 6A39 LW A0, 36(V1)
+BFD05D68 0010FC7E LW V1, 16(S8)
+BFD05D6C 44DC OR16 V1, A0
+BFD05D6E E9A9 SW V1, 36(V0)
+112: laddr = led_addr(led_id);\r
+BFD05D70 0020145E LBU V0, 32(S8)
+BFD05D74 0C82 MOVE A0, V0
+BFD05D76 4A1077E8 JALS led_addr
+BFD05D78 4A10 LW S0, 64(SP)
+BFD05D7A 0C00 NOP
+BFD05D7C 0014F85E SW V0, 20(S8)
+113: ((BBLED_TypeDef *)laddr)->CONFIG &= ~(0x03ul);\r
+BFD05D80 0014FC5E LW V0, 20(S8)
+BFD05D84 0014FC7E LW V1, 20(S8)
+BFD05D88 6A30 LW A0, 0(V1)
+BFD05D8A FFFC3060 ADDIU V1, ZERO, -4
+BFD05D8C 449CFFFC LW RA, 17564(GP)
+BFD05D8E 449C AND16 V1, A0
+BFD05D90 E9A0 SW V1, 0(V0)
+BFD05D92 CC0F B 0xBFD05DB2
+BFD05D94 0C00 NOP
+114: } else {\r
+115: PCR->EC_SLEEP_EN2 &= ~(slp_mask);\r
+BFD05D96 A00841A2 LUI V0, 0xA008
+BFD05D9A 01005042 ORI V0, V0, 256
+BFD05D9E A00841A3 LUI V1, 0xA008
+BFD05DA2 01005063 ORI V1, V1, 256
+BFD05DA6 6A39 LW A0, 36(V1)
+BFD05DA8 0010FC7E LW V1, 16(S8)
+BFD05DAC 441B NOT16 V1, V1
+BFD05DAE 449C AND16 V1, A0
+BFD05DB0 E9A9 SW V1, 36(V0)
+116: }\r
+117: }\r
+118: }\r
+BFD05DB2 0FBE MOVE SP, S8
+BFD05DB4 4BE7 LW RA, 28(SP)
+BFD05DB6 4BC6 LW S8, 24(SP)
+BFD05DB8 4C11 ADDIU SP, SP, 32
+BFD05DBA 459F JR16 RA
+BFD05DBC 0C00 NOP
+119: \r
+120: \r
+121: /**\r
+122: * led_reset - Reset the specified LED hardware block.\r
+123: * \r
+124: * @author sworley \r
+125: * \r
+126: * @param led_id 0-based LED ID \r
+127: * @note Sets the LED's soft reset bit and waits for hardware to \r
+128: * clear it. Will wait up to 0x10000 times.\r
+129: */\r
+130: void led_reset(uint8_t led_id)\r
+131: {\r
+BFD07FC8 4FF1 ADDIU SP, SP, -32
+BFD07FCA CBE7 SW RA, 28(SP)
+BFD07FCC CBC6 SW S8, 24(SP)
+BFD07FCE 0FDD MOVE S8, SP
+BFD07FD0 0C44 MOVE V0, A0
+BFD07FD2 0020185E SB V0, 32(S8)
+132: uint32_t p;\r
+133: uint32_t cnt;\r
+134: \r
+135: p = led_addr(led_id);\r
+BFD07FD6 0020145E LBU V0, 32(S8)
+BFD07FDA 0C82 MOVE A0, V0
+BFD07FDC 4A1077E8 JALS led_addr
+BFD07FDE 4A10 LW S0, 64(SP)
+BFD07FE0 0C00 NOP
+BFD07FE2 0014F85E SW V0, 20(S8)
+136: ((BBLED_TypeDef *)p)->CONFIG = (LED_CFG_RESET);\r
+BFD07FE6 0014FC5E LW V0, 20(S8)
+BFD07FEA 00803060 ADDIU V1, ZERO, 128
+BFD07FEE E9A0 SW V1, 0(V0)
+137: \r
+138: cnt = 0x100000UL;\r
+BFD07FF0 001041A2 LUI V0, 0x10
+BFD07FF4 0010F85E SW V0, 16(S8)
+139: while ( ((BBLED_TypeDef *)p)->CONFIG & (LED_CFG_RESET) ) {\r
+BFD07FF8 CC0A B 0xBFD0800E
+BFD07FFA 0C00 NOP
+BFD0800E 0014FC5E LW V0, 20(S8)
+BFD08012 6920 LW V0, 0(V0)
+BFD08014 2D20 ANDI V0, V0, 0x80
+BFD08016 FFF140A2 BNEZC V0, 0xBFD07FFC
+BFD08018 CC02FFF1 LW RA, -13310(S1)
+BFD0801A CC02 B 0xBFD08020
+BFD0801C 0C00 NOP
+140: if ( cnt != 0UL ) {\r
+BFD07FFC 0010FC5E LW V0, 16(S8)
+BFD08000 000D40E2 BEQZC V0, 0xBFD0801E
+141: cnt--;\r
+BFD08004 0010FC5E LW V0, 16(S8)
+BFD08008 6D2E ADDIU V0, V0, -1
+BFD0800A 0010F85E SW V0, 16(S8)
+142: } else {\r
+143: break;\r
+BFD0801E 0C00 NOP
+144: }\r
+145: }\r
+146: } \r
+BFD08020 0FBE MOVE SP, S8
+BFD08022 4BE7 LW RA, 28(SP)
+BFD08024 4BC6 LW S8, 24(SP)
+BFD08026 4C11 ADDIU SP, SP, 32
+BFD08028 459F JR16 RA
+BFD0802A 0C00 NOP
+147: \r
+148: \r
+149: uint8_t led_get_gpio_num(uint8_t led_id)\r
+150: {\r
+BFD099EC 4FB0 ADDIU SP, SP, -8
+BFD099EE CBC1 SW S8, 4(SP)
+BFD099F0 0FDD MOVE S8, SP
+BFD099F2 0C44 MOVE V0, A0
+BFD099F4 0008185E SB V0, 8(S8)
+151: return led_gpio_tbl[(led_id & ((LED_ID_MAX)-1u))];\r
+BFD099F8 0008145E LBU V0, 8(S8)
+BFD099FC 2DA2 ANDI V1, V0, 0x2
+BFD099FE BFD041A2 LUI V0, 0xBFD0
+BFD09A00 25B2BFD0 LDC1 F30, 9650(S0)
+BFD09A02 25B2 SLL V1, V1, 1
+BFD09A04 01783042 ADDIU V0, V0, 376
+BFD09A08 0526 ADDU V0, V1, V0
+BFD09A0A 2920 LHU V0, 0(V0)
+BFD09A0C 2D2D ANDI V0, V0, 0xFF
+152: }\r
+BFD09A0E 0FBE MOVE SP, S8
+BFD09A10 4BC1 LW S8, 4(SP)
+BFD09A12 4C05 ADDIU SP, SP, 8
+BFD09A14 459F JR16 RA
+BFD09A16 0C00 NOP
+153: \r
+154: \r
+155: /**\r
+156: * led_init - Initialize the specified LED \r
+157: * \r
+158: * @author sworley \r
+159: * \r
+160: * @param led_id 0-based LED ID \r
+161: * @note Configures the LED's GPIO pin for LED function and then \r
+162: * peforms a soft reset of the LED hardware.\r
+163: */\r
+164: void led_init(uint8_t led_id)\r
+165: {\r
+BFD07CFC 4FF1 ADDIU SP, SP, -32
+BFD07CFE CBE7 SW RA, 28(SP)
+BFD07D00 CBC6 SW S8, 24(SP)
+BFD07D02 0FDD MOVE S8, SP
+BFD07D04 0C44 MOVE V0, A0
+BFD07D06 0020185E SB V0, 32(S8)
+166: uint16_t ledi;\r
+167: \r
+168: if ( led_id < LED_ID_MAX )\r
+BFD07D0A 0020145E LBU V0, 32(S8)
+BFD07D0E 0003B042 SLTIU V0, V0, 3
+BFD07D12 002040E2 BEQZC V0, 0xBFD07D56
+169: {\r
+170: /* bits[7:0] = GPIO_ID, bits[15:8] = GPIO Function */\r
+171: ledi = led_gpio_tbl[led_id];\r
+BFD07D16 0020147E LBU V1, 32(S8)
+BFD07D1A BFD041A2 LUI V0, 0xBFD0
+BFD07D1C 25B2BFD0 LDC1 F30, 9650(S0)
+BFD07D1E 25B2 SLL V1, V1, 1
+BFD07D20 01783042 ADDIU V0, V0, 376
+BFD07D24 0526 ADDU V0, V1, V0
+BFD07D26 2920 LHU V0, 0(V0)
+BFD07D28 0010385E SH V0, 16(S8)
+172: GPIOPropertySet((ledi & 0xFF), GPIO_PROP_MUX_SEL, (ledi >> 8) & 0xFF);\r
+BFD07D2C 0010345E LHU V0, 16(S8)
+BFD07D30 2D2D ANDI V0, V0, 0xFF
+BFD07D32 0C62 MOVE V1, V0
+BFD07D34 0010345E LHU V0, 16(S8)
+BFD07D38 2521 SRL V0, V0, 8
+BFD07D3A 2D2F ANDI V0, V0, 0xFFFF
+BFD07D3C 0C83 MOVE A0, V1
+BFD07D3E EE87 LI A1, 7
+BFD07D40 0CC2 MOVE A2, V0
+BFD07D42 25CC77E8 JALS GPIOPropertySet
+BFD07D44 25CC SLL V1, A0, 6
+BFD07D46 0C00 NOP
+173: led_reset(ledi & 0xFF);\r
+BFD07D48 0010345E LHU V0, 16(S8)
+BFD07D4C 2D2D ANDI V0, V0, 0xFF
+BFD07D4E 0C82 MOVE A0, V0
+BFD07D50 3FE477E8 JALS led_reset
+BFD07D52 0C003FE4 LH RA, 3072(A0)
+BFD07D54 0C00 NOP
+174: }\r
+175: }\r
+BFD07D56 0FBE MOVE SP, S8
+BFD07D58 4BE7 LW RA, 28(SP)
+BFD07D5A 4BC6 LW S8, 24(SP)
+BFD07D5C 4C11 ADDIU SP, SP, 32
+BFD07D5E 459F JR16 RA
+BFD07D60 0C00 NOP
+176: \r
+177: \r
+178: /**\r
+179: * led_mode_blink - Enable LED hardware blink\r
+180: * \r
+181: * @author sworley \r
+182: * \r
+183: * @param led_id 0-based LED ID\r
+184: * @param duty_cycle duty cycle (0x80 = 50%)\r
+185: * @param prescale sets the blink frequency \r
+186: * @note Blink frequency is (32768 * 255)/(prescale + 1) Hz\r
+187: */\r
+188: void led_mode_blink(uint8_t led_id,\r
+189: uint8_t duty_cycle,\r
+190: uint16_t prescale)\r
+191: {\r
+BFD07914 4FF1 ADDIU SP, SP, -32
+BFD07916 CBE7 SW RA, 28(SP)
+BFD07918 CBC6 SW S8, 24(SP)
+BFD0791A 0FDD MOVE S8, SP
+BFD0791C 0C65 MOVE V1, A1
+BFD0791E 0C46 MOVE V0, A2
+BFD07920 0020189E SB A0, 32(S8)
+BFD07924 0024187E SB V1, 36(S8)
+BFD07928 0028385E SH V0, 40(S8)
+192: uint32_t pLed;\r
+193: \r
+194: pLed = 0UL;\r
+BFD0792C 0010F81E SW ZERO, 16(S8)
+195: \r
+196: if (led_is_valid(led_id)) {\r
+BFD07930 0020145E LBU V0, 32(S8)
+BFD07934 0C82 MOVE A0, V0
+BFD07936 4F3677E8 JALS led_is_valid
+BFD07938 4F36 ADDIU T9, T9, -5
+BFD0793A 0C00 NOP
+BFD0793C 001E40E2 BEQZC V0, 0xBFD0797C
+197: pLed = led_addr(led_id);\r
+BFD07940 0020145E LBU V0, 32(S8)
+BFD07944 0C82 MOVE A0, V0
+BFD07946 4A1077E8 JALS led_addr
+BFD07948 4A10 LW S0, 64(SP)
+BFD0794A 0C00 NOP
+BFD0794C 0010F85E SW V0, 16(S8)
+198: \r
+199: ((BBLED_TypeDef *)pLed)->CONFIG = LED_CFG_CNTL_BLINK;\r
+BFD07950 0010FC5E LW V0, 16(S8)
+BFD07954 ED82 LI V1, 2
+BFD07956 E9A0 SW V1, 0(V0)
+200: ((BBLED_TypeDef *)pLed)->LIMIT = (uint32_t)duty_cycle;\r
+BFD07958 0010FC5E LW V0, 16(S8)
+BFD0795C 0024147E LBU V1, 36(S8)
+BFD07960 E9A1 SW V1, 4(V0)
+201: ((BBLED_TypeDef *)pLed)->DELAY = (uint32_t)prescale;\r
+BFD07962 0010FC5E LW V0, 16(S8)
+BFD07966 0028347E LHU V1, 40(S8)
+BFD0796A E9A2 SW V1, 8(V0)
+202: ((BBLED_TypeDef *)pLed)->CONFIG |= (LED_CFG_EN_UPDATE);\r
+BFD0796C 0010FC5E LW V0, 16(S8)
+BFD07970 0010FC7E LW V1, 16(S8)
+BFD07974 69B0 LW V1, 0(V1)
+BFD07976 00405063 ORI V1, V1, 64
+BFD0797A E9A0 SW V1, 0(V0)
+203: }\r
+204: }\r
+BFD0797C 0FBE MOVE SP, S8
+BFD0797E 4BE7 LW RA, 28(SP)
+BFD07980 4BC6 LW S8, 24(SP)
+BFD07982 4C11 ADDIU SP, SP, 32
+BFD07984 459F JR16 RA
+BFD07986 0C00 NOP
+205: \r
+206: \r
+207: /**\r
+208: * led_out_toggle - Toggle the LED output pin.\r
+209: * \r
+210: * @author sworley \r
+211: * \r
+212: * @param led_id 0-based LED ID.\r
+213: */\r
+214: void led_out_toggle(uint8_t led_id)\r
+215: {\r
+BFD085A8 4FF1 ADDIU SP, SP, -32
+BFD085AA CBE7 SW RA, 28(SP)
+BFD085AC CBC6 SW S8, 24(SP)
+BFD085AE 0FDD MOVE S8, SP
+BFD085B0 0C44 MOVE V0, A0
+BFD085B2 0020185E SB V0, 32(S8)
+216: uint32_t p;\r
+217: \r
+218: if (led_is_valid(led_id)) {\r
+BFD085B6 0020145E LBU V0, 32(S8)
+BFD085BA 0C82 MOVE A0, V0
+BFD085BC 4F3677E8 JALS led_is_valid
+BFD085BE 4F36 ADDIU T9, T9, -5
+BFD085C0 0C00 NOP
+BFD085C2 001740E2 BEQZC V0, 0xBFD085F4
+219: p = led_addr(led_id);\r
+BFD085C6 0020145E LBU V0, 32(S8)
+BFD085CA 0C82 MOVE A0, V0
+BFD085CC 4A1077E8 JALS led_addr
+BFD085CE 4A10 LW S0, 64(SP)
+BFD085D0 0C00 NOP
+BFD085D2 0010F85E SW V0, 16(S8)
+220: \r
+221: if (((BBLED_TypeDef *)p)->CONFIG & LED_CFG_CNTL_MASK) {\r
+BFD085D6 0010FC5E LW V0, 16(S8)
+BFD085DA 6920 LW V0, 0(V0)
+BFD085DC 2D23 ANDI V0, V0, 0x3
+BFD085DE 000540E2 BEQZC V0, 0xBFD085EC
+222: ((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_LO;\r
+BFD085E2 0010FC5E LW V0, 16(S8)
+BFD085E6 E820 SW S0, 0(V0)
+BFD085E8 CC05 B 0xBFD085F4
+BFD085EA 0C00 NOP
+223: } else {\r
+224: ((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_HI;\r
+BFD085EC 0010FC5E LW V0, 16(S8)
+BFD085F0 ED83 LI V1, 3
+BFD085F2 E9A0 SW V1, 0(V0)
+225: }\r
+226: }\r
+227: }\r
+BFD085F4 0FBE MOVE SP, S8
+BFD085F6 4BE7 LW RA, 28(SP)
+BFD085F8 4BC6 LW S8, 24(SP)
+BFD085FA 4C11 ADDIU SP, SP, 32
+BFD085FC 459F JR16 RA
+BFD085FE 0C00 NOP
+228: \r
+229: \r
+230: /**\r
+231: * led_out_high - Set the LED block to drive the pin High\r
+232: * \r
+233: * @author sworley \r
+234: * \r
+235: * @param led_id 0-based LED ID \r
+236: * @note The LED controller will drive the pin High. Depending \r
+237: * upon the external circuit the LED may be in ON or OFF\r
+238: * state.\r
+239: */\r
+240: void led_out_high(uint8_t led_id)\r
+241: {\r
+BFD09210 4FF1 ADDIU SP, SP, -32
+BFD09212 CBE7 SW RA, 28(SP)
+BFD09214 CBC6 SW S8, 24(SP)
+BFD09216 0FDD MOVE S8, SP
+BFD09218 0C44 MOVE V0, A0
+BFD0921A 0020185E SB V0, 32(S8)
+242: uint32_t p;\r
+243: \r
+244: if (led_is_valid(led_id)) {\r
+BFD0921E 0020145E LBU V0, 32(S8)
+BFD09222 0C82 MOVE A0, V0
+BFD09224 4F3677E8 JALS led_is_valid
+BFD09226 4F36 ADDIU T9, T9, -5
+BFD09228 0C00 NOP
+BFD0922A 000C40E2 BEQZC V0, 0xBFD09246
+245: p = led_addr(led_id);\r
+BFD0922E 0020145E LBU V0, 32(S8)
+BFD09232 0C82 MOVE A0, V0
+BFD09234 4A1077E8 JALS led_addr
+BFD09236 4A10 LW S0, 64(SP)
+BFD09238 0C00 NOP
+BFD0923A 0010F85E SW V0, 16(S8)
+246: ((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_HI;\r
+BFD0923E 0010FC5E LW V0, 16(S8)
+BFD09242 ED83 LI V1, 3
+BFD09244 E9A0 SW V1, 0(V0)
+247: }\r
+248: }\r
+BFD09246 0FBE MOVE SP, S8
+BFD09248 4BE7 LW RA, 28(SP)
+BFD0924A 4BC6 LW S8, 24(SP)
+BFD0924C 4C11 ADDIU SP, SP, 32
+BFD0924E 459F JR16 RA
+BFD09250 0C00 NOP
+249: \r
+250: \r
+251: /**\r
+252: * led_out_low - Set the LED block to drive the pin Low\r
+253: * \r
+254: * @author sworley \r
+255: * \r
+256: * @param led_id 0-based LED ID \r
+257: * @note The LED controller will drive the pin Low. Depending \r
+258: * upon the external circuit the LED may be in ON or OFF\r
+259: * state.\r
+260: */\r
+261: void led_out_low(uint8_t led_id)\r
+262: {\r
+BFD09460 4FF1 ADDIU SP, SP, -32
+BFD09462 CBE7 SW RA, 28(SP)
+BFD09464 CBC6 SW S8, 24(SP)
+BFD09466 0FDD MOVE S8, SP
+BFD09468 0C44 MOVE V0, A0
+BFD0946A 0020185E SB V0, 32(S8)
+263: uint32_t p;\r
+264: \r
+265: if (led_is_valid(led_id)) {\r
+BFD0946E 0020145E LBU V0, 32(S8)
+BFD09472 0C82 MOVE A0, V0
+BFD09474 4F3677E8 JALS led_is_valid
+BFD09476 4F36 ADDIU T9, T9, -5
+BFD09478 0C00 NOP
+BFD0947A 000B40E2 BEQZC V0, 0xBFD09494
+266: p = led_addr(led_id);\r
+BFD0947E 0020145E LBU V0, 32(S8)
+BFD09482 0C82 MOVE A0, V0
+BFD09484 4A1077E8 JALS led_addr
+BFD09486 4A10 LW S0, 64(SP)
+BFD09488 0C00 NOP
+BFD0948A 0010F85E SW V0, 16(S8)
+267: ((BBLED_TypeDef *)p)->CONFIG = LED_CFG_CNTL_LO;\r
+BFD0948E 0010FC5E LW V0, 16(S8)
+BFD09492 E820 SW S0, 0(V0)
+268: }\r
+269: }\r
+BFD09494 0FBE MOVE SP, S8
+BFD09496 4BE7 LW RA, 28(SP)
+BFD09498 4BC6 LW S8, 24(SP)
+BFD0949A 4C11 ADDIU SP, SP, 32
+BFD0949C 459F JR16 RA
+BFD0949E 0C00 NOP
+270: \r
+271: \r
+272: #ifdef __cplusplus\r
+273: }\r
+274: #endif\r
+275: \r
+276: /* end mec14xx_bbled.h */\r
+277: /** @}\r
+278: */\r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq26.c ----
+1: /*****************************************************************************\r
+2: * (c) 2013 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq26.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: \r
+29: #include "appcfg.h"\r
+30: #include "platform.h"\r
+31: #include "MEC14xx/mec14xx.h"\r
+32: #include "MEC14xx/mec14xx_girqs.h"\r
+33: #include "MEC14xx/mec14xx_gpio.h"\r
+34: #include "MEC14xx/mec14xx_trace_func.h"\r
+35: \r
+36: \r
+37: #if GIRQ26_DISAGG == 0\r
+38: \r
+39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+40: girq26_isr(void)\r
+41: {\r
+BFD07408 E17C03BD RDPGPR SP, SP
+BFD0740C 00FC036E MFC0 K1, EPC
+BFD0740E 034C00FC INS A3, GP, 13, -12
+BFD07410 10FC034C MFC0 K0, SRSCtl
+BFD07412 4FF110FC ADDI A3, GP, 20465
+BFD07414 4FF1 ADDIU SP, SP, -32
+BFD07416 CB67 SW K1, 28(SP)
+BFD07418 00FC036C MFC0 K1, Status
+BFD0741C CB46 SW K0, 24(SP)
+BFD0741E 00FC034D MFC0 K0, Cause
+BFD07422 CB65 SW K1, 20(SP)
+BFD07424 5040035A SRL K0, K0, 10
+BFD07426 037A5040 ORI V0, ZERO, 890
+BFD07428 7A8C037A INS K1, K0, 10, 6
+BFD0742A 03607A8C ADDIUPC A1, 787296
+BFD0742C 204C0360 INS K1, ZERO, 1, 4
+BFD0742E 036C204C LWC2 V0, 876(T4)
+BFD07430 02FC036C MTC0 K1, Status
+BFD07434 C862 SW V1, 8(SP)
+BFD07436 C841 SW V0, 4(SP)
+BFD07438 4866 LW V1, 24(SP)
+BFD0743A 2DB7 ANDI V1, V1, 0xF
+BFD0743C CBC3 SW S8, 12(SP)
+BFD0743E 0FDD MOVE S8, SP
+42: JTVIC_GROUP_EN_CLR->w = (1ul<<16);\r
+BFD07440 BFFF41A2 LUI V0, 0xBFFF
+BFD07442 5042BFFF LDC1 F31, 20546(RA)
+BFD07444 C50C5042 ORI V0, V0, -15092
+BFD07448 000141A3 LUI V1, 0x1
+BFD0744C E9A0 SW V1, 0(V0)
+43: }\r
+BFD0744E 0FBE MOVE SP, S8
+BFD07450 4846 LW V0, 24(SP)
+BFD07452 2D27 ANDI V0, V0, 0xF
+BFD07454 4BC3 LW S8, 12(SP)
+BFD07456 4862 LW V1, 8(SP)
+BFD07458 4841 LW V0, 4(SP)
+BFD0745A 477C0000 DI ZERO
+BFD0745E 18000000 SLL ZERO, ZERO, 3
+BFD07460 4B471800 SB ZERO, 19271(ZERO)
+BFD07462 4B47 LW K0, 28(SP)
+BFD07464 4B65 LW K1, 20(SP)
+BFD07466 02FC034E MTC0 K0, EPC
+BFD0746A 4B46 LW K0, 24(SP)
+BFD0746C 4C11 ADDIU SP, SP, 32
+BFD0746E 12FC034C MTC0 K0, SRSCtl
+BFD07470 03BD12FC ADDI S7, GP, 957
+BFD07472 F17C03BD WRPGPR SP, SP
+BFD07474 036CF17C JALX 0xBDF00DB0
+BFD07476 02FC036C MTC0 K1, Status
+BFD07478 000002FC SLL S7, GP, 0
+BFD0747A F37C0000 ERET
+BFD0747C 0C00F37C JALX 0xBDF03000
+44: \r
+45: #else\r
+46: \r
+47: void __attribute__((weak, interrupt, nomips16))\r
+48: girq26_b0(void)\r
+49: {\r
+50: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 0);\r
+51: }\r
+52: \r
+53: void __attribute__((weak, interrupt, nomips16))\r
+54: girq26_b1(void)\r
+55: {\r
+56: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 1);\r
+57: }\r
+58: \r
+59: void __attribute__((weak, interrupt, nomips16))\r
+60: girq26_b2(void)\r
+61: {\r
+62: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 2);\r
+63: }\r
+64: \r
+65: void __attribute__((weak, interrupt, nomips16))\r
+66: girq26_b3(void)\r
+67: {\r
+68: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 3);\r
+69: }\r
+70: \r
+71: void __attribute__((weak, interrupt, nomips16))\r
+72: girq26_b4(void)\r
+73: {\r
+74: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 4);\r
+75: }\r
+76: \r
+77: void __attribute__((weak, interrupt, nomips16))\r
+78: girq26_b5(void)\r
+79: {\r
+80: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 5);\r
+81: }\r
+82: \r
+83: void __attribute__((weak, interrupt, nomips16))\r
+84: girq26_b6(void)\r
+85: {\r
+86: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 6);\r
+87: }\r
+88: \r
+89: void __attribute__((weak, interrupt, nomips16))\r
+90: girq26_b7(void)\r
+91: {\r
+92: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 7);\r
+93: }\r
+94: \r
+95: void __attribute__((weak, interrupt, nomips16))\r
+96: girq26_b8(void)\r
+97: {\r
+98: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 8);\r
+99: }\r
+100: \r
+101: void __attribute__((weak, interrupt, nomips16))\r
+102: girq26_b9(void)\r
+103: {\r
+104: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 9);\r
+105: }\r
+106: \r
+107: void __attribute__((weak, interrupt, nomips16))\r
+108: girq26_b10(void)\r
+109: {\r
+110: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 10);\r
+111: }\r
+112: \r
+113: void __attribute__((weak, interrupt, nomips16))\r
+114: girq26_b11(void)\r
+115: {\r
+116: jtvic_dis_clr_source(MEC14xx_GIRQ26_ID, 11);\r
+117: }\r
+118: \r
+119: \r
+120: #endif\r
+121: \r
+122: /* end girq26.c */\r
+123: /** @}\r
+124: */\r
+125: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq25.c ----
+1: /*****************************************************************************\r
+2: * (c) 2013 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq25.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_trace_func.h"\r
+34: \r
+35: \r
+36: #if GIRQ25_DISAGG == 0\r
+37: \r
+38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+39: girq25_isr(void)\r
+40: {\r
+BFD07390 E17C03BD RDPGPR SP, SP
+BFD07394 00FC036E MFC0 K1, EPC
+BFD07396 034C00FC INS A3, GP, 13, -12
+BFD07398 10FC034C MFC0 K0, SRSCtl
+BFD0739A 4FF110FC ADDI A3, GP, 20465
+BFD0739C 4FF1 ADDIU SP, SP, -32
+BFD0739E CB67 SW K1, 28(SP)
+BFD073A0 00FC036C MFC0 K1, Status
+BFD073A4 CB46 SW K0, 24(SP)
+BFD073A6 00FC034D MFC0 K0, Cause
+BFD073AA CB65 SW K1, 20(SP)
+BFD073AC 5040035A SRL K0, K0, 10
+BFD073AE 037A5040 ORI V0, ZERO, 890
+BFD073B0 7A8C037A INS K1, K0, 10, 6
+BFD073B2 03607A8C ADDIUPC A1, 787296
+BFD073B4 204C0360 INS K1, ZERO, 1, 4
+BFD073B6 036C204C LWC2 V0, 876(T4)
+BFD073B8 02FC036C MTC0 K1, Status
+BFD073BC C862 SW V1, 8(SP)
+BFD073BE C841 SW V0, 4(SP)
+BFD073C0 4866 LW V1, 24(SP)
+BFD073C2 2DB7 ANDI V1, V1, 0xF
+BFD073C4 CBC3 SW S8, 12(SP)
+BFD073C6 0FDD MOVE S8, SP
+41: JTVIC_GROUP_EN_CLR->w = (1ul<<15);\r
+BFD073C8 BFFF41A2 LUI V0, 0xBFFF
+BFD073CA 5042BFFF LDC1 F31, 20546(RA)
+BFD073CC C50C5042 ORI V0, V0, -15092
+BFD073D0 80005060 ORI V1, ZERO, -32768
+BFD073D4 E9A0 SW V1, 0(V0)
+42: }\r
+BFD073D6 0FBE MOVE SP, S8
+BFD073D8 4846 LW V0, 24(SP)
+BFD073DA 2D27 ANDI V0, V0, 0xF
+BFD073DC 4BC3 LW S8, 12(SP)
+BFD073DE 4862 LW V1, 8(SP)
+BFD073E0 4841 LW V0, 4(SP)
+BFD073E2 477C0000 DI ZERO
+BFD073E6 18000000 SLL ZERO, ZERO, 3
+BFD073E8 4B471800 SB ZERO, 19271(ZERO)
+BFD073EA 4B47 LW K0, 28(SP)
+BFD073EC 4B65 LW K1, 20(SP)
+BFD073EE 02FC034E MTC0 K0, EPC
+BFD073F2 4B46 LW K0, 24(SP)
+BFD073F4 4C11 ADDIU SP, SP, 32
+BFD073F6 12FC034C MTC0 K0, SRSCtl
+BFD073F8 03BD12FC ADDI S7, GP, 957
+BFD073FA F17C03BD WRPGPR SP, SP
+BFD073FC 036CF17C JALX 0xBDF00DB0
+BFD073FE 02FC036C MTC0 K1, Status
+BFD07400 000002FC SLL S7, GP, 0
+BFD07402 F37C0000 ERET
+BFD07404 0C00F37C JALX 0xBDF03000
+43: \r
+44: #else\r
+45: \r
+46: void __attribute__((weak, interrupt, nomips16))\r
+47: girq25_b0(void)\r
+48: {\r
+49: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 0);\r
+50: }\r
+51: \r
+52: void __attribute__((weak, interrupt, nomips16))\r
+53: girq25_b1(void)\r
+54: {\r
+55: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 1);\r
+56: }\r
+57: \r
+58: void __attribute__((weak, interrupt, nomips16))\r
+59: girq25_b2(void)\r
+60: {\r
+61: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 2);\r
+62: }\r
+63: \r
+64: void __attribute__((weak, interrupt, nomips16))\r
+65: girq25_b3(void)\r
+66: {\r
+67: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 3);\r
+68: }\r
+69: \r
+70: void __attribute__((weak, interrupt, nomips16))\r
+71: girq25_b4(void)\r
+72: {\r
+73: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 4);\r
+74: }\r
+75: \r
+76: void __attribute__((weak, interrupt, nomips16))\r
+77: girq25_b5(void)\r
+78: {\r
+79: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 5);\r
+80: }\r
+81: \r
+82: void __attribute__((weak, interrupt, nomips16))\r
+83: girq25_b6(void)\r
+84: {\r
+85: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 6);\r
+86: }\r
+87: \r
+88: void __attribute__((weak, interrupt, nomips16))\r
+89: girq25_b7(void)\r
+90: {\r
+91: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 7);\r
+92: }\r
+93: \r
+94: void __attribute__((weak, interrupt, nomips16))\r
+95: girq25_b8(void)\r
+96: {\r
+97: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 8);\r
+98: }\r
+99: \r
+100: void __attribute__((weak, interrupt, nomips16))\r
+101: girq25_b9(void)\r
+102: {\r
+103: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 9);\r
+104: }\r
+105: \r
+106: void __attribute__((weak, interrupt, nomips16))\r
+107: girq25_b10(void)\r
+108: {\r
+109: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 10);\r
+110: }\r
+111: \r
+112: void __attribute__((weak, interrupt, nomips16))\r
+113: girq25_b11(void)\r
+114: {\r
+115: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 11);\r
+116: }\r
+117: \r
+118: void __attribute__((weak, interrupt, nomips16))\r
+119: girq25_b12(void)\r
+120: {\r
+121: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 12);\r
+122: }\r
+123: \r
+124: void __attribute__((weak, interrupt, nomips16))\r
+125: girq25_b13(void)\r
+126: {\r
+127: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 13);\r
+128: }\r
+129: \r
+130: void __attribute__((weak, interrupt, nomips16))\r
+131: girq25_b14(void)\r
+132: {\r
+133: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 14);\r
+134: }\r
+135: \r
+136: void __attribute__((weak, interrupt, nomips16))\r
+137: girq25_b15(void)\r
+138: {\r
+139: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 15);\r
+140: }\r
+141: \r
+142: void __attribute__((weak, interrupt, nomips16))\r
+143: girq25_b16(void)\r
+144: {\r
+145: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 16);\r
+146: }\r
+147: \r
+148: void __attribute__((weak, interrupt, nomips16))\r
+149: girq25_b17(void)\r
+150: {\r
+151: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 17);\r
+152: }\r
+153: \r
+154: void __attribute__((weak, interrupt, nomips16))\r
+155: girq25_b18(void)\r
+156: {\r
+157: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 18);\r
+158: }\r
+159: \r
+160: void __attribute__((weak, interrupt, nomips16))\r
+161: girq25_b19(void)\r
+162: {\r
+163: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 19);\r
+164: }\r
+165: \r
+166: void __attribute__((weak, interrupt, nomips16))\r
+167: girq25_b20(void)\r
+168: {\r
+169: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 20);\r
+170: }\r
+171: \r
+172: void __attribute__((weak, interrupt, nomips16))\r
+173: girq25_b21(void)\r
+174: {\r
+175: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 21);\r
+176: }\r
+177: \r
+178: void __attribute__((weak, interrupt, nomips16))\r
+179: girq25_b22(void)\r
+180: {\r
+181: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 22);\r
+182: }\r
+183: \r
+184: void __attribute__((weak, interrupt, nomips16))\r
+185: girq25_b23(void)\r
+186: {\r
+187: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 23);\r
+188: }\r
+189: \r
+190: void __attribute__((weak, interrupt, nomips16))\r
+191: girq25_b24(void)\r
+192: {\r
+193: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 24);\r
+194: }\r
+195: \r
+196: void __attribute__((weak, interrupt, nomips16))\r
+197: girq25_b25(void)\r
+198: {\r
+199: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 25);\r
+200: }\r
+201: \r
+202: void __attribute__((weak, interrupt, nomips16))\r
+203: girq25_b26(void)\r
+204: {\r
+205: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 26);\r
+206: }\r
+207: \r
+208: void __attribute__((weak, interrupt, nomips16))\r
+209: girq25_b27(void)\r
+210: {\r
+211: jtvic_dis_clr_source(MEC14xx_GIRQ25_ID, 27);\r
+212: }\r
+213: \r
+214: \r
+215: #endif\r
+216: \r
+217: /* end girq25.c */\r
+218: /** @}\r
+219: */\r
+220: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq24.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq24.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_bbled.h"\r
+34: #include "MEC14xx/mec14xx_trace_func.h"\r
+35: \r
+36: \r
+37: typedef void (* GIRQ24_FPVU8)(uint8_t);\r
+38: \r
+39: \r
+40: /* MIPS M14K internal counter is connected to GIRQ24 bit[0]\r
+41: * It is a simple counter which fires an interrupt when its \r
+42: * count value is equal to a match value.\r
+43: * \r
+44: */\r
+45: \r
+46: #if GIRQ24_DISAGG == 0\r
+47: \r
+48: \r
+49: void girq24_dflt_handler(uint8_t inum)\r
+50: {\r
+51: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].EN_CLR = (1ul << inum);\r
+52: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << inum);\r
+53: }\r
+54: \r
+55: void __attribute__((weak)) m14k_counter_handler(uint8_t inum)\r
+56: {\r
+57: uint32_t r;\r
+58: \r
+59: (void) inum;\r
+60: \r
+61: r = _CP0_GET_COUNT();\r
+62: r += (M14K_TIMER_COMPARE);\r
+63: /* Write of CP0.Compare clears status in M14K */\r
+64: _CP0_SET_COUNT(r);\r
+65: \r
+66: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0);\r
+67: \r
+68: }\r
+69: \r
+70: /*\r
+71: * TODO - FreeRTOS M14K Software Interrupt 0 handler\r
+72: * is vPortYieldISR in port_asm.S\r
+73: * vPortYieldISR was designed to be entered directly by the\r
+74: * CPU not via a higher level ISR handler.\r
+75: * One work-around is to modify vPortYieldISR to do the work\r
+76: * of girq24_handler below. It must determine which GIRQ24 source\r
+77: * was active: M14K counter, SoftIRQ0, or SoftIRQ1.\r
+78: */\r
+79: void __attribute__((weak)) m14k_soft_irq0(uint8_t inum)\r
+80: {\r
+81: (void) inum;\r
+82: \r
+83: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 1);\r
+84: \r
+85: }\r
+86: \r
+87: void __attribute__((weak)) m14k_soft_irq1(uint8_t inum)\r
+88: {\r
+89: (void) inum;\r
+90: \r
+91: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 2);\r
+92: \r
+93: }\r
+94: \r
+95: void girq24_b_0_2( void )\r
+96: {\r
+97: uint32_t d;\r
+98: \r
+99: d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].RESULT & (GIRQ24_SRC_MASK);\r
+100: \r
+101: if ( d & (1ul << 0) )\r
+102: {\r
+103: m14k_counter_handler(0);\r
+104: }\r
+105: \r
+106: if ( d & (1ul << 2) )\r
+107: {\r
+108: m14k_soft_irq1(2);\r
+109: }\r
+110: }\r
+111: \r
+112: \r
+113: const GIRQ24_FPVU8 girq24_htable[GIRQ24_NUM_SOURCES] =\r
+114: {\r
+115: m14k_counter_handler, /* m14k_counter_handler, */\r
+116: m14k_soft_irq0, /* m14k_soft_irq0, */\r
+117: m14k_soft_irq1, /* m14k_soft_irq1 */\r
+118: };\r
+119: \r
+120: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+121: girq24_isr(void)\r
+122: {\r
+123: uint32_t d;\r
+124: uint8_t bitpos;\r
+125: \r
+126: d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].RESULT & (GIRQ24_SRC_MASK);\r
+127: while ( 0 != d )\r
+128: {\r
+129: bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);\r
+130: (girq24_htable[bitpos])(bitpos);\r
+131: d &= ~(1ul << bitpos);\r
+132: }\r
+133: }\r
+134: \r
+135: #else\r
+136: \r
+137: void __attribute__((weak, interrupt, nomips16))\r
+138: girq24_b0(void)\r
+139: {\r
+BFD065A8 E17C03BD RDPGPR SP, SP
+BFD065AC 00FC036E MFC0 K1, EPC
+BFD065AE 034C00FC INS A3, GP, 13, -12
+BFD065B0 10FC034C MFC0 K0, SRSCtl
+BFD065B2 4FED10FC ADDI A3, GP, 20461
+BFD065B4 4FED ADDIU SP, SP, -40
+BFD065B6 CB69 SW K1, 36(SP)
+BFD065B8 00FC036C MFC0 K1, Status
+BFD065BC CB48 SW K0, 32(SP)
+BFD065BE 00FC034D MFC0 K0, Cause
+BFD065C2 CB67 SW K1, 28(SP)
+BFD065C4 5040035A SRL K0, K0, 10
+BFD065C6 037A5040 ORI V0, ZERO, 890
+BFD065C8 7A8C037A INS K1, K0, 10, 6
+BFD065CA 03607A8C ADDIUPC A1, 787296
+BFD065CC 204C0360 INS K1, ZERO, 1, 4
+BFD065CE 036C204C LWC2 V0, 876(T4)
+BFD065D0 02FC036C MTC0 K1, Status
+BFD065D4 C864 SW V1, 16(SP)
+BFD065D6 C843 SW V0, 12(SP)
+BFD065D8 4868 LW V1, 32(SP)
+BFD065DA 2DB7 ANDI V1, V1, 0xF
+BFD065DC CBC5 SW S8, 20(SP)
+BFD065DE 0FDD MOVE S8, SP
+140: uint32_t r;\r
+141: \r
+142: r = _CP0_GET_COUNT();\r
+BFD065E0 00FC0049 MFC0 V0, Count
+BFD065E4 0000F85E SW V0, 0(S8)
+143: r += (M14K_TIMER_COMPARE);\r
+BFD065E8 0000FC7E LW V1, 0(S8)
+BFD065EC 00B741A2 LUI V0, 0xB7
+BFD065F0 1B005042 ORI V0, V0, 6912
+BFD065F2 05261B00 SB T8, 1318(ZERO)
+BFD065F4 0526 ADDU V0, V1, V0
+BFD065F6 0000F85E SW V0, 0(S8)
+144: _CP0_SET_COUNT(r);\r
+BFD065FA 0000FC5E LW V0, 0(S8)
+BFD065FE 02FC0049 MTC0 V0, Count
+BFD06600 000002FC SLL S7, GP, 0
+BFD06602 18000000 SLL ZERO, ZERO, 3
+BFD06604 41A21800 SB ZERO, 16802(ZERO)
+145: \r
+146: JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0); \r
+BFD06606 BFFF41A2 LUI V0, 0xBFFF
+BFD06608 5042BFFF LDC1 F31, 20546(RA)
+BFD0660A C0005042 ORI V0, V0, -16384
+BFD0660E ED81 LI V1, 1
+BFD06610 0100F862 SW V1, 256(V0)
+147: }\r
+BFD06614 0FBE MOVE SP, S8
+BFD06616 4848 LW V0, 32(SP)
+BFD06618 2D27 ANDI V0, V0, 0xF
+BFD0661A 4BC5 LW S8, 20(SP)
+BFD0661C 4864 LW V1, 16(SP)
+BFD0661E 4843 LW V0, 12(SP)
+BFD06620 477C0000 DI ZERO
+BFD06624 18000000 SLL ZERO, ZERO, 3
+BFD06626 4B491800 SB ZERO, 19273(ZERO)
+BFD06628 4B49 LW K0, 36(SP)
+BFD0662A 4B67 LW K1, 28(SP)
+BFD0662C 02FC034E MTC0 K0, EPC
+BFD06630 4B48 LW K0, 32(SP)
+BFD06632 4C15 ADDIU SP, SP, 40
+BFD06634 12FC034C MTC0 K0, SRSCtl
+BFD06636 03BD12FC ADDI S7, GP, 957
+BFD06638 F17C03BD WRPGPR SP, SP
+BFD0663A 036CF17C JALX 0xBDF00DB0
+BFD0663C 02FC036C MTC0 K1, Status
+BFD0663E 000002FC SLL S7, GP, 0
+BFD06640 F37C0000 ERET
+BFD06642 4FEDF37C JALX 0xBDF13FB4
+148: \r
+149: void __attribute__((weak, interrupt, nomips16))\r
+150: girq24_b1(void)\r
+151: {\r
+BFD0465C E17C03BD RDPGPR SP, SP
+BFD04660 00FC036E MFC0 K1, EPC
+BFD04662 034C00FC INS A3, GP, 13, -12
+BFD04664 10FC034C MFC0 K0, SRSCtl
+BFD04666 4FC510FC ADDI A3, GP, 20421
+BFD04668 4FC5 ADDIU SP, SP, -120
+BFD0466A CB7D SW K1, 116(SP)
+BFD0466C 00FC036C MFC0 K1, Status
+BFD04670 CB5C SW K0, 112(SP)
+BFD04672 00FC034D MFC0 K0, Cause
+BFD04676 CB7B SW K1, 108(SP)
+BFD04678 5040035A SRL K0, K0, 10
+BFD0467A 037A5040 ORI V0, ZERO, 890
+BFD0467C 7A8C037A INS K1, K0, 10, 6
+BFD0467E 03607A8C ADDIUPC A1, 787296
+BFD04680 204C0360 INS K1, ZERO, 1, 4
+BFD04682 036C204C LWC2 V0, 876(T4)
+BFD04684 02FC036C MTC0 K1, Status
+BFD04688 C867 SW V1, 28(SP)
+BFD0468A C846 SW V0, 24(SP)
+BFD0468C 487C LW V1, 112(SP)
+BFD0468E 2DB7 ANDI V1, V1, 0xF
+BFD04690 001140A3 BNEZC V1, 0xBFD046B6
+BFD04694 CBF7 SW RA, 92(SP)
+BFD04696 CBD6 SW S8, 88(SP)
+BFD04698 CB35 SW T9, 84(SP)
+BFD0469A CB14 SW T8, 80(SP)
+BFD0469C C9F3 SW T7, 76(SP)
+BFD0469E C9D2 SW T6, 72(SP)
+BFD046A0 C9B1 SW T5, 68(SP)
+BFD046A2 C990 SW T4, 64(SP)
+BFD046A4 C96F SW T3, 60(SP)
+BFD046A6 C94E SW T2, 56(SP)
+BFD046A8 C92D SW T1, 52(SP)
+BFD046AA C90C SW T0, 48(SP)
+BFD046AC C8EB SW A3, 44(SP)
+BFD046AE C8CA SW A2, 40(SP)
+BFD046B0 C8A9 SW A1, 36(SP)
+BFD046B2 C888 SW A0, 32(SP)
+BFD046B4 C825 SW AT, 20(SP)
+BFD046B6 4642 MFLO V0
+BFD046B8 C859 SW V0, 100(SP)
+BFD046BA 4603 MFHI V1
+BFD046BC C878 SW V1, 96(SP)
+BFD046BE 0FDD MOVE S8, SP
+152: \r
+153: _CP0_BIC_CAUSE(0x100ul);\r
+BFD046C0 01003040 ADDIU V0, ZERO, 256
+BFD046C2 006D0100 PRECR.QB.PH ZERO, ZERO, T0
+BFD046C4 00FC006D MFC0 V1, Cause
+BFD046C6 0C0000FC SLL A3, GP, 1
+BFD046C8 0C00 NOP
+BFD046CA 4412 NOT16 V0, V0
+BFD046CC 4493 AND16 V0, V1
+BFD046CE 02FC004D MTC0 V0, Cause
+BFD046D0 000002FC SLL S7, GP, 0
+BFD046D2 18000000 SLL ZERO, ZERO, 3
+BFD046D4 EE101800 SB ZERO, -4592(ZERO)
+154: \r
+155: jtvic_clr_source(MEC14xx_GIRQ24_ID, 1);\r
+BFD046D6 EE10 LI A0, 16
+BFD046D8 EE81 LI A1, 1
+BFD046DA 44FA77E8 JALS jtvic_clr_source
+BFD046DC 44FA OR16 A3, V0
+BFD046DE 0C00 NOP
+156: }\r
+BFD046E0 0FBE MOVE SP, S8
+BFD046E2 4859 LW V0, 100(SP)
+BFD046E4 3D7C0002 MTLO V0
+BFD046E6 48783D7C LH T3, 18552(GP)
+BFD046E8 4878 LW V1, 96(SP)
+BFD046EA 2D7C0003 MTHI V1
+BFD046EC 2D7C ANDI V0, A3, 0x40
+BFD046EE 485C LW V0, 112(SP)
+BFD046F0 2D27 ANDI V0, V0, 0xF
+BFD046F2 001340A2 BNEZC V0, 0xBFD0471C
+BFD046F6 4BF7 LW RA, 92(SP)
+BFD046F8 4BD6 LW S8, 88(SP)
+BFD046FA 4B35 LW T9, 84(SP)
+BFD046FC 4B14 LW T8, 80(SP)
+BFD046FE 49F3 LW T7, 76(SP)
+BFD04700 49D2 LW T6, 72(SP)
+BFD04702 49B1 LW T5, 68(SP)
+BFD04704 4990 LW T4, 64(SP)
+BFD04706 496F LW T3, 60(SP)
+BFD04708 494E LW T2, 56(SP)
+BFD0470A 492D LW T1, 52(SP)
+BFD0470C 490C LW T0, 48(SP)
+BFD0470E 48EB LW A3, 44(SP)
+BFD04710 48CA LW A2, 40(SP)
+BFD04712 48A9 LW A1, 36(SP)
+BFD04714 4888 LW A0, 32(SP)
+BFD04716 4867 LW V1, 28(SP)
+BFD04718 4846 LW V0, 24(SP)
+BFD0471A 4825 LW AT, 20(SP)
+BFD0471C 477C0000 DI ZERO
+BFD04720 18000000 SLL ZERO, ZERO, 3
+BFD04722 4B5D1800 SB ZERO, 19293(ZERO)
+BFD04724 4B5D LW K0, 116(SP)
+BFD04726 4B7B LW K1, 108(SP)
+BFD04728 02FC034E MTC0 K0, EPC
+BFD0472C 4B5C LW K0, 112(SP)
+BFD0472E 4C3D ADDIU SP, SP, 120
+BFD04730 12FC034C MTC0 K0, SRSCtl
+BFD04732 03BD12FC ADDI S7, GP, 957
+BFD04734 F17C03BD WRPGPR SP, SP
+BFD04736 036CF17C JALX 0xBDF00DB0
+BFD04738 02FC036C MTC0 K1, Status
+BFD0473A 000002FC SLL S7, GP, 0
+BFD0473C F37C0000 ERET
+BFD0473E 03BDF37C JALX 0xBDF00EF4
+157: \r
+158: void __attribute__((weak, interrupt, nomips16))\r
+159: girq24_b2(void)\r
+160: {\r
+BFD04740 E17C03BD RDPGPR SP, SP
+BFD04744 00FC036E MFC0 K1, EPC
+BFD04746 034C00FC INS A3, GP, 13, -12
+BFD04748 10FC034C MFC0 K0, SRSCtl
+BFD0474A 4FC510FC ADDI A3, GP, 20421
+BFD0474C 4FC5 ADDIU SP, SP, -120
+BFD0474E CB7D SW K1, 116(SP)
+BFD04750 00FC036C MFC0 K1, Status
+BFD04754 CB5C SW K0, 112(SP)
+BFD04756 00FC034D MFC0 K0, Cause
+BFD0475A CB7B SW K1, 108(SP)
+BFD0475C 5040035A SRL K0, K0, 10
+BFD0475E 037A5040 ORI V0, ZERO, 890
+BFD04760 7A8C037A INS K1, K0, 10, 6
+BFD04762 03607A8C ADDIUPC A1, 787296
+BFD04764 204C0360 INS K1, ZERO, 1, 4
+BFD04766 036C204C LWC2 V0, 876(T4)
+BFD04768 02FC036C MTC0 K1, Status
+BFD0476C C867 SW V1, 28(SP)
+BFD0476E C846 SW V0, 24(SP)
+BFD04770 487C LW V1, 112(SP)
+BFD04772 2DB7 ANDI V1, V1, 0xF
+BFD04774 001140A3 BNEZC V1, 0xBFD0479A
+BFD04778 CBF7 SW RA, 92(SP)
+BFD0477A CBD6 SW S8, 88(SP)
+BFD0477C CB35 SW T9, 84(SP)
+BFD0477E CB14 SW T8, 80(SP)
+BFD04780 C9F3 SW T7, 76(SP)
+BFD04782 C9D2 SW T6, 72(SP)
+BFD04784 C9B1 SW T5, 68(SP)
+BFD04786 C990 SW T4, 64(SP)
+BFD04788 C96F SW T3, 60(SP)
+BFD0478A C94E SW T2, 56(SP)
+BFD0478C C92D SW T1, 52(SP)
+BFD0478E C90C SW T0, 48(SP)
+BFD04790 C8EB SW A3, 44(SP)
+BFD04792 C8CA SW A2, 40(SP)
+BFD04794 C8A9 SW A1, 36(SP)
+BFD04796 C888 SW A0, 32(SP)
+BFD04798 C825 SW AT, 20(SP)
+BFD0479A 4642 MFLO V0
+BFD0479C C859 SW V0, 100(SP)
+BFD0479E 4603 MFHI V1
+BFD047A0 C878 SW V1, 96(SP)
+BFD047A2 0FDD MOVE S8, SP
+161: \r
+162: _CP0_BIC_CAUSE(0x200ul);\r
+BFD047A4 02003040 ADDIU V0, ZERO, 512
+BFD047A6 006D0200 PRECR.QB.PH ZERO, ZERO, S0
+BFD047A8 00FC006D MFC0 V1, Cause
+BFD047AA 0C0000FC SLL A3, GP, 1
+BFD047AC 0C00 NOP
+BFD047AE 4412 NOT16 V0, V0
+BFD047B0 4493 AND16 V0, V1
+BFD047B2 02FC004D MTC0 V0, Cause
+BFD047B4 000002FC SLL S7, GP, 0
+BFD047B6 18000000 SLL ZERO, ZERO, 3
+BFD047B8 EE101800 SB ZERO, -4592(ZERO)
+163: \r
+164: jtvic_clr_source(MEC14xx_GIRQ24_ID, 2);\r
+BFD047BA EE10 LI A0, 16
+BFD047BC EE82 LI A1, 2
+BFD047BE 44FA77E8 JALS jtvic_clr_source
+BFD047C0 44FA OR16 A3, V0
+BFD047C2 0C00 NOP
+165: }\r
+BFD047C4 0FBE MOVE SP, S8
+BFD047C6 4859 LW V0, 100(SP)
+BFD047C8 3D7C0002 MTLO V0
+BFD047CA 48783D7C LH T3, 18552(GP)
+BFD047CC 4878 LW V1, 96(SP)
+BFD047CE 2D7C0003 MTHI V1
+BFD047D0 2D7C ANDI V0, A3, 0x40
+BFD047D2 485C LW V0, 112(SP)
+BFD047D4 2D27 ANDI V0, V0, 0xF
+BFD047D6 001340A2 BNEZC V0, 0xBFD04800
+BFD047DA 4BF7 LW RA, 92(SP)
+BFD047DC 4BD6 LW S8, 88(SP)
+BFD047DE 4B35 LW T9, 84(SP)
+BFD047E0 4B14 LW T8, 80(SP)
+BFD047E2 49F3 LW T7, 76(SP)
+BFD047E4 49D2 LW T6, 72(SP)
+BFD047E6 49B1 LW T5, 68(SP)
+BFD047E8 4990 LW T4, 64(SP)
+BFD047EA 496F LW T3, 60(SP)
+BFD047EC 494E LW T2, 56(SP)
+BFD047EE 492D LW T1, 52(SP)
+BFD047F0 490C LW T0, 48(SP)
+BFD047F2 48EB LW A3, 44(SP)
+BFD047F4 48CA LW A2, 40(SP)
+BFD047F6 48A9 LW A1, 36(SP)
+BFD047F8 4888 LW A0, 32(SP)
+BFD047FA 4867 LW V1, 28(SP)
+BFD047FC 4846 LW V0, 24(SP)
+BFD047FE 4825 LW AT, 20(SP)
+BFD04800 477C0000 DI ZERO
+BFD04804 18000000 SLL ZERO, ZERO, 3
+BFD04806 4B5D1800 SB ZERO, 19293(ZERO)
+BFD04808 4B5D LW K0, 116(SP)
+BFD0480A 4B7B LW K1, 108(SP)
+BFD0480C 02FC034E MTC0 K0, EPC
+BFD04810 4B5C LW K0, 112(SP)
+BFD04812 4C3D ADDIU SP, SP, 120
+BFD04814 12FC034C MTC0 K0, SRSCtl
+BFD04816 03BD12FC ADDI S7, GP, 957
+BFD04818 F17C03BD WRPGPR SP, SP
+BFD0481A 036CF17C JALX 0xBDF00DB0
+BFD0481C 02FC036C MTC0 K1, Status
+BFD0481E 000002FC SLL S7, GP, 0
+BFD04820 F37C0000 ERET
+BFD04822 4FEDF37C JALX 0xBDF13FB4
+166: \r
+167: #endif\r
+168: \r
+169: /* end girq24.c */\r
+170: /** @}\r
+171: */\r
+172: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq23.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq23.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_bbled.h"\r
+34: #include "MEC14xx/mec14xx_trace_func.h"\r
+35: \r
+36: \r
+37: typedef void (* GIRQ23_FPVU8)(uint8_t);\r
+38: \r
+39: #if GIRQ23_DISAGG == 0\r
+40: \r
+41: /*\r
+42: * FreeRTOS ISR for HW timer used as RTOS tick.\r
+43: * Implemented in MEC14xx FreeRTOS porting layer, port_asm.S\r
+44: * It save/restores CPU context and clears HW timer interrupt \r
+45: * status in JTVIC. On each timer tick it checks if any task \r
+46: * requires service. If yes then it triggers the PendSV low \r
+47: * priority software interrupt.\r
+48: * Issue:\r
+49: * When aggregated girq23_isr save CPU context but this context \r
+50: * is not the same as a FreeRTOS context save. If the RTOS timer \r
+51: * is active then girq23_isr would call vPortTickInterruptHandler \r
+52: * which uses FreeRTOS portSAVE_CONTEXT macro to save RTOS + CPU \r
+53: * context. At this point you have two context saves on the stack.\r
+54: * There is a problem:\r
+55: * vPortTickInterruptHandler does not return but exits using \r
+56: * portRESTORE_CONTEXT. This means the context save performed \r
+57: * by aggregated girq23_isr is left on the stack. Eventually \r
+58: * a stack overflow will occur.\r
+59: * \r
+60: * Solutions:\r
+61: * 1. vPortTickInterruptHandler must be modified to handle scan \r
+62: * GIRQ23 Result bits and all the respective handler. All \r
+63: * other GIRQ23 source are called as hook functions.\r
+64: * \r
+65: * 2. Do not use vPortTickInterruptHandler.\r
+66: * Modify girq23_isr here to use FreeRTOS portSAVE_CONTEXT \r
+67: * and portRESTORE_CONTEXT macros. \r
+68: * If RTOS timer is active interrupt then call vPortIncrementTick \r
+69: * as vPortTickInterruptHandler does.\r
+70: * For all other GIRQ23 sources call the respective handlers.\r
+71: * \r
+72: * NOTE: for both of the above solutions a we must either:\r
+73: * A. Service one source only resulting in GIRQ23 firing multiple \r
+74: * times if more than one source is active.\r
+75: * B. Service all active sources with RTOS Timer checked first.\r
+76: * \r
+77: * We will implement 1A with a single hook for all other sources.\r
+78: * \r
+79: */\r
+80: \r
+81: extern void vPortIncrementTick(void);\r
+82: \r
+83: void girq23_dflt_handler(uint8_t inum)\r
+84: {\r
+85: JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].EN_CLR = (1ul << inum);\r
+86: JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << inum);\r
+87: }\r
+88: \r
+89: void __attribute__((weak)) rtos_tmr_handler(uint8_t inum)\r
+90: {\r
+91: (void) inum;\r
+92: \r
+93: JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 4);\r
+94: }\r
+95: \r
+96: const GIRQ23_FPVU8 girq23_htable[GIRQ23_NUM_SOURCES] =\r
+97: {\r
+98: girq23_dflt_handler, /* btmr0_handler, */\r
+99: girq23_dflt_handler, /* btmr1_handler, */\r
+100: girq23_dflt_handler, /* btmr2_handler, */\r
+101: girq23_dflt_handler, /* btmr3_handler, */\r
+102: vPortIncrementTick,\r
+103: girq23_dflt_handler, /* hib_tmr_handler, */\r
+104: girq23_dflt_handler, /* week_tmr_handler, */\r
+105: girq23_dflt_handler, /* week_tmr_handler, */\r
+106: girq23_dflt_handler, /* week_tmr_handler, */\r
+107: girq23_dflt_handler, /* week_tmr_handler, */\r
+108: girq23_dflt_handler, /* week_tmr_handler, */\r
+109: girq23_dflt_handler, /* vci_handler, */\r
+110: girq23_dflt_handler, /* vci_handler, */\r
+111: girq23_dflt_handler, /* vci_handler, */\r
+112: };\r
+113: \r
+114: /* Called by FreeRTOS vPortTickInterruptHandler(girq23_isr) \r
+115: * after saving FreeRTOS context \r
+116: */\r
+117: void girq23_handler(void)\r
+118: {\r
+119: uint32_t d;\r
+120: uint8_t bitpos;\r
+121: \r
+122: d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].RESULT & (GIRQ23_SRC_MASK);\r
+123: while ( 0 != d )\r
+124: {\r
+125: bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);\r
+126: (girq23_htable[bitpos])(bitpos);\r
+127: d &= ~(1ul << bitpos);\r
+128: }\r
+129: }\r
+130: \r
+131: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+132: girq23_isr(void)\r
+133: {\r
+134: uint32_t d;\r
+135: uint8_t bitpos;\r
+136: \r
+137: d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].RESULT & (GIRQ23_SRC_MASK);\r
+138: while ( 0 != d )\r
+139: {\r
+140: bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);\r
+141: (girq23_htable[bitpos])(bitpos);\r
+142: d &= ~(1ul << bitpos);\r
+143: } \r
+144: }\r
+145: \r
+146: #else\r
+147: \r
+148: \r
+149: /* 16-bit Basic Timer 0 */\r
+150: void __attribute__((weak, interrupt, nomips16))\r
+151: girq23_b0(void)\r
+152: {\r
+BFD072A0 E17C03BD RDPGPR SP, SP
+BFD072A4 00FC036E MFC0 K1, EPC
+BFD072A6 034C00FC INS A3, GP, 13, -12
+BFD072A8 10FC034C MFC0 K0, SRSCtl
+BFD072AA 4FF110FC ADDI A3, GP, 20465
+BFD072AC 4FF1 ADDIU SP, SP, -32
+BFD072AE CB67 SW K1, 28(SP)
+BFD072B0 00FC036C MFC0 K1, Status
+BFD072B4 CB46 SW K0, 24(SP)
+BFD072B6 00FC034D MFC0 K0, Cause
+BFD072BA CB65 SW K1, 20(SP)
+BFD072BC 5040035A SRL K0, K0, 10
+BFD072BE 037A5040 ORI V0, ZERO, 890
+BFD072C0 7A8C037A INS K1, K0, 10, 6
+BFD072C2 03607A8C ADDIUPC A1, 787296
+BFD072C4 204C0360 INS K1, ZERO, 1, 4
+BFD072C6 036C204C LWC2 V0, 876(T4)
+BFD072C8 02FC036C MTC0 K1, Status
+BFD072CC C862 SW V1, 8(SP)
+BFD072CE C841 SW V0, 4(SP)
+BFD072D0 4866 LW V1, 24(SP)
+BFD072D2 2DB7 ANDI V1, V1, 0xF
+BFD072D4 CBC3 SW S8, 12(SP)
+BFD072D6 0FDD MOVE S8, SP
+153: JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 0); \r
+BFD072D8 BFFF41A2 LUI V0, 0xBFFF
+BFD072DA 5042BFFF LDC1 F31, 20546(RA)
+BFD072DC C0005042 ORI V0, V0, -16384
+BFD072E0 ED81 LI V1, 1
+BFD072E2 00F0F862 SW V1, 240(V0)
+154: }\r
+BFD072E6 0FBE MOVE SP, S8
+BFD072E8 4846 LW V0, 24(SP)
+BFD072EA 2D27 ANDI V0, V0, 0xF
+BFD072EC 4BC3 LW S8, 12(SP)
+BFD072EE 4862 LW V1, 8(SP)
+BFD072F0 4841 LW V0, 4(SP)
+BFD072F2 477C0000 DI ZERO
+BFD072F6 18000000 SLL ZERO, ZERO, 3
+BFD072F8 4B471800 SB ZERO, 19271(ZERO)
+BFD072FA 4B47 LW K0, 28(SP)
+BFD072FC 4B65 LW K1, 20(SP)
+BFD072FE 02FC034E MTC0 K0, EPC
+BFD07302 4B46 LW K0, 24(SP)
+BFD07304 4C11 ADDIU SP, SP, 32
+BFD07306 12FC034C MTC0 K0, SRSCtl
+BFD07308 03BD12FC ADDI S7, GP, 957
+BFD0730A F17C03BD WRPGPR SP, SP
+BFD0730C 036CF17C JALX 0xBDF00DB0
+BFD0730E 02FC036C MTC0 K1, Status
+BFD07310 000002FC SLL S7, GP, 0
+BFD07312 F37C0000 ERET
+BFD07314 0C00F37C JALX 0xBDF03000
+155: \r
+156: /* 16-bit Basic Timer 1 */\r
+157: void __attribute__((weak, interrupt, nomips16))\r
+158: girq23_b1(void)\r
+159: {\r
+BFD04C70 E17C03BD RDPGPR SP, SP
+BFD04C74 00FC036E MFC0 K1, EPC
+BFD04C76 034C00FC INS A3, GP, 13, -12
+BFD04C78 10FC034C MFC0 K0, SRSCtl
+BFD04C7A 4FC510FC ADDI A3, GP, 20421
+BFD04C7C 4FC5 ADDIU SP, SP, -120
+BFD04C7E CB7D SW K1, 116(SP)
+BFD04C80 00FC036C MFC0 K1, Status
+BFD04C84 CB5C SW K0, 112(SP)
+BFD04C86 00FC034D MFC0 K0, Cause
+BFD04C8A CB7B SW K1, 108(SP)
+BFD04C8C 5040035A SRL K0, K0, 10
+BFD04C8E 037A5040 ORI V0, ZERO, 890
+BFD04C90 7A8C037A INS K1, K0, 10, 6
+BFD04C92 03607A8C ADDIUPC A1, 787296
+BFD04C94 204C0360 INS K1, ZERO, 1, 4
+BFD04C96 036C204C LWC2 V0, 876(T4)
+BFD04C98 02FC036C MTC0 K1, Status
+BFD04C9C C867 SW V1, 28(SP)
+BFD04C9E C846 SW V0, 24(SP)
+BFD04CA0 487C LW V1, 112(SP)
+BFD04CA2 2DB7 ANDI V1, V1, 0xF
+BFD04CA4 001140A3 BNEZC V1, 0xBFD04CCA
+BFD04CA8 CBF7 SW RA, 92(SP)
+BFD04CAA CBD6 SW S8, 88(SP)
+BFD04CAC CB35 SW T9, 84(SP)
+BFD04CAE CB14 SW T8, 80(SP)
+BFD04CB0 C9F3 SW T7, 76(SP)
+BFD04CB2 C9D2 SW T6, 72(SP)
+BFD04CB4 C9B1 SW T5, 68(SP)
+BFD04CB6 C990 SW T4, 64(SP)
+BFD04CB8 C96F SW T3, 60(SP)
+BFD04CBA C94E SW T2, 56(SP)
+BFD04CBC C92D SW T1, 52(SP)
+BFD04CBE C90C SW T0, 48(SP)
+BFD04CC0 C8EB SW A3, 44(SP)
+BFD04CC2 C8CA SW A2, 40(SP)
+BFD04CC4 C8A9 SW A1, 36(SP)
+BFD04CC6 C888 SW A0, 32(SP)
+BFD04CC8 C825 SW AT, 20(SP)
+BFD04CCA 4642 MFLO V0
+BFD04CCC C859 SW V0, 100(SP)
+BFD04CCE 4603 MFHI V1
+BFD04CD0 C878 SW V1, 96(SP)
+BFD04CD2 0FDD MOVE S8, SP
+160: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 1, TRUE);\r
+BFD04CD4 EE0F LI A0, 15
+BFD04CD6 EE81 LI A1, 1
+BFD04CD8 EF01 LI A2, 1
+BFD04CDA 3A4077E8 JALS jtvic_dis_clr_source
+BFD04CDC 0C003A40 SH S2, 3072(ZERO)
+BFD04CDE 0C00 NOP
+161: }\r
+BFD04CE0 0FBE MOVE SP, S8
+BFD04CE2 4859 LW V0, 100(SP)
+BFD04CE4 3D7C0002 MTLO V0
+BFD04CE6 48783D7C LH T3, 18552(GP)
+BFD04CE8 4878 LW V1, 96(SP)
+BFD04CEA 2D7C0003 MTHI V1
+BFD04CEC 2D7C ANDI V0, A3, 0x40
+BFD04CEE 485C LW V0, 112(SP)
+BFD04CF0 2D27 ANDI V0, V0, 0xF
+BFD04CF2 001340A2 BNEZC V0, 0xBFD04D1C
+BFD04CF6 4BF7 LW RA, 92(SP)
+BFD04CF8 4BD6 LW S8, 88(SP)
+BFD04CFA 4B35 LW T9, 84(SP)
+BFD04CFC 4B14 LW T8, 80(SP)
+BFD04CFE 49F3 LW T7, 76(SP)
+BFD04D00 49D2 LW T6, 72(SP)
+BFD04D02 49B1 LW T5, 68(SP)
+BFD04D04 4990 LW T4, 64(SP)
+BFD04D06 496F LW T3, 60(SP)
+BFD04D08 494E LW T2, 56(SP)
+BFD04D0A 492D LW T1, 52(SP)
+BFD04D0C 490C LW T0, 48(SP)
+BFD04D0E 48EB LW A3, 44(SP)
+BFD04D10 48CA LW A2, 40(SP)
+BFD04D12 48A9 LW A1, 36(SP)
+BFD04D14 4888 LW A0, 32(SP)
+BFD04D16 4867 LW V1, 28(SP)
+BFD04D18 4846 LW V0, 24(SP)
+BFD04D1A 4825 LW AT, 20(SP)
+BFD04D1C 477C0000 DI ZERO
+BFD04D20 18000000 SLL ZERO, ZERO, 3
+BFD04D22 4B5D1800 SB ZERO, 19293(ZERO)
+BFD04D24 4B5D LW K0, 116(SP)
+BFD04D26 4B7B LW K1, 108(SP)
+BFD04D28 02FC034E MTC0 K0, EPC
+BFD04D2C 4B5C LW K0, 112(SP)
+BFD04D2E 4C3D ADDIU SP, SP, 120
+BFD04D30 12FC034C MTC0 K0, SRSCtl
+BFD04D32 03BD12FC ADDI S7, GP, 957
+BFD04D34 F17C03BD WRPGPR SP, SP
+BFD04D36 036CF17C JALX 0xBDF00DB0
+BFD04D38 02FC036C MTC0 K1, Status
+BFD04D3A 000002FC SLL S7, GP, 0
+BFD04D3C F37C0000 ERET
+BFD04D3E 03BDF37C JALX 0xBDF00EF4
+162: \r
+163: /* 16-bit Basic Timer 2 */\r
+164: void __attribute__((weak, interrupt, nomips16))\r
+165: girq23_b2(void)\r
+166: {\r
+BFD04D40 E17C03BD RDPGPR SP, SP
+BFD04D44 00FC036E MFC0 K1, EPC
+BFD04D46 034C00FC INS A3, GP, 13, -12
+BFD04D48 10FC034C MFC0 K0, SRSCtl
+BFD04D4A 4FC510FC ADDI A3, GP, 20421
+BFD04D4C 4FC5 ADDIU SP, SP, -120
+BFD04D4E CB7D SW K1, 116(SP)
+BFD04D50 00FC036C MFC0 K1, Status
+BFD04D54 CB5C SW K0, 112(SP)
+BFD04D56 00FC034D MFC0 K0, Cause
+BFD04D5A CB7B SW K1, 108(SP)
+BFD04D5C 5040035A SRL K0, K0, 10
+BFD04D5E 037A5040 ORI V0, ZERO, 890
+BFD04D60 7A8C037A INS K1, K0, 10, 6
+BFD04D62 03607A8C ADDIUPC A1, 787296
+BFD04D64 204C0360 INS K1, ZERO, 1, 4
+BFD04D66 036C204C LWC2 V0, 876(T4)
+BFD04D68 02FC036C MTC0 K1, Status
+BFD04D6C C867 SW V1, 28(SP)
+BFD04D6E C846 SW V0, 24(SP)
+BFD04D70 487C LW V1, 112(SP)
+BFD04D72 2DB7 ANDI V1, V1, 0xF
+BFD04D74 001140A3 BNEZC V1, 0xBFD04D9A
+BFD04D78 CBF7 SW RA, 92(SP)
+BFD04D7A CBD6 SW S8, 88(SP)
+BFD04D7C CB35 SW T9, 84(SP)
+BFD04D7E CB14 SW T8, 80(SP)
+BFD04D80 C9F3 SW T7, 76(SP)
+BFD04D82 C9D2 SW T6, 72(SP)
+BFD04D84 C9B1 SW T5, 68(SP)
+BFD04D86 C990 SW T4, 64(SP)
+BFD04D88 C96F SW T3, 60(SP)
+BFD04D8A C94E SW T2, 56(SP)
+BFD04D8C C92D SW T1, 52(SP)
+BFD04D8E C90C SW T0, 48(SP)
+BFD04D90 C8EB SW A3, 44(SP)
+BFD04D92 C8CA SW A2, 40(SP)
+BFD04D94 C8A9 SW A1, 36(SP)
+BFD04D96 C888 SW A0, 32(SP)
+BFD04D98 C825 SW AT, 20(SP)
+BFD04D9A 4642 MFLO V0
+BFD04D9C C859 SW V0, 100(SP)
+BFD04D9E 4603 MFHI V1
+BFD04DA0 C878 SW V1, 96(SP)
+BFD04DA2 0FDD MOVE S8, SP
+167: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 2, TRUE);\r
+BFD04DA4 EE0F LI A0, 15
+BFD04DA6 EE82 LI A1, 2
+BFD04DA8 EF01 LI A2, 1
+BFD04DAA 3A4077E8 JALS jtvic_dis_clr_source
+BFD04DAC 0C003A40 SH S2, 3072(ZERO)
+BFD04DAE 0C00 NOP
+168: }\r
+BFD04DB0 0FBE MOVE SP, S8
+BFD04DB2 4859 LW V0, 100(SP)
+BFD04DB4 3D7C0002 MTLO V0
+BFD04DB6 48783D7C LH T3, 18552(GP)
+BFD04DB8 4878 LW V1, 96(SP)
+BFD04DBA 2D7C0003 MTHI V1
+BFD04DBC 2D7C ANDI V0, A3, 0x40
+BFD04DBE 485C LW V0, 112(SP)
+BFD04DC0 2D27 ANDI V0, V0, 0xF
+BFD04DC2 001340A2 BNEZC V0, 0xBFD04DEC
+BFD04DC6 4BF7 LW RA, 92(SP)
+BFD04DC8 4BD6 LW S8, 88(SP)
+BFD04DCA 4B35 LW T9, 84(SP)
+BFD04DCC 4B14 LW T8, 80(SP)
+BFD04DCE 49F3 LW T7, 76(SP)
+BFD04DD0 49D2 LW T6, 72(SP)
+BFD04DD2 49B1 LW T5, 68(SP)
+BFD04DD4 4990 LW T4, 64(SP)
+BFD04DD6 496F LW T3, 60(SP)
+BFD04DD8 494E LW T2, 56(SP)
+BFD04DDA 492D LW T1, 52(SP)
+BFD04DDC 490C LW T0, 48(SP)
+BFD04DDE 48EB LW A3, 44(SP)
+BFD04DE0 48CA LW A2, 40(SP)
+BFD04DE2 48A9 LW A1, 36(SP)
+BFD04DE4 4888 LW A0, 32(SP)
+BFD04DE6 4867 LW V1, 28(SP)
+BFD04DE8 4846 LW V0, 24(SP)
+BFD04DEA 4825 LW AT, 20(SP)
+BFD04DEC 477C0000 DI ZERO
+BFD04DF0 18000000 SLL ZERO, ZERO, 3
+BFD04DF2 4B5D1800 SB ZERO, 19293(ZERO)
+BFD04DF4 4B5D LW K0, 116(SP)
+BFD04DF6 4B7B LW K1, 108(SP)
+BFD04DF8 02FC034E MTC0 K0, EPC
+BFD04DFC 4B5C LW K0, 112(SP)
+BFD04DFE 4C3D ADDIU SP, SP, 120
+BFD04E00 12FC034C MTC0 K0, SRSCtl
+BFD04E02 03BD12FC ADDI S7, GP, 957
+BFD04E04 F17C03BD WRPGPR SP, SP
+BFD04E06 036CF17C JALX 0xBDF00DB0
+BFD04E08 02FC036C MTC0 K1, Status
+BFD04E0A 000002FC SLL S7, GP, 0
+BFD04E0C F37C0000 ERET
+BFD04E0E 03BDF37C JALX 0xBDF00EF4
+169: \r
+170: /* 16-bit Basic Timer 3 */\r
+171: void __attribute__((weak, interrupt, nomips16))\r
+172: girq23_b3(void)\r
+173: {\r
+BFD04E10 E17C03BD RDPGPR SP, SP
+BFD04E14 00FC036E MFC0 K1, EPC
+BFD04E16 034C00FC INS A3, GP, 13, -12
+BFD04E18 10FC034C MFC0 K0, SRSCtl
+BFD04E1A 4FC510FC ADDI A3, GP, 20421
+BFD04E1C 4FC5 ADDIU SP, SP, -120
+BFD04E1E CB7D SW K1, 116(SP)
+BFD04E20 00FC036C MFC0 K1, Status
+BFD04E24 CB5C SW K0, 112(SP)
+BFD04E26 00FC034D MFC0 K0, Cause
+BFD04E2A CB7B SW K1, 108(SP)
+BFD04E2C 5040035A SRL K0, K0, 10
+BFD04E2E 037A5040 ORI V0, ZERO, 890
+BFD04E30 7A8C037A INS K1, K0, 10, 6
+BFD04E32 03607A8C ADDIUPC A1, 787296
+BFD04E34 204C0360 INS K1, ZERO, 1, 4
+BFD04E36 036C204C LWC2 V0, 876(T4)
+BFD04E38 02FC036C MTC0 K1, Status
+BFD04E3C C867 SW V1, 28(SP)
+BFD04E3E C846 SW V0, 24(SP)
+BFD04E40 487C LW V1, 112(SP)
+BFD04E42 2DB7 ANDI V1, V1, 0xF
+BFD04E44 001140A3 BNEZC V1, 0xBFD04E6A
+BFD04E48 CBF7 SW RA, 92(SP)
+BFD04E4A CBD6 SW S8, 88(SP)
+BFD04E4C CB35 SW T9, 84(SP)
+BFD04E4E CB14 SW T8, 80(SP)
+BFD04E50 C9F3 SW T7, 76(SP)
+BFD04E52 C9D2 SW T6, 72(SP)
+BFD04E54 C9B1 SW T5, 68(SP)
+BFD04E56 C990 SW T4, 64(SP)
+BFD04E58 C96F SW T3, 60(SP)
+BFD04E5A C94E SW T2, 56(SP)
+BFD04E5C C92D SW T1, 52(SP)
+BFD04E5E C90C SW T0, 48(SP)
+BFD04E60 C8EB SW A3, 44(SP)
+BFD04E62 C8CA SW A2, 40(SP)
+BFD04E64 C8A9 SW A1, 36(SP)
+BFD04E66 C888 SW A0, 32(SP)
+BFD04E68 C825 SW AT, 20(SP)
+BFD04E6A 4642 MFLO V0
+BFD04E6C C859 SW V0, 100(SP)
+BFD04E6E 4603 MFHI V1
+BFD04E70 C878 SW V1, 96(SP)
+BFD04E72 0FDD MOVE S8, SP
+174: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 3, TRUE);\r
+BFD04E74 EE0F LI A0, 15
+BFD04E76 EE83 LI A1, 3
+BFD04E78 EF01 LI A2, 1
+BFD04E7A 3A4077E8 JALS jtvic_dis_clr_source
+BFD04E7C 0C003A40 SH S2, 3072(ZERO)
+BFD04E7E 0C00 NOP
+175: }\r
+BFD04E80 0FBE MOVE SP, S8
+BFD04E82 4859 LW V0, 100(SP)
+BFD04E84 3D7C0002 MTLO V0
+BFD04E86 48783D7C LH T3, 18552(GP)
+BFD04E88 4878 LW V1, 96(SP)
+BFD04E8A 2D7C0003 MTHI V1
+BFD04E8C 2D7C ANDI V0, A3, 0x40
+BFD04E8E 485C LW V0, 112(SP)
+BFD04E90 2D27 ANDI V0, V0, 0xF
+BFD04E92 001340A2 BNEZC V0, 0xBFD04EBC
+BFD04E96 4BF7 LW RA, 92(SP)
+BFD04E98 4BD6 LW S8, 88(SP)
+BFD04E9A 4B35 LW T9, 84(SP)
+BFD04E9C 4B14 LW T8, 80(SP)
+BFD04E9E 49F3 LW T7, 76(SP)
+BFD04EA0 49D2 LW T6, 72(SP)
+BFD04EA2 49B1 LW T5, 68(SP)
+BFD04EA4 4990 LW T4, 64(SP)
+BFD04EA6 496F LW T3, 60(SP)
+BFD04EA8 494E LW T2, 56(SP)
+BFD04EAA 492D LW T1, 52(SP)
+BFD04EAC 490C LW T0, 48(SP)
+BFD04EAE 48EB LW A3, 44(SP)
+BFD04EB0 48CA LW A2, 40(SP)
+BFD04EB2 48A9 LW A1, 36(SP)
+BFD04EB4 4888 LW A0, 32(SP)
+BFD04EB6 4867 LW V1, 28(SP)
+BFD04EB8 4846 LW V0, 24(SP)
+BFD04EBA 4825 LW AT, 20(SP)
+BFD04EBC 477C0000 DI ZERO
+BFD04EC0 18000000 SLL ZERO, ZERO, 3
+BFD04EC2 4B5D1800 SB ZERO, 19293(ZERO)
+BFD04EC4 4B5D LW K0, 116(SP)
+BFD04EC6 4B7B LW K1, 108(SP)
+BFD04EC8 02FC034E MTC0 K0, EPC
+BFD04ECC 4B5C LW K0, 112(SP)
+BFD04ECE 4C3D ADDIU SP, SP, 120
+BFD04ED0 12FC034C MTC0 K0, SRSCtl
+BFD04ED2 03BD12FC ADDI S7, GP, 957
+BFD04ED4 F17C03BD WRPGPR SP, SP
+BFD04ED6 036CF17C JALX 0xBDF00DB0
+BFD04ED8 02FC036C MTC0 K1, Status
+BFD04EDA 000002FC SLL S7, GP, 0
+BFD04EDC F37C0000 ERET
+BFD04EDE 03BDF37C JALX 0xBDF00EF4
+176: \r
+177: /* RTOS Timer */\r
+178: void __attribute__((weak, interrupt, nomips16))\r
+179: girq23_b4(void)\r
+180: {\r
+BFD07318 E17C03BD RDPGPR SP, SP
+BFD0731C 00FC036E MFC0 K1, EPC
+BFD0731E 034C00FC INS A3, GP, 13, -12
+BFD07320 10FC034C MFC0 K0, SRSCtl
+BFD07322 4FF110FC ADDI A3, GP, 20465
+BFD07324 4FF1 ADDIU SP, SP, -32
+BFD07326 CB67 SW K1, 28(SP)
+BFD07328 00FC036C MFC0 K1, Status
+BFD0732C CB46 SW K0, 24(SP)
+BFD0732E 00FC034D MFC0 K0, Cause
+BFD07332 CB65 SW K1, 20(SP)
+BFD07334 5040035A SRL K0, K0, 10
+BFD07336 037A5040 ORI V0, ZERO, 890
+BFD07338 7A8C037A INS K1, K0, 10, 6
+BFD0733A 03607A8C ADDIUPC A1, 787296
+BFD0733C 204C0360 INS K1, ZERO, 1, 4
+BFD0733E 036C204C LWC2 V0, 876(T4)
+BFD07340 02FC036C MTC0 K1, Status
+BFD07344 C862 SW V1, 8(SP)
+BFD07346 C841 SW V0, 4(SP)
+BFD07348 4866 LW V1, 24(SP)
+BFD0734A 2DB7 ANDI V1, V1, 0xF
+BFD0734C CBC3 SW S8, 12(SP)
+BFD0734E 0FDD MOVE S8, SP
+181: JTVIC_GIRQ->REGS[MEC14xx_GIRQ23_ID].SOURCE = (1ul << 4);\r
+BFD07350 BFFF41A2 LUI V0, 0xBFFF
+BFD07352 5042BFFF LDC1 F31, 20546(RA)
+BFD07354 C0005042 ORI V0, V0, -16384
+BFD07358 ED90 LI V1, 16
+BFD0735A 00F0F862 SW V1, 240(V0)
+182: \r
+183: }\r
+BFD0735E 0FBE MOVE SP, S8
+BFD07360 4846 LW V0, 24(SP)
+BFD07362 2D27 ANDI V0, V0, 0xF
+BFD07364 4BC3 LW S8, 12(SP)
+BFD07366 4862 LW V1, 8(SP)
+BFD07368 4841 LW V0, 4(SP)
+BFD0736A 477C0000 DI ZERO
+BFD0736E 18000000 SLL ZERO, ZERO, 3
+BFD07370 4B471800 SB ZERO, 19271(ZERO)
+BFD07372 4B47 LW K0, 28(SP)
+BFD07374 4B65 LW K1, 20(SP)
+BFD07376 02FC034E MTC0 K0, EPC
+BFD0737A 4B46 LW K0, 24(SP)
+BFD0737C 4C11 ADDIU SP, SP, 32
+BFD0737E 12FC034C MTC0 K0, SRSCtl
+BFD07380 03BD12FC ADDI S7, GP, 957
+BFD07382 F17C03BD WRPGPR SP, SP
+BFD07384 036CF17C JALX 0xBDF00DB0
+BFD07386 02FC036C MTC0 K1, Status
+BFD07388 000002FC SLL S7, GP, 0
+BFD0738A F37C0000 ERET
+BFD0738C 0C00F37C JALX 0xBDF03000
+184: \r
+185: /* Hibernation Timer */\r
+186: void __attribute__((weak, interrupt, nomips16))\r
+187: girq23_b5(void)\r
+188: {\r
+BFD04EE0 E17C03BD RDPGPR SP, SP
+BFD04EE4 00FC036E MFC0 K1, EPC
+BFD04EE6 034C00FC INS A3, GP, 13, -12
+BFD04EE8 10FC034C MFC0 K0, SRSCtl
+BFD04EEA 4FC510FC ADDI A3, GP, 20421
+BFD04EEC 4FC5 ADDIU SP, SP, -120
+BFD04EEE CB7D SW K1, 116(SP)
+BFD04EF0 00FC036C MFC0 K1, Status
+BFD04EF4 CB5C SW K0, 112(SP)
+BFD04EF6 00FC034D MFC0 K0, Cause
+BFD04EFA CB7B SW K1, 108(SP)
+BFD04EFC 5040035A SRL K0, K0, 10
+BFD04EFE 037A5040 ORI V0, ZERO, 890
+BFD04F00 7A8C037A INS K1, K0, 10, 6
+BFD04F02 03607A8C ADDIUPC A1, 787296
+BFD04F04 204C0360 INS K1, ZERO, 1, 4
+BFD04F06 036C204C LWC2 V0, 876(T4)
+BFD04F08 02FC036C MTC0 K1, Status
+BFD04F0C C867 SW V1, 28(SP)
+BFD04F0E C846 SW V0, 24(SP)
+BFD04F10 487C LW V1, 112(SP)
+BFD04F12 2DB7 ANDI V1, V1, 0xF
+BFD04F14 001140A3 BNEZC V1, 0xBFD04F3A
+BFD04F18 CBF7 SW RA, 92(SP)
+BFD04F1A CBD6 SW S8, 88(SP)
+BFD04F1C CB35 SW T9, 84(SP)
+BFD04F1E CB14 SW T8, 80(SP)
+BFD04F20 C9F3 SW T7, 76(SP)
+BFD04F22 C9D2 SW T6, 72(SP)
+BFD04F24 C9B1 SW T5, 68(SP)
+BFD04F26 C990 SW T4, 64(SP)
+BFD04F28 C96F SW T3, 60(SP)
+BFD04F2A C94E SW T2, 56(SP)
+BFD04F2C C92D SW T1, 52(SP)
+BFD04F2E C90C SW T0, 48(SP)
+BFD04F30 C8EB SW A3, 44(SP)
+BFD04F32 C8CA SW A2, 40(SP)
+BFD04F34 C8A9 SW A1, 36(SP)
+BFD04F36 C888 SW A0, 32(SP)
+BFD04F38 C825 SW AT, 20(SP)
+BFD04F3A 4642 MFLO V0
+BFD04F3C C859 SW V0, 100(SP)
+BFD04F3E 4603 MFHI V1
+BFD04F40 C878 SW V1, 96(SP)
+BFD04F42 0FDD MOVE S8, SP
+189: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 5, TRUE);\r
+BFD04F44 EE0F LI A0, 15
+BFD04F46 EE85 LI A1, 5
+BFD04F48 EF01 LI A2, 1
+BFD04F4A 3A4077E8 JALS jtvic_dis_clr_source
+BFD04F4C 0C003A40 SH S2, 3072(ZERO)
+BFD04F4E 0C00 NOP
+190: }\r
+BFD04F50 0FBE MOVE SP, S8
+BFD04F52 4859 LW V0, 100(SP)
+BFD04F54 3D7C0002 MTLO V0
+BFD04F56 48783D7C LH T3, 18552(GP)
+BFD04F58 4878 LW V1, 96(SP)
+BFD04F5A 2D7C0003 MTHI V1
+BFD04F5C 2D7C ANDI V0, A3, 0x40
+BFD04F5E 485C LW V0, 112(SP)
+BFD04F60 2D27 ANDI V0, V0, 0xF
+BFD04F62 001340A2 BNEZC V0, 0xBFD04F8C
+BFD04F66 4BF7 LW RA, 92(SP)
+BFD04F68 4BD6 LW S8, 88(SP)
+BFD04F6A 4B35 LW T9, 84(SP)
+BFD04F6C 4B14 LW T8, 80(SP)
+BFD04F6E 49F3 LW T7, 76(SP)
+BFD04F70 49D2 LW T6, 72(SP)
+BFD04F72 49B1 LW T5, 68(SP)
+BFD04F74 4990 LW T4, 64(SP)
+BFD04F76 496F LW T3, 60(SP)
+BFD04F78 494E LW T2, 56(SP)
+BFD04F7A 492D LW T1, 52(SP)
+BFD04F7C 490C LW T0, 48(SP)
+BFD04F7E 48EB LW A3, 44(SP)
+BFD04F80 48CA LW A2, 40(SP)
+BFD04F82 48A9 LW A1, 36(SP)
+BFD04F84 4888 LW A0, 32(SP)
+BFD04F86 4867 LW V1, 28(SP)
+BFD04F88 4846 LW V0, 24(SP)
+BFD04F8A 4825 LW AT, 20(SP)
+BFD04F8C 477C0000 DI ZERO
+BFD04F90 18000000 SLL ZERO, ZERO, 3
+BFD04F92 4B5D1800 SB ZERO, 19293(ZERO)
+BFD04F94 4B5D LW K0, 116(SP)
+BFD04F96 4B7B LW K1, 108(SP)
+BFD04F98 02FC034E MTC0 K0, EPC
+BFD04F9C 4B5C LW K0, 112(SP)
+BFD04F9E 4C3D ADDIU SP, SP, 120
+BFD04FA0 12FC034C MTC0 K0, SRSCtl
+BFD04FA2 03BD12FC ADDI S7, GP, 957
+BFD04FA4 F17C03BD WRPGPR SP, SP
+BFD04FA6 036CF17C JALX 0xBDF00DB0
+BFD04FA8 02FC036C MTC0 K1, Status
+BFD04FAA 000002FC SLL S7, GP, 0
+BFD04FAC F37C0000 ERET
+BFD04FAE 03BDF37C JALX 0xBDF00EF4
+191: \r
+192: /* Week Alarm */\r
+193: void __attribute__((weak, interrupt, nomips16))\r
+194: girq23_b6(void)\r
+195: {\r
+BFD04FB0 E17C03BD RDPGPR SP, SP
+BFD04FB4 00FC036E MFC0 K1, EPC
+BFD04FB6 034C00FC INS A3, GP, 13, -12
+BFD04FB8 10FC034C MFC0 K0, SRSCtl
+BFD04FBA 4FC510FC ADDI A3, GP, 20421
+BFD04FBC 4FC5 ADDIU SP, SP, -120
+BFD04FBE CB7D SW K1, 116(SP)
+BFD04FC0 00FC036C MFC0 K1, Status
+BFD04FC4 CB5C SW K0, 112(SP)
+BFD04FC6 00FC034D MFC0 K0, Cause
+BFD04FCA CB7B SW K1, 108(SP)
+BFD04FCC 5040035A SRL K0, K0, 10
+BFD04FCE 037A5040 ORI V0, ZERO, 890
+BFD04FD0 7A8C037A INS K1, K0, 10, 6
+BFD04FD2 03607A8C ADDIUPC A1, 787296
+BFD04FD4 204C0360 INS K1, ZERO, 1, 4
+BFD04FD6 036C204C LWC2 V0, 876(T4)
+BFD04FD8 02FC036C MTC0 K1, Status
+BFD04FDC C867 SW V1, 28(SP)
+BFD04FDE C846 SW V0, 24(SP)
+BFD04FE0 487C LW V1, 112(SP)
+BFD04FE2 2DB7 ANDI V1, V1, 0xF
+BFD04FE4 001140A3 BNEZC V1, 0xBFD0500A
+BFD04FE8 CBF7 SW RA, 92(SP)
+BFD04FEA CBD6 SW S8, 88(SP)
+BFD04FEC CB35 SW T9, 84(SP)
+BFD04FEE CB14 SW T8, 80(SP)
+BFD04FF0 C9F3 SW T7, 76(SP)
+BFD04FF2 C9D2 SW T6, 72(SP)
+BFD04FF4 C9B1 SW T5, 68(SP)
+BFD04FF6 C990 SW T4, 64(SP)
+BFD04FF8 C96F SW T3, 60(SP)
+BFD04FFA C94E SW T2, 56(SP)
+BFD04FFC C92D SW T1, 52(SP)
+BFD04FFE C90C SW T0, 48(SP)
+BFD05000 C8EB SW A3, 44(SP)
+BFD05002 C8CA SW A2, 40(SP)
+BFD05004 C8A9 SW A1, 36(SP)
+BFD05006 C888 SW A0, 32(SP)
+BFD05008 C825 SW AT, 20(SP)
+BFD0500A 4642 MFLO V0
+BFD0500C C859 SW V0, 100(SP)
+BFD0500E 4603 MFHI V1
+BFD05010 C878 SW V1, 96(SP)
+BFD05012 0FDD MOVE S8, SP
+196: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 6, TRUE);\r
+BFD05014 EE0F LI A0, 15
+BFD05016 EE86 LI A1, 6
+BFD05018 EF01 LI A2, 1
+BFD0501A 3A4077E8 JALS jtvic_dis_clr_source
+BFD0501C 0C003A40 SH S2, 3072(ZERO)
+BFD0501E 0C00 NOP
+197: }\r
+BFD05020 0FBE MOVE SP, S8
+BFD05022 4859 LW V0, 100(SP)
+BFD05024 3D7C0002 MTLO V0
+BFD05026 48783D7C LH T3, 18552(GP)
+BFD05028 4878 LW V1, 96(SP)
+BFD0502A 2D7C0003 MTHI V1
+BFD0502C 2D7C ANDI V0, A3, 0x40
+BFD0502E 485C LW V0, 112(SP)
+BFD05030 2D27 ANDI V0, V0, 0xF
+BFD05032 001340A2 BNEZC V0, 0xBFD0505C
+BFD05036 4BF7 LW RA, 92(SP)
+BFD05038 4BD6 LW S8, 88(SP)
+BFD0503A 4B35 LW T9, 84(SP)
+BFD0503C 4B14 LW T8, 80(SP)
+BFD0503E 49F3 LW T7, 76(SP)
+BFD05040 49D2 LW T6, 72(SP)
+BFD05042 49B1 LW T5, 68(SP)
+BFD05044 4990 LW T4, 64(SP)
+BFD05046 496F LW T3, 60(SP)
+BFD05048 494E LW T2, 56(SP)
+BFD0504A 492D LW T1, 52(SP)
+BFD0504C 490C LW T0, 48(SP)
+BFD0504E 48EB LW A3, 44(SP)
+BFD05050 48CA LW A2, 40(SP)
+BFD05052 48A9 LW A1, 36(SP)
+BFD05054 4888 LW A0, 32(SP)
+BFD05056 4867 LW V1, 28(SP)
+BFD05058 4846 LW V0, 24(SP)
+BFD0505A 4825 LW AT, 20(SP)
+BFD0505C 477C0000 DI ZERO
+BFD05060 18000000 SLL ZERO, ZERO, 3
+BFD05062 4B5D1800 SB ZERO, 19293(ZERO)
+BFD05064 4B5D LW K0, 116(SP)
+BFD05066 4B7B LW K1, 108(SP)
+BFD05068 02FC034E MTC0 K0, EPC
+BFD0506C 4B5C LW K0, 112(SP)
+BFD0506E 4C3D ADDIU SP, SP, 120
+BFD05070 12FC034C MTC0 K0, SRSCtl
+BFD05072 03BD12FC ADDI S7, GP, 957
+BFD05074 F17C03BD WRPGPR SP, SP
+BFD05076 036CF17C JALX 0xBDF00DB0
+BFD05078 02FC036C MTC0 K1, Status
+BFD0507A 000002FC SLL S7, GP, 0
+BFD0507C F37C0000 ERET
+BFD0507E 03BDF37C JALX 0xBDF00EF4
+198: \r
+199: /* Sub-Week Alarm */\r
+200: void __attribute__((weak, interrupt, nomips16))\r
+201: girq23_b7(void)\r
+202: {\r
+BFD05080 E17C03BD RDPGPR SP, SP
+BFD05084 00FC036E MFC0 K1, EPC
+BFD05086 034C00FC INS A3, GP, 13, -12
+BFD05088 10FC034C MFC0 K0, SRSCtl
+BFD0508A 4FC510FC ADDI A3, GP, 20421
+BFD0508C 4FC5 ADDIU SP, SP, -120
+BFD0508E CB7D SW K1, 116(SP)
+BFD05090 00FC036C MFC0 K1, Status
+BFD05094 CB5C SW K0, 112(SP)
+BFD05096 00FC034D MFC0 K0, Cause
+BFD0509A CB7B SW K1, 108(SP)
+BFD0509C 5040035A SRL K0, K0, 10
+BFD0509E 037A5040 ORI V0, ZERO, 890
+BFD050A0 7A8C037A INS K1, K0, 10, 6
+BFD050A2 03607A8C ADDIUPC A1, 787296
+BFD050A4 204C0360 INS K1, ZERO, 1, 4
+BFD050A6 036C204C LWC2 V0, 876(T4)
+BFD050A8 02FC036C MTC0 K1, Status
+BFD050AC C867 SW V1, 28(SP)
+BFD050AE C846 SW V0, 24(SP)
+BFD050B0 487C LW V1, 112(SP)
+BFD050B2 2DB7 ANDI V1, V1, 0xF
+BFD050B4 001140A3 BNEZC V1, 0xBFD050DA
+BFD050B8 CBF7 SW RA, 92(SP)
+BFD050BA CBD6 SW S8, 88(SP)
+BFD050BC CB35 SW T9, 84(SP)
+BFD050BE CB14 SW T8, 80(SP)
+BFD050C0 C9F3 SW T7, 76(SP)
+BFD050C2 C9D2 SW T6, 72(SP)
+BFD050C4 C9B1 SW T5, 68(SP)
+BFD050C6 C990 SW T4, 64(SP)
+BFD050C8 C96F SW T3, 60(SP)
+BFD050CA C94E SW T2, 56(SP)
+BFD050CC C92D SW T1, 52(SP)
+BFD050CE C90C SW T0, 48(SP)
+BFD050D0 C8EB SW A3, 44(SP)
+BFD050D2 C8CA SW A2, 40(SP)
+BFD050D4 C8A9 SW A1, 36(SP)
+BFD050D6 C888 SW A0, 32(SP)
+BFD050D8 C825 SW AT, 20(SP)
+BFD050DA 4642 MFLO V0
+BFD050DC C859 SW V0, 100(SP)
+BFD050DE 4603 MFHI V1
+BFD050E0 C878 SW V1, 96(SP)
+BFD050E2 0FDD MOVE S8, SP
+203: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 7, TRUE);\r
+BFD050E4 EE0F LI A0, 15
+BFD050E6 EE87 LI A1, 7
+BFD050E8 EF01 LI A2, 1
+BFD050EA 3A4077E8 JALS jtvic_dis_clr_source
+BFD050EC 0C003A40 SH S2, 3072(ZERO)
+BFD050EE 0C00 NOP
+204: }\r
+BFD050F0 0FBE MOVE SP, S8
+BFD050F2 4859 LW V0, 100(SP)
+BFD050F4 3D7C0002 MTLO V0
+BFD050F6 48783D7C LH T3, 18552(GP)
+BFD050F8 4878 LW V1, 96(SP)
+BFD050FA 2D7C0003 MTHI V1
+BFD050FC 2D7C ANDI V0, A3, 0x40
+BFD050FE 485C LW V0, 112(SP)
+BFD05100 2D27 ANDI V0, V0, 0xF
+BFD05102 001340A2 BNEZC V0, 0xBFD0512C
+BFD05106 4BF7 LW RA, 92(SP)
+BFD05108 4BD6 LW S8, 88(SP)
+BFD0510A 4B35 LW T9, 84(SP)
+BFD0510C 4B14 LW T8, 80(SP)
+BFD0510E 49F3 LW T7, 76(SP)
+BFD05110 49D2 LW T6, 72(SP)
+BFD05112 49B1 LW T5, 68(SP)
+BFD05114 4990 LW T4, 64(SP)
+BFD05116 496F LW T3, 60(SP)
+BFD05118 494E LW T2, 56(SP)
+BFD0511A 492D LW T1, 52(SP)
+BFD0511C 490C LW T0, 48(SP)
+BFD0511E 48EB LW A3, 44(SP)
+BFD05120 48CA LW A2, 40(SP)
+BFD05122 48A9 LW A1, 36(SP)
+BFD05124 4888 LW A0, 32(SP)
+BFD05126 4867 LW V1, 28(SP)
+BFD05128 4846 LW V0, 24(SP)
+BFD0512A 4825 LW AT, 20(SP)
+BFD0512C 477C0000 DI ZERO
+BFD05130 18000000 SLL ZERO, ZERO, 3
+BFD05132 4B5D1800 SB ZERO, 19293(ZERO)
+BFD05134 4B5D LW K0, 116(SP)
+BFD05136 4B7B LW K1, 108(SP)
+BFD05138 02FC034E MTC0 K0, EPC
+BFD0513C 4B5C LW K0, 112(SP)
+BFD0513E 4C3D ADDIU SP, SP, 120
+BFD05140 12FC034C MTC0 K0, SRSCtl
+BFD05142 03BD12FC ADDI S7, GP, 957
+BFD05144 F17C03BD WRPGPR SP, SP
+BFD05146 036CF17C JALX 0xBDF00DB0
+BFD05148 02FC036C MTC0 K1, Status
+BFD0514A 000002FC SLL S7, GP, 0
+BFD0514C F37C0000 ERET
+BFD0514E 03BDF37C JALX 0xBDF00EF4
+205: \r
+206: /* Week Alarm One Second */\r
+207: void __attribute__((weak, interrupt, nomips16))\r
+208: girq23_b8(void)\r
+209: {\r
+BFD05150 E17C03BD RDPGPR SP, SP
+BFD05154 00FC036E MFC0 K1, EPC
+BFD05156 034C00FC INS A3, GP, 13, -12
+BFD05158 10FC034C MFC0 K0, SRSCtl
+BFD0515A 4FC510FC ADDI A3, GP, 20421
+BFD0515C 4FC5 ADDIU SP, SP, -120
+BFD0515E CB7D SW K1, 116(SP)
+BFD05160 00FC036C MFC0 K1, Status
+BFD05164 CB5C SW K0, 112(SP)
+BFD05166 00FC034D MFC0 K0, Cause
+BFD0516A CB7B SW K1, 108(SP)
+BFD0516C 5040035A SRL K0, K0, 10
+BFD0516E 037A5040 ORI V0, ZERO, 890
+BFD05170 7A8C037A INS K1, K0, 10, 6
+BFD05172 03607A8C ADDIUPC A1, 787296
+BFD05174 204C0360 INS K1, ZERO, 1, 4
+BFD05176 036C204C LWC2 V0, 876(T4)
+BFD05178 02FC036C MTC0 K1, Status
+BFD0517C C867 SW V1, 28(SP)
+BFD0517E C846 SW V0, 24(SP)
+BFD05180 487C LW V1, 112(SP)
+BFD05182 2DB7 ANDI V1, V1, 0xF
+BFD05184 001140A3 BNEZC V1, 0xBFD051AA
+BFD05188 CBF7 SW RA, 92(SP)
+BFD0518A CBD6 SW S8, 88(SP)
+BFD0518C CB35 SW T9, 84(SP)
+BFD0518E CB14 SW T8, 80(SP)
+BFD05190 C9F3 SW T7, 76(SP)
+BFD05192 C9D2 SW T6, 72(SP)
+BFD05194 C9B1 SW T5, 68(SP)
+BFD05196 C990 SW T4, 64(SP)
+BFD05198 C96F SW T3, 60(SP)
+BFD0519A C94E SW T2, 56(SP)
+BFD0519C C92D SW T1, 52(SP)
+BFD0519E C90C SW T0, 48(SP)
+BFD051A0 C8EB SW A3, 44(SP)
+BFD051A2 C8CA SW A2, 40(SP)
+BFD051A4 C8A9 SW A1, 36(SP)
+BFD051A6 C888 SW A0, 32(SP)
+BFD051A8 C825 SW AT, 20(SP)
+BFD051AA 4642 MFLO V0
+BFD051AC C859 SW V0, 100(SP)
+BFD051AE 4603 MFHI V1
+BFD051B0 C878 SW V1, 96(SP)
+BFD051B2 0FDD MOVE S8, SP
+210: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 8, TRUE);\r
+BFD051B4 EE0F LI A0, 15
+BFD051B6 EE88 LI A1, 8
+BFD051B8 EF01 LI A2, 1
+BFD051BA 3A4077E8 JALS jtvic_dis_clr_source
+BFD051BC 0C003A40 SH S2, 3072(ZERO)
+BFD051BE 0C00 NOP
+211: }\r
+BFD051C0 0FBE MOVE SP, S8
+BFD051C2 4859 LW V0, 100(SP)
+BFD051C4 3D7C0002 MTLO V0
+BFD051C6 48783D7C LH T3, 18552(GP)
+BFD051C8 4878 LW V1, 96(SP)
+BFD051CA 2D7C0003 MTHI V1
+BFD051CC 2D7C ANDI V0, A3, 0x40
+BFD051CE 485C LW V0, 112(SP)
+BFD051D0 2D27 ANDI V0, V0, 0xF
+BFD051D2 001340A2 BNEZC V0, 0xBFD051FC
+BFD051D6 4BF7 LW RA, 92(SP)
+BFD051D8 4BD6 LW S8, 88(SP)
+BFD051DA 4B35 LW T9, 84(SP)
+BFD051DC 4B14 LW T8, 80(SP)
+BFD051DE 49F3 LW T7, 76(SP)
+BFD051E0 49D2 LW T6, 72(SP)
+BFD051E2 49B1 LW T5, 68(SP)
+BFD051E4 4990 LW T4, 64(SP)
+BFD051E6 496F LW T3, 60(SP)
+BFD051E8 494E LW T2, 56(SP)
+BFD051EA 492D LW T1, 52(SP)
+BFD051EC 490C LW T0, 48(SP)
+BFD051EE 48EB LW A3, 44(SP)
+BFD051F0 48CA LW A2, 40(SP)
+BFD051F2 48A9 LW A1, 36(SP)
+BFD051F4 4888 LW A0, 32(SP)
+BFD051F6 4867 LW V1, 28(SP)
+BFD051F8 4846 LW V0, 24(SP)
+BFD051FA 4825 LW AT, 20(SP)
+BFD051FC 477C0000 DI ZERO
+BFD05200 18000000 SLL ZERO, ZERO, 3
+BFD05202 4B5D1800 SB ZERO, 19293(ZERO)
+BFD05204 4B5D LW K0, 116(SP)
+BFD05206 4B7B LW K1, 108(SP)
+BFD05208 02FC034E MTC0 K0, EPC
+BFD0520C 4B5C LW K0, 112(SP)
+BFD0520E 4C3D ADDIU SP, SP, 120
+BFD05210 12FC034C MTC0 K0, SRSCtl
+BFD05212 03BD12FC ADDI S7, GP, 957
+BFD05214 F17C03BD WRPGPR SP, SP
+BFD05216 036CF17C JALX 0xBDF00DB0
+BFD05218 02FC036C MTC0 K1, Status
+BFD0521A 000002FC SLL S7, GP, 0
+BFD0521C F37C0000 ERET
+BFD0521E 03BDF37C JALX 0xBDF00EF4
+212: \r
+213: /* Week Alarm Sub Second */\r
+214: void __attribute__((weak, interrupt, nomips16))\r
+215: girq23_b9(void)\r
+216: {\r
+BFD05220 E17C03BD RDPGPR SP, SP
+BFD05224 00FC036E MFC0 K1, EPC
+BFD05226 034C00FC INS A3, GP, 13, -12
+BFD05228 10FC034C MFC0 K0, SRSCtl
+BFD0522A 4FC510FC ADDI A3, GP, 20421
+BFD0522C 4FC5 ADDIU SP, SP, -120
+BFD0522E CB7D SW K1, 116(SP)
+BFD05230 00FC036C MFC0 K1, Status
+BFD05234 CB5C SW K0, 112(SP)
+BFD05236 00FC034D MFC0 K0, Cause
+BFD0523A CB7B SW K1, 108(SP)
+BFD0523C 5040035A SRL K0, K0, 10
+BFD0523E 037A5040 ORI V0, ZERO, 890
+BFD05240 7A8C037A INS K1, K0, 10, 6
+BFD05242 03607A8C ADDIUPC A1, 787296
+BFD05244 204C0360 INS K1, ZERO, 1, 4
+BFD05246 036C204C LWC2 V0, 876(T4)
+BFD05248 02FC036C MTC0 K1, Status
+BFD0524C C867 SW V1, 28(SP)
+BFD0524E C846 SW V0, 24(SP)
+BFD05250 487C LW V1, 112(SP)
+BFD05252 2DB7 ANDI V1, V1, 0xF
+BFD05254 001140A3 BNEZC V1, 0xBFD0527A
+BFD05258 CBF7 SW RA, 92(SP)
+BFD0525A CBD6 SW S8, 88(SP)
+BFD0525C CB35 SW T9, 84(SP)
+BFD0525E CB14 SW T8, 80(SP)
+BFD05260 C9F3 SW T7, 76(SP)
+BFD05262 C9D2 SW T6, 72(SP)
+BFD05264 C9B1 SW T5, 68(SP)
+BFD05266 C990 SW T4, 64(SP)
+BFD05268 C96F SW T3, 60(SP)
+BFD0526A C94E SW T2, 56(SP)
+BFD0526C C92D SW T1, 52(SP)
+BFD0526E C90C SW T0, 48(SP)
+BFD05270 C8EB SW A3, 44(SP)
+BFD05272 C8CA SW A2, 40(SP)
+BFD05274 C8A9 SW A1, 36(SP)
+BFD05276 C888 SW A0, 32(SP)
+BFD05278 C825 SW AT, 20(SP)
+BFD0527A 4642 MFLO V0
+BFD0527C C859 SW V0, 100(SP)
+BFD0527E 4603 MFHI V1
+BFD05280 C878 SW V1, 96(SP)
+BFD05282 0FDD MOVE S8, SP
+217: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 9, TRUE);\r
+BFD05284 EE0F LI A0, 15
+BFD05286 EE89 LI A1, 9
+BFD05288 EF01 LI A2, 1
+BFD0528A 3A4077E8 JALS jtvic_dis_clr_source
+BFD0528C 0C003A40 SH S2, 3072(ZERO)
+BFD0528E 0C00 NOP
+218: }\r
+BFD05290 0FBE MOVE SP, S8
+BFD05292 4859 LW V0, 100(SP)
+BFD05294 3D7C0002 MTLO V0
+BFD05296 48783D7C LH T3, 18552(GP)
+BFD05298 4878 LW V1, 96(SP)
+BFD0529A 2D7C0003 MTHI V1
+BFD0529C 2D7C ANDI V0, A3, 0x40
+BFD0529E 485C LW V0, 112(SP)
+BFD052A0 2D27 ANDI V0, V0, 0xF
+BFD052A2 001340A2 BNEZC V0, 0xBFD052CC
+BFD052A6 4BF7 LW RA, 92(SP)
+BFD052A8 4BD6 LW S8, 88(SP)
+BFD052AA 4B35 LW T9, 84(SP)
+BFD052AC 4B14 LW T8, 80(SP)
+BFD052AE 49F3 LW T7, 76(SP)
+BFD052B0 49D2 LW T6, 72(SP)
+BFD052B2 49B1 LW T5, 68(SP)
+BFD052B4 4990 LW T4, 64(SP)
+BFD052B6 496F LW T3, 60(SP)
+BFD052B8 494E LW T2, 56(SP)
+BFD052BA 492D LW T1, 52(SP)
+BFD052BC 490C LW T0, 48(SP)
+BFD052BE 48EB LW A3, 44(SP)
+BFD052C0 48CA LW A2, 40(SP)
+BFD052C2 48A9 LW A1, 36(SP)
+BFD052C4 4888 LW A0, 32(SP)
+BFD052C6 4867 LW V1, 28(SP)
+BFD052C8 4846 LW V0, 24(SP)
+BFD052CA 4825 LW AT, 20(SP)
+BFD052CC 477C0000 DI ZERO
+BFD052D0 18000000 SLL ZERO, ZERO, 3
+BFD052D2 4B5D1800 SB ZERO, 19293(ZERO)
+BFD052D4 4B5D LW K0, 116(SP)
+BFD052D6 4B7B LW K1, 108(SP)
+BFD052D8 02FC034E MTC0 K0, EPC
+BFD052DC 4B5C LW K0, 112(SP)
+BFD052DE 4C3D ADDIU SP, SP, 120
+BFD052E0 12FC034C MTC0 K0, SRSCtl
+BFD052E2 03BD12FC ADDI S7, GP, 957
+BFD052E4 F17C03BD WRPGPR SP, SP
+BFD052E6 036CF17C JALX 0xBDF00DB0
+BFD052E8 02FC036C MTC0 K1, Status
+BFD052EA 000002FC SLL S7, GP, 0
+BFD052EC F37C0000 ERET
+BFD052EE 03BDF37C JALX 0xBDF00EF4
+219: \r
+220: /* Week Alarm System Power Present Pin */\r
+221: void __attribute__((weak, interrupt, nomips16))\r
+222: girq23_b10(void)\r
+223: {\r
+BFD052F0 E17C03BD RDPGPR SP, SP
+BFD052F4 00FC036E MFC0 K1, EPC
+BFD052F6 034C00FC INS A3, GP, 13, -12
+BFD052F8 10FC034C MFC0 K0, SRSCtl
+BFD052FA 4FC510FC ADDI A3, GP, 20421
+BFD052FC 4FC5 ADDIU SP, SP, -120
+BFD052FE CB7D SW K1, 116(SP)
+BFD05300 00FC036C MFC0 K1, Status
+BFD05304 CB5C SW K0, 112(SP)
+BFD05306 00FC034D MFC0 K0, Cause
+BFD0530A CB7B SW K1, 108(SP)
+BFD0530C 5040035A SRL K0, K0, 10
+BFD0530E 037A5040 ORI V0, ZERO, 890
+BFD05310 7A8C037A INS K1, K0, 10, 6
+BFD05312 03607A8C ADDIUPC A1, 787296
+BFD05314 204C0360 INS K1, ZERO, 1, 4
+BFD05316 036C204C LWC2 V0, 876(T4)
+BFD05318 02FC036C MTC0 K1, Status
+BFD0531C C867 SW V1, 28(SP)
+BFD0531E C846 SW V0, 24(SP)
+BFD05320 487C LW V1, 112(SP)
+BFD05322 2DB7 ANDI V1, V1, 0xF
+BFD05324 001140A3 BNEZC V1, 0xBFD0534A
+BFD05328 CBF7 SW RA, 92(SP)
+BFD0532A CBD6 SW S8, 88(SP)
+BFD0532C CB35 SW T9, 84(SP)
+BFD0532E CB14 SW T8, 80(SP)
+BFD05330 C9F3 SW T7, 76(SP)
+BFD05332 C9D2 SW T6, 72(SP)
+BFD05334 C9B1 SW T5, 68(SP)
+BFD05336 C990 SW T4, 64(SP)
+BFD05338 C96F SW T3, 60(SP)
+BFD0533A C94E SW T2, 56(SP)
+BFD0533C C92D SW T1, 52(SP)
+BFD0533E C90C SW T0, 48(SP)
+BFD05340 C8EB SW A3, 44(SP)
+BFD05342 C8CA SW A2, 40(SP)
+BFD05344 C8A9 SW A1, 36(SP)
+BFD05346 C888 SW A0, 32(SP)
+BFD05348 C825 SW AT, 20(SP)
+BFD0534A 4642 MFLO V0
+BFD0534C C859 SW V0, 100(SP)
+BFD0534E 4603 MFHI V1
+BFD05350 C878 SW V1, 96(SP)
+BFD05352 0FDD MOVE S8, SP
+224: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 10, TRUE);\r
+BFD05354 EE0F LI A0, 15
+BFD05356 EE8A LI A1, 10
+BFD05358 EF01 LI A2, 1
+BFD0535A 3A4077E8 JALS jtvic_dis_clr_source
+BFD0535C 0C003A40 SH S2, 3072(ZERO)
+BFD0535E 0C00 NOP
+225: }\r
+BFD05360 0FBE MOVE SP, S8
+BFD05362 4859 LW V0, 100(SP)
+BFD05364 3D7C0002 MTLO V0
+BFD05366 48783D7C LH T3, 18552(GP)
+BFD05368 4878 LW V1, 96(SP)
+BFD0536A 2D7C0003 MTHI V1
+BFD0536C 2D7C ANDI V0, A3, 0x40
+BFD0536E 485C LW V0, 112(SP)
+BFD05370 2D27 ANDI V0, V0, 0xF
+BFD05372 001340A2 BNEZC V0, 0xBFD0539C
+BFD05376 4BF7 LW RA, 92(SP)
+BFD05378 4BD6 LW S8, 88(SP)
+BFD0537A 4B35 LW T9, 84(SP)
+BFD0537C 4B14 LW T8, 80(SP)
+BFD0537E 49F3 LW T7, 76(SP)
+BFD05380 49D2 LW T6, 72(SP)
+BFD05382 49B1 LW T5, 68(SP)
+BFD05384 4990 LW T4, 64(SP)
+BFD05386 496F LW T3, 60(SP)
+BFD05388 494E LW T2, 56(SP)
+BFD0538A 492D LW T1, 52(SP)
+BFD0538C 490C LW T0, 48(SP)
+BFD0538E 48EB LW A3, 44(SP)
+BFD05390 48CA LW A2, 40(SP)
+BFD05392 48A9 LW A1, 36(SP)
+BFD05394 4888 LW A0, 32(SP)
+BFD05396 4867 LW V1, 28(SP)
+BFD05398 4846 LW V0, 24(SP)
+BFD0539A 4825 LW AT, 20(SP)
+BFD0539C 477C0000 DI ZERO
+BFD053A0 18000000 SLL ZERO, ZERO, 3
+BFD053A2 4B5D1800 SB ZERO, 19293(ZERO)
+BFD053A4 4B5D LW K0, 116(SP)
+BFD053A6 4B7B LW K1, 108(SP)
+BFD053A8 02FC034E MTC0 K0, EPC
+BFD053AC 4B5C LW K0, 112(SP)
+BFD053AE 4C3D ADDIU SP, SP, 120
+BFD053B0 12FC034C MTC0 K0, SRSCtl
+BFD053B2 03BD12FC ADDI S7, GP, 957
+BFD053B4 F17C03BD WRPGPR SP, SP
+BFD053B6 036CF17C JALX 0xBDF00DB0
+BFD053B8 02FC036C MTC0 K1, Status
+BFD053BA 000002FC SLL S7, GP, 0
+BFD053BC F37C0000 ERET
+BFD053BE 03BDF37C JALX 0xBDF00EF4
+226: \r
+227: /* VCI OVRD Input */\r
+228: void __attribute__((weak, interrupt, nomips16))\r
+229: girq23_b11(void)\r
+230: {\r
+BFD053C0 E17C03BD RDPGPR SP, SP
+BFD053C4 00FC036E MFC0 K1, EPC
+BFD053C6 034C00FC INS A3, GP, 13, -12
+BFD053C8 10FC034C MFC0 K0, SRSCtl
+BFD053CA 4FC510FC ADDI A3, GP, 20421
+BFD053CC 4FC5 ADDIU SP, SP, -120
+BFD053CE CB7D SW K1, 116(SP)
+BFD053D0 00FC036C MFC0 K1, Status
+BFD053D4 CB5C SW K0, 112(SP)
+BFD053D6 00FC034D MFC0 K0, Cause
+BFD053DA CB7B SW K1, 108(SP)
+BFD053DC 5040035A SRL K0, K0, 10
+BFD053DE 037A5040 ORI V0, ZERO, 890
+BFD053E0 7A8C037A INS K1, K0, 10, 6
+BFD053E2 03607A8C ADDIUPC A1, 787296
+BFD053E4 204C0360 INS K1, ZERO, 1, 4
+BFD053E6 036C204C LWC2 V0, 876(T4)
+BFD053E8 02FC036C MTC0 K1, Status
+BFD053EC C867 SW V1, 28(SP)
+BFD053EE C846 SW V0, 24(SP)
+BFD053F0 487C LW V1, 112(SP)
+BFD053F2 2DB7 ANDI V1, V1, 0xF
+BFD053F4 001140A3 BNEZC V1, 0xBFD0541A
+BFD053F8 CBF7 SW RA, 92(SP)
+BFD053FA CBD6 SW S8, 88(SP)
+BFD053FC CB35 SW T9, 84(SP)
+BFD053FE CB14 SW T8, 80(SP)
+BFD05400 C9F3 SW T7, 76(SP)
+BFD05402 C9D2 SW T6, 72(SP)
+BFD05404 C9B1 SW T5, 68(SP)
+BFD05406 C990 SW T4, 64(SP)
+BFD05408 C96F SW T3, 60(SP)
+BFD0540A C94E SW T2, 56(SP)
+BFD0540C C92D SW T1, 52(SP)
+BFD0540E C90C SW T0, 48(SP)
+BFD05410 C8EB SW A3, 44(SP)
+BFD05412 C8CA SW A2, 40(SP)
+BFD05414 C8A9 SW A1, 36(SP)
+BFD05416 C888 SW A0, 32(SP)
+BFD05418 C825 SW AT, 20(SP)
+BFD0541A 4642 MFLO V0
+BFD0541C C859 SW V0, 100(SP)
+BFD0541E 4603 MFHI V1
+BFD05420 C878 SW V1, 96(SP)
+BFD05422 0FDD MOVE S8, SP
+231: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 11, TRUE);\r
+BFD05424 EE0F LI A0, 15
+BFD05426 EE8B LI A1, 11
+BFD05428 EF01 LI A2, 1
+BFD0542A 3A4077E8 JALS jtvic_dis_clr_source
+BFD0542C 0C003A40 SH S2, 3072(ZERO)
+BFD0542E 0C00 NOP
+232: }\r
+BFD05430 0FBE MOVE SP, S8
+BFD05432 4859 LW V0, 100(SP)
+BFD05434 3D7C0002 MTLO V0
+BFD05436 48783D7C LH T3, 18552(GP)
+BFD05438 4878 LW V1, 96(SP)
+BFD0543A 2D7C0003 MTHI V1
+BFD0543C 2D7C ANDI V0, A3, 0x40
+BFD0543E 485C LW V0, 112(SP)
+BFD05440 2D27 ANDI V0, V0, 0xF
+BFD05442 001340A2 BNEZC V0, 0xBFD0546C
+BFD05446 4BF7 LW RA, 92(SP)
+BFD05448 4BD6 LW S8, 88(SP)
+BFD0544A 4B35 LW T9, 84(SP)
+BFD0544C 4B14 LW T8, 80(SP)
+BFD0544E 49F3 LW T7, 76(SP)
+BFD05450 49D2 LW T6, 72(SP)
+BFD05452 49B1 LW T5, 68(SP)
+BFD05454 4990 LW T4, 64(SP)
+BFD05456 496F LW T3, 60(SP)
+BFD05458 494E LW T2, 56(SP)
+BFD0545A 492D LW T1, 52(SP)
+BFD0545C 490C LW T0, 48(SP)
+BFD0545E 48EB LW A3, 44(SP)
+BFD05460 48CA LW A2, 40(SP)
+BFD05462 48A9 LW A1, 36(SP)
+BFD05464 4888 LW A0, 32(SP)
+BFD05466 4867 LW V1, 28(SP)
+BFD05468 4846 LW V0, 24(SP)
+BFD0546A 4825 LW AT, 20(SP)
+BFD0546C 477C0000 DI ZERO
+BFD05470 18000000 SLL ZERO, ZERO, 3
+BFD05472 4B5D1800 SB ZERO, 19293(ZERO)
+BFD05474 4B5D LW K0, 116(SP)
+BFD05476 4B7B LW K1, 108(SP)
+BFD05478 02FC034E MTC0 K0, EPC
+BFD0547C 4B5C LW K0, 112(SP)
+BFD0547E 4C3D ADDIU SP, SP, 120
+BFD05480 12FC034C MTC0 K0, SRSCtl
+BFD05482 03BD12FC ADDI S7, GP, 957
+BFD05484 F17C03BD WRPGPR SP, SP
+BFD05486 036CF17C JALX 0xBDF00DB0
+BFD05488 02FC036C MTC0 K1, Status
+BFD0548A 000002FC SLL S7, GP, 0
+BFD0548C F37C0000 ERET
+BFD0548E 03BDF37C JALX 0xBDF00EF4
+233: \r
+234: /* VCI IN0 */\r
+235: void __attribute__((weak, interrupt, nomips16))\r
+236: girq23_b12(void)\r
+237: {\r
+BFD05490 E17C03BD RDPGPR SP, SP
+BFD05494 00FC036E MFC0 K1, EPC
+BFD05496 034C00FC INS A3, GP, 13, -12
+BFD05498 10FC034C MFC0 K0, SRSCtl
+BFD0549A 4FC510FC ADDI A3, GP, 20421
+BFD0549C 4FC5 ADDIU SP, SP, -120
+BFD0549E CB7D SW K1, 116(SP)
+BFD054A0 00FC036C MFC0 K1, Status
+BFD054A4 CB5C SW K0, 112(SP)
+BFD054A6 00FC034D MFC0 K0, Cause
+BFD054AA CB7B SW K1, 108(SP)
+BFD054AC 5040035A SRL K0, K0, 10
+BFD054AE 037A5040 ORI V0, ZERO, 890
+BFD054B0 7A8C037A INS K1, K0, 10, 6
+BFD054B2 03607A8C ADDIUPC A1, 787296
+BFD054B4 204C0360 INS K1, ZERO, 1, 4
+BFD054B6 036C204C LWC2 V0, 876(T4)
+BFD054B8 02FC036C MTC0 K1, Status
+BFD054BC C867 SW V1, 28(SP)
+BFD054BE C846 SW V0, 24(SP)
+BFD054C0 487C LW V1, 112(SP)
+BFD054C2 2DB7 ANDI V1, V1, 0xF
+BFD054C4 001140A3 BNEZC V1, 0xBFD054EA
+BFD054C8 CBF7 SW RA, 92(SP)
+BFD054CA CBD6 SW S8, 88(SP)
+BFD054CC CB35 SW T9, 84(SP)
+BFD054CE CB14 SW T8, 80(SP)
+BFD054D0 C9F3 SW T7, 76(SP)
+BFD054D2 C9D2 SW T6, 72(SP)
+BFD054D4 C9B1 SW T5, 68(SP)
+BFD054D6 C990 SW T4, 64(SP)
+BFD054D8 C96F SW T3, 60(SP)
+BFD054DA C94E SW T2, 56(SP)
+BFD054DC C92D SW T1, 52(SP)
+BFD054DE C90C SW T0, 48(SP)
+BFD054E0 C8EB SW A3, 44(SP)
+BFD054E2 C8CA SW A2, 40(SP)
+BFD054E4 C8A9 SW A1, 36(SP)
+BFD054E6 C888 SW A0, 32(SP)
+BFD054E8 C825 SW AT, 20(SP)
+BFD054EA 4642 MFLO V0
+BFD054EC C859 SW V0, 100(SP)
+BFD054EE 4603 MFHI V1
+BFD054F0 C878 SW V1, 96(SP)
+BFD054F2 0FDD MOVE S8, SP
+238: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 12, TRUE);\r
+BFD054F4 EE0F LI A0, 15
+BFD054F6 EE8C LI A1, 12
+BFD054F8 EF01 LI A2, 1
+BFD054FA 3A4077E8 JALS jtvic_dis_clr_source
+BFD054FC 0C003A40 SH S2, 3072(ZERO)
+BFD054FE 0C00 NOP
+239: }\r
+BFD05500 0FBE MOVE SP, S8
+BFD05502 4859 LW V0, 100(SP)
+BFD05504 3D7C0002 MTLO V0
+BFD05506 48783D7C LH T3, 18552(GP)
+BFD05508 4878 LW V1, 96(SP)
+BFD0550A 2D7C0003 MTHI V1
+BFD0550C 2D7C ANDI V0, A3, 0x40
+BFD0550E 485C LW V0, 112(SP)
+BFD05510 2D27 ANDI V0, V0, 0xF
+BFD05512 001340A2 BNEZC V0, 0xBFD0553C
+BFD05516 4BF7 LW RA, 92(SP)
+BFD05518 4BD6 LW S8, 88(SP)
+BFD0551A 4B35 LW T9, 84(SP)
+BFD0551C 4B14 LW T8, 80(SP)
+BFD0551E 49F3 LW T7, 76(SP)
+BFD05520 49D2 LW T6, 72(SP)
+BFD05522 49B1 LW T5, 68(SP)
+BFD05524 4990 LW T4, 64(SP)
+BFD05526 496F LW T3, 60(SP)
+BFD05528 494E LW T2, 56(SP)
+BFD0552A 492D LW T1, 52(SP)
+BFD0552C 490C LW T0, 48(SP)
+BFD0552E 48EB LW A3, 44(SP)
+BFD05530 48CA LW A2, 40(SP)
+BFD05532 48A9 LW A1, 36(SP)
+BFD05534 4888 LW A0, 32(SP)
+BFD05536 4867 LW V1, 28(SP)
+BFD05538 4846 LW V0, 24(SP)
+BFD0553A 4825 LW AT, 20(SP)
+BFD0553C 477C0000 DI ZERO
+BFD05540 18000000 SLL ZERO, ZERO, 3
+BFD05542 4B5D1800 SB ZERO, 19293(ZERO)
+BFD05544 4B5D LW K0, 116(SP)
+BFD05546 4B7B LW K1, 108(SP)
+BFD05548 02FC034E MTC0 K0, EPC
+BFD0554C 4B5C LW K0, 112(SP)
+BFD0554E 4C3D ADDIU SP, SP, 120
+BFD05550 12FC034C MTC0 K0, SRSCtl
+BFD05552 03BD12FC ADDI S7, GP, 957
+BFD05554 F17C03BD WRPGPR SP, SP
+BFD05556 036CF17C JALX 0xBDF00DB0
+BFD05558 02FC036C MTC0 K1, Status
+BFD0555A 000002FC SLL S7, GP, 0
+BFD0555C F37C0000 ERET
+BFD0555E 03BDF37C JALX 0xBDF00EF4
+240: \r
+241: /* VCI IN1 */\r
+242: void __attribute__((weak, interrupt, nomips16))\r
+243: girq23_b13(void)\r
+244: {\r
+BFD05560 E17C03BD RDPGPR SP, SP
+BFD05564 00FC036E MFC0 K1, EPC
+BFD05566 034C00FC INS A3, GP, 13, -12
+BFD05568 10FC034C MFC0 K0, SRSCtl
+BFD0556A 4FC510FC ADDI A3, GP, 20421
+BFD0556C 4FC5 ADDIU SP, SP, -120
+BFD0556E CB7D SW K1, 116(SP)
+BFD05570 00FC036C MFC0 K1, Status
+BFD05574 CB5C SW K0, 112(SP)
+BFD05576 00FC034D MFC0 K0, Cause
+BFD0557A CB7B SW K1, 108(SP)
+BFD0557C 5040035A SRL K0, K0, 10
+BFD0557E 037A5040 ORI V0, ZERO, 890
+BFD05580 7A8C037A INS K1, K0, 10, 6
+BFD05582 03607A8C ADDIUPC A1, 787296
+BFD05584 204C0360 INS K1, ZERO, 1, 4
+BFD05586 036C204C LWC2 V0, 876(T4)
+BFD05588 02FC036C MTC0 K1, Status
+BFD0558C C867 SW V1, 28(SP)
+BFD0558E C846 SW V0, 24(SP)
+BFD05590 487C LW V1, 112(SP)
+BFD05592 2DB7 ANDI V1, V1, 0xF
+BFD05594 001140A3 BNEZC V1, 0xBFD055BA
+BFD05598 CBF7 SW RA, 92(SP)
+BFD0559A CBD6 SW S8, 88(SP)
+BFD0559C CB35 SW T9, 84(SP)
+BFD0559E CB14 SW T8, 80(SP)
+BFD055A0 C9F3 SW T7, 76(SP)
+BFD055A2 C9D2 SW T6, 72(SP)
+BFD055A4 C9B1 SW T5, 68(SP)
+BFD055A6 C990 SW T4, 64(SP)
+BFD055A8 C96F SW T3, 60(SP)
+BFD055AA C94E SW T2, 56(SP)
+BFD055AC C92D SW T1, 52(SP)
+BFD055AE C90C SW T0, 48(SP)
+BFD055B0 C8EB SW A3, 44(SP)
+BFD055B2 C8CA SW A2, 40(SP)
+BFD055B4 C8A9 SW A1, 36(SP)
+BFD055B6 C888 SW A0, 32(SP)
+BFD055B8 C825 SW AT, 20(SP)
+BFD055BA 4642 MFLO V0
+BFD055BC C859 SW V0, 100(SP)
+BFD055BE 4603 MFHI V1
+BFD055C0 C878 SW V1, 96(SP)
+BFD055C2 0FDD MOVE S8, SP
+245: jtvic_dis_clr_source(MEC14xx_GIRQ23_ID, 13, TRUE);\r
+BFD055C4 EE0F LI A0, 15
+BFD055C6 EE8D LI A1, 13
+BFD055C8 EF01 LI A2, 1
+BFD055CA 3A4077E8 JALS jtvic_dis_clr_source
+BFD055CC 0C003A40 SH S2, 3072(ZERO)
+BFD055CE 0C00 NOP
+246: }\r
+BFD055D0 0FBE MOVE SP, S8
+BFD055D2 4859 LW V0, 100(SP)
+BFD055D4 3D7C0002 MTLO V0
+BFD055D6 48783D7C LH T3, 18552(GP)
+BFD055D8 4878 LW V1, 96(SP)
+BFD055DA 2D7C0003 MTHI V1
+BFD055DC 2D7C ANDI V0, A3, 0x40
+BFD055DE 485C LW V0, 112(SP)
+BFD055E0 2D27 ANDI V0, V0, 0xF
+BFD055E2 001340A2 BNEZC V0, 0xBFD0560C
+BFD055E6 4BF7 LW RA, 92(SP)
+BFD055E8 4BD6 LW S8, 88(SP)
+BFD055EA 4B35 LW T9, 84(SP)
+BFD055EC 4B14 LW T8, 80(SP)
+BFD055EE 49F3 LW T7, 76(SP)
+BFD055F0 49D2 LW T6, 72(SP)
+BFD055F2 49B1 LW T5, 68(SP)
+BFD055F4 4990 LW T4, 64(SP)
+BFD055F6 496F LW T3, 60(SP)
+BFD055F8 494E LW T2, 56(SP)
+BFD055FA 492D LW T1, 52(SP)
+BFD055FC 490C LW T0, 48(SP)
+BFD055FE 48EB LW A3, 44(SP)
+BFD05600 48CA LW A2, 40(SP)
+BFD05602 48A9 LW A1, 36(SP)
+BFD05604 4888 LW A0, 32(SP)
+BFD05606 4867 LW V1, 28(SP)
+BFD05608 4846 LW V0, 24(SP)
+BFD0560A 4825 LW AT, 20(SP)
+BFD0560C 477C0000 DI ZERO
+BFD05610 18000000 SLL ZERO, ZERO, 3
+BFD05612 4B5D1800 SB ZERO, 19293(ZERO)
+BFD05614 4B5D LW K0, 116(SP)
+BFD05616 4B7B LW K1, 108(SP)
+BFD05618 02FC034E MTC0 K0, EPC
+BFD0561C 4B5C LW K0, 112(SP)
+BFD0561E 4C3D ADDIU SP, SP, 120
+BFD05620 12FC034C MTC0 K0, SRSCtl
+BFD05622 03BD12FC ADDI S7, GP, 957
+BFD05624 F17C03BD WRPGPR SP, SP
+BFD05626 036CF17C JALX 0xBDF00DB0
+BFD05628 02FC036C MTC0 K1, Status
+BFD0562A 000002FC SLL S7, GP, 0
+BFD0562C F37C0000 ERET
+BFD0562E 4FF5F37C JALX 0xBDF13FD4
+247: \r
+248: \r
+249: #endif\r
+250: \r
+251: \r
+252: /* end girq23.c */\r
+253: /** @}\r
+254: */\r
+255: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq22.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq22.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_trace_func.h"\r
+34: \r
+35: \r
+36: #if GIRQ22_DISAGG == 0\r
+37: \r
+38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+39: girq22_isr(void)\r
+40: {\r
+BFD07228 E17C03BD RDPGPR SP, SP
+BFD0722C 00FC036E MFC0 K1, EPC
+BFD0722E 034C00FC INS A3, GP, 13, -12
+BFD07230 10FC034C MFC0 K0, SRSCtl
+BFD07232 4FF110FC ADDI A3, GP, 20465
+BFD07234 4FF1 ADDIU SP, SP, -32
+BFD07236 CB67 SW K1, 28(SP)
+BFD07238 00FC036C MFC0 K1, Status
+BFD0723C CB46 SW K0, 24(SP)
+BFD0723E 00FC034D MFC0 K0, Cause
+BFD07242 CB65 SW K1, 20(SP)
+BFD07244 5040035A SRL K0, K0, 10
+BFD07246 037A5040 ORI V0, ZERO, 890
+BFD07248 7A8C037A INS K1, K0, 10, 6
+BFD0724A 03607A8C ADDIUPC A1, 787296
+BFD0724C 204C0360 INS K1, ZERO, 1, 4
+BFD0724E 036C204C LWC2 V0, 876(T4)
+BFD07250 02FC036C MTC0 K1, Status
+BFD07254 C862 SW V1, 8(SP)
+BFD07256 C841 SW V0, 4(SP)
+BFD07258 4866 LW V1, 24(SP)
+BFD0725A 2DB7 ANDI V1, V1, 0xF
+BFD0725C CBC3 SW S8, 12(SP)
+BFD0725E 0FDD MOVE S8, SP
+41: JTVIC_GROUP_EN_CLR->w = (1ul<<14);\r
+BFD07260 BFFF41A2 LUI V0, 0xBFFF
+BFD07262 5042BFFF LDC1 F31, 20546(RA)
+BFD07264 C50C5042 ORI V0, V0, -15092
+BFD07268 40003060 ADDIU V1, ZERO, 16384
+BFD0726A E9A04000 BLTZ ZERO, 0xBFD045AE
+BFD0726C E9A0 SW V1, 0(V0)
+42: }\r
+BFD0726E 0FBE MOVE SP, S8
+BFD07270 4846 LW V0, 24(SP)
+BFD07272 2D27 ANDI V0, V0, 0xF
+BFD07274 4BC3 LW S8, 12(SP)
+BFD07276 4862 LW V1, 8(SP)
+BFD07278 4841 LW V0, 4(SP)
+BFD0727A 477C0000 DI ZERO
+BFD0727E 18000000 SLL ZERO, ZERO, 3
+BFD07280 4B471800 SB ZERO, 19271(ZERO)
+BFD07282 4B47 LW K0, 28(SP)
+BFD07284 4B65 LW K1, 20(SP)
+BFD07286 02FC034E MTC0 K0, EPC
+BFD0728A 4B46 LW K0, 24(SP)
+BFD0728C 4C11 ADDIU SP, SP, 32
+BFD0728E 12FC034C MTC0 K0, SRSCtl
+BFD07290 03BD12FC ADDI S7, GP, 957
+BFD07292 F17C03BD WRPGPR SP, SP
+BFD07294 036CF17C JALX 0xBDF00DB0
+BFD07296 02FC036C MTC0 K1, Status
+BFD07298 000002FC SLL S7, GP, 0
+BFD0729A F37C0000 ERET
+BFD0729C 0C00F37C JALX 0xBDF03000
+43: \r
+44: #else\r
+45: \r
+46: void __attribute__((weak, interrupt, nomips16))\r
+47: girq22_b0(void)\r
+48: {\r
+49: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 0);\r
+50: }\r
+51: \r
+52: void __attribute__((weak, interrupt, nomips16))\r
+53: girq22_b1(void)\r
+54: {\r
+55: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 1);\r
+56: }\r
+57: \r
+58: void __attribute__((weak, interrupt, nomips16))\r
+59: girq22_b2(void)\r
+60: {\r
+61: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 2);\r
+62: }\r
+63: \r
+64: void __attribute__((weak, interrupt, nomips16))\r
+65: girq22_b3(void)\r
+66: {\r
+67: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 3);\r
+68: }\r
+69: \r
+70: void __attribute__((weak, interrupt, nomips16))\r
+71: girq22_b4(void)\r
+72: {\r
+73: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 4);\r
+74: }\r
+75: \r
+76: void __attribute__((weak, interrupt, nomips16))\r
+77: girq22_b5(void)\r
+78: {\r
+79: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 5);\r
+80: }\r
+81: \r
+82: void __attribute__((weak, interrupt, nomips16))\r
+83: girq22_b6(void)\r
+84: {\r
+85: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 6);\r
+86: }\r
+87: \r
+88: void __attribute__((weak, interrupt, nomips16))\r
+89: girq22_b7(void)\r
+90: {\r
+91: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 7);\r
+92: }\r
+93: \r
+94: void __attribute__((weak, interrupt, nomips16))\r
+95: girq22_b8(void)\r
+96: {\r
+97: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 8);\r
+98: }\r
+99: \r
+100: void __attribute__((weak, interrupt, nomips16))\r
+101: girq22_b9(void)\r
+102: {\r
+103: jtvic_dis_clr_source(MEC14xx_GIRQ22_ID, 9);\r
+104: }\r
+105: \r
+106: \r
+107: #endif\r
+108: \r
+109: /* end girq22.c */\r
+110: /** @}\r
+111: */\r
+112: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq21.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq21.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_trace_func.h"\r
+34: \r
+35: \r
+36: #if GIRQ21_DISAGG == 0\r
+37: \r
+38: /*\r
+39: * GIRQ21 is a wake peripheral logic only interrupt.\r
+40: * It's purpose is to allow the peripheral logic such as SMBus or LPC to \r
+41: * wake an service HW event without waking the EC.\r
+42: * This handler is superfluous.\r
+43: */\r
+44: \r
+45: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+46: girq21_isr(void)\r
+47: {\r
+BFD071B0 E17C03BD RDPGPR SP, SP
+BFD071B4 00FC036E MFC0 K1, EPC
+BFD071B6 034C00FC INS A3, GP, 13, -12
+BFD071B8 10FC034C MFC0 K0, SRSCtl
+BFD071BA 4FF110FC ADDI A3, GP, 20465
+BFD071BC 4FF1 ADDIU SP, SP, -32
+BFD071BE CB67 SW K1, 28(SP)
+BFD071C0 00FC036C MFC0 K1, Status
+BFD071C4 CB46 SW K0, 24(SP)
+BFD071C6 00FC034D MFC0 K0, Cause
+BFD071CA CB65 SW K1, 20(SP)
+BFD071CC 5040035A SRL K0, K0, 10
+BFD071CE 037A5040 ORI V0, ZERO, 890
+BFD071D0 7A8C037A INS K1, K0, 10, 6
+BFD071D2 03607A8C ADDIUPC A1, 787296
+BFD071D4 204C0360 INS K1, ZERO, 1, 4
+BFD071D6 036C204C LWC2 V0, 876(T4)
+BFD071D8 02FC036C MTC0 K1, Status
+BFD071DC C862 SW V1, 8(SP)
+BFD071DE C841 SW V0, 4(SP)
+BFD071E0 4866 LW V1, 24(SP)
+BFD071E2 2DB7 ANDI V1, V1, 0xF
+BFD071E4 CBC3 SW S8, 12(SP)
+BFD071E6 0FDD MOVE S8, SP
+48: JTVIC_GROUP_EN_CLR->w = (1ul<<13);\r
+BFD071E8 BFFF41A2 LUI V0, 0xBFFF
+BFD071EA 5042BFFF LDC1 F31, 20546(RA)
+BFD071EC C50C5042 ORI V0, V0, -15092
+BFD071F0 20003060 ADDIU V1, ZERO, 8192
+BFD071F4 E9A0 SW V1, 0(V0)
+49: }\r
+BFD071F6 0FBE MOVE SP, S8
+BFD071F8 4846 LW V0, 24(SP)
+BFD071FA 2D27 ANDI V0, V0, 0xF
+BFD071FC 4BC3 LW S8, 12(SP)
+BFD071FE 4862 LW V1, 8(SP)
+BFD07200 4841 LW V0, 4(SP)
+BFD07202 477C0000 DI ZERO
+BFD07206 18000000 SLL ZERO, ZERO, 3
+BFD07208 4B471800 SB ZERO, 19271(ZERO)
+BFD0720A 4B47 LW K0, 28(SP)
+BFD0720C 4B65 LW K1, 20(SP)
+BFD0720E 02FC034E MTC0 K0, EPC
+BFD07212 4B46 LW K0, 24(SP)
+BFD07214 4C11 ADDIU SP, SP, 32
+BFD07216 12FC034C MTC0 K0, SRSCtl
+BFD07218 03BD12FC ADDI S7, GP, 957
+BFD0721A F17C03BD WRPGPR SP, SP
+BFD0721C 036CF17C JALX 0xBDF00DB0
+BFD0721E 02FC036C MTC0 K1, Status
+BFD07220 000002FC SLL S7, GP, 0
+BFD07222 F37C0000 ERET
+BFD07224 0C00F37C JALX 0xBDF03000
+50: \r
+51: #else\r
+52: \r
+53: void __attribute__((weak, interrupt, nomips16))\r
+54: girq21_b0(void)\r
+55: {\r
+56: JTVIC_GROUP_EN_CLR->w = (1ul<<13);\r
+57: }\r
+58: \r
+59: #endif\r
+60: \r
+61: /* end girq21.c */\r
+62: /** @}\r
+63: */\r
+64: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq20.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq20.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_trace_func.h"\r
+34: \r
+35: \r
+36: #if GIRQ20_DISAGG == 0\r
+37: \r
+38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+39: girq20_isr(void)\r
+40: {\r
+BFD07138 E17C03BD RDPGPR SP, SP
+BFD0713C 00FC036E MFC0 K1, EPC
+BFD0713E 034C00FC INS A3, GP, 13, -12
+BFD07140 10FC034C MFC0 K0, SRSCtl
+BFD07142 4FF110FC ADDI A3, GP, 20465
+BFD07144 4FF1 ADDIU SP, SP, -32
+BFD07146 CB67 SW K1, 28(SP)
+BFD07148 00FC036C MFC0 K1, Status
+BFD0714C CB46 SW K0, 24(SP)
+BFD0714E 00FC034D MFC0 K0, Cause
+BFD07152 CB65 SW K1, 20(SP)
+BFD07154 5040035A SRL K0, K0, 10
+BFD07156 037A5040 ORI V0, ZERO, 890
+BFD07158 7A8C037A INS K1, K0, 10, 6
+BFD0715A 03607A8C ADDIUPC A1, 787296
+BFD0715C 204C0360 INS K1, ZERO, 1, 4
+BFD0715E 036C204C LWC2 V0, 876(T4)
+BFD07160 02FC036C MTC0 K1, Status
+BFD07164 C862 SW V1, 8(SP)
+BFD07166 C841 SW V0, 4(SP)
+BFD07168 4866 LW V1, 24(SP)
+BFD0716A 2DB7 ANDI V1, V1, 0xF
+BFD0716C CBC3 SW S8, 12(SP)
+BFD0716E 0FDD MOVE S8, SP
+41: JTVIC_GROUP_EN_CLR->w = (1ul<<12);\r
+BFD07170 BFFF41A2 LUI V0, 0xBFFF
+BFD07172 5042BFFF LDC1 F31, 20546(RA)
+BFD07174 C50C5042 ORI V0, V0, -15092
+BFD07178 10003060 ADDIU V1, ZERO, 4096
+BFD0717A E9A01000 ADDI ZERO, ZERO, -5728
+BFD0717C E9A0 SW V1, 0(V0)
+42: }\r
+BFD0717E 0FBE MOVE SP, S8
+BFD07180 4846 LW V0, 24(SP)
+BFD07182 2D27 ANDI V0, V0, 0xF
+BFD07184 4BC3 LW S8, 12(SP)
+BFD07186 4862 LW V1, 8(SP)
+BFD07188 4841 LW V0, 4(SP)
+BFD0718A 477C0000 DI ZERO
+BFD0718E 18000000 SLL ZERO, ZERO, 3
+BFD07190 4B471800 SB ZERO, 19271(ZERO)
+BFD07192 4B47 LW K0, 28(SP)
+BFD07194 4B65 LW K1, 20(SP)
+BFD07196 02FC034E MTC0 K0, EPC
+BFD0719A 4B46 LW K0, 24(SP)
+BFD0719C 4C11 ADDIU SP, SP, 32
+BFD0719E 12FC034C MTC0 K0, SRSCtl
+BFD071A0 03BD12FC ADDI S7, GP, 957
+BFD071A2 F17C03BD WRPGPR SP, SP
+BFD071A4 036CF17C JALX 0xBDF00DB0
+BFD071A6 02FC036C MTC0 K1, Status
+BFD071A8 000002FC SLL S7, GP, 0
+BFD071AA F37C0000 ERET
+BFD071AC 0C00F37C JALX 0xBDF03000
+43: \r
+44: #else\r
+45: \r
+46: void __attribute__((weak, interrupt, nomips16))\r
+47: girq20_b0(void)\r
+48: {\r
+49: jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 0);\r
+50: }\r
+51: \r
+52: void __attribute__((weak, interrupt, nomips16))\r
+53: girq20_b1(void)\r
+54: {\r
+55: jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 1);\r
+56: }\r
+57: \r
+58: void __attribute__((weak, interrupt, nomips16))\r
+59: girq20_b2(void)\r
+60: {\r
+61: jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 2);\r
+62: }\r
+63: \r
+64: void __attribute__((weak, interrupt, nomips16))\r
+65: girq20_b3(void)\r
+66: {\r
+67: jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 3);\r
+68: }\r
+69: \r
+70: void __attribute__((weak, interrupt, nomips16))\r
+71: girq20_b4(void)\r
+72: {\r
+73: jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 4);\r
+74: }\r
+75: \r
+76: void __attribute__((weak, interrupt, nomips16))\r
+77: girq20_b5(void)\r
+78: {\r
+79: jtvic_dis_clr_source(MEC14xx_GIRQ20_ID, 5);\r
+80: }\r
+81: \r
+82: \r
+83: #endif\r
+84: \r
+85: /* end girq20.c */\r
+86: /** @}\r
+87: */\r
+88: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq19.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq19.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_trace_func.h"\r
+34: \r
+35: \r
+36: #if GIRQ19_DISAGG == 0\r
+37: \r
+38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+39: girq19_isr(void)\r
+40: {\r
+BFD070C0 E17C03BD RDPGPR SP, SP
+BFD070C4 00FC036E MFC0 K1, EPC
+BFD070C6 034C00FC INS A3, GP, 13, -12
+BFD070C8 10FC034C MFC0 K0, SRSCtl
+BFD070CA 4FF110FC ADDI A3, GP, 20465
+BFD070CC 4FF1 ADDIU SP, SP, -32
+BFD070CE CB67 SW K1, 28(SP)
+BFD070D0 00FC036C MFC0 K1, Status
+BFD070D4 CB46 SW K0, 24(SP)
+BFD070D6 00FC034D MFC0 K0, Cause
+BFD070DA CB65 SW K1, 20(SP)
+BFD070DC 5040035A SRL K0, K0, 10
+BFD070DE 037A5040 ORI V0, ZERO, 890
+BFD070E0 7A8C037A INS K1, K0, 10, 6
+BFD070E2 03607A8C ADDIUPC A1, 787296
+BFD070E4 204C0360 INS K1, ZERO, 1, 4
+BFD070E6 036C204C LWC2 V0, 876(T4)
+BFD070E8 02FC036C MTC0 K1, Status
+BFD070EC C862 SW V1, 8(SP)
+BFD070EE C841 SW V0, 4(SP)
+BFD070F0 4866 LW V1, 24(SP)
+BFD070F2 2DB7 ANDI V1, V1, 0xF
+BFD070F4 CBC3 SW S8, 12(SP)
+BFD070F6 0FDD MOVE S8, SP
+41: JTVIC_GROUP_EN_CLR->w = (1ul<<11);\r
+BFD070F8 BFFF41A2 LUI V0, 0xBFFF
+BFD070FA 5042BFFF LDC1 F31, 20546(RA)
+BFD070FC C50C5042 ORI V0, V0, -15092
+BFD07100 08003060 ADDIU V1, ZERO, 2048
+BFD07102 0800 LBU S0, 0(S0)
+BFD07104 E9A0 SW V1, 0(V0)
+42: }\r
+BFD07106 0FBE MOVE SP, S8
+BFD07108 4846 LW V0, 24(SP)
+BFD0710A 2D27 ANDI V0, V0, 0xF
+BFD0710C 4BC3 LW S8, 12(SP)
+BFD0710E 4862 LW V1, 8(SP)
+BFD07110 4841 LW V0, 4(SP)
+BFD07112 477C0000 DI ZERO
+BFD07116 18000000 SLL ZERO, ZERO, 3
+BFD07118 4B471800 SB ZERO, 19271(ZERO)
+BFD0711A 4B47 LW K0, 28(SP)
+BFD0711C 4B65 LW K1, 20(SP)
+BFD0711E 02FC034E MTC0 K0, EPC
+BFD07122 4B46 LW K0, 24(SP)
+BFD07124 4C11 ADDIU SP, SP, 32
+BFD07126 12FC034C MTC0 K0, SRSCtl
+BFD07128 03BD12FC ADDI S7, GP, 957
+BFD0712A F17C03BD WRPGPR SP, SP
+BFD0712C 036CF17C JALX 0xBDF00DB0
+BFD0712E 02FC036C MTC0 K1, Status
+BFD07130 000002FC SLL S7, GP, 0
+BFD07132 F37C0000 ERET
+BFD07134 0C00F37C JALX 0xBDF03000
+43: \r
+44: #else\r
+45: \r
+46: void __attribute__((weak, interrupt, nomips16))\r
+47: girq19_b0(void)\r
+48: {\r
+49: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 0);\r
+50: }\r
+51: \r
+52: void __attribute__((weak, interrupt, nomips16))\r
+53: girq19_b1(void)\r
+54: {\r
+55: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 1);\r
+56: }\r
+57: \r
+58: void __attribute__((weak, interrupt, nomips16))\r
+59: girq19_b2(void)\r
+60: {\r
+61: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 2);\r
+62: }\r
+63: \r
+64: void __attribute__((weak, interrupt, nomips16))\r
+65: girq19_b3(void)\r
+66: {\r
+67: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 3);\r
+68: }\r
+69: \r
+70: void __attribute__((weak, interrupt, nomips16))\r
+71: girq19_b4(void)\r
+72: {\r
+73: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 4);\r
+74: }\r
+75: \r
+76: void __attribute__((weak, interrupt, nomips16))\r
+77: girq19_b5(void)\r
+78: {\r
+79: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 5);\r
+80: }\r
+81: \r
+82: void __attribute__((weak, interrupt, nomips16))\r
+83: girq19_b6(void)\r
+84: {\r
+85: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 6);\r
+86: }\r
+87: \r
+88: void __attribute__((weak, interrupt, nomips16))\r
+89: girq19_b7(void)\r
+90: {\r
+91: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 7);\r
+92: }\r
+93: \r
+94: void __attribute__((weak, interrupt, nomips16))\r
+95: girq19_b8(void)\r
+96: {\r
+97: jtvic_dis_clr_source(MEC14xx_GIRQ19_ID, 8);\r
+98: }\r
+99: \r
+100: \r
+101: #endif\r
+102: \r
+103: /* end girq19.c */\r
+104: /** @}\r
+105: */\r
+106: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq18.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq18.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_trace_func.h"\r
+34: \r
+35: \r
+36: #if GIRQ18_DISAGG == 0\r
+37: \r
+38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+39: girq18_isr(void)\r
+40: {\r
+BFD07048 E17C03BD RDPGPR SP, SP
+BFD0704C 00FC036E MFC0 K1, EPC
+BFD0704E 034C00FC INS A3, GP, 13, -12
+BFD07050 10FC034C MFC0 K0, SRSCtl
+BFD07052 4FF110FC ADDI A3, GP, 20465
+BFD07054 4FF1 ADDIU SP, SP, -32
+BFD07056 CB67 SW K1, 28(SP)
+BFD07058 00FC036C MFC0 K1, Status
+BFD0705C CB46 SW K0, 24(SP)
+BFD0705E 00FC034D MFC0 K0, Cause
+BFD07062 CB65 SW K1, 20(SP)
+BFD07064 5040035A SRL K0, K0, 10
+BFD07066 037A5040 ORI V0, ZERO, 890
+BFD07068 7A8C037A INS K1, K0, 10, 6
+BFD0706A 03607A8C ADDIUPC A1, 787296
+BFD0706C 204C0360 INS K1, ZERO, 1, 4
+BFD0706E 036C204C LWC2 V0, 876(T4)
+BFD07070 02FC036C MTC0 K1, Status
+BFD07074 C862 SW V1, 8(SP)
+BFD07076 C841 SW V0, 4(SP)
+BFD07078 4866 LW V1, 24(SP)
+BFD0707A 2DB7 ANDI V1, V1, 0xF
+BFD0707C CBC3 SW S8, 12(SP)
+BFD0707E 0FDD MOVE S8, SP
+41: JTVIC_GROUP_EN_CLR->w = (1ul<<10);\r
+BFD07080 BFFF41A2 LUI V0, 0xBFFF
+BFD07082 5042BFFF LDC1 F31, 20546(RA)
+BFD07084 C50C5042 ORI V0, V0, -15092
+BFD07088 04003060 ADDIU V1, ZERO, 1024
+BFD0708A 0400 ADDU S0, S0, S0
+BFD0708C E9A0 SW V1, 0(V0)
+42: }\r
+BFD0708E 0FBE MOVE SP, S8
+BFD07090 4846 LW V0, 24(SP)
+BFD07092 2D27 ANDI V0, V0, 0xF
+BFD07094 4BC3 LW S8, 12(SP)
+BFD07096 4862 LW V1, 8(SP)
+BFD07098 4841 LW V0, 4(SP)
+BFD0709A 477C0000 DI ZERO
+BFD0709E 18000000 SLL ZERO, ZERO, 3
+BFD070A0 4B471800 SB ZERO, 19271(ZERO)
+BFD070A2 4B47 LW K0, 28(SP)
+BFD070A4 4B65 LW K1, 20(SP)
+BFD070A6 02FC034E MTC0 K0, EPC
+BFD070AA 4B46 LW K0, 24(SP)
+BFD070AC 4C11 ADDIU SP, SP, 32
+BFD070AE 12FC034C MTC0 K0, SRSCtl
+BFD070B0 03BD12FC ADDI S7, GP, 957
+BFD070B2 F17C03BD WRPGPR SP, SP
+BFD070B4 036CF17C JALX 0xBDF00DB0
+BFD070B6 02FC036C MTC0 K1, Status
+BFD070B8 000002FC SLL S7, GP, 0
+BFD070BA F37C0000 ERET
+BFD070BC 0C00F37C JALX 0xBDF03000
+43: \r
+44: #else\r
+45: \r
+46: void __attribute__((weak, interrupt, nomips16))\r
+47: girq18_b0(void)\r
+48: {\r
+49: jtvic_dis_clr_source(MEC14xx_GIRQ18_ID, 0);\r
+50: }\r
+51: \r
+52: #endif\r
+53: \r
+54: /* end girq18.c */\r
+55: /** @}\r
+56: */\r
+57: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq17.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq17.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_trace_func.h"\r
+34: \r
+35: \r
+36: #if GIRQ17_DISAGG == 0\r
+37: \r
+38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+39: girq17_isr(void)\r
+40: {\r
+BFD06FD0 E17C03BD RDPGPR SP, SP
+BFD06FD4 00FC036E MFC0 K1, EPC
+BFD06FD6 034C00FC INS A3, GP, 13, -12
+BFD06FD8 10FC034C MFC0 K0, SRSCtl
+BFD06FDA 4FF110FC ADDI A3, GP, 20465
+BFD06FDC 4FF1 ADDIU SP, SP, -32
+BFD06FDE CB67 SW K1, 28(SP)
+BFD06FE0 00FC036C MFC0 K1, Status
+BFD06FE4 CB46 SW K0, 24(SP)
+BFD06FE6 00FC034D MFC0 K0, Cause
+BFD06FEA CB65 SW K1, 20(SP)
+BFD06FEC 5040035A SRL K0, K0, 10
+BFD06FEE 037A5040 ORI V0, ZERO, 890
+BFD06FF0 7A8C037A INS K1, K0, 10, 6
+BFD06FF2 03607A8C ADDIUPC A1, 787296
+BFD06FF4 204C0360 INS K1, ZERO, 1, 4
+BFD06FF6 036C204C LWC2 V0, 876(T4)
+BFD06FF8 02FC036C MTC0 K1, Status
+BFD06FFC C862 SW V1, 8(SP)
+BFD06FFE C841 SW V0, 4(SP)
+BFD07000 4866 LW V1, 24(SP)
+BFD07002 2DB7 ANDI V1, V1, 0xF
+BFD07004 CBC3 SW S8, 12(SP)
+BFD07006 0FDD MOVE S8, SP
+41: JTVIC_GROUP_EN_CLR->w = (1ul<<9);\r
+BFD07008 BFFF41A2 LUI V0, 0xBFFF
+BFD0700A 5042BFFF LDC1 F31, 20546(RA)
+BFD0700C C50C5042 ORI V0, V0, -15092
+BFD07010 02003060 ADDIU V1, ZERO, 512
+BFD07014 E9A0 SW V1, 0(V0)
+42: }\r
+BFD07016 0FBE MOVE SP, S8
+BFD07018 4846 LW V0, 24(SP)
+BFD0701A 2D27 ANDI V0, V0, 0xF
+BFD0701C 4BC3 LW S8, 12(SP)
+BFD0701E 4862 LW V1, 8(SP)
+BFD07020 4841 LW V0, 4(SP)
+BFD07022 477C0000 DI ZERO
+BFD07026 18000000 SLL ZERO, ZERO, 3
+BFD07028 4B471800 SB ZERO, 19271(ZERO)
+BFD0702A 4B47 LW K0, 28(SP)
+BFD0702C 4B65 LW K1, 20(SP)
+BFD0702E 02FC034E MTC0 K0, EPC
+BFD07032 4B46 LW K0, 24(SP)
+BFD07034 4C11 ADDIU SP, SP, 32
+BFD07036 12FC034C MTC0 K0, SRSCtl
+BFD07038 03BD12FC ADDI S7, GP, 957
+BFD0703A F17C03BD WRPGPR SP, SP
+BFD0703C 036CF17C JALX 0xBDF00DB0
+BFD0703E 02FC036C MTC0 K1, Status
+BFD07040 000002FC SLL S7, GP, 0
+BFD07042 F37C0000 ERET
+BFD07044 0C00F37C JALX 0xBDF03000
+43: \r
+44: #else\r
+45: \r
+46: void __attribute__((weak, interrupt, nomips16))\r
+47: girq17_b0(void)\r
+48: {\r
+49: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 0);\r
+50: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 0);\r
+51: }\r
+52: \r
+53: void __attribute__((weak, interrupt, nomips16))\r
+54: girq17_b1(void)\r
+55: {\r
+56: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 1);\r
+57: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 1);\r
+58: }\r
+59: \r
+60: void __attribute__((weak, interrupt, nomips16))\r
+61: girq17_b2(void)\r
+62: {\r
+63: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 2);\r
+64: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 2);\r
+65: }\r
+66: \r
+67: void __attribute__((weak, interrupt, nomips16))\r
+68: girq17_b3(void)\r
+69: {\r
+70: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 3);\r
+71: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 3);\r
+72: }\r
+73: \r
+74: void __attribute__((weak, interrupt, nomips16))\r
+75: girq17_b4(void)\r
+76: {\r
+77: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 4);\r
+78: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 4);\r
+79: }\r
+80: \r
+81: void __attribute__((weak, interrupt, nomips16))\r
+82: girq17_b5(void)\r
+83: {\r
+84: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 5);\r
+85: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 5);\r
+86: }\r
+87: \r
+88: void __attribute__((weak, interrupt, nomips16))\r
+89: girq17_b6(void)\r
+90: {\r
+91: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 6);\r
+92: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 6);\r
+93: }\r
+94: \r
+95: void __attribute__((weak, interrupt, nomips16))\r
+96: girq17_b7(void)\r
+97: {\r
+98: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 7);\r
+99: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 7);\r
+100: }\r
+101: \r
+102: void __attribute__((weak, interrupt, nomips16))\r
+103: girq17_b8(void)\r
+104: {\r
+105: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 8);\r
+106: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 8);\r
+107: }\r
+108: \r
+109: void __attribute__((weak, interrupt, nomips16))\r
+110: girq17_b9(void)\r
+111: {\r
+112: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 9);\r
+113: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 9);\r
+114: }\r
+115: \r
+116: void __attribute__((weak, interrupt, nomips16))\r
+117: girq17_b10(void)\r
+118: {\r
+119: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].EN_CLR = (1ul << 10);\r
+120: JTVIC_GIRQ->REGS[MEC14xx_GIRQ17_ID].SOURCE = (1ul << 10);\r
+121: }\r
+122: \r
+123: #endif\r
+124: \r
+125: /* end girq17.c */\r
+126: /** @}\r
+127: */\r
+128: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq16.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq16.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: \r
+29: #include "appcfg.h"\r
+30: #include "platform.h"\r
+31: #include "MEC14xx/mec14xx.h"\r
+32: #include "MEC14xx/mec14xx_girqs.h"\r
+33: #include "MEC14xx/mec14xx_gpio.h"\r
+34: #include "MEC14xx/mec14xx_trace_func.h"\r
+35: \r
+36: \r
+37: #if GIRQ16_DISAGG == 0\r
+38: \r
+39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+40: girq16_isr(void)\r
+41: {\r
+BFD06F58 E17C03BD RDPGPR SP, SP
+BFD06F5C 00FC036E MFC0 K1, EPC
+BFD06F5E 034C00FC INS A3, GP, 13, -12
+BFD06F60 10FC034C MFC0 K0, SRSCtl
+BFD06F62 4FF110FC ADDI A3, GP, 20465
+BFD06F64 4FF1 ADDIU SP, SP, -32
+BFD06F66 CB67 SW K1, 28(SP)
+BFD06F68 00FC036C MFC0 K1, Status
+BFD06F6C CB46 SW K0, 24(SP)
+BFD06F6E 00FC034D MFC0 K0, Cause
+BFD06F72 CB65 SW K1, 20(SP)
+BFD06F74 5040035A SRL K0, K0, 10
+BFD06F76 037A5040 ORI V0, ZERO, 890
+BFD06F78 7A8C037A INS K1, K0, 10, 6
+BFD06F7A 03607A8C ADDIUPC A1, 787296
+BFD06F7C 204C0360 INS K1, ZERO, 1, 4
+BFD06F7E 036C204C LWC2 V0, 876(T4)
+BFD06F80 02FC036C MTC0 K1, Status
+BFD06F84 C862 SW V1, 8(SP)
+BFD06F86 C841 SW V0, 4(SP)
+BFD06F88 4866 LW V1, 24(SP)
+BFD06F8A 2DB7 ANDI V1, V1, 0xF
+BFD06F8C CBC3 SW S8, 12(SP)
+BFD06F8E 0FDD MOVE S8, SP
+42: JTVIC_GROUP_EN_CLR->w = (1ul<<8);\r
+BFD06F90 BFFF41A2 LUI V0, 0xBFFF
+BFD06F92 5042BFFF LDC1 F31, 20546(RA)
+BFD06F94 C50C5042 ORI V0, V0, -15092
+BFD06F98 01003060 ADDIU V1, ZERO, 256
+BFD06F9C E9A0 SW V1, 0(V0)
+43: }\r
+BFD06F9E 0FBE MOVE SP, S8
+BFD06FA0 4846 LW V0, 24(SP)
+BFD06FA2 2D27 ANDI V0, V0, 0xF
+BFD06FA4 4BC3 LW S8, 12(SP)
+BFD06FA6 4862 LW V1, 8(SP)
+BFD06FA8 4841 LW V0, 4(SP)
+BFD06FAA 477C0000 DI ZERO
+BFD06FAE 18000000 SLL ZERO, ZERO, 3
+BFD06FB0 4B471800 SB ZERO, 19271(ZERO)
+BFD06FB2 4B47 LW K0, 28(SP)
+BFD06FB4 4B65 LW K1, 20(SP)
+BFD06FB6 02FC034E MTC0 K0, EPC
+BFD06FBA 4B46 LW K0, 24(SP)
+BFD06FBC 4C11 ADDIU SP, SP, 32
+BFD06FBE 12FC034C MTC0 K0, SRSCtl
+BFD06FC0 03BD12FC ADDI S7, GP, 957
+BFD06FC2 F17C03BD WRPGPR SP, SP
+BFD06FC4 036CF17C JALX 0xBDF00DB0
+BFD06FC6 02FC036C MTC0 K1, Status
+BFD06FC8 000002FC SLL S7, GP, 0
+BFD06FCA F37C0000 ERET
+BFD06FCC 0C00F37C JALX 0xBDF03000
+44: \r
+45: #else\r
+46: \r
+47: void __attribute__((weak, interrupt, nomips16))\r
+48: girq16_b0(void)\r
+49: {\r
+50: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 0);\r
+51: }\r
+52: \r
+53: void __attribute__((weak, interrupt, nomips16))\r
+54: girq16_b1(void)\r
+55: {\r
+56: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 1);\r
+57: }\r
+58: \r
+59: void __attribute__((weak, interrupt, nomips16))\r
+60: girq16_b2(void)\r
+61: {\r
+62: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 2);\r
+63: }\r
+64: \r
+65: void __attribute__((weak, interrupt, nomips16))\r
+66: girq16_b3(void)\r
+67: {\r
+68: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 3);\r
+69: }\r
+70: \r
+71: void __attribute__((weak, interrupt, nomips16))\r
+72: girq16_b4(void)\r
+73: {\r
+74: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 4);\r
+75: }\r
+76: \r
+77: void __attribute__((weak, interrupt, nomips16))\r
+78: girq16_b5(void)\r
+79: {\r
+80: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 5);\r
+81: }\r
+82: \r
+83: void __attribute__((weak, interrupt, nomips16))\r
+84: girq16_b6(void)\r
+85: {\r
+86: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 6);\r
+87: }\r
+88: \r
+89: void __attribute__((weak, interrupt, nomips16))\r
+90: girq16_b7(void)\r
+91: {\r
+92: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 7);\r
+93: }\r
+94: \r
+95: void __attribute__((weak, interrupt, nomips16))\r
+96: girq16_b8(void)\r
+97: {\r
+98: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 8);\r
+99: }\r
+100: \r
+101: void __attribute__((weak, interrupt, nomips16))\r
+102: girq16_b9(void)\r
+103: {\r
+104: jtvic_dis_clr_source(MEC14xx_GIRQ16_ID, 9);\r
+105: }\r
+106: \r
+107: #endif\r
+108: \r
+109: /* end girq16.c */\r
+110: /** @}\r
+111: */\r
+112: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq15.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq15.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_trace_func.h"\r
+34: \r
+35: \r
+36: #if GIRQ15_DISAGG == 0\r
+37: \r
+38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+39: girq15_isr(void)\r
+40: {\r
+BFD06EE0 E17C03BD RDPGPR SP, SP
+BFD06EE4 00FC036E MFC0 K1, EPC
+BFD06EE6 034C00FC INS A3, GP, 13, -12
+BFD06EE8 10FC034C MFC0 K0, SRSCtl
+BFD06EEA 4FF110FC ADDI A3, GP, 20465
+BFD06EEC 4FF1 ADDIU SP, SP, -32
+BFD06EEE CB67 SW K1, 28(SP)
+BFD06EF0 00FC036C MFC0 K1, Status
+BFD06EF4 CB46 SW K0, 24(SP)
+BFD06EF6 00FC034D MFC0 K0, Cause
+BFD06EFA CB65 SW K1, 20(SP)
+BFD06EFC 5040035A SRL K0, K0, 10
+BFD06EFE 037A5040 ORI V0, ZERO, 890
+BFD06F00 7A8C037A INS K1, K0, 10, 6
+BFD06F02 03607A8C ADDIUPC A1, 787296
+BFD06F04 204C0360 INS K1, ZERO, 1, 4
+BFD06F06 036C204C LWC2 V0, 876(T4)
+BFD06F08 02FC036C MTC0 K1, Status
+BFD06F0C C862 SW V1, 8(SP)
+BFD06F0E C841 SW V0, 4(SP)
+BFD06F10 4866 LW V1, 24(SP)
+BFD06F12 2DB7 ANDI V1, V1, 0xF
+BFD06F14 CBC3 SW S8, 12(SP)
+BFD06F16 0FDD MOVE S8, SP
+41: JTVIC_GROUP_EN_CLR->w = (1ul<<7);\r
+BFD06F18 BFFF41A2 LUI V0, 0xBFFF
+BFD06F1A 5042BFFF LDC1 F31, 20546(RA)
+BFD06F1C C50C5042 ORI V0, V0, -15092
+BFD06F20 00803060 ADDIU V1, ZERO, 128
+BFD06F24 E9A0 SW V1, 0(V0)
+42: }\r
+BFD06F26 0FBE MOVE SP, S8
+BFD06F28 4846 LW V0, 24(SP)
+BFD06F2A 2D27 ANDI V0, V0, 0xF
+BFD06F2C 4BC3 LW S8, 12(SP)
+BFD06F2E 4862 LW V1, 8(SP)
+BFD06F30 4841 LW V0, 4(SP)
+BFD06F32 477C0000 DI ZERO
+BFD06F36 18000000 SLL ZERO, ZERO, 3
+BFD06F38 4B471800 SB ZERO, 19271(ZERO)
+BFD06F3A 4B47 LW K0, 28(SP)
+BFD06F3C 4B65 LW K1, 20(SP)
+BFD06F3E 02FC034E MTC0 K0, EPC
+BFD06F42 4B46 LW K0, 24(SP)
+BFD06F44 4C11 ADDIU SP, SP, 32
+BFD06F46 12FC034C MTC0 K0, SRSCtl
+BFD06F48 03BD12FC ADDI S7, GP, 957
+BFD06F4A F17C03BD WRPGPR SP, SP
+BFD06F4C 036CF17C JALX 0xBDF00DB0
+BFD06F4E 02FC036C MTC0 K1, Status
+BFD06F50 000002FC SLL S7, GP, 0
+BFD06F52 F37C0000 ERET
+BFD06F54 0C00F37C JALX 0xBDF03000
+43: \r
+44: #else\r
+45: \r
+46: void __attribute__((weak, interrupt, nomips16))\r
+47: girq15_b0(void)\r
+48: {\r
+49: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 0);\r
+50: }\r
+51: \r
+52: void __attribute__((weak, interrupt, nomips16))\r
+53: girq15_b1(void)\r
+54: {\r
+55: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 1);\r
+56: }\r
+57: \r
+58: void __attribute__((weak, interrupt, nomips16))\r
+59: girq15_b2(void)\r
+60: {\r
+61: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 2);\r
+62: }\r
+63: \r
+64: void __attribute__((weak, interrupt, nomips16))\r
+65: girq15_b3(void)\r
+66: {\r
+67: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 3);\r
+68: }\r
+69: \r
+70: void __attribute__((weak, interrupt, nomips16))\r
+71: girq15_b4(void)\r
+72: {\r
+73: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 4);\r
+74: }\r
+75: \r
+76: void __attribute__((weak, interrupt, nomips16))\r
+77: girq15_b5(void)\r
+78: {\r
+79: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 5);\r
+80: }\r
+81: \r
+82: void __attribute__((weak, interrupt, nomips16))\r
+83: girq15_b6(void)\r
+84: {\r
+85: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 6);\r
+86: }\r
+87: \r
+88: void __attribute__((weak, interrupt, nomips16))\r
+89: girq15_b7(void)\r
+90: {\r
+91: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 7);\r
+92: }\r
+93: \r
+94: void __attribute__((weak, interrupt, nomips16))\r
+95: girq15_b8(void)\r
+96: {\r
+97: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 8);\r
+98: }\r
+99: \r
+100: void __attribute__((weak, interrupt, nomips16))\r
+101: girq15_b9(void)\r
+102: {\r
+103: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 9);\r
+104: }\r
+105: \r
+106: void __attribute__((weak, interrupt, nomips16))\r
+107: girq15_b10(void)\r
+108: {\r
+109: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 10);\r
+110: }\r
+111: \r
+112: void __attribute__((weak, interrupt, nomips16))\r
+113: girq15_b11(void)\r
+114: {\r
+115: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 11);\r
+116: }\r
+117: \r
+118: void __attribute__((weak, interrupt, nomips16))\r
+119: girq15_b12(void)\r
+120: {\r
+121: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 12);\r
+122: }\r
+123: \r
+124: void __attribute__((weak, interrupt, nomips16))\r
+125: girq15_b13(void)\r
+126: {\r
+127: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 13);\r
+128: }\r
+129: \r
+130: void __attribute__((weak, interrupt, nomips16))\r
+131: girq15_b14(void)\r
+132: {\r
+133: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 14);\r
+134: }\r
+135: \r
+136: void __attribute__((weak, interrupt, nomips16))\r
+137: girq15_b15(void)\r
+138: {\r
+139: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 15);\r
+140: }\r
+141: \r
+142: void __attribute__((weak, interrupt, nomips16))\r
+143: girq15_b16(void)\r
+144: {\r
+145: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 16);\r
+146: }\r
+147: \r
+148: void __attribute__((weak, interrupt, nomips16))\r
+149: girq15_b17(void)\r
+150: {\r
+151: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 17);\r
+152: }\r
+153: \r
+154: void __attribute__((weak, interrupt, nomips16))\r
+155: girq15_b18(void)\r
+156: {\r
+157: jtvic_dis_clr_source(MEC14xx_GIRQ15_ID, 18);\r
+158: }\r
+159: \r
+160: \r
+161: #endif\r
+162: \r
+163: /* end girq15.c */\r
+164: /** @}\r
+165: */\r
+166: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq14.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq14.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_trace_func.h"\r
+34: \r
+35: \r
+36: #if GIRQ14_DISAGG == 0\r
+37: \r
+38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+39: girq14_isr(void)\r
+40: {\r
+BFD078A0 E17C03BD RDPGPR SP, SP
+BFD078A4 00FC036E MFC0 K1, EPC
+BFD078A6 034C00FC INS A3, GP, 13, -12
+BFD078A8 10FC034C MFC0 K0, SRSCtl
+BFD078AA 4FF110FC ADDI A3, GP, 20465
+BFD078AC 4FF1 ADDIU SP, SP, -32
+BFD078AE CB67 SW K1, 28(SP)
+BFD078B0 00FC036C MFC0 K1, Status
+BFD078B4 CB46 SW K0, 24(SP)
+BFD078B6 00FC034D MFC0 K0, Cause
+BFD078BA CB65 SW K1, 20(SP)
+BFD078BC 5040035A SRL K0, K0, 10
+BFD078BE 037A5040 ORI V0, ZERO, 890
+BFD078C0 7A8C037A INS K1, K0, 10, 6
+BFD078C2 03607A8C ADDIUPC A1, 787296
+BFD078C4 204C0360 INS K1, ZERO, 1, 4
+BFD078C6 036C204C LWC2 V0, 876(T4)
+BFD078C8 02FC036C MTC0 K1, Status
+BFD078CC C862 SW V1, 8(SP)
+BFD078CE C841 SW V0, 4(SP)
+BFD078D0 4866 LW V1, 24(SP)
+BFD078D2 2DB7 ANDI V1, V1, 0xF
+BFD078D4 CBC3 SW S8, 12(SP)
+BFD078D6 0FDD MOVE S8, SP
+41: JTVIC_GROUP_EN_CLR->w = (1ul<<6);\r
+BFD078D8 BFFF41A2 LUI V0, 0xBFFF
+BFD078DA 5042BFFF LDC1 F31, 20546(RA)
+BFD078DC C50C5042 ORI V0, V0, -15092
+BFD078E0 EDC0 LI V1, 64
+BFD078E2 E9A0 SW V1, 0(V0)
+42: }\r
+BFD078E4 0FBE MOVE SP, S8
+BFD078E6 4846 LW V0, 24(SP)
+BFD078E8 2D27 ANDI V0, V0, 0xF
+BFD078EA 4BC3 LW S8, 12(SP)
+BFD078EC 4862 LW V1, 8(SP)
+BFD078EE 4841 LW V0, 4(SP)
+BFD078F0 477C0000 DI ZERO
+BFD078F4 18000000 SLL ZERO, ZERO, 3
+BFD078F6 4B471800 SB ZERO, 19271(ZERO)
+BFD078F8 4B47 LW K0, 28(SP)
+BFD078FA 4B65 LW K1, 20(SP)
+BFD078FC 02FC034E MTC0 K0, EPC
+BFD07900 4B46 LW K0, 24(SP)
+BFD07902 4C11 ADDIU SP, SP, 32
+BFD07904 12FC034C MTC0 K0, SRSCtl
+BFD07906 03BD12FC ADDI S7, GP, 957
+BFD07908 F17C03BD WRPGPR SP, SP
+BFD0790A 036CF17C JALX 0xBDF00DB0
+BFD0790C 02FC036C MTC0 K1, Status
+BFD0790E 000002FC SLL S7, GP, 0
+BFD07910 F37C0000 ERET
+BFD07912 4FF1F37C JALX 0xBDF13FC4
+43: \r
+44: #else\r
+45: \r
+46: void __attribute__((weak, interrupt, nomips16))\r
+47: girq14_b0(void)\r
+48: {\r
+49: jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 0);\r
+50: }\r
+51: \r
+52: void __attribute__((weak, interrupt, nomips16))\r
+53: girq14_b1(void)\r
+54: {\r
+55: jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 1);\r
+56: }\r
+57: \r
+58: void __attribute__((weak, interrupt, nomips16))\r
+59: girq14_b2(void)\r
+60: {\r
+61: jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 2);\r
+62: }\r
+63: \r
+64: void __attribute__((weak, interrupt, nomips16))\r
+65: girq14_b3(void)\r
+66: {\r
+67: jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 3);\r
+68: }\r
+69: \r
+70: void __attribute__((weak, interrupt, nomips16))\r
+71: girq14_b4(void)\r
+72: {\r
+73: jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 4);\r
+74: }\r
+75: \r
+76: void __attribute__((weak, interrupt, nomips16))\r
+77: girq14_b5(void)\r
+78: {\r
+79: jtvic_dis_clr_source(MEC14xx_GIRQ14_ID, 5);\r
+80: }\r
+81: \r
+82: \r
+83: #endif\r
+84: \r
+85: /* end girq14.c */\r
+86: /** @}\r
+87: */\r
+88: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq13.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq13.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_trace_func.h"\r
+34: \r
+35: \r
+36: #if GIRQ13_DISAGG == 0\r
+37: \r
+38: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+39: girq13_isr(void)\r
+40: {\r
+BFD0782C E17C03BD RDPGPR SP, SP
+BFD07830 00FC036E MFC0 K1, EPC
+BFD07832 034C00FC INS A3, GP, 13, -12
+BFD07834 10FC034C MFC0 K0, SRSCtl
+BFD07836 4FF110FC ADDI A3, GP, 20465
+BFD07838 4FF1 ADDIU SP, SP, -32
+BFD0783A CB67 SW K1, 28(SP)
+BFD0783C 00FC036C MFC0 K1, Status
+BFD07840 CB46 SW K0, 24(SP)
+BFD07842 00FC034D MFC0 K0, Cause
+BFD07846 CB65 SW K1, 20(SP)
+BFD07848 5040035A SRL K0, K0, 10
+BFD0784A 037A5040 ORI V0, ZERO, 890
+BFD0784C 7A8C037A INS K1, K0, 10, 6
+BFD0784E 03607A8C ADDIUPC A1, 787296
+BFD07850 204C0360 INS K1, ZERO, 1, 4
+BFD07852 036C204C LWC2 V0, 876(T4)
+BFD07854 02FC036C MTC0 K1, Status
+BFD07858 C862 SW V1, 8(SP)
+BFD0785A C841 SW V0, 4(SP)
+BFD0785C 4866 LW V1, 24(SP)
+BFD0785E 2DB7 ANDI V1, V1, 0xF
+BFD07860 CBC3 SW S8, 12(SP)
+BFD07862 0FDD MOVE S8, SP
+41: JTVIC_GROUP_EN_CLR->w = (1ul<<5);\r
+BFD07864 BFFF41A2 LUI V0, 0xBFFF
+BFD07866 5042BFFF LDC1 F31, 20546(RA)
+BFD07868 C50C5042 ORI V0, V0, -15092
+BFD0786C EDA0 LI V1, 32
+BFD0786E E9A0 SW V1, 0(V0)
+42: }\r
+BFD07870 0FBE MOVE SP, S8
+BFD07872 4846 LW V0, 24(SP)
+BFD07874 2D27 ANDI V0, V0, 0xF
+BFD07876 4BC3 LW S8, 12(SP)
+BFD07878 4862 LW V1, 8(SP)
+BFD0787A 4841 LW V0, 4(SP)
+BFD0787C 477C0000 DI ZERO
+BFD07880 18000000 SLL ZERO, ZERO, 3
+BFD07882 4B471800 SB ZERO, 19271(ZERO)
+BFD07884 4B47 LW K0, 28(SP)
+BFD07886 4B65 LW K1, 20(SP)
+BFD07888 02FC034E MTC0 K0, EPC
+BFD0788C 4B46 LW K0, 24(SP)
+BFD0788E 4C11 ADDIU SP, SP, 32
+BFD07890 12FC034C MTC0 K0, SRSCtl
+BFD07892 03BD12FC ADDI S7, GP, 957
+BFD07894 F17C03BD WRPGPR SP, SP
+BFD07896 036CF17C JALX 0xBDF00DB0
+BFD07898 02FC036C MTC0 K1, Status
+BFD0789A 000002FC SLL S7, GP, 0
+BFD0789C F37C0000 ERET
+BFD0789E 03BDF37C JALX 0xBDF00EF4
+43: \r
+44: #else\r
+45: \r
+46: void __attribute__((weak, interrupt, nomips16))\r
+47: girq13_b0(void)\r
+48: {\r
+49: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 0);\r
+50: }\r
+51: \r
+52: void __attribute__((weak, interrupt, nomips16))\r
+53: girq13_b1(void)\r
+54: {\r
+55: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 1);\r
+56: }\r
+57: \r
+58: void __attribute__((weak, interrupt, nomips16))\r
+59: girq13_b2(void)\r
+60: {\r
+61: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 2);\r
+62: }\r
+63: \r
+64: void __attribute__((weak, interrupt, nomips16))\r
+65: girq13_b3(void)\r
+66: {\r
+67: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 3);\r
+68: }\r
+69: \r
+70: void __attribute__((weak, interrupt, nomips16))\r
+71: girq13_b4(void)\r
+72: {\r
+73: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 4);\r
+74: }\r
+75: \r
+76: void __attribute__((weak, interrupt, nomips16))\r
+77: girq13_b5(void)\r
+78: {\r
+79: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 5);\r
+80: }\r
+81: \r
+82: void __attribute__((weak, interrupt, nomips16))\r
+83: girq13_b6(void)\r
+84: {\r
+85: jtvic_dis_clr_source(MEC14xx_GIRQ13_ID, 6);\r
+86: }\r
+87: \r
+88: #endif\r
+89: \r
+90: /* end girq13.c */\r
+91: /** @}\r
+92: */\r
+93: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq12.c ----
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq12.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: \r
+29: #include "appcfg.h"\r
+30: #include "platform.h"\r
+31: #include "MEC14xx/mec14xx.h"\r
+32: #include "MEC14xx/mec14xx_girqs.h"\r
+33: #include "MEC14xx/mec14xx_gpio.h"\r
+34: #include "MEC14xx/mec14xx_trace_func.h"\r
+35: \r
+36: \r
+37: #if GIRQ12_DISAGG == 0\r
+38: \r
+39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+40: girq12_isr(void)\r
+41: {\r
+BFD077B8 E17C03BD RDPGPR SP, SP
+BFD077BC 00FC036E MFC0 K1, EPC
+BFD077BE 034C00FC INS A3, GP, 13, -12
+BFD077C0 10FC034C MFC0 K0, SRSCtl
+BFD077C2 4FF110FC ADDI A3, GP, 20465
+BFD077C4 4FF1 ADDIU SP, SP, -32
+BFD077C6 CB67 SW K1, 28(SP)
+BFD077C8 00FC036C MFC0 K1, Status
+BFD077CC CB46 SW K0, 24(SP)
+BFD077CE 00FC034D MFC0 K0, Cause
+BFD077D2 CB65 SW K1, 20(SP)
+BFD077D4 5040035A SRL K0, K0, 10
+BFD077D6 037A5040 ORI V0, ZERO, 890
+BFD077D8 7A8C037A INS K1, K0, 10, 6
+BFD077DA 03607A8C ADDIUPC A1, 787296
+BFD077DC 204C0360 INS K1, ZERO, 1, 4
+BFD077DE 036C204C LWC2 V0, 876(T4)
+BFD077E0 02FC036C MTC0 K1, Status
+BFD077E4 C862 SW V1, 8(SP)
+BFD077E6 C841 SW V0, 4(SP)
+BFD077E8 4866 LW V1, 24(SP)
+BFD077EA 2DB7 ANDI V1, V1, 0xF
+BFD077EC CBC3 SW S8, 12(SP)
+BFD077EE 0FDD MOVE S8, SP
+42: JTVIC_GROUP_EN_CLR->w = (1ul<<4);\r
+BFD077F0 BFFF41A2 LUI V0, 0xBFFF
+BFD077F2 5042BFFF LDC1 F31, 20546(RA)
+BFD077F4 C50C5042 ORI V0, V0, -15092
+BFD077F8 ED90 LI V1, 16
+BFD077FA E9A0 SW V1, 0(V0)
+43: }\r
+BFD077FC 0FBE MOVE SP, S8
+BFD077FE 4846 LW V0, 24(SP)
+BFD07800 2D27 ANDI V0, V0, 0xF
+BFD07802 4BC3 LW S8, 12(SP)
+BFD07804 4862 LW V1, 8(SP)
+BFD07806 4841 LW V0, 4(SP)
+BFD07808 477C0000 DI ZERO
+BFD0780C 18000000 SLL ZERO, ZERO, 3
+BFD0780E 4B471800 SB ZERO, 19271(ZERO)
+BFD07810 4B47 LW K0, 28(SP)
+BFD07812 4B65 LW K1, 20(SP)
+BFD07814 02FC034E MTC0 K0, EPC
+BFD07818 4B46 LW K0, 24(SP)
+BFD0781A 4C11 ADDIU SP, SP, 32
+BFD0781C 12FC034C MTC0 K0, SRSCtl
+BFD0781E 03BD12FC ADDI S7, GP, 957
+BFD07820 F17C03BD WRPGPR SP, SP
+BFD07822 036CF17C JALX 0xBDF00DB0
+BFD07824 02FC036C MTC0 K1, Status
+BFD07826 000002FC SLL S7, GP, 0
+BFD07828 F37C0000 ERET
+BFD0782A 03BDF37C JALX 0xBDF00EF4
+44: \r
+45: #else\r
+46: \r
+47: void __attribute__((weak, interrupt, nomips16))\r
+48: girq12_b0(void)\r
+49: {\r
+50: jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 0);\r
+51: }\r
+52: \r
+53: void __attribute__((weak, interrupt, nomips16))\r
+54: girq12_b1(void)\r
+55: {\r
+56: jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 1);\r
+57: }\r
+58: \r
+59: void __attribute__((weak, interrupt, nomips16))\r
+60: girq12_b2(void)\r
+61: {\r
+62: jtvic_dis_clr_source(MEC14xx_GIRQ12_ID, 2);\r
+63: }\r
+64: \r
+65: #endif\r
+66: \r
+67: /* end girq12.c */\r
+68: /** @}\r
+69: */\r
+70: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq11.c ----
+1: /*****************************************************************************\r
+2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq11.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: \r
+29: #include "appcfg.h"\r
+30: #include "platform.h"\r
+31: #include "MEC14xx/mec14xx.h"\r
+32: #include "MEC14xx/mec14xx_girqs.h"\r
+33: #include "MEC14xx/mec14xx_gpio.h"\r
+34: #include "MEC14xx/mec14xx_trace_func.h"\r
+35: \r
+36: \r
+37: #if GIRQ11_DISAGG == 0\r
+38: \r
+39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+40: girq11_isr(void)\r
+41: {\r
+BFD07744 E17C03BD RDPGPR SP, SP
+BFD07748 00FC036E MFC0 K1, EPC
+BFD0774A 034C00FC INS A3, GP, 13, -12
+BFD0774C 10FC034C MFC0 K0, SRSCtl
+BFD0774E 4FF110FC ADDI A3, GP, 20465
+BFD07750 4FF1 ADDIU SP, SP, -32
+BFD07752 CB67 SW K1, 28(SP)
+BFD07754 00FC036C MFC0 K1, Status
+BFD07758 CB46 SW K0, 24(SP)
+BFD0775A 00FC034D MFC0 K0, Cause
+BFD0775E CB65 SW K1, 20(SP)
+BFD07760 5040035A SRL K0, K0, 10
+BFD07762 037A5040 ORI V0, ZERO, 890
+BFD07764 7A8C037A INS K1, K0, 10, 6
+BFD07766 03607A8C ADDIUPC A1, 787296
+BFD07768 204C0360 INS K1, ZERO, 1, 4
+BFD0776A 036C204C LWC2 V0, 876(T4)
+BFD0776C 02FC036C MTC0 K1, Status
+BFD07770 C862 SW V1, 8(SP)
+BFD07772 C841 SW V0, 4(SP)
+BFD07774 4866 LW V1, 24(SP)
+BFD07776 2DB7 ANDI V1, V1, 0xF
+BFD07778 CBC3 SW S8, 12(SP)
+BFD0777A 0FDD MOVE S8, SP
+42: JTVIC_GROUP_EN_CLR->w = (1ul<<3);\r
+BFD0777C BFFF41A2 LUI V0, 0xBFFF
+BFD0777E 5042BFFF LDC1 F31, 20546(RA)
+BFD07780 C50C5042 ORI V0, V0, -15092
+BFD07784 ED88 LI V1, 8
+BFD07786 E9A0 SW V1, 0(V0)
+43: }\r
+BFD07788 0FBE MOVE SP, S8
+BFD0778A 4846 LW V0, 24(SP)
+BFD0778C 2D27 ANDI V0, V0, 0xF
+BFD0778E 4BC3 LW S8, 12(SP)
+BFD07790 4862 LW V1, 8(SP)
+BFD07792 4841 LW V0, 4(SP)
+BFD07794 477C0000 DI ZERO
+BFD07798 18000000 SLL ZERO, ZERO, 3
+BFD0779A 4B471800 SB ZERO, 19271(ZERO)
+BFD0779C 4B47 LW K0, 28(SP)
+BFD0779E 4B65 LW K1, 20(SP)
+BFD077A0 02FC034E MTC0 K0, EPC
+BFD077A4 4B46 LW K0, 24(SP)
+BFD077A6 4C11 ADDIU SP, SP, 32
+BFD077A8 12FC034C MTC0 K0, SRSCtl
+BFD077AA 03BD12FC ADDI S7, GP, 957
+BFD077AC F17C03BD WRPGPR SP, SP
+BFD077AE 036CF17C JALX 0xBDF00DB0
+BFD077B0 02FC036C MTC0 K1, Status
+BFD077B2 000002FC SLL S7, GP, 0
+BFD077B4 F37C0000 ERET
+BFD077B6 03BDF37C JALX 0xBDF00EF4
+44: \r
+45: #else\r
+46: \r
+47: void __attribute__((weak, interrupt, nomips16))\r
+48: girq11_b0(void)\r
+49: {\r
+50: return;\r
+51: }\r
+52: \r
+53: void __attribute__((weak, interrupt, nomips16))\r
+54: girq11_b1(void)\r
+55: {\r
+56: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 1, JTVIC_CLR_SRC);\r
+57: }\r
+58: \r
+59: void __attribute__((weak, interrupt, nomips16))\r
+60: girq11_b2(void)\r
+61: {\r
+62: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 2, JTVIC_CLR_SRC);\r
+63: }\r
+64: \r
+65: void __attribute__((weak, interrupt, nomips16))\r
+66: girq11_b3(void)\r
+67: {\r
+68: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 3, JTVIC_CLR_SRC);\r
+69: }\r
+70: \r
+71: void __attribute__((weak, interrupt, nomips16))\r
+72: girq11_b4(void)\r
+73: {\r
+74: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 4, JTVIC_CLR_SRC);\r
+75: }\r
+76: \r
+77: void __attribute__((weak, interrupt, nomips16))\r
+78: girq11_b5(void)\r
+79: {\r
+80: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 5, JTVIC_CLR_SRC);\r
+81: }\r
+82: \r
+83: void __attribute__((weak, interrupt, nomips16))\r
+84: girq11_b6(void)\r
+85: {\r
+86: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 6, JTVIC_CLR_SRC);\r
+87: }\r
+88: \r
+89: void __attribute__((weak, interrupt, nomips16))\r
+90: girq11_b7(void)\r
+91: {\r
+92: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 7, JTVIC_CLR_SRC);\r
+93: }\r
+94: \r
+95: void __attribute__((weak, interrupt, nomips16))\r
+96: girq11_b8(void)\r
+97: {\r
+98: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 8, JTVIC_CLR_SRC);\r
+99: }\r
+100: \r
+101: void __attribute__((weak, interrupt, nomips16))\r
+102: girq11_b9(void)\r
+103: {\r
+104: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 9, JTVIC_CLR_SRC);\r
+105: }\r
+106: \r
+107: void __attribute__((weak, interrupt, nomips16))\r
+108: girq11_b10(void)\r
+109: {\r
+110: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 10, JTVIC_CLR_SRC);\r
+111: }\r
+112: \r
+113: void __attribute__((weak, interrupt, nomips16))\r
+114: girq11_b11(void)\r
+115: {\r
+116: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 11, JTVIC_CLR_SRC);\r
+117: }\r
+118: \r
+119: void __attribute__((weak, interrupt, nomips16))\r
+120: girq11_b12(void)\r
+121: {\r
+122: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 12, JTVIC_CLR_SRC);\r
+123: }\r
+124: \r
+125: void __attribute__((weak, interrupt, nomips16))\r
+126: girq11_b13(void)\r
+127: {\r
+128: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 13, JTVIC_CLR_SRC);\r
+129: }\r
+130: \r
+131: void __attribute__((weak, interrupt, nomips16))\r
+132: girq11_b14(void)\r
+133: {\r
+134: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 14, JTVIC_CLR_SRC);\r
+135: }\r
+136: \r
+137: void __attribute__((weak, interrupt, nomips16))\r
+138: girq11_b15(void)\r
+139: {\r
+140: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 15, JTVIC_CLR_SRC);\r
+141: }\r
+142: \r
+143: void __attribute__((weak, interrupt, nomips16))\r
+144: girq11_b16(void)\r
+145: {\r
+146: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 16, JTVIC_CLR_SRC);\r
+147: }\r
+148: \r
+149: void __attribute__((weak, interrupt, nomips16))\r
+150: girq11_b17(void)\r
+151: {\r
+152: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 17, JTVIC_CLR_SRC);\r
+153: }\r
+154: \r
+155: void __attribute__((weak, interrupt, nomips16))\r
+156: girq11_b18(void)\r
+157: {\r
+158: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 18, JTVIC_CLR_SRC);\r
+159: }\r
+160: \r
+161: void __attribute__((weak, interrupt, nomips16))\r
+162: girq11_b19(void)\r
+163: {\r
+164: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 19, JTVIC_CLR_SRC);\r
+165: }\r
+166: \r
+167: void __attribute__((weak, interrupt, nomips16))\r
+168: girq11_b20(void)\r
+169: {\r
+170: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 20, JTVIC_CLR_SRC);\r
+171: }\r
+172: \r
+173: void __attribute__((weak, interrupt, nomips16))\r
+174: girq11_b21(void)\r
+175: {\r
+176: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 21, JTVIC_CLR_SRC);\r
+177: }\r
+178: \r
+179: void __attribute__((weak, interrupt, nomips16))\r
+180: girq11_b22(void)\r
+181: {\r
+182: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 22, JTVIC_CLR_SRC);\r
+183: }\r
+184: \r
+185: void __attribute__((weak, interrupt, nomips16))\r
+186: girq11_b23(void)\r
+187: {\r
+188: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 23, JTVIC_CLR_SRC);\r
+189: }\r
+190: \r
+191: void __attribute__((weak, interrupt, nomips16))\r
+192: girq11_b24(void)\r
+193: {\r
+194: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 24, JTVIC_CLR_SRC);\r
+195: }\r
+196: \r
+197: void __attribute__((weak, interrupt, nomips16))\r
+198: girq11_b25(void)\r
+199: {\r
+200: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 25, JTVIC_CLR_SRC);\r
+201: }\r
+202: \r
+203: void __attribute__((weak, interrupt, nomips16))\r
+204: girq11_b26(void)\r
+205: {\r
+206: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 26, JTVIC_CLR_SRC);\r
+207: }\r
+208: \r
+209: void __attribute__((weak, interrupt, nomips16))\r
+210: girq11_b27(void)\r
+211: {\r
+212: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 27, JTVIC_CLR_SRC);\r
+213: }\r
+214: \r
+215: void __attribute__((weak, interrupt, nomips16))\r
+216: girq11_b28(void)\r
+217: {\r
+218: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 28, JTVIC_CLR_SRC);\r
+219: }\r
+220: \r
+221: void __attribute__((weak, interrupt, nomips16))\r
+222: girq11_b29(void)\r
+223: {\r
+224: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 29, JTVIC_CLR_SRC);\r
+225: }\r
+226: \r
+227: void __attribute__((weak, interrupt, nomips16))\r
+228: girq11_b30(void)\r
+229: {\r
+230: jtvic_dis_clr_source(MEC14xx_GIRQ11_ID, 30, JTVIC_CLR_SRC);\r
+231: }\r
+232: \r
+233: #endif\r
+234: \r
+235: /* end girq11.c */\r
+236: /** @}\r
+237: */\r
+238: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq10.c ----
+1: /*****************************************************************************\r
+2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq10.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: \r
+29: #include "appcfg.h"\r
+30: #include "platform.h"\r
+31: #include "MEC14xx/mec14xx.h"\r
+32: #include "MEC14xx/mec14xx_girqs.h"\r
+33: #include "MEC14xx/mec14xx_gpio.h"\r
+34: #include "MEC14xx/mec14xx_trace_func.h"\r
+35: \r
+36: \r
+37: #if GIRQ10_DISAGG == 0\r
+38: \r
+39: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+40: girq10_isr(void)\r
+41: {\r
+BFD076D0 E17C03BD RDPGPR SP, SP
+BFD076D4 00FC036E MFC0 K1, EPC
+BFD076D6 034C00FC INS A3, GP, 13, -12
+BFD076D8 10FC034C MFC0 K0, SRSCtl
+BFD076DA 4FF110FC ADDI A3, GP, 20465
+BFD076DC 4FF1 ADDIU SP, SP, -32
+BFD076DE CB67 SW K1, 28(SP)
+BFD076E0 00FC036C MFC0 K1, Status
+BFD076E4 CB46 SW K0, 24(SP)
+BFD076E6 00FC034D MFC0 K0, Cause
+BFD076EA CB65 SW K1, 20(SP)
+BFD076EC 5040035A SRL K0, K0, 10
+BFD076EE 037A5040 ORI V0, ZERO, 890
+BFD076F0 7A8C037A INS K1, K0, 10, 6
+BFD076F2 03607A8C ADDIUPC A1, 787296
+BFD076F4 204C0360 INS K1, ZERO, 1, 4
+BFD076F6 036C204C LWC2 V0, 876(T4)
+BFD076F8 02FC036C MTC0 K1, Status
+BFD076FC C862 SW V1, 8(SP)
+BFD076FE C841 SW V0, 4(SP)
+BFD07700 4866 LW V1, 24(SP)
+BFD07702 2DB7 ANDI V1, V1, 0xF
+BFD07704 CBC3 SW S8, 12(SP)
+BFD07706 0FDD MOVE S8, SP
+42: JTVIC_GROUP_EN_CLR->w = (1ul<<2);\r
+BFD07708 BFFF41A2 LUI V0, 0xBFFF
+BFD0770A 5042BFFF LDC1 F31, 20546(RA)
+BFD0770C C50C5042 ORI V0, V0, -15092
+BFD07710 ED84 LI V1, 4
+BFD07712 E9A0 SW V1, 0(V0)
+43: }\r
+BFD07714 0FBE MOVE SP, S8
+BFD07716 4846 LW V0, 24(SP)
+BFD07718 2D27 ANDI V0, V0, 0xF
+BFD0771A 4BC3 LW S8, 12(SP)
+BFD0771C 4862 LW V1, 8(SP)
+BFD0771E 4841 LW V0, 4(SP)
+BFD07720 477C0000 DI ZERO
+BFD07724 18000000 SLL ZERO, ZERO, 3
+BFD07726 4B471800 SB ZERO, 19271(ZERO)
+BFD07728 4B47 LW K0, 28(SP)
+BFD0772A 4B65 LW K1, 20(SP)
+BFD0772C 02FC034E MTC0 K0, EPC
+BFD07730 4B46 LW K0, 24(SP)
+BFD07732 4C11 ADDIU SP, SP, 32
+BFD07734 12FC034C MTC0 K0, SRSCtl
+BFD07736 03BD12FC ADDI S7, GP, 957
+BFD07738 F17C03BD WRPGPR SP, SP
+BFD0773A 036CF17C JALX 0xBDF00DB0
+BFD0773C 02FC036C MTC0 K1, Status
+BFD0773E 000002FC SLL S7, GP, 0
+BFD07740 F37C0000 ERET
+BFD07742 03BDF37C JALX 0xBDF00EF4
+44: \r
+45: #else\r
+46: \r
+47: void __attribute__((weak, interrupt, nomips16))\r
+48: girq10_b0(void)\r
+49: {\r
+50: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 0, JTVIC_CLR_SRC);\r
+51: }\r
+52: \r
+53: void __attribute__((weak, interrupt, nomips16))\r
+54: girq10_b1(void)\r
+55: {\r
+56: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 1, JTVIC_CLR_SRC);\r
+57: }\r
+58: \r
+59: void __attribute__((weak, interrupt, nomips16))\r
+60: girq10_b2(void)\r
+61: {\r
+62: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 2, JTVIC_CLR_SRC);\r
+63: }\r
+64: \r
+65: void __attribute__((weak, interrupt, nomips16))\r
+66: girq10_b3(void)\r
+67: {\r
+68: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 3, JTVIC_CLR_SRC);\r
+69: }\r
+70: \r
+71: void __attribute__((weak, interrupt, nomips16))\r
+72: girq10_b4(void)\r
+73: {\r
+74: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 4, JTVIC_CLR_SRC);\r
+75: }\r
+76: \r
+77: void __attribute__((weak, interrupt, nomips16))\r
+78: girq10_b5(void)\r
+79: {\r
+80: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 5, JTVIC_CLR_SRC);\r
+81: }\r
+82: \r
+83: void __attribute__((weak, interrupt, nomips16))\r
+84: girq10_b6(void)\r
+85: {\r
+86: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 6, JTVIC_CLR_SRC);\r
+87: }\r
+88: \r
+89: void __attribute__((weak, interrupt, nomips16))\r
+90: girq10_b7(void)\r
+91: {\r
+92: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 7, JTVIC_CLR_SRC);\r
+93: }\r
+94: \r
+95: void __attribute__((weak, interrupt, nomips16))\r
+96: girq10_b8(void)\r
+97: {\r
+98: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 8, JTVIC_CLR_SRC);\r
+99: }\r
+100: \r
+101: void __attribute__((weak, interrupt, nomips16))\r
+102: girq10_b9(void)\r
+103: {\r
+104: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 9, JTVIC_CLR_SRC);\r
+105: }\r
+106: \r
+107: void __attribute__((weak, interrupt, nomips16))\r
+108: girq10_b10(void)\r
+109: {\r
+110: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 10, JTVIC_CLR_SRC);\r
+111: }\r
+112: \r
+113: void __attribute__((weak, interrupt, nomips16))\r
+114: girq10_b11(void)\r
+115: {\r
+116: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 11, JTVIC_CLR_SRC);\r
+117: }\r
+118: \r
+119: \r
+120: void __attribute__((weak, interrupt, nomips16))\r
+121: girq10_b12(void)\r
+122: {\r
+123: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 12, JTVIC_CLR_SRC);\r
+124: }\r
+125: \r
+126: void __attribute__((weak, interrupt, nomips16))\r
+127: girq10_b13(void)\r
+128: {\r
+129: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 13, JTVIC_CLR_SRC);\r
+130: }\r
+131: \r
+132: void __attribute__((weak, interrupt, nomips16))\r
+133: girq10_b14(void)\r
+134: {\r
+135: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 14, JTVIC_CLR_SRC);\r
+136: }\r
+137: \r
+138: void __attribute__((weak, interrupt, nomips16))\r
+139: girq10_b15(void)\r
+140: {\r
+141: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 15, JTVIC_CLR_SRC);\r
+142: }\r
+143: \r
+144: void __attribute__((weak, interrupt, nomips16))\r
+145: girq10_b16(void)\r
+146: {\r
+147: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 16, JTVIC_CLR_SRC);\r
+148: }\r
+149: \r
+150: void __attribute__((weak, interrupt, nomips16))\r
+151: girq10_b17(void)\r
+152: {\r
+153: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 17, JTVIC_CLR_SRC);\r
+154: }\r
+155: \r
+156: void __attribute__((weak, interrupt, nomips16))\r
+157: girq10_b18(void)\r
+158: {\r
+159: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 18, JTVIC_CLR_SRC);\r
+160: }\r
+161: \r
+162: void __attribute__((weak, interrupt, nomips16))\r
+163: girq10_b19(void)\r
+164: {\r
+165: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 19, JTVIC_CLR_SRC);\r
+166: }\r
+167: \r
+168: void __attribute__((weak, interrupt, nomips16))\r
+169: girq10_b20(void)\r
+170: {\r
+171: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 20, JTVIC_CLR_SRC);\r
+172: }\r
+173: \r
+174: void __attribute__((weak, interrupt, nomips16))\r
+175: girq10_b21(void)\r
+176: {\r
+177: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 21, JTVIC_CLR_SRC);\r
+178: }\r
+179: \r
+180: void __attribute__((weak, interrupt, nomips16))\r
+181: girq10_b22(void)\r
+182: {\r
+183: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 22, JTVIC_CLR_SRC);\r
+184: }\r
+185: \r
+186: void __attribute__((weak, interrupt, nomips16))\r
+187: girq10_b23(void)\r
+188: {\r
+189: jtvic_dis_clr_source(MEC14xx_GIRQ10_ID, 23, JTVIC_CLR_SRC);\r
+190: }\r
+191: \r
+192: #endif\r
+193: \r
+194: /* end girq10.c */\r
+195: /** @}\r
+196: */\r
+197: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq09.c ----
+1: /*****************************************************************************\r
+2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq09.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: \r
+29: \r
+30: #include "appcfg.h"\r
+31: #include "platform.h"\r
+32: #include "MEC14xx/mec14xx.h"\r
+33: #include "MEC14xx/mec14xx_girqs.h"\r
+34: #include "MEC14xx/mec14xx_gpio.h"\r
+35: #include "MEC14xx/mec14xx_trace_func.h"\r
+36: \r
+37: \r
+38: #if GIRQ09_DISAGG == 0\r
+39: \r
+40: /*\r
+41: * Aggregated mode handler, must handle all enabled \r
+42: * GIRQ08 sources. \r
+43: */\r
+44: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+45: girq09_isr( void )\r
+46: {\r
+BFD0765C E17C03BD RDPGPR SP, SP
+BFD07660 00FC036E MFC0 K1, EPC
+BFD07662 034C00FC INS A3, GP, 13, -12
+BFD07664 10FC034C MFC0 K0, SRSCtl
+BFD07666 4FF110FC ADDI A3, GP, 20465
+BFD07668 4FF1 ADDIU SP, SP, -32
+BFD0766A CB67 SW K1, 28(SP)
+BFD0766C 00FC036C MFC0 K1, Status
+BFD07670 CB46 SW K0, 24(SP)
+BFD07672 00FC034D MFC0 K0, Cause
+BFD07676 CB65 SW K1, 20(SP)
+BFD07678 5040035A SRL K0, K0, 10
+BFD0767A 037A5040 ORI V0, ZERO, 890
+BFD0767C 7A8C037A INS K1, K0, 10, 6
+BFD0767E 03607A8C ADDIUPC A1, 787296
+BFD07680 204C0360 INS K1, ZERO, 1, 4
+BFD07682 036C204C LWC2 V0, 876(T4)
+BFD07684 02FC036C MTC0 K1, Status
+BFD07688 C862 SW V1, 8(SP)
+BFD0768A C841 SW V0, 4(SP)
+BFD0768C 4866 LW V1, 24(SP)
+BFD0768E 2DB7 ANDI V1, V1, 0xF
+BFD07690 CBC3 SW S8, 12(SP)
+BFD07692 0FDD MOVE S8, SP
+47: JTVIC_GROUP_EN_CLR->w = (1ul<<1);\r
+BFD07694 BFFF41A2 LUI V0, 0xBFFF
+BFD07696 5042BFFF LDC1 F31, 20546(RA)
+BFD07698 C50C5042 ORI V0, V0, -15092
+BFD0769C ED82 LI V1, 2
+BFD0769E E9A0 SW V1, 0(V0)
+48: }\r
+BFD076A0 0FBE MOVE SP, S8
+BFD076A2 4846 LW V0, 24(SP)
+BFD076A4 2D27 ANDI V0, V0, 0xF
+BFD076A6 4BC3 LW S8, 12(SP)
+BFD076A8 4862 LW V1, 8(SP)
+BFD076AA 4841 LW V0, 4(SP)
+BFD076AC 477C0000 DI ZERO
+BFD076B0 18000000 SLL ZERO, ZERO, 3
+BFD076B2 4B471800 SB ZERO, 19271(ZERO)
+BFD076B4 4B47 LW K0, 28(SP)
+BFD076B6 4B65 LW K1, 20(SP)
+BFD076B8 02FC034E MTC0 K0, EPC
+BFD076BC 4B46 LW K0, 24(SP)
+BFD076BE 4C11 ADDIU SP, SP, 32
+BFD076C0 12FC034C MTC0 K0, SRSCtl
+BFD076C2 03BD12FC ADDI S7, GP, 957
+BFD076C4 F17C03BD WRPGPR SP, SP
+BFD076C6 036CF17C JALX 0xBDF00DB0
+BFD076C8 02FC036C MTC0 K1, Status
+BFD076CA 000002FC SLL S7, GP, 0
+BFD076CC F37C0000 ERET
+BFD076CE 03BDF37C JALX 0xBDF00EF4
+49: \r
+50: #else\r
+51: \r
+52: void __attribute__((weak, interrupt, nomips16))\r
+53: girq09_b0(void)\r
+54: {\r
+55: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 0);\r
+56: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 0);\r
+57: }\r
+58: \r
+59: void __attribute__((weak, interrupt, nomips16))\r
+60: girq09_b1(void)\r
+61: {\r
+62: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 1);\r
+63: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 1);\r
+64: }\r
+65: \r
+66: void __attribute__((weak, interrupt, nomips16))\r
+67: girq09_b2(void)\r
+68: {\r
+69: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 2);\r
+70: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 2);\r
+71: }\r
+72: \r
+73: void __attribute__((weak, interrupt, nomips16))\r
+74: girq09_b3(void)\r
+75: {\r
+76: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 3);\r
+77: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 3);\r
+78: }\r
+79: \r
+80: void __attribute__((weak, interrupt, nomips16))\r
+81: girq09_b4(void)\r
+82: {\r
+83: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 4);\r
+84: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 4);\r
+85: }\r
+86: \r
+87: void __attribute__((weak, interrupt, nomips16))\r
+88: girq09_b5(void)\r
+89: {\r
+90: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 5);\r
+91: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 5);\r
+92: }\r
+93: \r
+94: void __attribute__((weak, interrupt, nomips16))\r
+95: girq09_b6(void)\r
+96: {\r
+97: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 6);\r
+98: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 6);\r
+99: }\r
+100: \r
+101: void __attribute__((weak, interrupt, nomips16))\r
+102: girq09_b7(void)\r
+103: {\r
+104: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 7);\r
+105: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 7);\r
+106: }\r
+107: \r
+108: void __attribute__((weak, interrupt, nomips16))\r
+109: girq09_b8(void)\r
+110: {\r
+111: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 8);\r
+112: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 8);\r
+113: }\r
+114: \r
+115: void __attribute__((weak, interrupt, nomips16))\r
+116: girq09_b9(void)\r
+117: {\r
+118: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 9);\r
+119: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 9);\r
+120: }\r
+121: \r
+122: void __attribute__((weak, interrupt, nomips16))\r
+123: girq09_b10(void)\r
+124: {\r
+125: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 10);\r
+126: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 10);\r
+127: }\r
+128: \r
+129: void __attribute__((weak, interrupt, nomips16))\r
+130: girq09_b11(void)\r
+131: {\r
+132: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 11);\r
+133: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 11);\r
+134: }\r
+135: \r
+136: void __attribute__((weak, interrupt, nomips16))\r
+137: girq09_b12(void)\r
+138: {\r
+139: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 12);\r
+140: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 12);\r
+141: }\r
+142: \r
+143: void __attribute__((weak, interrupt, nomips16))\r
+144: girq09_b13(void)\r
+145: {\r
+146: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 13);\r
+147: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 13);\r
+148: }\r
+149: \r
+150: void __attribute__((weak, interrupt, nomips16))\r
+151: girq09_b14(void)\r
+152: {\r
+153: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 14);\r
+154: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 14);\r
+155: }\r
+156: \r
+157: void __attribute__((weak, interrupt, nomips16))\r
+158: girq09_b15(void)\r
+159: {\r
+160: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 15);\r
+161: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 15);\r
+162: }\r
+163: \r
+164: void __attribute__((weak, interrupt, nomips16))\r
+165: girq09_b16(void)\r
+166: {\r
+167: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 16);\r
+168: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 16);\r
+169: }\r
+170: \r
+171: void __attribute__((weak, interrupt, nomips16))\r
+172: girq09_b17(void)\r
+173: {\r
+174: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 17);\r
+175: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 17);\r
+176: }\r
+177: \r
+178: void __attribute__((weak, interrupt, nomips16))\r
+179: girq09_b18(void)\r
+180: {\r
+181: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 18);\r
+182: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 18);\r
+183: }\r
+184: \r
+185: void __attribute__((weak, interrupt, nomips16))\r
+186: girq09_b19(void)\r
+187: {\r
+188: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 19);\r
+189: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 19);\r
+190: }\r
+191: \r
+192: void __attribute__((weak, interrupt, nomips16))\r
+193: girq09_b20(void)\r
+194: {\r
+195: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 20);\r
+196: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 20);\r
+197: }\r
+198: \r
+199: void __attribute__((weak, interrupt, nomips16))\r
+200: girq09_b21(void)\r
+201: {\r
+202: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 21);\r
+203: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 21);\r
+204: }\r
+205: \r
+206: void __attribute__((weak, interrupt, nomips16))\r
+207: girq09_b22(void)\r
+208: {\r
+209: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 22);\r
+210: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 22);\r
+211: }\r
+212: \r
+213: void __attribute__((weak, interrupt, nomips16))\r
+214: girq09_b23(void)\r
+215: {\r
+216: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 23);\r
+217: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 23);\r
+218: }\r
+219: \r
+220: void __attribute__((weak, interrupt, nomips16))\r
+221: girq09_b24(void)\r
+222: {\r
+223: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 24);\r
+224: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 24);\r
+225: }\r
+226: \r
+227: void __attribute__((weak, interrupt, nomips16))\r
+228: girq09_b25(void)\r
+229: {\r
+230: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 25);\r
+231: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 25);\r
+232: }\r
+233: \r
+234: void __attribute__((weak, interrupt, nomips16))\r
+235: girq09_b26(void)\r
+236: {\r
+237: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 26);\r
+238: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 26);\r
+239: }\r
+240: \r
+241: void __attribute__((weak, interrupt, nomips16))\r
+242: girq09_b27(void)\r
+243: {\r
+244: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 27);\r
+245: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 27);\r
+246: }\r
+247: \r
+248: void __attribute__((weak, interrupt, nomips16))\r
+249: girq09_b28(void)\r
+250: {\r
+251: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 28);\r
+252: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 28);\r
+253: }\r
+254: \r
+255: void __attribute__((weak, interrupt, nomips16))\r
+256: girq09_b29(void)\r
+257: {\r
+258: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 29);\r
+259: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 29);\r
+260: }\r
+261: \r
+262: void __attribute__((weak, interrupt, nomips16))\r
+263: girq09_b30(void)\r
+264: {\r
+265: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].EN_CLR = (1ul << 30);\r
+266: JTVIC_GIRQ->REGS[MEC14xx_GIRQ09_ID].SOURCE = (1ul << 30);\r
+267: }\r
+268: \r
+269: \r
+270: #endif\r
+271: \r
+272: /* end girq09.c */\r
+273: /** @}\r
+274: */\r
+275: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/interrupts/girq08.c ----
+1: /*****************************************************************************\r
+2: * Copyright 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file girq08.c\r
+22: *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32\r
+23: */\r
+24: /** @defgroup MEC14xx ISR\r
+25: * @{\r
+26: */\r
+27: \r
+28: #include "appcfg.h"\r
+29: #include "platform.h"\r
+30: #include "MEC14xx/mec14xx.h"\r
+31: #include "MEC14xx/mec14xx_girqs.h"\r
+32: #include "MEC14xx/mec14xx_gpio.h"\r
+33: #include "MEC14xx/mec14xx_trace_func.h"\r
+34: \r
+35: \r
+36: \r
+37: #if GIRQ08_DISAGG == 0\r
+38: \r
+39: /*\r
+40: * Aggregated mode handler, must handle all enabled \r
+41: * GIRQ08 sources. \r
+42: */\r
+43: void __attribute__((weak, interrupt, nomips16, section(".girqs")))\r
+44: girq08_isr( void )\r
+45: {\r
+BFD075E8 E17C03BD RDPGPR SP, SP
+BFD075EC 00FC036E MFC0 K1, EPC
+BFD075EE 034C00FC INS A3, GP, 13, -12
+BFD075F0 10FC034C MFC0 K0, SRSCtl
+BFD075F2 4FF110FC ADDI A3, GP, 20465
+BFD075F4 4FF1 ADDIU SP, SP, -32
+BFD075F6 CB67 SW K1, 28(SP)
+BFD075F8 00FC036C MFC0 K1, Status
+BFD075FC CB46 SW K0, 24(SP)
+BFD075FE 00FC034D MFC0 K0, Cause
+BFD07602 CB65 SW K1, 20(SP)
+BFD07604 5040035A SRL K0, K0, 10
+BFD07606 037A5040 ORI V0, ZERO, 890
+BFD07608 7A8C037A INS K1, K0, 10, 6
+BFD0760A 03607A8C ADDIUPC A1, 787296
+BFD0760C 204C0360 INS K1, ZERO, 1, 4
+BFD0760E 036C204C LWC2 V0, 876(T4)
+BFD07610 02FC036C MTC0 K1, Status
+BFD07614 C862 SW V1, 8(SP)
+BFD07616 C841 SW V0, 4(SP)
+BFD07618 4866 LW V1, 24(SP)
+BFD0761A 2DB7 ANDI V1, V1, 0xF
+BFD0761C CBC3 SW S8, 12(SP)
+BFD0761E 0FDD MOVE S8, SP
+46: JTVIC_GROUP_EN_CLR->w = (1ul<<0);\r
+BFD07620 BFFF41A2 LUI V0, 0xBFFF
+BFD07622 5042BFFF LDC1 F31, 20546(RA)
+BFD07624 C50C5042 ORI V0, V0, -15092
+BFD07628 ED81 LI V1, 1
+BFD0762A E9A0 SW V1, 0(V0)
+47: }\r
+BFD0762C 0FBE MOVE SP, S8
+BFD0762E 4846 LW V0, 24(SP)
+BFD07630 2D27 ANDI V0, V0, 0xF
+BFD07632 4BC3 LW S8, 12(SP)
+BFD07634 4862 LW V1, 8(SP)
+BFD07636 4841 LW V0, 4(SP)
+BFD07638 477C0000 DI ZERO
+BFD0763C 18000000 SLL ZERO, ZERO, 3
+BFD0763E 4B471800 SB ZERO, 19271(ZERO)
+BFD07640 4B47 LW K0, 28(SP)
+BFD07642 4B65 LW K1, 20(SP)
+BFD07644 02FC034E MTC0 K0, EPC
+BFD07648 4B46 LW K0, 24(SP)
+BFD0764A 4C11 ADDIU SP, SP, 32
+BFD0764C 12FC034C MTC0 K0, SRSCtl
+BFD0764E 03BD12FC ADDI S7, GP, 957
+BFD07650 F17C03BD WRPGPR SP, SP
+BFD07652 036CF17C JALX 0xBDF00DB0
+BFD07654 02FC036C MTC0 K1, Status
+BFD07656 000002FC SLL S7, GP, 0
+BFD07658 F37C0000 ERET
+BFD0765A 03BDF37C JALX 0xBDF00EF4
+48: \r
+49: #else\r
+50: \r
+51: /*\r
+52: * Disaggregated GIRQ08 subhandlers, one for each \r
+53: * source. Called by assembly language wrapper. \r
+54: */\r
+55: \r
+56: \r
+57: void __attribute__((weak, interrupt, nomips16))\r
+58: girq08_b0(void)\r
+59: {\r
+60: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 0);\r
+61: }\r
+62: \r
+63: \r
+64: void __attribute__((weak, interrupt, nomips16))\r
+65: girq08_b1(void)\r
+66: {\r
+67: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 1);\r
+68: }\r
+69: \r
+70: \r
+71: void __attribute__((weak, interrupt, nomips16))\r
+72: girq08_b2(void)\r
+73: {\r
+74: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 2);\r
+75: }\r
+76: \r
+77: \r
+78: void __attribute__((weak, interrupt, nomips16))\r
+79: girq08_b3(void)\r
+80: {\r
+81: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 3);\r
+82: }\r
+83: \r
+84: \r
+85: void __attribute__((weak, interrupt, nomips16))\r
+86: girq08_b4(void)\r
+87: {\r
+88: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 4);\r
+89: }\r
+90: \r
+91: \r
+92: void __attribute__((weak, interrupt, nomips16))\r
+93: girq08_b5(void)\r
+94: {\r
+95: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 5);\r
+96: }\r
+97: \r
+98: \r
+99: void __attribute__((weak, interrupt, nomips16))\r
+100: girq08_b6(void)\r
+101: {\r
+102: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 6);\r
+103: }\r
+104: \r
+105: \r
+106: void __attribute__((weak, interrupt, nomips16))\r
+107: girq08_b7(void)\r
+108: {\r
+109: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 7);\r
+110: }\r
+111: \r
+112: \r
+113: void __attribute__((weak, interrupt, nomips16))\r
+114: girq08_b8(void)\r
+115: {\r
+116: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 8);\r
+117: }\r
+118: \r
+119: \r
+120: void __attribute__((weak, interrupt, nomips16))\r
+121: girq08_b9(void)\r
+122: {\r
+123: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 9);\r
+124: }\r
+125: \r
+126: \r
+127: void __attribute__((weak, interrupt, nomips16))\r
+128: girq08_b10(void)\r
+129: {\r
+130: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 10);\r
+131: }\r
+132: \r
+133: \r
+134: void __attribute__((weak, interrupt, nomips16))\r
+135: girq08_b11(void)\r
+136: {\r
+137: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 11);\r
+138: }\r
+139: \r
+140: \r
+141: void __attribute__((weak, interrupt, nomips16))\r
+142: girq08_b12(void)\r
+143: {\r
+144: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 12);\r
+145: }\r
+146: \r
+147: \r
+148: void __attribute__((weak, interrupt, nomips16))\r
+149: girq08_b13(void)\r
+150: {\r
+151: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 13);\r
+152: }\r
+153: \r
+154: \r
+155: void __attribute__((weak, interrupt, nomips16))\r
+156: girq08_b14(void)\r
+157: {\r
+158: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 14);\r
+159: }\r
+160: \r
+161: \r
+162: void __attribute__((weak, interrupt, nomips16))\r
+163: girq08_b15(void)\r
+164: {\r
+165: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 15);\r
+166: }\r
+167: \r
+168: \r
+169: void __attribute__((weak, interrupt, nomips16))\r
+170: girq08_b16(void)\r
+171: {\r
+172: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 16);\r
+173: }\r
+174: \r
+175: \r
+176: void __attribute__((weak, interrupt, nomips16))\r
+177: girq08_b17(void)\r
+178: {\r
+179: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 17);\r
+180: }\r
+181: \r
+182: \r
+183: void __attribute__((weak, interrupt, nomips16))\r
+184: girq08_b18(void)\r
+185: {\r
+186: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 18);\r
+187: }\r
+188: \r
+189: \r
+190: void __attribute__((weak, interrupt, nomips16))\r
+191: girq08_b19(void)\r
+192: {\r
+193: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 19);\r
+194: }\r
+195: \r
+196: \r
+197: void __attribute__((weak, interrupt, nomips16))\r
+198: girq08_b20(void)\r
+199: {\r
+200: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 20);\r
+201: }\r
+202: \r
+203: \r
+204: void __attribute__((weak, interrupt, nomips16))\r
+205: girq08_b21(void)\r
+206: {\r
+207: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 21);\r
+208: }\r
+209: \r
+210: \r
+211: void __attribute__((weak, interrupt, nomips16))\r
+212: girq08_b22(void)\r
+213: {\r
+214: jtvic_dis_clr_source(MEC14xx_GIRQ08_ID, 22);\r
+215: }\r
+216: \r
+217: \r
+218: #endif\r
+219: \r
+220: \r
+221: /* end girq08.c */\r
+222: /** @}\r
+223: */\r
+224: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/mec14xx/exceptions/mplab/general_exception.c
+1: /*****************************************************************************\r
+2: * (c) 2014 Microchip Technology Inc. and its subsidiaries.\r
+3: * You may use this software and any derivatives exclusively with\r
+4: * Microchip products.\r
+5: * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+6: * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+7: * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+8: * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+9: * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+10: * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+11: * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+12: * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+13: * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+14: * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+15: * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+16: * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+17: * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+18: * OF THESE TERMS.\r
+19: *****************************************************************************/\r
+20: \r
+21: /** @file general_exception.c\r
+22: *MEC14xx General Exception Handler\r
+23: */\r
+24: /** @defgroup MEC14xx Exceptions\r
+25: * @{\r
+26: */\r
+27: \r
+28: \r
+29: #include "appcfg.h"\r
+30: #include "platform.h"\r
+31: #include "MEC14xx/mec14xx.h"\r
+32: #include "MEC14xx/mec14xx_trace_inline.h"\r
+33: \r
+34: typedef struct gen_except_capture\r
+35: {\r
+36: uint32_t stack_ptr;\r
+37: uint32_t cp0_status;\r
+38: uint32_t cp0_cause;\r
+39: uint32_t cp0_epc;\r
+40: uint32_t cp0_error_epc;\r
+41: uint32_t cp0_nexc;\r
+42: uint32_t cp0_nepc;\r
+43: uint32_t cp0_badvaddr;\r
+44: uint32_t ahb_err;\r
+45: } GEN_EXCEPT_CAPTURE;\r
+46: \r
+47: GEN_EXCEPT_CAPTURE gexc_cap;\r
+48: \r
+49: void \r
+50: __attribute__((nomips16, noreturn)) _general_exception_handler (void)\r
+51: {\r
+BFD00460 4FF9 ADDIU SP, SP, -16
+BFD00462 CBE3 SW RA, 12(SP)
+BFD00464 CBC2 SW S8, 8(SP)
+BFD00466 0FDD MOVE S8, SP
+52: /* \r
+53: * MEC14xx Application General Exception handler\r
+54: */\r
+55: uint32_t e;\r
+56: \r
+57: /* Get current Stack Pointer. Note: this is not SP at\r
+58: * exception. XC32 wraps _general_exception_handler in\r
+59: * assembly code which saves state resulting is a\r
+60: * modified SP. Wrapper allocates 88 bytes for context\r
+61: * save. Original SP = SPcurrent + 88.\r
+62: */\r
+63: __asm__ __volatile (\r
+BFD00468 0FFD MOVE RA, SP
+BFD0046A 0C00 NOP
+BFD0046C 0000FBFE SW RA, 0(S8)
+64: "move %0,$sp \n\t"\r
+65: "nop \n\t" \r
+66: :"=r" (e) \r
+67: ::);\r
+68: gexc_cap.stack_ptr = e;\r
+BFD00470 BFD241A2 LUI V0, 0xBFD2
+BFD00472 FC7EBFD2 LDC1 F30, -898(S2)
+BFD00474 0000FC7E LW V1, 0(S8)
+BFD00478 8134F862 SW V1, -32460(V0)
+69: \r
+70: gexc_cap.cp0_status = _CP0_GET_STATUS();\r
+BFD0047C 00FC006C MFC0 V1, Status
+BFD00480 BFD241A2 LUI V0, 0xBFD2
+BFD00482 3042BFD2 LDC1 F30, 12354(S2)
+BFD00484 81343042 ADDIU V0, V0, -32460
+BFD00488 E9A1 SW V1, 4(V0)
+71: gexc_cap.cp0_cause = _CP0_GET_CAUSE();\r
+BFD0048A 00FC006D MFC0 V1, Cause
+BFD0048E BFD241A2 LUI V0, 0xBFD2
+BFD00490 3042BFD2 LDC1 F30, 12354(S2)
+BFD00492 81343042 ADDIU V0, V0, -32460
+BFD00496 E9A2 SW V1, 8(V0)
+72: gexc_cap.cp0_epc = _CP0_GET_EPC();\r
+BFD00498 00FC006E MFC0 V1, EPC
+BFD0049C BFD241A2 LUI V0, 0xBFD2
+BFD0049E 3042BFD2 LDC1 F30, 12354(S2)
+BFD004A0 81343042 ADDIU V0, V0, -32460
+BFD004A4 E9A3 SW V1, 12(V0)
+73: gexc_cap.cp0_error_epc = _CP0_GET_ERROREPC();\r
+BFD004A6 00FC007E MFC0 V1, ErrorEPC
+BFD004AA BFD241A2 LUI V0, 0xBFD2
+BFD004AC 3042BFD2 LDC1 F30, 12354(S2)
+BFD004AE 81343042 ADDIU V0, V0, -32460
+BFD004B2 E9A4 SW V1, 16(V0)
+74: gexc_cap.cp0_nexc = _CP0_GET_NESTEDEXC();\r
+BFD004B4 10FC006D MFC0 V1, $13, 2
+BFD004B6 41A210FC ADDI A3, GP, 16802
+BFD004B8 BFD241A2 LUI V0, 0xBFD2
+BFD004BA 3042BFD2 LDC1 F30, 12354(S2)
+BFD004BC 81343042 ADDIU V0, V0, -32460
+BFD004C0 E9A5 SW V1, 20(V0)
+75: gexc_cap.cp0_nepc = _CP0_GET_NESTEDEPC();\r
+BFD004C2 08FC006E MFC0 V1, $14, 1
+BFD004C4 08FC LBU S1, 12(A3)
+BFD004C6 BFD241A2 LUI V0, 0xBFD2
+BFD004C8 3042BFD2 LDC1 F30, 12354(S2)
+BFD004CA 81343042 ADDIU V0, V0, -32460
+BFD004CE E9A6 SW V1, 24(V0)
+76: gexc_cap.cp0_badvaddr = _CP0_GET_BADVADDR();\r
+BFD004D0 00FC0068 MFC0 V1, BadVAddr
+BFD004D4 BFD241A2 LUI V0, 0xBFD2
+BFD004D6 3042BFD2 LDC1 F30, 12354(S2)
+BFD004D8 81343042 ADDIU V0, V0, -32460
+BFD004DC E9A7 SW V1, 28(V0)
+77: \r
+78: trace0(0, AP3GENEXCEPT, 0, "Application General Exception Handler (BEV=0)");\r
+79: TRACE11(601, AP3GENEXCEPT, 0, "Current SP = 0x%08x",gexc_cap.stack_ptr);\r
+BFD004DE A00041A2 LUI V0, 0xA000
+BFD004E2 8C005042 ORI V0, V0, -29696
+BFD004E4 8C00 BEQZ S0, 0xBFD004E6
+BFD004E6 FFFD3060 ADDIU V1, ZERO, -3
+BFD004E8 89A0FFFD LW RA, -30304(SP)
+BFD004EA 89A0 SB V1, 0(V0)
+BFD004EC A00041A2 LUI V0, 0xA000
+BFD004F0 8C005042 ORI V0, V0, -29696
+BFD004F2 8C00 BEQZ S0, 0xBFD004F4
+BFD004F4 EDD9 LI V1, 89
+BFD004F6 89A0 SB V1, 0(V0)
+BFD004F8 A00041A2 LUI V0, 0xA000
+BFD004FC 8C005042 ORI V0, V0, -29696
+BFD004FE 8C00 BEQZ S0, 0xBFD00500
+BFD00500 ED82 LI V1, 2
+BFD00502 89A0 SB V1, 0(V0)
+BFD00504 A00041A2 LUI V0, 0xA000
+BFD00508 8C005042 ORI V0, V0, -29696
+BFD0050A 8C00 BEQZ S0, 0xBFD0050C
+BFD0050C BFD241A3 LUI V1, 0xBFD2
+BFD0050E FC63BFD2 LDC1 F30, -925(S2)
+BFD00510 8134FC63 LW V1, -32460(V1)
+BFD00514 2DBD ANDI V1, V1, 0xFF
+BFD00516 89A0 SB V1, 0(V0)
+BFD00518 A00041A2 LUI V0, 0xA000
+BFD0051C 8C005042 ORI V0, V0, -29696
+BFD0051E 8C00 BEQZ S0, 0xBFD00520
+BFD00520 BFD241A3 LUI V1, 0xBFD2
+BFD00522 FC63BFD2 LDC1 F30, -925(S2)
+BFD00524 8134FC63 LW V1, -32460(V1)
+BFD00528 25B1 SRL V1, V1, 8
+BFD0052A 2DBD ANDI V1, V1, 0xFF
+BFD0052C 89A0 SB V1, 0(V0)
+BFD0052E A00041A2 LUI V0, 0xA000
+BFD00532 8C005042 ORI V0, V0, -29696
+BFD00534 8C00 BEQZ S0, 0xBFD00536
+BFD00536 BFD241A3 LUI V1, 0xBFD2
+BFD00538 FC63BFD2 LDC1 F30, -925(S2)
+BFD0053A 8134FC63 LW V1, -32460(V1)
+BFD0053E 80400063 SRL V1, V1, 16
+BFD00542 2DBD ANDI V1, V1, 0xFF
+BFD00544 89A0 SB V1, 0(V0)
+BFD00546 A00041A2 LUI V0, 0xA000
+BFD0054A 8C005042 ORI V0, V0, -29696
+BFD0054C 8C00 BEQZ S0, 0xBFD0054E
+BFD0054E BFD241A3 LUI V1, 0xBFD2
+BFD00550 FC63BFD2 LDC1 F30, -925(S2)
+BFD00552 8134FC63 LW V1, -32460(V1)
+BFD00556 C0400063 SRL V1, V1, 24
+BFD0055A 2DBD ANDI V1, V1, 0xFF
+BFD0055C 89A0 SB V1, 0(V0)
+80: TRACE11(602, AP3GENEXCEPT, 0, "CP0 STATUS = 0x%08x",gexc_cap.cp0_status);\r
+BFD0055E A00041A2 LUI V0, 0xA000
+BFD00562 8C005042 ORI V0, V0, -29696
+BFD00564 8C00 BEQZ S0, 0xBFD00566
+BFD00566 FFFD3060 ADDIU V1, ZERO, -3
+BFD00568 89A0FFFD LW RA, -30304(SP)
+BFD0056A 89A0 SB V1, 0(V0)
+BFD0056C A00041A2 LUI V0, 0xA000
+BFD00570 8C005042 ORI V0, V0, -29696
+BFD00572 8C00 BEQZ S0, 0xBFD00574
+BFD00574 EDDA LI V1, 90
+BFD00576 89A0 SB V1, 0(V0)
+BFD00578 A00041A2 LUI V0, 0xA000
+BFD0057C 8C005042 ORI V0, V0, -29696
+BFD0057E 8C00 BEQZ S0, 0xBFD00580
+BFD00580 ED82 LI V1, 2
+BFD00582 89A0 SB V1, 0(V0)
+BFD00584 A00041A2 LUI V0, 0xA000
+BFD00588 8C005042 ORI V0, V0, -29696
+BFD0058A 8C00 BEQZ S0, 0xBFD0058C
+BFD0058C BFD241A3 LUI V1, 0xBFD2
+BFD0058E 3063BFD2 LDC1 F30, 12387(S2)
+BFD00590 81343063 ADDIU V1, V1, -32460
+BFD00594 69B1 LW V1, 4(V1)
+BFD00596 2DBD ANDI V1, V1, 0xFF
+BFD00598 89A0 SB V1, 0(V0)
+BFD0059A A00041A2 LUI V0, 0xA000
+BFD0059E 8C005042 ORI V0, V0, -29696
+BFD005A0 8C00 BEQZ S0, 0xBFD005A2
+BFD005A2 BFD241A3 LUI V1, 0xBFD2
+BFD005A4 3063BFD2 LDC1 F30, 12387(S2)
+BFD005A6 81343063 ADDIU V1, V1, -32460
+BFD005AA 69B1 LW V1, 4(V1)
+BFD005AC 25B1 SRL V1, V1, 8
+BFD005AE 2DBD ANDI V1, V1, 0xFF
+BFD005B0 89A0 SB V1, 0(V0)
+BFD005B2 A00041A2 LUI V0, 0xA000
+BFD005B6 8C005042 ORI V0, V0, -29696
+BFD005B8 8C00 BEQZ S0, 0xBFD005BA
+BFD005BA BFD241A3 LUI V1, 0xBFD2
+BFD005BC 3063BFD2 LDC1 F30, 12387(S2)
+BFD005BE 81343063 ADDIU V1, V1, -32460
+BFD005C2 69B1 LW V1, 4(V1)
+BFD005C4 80400063 SRL V1, V1, 16
+BFD005C8 2DBD ANDI V1, V1, 0xFF
+BFD005CA 89A0 SB V1, 0(V0)
+BFD005CC A00041A2 LUI V0, 0xA000
+BFD005D0 8C005042 ORI V0, V0, -29696
+BFD005D2 8C00 BEQZ S0, 0xBFD005D4
+BFD005D4 BFD241A3 LUI V1, 0xBFD2
+BFD005D6 3063BFD2 LDC1 F30, 12387(S2)
+BFD005D8 81343063 ADDIU V1, V1, -32460
+BFD005DC 69B1 LW V1, 4(V1)
+BFD005DE C0400063 SRL V1, V1, 24
+BFD005E2 2DBD ANDI V1, V1, 0xFF
+BFD005E4 89A0 SB V1, 0(V0)
+81: TRACE11(603, AP3GENEXCEPT, 0, "CP0 CAUSE = 0x%08x",gexc_cap.cp0_cause);\r
+BFD005E6 A00041A2 LUI V0, 0xA000
+BFD005EA 8C005042 ORI V0, V0, -29696
+BFD005EC 8C00 BEQZ S0, 0xBFD005EE
+BFD005EE FFFD3060 ADDIU V1, ZERO, -3
+BFD005F0 89A0FFFD LW RA, -30304(SP)
+BFD005F2 89A0 SB V1, 0(V0)
+BFD005F4 A00041A2 LUI V0, 0xA000
+BFD005F8 8C005042 ORI V0, V0, -29696
+BFD005FA 8C00 BEQZ S0, 0xBFD005FC
+BFD005FC EDDB LI V1, 91
+BFD005FE 89A0 SB V1, 0(V0)
+BFD00600 A00041A2 LUI V0, 0xA000
+BFD00604 8C005042 ORI V0, V0, -29696
+BFD00606 8C00 BEQZ S0, 0xBFD00608
+BFD00608 ED82 LI V1, 2
+BFD0060A 89A0 SB V1, 0(V0)
+BFD0060C A00041A2 LUI V0, 0xA000
+BFD00610 8C005042 ORI V0, V0, -29696
+BFD00612 8C00 BEQZ S0, 0xBFD00614
+BFD00614 BFD241A3 LUI V1, 0xBFD2
+BFD00616 3063BFD2 LDC1 F30, 12387(S2)
+BFD00618 81343063 ADDIU V1, V1, -32460
+BFD0061C 69B2 LW V1, 8(V1)
+BFD0061E 2DBD ANDI V1, V1, 0xFF
+BFD00620 89A0 SB V1, 0(V0)
+BFD00622 A00041A2 LUI V0, 0xA000
+BFD00626 8C005042 ORI V0, V0, -29696
+BFD00628 8C00 BEQZ S0, 0xBFD0062A
+BFD0062A BFD241A3 LUI V1, 0xBFD2
+BFD0062C 3063BFD2 LDC1 F30, 12387(S2)
+BFD0062E 81343063 ADDIU V1, V1, -32460
+BFD00632 69B2 LW V1, 8(V1)
+BFD00634 25B1 SRL V1, V1, 8
+BFD00636 2DBD ANDI V1, V1, 0xFF
+BFD00638 89A0 SB V1, 0(V0)
+BFD0063A A00041A2 LUI V0, 0xA000
+BFD0063E 8C005042 ORI V0, V0, -29696
+BFD00640 8C00 BEQZ S0, 0xBFD00642
+BFD00642 BFD241A3 LUI V1, 0xBFD2
+BFD00644 3063BFD2 LDC1 F30, 12387(S2)
+BFD00646 81343063 ADDIU V1, V1, -32460
+BFD0064A 69B2 LW V1, 8(V1)
+BFD0064C 80400063 SRL V1, V1, 16
+BFD00650 2DBD ANDI V1, V1, 0xFF
+BFD00652 89A0 SB V1, 0(V0)
+BFD00654 A00041A2 LUI V0, 0xA000
+BFD00658 8C005042 ORI V0, V0, -29696
+BFD0065A 8C00 BEQZ S0, 0xBFD0065C
+BFD0065C BFD241A3 LUI V1, 0xBFD2
+BFD0065E 3063BFD2 LDC1 F30, 12387(S2)
+BFD00660 81343063 ADDIU V1, V1, -32460
+BFD00664 69B2 LW V1, 8(V1)
+BFD00666 C0400063 SRL V1, V1, 24
+BFD0066A 2DBD ANDI V1, V1, 0xFF
+BFD0066C 89A0 SB V1, 0(V0)
+82: TRACE11(604, AP3GENEXCEPT, 0, "CP0 EPC = 0x%08x",gexc_cap.cp0_epc);\r
+BFD0066E A00041A2 LUI V0, 0xA000
+BFD00672 8C005042 ORI V0, V0, -29696
+BFD00674 8C00 BEQZ S0, 0xBFD00676
+BFD00676 FFFD3060 ADDIU V1, ZERO, -3
+BFD00678 89A0FFFD LW RA, -30304(SP)
+BFD0067A 89A0 SB V1, 0(V0)
+BFD0067C A00041A2 LUI V0, 0xA000
+BFD00680 8C005042 ORI V0, V0, -29696
+BFD00682 8C00 BEQZ S0, 0xBFD00684
+BFD00684 EDDC LI V1, 92
+BFD00686 89A0 SB V1, 0(V0)
+BFD00688 A00041A2 LUI V0, 0xA000
+BFD0068C 8C005042 ORI V0, V0, -29696
+BFD0068E 8C00 BEQZ S0, 0xBFD00690
+BFD00690 ED82 LI V1, 2
+BFD00692 89A0 SB V1, 0(V0)
+BFD00694 A00041A2 LUI V0, 0xA000
+BFD00698 8C005042 ORI V0, V0, -29696
+BFD0069A 8C00 BEQZ S0, 0xBFD0069C
+BFD0069C BFD241A3 LUI V1, 0xBFD2
+BFD0069E 3063BFD2 LDC1 F30, 12387(S2)
+BFD006A0 81343063 ADDIU V1, V1, -32460
+BFD006A4 69B3 LW V1, 12(V1)
+BFD006A6 2DBD ANDI V1, V1, 0xFF
+BFD006A8 89A0 SB V1, 0(V0)
+BFD006AA A00041A2 LUI V0, 0xA000
+BFD006AE 8C005042 ORI V0, V0, -29696
+BFD006B0 8C00 BEQZ S0, 0xBFD006B2
+BFD006B2 BFD241A3 LUI V1, 0xBFD2
+BFD006B4 3063BFD2 LDC1 F30, 12387(S2)
+BFD006B6 81343063 ADDIU V1, V1, -32460
+BFD006BA 69B3 LW V1, 12(V1)
+BFD006BC 25B1 SRL V1, V1, 8
+BFD006BE 2DBD ANDI V1, V1, 0xFF
+BFD006C0 89A0 SB V1, 0(V0)
+BFD006C2 A00041A2 LUI V0, 0xA000
+BFD006C6 8C005042 ORI V0, V0, -29696
+BFD006C8 8C00 BEQZ S0, 0xBFD006CA
+BFD006CA BFD241A3 LUI V1, 0xBFD2
+BFD006CC 3063BFD2 LDC1 F30, 12387(S2)
+BFD006CE 81343063 ADDIU V1, V1, -32460
+BFD006D2 69B3 LW V1, 12(V1)
+BFD006D4 80400063 SRL V1, V1, 16
+BFD006D8 2DBD ANDI V1, V1, 0xFF
+BFD006DA 89A0 SB V1, 0(V0)
+BFD006DC A00041A2 LUI V0, 0xA000
+BFD006E0 8C005042 ORI V0, V0, -29696
+BFD006E2 8C00 BEQZ S0, 0xBFD006E4
+BFD006E4 BFD241A3 LUI V1, 0xBFD2
+BFD006E6 3063BFD2 LDC1 F30, 12387(S2)
+BFD006E8 81343063 ADDIU V1, V1, -32460
+BFD006EC 69B3 LW V1, 12(V1)
+BFD006EE C0400063 SRL V1, V1, 24
+BFD006F2 2DBD ANDI V1, V1, 0xFF
+BFD006F4 89A0 SB V1, 0(V0)
+83: TRACE11(605, AP3GENEXCEPT, 0, "CP0 ERROREPC = 0x%08x",gexc_cap.cp0_error_epc);\r
+BFD006F6 A00041A2 LUI V0, 0xA000
+BFD006FA 8C005042 ORI V0, V0, -29696
+BFD006FC 8C00 BEQZ S0, 0xBFD006FE
+BFD006FE FFFD3060 ADDIU V1, ZERO, -3
+BFD00700 89A0FFFD LW RA, -30304(SP)
+BFD00702 89A0 SB V1, 0(V0)
+BFD00704 A00041A2 LUI V0, 0xA000
+BFD00708 8C005042 ORI V0, V0, -29696
+BFD0070A 8C00 BEQZ S0, 0xBFD0070C
+BFD0070C EDDD LI V1, 93
+BFD0070E 89A0 SB V1, 0(V0)
+BFD00710 A00041A2 LUI V0, 0xA000
+BFD00714 8C005042 ORI V0, V0, -29696
+BFD00716 8C00 BEQZ S0, 0xBFD00718
+BFD00718 ED82 LI V1, 2
+BFD0071A 89A0 SB V1, 0(V0)
+BFD0071C A00041A2 LUI V0, 0xA000
+BFD00720 8C005042 ORI V0, V0, -29696
+BFD00722 8C00 BEQZ S0, 0xBFD00724
+BFD00724 BFD241A3 LUI V1, 0xBFD2
+BFD00726 3063BFD2 LDC1 F30, 12387(S2)
+BFD00728 81343063 ADDIU V1, V1, -32460
+BFD0072C 69B4 LW V1, 16(V1)
+BFD0072E 2DBD ANDI V1, V1, 0xFF
+BFD00730 89A0 SB V1, 0(V0)
+BFD00732 A00041A2 LUI V0, 0xA000
+BFD00736 8C005042 ORI V0, V0, -29696
+BFD00738 8C00 BEQZ S0, 0xBFD0073A
+BFD0073A BFD241A3 LUI V1, 0xBFD2
+BFD0073C 3063BFD2 LDC1 F30, 12387(S2)
+BFD0073E 81343063 ADDIU V1, V1, -32460
+BFD00742 69B4 LW V1, 16(V1)
+BFD00744 25B1 SRL V1, V1, 8
+BFD00746 2DBD ANDI V1, V1, 0xFF
+BFD00748 89A0 SB V1, 0(V0)
+BFD0074A A00041A2 LUI V0, 0xA000
+BFD0074E 8C005042 ORI V0, V0, -29696
+BFD00750 8C00 BEQZ S0, 0xBFD00752
+BFD00752 BFD241A3 LUI V1, 0xBFD2
+BFD00754 3063BFD2 LDC1 F30, 12387(S2)
+BFD00756 81343063 ADDIU V1, V1, -32460
+BFD0075A 69B4 LW V1, 16(V1)
+BFD0075C 80400063 SRL V1, V1, 16
+BFD00760 2DBD ANDI V1, V1, 0xFF
+BFD00762 89A0 SB V1, 0(V0)
+BFD00764 A00041A2 LUI V0, 0xA000
+BFD00768 8C005042 ORI V0, V0, -29696
+BFD0076A 8C00 BEQZ S0, 0xBFD0076C
+BFD0076C BFD241A3 LUI V1, 0xBFD2
+BFD0076E 3063BFD2 LDC1 F30, 12387(S2)
+BFD00770 81343063 ADDIU V1, V1, -32460
+BFD00774 69B4 LW V1, 16(V1)
+BFD00776 C0400063 SRL V1, V1, 24
+BFD0077A 2DBD ANDI V1, V1, 0xFF
+BFD0077C 89A0 SB V1, 0(V0)
+84: TRACE11(606, AP3GENEXCEPT, 0, "CP0 NEXC = 0x%08x",gexc_cap.cp0_nexc);\r
+BFD0077E A00041A2 LUI V0, 0xA000
+BFD00782 8C005042 ORI V0, V0, -29696
+BFD00784 8C00 BEQZ S0, 0xBFD00786
+BFD00786 FFFD3060 ADDIU V1, ZERO, -3
+BFD00788 89A0FFFD LW RA, -30304(SP)
+BFD0078A 89A0 SB V1, 0(V0)
+BFD0078C A00041A2 LUI V0, 0xA000
+BFD00790 8C005042 ORI V0, V0, -29696
+BFD00792 8C00 BEQZ S0, 0xBFD00794
+BFD00794 EDDE LI V1, 94
+BFD00796 89A0 SB V1, 0(V0)
+BFD00798 A00041A2 LUI V0, 0xA000
+BFD0079C 8C005042 ORI V0, V0, -29696
+BFD0079E 8C00 BEQZ S0, 0xBFD007A0
+BFD007A0 ED82 LI V1, 2
+BFD007A2 89A0 SB V1, 0(V0)
+BFD007A4 A00041A2 LUI V0, 0xA000
+BFD007A8 8C005042 ORI V0, V0, -29696
+BFD007AA 8C00 BEQZ S0, 0xBFD007AC
+BFD007AC BFD241A3 LUI V1, 0xBFD2
+BFD007AE 3063BFD2 LDC1 F30, 12387(S2)
+BFD007B0 81343063 ADDIU V1, V1, -32460
+BFD007B4 69B5 LW V1, 20(V1)
+BFD007B6 2DBD ANDI V1, V1, 0xFF
+BFD007B8 89A0 SB V1, 0(V0)
+BFD007BA A00041A2 LUI V0, 0xA000
+BFD007BE 8C005042 ORI V0, V0, -29696
+BFD007C0 8C00 BEQZ S0, 0xBFD007C2
+BFD007C2 BFD241A3 LUI V1, 0xBFD2
+BFD007C4 3063BFD2 LDC1 F30, 12387(S2)
+BFD007C6 81343063 ADDIU V1, V1, -32460
+BFD007CA 69B5 LW V1, 20(V1)
+BFD007CC 25B1 SRL V1, V1, 8
+BFD007CE 2DBD ANDI V1, V1, 0xFF
+BFD007D0 89A0 SB V1, 0(V0)
+BFD007D2 A00041A2 LUI V0, 0xA000
+BFD007D6 8C005042 ORI V0, V0, -29696
+BFD007D8 8C00 BEQZ S0, 0xBFD007DA
+BFD007DA BFD241A3 LUI V1, 0xBFD2
+BFD007DC 3063BFD2 LDC1 F30, 12387(S2)
+BFD007DE 81343063 ADDIU V1, V1, -32460
+BFD007E2 69B5 LW V1, 20(V1)
+BFD007E4 80400063 SRL V1, V1, 16
+BFD007E8 2DBD ANDI V1, V1, 0xFF
+BFD007EA 89A0 SB V1, 0(V0)
+BFD007EC A00041A2 LUI V0, 0xA000
+BFD007F0 8C005042 ORI V0, V0, -29696
+BFD007F2 8C00 BEQZ S0, 0xBFD007F4
+BFD007F4 BFD241A3 LUI V1, 0xBFD2
+BFD007F6 3063BFD2 LDC1 F30, 12387(S2)
+BFD007F8 81343063 ADDIU V1, V1, -32460
+BFD007FC 69B5 LW V1, 20(V1)
+BFD007FE C0400063 SRL V1, V1, 24
+BFD00802 2DBD ANDI V1, V1, 0xFF
+BFD00804 89A0 SB V1, 0(V0)
+85: TRACE11(607, AP3GENEXCEPT, 0, "CP0 NEPC = 0x%08x",gexc_cap.cp0_nepc);\r
+BFD00806 A00041A2 LUI V0, 0xA000
+BFD0080A 8C005042 ORI V0, V0, -29696
+BFD0080C 8C00 BEQZ S0, 0xBFD0080E
+BFD0080E FFFD3060 ADDIU V1, ZERO, -3
+BFD00810 89A0FFFD LW RA, -30304(SP)
+BFD00812 89A0 SB V1, 0(V0)
+BFD00814 A00041A2 LUI V0, 0xA000
+BFD00818 8C005042 ORI V0, V0, -29696
+BFD0081A 8C00 BEQZ S0, 0xBFD0081C
+BFD0081C EDDF LI V1, 95
+BFD0081E 89A0 SB V1, 0(V0)
+BFD00820 A00041A2 LUI V0, 0xA000
+BFD00824 8C005042 ORI V0, V0, -29696
+BFD00826 8C00 BEQZ S0, 0xBFD00828
+BFD00828 ED82 LI V1, 2
+BFD0082A 89A0 SB V1, 0(V0)
+BFD0082C A00041A2 LUI V0, 0xA000
+BFD00830 8C005042 ORI V0, V0, -29696
+BFD00832 8C00 BEQZ S0, 0xBFD00834
+BFD00834 BFD241A3 LUI V1, 0xBFD2
+BFD00836 3063BFD2 LDC1 F30, 12387(S2)
+BFD00838 81343063 ADDIU V1, V1, -32460
+BFD0083C 69B6 LW V1, 24(V1)
+BFD0083E 2DBD ANDI V1, V1, 0xFF
+BFD00840 89A0 SB V1, 0(V0)
+BFD00842 A00041A2 LUI V0, 0xA000
+BFD00846 8C005042 ORI V0, V0, -29696
+BFD00848 8C00 BEQZ S0, 0xBFD0084A
+BFD0084A BFD241A3 LUI V1, 0xBFD2
+BFD0084C 3063BFD2 LDC1 F30, 12387(S2)
+BFD0084E 81343063 ADDIU V1, V1, -32460
+BFD00852 69B6 LW V1, 24(V1)
+BFD00854 25B1 SRL V1, V1, 8
+BFD00856 2DBD ANDI V1, V1, 0xFF
+BFD00858 89A0 SB V1, 0(V0)
+BFD0085A A00041A2 LUI V0, 0xA000
+BFD0085E 8C005042 ORI V0, V0, -29696
+BFD00860 8C00 BEQZ S0, 0xBFD00862
+BFD00862 BFD241A3 LUI V1, 0xBFD2
+BFD00864 3063BFD2 LDC1 F30, 12387(S2)
+BFD00866 81343063 ADDIU V1, V1, -32460
+BFD0086A 69B6 LW V1, 24(V1)
+BFD0086C 80400063 SRL V1, V1, 16
+BFD00870 2DBD ANDI V1, V1, 0xFF
+BFD00872 89A0 SB V1, 0(V0)
+BFD00874 A00041A2 LUI V0, 0xA000
+BFD00878 8C005042 ORI V0, V0, -29696
+BFD0087A 8C00 BEQZ S0, 0xBFD0087C
+BFD0087C BFD241A3 LUI V1, 0xBFD2
+BFD0087E 3063BFD2 LDC1 F30, 12387(S2)
+BFD00880 81343063 ADDIU V1, V1, -32460
+BFD00884 69B6 LW V1, 24(V1)
+BFD00886 C0400063 SRL V1, V1, 24
+BFD0088A 2DBD ANDI V1, V1, 0xFF
+BFD0088C 89A0 SB V1, 0(V0)
+86: TRACE11(608, AP3GENEXCEPT, 0, "CP0 BADVADDR = 0x%08x",gexc_cap.cp0_badvaddr);\r
+BFD0088E A00041A2 LUI V0, 0xA000
+BFD00892 8C005042 ORI V0, V0, -29696
+BFD00894 8C00 BEQZ S0, 0xBFD00896
+BFD00896 FFFD3060 ADDIU V1, ZERO, -3
+BFD00898 89A0FFFD LW RA, -30304(SP)
+BFD0089A 89A0 SB V1, 0(V0)
+BFD0089C A00041A2 LUI V0, 0xA000
+BFD008A0 8C005042 ORI V0, V0, -29696
+BFD008A2 8C00 BEQZ S0, 0xBFD008A4
+BFD008A4 EDE0 LI V1, 96
+BFD008A6 89A0 SB V1, 0(V0)
+BFD008A8 A00041A2 LUI V0, 0xA000
+BFD008AC 8C005042 ORI V0, V0, -29696
+BFD008AE 8C00 BEQZ S0, 0xBFD008B0
+BFD008B0 ED82 LI V1, 2
+BFD008B2 89A0 SB V1, 0(V0)
+BFD008B4 A00041A2 LUI V0, 0xA000
+BFD008B8 8C005042 ORI V0, V0, -29696
+BFD008BA 8C00 BEQZ S0, 0xBFD008BC
+BFD008BC BFD241A3 LUI V1, 0xBFD2
+BFD008BE 3063BFD2 LDC1 F30, 12387(S2)
+BFD008C0 81343063 ADDIU V1, V1, -32460
+BFD008C4 69B7 LW V1, 28(V1)
+BFD008C6 2DBD ANDI V1, V1, 0xFF
+BFD008C8 89A0 SB V1, 0(V0)
+BFD008CA A00041A2 LUI V0, 0xA000
+BFD008CE 8C005042 ORI V0, V0, -29696
+BFD008D0 8C00 BEQZ S0, 0xBFD008D2
+BFD008D2 BFD241A3 LUI V1, 0xBFD2
+BFD008D4 3063BFD2 LDC1 F30, 12387(S2)
+BFD008D6 81343063 ADDIU V1, V1, -32460
+BFD008DA 69B7 LW V1, 28(V1)
+BFD008DC 25B1 SRL V1, V1, 8
+BFD008DE 2DBD ANDI V1, V1, 0xFF
+BFD008E0 89A0 SB V1, 0(V0)
+BFD008E2 A00041A2 LUI V0, 0xA000
+BFD008E6 8C005042 ORI V0, V0, -29696
+BFD008E8 8C00 BEQZ S0, 0xBFD008EA
+BFD008EA BFD241A3 LUI V1, 0xBFD2
+BFD008EC 3063BFD2 LDC1 F30, 12387(S2)
+BFD008EE 81343063 ADDIU V1, V1, -32460
+BFD008F2 69B7 LW V1, 28(V1)
+BFD008F4 80400063 SRL V1, V1, 16
+BFD008F8 2DBD ANDI V1, V1, 0xFF
+BFD008FA 89A0 SB V1, 0(V0)
+BFD008FC A00041A2 LUI V0, 0xA000
+BFD00900 8C005042 ORI V0, V0, -29696
+BFD00902 8C00 BEQZ S0, 0xBFD00904
+BFD00904 BFD241A3 LUI V1, 0xBFD2
+BFD00906 3063BFD2 LDC1 F30, 12387(S2)
+BFD00908 81343063 ADDIU V1, V1, -32460
+BFD0090C 69B7 LW V1, 28(V1)
+BFD0090E C0400063 SRL V1, V1, 24
+BFD00912 2DBD ANDI V1, V1, 0xFF
+BFD00914 89A0 SB V1, 0(V0)
+87: \r
+88: for (;;) {\r
+89: __asm__ __volatile ("%(ssnop%)" : :);\r
+BFD00916 08000000 SSNOP
+BFD00918 0800 LBU S0, 0(S0)
+90: } \r
+BFD0091A CFFD B 0xBFD00916
+BFD0091C 0C00 NOP
+91: }\r
+92: \r
+93: \r
+94: /* end general_exception.c */\r
+95: /** @}\r
+96: */\r
+97: \r
+--- c:/e/dev/freertos/workingcopy/freertos/demo/pic32mec14xx_mplab/src/main.c -------------------------
+1: #warning configTIMERS_DISAGGREGATED_ISRS and configCPU_DISAGGREGATED_ISRS need documenting.\r
+2: \r
+3: /*\r
+4: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+5: All rights reserved\r
+6: \r
+7: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+8: \r
+9: This file is part of the FreeRTOS distribution.\r
+10: \r
+11: FreeRTOS is free software; you can redistribute it and/or modify it under\r
+12: the terms of the GNU General Public License (version 2) as published by the\r
+13: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+14: \r
+15: ***************************************************************************\r
+16: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+17: >>! distribute a combined work that includes FreeRTOS without being !<<\r
+18: >>! obliged to provide the source code for proprietary components !<<\r
+19: >>! outside of the FreeRTOS kernel. !<<\r
+20: ***************************************************************************\r
+21: \r
+22: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+23: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+24: FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+25: link: http://www.freertos.org/a00114.html\r
+26: \r
+27: ***************************************************************************\r
+28: * *\r
+29: * FreeRTOS provides completely free yet professionally developed, *\r
+30: * robust, strictly quality controlled, supported, and cross *\r
+31: * platform software that is more than just the market leader, it *\r
+32: * is the industry's de facto standard. *\r
+33: * *\r
+34: * Help yourself get started quickly while simultaneously helping *\r
+35: * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+36: * tutorial book, reference manual, or both: *\r
+37: * http://www.FreeRTOS.org/Documentation *\r
+38: * *\r
+39: ***************************************************************************\r
+40: \r
+41: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+42: the FAQ page "My application does not run, what could be wrong?". Have you\r
+43: defined configASSERT()?\r
+44: \r
+45: http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+46: embedded software for free we request you assist our global community by\r
+47: participating in the support forum.\r
+48: \r
+49: http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+50: be as productive as possible as early as possible. Now you can receive\r
+51: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+52: Ltd, and the world's leading authority on the world's leading RTOS.\r
+53: \r
+54: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+55: including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+56: compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+57: \r
+58: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+59: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+60: \r
+61: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+62: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+63: licenses offer ticketed support, indemnification and commercial middleware.\r
+64: \r
+65: http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+66: engineered and independently SIL3 certified version for use in safety and\r
+67: mission critical applications that require provable dependability.\r
+68: \r
+69: 1 tab == 4 spaces!\r
+70: */\r
+71: \r
+72: /******************************************************************************\r
+73: * This project only provides a simple blinky demonstration.\r
+74: *\r
+75: * main() creates one queue, two tasks, and one software timer. It then starts\r
+76: * the scheduler.\r
+77: *\r
+78: * The Blinky Software Timer:\r
+79: * This demonstrates an auto-reload software timer. The timer callback function\r
+80: * does nothing but toggle an LED.\r
+81: *\r
+82: * The Queue Send Task:\r
+83: * The queue send task is implemented by prvQueueSendTask(). It sends the value\r
+84: * 100 to the queue every 200 milliseconds.\r
+85: *\r
+86: * The Queue Receive Task:\r
+87: * The queue receive task is implemented by prvQueueReceiveTask().\r
+88: * prvQueueReceiveTask() repeatedly blocks on attempts to read from the queue,\r
+89: * toggling an LED each time data is received. The queue send task sends data\r
+90: * to the queue every 200 milliseconds, so the LED will toggle every 200\r
+91: * milliseconds.\r
+92: */\r
+93: \r
+94: /* Kernel includes. */\r
+95: #include "FreeRTOS.h"\r
+96: #include "task.h"\r
+97: #include "queue.h"\r
+98: #include "timers.h"\r
+99: \r
+100: /* Target includes. */\r
+101: #include "appcfg.h"\r
+102: #include "MEC14xx/mec14xx.h"\r
+103: #include "MEC14xx/mec14xx_jtvic.h"\r
+104: #include "MEC14xx/mec14xx_bbled.h"\r
+105: #include "MEC14xx/mec14xx_girqs.h"\r
+106: \r
+107: /* Priorities at which the tasks are created. */\r
+108: #define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+109: #define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+110: \r
+111: /* The rate at which data is sent to the queue. The 200ms value is converted\r
+112: to ticks using the pdMS_TO_TICKS() macro. */\r
+113: #define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 200UL ) )\r
+114: \r
+115: /* The number of items the queue can hold. This is 1 as the receive task\r
+116: will remove items as they are added, meaning the send task should always find\r
+117: the queue empty. */\r
+118: #define mainQUEUE_LENGTH ( 1 )\r
+119: \r
+120: /* Values passed to the two tasks just to check the task parameter\r
+121: functionality. */\r
+122: #define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
+123: #define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
+124: \r
+125: /* The period of the software timer. The period is specified in ms and\r
+126: converted to ticks using the pdMS_TO_TICKS() macro. */\r
+127: #define mainBLINKY_TIMER_PERIOD ( pdMS_TO_TICKS( 50UL ) )\r
+128: \r
+129: /* The LED used by the communicating tasks and the timer respectively. */\r
+130: #define mainTASKS_LED ( LED0_ID )\r
+131: #define mainTIMER_LED ( LED1_ID )\r
+132: \r
+133: /* Misc. */\r
+134: #define mainDONT_BLOCK ( 0 )\r
+135: \r
+136: \r
+137: /*-----------------------------------------------------------*/\r
+138: \r
+139: /*\r
+140: * The tasks as described in the comments at the top of this file.\r
+141: */\r
+142: static void prvQueueReceiveTask( void *pvParameters );\r
+143: static void prvQueueSendTask( void *pvParameters );\r
+144: \r
+145: /*\r
+146: * The callback function for the software timer, as described at the top of this\r
+147: * file.\r
+148: */\r
+149: static void prvBlinkyTimerCallback( TimerHandle_t xTimer );\r
+150: \r
+151: /*\r
+152: * Performs any hardware setup necessary.\r
+153: */\r
+154: static void prvSetupHardware( void );\r
+155: \r
+156: /*\r
+157: * Add some thread safety to the LED toggle function.\r
+158: */\r
+159: static void prvToggleLED( uint8_t ucLED );\r
+160: \r
+161: /*-----------------------------------------------------------*/\r
+162: \r
+163: /* The queue used by both tasks. */\r
+164: static QueueHandle_t xQueue = NULL;\r
+165: \r
+166: /*-----------------------------------------------------------*/\r
+167: \r
+168: int main( void )\r
+169: {\r
+BFD096C0 4FF1 ADDIU SP, SP, -32
+BFD096C2 CBE7 SW RA, 28(SP)
+BFD096C4 CBC6 SW S8, 24(SP)
+BFD096C6 0FDD MOVE S8, SP
+170: TimerHandle_t xTimer;\r
+171: \r
+172: /* Perform any hardware initialisation necessary. */\r
+173: //prvSetupHardware();\r
+174: \r
+175: __asm volatile( "di" );\r
+BFD096C8 477C0000 DI ZERO
+176: \r
+177: \r
+178: {\r
+179: volatile uint32_t ulx = 0;\r
+BFD096CC 0010F81E SW ZERO, 16(S8)
+180: \r
+181: for( ;; )\r
+182: {\r
+183: for( ulx = 0; ulx < 0x1fff; ulx++ )\r
+BFD096D0 CC0A B 0xBFD096E6
+BFD096D2 0010F81E SW ZERO, 16(S8)
+BFD096D4 0C000010 SLL ZERO, S0, 1
+BFD096DC 0010FC5E LW V0, 16(S8)
+BFD096E0 6D20 ADDIU V0, V0, 1
+BFD096E2 0010F85E SW V0, 16(S8)
+BFD096E6 0010FC5E LW V0, 16(S8)
+BFD096EA 1FFFB042 SLTIU V0, V0, 8191
+BFD096EC 40A21FFF LB RA, 16546(RA)
+BFD096EE FFF240A2 BNEZC V0, 0xBFD096D6
+BFD096F0 77E8FFF2 LW RA, 30696(S2)
+184: {\r
+185: __asm volatile( "NOP" );\r
+BFD096D6 0C00 NOP
+186: __asm volatile( "NOP" );\r
+BFD096D8 0C00 NOP
+187: __asm volatile( "NOP" ); \r
+BFD096DA 0C00 NOP
+188: }\r
+189: \r
+190: led_out_toggle( 0 );\r
+BFD096F2 42D477E8 JALS led_out_toggle
+BFD096F6 0C80 MOVE A0, ZERO
+191: }\r
+BFD096F8 CFEB B 0xBFD096D0
+BFD096FA 0C00 NOP
+192: }\r
+193: \r
+194: \r
+195: \r
+196: /* Create the queue. */\r
+197: xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+198: configASSERT( xQueue );\r
+199: \r
+200: if( xQueue != NULL )\r
+201: {\r
+202: /* Create the two tasks as described in the comments at the top of this\r
+203: file. */\r
+204: xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+205: "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+206: configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+207: ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */\r
+208: mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+209: NULL ); /* The task handle is not required, so NULL is passed. */\r
+210: \r
+211: xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+212: \r
+213: \r
+214: /* Create the blinky software timer as described at the top of this file. */\r
+215: xTimer = xTimerCreate( "Blinky", /* A text name, purely to help debugging. */\r
+216: ( mainBLINKY_TIMER_PERIOD ),/* The timer period. */\r
+217: pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+218: ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+219: prvBlinkyTimerCallback ); /* The callback function that inspects the status of all the other tasks. */\r
+220: configASSERT( xTimer );\r
+221: \r
+222: if( xTimer != NULL )\r
+223: {\r
+224: xTimerStart( xTimer, mainDONT_BLOCK );\r
+225: }\r
+226: \r
+227: /* Start the tasks and timer running. */\r
+228: vTaskStartScheduler();\r
+229: }\r
+230: \r
+231: /* If all is well, the scheduler will now be running, and the following\r
+232: line will never be reached. If the following line does execute, then\r
+233: there was insufficient FreeRTOS heap memory available for the idle and/or\r
+234: timer tasks to be created. See the memory management section on the\r
+235: FreeRTOS web site for more details. http://www.freertos.org/a00111.html */\r
+236: for( ;; );\r
+237: }\r
+238: /*-----------------------------------------------------------*/\r
+239: \r
+240: static void prvQueueSendTask( void *pvParameters )\r
+241: {\r
+BFD07E34 4FF1 ADDIU SP, SP, -32
+BFD07E36 CBE7 SW RA, 28(SP)
+BFD07E38 CBC6 SW S8, 24(SP)
+BFD07E3A 0FDD MOVE S8, SP
+BFD07E3C 0020F89E SW A0, 32(S8)
+242: TickType_t xNextWakeTime;\r
+243: const unsigned long ulValueToSend = 100UL;\r
+BFD07E40 ED64 LI V0, 100
+BFD07E42 0014F85E SW V0, 20(S8)
+244: \r
+245: /* Remove compiler warnigns in the case that configASSERT() is not dfined. */\r
+246: ( void ) pvParameters;\r
+247: \r
+248: /* Check the task parameter is as expected. */\r
+249: configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );\r
+BFD07E46 0020FC7E LW V1, 32(S8)
+BFD07E48 30400020 SRL AT, ZERO, 6
+BFD07E4A 11113040 ADDIU V0, ZERO, 4369
+BFD07E4C 94431111 ADDI T0, S1, -27581
+BFD07E4E 000A9443 BEQ V1, V0, 0xBFD07E66
+BFD07E50 0C00000A SLL ZERO, T2, 1
+BFD07E52 0C00 NOP
+BFD07E54 BFD141A2 LUI V0, 0xBFD1
+BFD07E56 3082BFD1 LDC1 F30, 12418(S1)
+BFD07E58 9EF43082 ADDIU A0, V0, -24844
+BFD07E5A 30A09EF4 LWC1 F23, 12448(S4)
+BFD07E5C 00F930A0 ADDIU A1, ZERO, 249
+BFD07E60 4B7E77E8 JALS vAssertCalled
+BFD07E62 4B7E LW K1, 120(SP)
+BFD07E64 0C00 NOP
+250: \r
+251: /* Initialise xNextWakeTime - this only needs to be done once. */\r
+252: xNextWakeTime = xTaskGetTickCount();\r
+BFD07E66 4CCA77E8 JALS xTaskGetTickCount
+BFD07E68 4CCA ADDIU A2, A2, 5
+BFD07E6A 0C00 NOP
+BFD07E6C 0010F85E SW V0, 16(S8)
+253: \r
+254: for( ;; )\r
+255: {\r
+256: /* Place this task in the blocked state until it is time to run again.\r
+257: The block time is specified in ticks, the constant used converts ticks\r
+258: to ms. While in the Blocked state this task will not consume any CPU\r
+259: time. */\r
+260: vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+BFD07E70 0010305E ADDIU V0, S8, 16
+BFD07E74 0C82 MOVE A0, V0
+BFD07E76 00C830A0 ADDIU A1, ZERO, 200
+BFD07E7A 000477E8 JALS vTaskDelayUntil
+BFD07E7C 0C000004 SLL ZERO, A0, 1
+BFD07E7E 0C00 NOP
+261: \r
+262: /* Send to the queue - causing the queue receive task to unblock and\r
+263: toggle the LED. 0 is used as the block time so the sending operation\r
+264: will not block - it shouldn't need to block as the queue should always\r
+265: be empty at this point in the code. */\r
+266: xQueueSend( xQueue, &ulValueToSend, 0U );\r
+BFD07E80 8070FC7C LW V1, -32656(GP)
+BFD07E84 0014305E ADDIU V0, S8, 20
+BFD07E88 0C83 MOVE A0, V1
+BFD07E8A 0CA2 MOVE A1, V0
+BFD07E8C 0CC0 MOVE A2, ZERO
+BFD07E8E 0CE0 MOVE A3, ZERO
+BFD07E90 06A277E8 JALS xQueueGenericSend
+BFD07E92 06A2 ADDU A1, S1, V0
+BFD07E94 0C00 NOP
+267: }\r
+BFD07E96 CFEC B 0xBFD07E70
+BFD07E98 0C00 NOP
+268: }\r
+269: /*-----------------------------------------------------------*/\r
+270: \r
+271: static void prvQueueReceiveTask( void *pvParameters )\r
+272: {\r
+BFD08090 4FF1 ADDIU SP, SP, -32
+BFD08092 CBE7 SW RA, 28(SP)
+BFD08094 CBC6 SW S8, 24(SP)
+BFD08096 0FDD MOVE S8, SP
+BFD08098 0020F89E SW A0, 32(S8)
+273: unsigned long ulReceivedValue;\r
+274: \r
+275: /* Remove compiler warnings in the case where configASSERT() is not defined. */\r
+276: ( void ) pvParameters;\r
+277: \r
+278: /* Check the task parameter is as expected. */\r
+279: configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );\r
+BFD0809C 0020FC7E LW V1, 32(S8)
+BFD080A0 ED22 LI V0, 34
+BFD080A2 000D9443 BEQ V1, V0, 0xBFD080C0
+BFD080A4 0C00000D SLL ZERO, T5, 1
+BFD080A6 0C00 NOP
+BFD080A8 BFD141A2 LUI V0, 0xBFD1
+BFD080AA 3082BFD1 LDC1 F30, 12418(S1)
+BFD080AC 9EF43082 ADDIU A0, V0, -24844
+BFD080AE 30A09EF4 LWC1 F23, 12448(S4)
+BFD080B0 011730A0 ADDIU A1, ZERO, 279
+BFD080B4 4B7E77E8 JALS vAssertCalled
+BFD080B6 4B7E LW K1, 120(SP)
+BFD080B8 0C00 NOP
+BFD080BA CC02 B 0xBFD080C0
+BFD080BC 0C00 NOP
+280: \r
+281: for( ;; )\r
+282: {\r
+283: /* Wait until something arrives in the queue - this task will block\r
+284: indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+285: FreeRTOSConfig.h. */\r
+286: xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+BFD080C0 8070FC5C LW V0, -32656(GP)
+BFD080C4 0C82 MOVE A0, V0
+BFD080C6 0010305E ADDIU V0, S8, 16
+BFD080CA 0CA2 MOVE A1, V0
+BFD080CC EF7F LI A2, -1
+BFD080CE 0CE0 MOVE A3, ZERO
+BFD080D0 081E77E8 JALS xQueueGenericReceive
+BFD080D2 081E LBU S0, 14(S1)
+BFD080D4 0C00 NOP
+287: \r
+288: /* To get here something must have been received from the queue, but\r
+289: is it the expected value? If it is, toggle the LED. */\r
+290: if( ulReceivedValue == 100UL )\r
+BFD080D6 0010FC7E LW V1, 16(S8)
+BFD080DA ED64 LI V0, 100
+BFD080DC FFEFB443 BNE V1, V0, 0xBFD080BE
+BFD080DE 0C00FFEF LW RA, 3072(T7)
+BFD080E0 0C00 NOP
+291: {\r
+292: prvToggleLED( mainTASKS_LED );\r
+BFD080E2 0C80 MOVE A0, ZERO
+BFD080E4 4C3C77E8 JALS prvToggleLED
+BFD080E6 4C3C ADDIU AT, AT, -2
+BFD080E8 0C00 NOP
+293: ulReceivedValue = 0U;\r
+BFD080EA 0010F81E SW ZERO, 16(S8)
+294: }\r
+295: }\r
+BFD080BE 0C00 NOP
+BFD080EE CFE8 B 0xBFD080C0
+BFD080F0 0C00 NOP
+296: }\r
+297: /*-----------------------------------------------------------*/\r
+298: \r
+299: static void prvBlinkyTimerCallback( TimerHandle_t xTimer )\r
+300: {\r
+BFD09DAC 4FF5 ADDIU SP, SP, -24
+BFD09DAE CBE5 SW RA, 20(SP)
+BFD09DB0 CBC4 SW S8, 16(SP)
+BFD09DB2 0FDD MOVE S8, SP
+BFD09DB4 0018F89E SW A0, 24(S8)
+301: /* Avoid compiler warnings. */\r
+302: ( void ) xTimer;\r
+303: \r
+304: /* This function is called when the blinky software time expires. All the\r
+305: function does is toggle the LED. LED mainTIMER_LED should therefore toggle\r
+306: with the period set by mainBLINKY_TIMER_PERIOD. */\r
+307: prvToggleLED( mainTIMER_LED );\r
+BFD09DB8 EE01 LI A0, 1
+BFD09DBA 4C3C77E8 JALS prvToggleLED
+BFD09DBC 4C3C ADDIU AT, AT, -2
+BFD09DBE 0C00 NOP
+308: }\r
+BFD09DC0 0FBE MOVE SP, S8
+BFD09DC2 4BE5 LW RA, 20(SP)
+BFD09DC4 4BC4 LW S8, 16(SP)
+BFD09DC6 4C0D ADDIU SP, SP, 24
+BFD09DC8 459F JR16 RA
+BFD09DCA 0C00 NOP
+309: /*-----------------------------------------------------------*/\r
+310: \r
+311: static void prvToggleLED( uint8_t ucLED )\r
+312: {\r
+BFD09878 4FF5 ADDIU SP, SP, -24
+BFD0987A CBE5 SW RA, 20(SP)
+BFD0987C CBC4 SW S8, 16(SP)
+BFD0987E 0FDD MOVE S8, SP
+BFD09880 0C44 MOVE V0, A0
+BFD09882 0018185E SB V0, 24(S8)
+313: taskENTER_CRITICAL();\r
+BFD09886 33B877E8 JALS vTaskEnterCritical
+BFD09888 0C0033B8 ADDIU SP, T8, 3072
+BFD0988A 0C00 NOP
+314: {\r
+315: led_out_toggle( ucLED );\r
+BFD0988C 0018145E LBU V0, 24(S8)
+BFD09890 0C82 MOVE A0, V0
+BFD09892 42D477E8 JALS led_out_toggle
+BFD09896 0C00 NOP
+316: }\r
+317: taskEXIT_CRITICAL();\r
+BFD09898 40AA77E8 JALS vTaskExitCritical
+BFD0989A 0C0040AA BNEZC T2, 0xBFD0B09E
+BFD0989C 0C00 NOP
+318: }\r
+BFD0989E 0FBE MOVE SP, S8
+BFD098A0 4BE5 LW RA, 20(SP)
+BFD098A2 4BC4 LW S8, 16(SP)
+BFD098A4 4C0D ADDIU SP, SP, 24
+BFD098A6 459F JR16 RA
+BFD098A8 0C00 NOP
+319: /*-----------------------------------------------------------*/\r
+320: \r
+321: static void prvSetupHardware( void )\r
+322: {\r
+BFD05890 4FF1 ADDIU SP, SP, -32
+BFD05892 CBE7 SW RA, 28(SP)
+BFD05894 CBC6 SW S8, 24(SP)
+BFD05896 0FDD MOVE S8, SP
+323: volatile uint32_t ulTemp;\r
+324: \r
+325: /* Interrupts are automatically re-enabled when the scheduler is started. */\r
+326: __asm volatile( "di" );\r
+BFD05898 477C0000 DI ZERO
+327: \r
+328: /* Enable M14K Vector Pre-fetch: CP0.IntCtl b[22]=1\r
+329: IRET (interrupt chaining): b[21]=1\r
+330: Enable Auto-Prolog: b[14]=1 */\r
+331: ulTemp = _CP0_GET_INTCTL();\r
+BFD0589C 08FC004C MFC0 V0, IntCtl
+BFD0589E 08FC LBU S1, 12(A3)
+BFD058A0 0010F85E SW V0, 16(S8)
+332: ulTemp |= ( 1ul << 22 ) + ( 1ul << 21 ) + ( 1ul << 14 );\r
+BFD058A4 0010FC7E LW V1, 16(S8)
+BFD058A8 006041A2 LUI V0, 0x60
+BFD058AC 40005042 ORI V0, V0, 16384
+BFD058AE 44D34000 BLTZ ZERO, 0xBFD0E258
+BFD058B0 44D3 OR16 V0, V1
+BFD058B2 0010F85E SW V0, 16(S8)
+333: _CP0_SET_INTCTL( ulTemp );\r
+BFD058B6 0010FC5E LW V0, 16(S8)
+BFD058B8 004C0010 INS ZERO, S0, 1, 0
+BFD058BA 0AFC004C MTC0 V0, IntCtl
+BFD058BC 0AFC LBU A1, 12(A3)
+BFD058BE 18000000 SLL ZERO, ZERO, 3
+BFD058C0 41A21800 SB ZERO, 16802(ZERO)
+334: \r
+335: /* Configure 32KHz for Switched Clock Source always ON\r
+336: b[ 0 ] = XOSEL = 1\r
+337: b[ 1 ] = EXT_32K_OSC_EN = 1\r
+338: b[ 2 ] = INT_32K_OSC_EN = 1\r
+339: b[ 3 ] = INT_32K_VTR_PWR_WELL_EMUL = 0\r
+340: b[ 4 ] = 32K_SWITCHER_CTRL = 0 */\r
+341: VBAT_REGS->CLOCK_ENABLE = 0x07;\r
+BFD058C2 A00041A2 LUI V0, 0xA000
+BFD058C6 A4005042 ORI V0, V0, -23552
+BFD058CA ED87 LI V1, 7
+BFD058CC E9A2 SW V1, 8(V0)
+342: \r
+343: ulTemp = 256;\r
+BFD058CE 01003040 ADDIU V0, ZERO, 256
+344: while (ulTemp--)\r
+BFD058D2 CC06 B 0xBFD058E0
+BFD058D4 0010F85E SW V0, 16(S8)
+BFD058D6 0C000010 SLL ZERO, S0, 1
+BFD058E0 0010FC5E LW V0, 16(S8)
+BFD058E2 00400010 SRL ZERO, S0, 0
+BFD058E4 1B900040 SLTU V1, ZERO, V0
+BFD058E6 2DBD1B90 SB GP, 11709(S0)
+BFD058E8 2DBD ANDI V1, V1, 0xFF
+BFD058EA 6D2E ADDIU V0, V0, -1
+BFD058EC 0010F85E SW V0, 16(S8)
+BFD058F0 FFF240A3 BNEZC V1, 0xBFD058D8
+BFD058F2 41A2FFF2 LW RA, 16802(S2)
+345: {\r
+346: __asm volatile( "NOP" );\r
+BFD058D8 0C00 NOP
+347: __asm volatile( "NOP" );\r
+BFD058DA 0C00 NOP
+348: __asm volatile( "NOP" );\r
+BFD058DC 0C00 NOP
+349: __asm volatile( "NOP" );\r
+BFD058DE 0C00 NOP
+350: }\r
+351: \r
+352: /* Disaggregate GIRQ23 & GIRQ24 for FreeRTOS. Second parameter is a bit-map\r
+353: for each GIRQ where\r
+354: 0 = Aggregated, 1 = Dis-aggregate\r
+355: Bit position = GIRQ_Number - 8\r
+356: Example: GIRQ23 ( 23 - 8 ) = 15\r
+357: Dis-aggregate GIRQ23 & GIRQ24\r
+358: The symbols JTVIC_DISAGR_BITMAP is generated in header file mec14xx_girqm.h\r
+359: \r
+360: Each disaggregated interrupt handler is spaced 8-bytes apart starting at\r
+361: base address for that GIRQ. */\r
+362: jtvic_init( dflt_ih_table, ( JTVIC_DISAGR_BITMAP ), ( JTVIC_FLAG_DISAGR_SPACING_8 ) );\r
+BFD058F4 BFD041A2 LUI V0, 0xBFD0
+BFD058F6 3082BFD0 LDC1 F30, 12418(S0)
+BFD058F8 26F03082 ADDIU A0, V0, 9968
+BFD058FA 26F0 SLL A1, A3, 8
+BFD058FC 000141A2 LUI V0, 0x1
+BFD05900 800050A2 ORI A1, V0, -32768
+BFD05904 1B2277E8 JALS jtvic_init
+BFD05906 0CC01B22 SB T9, 3264(V0)
+BFD05908 0CC0 MOVE A2, ZERO
+363: \r
+364: /* Initialise the LEDs. */\r
+365: for( ulTemp = 0; ulTemp < LED_ID_MAX; ulTemp++ )\r
+BFD0590A CC1A B 0xBFD05940
+BFD0590C 0010F81E SW ZERO, 16(S8)
+BFD05936 0010FC5E LW V0, 16(S8)
+BFD0593A 6D20 ADDIU V0, V0, 1
+BFD0593C 0010F85E SW V0, 16(S8)
+BFD05940 0010FC5E LW V0, 16(S8)
+BFD05944 0003B042 SLTIU V0, V0, 3
+BFD05948 FFE240A2 BNEZC V0, 0xBFD05910
+BFD0594A 0FBEFFE2 LW RA, 4030(V0)
+366: {\r
+367: led_sleep_en( ulTemp, ADISABLE );\r
+BFD05910 0010FC5E LW V0, 16(S8)
+BFD05914 2D2D ANDI V0, V0, 0xFF
+BFD05916 0C82 MOVE A0, V0
+BFD05918 2E8677E8 JALS led_sleep_en
+BFD0591A 2E86 ANDI A1, S0, 0x8
+BFD0591C 0CA0 MOVE A1, ZERO
+368: led_init( ulTemp );\r
+BFD0591E 0010FC5E LW V0, 16(S8)
+BFD05922 2D2D ANDI V0, V0, 0xFF
+BFD05924 3E7E77E8 JALS led_init
+BFD05926 0C823E7E LH S3, 3202(S8)
+BFD05928 0C82 MOVE A0, V0
+369: led_out_low( ulTemp );\r
+BFD0592A 0010FC5E LW V0, 16(S8)
+BFD0592E 2D2D ANDI V0, V0, 0xFF
+BFD05930 4A3077E8 JALS led_out_low
+BFD05932 4A30 LW S1, 64(SP)
+BFD05934 0C82 MOVE A0, V0
+370: }\r
+371: }\r
+BFD0594C 0FBE MOVE SP, S8
+BFD0594E 4BE7 LW RA, 28(SP)
+BFD05950 4BC6 LW S8, 24(SP)
+BFD05952 459F JR16 RA
+BFD05954 4C11 ADDIU SP, SP, 32
+372: /*-----------------------------------------------------------*/\r
+373: \r
+374: void vApplicationMallocFailedHook( void )\r
+375: {\r
+BFD08900 4FF1 ADDIU SP, SP, -32
+BFD08902 CBE7 SW RA, 28(SP)
+BFD08904 CBC6 SW S8, 24(SP)
+BFD08906 0FDD MOVE S8, SP
+376: /* vApplicationMallocFailedHook() will only be called if\r
+377: configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+378: function that will get called if a call to pvPortMalloc() fails.\r
+379: pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+380: timer or semaphore is created. It is also called by various parts of the\r
+381: demo application. If heap_1.c or heap_2.c are used, then the size of the\r
+382: heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+383: FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+384: to query the size of free heap space that remains (although it does not\r
+385: provide information on how the remaining heap might be fragmented). */\r
+386: taskDISABLE_INTERRUPTS();\r
+BFD08908 4EB677E8 JALS ulPortGetCP0Status
+BFD0890A 4EB6 ADDIU S5, S5, -5
+BFD0890C 0C00 NOP
+BFD0890E 0010F85E SW V0, 16(S8)
+BFD08912 0010FC7E LW V1, 16(S8)
+BFD08916 000141A2 LUI V0, 0x1
+BFD0891A FC005042 ORI V0, V0, -1024
+BFD0891C 4493FC00 LW ZERO, 17555(ZERO)
+BFD0891E 4493 AND16 V0, V1
+BFD08920 50400042 SRL V0, V0, 10
+BFD08922 B0425040 ORI V0, ZERO, -20414
+BFD08924 0003B042 SLTIU V0, V0, 3
+BFD08928 001140E2 BEQZC V0, 0xBFD0894E
+BFD0892C 0010FC7E LW V1, 16(S8)
+BFD08930 FFFE41A2 LUI V0, 0xFFFE
+BFD08932 5042FFFE LW RA, 20546(S8)
+BFD08934 03FF5042 ORI V0, V0, 1023
+BFD08938 4493 AND16 V0, V1
+BFD0893A 0010F85E SW V0, 16(S8)
+BFD0893E 0010FC5E LW V0, 16(S8)
+BFD08942 0C005042 ORI V0, V0, 3072
+BFD08944 0C00 NOP
+BFD08946 0C82 MOVE A0, V0
+BFD08948 4EC677E8 JALS vPortSetCP0Status
+BFD0894A 4EC6 ADDIU S6, S6, 3
+BFD0894C 0C00 NOP
+387: for( ;; );\r
+BFD0894E CFFF B 0xBFD0894E
+BFD08950 0C00 NOP
+388: }\r
+389: /*-----------------------------------------------------------*/\r
+390: \r
+391: void vApplicationIdleHook( void )\r
+392: {\r
+BFD09F04 4FB0 ADDIU SP, SP, -8
+BFD09F06 CBC1 SW S8, 4(SP)
+BFD09F08 0FDD MOVE S8, SP
+393: /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+394: to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+395: task. It is essential that code added to this hook function never attempts\r
+396: to block in any way (for example, call xQueueReceive() with a block time\r
+397: specified, or call vTaskDelay()). If the application makes use of the\r
+398: vTaskDelete() API function (as this demo application does) then it is also\r
+399: important that vApplicationIdleHook() is permitted to return to its calling\r
+400: function, because it is the responsibility of the idle task to clean up\r
+401: memory allocated by the kernel to any task that has since been deleted. */\r
+402: }\r
+BFD09F0A 0FBE MOVE SP, S8
+BFD09F0C 4BC1 LW S8, 4(SP)
+BFD09F0E 4C05 ADDIU SP, SP, 8
+BFD09F10 459F JR16 RA
+BFD09F12 0C00 NOP
+403: /*-----------------------------------------------------------*/\r
+404: \r
+405: void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+406: {\r
+BFD08444 4FF1 ADDIU SP, SP, -32
+BFD08446 CBE7 SW RA, 28(SP)
+BFD08448 CBC6 SW S8, 24(SP)
+BFD0844A 0FDD MOVE S8, SP
+BFD0844C 0020F89E SW A0, 32(S8)
+BFD08450 0024F8BE SW A1, 36(S8)
+407: ( void ) pcTaskName;\r
+408: ( void ) pxTask;\r
+409: \r
+410: /* Run time task stack overflow checking is performed if\r
+411: configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is\r
+412: called if a task stack overflow is detected. Note the system/interrupt\r
+413: stack is not checked. */\r
+414: taskDISABLE_INTERRUPTS();\r
+BFD08454 4EB677E8 JALS ulPortGetCP0Status
+BFD08456 4EB6 ADDIU S5, S5, -5
+BFD08458 0C00 NOP
+BFD0845A 0010F85E SW V0, 16(S8)
+BFD0845E 0010FC7E LW V1, 16(S8)
+BFD08462 000141A2 LUI V0, 0x1
+BFD08466 FC005042 ORI V0, V0, -1024
+BFD08468 4493FC00 LW ZERO, 17555(ZERO)
+BFD0846A 4493 AND16 V0, V1
+BFD0846C 50400042 SRL V0, V0, 10
+BFD0846E B0425040 ORI V0, ZERO, -20414
+BFD08470 0003B042 SLTIU V0, V0, 3
+BFD08474 001140E2 BEQZC V0, 0xBFD0849A
+BFD08478 0010FC7E LW V1, 16(S8)
+BFD0847C FFFE41A2 LUI V0, 0xFFFE
+BFD0847E 5042FFFE LW RA, 20546(S8)
+BFD08480 03FF5042 ORI V0, V0, 1023
+BFD08484 4493 AND16 V0, V1
+BFD08486 0010F85E SW V0, 16(S8)
+BFD0848A 0010FC5E LW V0, 16(S8)
+BFD0848E 0C005042 ORI V0, V0, 3072
+BFD08490 0C00 NOP
+BFD08492 0C82 MOVE A0, V0
+BFD08494 4EC677E8 JALS vPortSetCP0Status
+BFD08496 4EC6 ADDIU S6, S6, 3
+BFD08498 0C00 NOP
+415: for( ;; );\r
+BFD0849A CFFF B 0xBFD0849A
+BFD0849C 0C00 NOP
+416: }\r
+417: /*-----------------------------------------------------------*/\r
+418: \r
+419: void vApplicationTickHook( void )\r
+420: {\r
+BFD09F14 4FB0 ADDIU SP, SP, -8
+BFD09F16 CBC1 SW S8, 4(SP)
+BFD09F18 0FDD MOVE S8, SP
+421: /* This function will be called by each tick interrupt if\r
+422: configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+423: added here, but the tick hook is called from an interrupt context, so\r
+424: code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+425: functions can be used (those that end in FromISR()). */\r
+426: }\r
+BFD09F1A 0FBE MOVE SP, S8
+BFD09F1C 4BC1 LW S8, 4(SP)
+BFD09F1E 4C05 ADDIU SP, SP, 8
+BFD09F20 459F JR16 RA
+BFD09F22 0C00 NOP
+427: /*-----------------------------------------------------------*/\r
+428: \r
+429: void vAssertCalled( const char * pcFile, unsigned long ulLine )\r
+430: {\r
+BFD096FC 4FF9 ADDIU SP, SP, -16
+BFD096FE CBC3 SW S8, 12(SP)
+BFD09700 0FDD MOVE S8, SP
+BFD09702 0010F89E SW A0, 16(S8)
+BFD09706 0014F8BE SW A1, 20(S8)
+431: volatile char *pcFileName;\r
+432: volatile unsigned long ulLineNumber;\r
+433: \r
+434: /* Prevent things that are useful to view in the debugger from being\r
+435: optimised away. */\r
+436: pcFileName = ( char * ) pcFile;\r
+BFD0970A 0010FC5E LW V0, 16(S8)
+BFD0970E 0000F85E SW V0, 0(S8)
+437: ( void ) pcFileName;\r
+438: ulLineNumber = ulLine;\r
+BFD09712 0014FC5E LW V0, 20(S8)
+BFD09716 0004F85E SW V0, 4(S8)
+439: \r
+440: /* Set ulLineNumber to 0 in the debugger to break out of this loop and\r
+441: return to the line that triggered the assert. */\r
+442: while( ulLineNumber != 0 )\r
+BFD0971A CC06 B 0xBFD09728
+BFD0971C 0C00 NOP
+BFD09728 0004FC5E LW V0, 4(S8)
+BFD0972C FFF740A2 BNEZC V0, 0xBFD0971E
+BFD0972E 0FBEFFF7 LW RA, 4030(S7)
+443: {\r
+444: __asm volatile( "NOP" );\r
+BFD0971E 0C00 NOP
+445: __asm volatile( "NOP" );\r
+BFD09720 0C00 NOP
+446: __asm volatile( "NOP" );\r
+BFD09722 0C00 NOP
+447: __asm volatile( "NOP" );\r
+BFD09724 0C00 NOP
+448: __asm volatile( "NOP" );\r
+BFD09726 0C00 NOP
+449: }\r
+450: }\r
+BFD09730 0FBE MOVE SP, S8
+BFD09732 4BC3 LW S8, 12(SP)
+BFD09734 459F JR16 RA
+BFD09736 4C09 ADDIU SP, SP, 16
+451: \r
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S --------------
+ 1: /*\r
+ 2: FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ 3: All rights reserved\r
+ 4: \r
+ 5: VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+ 6: \r
+ 7: This file is part of the FreeRTOS distribution.\r
+ 8: \r
+ 9: FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ 10: the terms of the GNU General Public License (version 2) as published by the\r
+ 11: Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+ 12: \r
+ 13: ***************************************************************************\r
+ 14: >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ 15: >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ 16: >>! obliged to provide the source code for proprietary components !<<\r
+ 17: >>! outside of the FreeRTOS kernel. !<<\r
+ 18: ***************************************************************************\r
+ 19: \r
+ 20: FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ 21: WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ 22: FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ 23: link: http://www.freertos.org/a00114.html\r
+ 24: \r
+ 25: ***************************************************************************\r
+ 26: * *\r
+ 27: * FreeRTOS provides completely free yet professionally developed, *\r
+ 28: * robust, strictly quality controlled, supported, and cross *\r
+ 29: * platform software that is more than just the market leader, it *\r
+ 30: * is the industry's de facto standard. *\r
+ 31: * *\r
+ 32: * Help yourself get started quickly while simultaneously helping *\r
+ 33: * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ 34: * tutorial book, reference manual, or both: *\r
+ 35: * http://www.FreeRTOS.org/Documentation *\r
+ 36: * *\r
+ 37: ***************************************************************************\r
+ 38: \r
+ 39: http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ 40: the FAQ page "My application does not run, what could be wrong?". Have you\r
+ 41: defined configASSERT()?\r
+ 42: \r
+ 43: http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ 44: embedded software for free we request you assist our global community by\r
+ 45: participating in the support forum.\r
+ 46: \r
+ 47: http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ 48: be as productive as possible as early as possible. Now you can receive\r
+ 49: FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ 50: Ltd, and the world's leading authority on the world's leading RTOS.\r
+ 51: \r
+ 52: http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ 53: including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ 54: compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+ 55: \r
+ 56: http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ 57: Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+ 58: \r
+ 59: http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ 60: Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ 61: licenses offer ticketed support, indemnification and commercial middleware.\r
+ 62: \r
+ 63: http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ 64: engineered and independently SIL3 certified version for use in safety and\r
+ 65: mission critical applications that require provable dependability.\r
+ 66: \r
+ 67: 1 tab == 4 spaces!\r
+ 68: */\r
+ 69: \r
+ 70: #include <xc.h>\r
+ 71: #include <sys/asm.h>\r
+ 72: #include "FreeRTOSConfig.h"\r
+ 73: #include "ISR_Support.h"\r
+ 74: \r
+ 75: \r
+ 76: .extern pxCurrentTCB\r
+ 77: .extern vTaskSwitchContext\r
+ 78: .extern vPortIncrementTick\r
+ 79: .extern xISRStackTop\r
+ 80: \r
+ 81: PORT_CPP_JTVIC_BASE = 0xBFFFC000\r
+ 82: PORT_CCP_JTVIC_GIRQ24_SRC = 0xBFFFC100\r
+ 83: \r
+ 84: .global vPortStartFirstTask .text\r
+ 85: .global vPortYieldISR .text\r
+ 86: .global vPortTickInterruptHandler .text\r
+ 87: \r
+ 88: \r
+ 89: /******************************************************************/\r
+ 90: \r
+ 91: \r
+ 92: /***************************************************************\r
+ 93: * The following is needed to locate the\r
+ 94: * vPortTickInterruptHandler function into the correct vector\r
+ 95: * MEC14xx - This ISR will only be used if HW timers' interrupts\r
+ 96: * in GIRQ23 are disaggregated.\r
+ 97: *\r
+ 98: ***************************************************************/\r
+ 99: \r
+ 100: .set noreorder\r
+ 101: .set noat\r
+ 102: .set micromips\r
+ 103: \r
+ 104: .section .text, code\r
+ 105: .ent vPortTickInterruptHandler\r
+ 106: \r
+ 107: #if configTIMERS_DISAGGREGATED_ISRS == 0\r
+ 108: \r
+ 109: .globl girq23_isr\r
+ 110: \r
+ 111: girq23_isr:\r
+ 112: vPortTickInterruptHandler:\r
+ 113: \r
+ 114: portSAVE_CONTEXT2 vpti\r
+ 115: \r
+ 116: jal girq23_handler\r
+ 117: nop\r
+ 118: \r
+ 119: portRESTORE_CONTEXT\r
+ 120: \r
+ 121: .end vPortTickInterruptHandler\r
+ 122: \r
+ 123: #else\r
+ 124: \r
+ 125: .globl girq23_b4\r
+ 126: \r
+ 127: girq23_b4:\r
+ 128: vPortTickInterruptHandler:\r
+ 129: \r
+ 130: /* portSAVE_CONTEXT */\r
+BFD00920 00FC034D MFC0 K0, Cause 131: portSAVE_CONTEXT2 vpti\r
+ 132: \r
+BFD009F0 34DCF7E8 JAL 0xBFD069B8 133: jal vPortIncrementTick\r
+BFD009F4 00000000 NOP 134: nop\r
+ 135: \r
+BFD009F8 BFD241B6 LUI S6, 0xBFD2 136: portRESTORE_CONTEXT\r
+ 137: \r
+ 138: .end vPortTickInterruptHandler\r
+ 139: \r
+ 140: #endif /* #if configTIMERS_DISAGGREGATED_ISRS == 0 */\r
+ 141: \r
+ 142: /******************************************************************/\r
+ 143: \r
+ 144: .set micromips\r
+ 145: .set noreorder\r
+ 146: .set noat\r
+ 147: \r
+ 148: .section .text, code\r
+ 149: .ent vPortStartFirstTask\r
+ 150: \r
+ 151: vPortStartFirstTask:\r
+ 152: \r
+ 153: /* Simply restore the context of the highest priority task that has\r
+ 154: been created so far. */\r
+BFD00AB4 BFD241B6 LUI S6, 0xBFD2 155: portRESTORE_CONTEXT\r
+ 156: \r
+ 157: .end vPortStartFirstTask\r
+ 158: \r
+ 159: \r
+ 160: \r
+ 161: /*******************************************************************/\r
+ 162: \r
+ 163: /***************************************************************\r
+ 164: * The following is needed to locate the vPortYieldISR function\r
+ 165: * into the correct vector\r
+ 166: ***************************************************************/\r
+ 167: \r
+ 168: .set micromips\r
+ 169: .set noreorder\r
+ 170: .set noat\r
+ 171: \r
+ 172: .section .text, code\r
+ 173: \r
+ 174: .global vPortYieldISR\r
+ 175: \r
+ 176: \r
+ 177: #if configCPU_DISAGGREGATED_ISRS == 0\r
+ 178: .global girq24_isr\r
+ 179: .ent girq24_isr\r
+ 180: girq24_isr:\r
+ 181: la k0, PORT_CPP_JTVIC_BASE\r
+ 182: lw k0, 0x10C(k0)\r
+ 183: andi k1, k0, 0x2\r
+ 184: bgtz k1, vPortYieldISR\r
+ 185: nop\r
+ 186: \r
+ 187: portSAVE_CONTEXT\r
+ 188: \r
+ 189: jal girq24_b_0_2\r
+ 190: \r
+ 191: portRESTORE_CONTEXT\r
+ 192: \r
+ 193: .end girq24_isr\r
+ 194: \r
+ 195: #else\r
+ 196: .global girq24_b1\r
+ 197: girq24_b1:\r
+ 198: #endif\r
+ 199: .ent vPortYieldISR\r
+ 200: vPortYieldISR:\r
+ 201: \r
+ 202: /* Make room for the context. First save the current status so it can be\r
+ 203: manipulated, and the cause and EPC registers so thier original values\r
+ 204: are captured. */\r
+BFD00B70 4FBF ADDIU SP, SP, -132 205: addiu sp, sp, -portCONTEXT_SIZE\r
+BFD00B72 00FC036C MFC0 K1, Status 206: mfc0 k1, _CP0_STATUS\r
+ 207: \r
+ 208: /* Also save s6 and s5 so they can be used. Any nesting interrupts should\r
+ 209: maintain the values of these registers across the ISR. */\r
+BFD00B76 CACB SW S6, 44(SP) 210: sw s6, 44(sp)\r
+BFD00B78 CAAA SW S5, 40(SP) 211: sw s5, 40(sp)\r
+BFD00B7A 0080FB7D SW K1, 128(SP) 212: sw k1, portSTATUS_STACK_LOCATION(sp)\r
+ 213: \r
+ 214: /* Prepare to re-enabled interrupts above the kernel priority. */\r
+BFD00B7E 828C0360 INS K1, ZERO, 10, 7 215: ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */\r
+BFD00B82 948C0360 INS K1, ZERO, 18, 1 216: ins k1, zero, 18, 1 /* Clear IPL bit 7 */\r
+BFD00B86 0C00537B ORI K1, K1, 3072 217: ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )\r
+BFD00B8A 204C0360 INS K1, ZERO, 1, 4 218: ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */\r
+ 219: \r
+ 220: /* s5 is used as the frame pointer. */\r
+BFD00B8E A91003A0 ADD S5, ZERO, SP 221: add s5, zero, sp\r
+ 222: \r
+ 223: /* Swap to the system stack. This is not conditional on the nesting\r
+ 224: count as this interrupt is always the lowest priority and therefore\r
+ 225: the nesting is always 0. */\r
+BFD00B92 BFD141BD LUI SP, 0xBFD1 226: la sp, xISRStackTop\r
+BFD00B9A 4BA0 LW SP, 0(SP) 227: lw sp, (sp)\r
+ 228: \r
+ 229: /* Set the nesting count. */\r
+BFD00B9C BFD241BA LUI K0, 0xBFD2 230: la k0, uxInterruptNesting\r
+BFD00BA4 000132C0 ADDIU S6, ZERO, 1 231: addiu s6, zero, 1\r
+BFD00BA8 0000FADA SW S6, 0(K0) 232: sw s6, 0(k0)\r
+ 233: \r
+ 234: /* s6 holds the EPC value, this is saved with the rest of the context\r
+ 235: after interrupts are enabled. */\r
+BFD00BAC 00FC02CE MFC0 S6, EPC 236: mfc0 s6, _CP0_EPC\r
+ 237: \r
+ 238: /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+BFD00BB0 02FC036C MTC0 K1, Status 239: mtc0 k1, _CP0_STATUS\r
+ 240: \r
+ 241: /* Save the context into the space just created. s6 is saved again\r
+ 242: here as it now contains the EPC value. */\r
+BFD00BB4 0078FBF5 SW RA, 120(S5) 243: sw ra, 120(s5)\r
+BFD00BB8 0074FBD5 SW S8, 116(S5) 244: sw s8, 116(s5)\r
+BFD00BBC 0070FB35 SW T9, 112(S5) 245: sw t9, 112(s5)\r
+BFD00BC0 006CFB15 SW T8, 108(S5) 246: sw t8, 108(s5)\r
+BFD00BC4 0068F9F5 SW T7, 104(S5) 247: sw t7, 104(s5)\r
+BFD00BC8 0064F9D5 SW T6, 100(S5) 248: sw t6, 100(s5)\r
+BFD00BCC 0060F9B5 SW T5, 96(S5) 249: sw t5, 96(s5)\r
+BFD00BD0 005CF995 SW T4, 92(S5) 250: sw t4, 92(s5)\r
+BFD00BD4 0058F975 SW T3, 88(S5) 251: sw t3, 88(s5)\r
+BFD00BD8 0054F955 SW T2, 84(S5) 252: sw t2, 84(s5)\r
+BFD00BDC 0050F935 SW T1, 80(S5) 253: sw t1, 80(s5)\r
+BFD00BE0 004CF915 SW T0, 76(S5) 254: sw t0, 76(s5)\r
+BFD00BE4 0048F8F5 SW A3, 72(S5) 255: sw a3, 72(s5)\r
+BFD00BE8 0044F8D5 SW A2, 68(S5) 256: sw a2, 68(s5)\r
+BFD00BEC 0040F8B5 SW A1, 64(S5) 257: sw a1, 64(s5)\r
+BFD00BF0 003CF895 SW A0, 60(S5) 258: sw a0, 60(s5)\r
+BFD00BF4 0038F875 SW V1, 56(S5) 259: sw v1, 56(s5)\r
+BFD00BF8 0034F855 SW V0, 52(S5) 260: sw v0, 52(s5)\r
+BFD00BFC 0030FAF5 SW S7, 48(S5) 261: sw s7, 48(s5)\r
+BFD00C00 007CFAD5 SW S6, 124(S5) 262: sw s6, portEPC_STACK_LOCATION(s5)\r
+ 263: /* s5 and s6 has already been saved. */\r
+BFD00C04 0024FA95 SW S4, 36(S5) 264: sw s4, 36(s5)\r
+BFD00C08 0020FA75 SW S3, 32(S5) 265: sw s3, 32(s5)\r
+BFD00C0C 001CFA55 SW S2, 28(S5) 266: sw s2, 28(s5)\r
+BFD00C10 0018FA35 SW S1, 24(S5) 267: sw s1, 24(s5)\r
+BFD00C14 0014FA15 SW S0, 20(S5) 268: sw s0, 20(s5)\r
+BFD00C18 0010F835 SW AT, 16(S5) 269: sw $1, 16(s5)\r
+ 270: \r
+ 271: /* s7 is used as a scratch register as this should always be saved acro ss\r
+ 272: nesting interrupts. */\r
+BFD00C1C 4617 MFHI S7 273: mfhi s7\r
+BFD00C1E 000CFAF5 SW S7, 12(S5) 274: sw s7, 12(s5)\r
+BFD00C22 4657 MFLO S7 275: mflo s7\r
+BFD00C24 0008FAF5 SW S7, 8(S5) 276: sw s7, 8(s5)\r
+ 277: \r
+ 278: /* Save the stack pointer to the task. */\r
+BFD00C28 BFD241B7 LUI S7, 0xBFD2 279: la s7, pxCurrentTCB\r
+BFD00C30 0000FEF7 LW S7, 0(S7) 280: lw s7, (s7)\r
+BFD00C34 0000FAB7 SW S5, 0(S7) 281: sw s5, (s7)\r
+ 282: \r
+ 283: /* Set the interrupt mask to the max priority that can use the API.\r
+ 284: The yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY\r
+ 285: which is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only\r
+ 286: ever raise the IPL value and never lower it. */\r
+BFD00C38 477C0000 DI ZERO 287: di\r
+BFD00C3C 18000000 SLL ZERO, ZERO, 3 288: ehb\r
+BFD00C40 00FC02EC MFC0 S7, Status 289: mfc0 s7, _CP0_STATUS\r
+BFD00C44 828C02E0 INS S7, ZERO, 10, 7 290: ins s7, zero, 10, 7\r
+BFD00C48 948C02E0 INS S7, ZERO, 18, 1 291: ins s7, zero, 18, 1\r
+BFD00C4C 0C0152D7 ORI S6, S7, 3073 292: ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1\r
+ 293: \r
+ 294: /* This mtc0 re-enables interrupts, but only above\r
+ 295: configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
+BFD00C50 02FC02CC MTC0 S6, Status 296: mtc0 s6, _CP0_STATUS\r
+BFD00C54 18000000 SLL ZERO, ZERO, 3 297: ehb\r
+ 298: \r
+ 299: /* Clear the software interrupt in the core. */\r
+BFD00C58 00FC02CD MFC0 S6, Cause 300: mfc0 s6, _CP0_CAUSE\r
+BFD00C5C 420C02C0 INS S6, ZERO, 8, 1 301: ins s6, zero, 8, 1\r
+BFD00C60 02FC02CD MTC0 S6, Cause 302: mtc0 s6, _CP0_CAUSE\r
+BFD00C64 18000000 SLL ZERO, ZERO, 3 303: ehb\r
+ 304: \r
+ 305: /* Clear the interrupt in the interrupt controller.\r
+ 306: MEC14xx GIRQ24 Source bit[1] = 1 to clear */\r
+BFD00C68 BFFF41B6 LUI S6, 0xBFFF 307: la s6, PORT_CCP_JTVIC_GIRQ24_SRC\r
+BFD00C70 00023280 ADDIU S4, ZERO, 2 308: addiu s4, zero, 2\r
+BFD00C74 0000FA96 SW S4, 0(S6) 309: sw s4, (s6)\r
+BFD00C78 16DEF7E8 JAL 0xBFD02DBC 310: jal vTaskSwitchContext\r
+BFD00C7C 00000000 NOP 311: nop\r
+ 312: \r
+ 313: /* Clear the interrupt mask again. The saved status value is still in s7 */\r
+BFD00C80 02FC02EC MTC0 S7, Status 314: mtc0 s7, _CP0_STATUS\r
+BFD00C84 18000000 SLL ZERO, ZERO, 3 315: ehb\r
+ 316: \r
+ 317: /* Restore the stack pointer from the TCB. */\r
+BFD00C88 BFD241B0 LUI S0, 0xBFD2 318: la s0, pxCurrentTCB\r
+BFD00C90 6800 LW S0, 0(S0) 319: lw s0, (s0)\r
+BFD00C92 0000FEB0 LW S5, 0(S0) 320: lw s5, (s0)\r
+ 321: \r
+ 322: /* Restore the rest of the context. */\r
+BFD00C96 0008FE15 LW S0, 8(S5) 323: lw s0, 8(s5)\r
+BFD00C9A 3D7C0010 MTLO S0 324: mtlo s0\r
+BFD00C9E 000CFE15 LW S0, 12(S5) 325: lw s0, 12(s5)\r
+BFD00CA2 2D7C0010 MTHI S0 326: mthi s0\r
+ 327: \r
+BFD00CA6 0010FC35 LW AT, 16(S5) 328: lw $1, 16(s5)\r
+BFD00CAA 0014FE15 LW S0, 20(S5) 329: lw s0, 20(s5)\r
+BFD00CAE 0018FE35 LW S1, 24(S5) 330: lw s1, 24(s5)\r
+BFD00CB2 001CFE55 LW S2, 28(S5) 331: lw s2, 28(s5)\r
+BFD00CB6 0020FE75 LW S3, 32(S5) 332: lw s3, 32(s5)\r
+BFD00CBA 0024FE95 LW S4, 36(S5) 333: lw s4, 36(s5)\r
+ 334: \r
+ 335: /* s5 is loaded later. */\r
+BFD00CBE 002CFED5 LW S6, 44(S5) 336: lw s6, 44(s5)\r
+BFD00CC2 0030FEF5 LW S7, 48(S5) 337: lw s7, 48(s5)\r
+BFD00CC6 0034FC55 LW V0, 52(S5) 338: lw v0, 52(s5)\r
+BFD00CCA 0038FC75 LW V1, 56(S5) 339: lw v1, 56(s5)\r
+BFD00CCE 003CFC95 LW A0, 60(S5) 340: lw a0, 60(s5)\r
+BFD00CD2 0040FCB5 LW A1, 64(S5) 341: lw a1, 64(s5)\r
+BFD00CD6 0044FCD5 LW A2, 68(S5) 342: lw a2, 68(s5)\r
+BFD00CDA 0048FCF5 LW A3, 72(S5) 343: lw a3, 72(s5)\r
+BFD00CDE 004CFD15 LW T0, 76(S5) 344: lw t0, 76(s5)\r
+BFD00CE2 0050FD35 LW T1, 80(S5) 345: lw t1, 80(s5)\r
+BFD00CE6 0054FD55 LW T2, 84(S5) 346: lw t2, 84(s5)\r
+BFD00CEA 0058FD75 LW T3, 88(S5) 347: lw t3, 88(s5)\r
+BFD00CEE 005CFD95 LW T4, 92(S5) 348: lw t4, 92(s5)\r
+BFD00CF2 0060FDB5 LW T5, 96(S5) 349: lw t5, 96(s5)\r
+BFD00CF6 0064FDD5 LW T6, 100(S5) 350: lw t6, 100(s5)\r
+BFD00CFA 0068FDF5 LW T7, 104(S5) 351: lw t7, 104(s5)\r
+BFD00CFE 006CFF15 LW T8, 108(S5) 352: lw t8, 108(s5)\r
+BFD00D02 0070FF35 LW T9, 112(S5) 353: lw t9, 112(s5)\r
+BFD00D06 0074FFD5 LW S8, 116(S5) 354: lw s8, 116(s5)\r
+BFD00D0A 0078FFF5 LW RA, 120(S5) 355: lw ra, 120(s5)\r
+ 356: \r
+ 357: /* Protect access to the k registers, and others. */\r
+BFD00D0E 477C0000 DI ZERO 358: di\r
+BFD00D12 18000000 SLL ZERO, ZERO, 3 359: ehb\r
+ 360: \r
+ 361: /* Set nesting back to zero. As the lowest priority interrupt this\r
+ 362: interrupt cannot have nested. */\r
+BFD00D16 BFD241BA LUI K0, 0xBFD2 363: la k0, uxInterruptNesting\r
+BFD00D1E 0000F81A SW ZERO, 0(K0) 364: sw zero, 0(k0)\r
+ 365: \r
+ 366: /* Switch back to use the real stack pointer. */\r
+BFD00D22 E91002A0 ADD SP, ZERO, S5 367: add sp, zero, s5\r
+ 368: \r
+ 369: /* Restore the real s5 value. */\r
+BFD00D26 4AAA LW S5, 40(SP) 370: lw s5, 40(sp)\r
+ 371: \r
+ 372: /* Pop the status and epc values. */\r
+BFD00D28 0080FF7D LW K1, 128(SP) 373: lw k1, portSTATUS_STACK_LOCATION(sp)\r
+BFD00D2C 4B5F LW K0, 124(SP) 374: lw k0, portEPC_STACK_LOCATION(sp)\r
+ 375: \r
+ 376: /* Remove stack frame. */\r
+BFD00D2E 4C43 ADDIU SP, SP, 132 377: addiu sp, sp, portCONTEXT_SIZE\r
+ 378: \r
+BFD00D30 02FC036C MTC0 K1, Status 379: mtc0 k1, _CP0_STATUS\r
+BFD00D34 02FC034E MTC0 K0, EPC 380: mtc0 k0, _CP0_EPC\r
+BFD00D38 18000000 SLL ZERO, ZERO, 3 381: ehb\r
+BFD00D3C F37C0000 ERET 382: eret\r
+BFD00D40 0C00 NOP 383: nop\r
+ 384: \r
+ 385: .end vPortYieldISR\r
+ 386: \r
+ 387: \r
+ 388: \r
+ 389: \r
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crtn.S ---
+ 1: /*********************************************************************\r
+ 2: *\r
+ 3: * C Runtime Startup\r
+ 4: *\r
+ 5: *********************************************************************\r
+ 6: * Filename: crtn.s\r
+ 7: *\r
+ 8: * Processor: PIC32\r
+ 9: *\r
+ 10: * Compiler: MPLAB XC32\r
+ 11: * MPLAB X IDE\r
+ 12: * Company: Microchip Technology Inc.\r
+ 13: *\r
+ 14: * Software License Agreement\r
+ 15: *\r
+ 16: * This software is developed by Microchip Technology Inc. and its\r
+ 17: * subsidiaries ("Microchip").\r
+ 18: *\r
+ 19: * Redistribution and use in source and binary forms, with or without\r
+ 20: * modification, are permitted provided that the following conditions are met:\r
+ 21: *\r
+ 22: * 1. Redistributions of source code must retain the above copyright\r
+ 23: * notice, this list of conditions and the following disclaimer.\r
+ 24: *\r
+ 25: * 2. Redistributions in binary form must reproduce the above copyright\r
+ 26: * notice, this list of conditions and the following disclaimer in the\r
+ 27: * documentation and/or other materials provided with the distribution.\r
+ 28: *\r
+ 29: * 3. Microchip's name may not be used to endorse or promote products\r
+ 30: * derived from this software without specific prior written permission.\r
+ 31: *\r
+ 32: * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ 33: * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ 34: * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL\r
+ 35: * MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ 36: * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO\r
+ 37: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;\r
+ 38: * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ 39: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ 40: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\r
+ 41: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ 42: *\r
+ 43: ********************************************************************/\r
+ 44: \r
+ 45: #ifdef __LIBBUILD__\r
+ 46: # Replace the standard debugging information with a simple filename. This \r
+ 47: # prevents the library build directory from showing up in MPLAB IDE. It \r
+ 48: # also effectively disables source-line debugging.\r
+ 49: .file 1 "libpic32/startup/crtn.s"\r
+ 50: .loc 1 0\r
+ 51: #endif\r
+ 52: \r
+ 53: .section .init, code\r
+BFD00440 8FBF0014 LW RA, 20(SP) 54: lw $31,20($sp)\r
+ 55: addu $sp,$sp,32\r
+BFD00444 03E00008 JR RA 56: j $31\r
+ 57: \r
+ 58: .section .fini, code\r
+BFD00454 8FBF0014 LW RA, 20(SP) 59: lw $31,20($sp)\r
+ 60: addu $sp,$sp,32\r
+BFD00458 03E00008 JR RA 61: j $31\r
+ 62: \r
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crti.S ---
+ 1: /*********************************************************************\r
+ 2: *\r
+ 3: * C Runtime Startup\r
+ 4: *\r
+ 5: *********************************************************************\r
+ 6: * Filename: crti.s\r
+ 7: *\r
+ 8: * Processor: PIC32\r
+ 9: *\r
+ 10: * Compiler: MPLAB XC32\r
+ 11: * MPLAB X IDE\r
+ 12: * Company: Microchip Technology Inc.\r
+ 13: *\r
+ 14: * Software License Agreement\r
+ 15: *\r
+ 16: * This software is developed by Microchip Technology Inc. and its\r
+ 17: * subsidiaries ("Microchip").\r
+ 18: *\r
+ 19: * Redistribution and use in source and binary forms, with or without\r
+ 20: * modification, are permitted provided that the following conditions are met:\r
+ 21: *\r
+ 22: * 1. Redistributions of source code must retain the above copyright\r
+ 23: * notice, this list of conditions and the following disclaimer.\r
+ 24: *\r
+ 25: * 2. Redistributions in binary form must reproduce the above copyright\r
+ 26: * notice, this list of conditions and the following disclaimer in the\r
+ 27: * documentation and/or other materials provided with the distribution.\r
+ 28: *\r
+ 29: * 3. Microchip's name may not be used to endorse or promote products\r
+ 30: * derived from this software without specific prior written permission.\r
+ 31: *\r
+ 32: * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ 33: * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ 34: * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL\r
+ 35: * MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ 36: * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO\r
+ 37: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;\r
+ 38: * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ 39: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ 40: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\r
+ 41: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ 42: *\r
+ 43: ********************************************************************/\r
+ 44: \r
+ 45: #ifdef __LIBBUILD__\r
+ 46: # Replace the standard debugging information with a simple filename. This \r
+ 47: # prevents the library build directory from showing up in MPLAB IDE. It \r
+ 48: # also effectively disables source-line debugging.\r
+ 49: .file 1 "libpic32/startup/crti.s"\r
+ 50: .loc 1 0\r
+ 51: #endif\r
+ 52: \r
+ 53: /* 4 slots for argument spill area. 1 for cpreturn, 1 for stack.\r
+ 54: Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */\r
+ 55: \r
+ 56: .section .init, code\r
+ 57: .globl _init\r
+ 58: .type _init,@function\r
+ 59: _init:\r
+BFD00438 27BDFFE0 ADDIU SP, SP, -32 60: addu $sp,$sp,-32\r
+BFD0043C AFBF0014 SW RA, 20(SP) 61: sw $31,20($sp)\r
+ 62: \r
+ 63: .section .fini, code\r
+ 64: .globl _fini\r
+ 65: .type _fini,@function\r
+ 66: _fini:\r
+BFD0044C 27BDFFE0 ADDIU SP, SP, -32 67: addu $sp,$sp,-32\r
+BFD00450 AFBF0014 SW RA, 20(SP) 68: sw $31,20($sp)\r
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crt0.S ---
+ 1: /*********************************************************************\r
+ 2: *\r
+ 3: * C Runtime Startup\r
+ 4: *\r
+ 5: *********************************************************************\r
+ 6: * Filename: crt0.S\r
+ 7: *\r
+ 8: * Processor: PIC32\r
+ 9: *\r
+ 10: * Compiler: MPLAB XC32\r
+ 11: * MPLAB X IDE\r
+ 12: * Company: Microchip Technology Inc.\r
+ 13: *\r
+ 14: * Software License Agreement\r
+ 15: *\r
+ 16: * This software is developed by Microchip Technology Inc. and its\r
+ 17: * subsidiaries ("Microchip").\r
+ 18: *\r
+ 19: * Redistribution and use in source and binary forms, with or without\r
+ 20: * modification, are permitted provided that the following conditions are met:\r
+ 21: *\r
+ 22: * 1. Redistributions of source code must retain the above copyright\r
+ 23: * notice, this list of conditions and the following disclaimer.\r
+ 24: *\r
+ 25: * 2. Redistributions in binary form must reproduce the above copyright\r
+ 26: * notice, this list of conditions and the following disclaimer in the\r
+ 27: * documentation and/or other materials provided with the distribution.\r
+ 28: *\r
+ 29: * 3. Microchip's name may not be used to endorse or promote products\r
+ 30: * derived from this software without specific prior written permission.\r
+ 31: *\r
+ 32: * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ 33: * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ 34: * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL\r
+ 35: * MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ 36: * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO\r
+ 37: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;\r
+ 38: * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ 39: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ 40: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\r
+ 41: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ 42: *\r
+ 43: ********************************************************************/\r
+ 44: \r
+ 45: #include <xc.h>\r
+ 46: #include <cp0defs.h>\r
+ 47: \r
+ 48: /* MEC14xx */\r
+ 49: #define PIC32_SRS_SET_COUNT 1\r
+ 50: #define INIT_SSX\r
+ 51: #undef INIT_MMU_MZ_FIXED\r
+ 52: #undef INIT_L1_CACHE\r
+ 53: \r
+ 54: /* MEC14xx fill stack with sentinel value */\r
+ 55: #define EN_STACK_FILL */\r
+ 56: \r
+ 57: #if (__XC32_VERSION > 1000) && !defined(CPP_INIT)\r
+ 58: #define CPP_INIT\r
+ 59: #endif\r
+ 60: \r
+ 61: #if !defined(PIC32_SRS_SET_COUNT)\r
+ 62: # warning PIC32_SRS_SET_COUNT not defined on build line\r
+ 63: # define PIC32_SRS_SET_COUNT 2\r
+ 64: #endif\r
+ 65: \r
+ 66: #if !defined(STACK_FILL_VALUE)\r
+ 67: # define STACK_FILL_VALUE 0xDEADBEEFul\r
+ 68: #endif\r
+ 69: \r
+ 70: /* This file contains 32-bit assembly code */\r
+ 71: .set nomips16\r
+ 72: \r
+ 73: ##################################################################\r
+ 74: # Entry point of the entire application\r
+ 75: ##################################################################\r
+ 76: .section .reset,code,keep\r
+ 77: .align 2\r
+ 78: .set noreorder\r
+ 79: .ent _reset\r
+ 80: \r
+ 81: ############################\r
+ 82: # Begin ISA switching code #\r
+ 83: ############################\r
+ 84: \r
+ 85: #if defined(__PIC32_HAS_MICROMIPS) || defined(__mips_micromips)\r
+ 86: #if defined (__mips_micromips)\r
+ 87: .set micromips\r
+ 88: #endif\r
+ 89: _reset:\r
+ 90: .word 0x10000003 /* MIPS32: branch to 0xBFC00010 from here */\r
+ 91: /* MicroMIPS: ADDI32 $0, $0, 0x0007 (nop) */\r
+ 92: /* DO NOT change the relative branch */\r
+ 93: \r
+ 94: .word 0x00000000 /* NOP */\r
+ 95: __reset_micromips_isa:\r
+ 96: .set micromips\r
+ 97: jal _startup\r
+ 98: nop\r
+ 99: \r
+ 100: .align 2\r
+ 101: /* Device not in proper ISA mode */\r
+ 102: .set nomicromips\r
+ 103: __reset_switch_isa:\r
+ 104: jal _startup\r
+ 105: nop\r
+ 106: \r
+ 107: #else\r
+ 108: \r
+ 109: _reset:\r
+BFD00000 0FF400A2 JAL 0xBFD00288 110: jal _startup\r
+BFD00004 00000000 NOP 111: nop\r
+ 112: \r
+ 113: #endif /* __PIC32_HAS_MICROMIPS */\r
+ 114: \r
+ 115: .align 2\r
+ 116: .end _reset\r
+ 117: .globl _reset\r
+ 118: .size _reset, .-_reset\r
+ 119: \r
+ 120: .section .reset.startup,code,keep\r
+ 121: .align 2\r
+ 122: .set noreorder\r
+ 123: \r
+ 124: #if defined (__mips_micromips)\r
+ 125: .set micromips\r
+ 126: #else\r
+ 127: .set nomicromips\r
+ 128: #endif\r
+ 129: \r
+ 130: ############################\r
+ 131: # End ISA switching code #\r
+ 132: ############################\r
+ 133: \r
+ 134: \r
+ 135: ##################################################################\r
+ 136: # Startup code\r
+ 137: ##################################################################\r
+ 138: .align 2\r
+ 139: .set noreorder\r
+ 140: .ent _startup\r
+ 141: _startup:\r
+ 142: \r
+ 143: ##################################################################\r
+ 144: # New - Set BEV=1 for the cases where M14K instruction pointer \r
+ 145: # is changed to force ROM to run again. CP0.BEV must be 1 to \r
+ 146: # safely write CP0.EBASE\r
+ 147: ##################################################################\r
+BFD00288 401A6000 MFC0 K0, Status 148: mfc0 k0, _CP0_STATUS\r
+BFD0028C 3C1B0040 LUI K1, 64 149: lui k1, 0x0040\r
+BFD00290 035BD025 OR K0, K0, K1 150: or k0, k0, k1 # CP0.STATUS.BEV(bit[22]) = 1\r
+BFD00294 409A6000 MTC0 K0, Status 151: mtc0 k0, _CP0_STATUS\r
+BFD00298 000000C0 EHB 152: ehb\r
+ 153: \r
+ 154: ##################################################################\r
+ 155: # Initialize Stack Pointer\r
+ 156: # _stack is initialized by the linker script to point to the\r
+ 157: # starting location of the stack in DRM\r
+ 158: ##################################################################\r
+BFD0029C 3C1DBFD2 LUI SP, -16430 159: la sp,_stack\r
+ 160: \r
+ 161: ##################################################################\r
+ 162: # Initialize Global Pointer\r
+ 163: # _gp is initialized by the linker script to point to "middle"\r
+ 164: # of the small variables region\r
+ 165: ##################################################################\r
+BFD002A4 3C1CBFD2 LUI GP, -16430 166: la gp,_gp\r
+ 167: \r
+ 168: #if (PIC32_SRS_SET_COUNT == 2)\r
+ 169: ##################################################################\r
+ 170: # Initialize Global Pointer in Shadow Set\r
+ 171: # The SRSCtl's PSS field must be set to the shadow set in which\r
+ 172: # to initialize the global pointer. Since we have only a\r
+ 173: # single shadow set (besides the normal), we will initialize\r
+ 174: # SRSCtl<PSS> to SRSCtl<HSS>. We then write the global pointer\r
+ 175: # to the previous shadow set to ensure that on interrupt, the\r
+ 176: # global pointer has been initialized.\r
+ 177: ##################################################################\r
+ 178: mfc0 t1,_CP0_SRSCTL # Read SRSCtl register\r
+ 179: add t3,t1,zero # Save off current SRSCtl\r
+ 180: ext t2,t1,26,4 # to obtain HSS field\r
+ 181: ins t1,t2,6,4 # Put HSS field\r
+ 182: mtc0 t1,_CP0_SRSCTL # into SRSCtl<PSS>\r
+ 183: ehb # Clear hazard before using new SRSCTL\r
+ 184: wrpgpr gp,gp # Set global pointer in PSS\r
+ 185: mtc0 t3,_CP0_SRSCTL # Restore SRSCtl\r
+ 186: ehb\r
+ 187: \r
+ 188: #elif (PIC32_SRS_SET_COUNT > 2)\r
+ 189: ##################################################################\r
+ 190: # Initialize Global Pointer in Shadow Set(s)\r
+ 191: # The SRSCtl PSS field must be set to the shadow set in which\r
+ 192: # to initialize the global pointer. We will initialize\r
+ 193: # SRSCtl<PSS> to the number of reg sets and work down to set zero.\r
+ 194: # We write the global pointer to the previous shadow set to\r
+ 195: # ensure that on interrupt, the global pointer has been\r
+ 196: # initialized.\r
+ 197: ##################################################################\r
+ 198: mfc0 t1,_CP0_SRSCTL # Read SRSCtl register\r
+ 199: add t3,t1,zero # Save off current SRSCtl\r
+ 200: \r
+ 201: li t2,(PIC32_SRS_SET_COUNT-1)\r
+ 202: \r
+ 203: 1: ins t1,t2,6,4 # Put next shadow set field\r
+ 204: mtc0 t1,_CP0_SRSCTL # into SRSCtl<PSS>\r
+ 205: ehb # Clear hazard before using new SRSCTL\r
+ 206: wrpgpr gp,gp # Set global pointer in PSS\r
+ 207: \r
+ 208: addiu t2,t2,-1 # Next lower shadow set\r
+ 209: # Loop for all sets\r
+ 210: bne t2,$0,1b # Down to zero (normal GPR set)\r
+ 211: nop\r
+ 212: \r
+ 213: mtc0 t3,_CP0_SRSCTL # Restore SRSCtl\r
+ 214: ehb\r
+ 215: \r
+ 216: #endif /* (PIC32_SRS_SET_COUNT > 2) */\r
+ 217: \r
+ 218: ##################################################################\r
+ 219: # Call the "on reset" procedure\r
+ 220: ##################################################################\r
+BFD002AC 3C08BFD1 LUI T0, -16431 221: la t0,_on_reset\r
+BFD002B4 0100F809 JALR T0 222: jalr t0\r
+BFD002B8 00000000 NOP 223: nop\r
+ 224: \r
+ 225: #if defined(INIT_MMU_MZ_FIXED)\r
+ 226: ##################################################################\r
+ 227: # Initialize TLB for fixed mapping to EBI and SQI\r
+ 228: ##################################################################\r
+ 229: .extern __pic32_tlb_init_ebi_sqi\r
+ 230: la t0,__pic32_tlb_init_ebi_sqi\r
+ 231: jalr t0\r
+ 232: nop\r
+ 233: #endif\r
+ 234: \r
+ 235: #if defined(INIT_L1_CACHE)\r
+ 236: ##################################################################\r
+ 237: # Initialize L1 cache register\r
+ 238: ##################################################################\r
+ 239: .extern __pic32_init_cache\r
+ 240: la t0,__pic32_init_cache\r
+ 241: jalr t0\r
+ 242: nop\r
+ 243: #endif\r
+ 244: \r
+ 245: #if defined(EN_STACK_FILL)\r
+ 246: ##################################################################\r
+ 247: # Fill stack\r
+ 248: # TODO - handle different stack lengths:\r
+ 249: # mulitple of 4, 8, 16, or 32\r
+ 250: ##################################################################\r
+BFD002BC 3C08BFD2 LUI T0, -16430 251: la t0,_stack_start\r
+BFD002C4 3C09BFD2 LUI T1, -16430 252: la t1,_stack\r
+BFD002CC 10000005 BEQ ZERO, ZERO, 0xBFD002E4 253: b _stack_check\r
+ 254: \r
+ 255: _stack_init:\r
+BFD002D0 AD000000 SW ZERO, 0(T0) 256: sw zero,0x0(t0)\r
+BFD002D4 AD000004 SW ZERO, 4(T0) 257: sw zero,0x4(t0)\r
+BFD002D8 AD000008 SW ZERO, 8(T0) 258: sw zero,0x8(t0)\r
+BFD002DC AD00000C SW ZERO, 12(T0) 259: sw zero,0xc(t0)\r
+BFD002E0 25080010 ADDIU T0, T0, 16 260: addu t0,16\r
+ 261: \r
+ 262: _stack_check:\r
+BFD002E4 0109082B SLTU AT, T0, T1 263: bltu t0,t1,_stack_init\r
+BFD002EC 00000000 NOP 264: nop\r
+ 265: #endif\r
+ 266: \r
+ 267: ##################################################################\r
+ 268: # Clear uninitialized data sections\r
+ 269: ##################################################################\r
+BFD002F0 3C08BFD2 LUI T0, -16430 270: la t0,_bss_begin\r
+BFD002F8 3C09BFD2 LUI T1, -16430 271: la t1,_bss_end\r
+BFD00300 10000006 BEQ ZERO, ZERO, 0xBFD0031C 272: b _bss_check\r
+BFD00304 00000000 NOP 273: nop\r
+ 274: \r
+ 275: _bss_init:\r
+BFD00308 AD000000 SW ZERO, 0(T0) 276: sw zero,0x0(t0)\r
+BFD0030C AD000004 SW ZERO, 4(T0) 277: sw zero,0x4(t0)\r
+BFD00310 AD000008 SW ZERO, 8(T0) 278: sw zero,0x8(t0)\r
+BFD00314 AD00000C SW ZERO, 12(T0) 279: sw zero,0xc(t0)\r
+BFD00318 25080010 ADDIU T0, T0, 16 280: addu t0,16\r
+ 281: _bss_check:\r
+BFD0031C 0109082B SLTU AT, T0, T1 282: bltu t0,t1,_bss_init\r
+BFD00324 00000000 NOP 283: nop\r
+ 284: \r
+ 285: ##################################################################\r
+ 286: # Initialize data using the linker-generated .dinit table\r
+ 287: ##################################################################\r
+ 288: .equiv FMT_CLEAR,0\r
+ 289: .equiv FMT_COPY,1\r
+ 290: _dinit_init:\r
+BFD00328 3C08BFD0 LUI T0, -16432 291: la t0,_dinit_addr\r
+ 292: \r
+ 293: #define SRC t0\r
+ 294: #define DST t1\r
+ 295: #define LEN t2\r
+ 296: #define FMT t3\r
+ 297: \r
+BFD00330 8D090000 LW T1, 0(T0) 298: 0: lw DST,0(SRC)\r
+BFD00334 11200018 BEQ T1, ZERO, 0xBFD00398 299: beqz DST,9f\r
+BFD00338 25080004 ADDIU T0, T0, 4 300: addu SRC,4\r
+BFD0033C 8D0A0000 LW T2, 0(T0) 301: lw LEN,0(SRC)\r
+BFD00340 25080004 ADDIU T0, T0, 4 302: addu SRC,4\r
+BFD00344 8D0B0000 LW T3, 0(T0) 303: lw FMT,0(SRC)\r
+BFD00348 11600009 BEQ T3, ZERO, 0xBFD00370 304: beq FMT,$0,_dinit_clear\r
+BFD0034C 25080004 ADDIU T0, T0, 4 305: addu SRC,4\r
+ 306: \r
+ 307: _dinit_copy:\r
+BFD00350 910C0000 LBU T4, 0(T0) 308: lbu t4,0(SRC)\r
+BFD00354 254AFFFF ADDIU T2, T2, -1 309: subu LEN,1\r
+BFD00358 25080001 ADDIU T0, T0, 1 310: addu SRC,1\r
+BFD0035C A12C0000 SB T4, 0(T1) 311: sb t4,0(DST)\r
+BFD00360 1540FFFB BNE T2, ZERO, 0xBFD00350 312: bne LEN,$0,_dinit_copy\r
+BFD00364 25290001 ADDIU T1, T1, 1 313: addu DST,1\r
+ 314: \r
+BFD00368 10000005 BEQ ZERO, ZERO, 0xBFD00380 315: b _dinit_end\r
+BFD0036C 00000000 NOP 316: nop\r
+ 317: \r
+ 318: _dinit_clear:\r
+BFD00370 A1200000 SB ZERO, 0(T1) 319: sb $0,(DST)\r
+BFD00374 254AFFFF ADDIU T2, T2, -1 320: subu LEN,1\r
+BFD00378 1540FFFD BNE T2, ZERO, 0xBFD00370 321: bne LEN,$0,_dinit_clear\r
+BFD0037C 25290001 ADDIU T1, T1, 1 322: addu DST,1\r
+ 323: \r
+ 324: _dinit_end:\r
+BFD00380 25080003 ADDIU T0, T0, 3 325: addu SRC,3\r
+BFD00384 240AFFFC ADDIU T2, ZERO, -4 326: addiu LEN,$0,0xFFFFFFFC\r
+BFD00388 01484024 AND T0, T2, T0 327: and SRC,LEN,SRC\r
+BFD0038C 8D090000 LW T1, 0(T0) 328: lw DST,0(SRC)\r
+BFD00390 1520FFE7 BNE T1, ZERO, 0xBFD00330 329: bne DST,$0,0b\r
+BFD00394 00000000 NOP 330: nop\r
+ 331: 9:\r
+ 332: \r
+ 333: ##################################################################\r
+ 334: # If there are no RAM functions, skip the next section --\r
+ 335: # initializing bus matrix registers.\r
+ 336: ##################################################################\r
+BFD00398 3C090000 LUI T1, 0 337: la t1,_ramfunc_begin\r
+BFD003A0 11200001 BEQ T1, ZERO, 0xBFD003A8 338: beqz t1,_ramfunc_done\r
+BFD003A4 00000000 NOP 339: nop\r
+ 340: \r
+ 341: #if defined(INIT_SSX)\r
+ 342: /* No initialization required */\r
+ 343: #else /* Use BMX */\r
+ 344: ##################################################################\r
+ 345: # Initialize bus matrix registers if RAM functions exist in the\r
+ 346: # application\r
+ 347: ##################################################################\r
+ 348: la t1,_bmxdkpba_address\r
+ 349: la t2,BMXDKPBA\r
+ 350: sw t1,0(t2)\r
+ 351: la t1,_bmxdudba_address\r
+ 352: la t2,BMXDUDBA\r
+ 353: sw t1,0(t2)\r
+ 354: la t1,_bmxdupba_address\r
+ 355: la t2,BMXDUPBA\r
+ 356: sw t1,0(t2)\r
+ 357: #endif /* INIT_SSX */\r
+ 358: \r
+ 359: _ramfunc_done:\r
+ 360: \r
+ 361: ##################################################################\r
+ 362: # Initialize CP0 registers\r
+ 363: ##################################################################\r
+ 364: # Initialize Count register\r
+ 365: ##################################################################\r
+BFD003A8 40804800 MTC0 ZERO, Count 366: mtc0 zero,_CP0_COUNT\r
+ 367: \r
+ 368: ##################################################################\r
+ 369: # Initialize Compare register\r
+ 370: ##################################################################\r
+BFD003AC 240AFFFF ADDIU T2, ZERO, -1 371: li t2,-1\r
+BFD003B0 408A5800 MTC0 T2, Compare 372: mtc0 t2,_CP0_COMPARE\r
+ 373: \r
+ 374: ##################################################################\r
+ 375: # Initialize EBase register\r
+ 376: ##################################################################\r
+BFD003B4 3C09BFD0 LUI T1, -16432 377: la t1,_ebase_address\r
+BFD003BC 40897801 MTC0 T1, EBase 378: mtc0 t1,_CP0_EBASE\r
+ 379: \r
+ 380: ##################################################################\r
+ 381: # Initialize IntCtl register\r
+ 382: ##################################################################\r
+BFD003C0 3C090000 LUI T1, 0 383: la t1,_vector_spacing\r
+BFD003C8 240A0000 ADDIU T2, ZERO, 0 384: li t2,0 # Clear t2 and\r
+BFD003CC 7D2A4944 INS T2, T1, 5, 5 385: ins t2,t1,5,5 # shift value to VS field\r
+BFD003D0 408A6001 MTC0 T2, IntCtl 386: mtc0 t2,_CP0_INTCTL\r
+ 387: \r
+ 388: ##################################################################\r
+ 389: # Initialize CAUSE registers\r
+ 390: # - Enable counting of Count register <DC = 0>\r
+ 391: # - Use special exception vector <IV = 1>\r
+ 392: # - Clear pending software interrupts <IP1:IP0 = 0>\r
+ 393: ##################################################################\r
+BFD003D4 3C090080 LUI T1, 128 394: li t1,0x00800000\r
+BFD003D8 40896800 MTC0 T1, Cause 395: mtc0 t1,_CP0_CAUSE\r
+ 396: \r
+ 397: ##################################################################\r
+ 398: # Initialize STATUS register\r
+ 399: # - Access to Coprocessor 0 not allowed in user mode <CU0 = 0>\r
+ 400: # - User mode uses configured endianness <RE = 0>\r
+ 401: # - Preserve Bootstrap Exception vectors <BEV>\r
+ 402: # - Preserve soft reset <SR> and non-maskable interrupt <NMI>\r
+ 403: # - CorExtend enabled based on whether CorExtend User Defined\r
+ 404: # Instructions have been implemented <CEE = Config<UDI>>\r
+ 405: # - Disable any pending interrups <IM7..IM2 = 0, IM1..IM0 = 0>\r
+ 406: # - Disable hardware interrupts <IPL7:IPL2 = 0>\r
+ 407: # - Base mode is Kernel mode <UM = 0>\r
+ 408: # - Error level is normal <ERL = 0>\r
+ 409: # - Exception level is normal <EXL = 0>\r
+ 410: # - Interrupts are disabled <IE = 0>\r
+ 411: # - DSPr2 ASE is enabled for devices that support it <MX = 1>\r
+ 412: ##################################################################\r
+BFD003DC 40088000 MFC0 T0, Config 413: mfc0 t0,_CP0_CONFIG\r
+BFD003E0 7D090580 EXT T1, T0, 22, 1 414: ext t1,t0,22,1 # Extract UDI from Config register\r
+BFD003E4 00094C40 SLL T1, T1, 17 415: sll t1,t1,17 # Move UDI to Status.CEE location\r
+BFD003E8 40086000 MFC0 T0, Status 416: mfc0 t0,_CP0_STATUS\r
+BFD003EC 3C010058 LUI AT, 88 417: and t0,t0,0x00580000 # Preserve SR, NMI, and BEV\r
+ 418: #if defined(INIT_DSPR2)\r
+ 419: li t2, 0x01000000 # Set the Status.MX bit to enable DSP\r
+ 420: or t0,t2,t0\r
+ 421: #endif\r
+BFD003F4 01284025 OR T0, T1, T0 422: or t0,t1,t0 # Include Status.CEE (from UDI)\r
+BFD003F8 40886000 MTC0 T0, Status 423: mtc0 t0,_CP0_STATUS\r
+ 424: \r
+ 425: ##################################################################\r
+ 426: # Call the "on bootstrap" procedure\r
+ 427: ##################################################################\r
+BFD003FC 3C08BFD1 LUI T0, -16431 428: la t0,_on_bootstrap\r
+BFD00404 0100F809 JALR T0 429: jalr t0\r
+BFD00408 00000000 NOP 430: nop\r
+ 431: \r
+ 432: ##################################################################\r
+ 433: # Initialize Status<BEV> for normal exception vectors\r
+ 434: ##################################################################\r
+BFD0040C 40086000 MFC0 T0, Status 435: mfc0 t0,_CP0_STATUS\r
+BFD00410 3C01FFBF LUI AT, -65 436: and t0,t0,0xffbfffff # Clear BEV\r
+BFD0041C 40886000 MTC0 T0, Status 437: mtc0 t0,_CP0_STATUS\r
+ 438: \r
+ 439: ##################################################################\r
+ 440: # Call main. We do this via a thunk in the text section so that\r
+ 441: # a normal jump and link can be used, enabling the startup code\r
+ 442: # to work properly whether main is written in MIPS16 or MIPS32\r
+ 443: # code. I.e., the linker will correctly adjust the JAL to JALX if\r
+ 444: # necessary\r
+ 445: ##################################################################\r
+BFD00420 30840000 ANDI A0, A0, 0 446: and a0,a0,0\r
+BFD00424 30A50000 ANDI A1, A1, 0 447: and a1,a1,0\r
+BFD00428 3C08BFD0 LUI T0, -16432 448: la t0,_main_entry\r
+BFD00430 01000008 JR T0 449: jr t0\r
+BFD00434 00000000 NOP 450: nop\r
+ 451: \r
+ 452: .end _startup\r
+ 453: \r
+ 454: \r
+ 455: ##################################################################\r
+ 456: # General Exception Vector Handler\r
+ 457: # Jumps to _general_exception_context\r
+ 458: ##################################################################\r
+ 459: .section .gen_handler,code\r
+ 460: .set noreorder\r
+ 461: .ent _gen_exception\r
+ 462: _gen_exception:\r
+BFD00180 3C1ABFD0 LUI K0, -16432 463: 0: la k0,_general_exception_context\r
+BFD00188 03400008 JR K0 464: jr k0\r
+BFD0018C 00000000 NOP 465: nop\r
+ 466: \r
+ 467: .end _gen_exception\r
+ 468: \r
+ 469: #if defined(INIT_MMU_MZ_FIXED)\r
+ 470: ##################################################################\r
+ 471: # Simple TLB-Refill Exception Vector\r
+ 472: # Jumps to _simple_tlb_refill_exception_context\r
+ 473: ##################################################################\r
+ 474: .section .simple_tlb_refill_vector,code,keep\r
+ 475: .set noreorder\r
+ 476: .ent simple_tlb_refill_vector\r
+ 477: simple_tlb_refill_vector:\r
+ 478: la k0,_simple_tlb_refill_exception_context\r
+ 479: jr k0\r
+ 480: nop\r
+ 481: \r
+ 482: .end simple_tlb_refill_vector\r
+ 483: #endif\r
+ 484: \r
+ 485: #if defined(INIT_L1_CACHE)\r
+ 486: ##################################################################\r
+ 487: # Cache-Error Exception Vector Handler\r
+ 488: # Jumps to _cache_err_exception_context\r
+ 489: ##################################################################\r
+ 490: .section .cache_err_vector,code,keep\r
+ 491: .set noreorder\r
+ 492: .ent _cache_err_vector\r
+ 493: _cache_err_vector:\r
+ 494: la k0,_cache_err_exception_context\r
+ 495: jr k0\r
+ 496: nop\r
+ 497: \r
+ 498: .end _cache_err_vector\r
+ 499: #endif\r
+ 500: \r
+ 501: .section .text.main_entry,code,keep\r
+ 502: .ent _main_entry\r
+ 503: _main_entry:\r
+ 504: \r
+ 505: #if defined(CPP_INIT)\r
+ 506: .weak _init\r
+ 507: # call .init section to run constructors etc\r
+BFD06804 3C04BFD0 LUI A0, -16432 508: lui a0,%hi(_init)\r
+BFD06808 27BDFFE8 ADDIU SP, SP, -24 509: addiu sp,sp,-24\r
+BFD0680C 24840438 ADDIU A0, A0, 1080 510: addiu a0,a0,%lo(_init)\r
+BFD06810 10800003 BEQ A0, ZERO, 0xBFD06820 511: beq a0,$0,2f\r
+BFD06814 AFBF0014 SW RA, 20(SP) 512: sw $31,20(sp) #,\r
+BFD06818 0080F809 JALR A0 513: jalr a0\r
+BFD0681C 00000000 NOP 514: nop\r
+ 515: 2:\r
+ 516: #endif\r
+BFD06820 30840000 ANDI A0, A0, 0 517: and a0,a0,0\r
+BFD06824 30A50000 ANDI A1, A1, 0 518: and a1,a1,0\r
+ 519: \r
+ 520: ##################################################################\r
+ 521: \r
+ 522: # Call main\r
+ 523: ##################################################################\r
+BFD06828 77F425B0 JALX 0xBFD096C0 524: jal main\r
+BFD0682C 00000000 NOP 525: nop\r
+ 526: \r
+ 527: #if defined(CALL_EXIT)\r
+ 528: ##################################################################\r
+ 529: # Call exit()\r
+ 530: ##################################################################\r
+ 531: jal exit\r
+ 532: nop\r
+ 533: #endif\r
+ 534: \r
+ 535: ##################################################################\r
+ 536: # Just in case, go into infinite loop\r
+ 537: # Call a software breakpoint only with -mdebugger compiler option\r
+ 538: ##################################################################\r
+ 539: .weak __exception_handler_break\r
+ 540: __crt0_exit:\r
+ 541: 1:\r
+BFD06830 3C020000 LUI V0, 0 542: la v0,__exception_handler_break\r
+BFD06838 10400003 BEQ V0, ZERO, 0xBFD06848 543: beq v0,0,0f\r
+BFD0683C 00000000 NOP 544: nop\r
+BFD06840 0040F809 JALR V0 545: jalr v0\r
+BFD06844 00000000 NOP 546: nop\r
+ 547: \r
+BFD06848 1000FFF9 BEQ ZERO, ZERO, 0xBFD06830 548: 0: b 1b\r
+BFD0684C 00000000 NOP 549: nop\r
+ 550: \r
+ 551: .globl __crt0_exit\r
+ 552: .end _main_entry\r
+ 553: \r
+ 554: ###############################################################\r
+ 555: # launch_fw\r
+ 556: ###############################################################\r
+ 557: .globl rom_launch_fw\r
+ 558: .set nomips16\r
+ 559: .set micromips\r
+ 560: .ent rom_launch_fw\r
+ 561: .type rom_launch_fw, @function\r
+ 562: \r
+ 563: rom_launch_fw:\r
+ 564: \r
+ 565: .set noreorder\r
+ 566: .set nomacro\r
+ 567: \r
+ 568: lfw1:\r
+BFD06850 477C0000 DI ZERO 569: di\r
+ 570: lfw2:\r
+BFD06854 18000000 SLL ZERO, ZERO, 3 571: ehb\r
+ 572: lfw3:\r
+BFD06858 0C00 NOP 573: nop\r
+ 574: \r
+ 575: # turn off core timer\r
+ 576: lfw4:\r
+BFD0685A 00FC010D MFC0 T0, Cause 577: mfc0 t0, _CP0_CAUSE\r
+ 578: lfw5:\r
+BFD0685E F7FF41A9 LUI T1, 0xF7FF 579: lui t1, 0xf7ff\r
+ 580: lfw6:\r
+BFD06862 FFFF5129 ORI T1, T1, -1 581: ori t1, t1, 0xffff\r
+ 582: lfw7:\r
+BFD06866 42500128 AND T0, T0, T1 583: and t0, t0, t1\r
+ 584: lfw8:\r
+BFD0686A 02FC010D MTC0 T0, Cause 585: mtc0 t0, _CP0_CAUSE\r
+ 586: lfw9:\r
+BFD0686E 18000000 SLL ZERO, ZERO, 3 587: ehb\r
+ 588: lfw10:\r
+BFD06872 0C00 NOP 589: nop\r
+ 590: lfw11:\r
+BFD06874 00FC010C MFC0 T0, Status 591: mfc0 t0, _CP0_STATUS\r
+ 592: lfw12:\r
+BFD06878 004041A9 LUI T1, 0x40 593: lui t1, 0x0040\r
+ 594: lfw13:\r
+BFD0687C 42900128 OR T0, T0, T1 595: or t0, t0, t1 # BEV(bit[22]) = 1\r
+ 596: lfw14:\r
+BFD06880 02FC010C MTC0 T0, Status 597: mtc0 t0, _CP0_STATUS\r
+ 598: lfw15:\r
+BFD06884 18000000 SLL ZERO, ZERO, 3 599: ehb\r
+ 600: lfw16:\r
+BFD06888 0C00 NOP 601: nop\r
+ 602: lfw17: \r
+BFD0688A 1F3C0004 JALR.HB ZERO, A0 603: JR.HB a0\r
+ 604: lfw18:\r
+BFD0688E 00000000 NOP 605: nop\r
+ 606: 0:\r
+BFD06892 3449D7E8 J 0xBFD06892 607: j 0b # should not get here\r
+ 608: lfw19:\r
+BFD06896 0C00 NOP 609: nop\r
+ 610: \r
+ 611: .set macro\r
+ 612: .set reorder\r
+ 613: \r
+ 614: .end rom_launch_fw\r
+ 615: .size rom_launch_fw, .-rom_launch_fw\r
+ 616:
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq24d.S ---
+ 1: /*\r
+ 2: Copyright (C) 2014 Microchip Inc.\r
+ 3: All rights reserved\r
+ 4: \r
+ 5: 1 tab == 4 spaces!\r
+ 6: */\r
+ 7: \r
+ 8: #ifdef __XC32\r
+ 9: #include <xc.h>\r
+ 10: #include <sys/asm.h>\r
+ 11: #else\r
+ 12: #include "Regs.S"\r
+ 13: #endif\r
+ 14: \r
+ 15: #include "MEC14xx/mec14xx_girqm.h"\r
+ 16: \r
+ 17: /******************************************************************/\r
+ 18: \r
+ 19: /***************************************************************\r
+ 20: * MEC14xx GIRQ24 Disaggregated Vector Jump table\r
+ 21: *\r
+ 22: ***************************************************************/\r
+ 23: \r
+ 24: .extern girq24_b0\r
+ 25: .extern girq24_b1\r
+ 26: .extern girq24_b2\r
+ 27: \r
+ 28: #if GIRQ24_DISAGG != 0\r
+ 29: \r
+ 30: /* \r
+ 31: * FreeRTOS Handler for MIPS M14K Software Interrupt 0 \r
+ 32: * implemented in the porting layer.\r
+ 33: */\r
+ 34: .extern vPortYieldISR\r
+ 35: \r
+ 36: /*\r
+ 37: * Disaggregated girq24_isr\r
+ 38: * Program address of this version of girq24_isr into JTVIC GIRQ24\r
+ 39: * Aggregator Control register with bit[0] = 1.\r
+ 40: */\r
+ 41: \r
+ 42: /*\r
+ 43: * NOTE: All the additional labels surrounding every instruction are\r
+ 44: * there to force GCC OBJDUMP to disassemble microMIPS correctly.\r
+ 45: */\r
+ 46: \r
+ 47: .insn\r
+ 48: #ifdef __XC32\r
+ 49: .section .girqs.girq24_isr, code\r
+ 50: #else\r
+ 51: .section .girqs.girq24_isr,"x"\r
+ 52: #endif\r
+ 53: .set nomips16\r
+ 54: .set micromips\r
+ 55: .set noreorder\r
+ 56: .set noat\r
+ 57: .ent girq24_isr\r
+ 58: .global girq24_isr\r
+ 59: .align 2\r
+ 60: \r
+ 61: girq24_isr:\r
+BFD00270 32D4D7E8 J 0xBFD065A8 62: J girq24_b0\r
+ 63: g24b0b:\r
+BFD00274 0C00 NOP 64: NOP\r
+ 65: \r
+ 66: .align 2\r
+ 67: g24b1a:\r
+BFD00278 05B8D7E8 J 0xBFD00B70 68: J vPortYieldISR /* girq24_b1 */\r
+ 69: g24b1b:\r
+BFD0027C 0C00 NOP 70: NOP\r
+ 71: \r
+ 72: .align 2\r
+ 73: g24b2a:\r
+BFD00280 23A0D7E8 J 0xBFD04740 74: J girq24_b2\r
+ 75: g24b2b:\r
+BFD00284 0C00 NOP 76: NOP\r
+ 77: g24end:\r
+ 78: .end girq24_isr\r
+ 79: \r
+ 80: #endif\r
+ 81: \r
+ 82: /******************************************************************/\r
+ 83: \r
+ 84: \r
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq23d.S ---
+ 1: /*\r
+ 2: Copyright (C) 2014 Microchip Inc.\r
+ 3: All rights reserved\r
+ 4: \r
+ 5: 1 tab == 4 spaces!\r
+ 6: */\r
+ 7: \r
+ 8: #ifdef __XC32\r
+ 9: #include <xc.h>\r
+ 10: #include <sys/asm.h>\r
+ 11: #else\r
+ 12: #include "Regs.S"\r
+ 13: #endif\r
+ 14: \r
+ 15: #include "MEC14xx/mec14xx_girqm.h"\r
+ 16: \r
+ 17: \r
+ 18: /***************************************************************\r
+ 19: * MEC14xx GIRQ23 Disaggregated Vector Jump table\r
+ 20: *\r
+ 21: ***************************************************************/\r
+ 22: \r
+ 23: .extern girq23_b0\r
+ 24: .extern girq23_b1\r
+ 25: .extern girq23_b2\r
+ 26: .extern girq23_b3\r
+ 27: .extern girq23_b4\r
+ 28: .extern girq23_b5\r
+ 29: .extern girq23_b6\r
+ 30: .extern girq23_b7\r
+ 31: .extern girq23_b8\r
+ 32: .extern girq23_b9\r
+ 33: .extern girq23_b10\r
+ 34: .extern girq23_b11\r
+ 35: .extern girq23_b12\r
+ 36: .extern girq23_b13\r
+ 37: \r
+ 38: #if GIRQ23_DISAGG != 0\r
+ 39: \r
+ 40: /*\r
+ 41: * FreeRTOS Handler for MEC14xx RTOS Timer\r
+ 42: * implemented in the porting layer.\r
+ 43: */\r
+ 44: .extern vPortTickInterruptHandler\r
+ 45: \r
+ 46: /*\r
+ 47: * Disaggregated girq23_isr\r
+ 48: * Program address of this version of girq23_isr into JTVIC GIRQ23\r
+ 49: * Aggregator Control register with bit[0] = 1.\r
+ 50: */\r
+ 51: \r
+ 52: /*\r
+ 53: * NOTE: All the additional labels surrounding every instruction are\r
+ 54: * there to force GCC OBJDUMP to disassemble microMIPS correctly.\r
+ 55: */\r
+ 56: \r
+ 57: .insn\r
+ 58: #ifdef __XC32\r
+ 59: .section .girqs.girq23_isr, code\r
+ 60: #else\r
+ 61: .section .girqs.girq23_isr,"x"\r
+ 62: #endif\r
+ 63: .set nomips16\r
+ 64: .set micromips\r
+ 65: .set noreorder\r
+ 66: .set noat\r
+ 67: .ent girq23_isr\r
+ 68: .global girq23_isr\r
+ 69: .align 2\r
+ 70: \r
+ 71: girq23_isr:\r
+ 72: \r
+BFD00200 3950D7E8 J 0xBFD072A0 73: J girq23_b0\r
+ 74: g23b0b:\r
+BFD00204 0C00 NOP 75: NOP\r
+ 76: \r
+ 77: .align 2\r
+ 78: g23b1a:\r
+BFD00208 2638D7E8 J 0xBFD04C70 79: J girq23_b1\r
+ 80: g23b1b:\r
+BFD0020C 0C00 NOP 81: NOP\r
+ 82: \r
+ 83: .align 2\r
+ 84: g23b2a:\r
+BFD00210 26A0D7E8 J 0xBFD04D40 85: J girq23_b2\r
+ 86: g23b2b:\r
+BFD00214 0C00 NOP 87: NOP\r
+ 88: \r
+ 89: .align 2\r
+ 90: g23b3a:\r
+BFD00218 2708D7E8 J 0xBFD04E10 91: J girq23_b3\r
+ 92: g23b3b:\r
+BFD0021C 0C00 NOP 93: NOP\r
+ 94: \r
+ 95: .align 2\r
+ 96: g23b4a:\r
+BFD00220 0490D7E8 J 0xBFD00920 97: J girq23_b4 \r
+ 98: g23b4b:\r
+BFD00224 0C00 NOP 99: NOP\r
+ 100: \r
+ 101: .align 2\r
+ 102: g23b5a:\r
+BFD00228 2770D7E8 J 0xBFD04EE0 103: J girq23_b5\r
+ 104: g23b5b:\r
+BFD0022C 0C00 NOP 105: NOP\r
+ 106: \r
+ 107: .align 2\r
+ 108: g23b6a:\r
+BFD00230 27D8D7E8 J 0xBFD04FB0 109: J girq23_b6\r
+ 110: g23b6b:\r
+BFD00234 0C00 NOP 111: NOP\r
+ 112: \r
+ 113: .align 2\r
+ 114: g23b7a:\r
+BFD00238 2840D7E8 J 0xBFD05080 115: J girq23_b7\r
+ 116: g23b7b:\r
+BFD0023C 0C00 NOP 117: NOP\r
+ 118: \r
+ 119: .align 2\r
+ 120: g23b8a:\r
+BFD00240 28A8D7E8 J 0xBFD05150 121: J girq23_b8\r
+ 122: g23b8b:\r
+BFD00244 0C00 NOP 123: NOP\r
+ 124: \r
+ 125: .align 2\r
+ 126: g23b9a:\r
+BFD00248 2910D7E8 J 0xBFD05220 127: J girq23_b9\r
+ 128: g23b9b:\r
+BFD0024C 0C00 NOP 129: NOP\r
+ 130: \r
+ 131: .align 2\r
+ 132: g23b10a:\r
+BFD00250 2978D7E8 J 0xBFD052F0 133: J girq23_b10\r
+ 134: g23b10b:\r
+BFD00254 0C00 NOP 135: NOP\r
+ 136: \r
+ 137: .align 2\r
+ 138: g23b11a:\r
+BFD00258 29E0D7E8 J 0xBFD053C0 139: J girq23_b11\r
+ 140: g23b11b:\r
+BFD0025C 0C00 NOP 141: NOP\r
+ 142: \r
+ 143: .align 2\r
+ 144: g23b12a:\r
+BFD00260 2A48D7E8 J 0xBFD05490 145: J girq23_b12\r
+ 146: g23b12b:\r
+BFD00264 0C00 NOP 147: NOP\r
+ 148: \r
+ 149: .align 2\r
+ 150: g23b13a:\r
+BFD00268 2AB0D7E8 J 0xBFD05560 151: J girq23_b13\r
+ 152: g23b13b:\r
+BFD0026C 0C00 NOP 153: NOP\r
+ 154: g23end:\r
+ 155: .end girq23_isr\r
+ 156: \r
+ 157: #endif\r
+ 158: \r
+ 159: /******************************************************************/\r
+ 160: \r
+ 161: \r
+ 162: \r
+ 163: \r
+--- C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/exceptions/MPLAB/general_exception_ctx.S
+ 1: /*********************************************************************\r
+ 2: *\r
+ 3: * General Exception\r
+ 4: *\r
+ 5: *********************************************************************\r
+ 6: * Filename: general-exception.S\r
+ 7: *\r
+ 8: * Processor: PIC32\r
+ 9: *\r
+ 10: * Compiler: MPLAB XC32 v1.00\r
+ 11: * MPLAB X IDE\r
+ 12: * Company: Microchip Technology Inc.\r
+ 13: *\r
+ 14: * Software License Agreement\r
+ 15: *\r
+ 16: * This software is developed by Microchip Technology Inc. and its\r
+ 17: * subsidiaries ("Microchip").\r
+ 18: *\r
+ 19: * Redistribution and use in source and binary forms, with or without\r
+ 20: * modification, are permitted provided that the following conditions are met:\r
+ 21: *\r
+ 22: * 1. Redistributions of source code must retain the above copyright\r
+ 23: * notice, this list of conditions and the following disclaimer.\r
+ 24: *\r
+ 25: * 2. Redistributions in binary form must reproduce the above copyright\r
+ 26: * notice, this list of conditions and the following disclaimer in the\r
+ 27: * documentation and/or other materials provided with the distribution.\r
+ 28: *\r
+ 29: * 3. Microchip's name may not be used to endorse or promote products\r
+ 30: * derived from this software without specific prior written permission.\r
+ 31: *\r
+ 32: * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ 33: * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ 34: * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL\r
+ 35: * MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ 36: * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO\r
+ 37: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS;\r
+ 38: * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ 39: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ 40: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\r
+ 41: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ 42: *\r
+ 43: ********************************************************************/\r
+ 44: \r
+ 45: #include <xc.h>\r
+ 46: #ifdef __LIBBUILD__\r
+ 47: .file 1 "general-exception.S"\r
+ 48: .loc 1 0\r
+ 49: #endif\r
+ 50: ###################\r
+ 51: # Default general exception handler\r
+ 52: ###################\r
+ 53: \r
+ 54: .extern _general_exception_handler\r
+ 55: \r
+ 56: .section .text.general_exception, code\r
+ 57: .set noreorder\r
+ 58: .set noat\r
+ 59: .set nomips16\r
+ 60: .globl _general_exception_context\r
+ 61: .ent _general_exception_context\r
+ 62: \r
+ 63: _general_exception_context:\r
+ 64: \r
+ 65: # Save off the non-callee saved registers that may get mucked with\r
+BFD049E4 27BDFFA8 ADDIU SP, SP, -88 66: addiu sp, sp, -88\r
+BFD049E8 AFA10004 SW AT, 4(SP) 67: sw $1, 4(sp)\r
+BFD049EC AFA20008 SW V0, 8(SP) 68: sw v0, 8(sp)\r
+BFD049F0 AFA3000C SW V1, 12(SP) 69: sw v1, 12(sp)\r
+BFD049F4 AFA40010 SW A0, 16(SP) 70: sw a0, 16(sp)\r
+BFD049F8 AFA50014 SW A1, 20(SP) 71: sw a1, 20(sp)\r
+BFD049FC AFA60018 SW A2, 24(SP) 72: sw a2, 24(sp)\r
+BFD04A00 AFA7001C SW A3, 28(SP) 73: sw a3, 28(sp)\r
+BFD04A04 AFA80020 SW T0, 32(SP) 74: sw t0, 32(sp)\r
+BFD04A08 AFA90024 SW T1, 36(SP) 75: sw t1, 36(sp)\r
+BFD04A0C AFAA0028 SW T2, 40(SP) 76: sw t2, 40(sp)\r
+BFD04A10 AFAB002C SW T3, 44(SP) 77: sw t3, 44(sp)\r
+BFD04A14 AFAC0030 SW T4, 48(SP) 78: sw t4, 48(sp)\r
+BFD04A18 AFAD0034 SW T5, 52(SP) 79: sw t5, 52(sp)\r
+BFD04A1C AFAE0038 SW T6, 56(SP) 80: sw t6, 56(sp)\r
+BFD04A20 AFAF003C SW T7, 60(SP) 81: sw t7, 60(sp)\r
+BFD04A24 AFB80040 SW T8, 64(SP) 82: sw t8, 64(sp)\r
+BFD04A28 AFB90044 SW T9, 68(SP) 83: sw t9, 68(sp)\r
+BFD04A2C AFBF0048 SW RA, 72(SP) 84: sw ra, 72(sp)\r
+BFD04A30 00004012 MFLO T0, 0 85: mflo t0\r
+BFD04A34 AFA8004C SW T0, 76(SP) 86: sw t0, 76(sp)\r
+BFD04A38 00004010 MFHI T0, 0 87: mfhi t0\r
+BFD04A3C AFA80050 SW T0, 80(SP) 88: sw t0, 80(sp)\r
+ 89: \r
+BFD04A40 3C1ABFD0 LUI K0, -16432 90: la k0,_general_exception_handler\r
+BFD04A48 00000000 NOP 91: nop\r
+ 92: \r
+ 93: # Pass Cause and Status to the handler function\r
+BFD04A4C 40046800 MFC0 A0, Cause 94: mfc0 a0, _CP0_CAUSE\r
+BFD04A50 40056000 MFC0 A1, Status 95: mfc0 a1, _CP0_STATUS\r
+BFD04A54 0340F809 JALR K0 96: jalr k0\r
+BFD04A58 00000000 NOP 97: nop\r
+ 98: \r
+BFD04A5C 8FA80050 LW T0, 80(SP) 99: lw t0, 80(sp)\r
+BFD04A60 01000011 MTHI T0, 0 100: mthi t0\r
+BFD04A64 8FA8004C LW T0, 76(SP) 101: lw t0, 76(sp)\r
+BFD04A68 01000013 MTLO T0, 0 102: mtlo t0\r
+ 103: \r
+BFD04A6C 8FA10004 LW AT, 4(SP) 104: lw $1, 4(sp)\r
+BFD04A70 8FA20008 LW V0, 8(SP) 105: lw v0, 8(sp)\r
+BFD04A74 8FA3000C LW V1, 12(SP) 106: lw v1, 12(sp)\r
+BFD04A78 8FA40010 LW A0, 16(SP) 107: lw a0, 16(sp)\r
+BFD04A7C 8FA50014 LW A1, 20(SP) 108: lw a1, 20(sp)\r
+BFD04A80 8FA60018 LW A2, 24(SP) 109: lw a2, 24(sp)\r
+BFD04A84 8FA7001C LW A3, 28(SP) 110: lw a3, 28(sp)\r
+BFD04A88 8FA80020 LW T0, 32(SP) 111: lw t0, 32(sp)\r
+BFD04A8C 8FA90024 LW T1, 36(SP) 112: lw t1, 36(sp)\r
+BFD04A90 8FAA0028 LW T2, 40(SP) 113: lw t2, 40(sp)\r
+BFD04A94 8FAB002C LW T3, 44(SP) 114: lw t3, 44(sp)\r
+BFD04A98 8FAC0030 LW T4, 48(SP) 115: lw t4, 48(sp)\r
+BFD04A9C 8FAD0034 LW T5, 52(SP) 116: lw t5, 52(sp)\r
+BFD04AA0 8FAE0038 LW T6, 56(SP) 117: lw t6, 56(sp)\r
+BFD04AA4 8FAF003C LW T7, 60(SP) 118: lw t7, 60(sp)\r
+BFD04AA8 8FB80040 LW T8, 64(SP) 119: lw t8, 64(sp)\r
+BFD04AAC 8FB90044 LW T9, 68(SP) 120: lw t9, 68(sp)\r
+BFD04AB0 8FBF0048 LW RA, 72(SP) 121: lw ra, 72(sp)\r
+BFD04AB4 27BD0058 ADDIU SP, SP, 88 122: addiu sp, sp, 88\r
+ 123: \r
+BFD04AB8 000000C0 EHB 124: ehb\r
+BFD04ABC 42000018 ERET 125: eret\r
+ 126: \r
+ 127: .end _general_exception_context\r
+ 128: \r
projects / freertos / commitdiff