--- /dev/null
+/*\r
+ Copyright (C) 2014 Microchip Inc.\r
+ All rights reserved\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifdef __XC32\r
+#include <xc.h>\r
+#include <sys/asm.h>\r
+#else\r
+#include "Regs.S"\r
+#endif\r
+\r
+#include "MEC14xx/mec14xx_girqm.h"\r
+\r
+\r
+/******************************************************************/\r
+\r
+/***************************************************************\r
+ * MEC14xx GIRQ13 Disaggregated Vector Jump table\r
+ *\r
+ ***************************************************************/\r
+\r
+ .extern girq13_b0\r
+ .extern girq13_b1\r
+ .extern girq13_b2\r
+ .extern girq13_b3\r
+ .extern girq13_b4\r
+ .extern girq13_b5\r
+ .extern girq13_b6\r
+\r
+#if GIRQ13_DISAGG != 0\r
+\r
+/*\r
+ * Disaggregated girq13_isr\r
+ * Program address of this version of girq23v into JTVIC GIRQ13\r
+ * Aggregator Control register with bit[0] = 1.\r
+ */\r
+ .insn\r
+#ifdef __XC32\r
+ .section .girqs.girq13_isr, code\r
+#else\r
+ .section .girqs.girq13_isr,"x"\r
+#endif\r
+ .set nomips16\r
+ .set micromips\r
+ .set noreorder\r
+ .set noat\r
+ .ent girq13_isr\r
+ .global girq13_isr\r
+ .align 2\r
+\r
+girq13_isr:\r
+ J girq13_b0\r
+ NOP\r
+\r
+ .align 2\r
+ J girq13_b1\r
+ NOP\r
+\r
+ .align 2\r
+ J girq13_b2\r
+ NOP\r
+\r
+ .align 2\r
+ J girq13_b3\r
+ NOP\r
+\r
+ .align 2\r
+ J girq13_b4\r
+ NOP\r
+\r
+ .align 2\r
+ J girq13_b5\r
+ NOP\r
+\r
+ .align 2\r
+ J girq13_b6\r
+ NOP\r
+\r
+ .end girq13_isr\r
+\r
+#endif\r
+\r
+/******************************************************************/\r
+\r
+\r