Add PIC32MEC14xx port and demo application.

[freertos] / FreeRTOS / Demo / PIC32MEC14xx_MPLAB / src / MEC14xx / interrupts / girq19d.S

diff --git a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq19d.S b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq19d.S
new file mode 100644 (file)
index 0000000..961fecb
--- /dev/null
+++ b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq19d.S
@@ -0,0 +1,121 @@
+/*\r
+    Copyright (C) 2014 Microchip Inc.\r
+    All rights reserved\r
+\r
+    1 tab == 4 spaces!\r
+*/\r
+\r
+#ifdef __XC32\r
+#include <xc.h>\r
+#include <sys/asm.h>\r
+#else\r
+#include "Regs.S"\r
+#endif\r
+\r
+#include "MEC14xx/mec14xx_girqm.h"\r
+\r
+\r
+/******************************************************************/\r
+\r
+/***************************************************************\r
+ *  MEC14xx GIRQ19 Disaggregated Vector Jump table\r
+ *\r
+ ***************************************************************/\r
+\r
+    .extern girq19_b0\r
+    .extern girq19_b1\r
+    .extern girq19_b2\r
+    .extern girq19_b3\r
+    .extern girq19_b4\r
+    .extern girq19_b5\r
+    .extern girq19_b6\r
+    .extern girq19_b7\r
+    .extern girq19_b8\r
+\r
+#if GIRQ19_DISAGG != 0\r
+\r
+/*\r
+ * Disaggregated girq19_isr\r
+ * Program address of this version of girq19_isr into JTVIC GIRQ19\r
+ * Aggregator Control register with bit[0] = 1.\r
+ */\r
+\r
+/*\r
+ * NOTE: All the additional labels surrounding every instruction are\r
+ * there to force GCC OBJDUMP to disassemble microMIPS correctly.\r
+ */\r
+\r
+    .insn\r
+#ifdef __XC32\r
+    .section .girqs.girq19_isr, code\r
+#else\r
+    .section .girqs.girq19_isr,"x"\r
+#endif\r
+    .set  nomips16\r
+    .set  micromips\r
+    .set  noreorder\r
+    .set  noat\r
+    .ent girq19_isr\r
+    .global girq19_isr\r
+    .align 2\r
+\r
+girq19_isr:\r
+    J       girq19_b0\r
+g19b0b:\r
+    NOP\r
+\r
+    .align 2\r
+g19b1a:\r
+    J       girq19_b1\r
+g19b1b:\r
+    NOP\r
+\r
+    .align 2\r
+g19b2a:\r
+    J       girq19_b2\r
+g19b2b:\r
+    NOP\r
+\r
+    .align 2\r
+g19b3a:\r
+    J       girq19_b3\r
+g19b3b:\r
+    NOP\r
+\r
+    .align 2\r
+g19b4a:\r
+    J       girq19_b4\r
+g19b4b:\r
+    NOP\r
+\r
+    .align 2\r
+g19b5a:\r
+    J       girq19_b5\r
+g19b5b:\r
+    NOP\r
+\r
+    .align 2\r
+g19b6a:\r
+    J       girq19_b6\r
+g19b6b:\r
+    NOP\r
+\r
+    .align 2\r
+g19b7a:\r
+    J       girq19_b7\r
+g19b7b:\r
+    NOP\r
+\r
+    .align 2\r
+g19b8a:\r
+    J       girq19_b8\r
+g19b8b:\r
+    NOP\r
+g19end:\r
+    .end girq19_isr\r
+\r
+#endif\r
+\r
+/******************************************************************/\r
+\r
+\r