Add PIC32MEC14xx port and demo application.

[freertos] / FreeRTOS / Demo / PIC32MEC14xx_MPLAB / src / MEC14xx / interrupts / girq26d.S

diff --git a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq26d.S b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq26d.S
new file mode 100644 (file)
index 0000000..2f72c1f
--- /dev/null
+++ b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/interrupts/girq26d.S
@@ -0,0 +1,142 @@
+/*\r
+    Copyright (C) 2014 Microchip Inc.\r
+    All rights reserved\r
+\r
+    1 tab == 4 spaces!\r
+*/\r
+\r
+#ifdef __XC32\r
+#include <xc.h>\r
+#include <sys/asm.h>\r
+#else\r
+#include "Regs.S"\r
+#endif\r
+\r
+#include "MEC14xx/mec14xx_girqm.h"\r
+\r
+\r
+/******************************************************************/\r
+\r
+/***************************************************************\r
+ *  MEC14xx GIRQ26 Disaggregated Vector Jump table\r
+ *\r
+ ***************************************************************/\r
+\r
+    .extern girq26_b0\r
+    .extern girq26_b1\r
+    .extern girq26_b2\r
+    .extern girq26_b3\r
+    .extern girq26_b4\r
+    .extern girq26_b5\r
+    .extern girq26_b6\r
+    .extern girq26_b7\r
+    .extern girq26_b8\r
+    .extern girq26_b9\r
+    .extern girq26_b10\r
+    .extern girq26_b11\r
+\r
+#if GIRQ26_DISAGG != 0\r
+\r
+/*\r
+ * Disaggregated girq26_isr\r
+ * Program address of this version of girq26_isr into JTVIC GIRQ26\r
+ * Aggregator Control register with bit[0] = 1.\r
+ */\r
+\r
+/*\r
+ * NOTE: All the additional labels surrounding every instruction are\r
+ * there to force GCC OBJDUMP to disassemble microMIPS correctly.\r
+ */\r
+\r
+    .insn\r
+#ifdef __XC32\r
+    .section .girqs.girq26_isr, code\r
+#else\r
+    .section .girqs.girq26_isr,"x"\r
+#endif\r
+    .set  nomips16\r
+    .set  micromips\r
+    .set  noreorder\r
+    .set  noat\r
+    .ent girq26_isr\r
+    .global girq26_isr\r
+    .align 2\r
+\r
+girq26_isr:\r
+    J       girq26_b0\r
+g26b0b:\r
+    NOP\r
+\r
+    .align 2\r
+g26b1a:\r
+    J       girq26_b1\r
+g26b1b:\r
+    NOP\r
+\r
+    .align 2\r
+g26b2a:\r
+    J       girq26_b2\r
+g26b2b:\r
+    NOP\r
+\r
+    .align 2\r
+g26b3a:\r
+    J       girq26_b3\r
+g26b3b:\r
+    NOP\r
+\r
+    .align 2\r
+g26b4a:\r
+    J       girq26_b4\r
+g26b4b:\r
+    NOP\r
+\r
+    .align 2\r
+g26b5a:\r
+    J       girq26_b5\r
+g26b5b:\r
+    NOP\r
+\r
+    .align 2\r
+g26b6a:\r
+    J       girq26_b6\r
+g26b6b:\r
+    NOP\r
+\r
+    .align 2\r
+g26b7a:\r
+    J       girq26_b7\r
+g26b7b:\r
+    NOP\r
+\r
+    .align 2\r
+g26b8a:\r
+    J       girq26_b8\r
+g26b8b:\r
+    NOP\r
+\r
+    .align 2\r
+g26b9a:\r
+    J       girq26_b9\r
+g26b9b:\r
+    NOP\r
+\r
+    .align 2\r
+g26b10a:\r
+    J       girq26_b10\r
+g26b10b:\r
+    NOP\r
+\r
+    .align 2\r
+g26b11a:\r
+    J       girq26_b11\r
+g26b11b:\r
+    NOP\r
+g26end:\r
+    .end girq26_isr\r
+\r
+#endif\r
+\r
+/******************************************************************/\r
+\r
+\r