Add PIC32MEC14xx port and demo application.

[freertos] / FreeRTOS / Demo / PIC32MEC14xx_MPLAB / src / include / MEC14xx / mec14xx_jtvic.h

diff --git a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/include/MEC14xx/mec14xx_jtvic.h b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/include/MEC14xx/mec14xx_jtvic.h
new file mode 100644 (file)
index 0000000..7119e71
--- /dev/null
+++ b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/include/MEC14xx/mec14xx_jtvic.h
@@ -0,0 +1,75 @@
+/*****************************************************************************\r
+* Copyright 2014 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+*****************************************************************************/\r
+\r
+/** @file mec14xx_jtvic.h\r
+ *MEC14xx JTVIC HW defines\r
+ */\r
+/** @defgroup MEC14xx Peripherals JTVIC\r
+ */\r
+\r
+#ifndef _MEC14XX_JTVIC_H\r
+#define _MEC14XX_JTVIC_H\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#define JTVIC_PRI1          0\r
+#define JTVIC_PRI3          1\r
+#define JTVIC_PRI5          2\r
+#define JTVIC_PRI7          3\r
+\r
+/* Each JTVIC GIRQx has 4 32-bit priority registers where each nibble \r
+ * encodes one of four priorities.\r
+ * Generate JTVIC GIRQx Priority Register value for field number b with \r
+ * priority p \r
+ * b is the field [0,7]\r
+ * p is the priority 0=IPL1, 1=IPL3, 2=IPL5, 3=IPL7\r
+ */\r
+#define JTVIC_PRI_VAL(b,p) ((uint32_t)((p) & 0x03) << (((b) & 0x07) << 2))\r
+\r
+#define JTVIC_GIRQ_NPRI_REGS     (4)\r
+typedef struct {\r
+    uint32_t isr_addr;\r
+    uint32_t pri[JTVIC_GIRQ_NPRI_REGS];\r
+} JTVIC_CFG;\r
+\r
+#define JTVIC_FLAG_DISAGR_SPACING_8      (0)\r
+#define JTVIC_FLAG_DISAGR_SPACING_512    (1ul << 0)\r
+\r
+#define JTVIC_NO_CLR_SRC    (0)\r
+#define JTVIC_CLR_SRC       (1)\r
+\r
+void jtvic_init(const JTVIC_CFG *ih_table, uint32_t disagg_bitmap, uint32_t cflags);\r
+void jtvic_clr_source(uint8_t girq_num, uint8_t bit_num);\r
+void jtvic_dis_clr_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src);\r
+void jtvic_en_source(uint8_t girq_num, uint8_t bit_num, uint8_t clr_src);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // #ifndef _MEC14XX_JTVIC_H\r
+/* end mec14XX_jtvic.h */\r
+/**   @}\r
+ */\r