\r
void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
- " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
- " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- " str r4, [r2] \n" /* Program MAIR0. */\r
- " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
- " movs r4, #4 \n" /* r4 = 4. */\r
- " str r4, [r2] \n" /* Program RNR = 4. */\r
- " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- " ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
- " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
- " ldr r5, xSecureContextConst2 \n"\r
- " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */\r
- " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
- " msr control, r3 \n" /* Set this task's CONTROL value. */\r
- " adds r0, #32 \n" /* Discard everything up to r0. */\r
- " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
- " isb \n"\r
- " bx r4 \n" /* Finally, branch to EXC_RETURN. */\r
- #else /* configENABLE_MPU */\r
- " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
- " ldr r4, xSecureContextConst2 \n"\r
- " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */\r
- " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
- " movs r1, #2 \n" /* r1 = 2. */\r
- " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
- " adds r0, #32 \n" /* Discard everything up to r0. */\r
- " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
- " isb \n"\r
- " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " .align 4 \n"\r
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
- "xSecureContextConst2: .word xSecureContext \n"\r
- #if( configENABLE_MPU == 1 )\r
- "xMAIR0Const2: .word 0xe000edc0 \n"\r
- "xRNRConst2: .word 0xe000ed98 \n"\r
- "xRBARConst2: .word 0xe000ed9c \n"\r
- #endif /* configENABLE_MPU */\r
- );\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ " ldr r5, xSecureContextConst2 \n"\r
+ " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r3 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r4 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ " ldr r4, xSecureContextConst2 \n"\r
+ " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ "xSecureContextConst2: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* r0 = CONTROL. */\r
- " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
- " ite ne \n"\r
- " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
- " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
- " bx lr \n" /* Return. */\r
- " \n"\r
- " .align 4 \n"\r
- ::: "r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ " ite ne \n"\r
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* Read the CONTROL register. */\r
- " bic r0, #1 \n" /* Clear the bit 0. */\r
- " msr control, r0 \n" /* Write back the new CONTROL value. */\r
- " bx lr \n" /* Return to the caller. */\r
- ::: "r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " bic r0, #1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* r0 = CONTROL. */\r
- " orr r0, #1 \n" /* r0 = r0 | 1. */\r
- " msr control, r0 \n" /* CONTROL = r0. */\r
- " bx lr \n" /* Return to the caller. */\r
- :::"r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " orr r0, #1 \n" /* r0 = r0 | 1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
- " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
- " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
- " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
- " cpsie i \n" /* Globally enable interrupts. */\r
- " cpsie f \n"\r
- " dsb \n"\r
- " isb \n"\r
- " svc %0 \n" /* System call to start the first task. */\r
- " nop \n"\r
- " \n"\r
- " .align 4 \n"\r
- "xVTORConst: .word 0xe000ed08 \n"\r
- :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, PRIMASK \n"\r
- " cpsid i \n"\r
- " bx lr \n"\r
- ::: "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
\r
#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- /* To avoid compiler warnings. The return statement will never be reached,\r
- * but some compilers warn if it is not included, while others won't compile\r
- * if it is. */\r
- return 0;\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " msr PRIMASK, r0 \n"\r
- " bx lr \n"\r
- ::: "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
\r
#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- /* Just to avoid compiler warning. ulMask is used from the asm code but\r
- * the compiler can't see that. Some compilers generate warnings without\r
- * the following line, while others generate warnings if the line is\r
- * included. */\r
- ( void ) ulMask;\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " .extern SecureContext_SaveContext \n"\r
- " .extern SecureContext_LoadContext \n"\r
- " \n"\r
- " mrs r1, psp \n" /* Read PSP in r1. */\r
- " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
- " \n"\r
- " cbz r0, save_ns_context \n" /* No secure context to save. */\r
- " push {r0-r2, r14} \n"\r
- " bl SecureContext_SaveContext \n"\r
- " pop {r0-r3} \n" /* LR is now in r3. */\r
- " mov lr, r3 \n" /* LR = r3. */\r
- " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
- #if( configENABLE_MPU == 1 )\r
- " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mrs r3, control \n" /* r3 = CONTROL. */\r
- " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
- " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- #else /* configENABLE_MPU */\r
- " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
- " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
- " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
- #endif /* configENABLE_MPU */\r
- " b select_next_task \n"\r
- " \n"\r
- " save_ns_context: \n"\r
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
- #if( configENABLE_FPU == 1 )\r
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- " it eq \n"\r
- " vstmdbeq r1!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
- #endif /* configENABLE_FPU */\r
- #if( configENABLE_MPU == 1 )\r
- " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
- " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
- " adds r1, r1, #16 \n" /* r1 = r1 + 16. */\r
- " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mrs r3, control \n" /* r3 = CONTROL. */\r
- " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
- " subs r1, r1, #16 \n" /* r1 = r1 - 16. */\r
- " stm r1, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- #else /* configENABLE_MPU */\r
- " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
- " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
- " adds r1, r1, #12 \n" /* r1 = r1 + 12. */\r
- " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
- " subs r1, r1, #12 \n" /* r1 = r1 - 12. */\r
- " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " select_next_task: \n"\r
- " cpsid i \n"\r
- " bl vTaskSwitchContext \n"\r
- " cpsie i \n"\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
- " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
- " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- " str r4, [r2] \n" /* Program MAIR0. */\r
- " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
- " movs r4, #4 \n" /* r4 = 4. */\r
- " str r4, [r2] \n" /* Program RNR = 4. */\r
- " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- " ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
- " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
- " msr control, r3 \n" /* Restore the CONTROL register value for the task. */\r
- " mov lr, r4 \n" /* LR = r4. */\r
- " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
- " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
- " push {r1,r4} \n"\r
- " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
- " pop {r1,r4} \n"\r
- " mov lr, r4 \n" /* LR = r4. */\r
- " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
- " bx lr \n"\r
- #else /* configENABLE_MPU */\r
- " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
- " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
- " mov lr, r3 \n" /* LR = r3. */\r
- " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
- " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
- " push {r1,r3} \n"\r
- " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
- " pop {r1,r3} \n"\r
- " mov lr, r3 \n" /* LR = r3. */\r
- " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
- " bx lr \n"\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " restore_ns_context: \n"\r
- " ldmia r1!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */\r
- #if( configENABLE_FPU == 1 )\r
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- " it eq \n"\r
- " vldmiaeq r1!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
- #endif /* configENABLE_FPU */\r
- " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
- " bx lr \n"\r
- " \n"\r
- " .align 4 \n"\r
- "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
- "xSecureContextConst: .word xSecureContext \n"\r
- #if( configENABLE_MPU == 1 )\r
- "xMAIR0Const: .word 0xe000edc0 \n"\r
- "xRNRConst: .word 0xe000ed98 \n"\r
- "xRBARConst: .word 0xe000ed9c \n"\r
- #endif /* configENABLE_MPU */\r
- );\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " .extern SecureContext_SaveContext \n"\r
+ " .extern SecureContext_LoadContext \n"\r
+ " \n"\r
+ " mrs r1, psp \n" /* Read PSP in r1. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+ " \n"\r
+ " cbz r0, save_ns_context \n" /* No secure context to save. */\r
+ " push {r0-r2, r14} \n"\r
+ " bl SecureContext_SaveContext \n"\r
+ " pop {r0-r3} \n" /* LR is now in r3. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " b select_next_task \n"\r
+ " \n"\r
+ " save_ns_context: \n"\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vstmdbeq r1!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " adds r1, r1, #16 \n" /* r1 = r1 + 16. */\r
+ " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " subs r1, r1, #16 \n" /* r1 = r1 - 16. */\r
+ " stm r1, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " adds r1, r1, #12 \n" /* r1 = r1 + 12. */\r
+ " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " subs r1, r1, #12 \n" /* r1 = r1 - 12. */\r
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " select_next_task: \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r3 \n" /* Restore the CONTROL register value for the task. */\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r4} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r4} \n"\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #else /* configENABLE_MPU */\r
+ " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r3} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r3} \n"\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " restore_ns_context: \n"\r
+ " ldmia r1!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vldmiaeq r1!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "xSecureContextConst: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " tst lr, #4 \n"\r
- " ite eq \n"\r
- " mrseq r0, msp \n"\r
- " mrsne r0, psp \n"\r
- " ldr r1, svchandler_address_const \n"\r
- " bx r1 \n"\r
- " \n"\r
- " .align 4 \n"\r
- "svchandler_address_const: .word vPortSVCHandler_C \n"\r
- );\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, svchandler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " svc %0 \n" /* Secure context is allocated in the supervisor call. */\r
- " bx lr \n" /* Return. */\r
- :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " svc %0 \n" /* Secure context is allocated in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */\r
- " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */\r
- " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */\r
- " it ne \n"\r
- " svcne %0 \n" /* Secure context is freed in the supervisor call. */\r
- " bx lr \n" /* Return. */\r
- :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */\r
+ " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */\r
+ " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */\r
+ " it ne \n"\r
+ " svcne %0 \n" /* Secure context is freed in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
projects / freertos / blobdiff