* 1 tab == 4 spaces!\r
*/\r
\r
- EXTERN pxCurrentTCB\r
- EXTERN vTaskSwitchContext\r
- EXTERN vPortSVCHandler_C\r
-\r
- PUBLIC xIsPrivileged\r
- PUBLIC vResetPrivilege\r
- PUBLIC vRestoreContextOfFirstTask\r
- PUBLIC vRaisePrivilege\r
- PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
- PUBLIC PendSV_Handler\r
- PUBLIC SVC_Handler\r
+ EXTERN pxCurrentTCB\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
/*-----------------------------------------------------------*/\r
\r
/*---------------- Unprivileged Functions -------------------*/\r
\r
/*-----------------------------------------------------------*/\r
\r
- SECTION .text:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
/*-----------------------------------------------------------*/\r
\r
xIsPrivileged:\r
- mrs r0, control /* r0 = CONTROL. */\r
- tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
- ite ne\r
- movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
- moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
- bx lr /* Return. */\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
vResetPrivilege:\r
- mrs r0, control /* r0 = CONTROL. */\r
- orr r0, r0, #1 /* r0 = r0 | 1. */\r
- msr control, r0 /* CONTROL = r0. */\r
- bx lr /* Return to the caller. */\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orr r0, r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
/*-----------------------------------------------------------*/\r
\r
/*----------------- Privileged Functions --------------------*/\r
\r
/*-----------------------------------------------------------*/\r
\r
- SECTION privileged_functions:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
/*-----------------------------------------------------------*/\r
\r
vRestoreContextOfFirstTask:\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r1, [r2] /* Read pxCurrentTCB. */\r
- ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
- adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
- ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
- ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- str r3, [r2] /* Program MAIR0. */\r
- ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
- movs r3, #4 /* r3 = 4. */\r
- str r3, [r2] /* Program RNR = 4. */\r
- adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
- ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r3, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r3, #4 /* r3 = 4. */\r
+ str r3, [r2] /* Program RNR = 4. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
- ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
- msr psplim, r1 /* Set this task's PSPLIM value. */\r
- msr control, r2 /* Set this task's CONTROL value. */\r
- adds r0, #32 /* Discard everything up to r0. */\r
- msr psp, r0 /* This is now the new top of stack to use in the task. */\r
- isb\r
- bx r3 /* Finally, branch to EXC_RETURN. */\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ msr control, r2 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
#else /* configENABLE_MPU */\r
- ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
- msr psplim, r1 /* Set this task's PSPLIM value. */\r
- movs r1, #2 /* r1 = 2. */\r
- msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
- adds r0, #32 /* Discard everything up to r0. */\r
- msr psp, r0 /* This is now the new top of stack to use in the task. */\r
- isb\r
- bx r2 /* Finally, branch to EXC_RETURN. */\r
+ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r2 /* Finally, branch to EXC_RETURN. */\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
vRaisePrivilege:\r
- mrs r0, control /* Read the CONTROL register. */\r
- bic r0, r0, #1 /* Clear the bit 0. */\r
- msr control, r0 /* Write back the new CONTROL value. */\r
- bx lr /* Return to the caller. */\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ bic r0, r0, #1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
/*-----------------------------------------------------------*/\r
\r
vStartFirstTask:\r
- ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
- ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
- ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
- msr msp, r0 /* Set the MSP back to the start of the stack. */\r
- cpsie i /* Globally enable interrupts. */\r
- cpsie f\r
- dsb\r
- isb\r
- svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
/*-----------------------------------------------------------*/\r
\r
ulSetInterruptMaskFromISR:\r
- mrs r0, PRIMASK\r
- cpsid i\r
- bx lr\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
vClearInterruptMaskFromISR:\r
- msr PRIMASK, r0\r
- bx lr\r
+ msr PRIMASK, r0\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
PendSV_Handler:\r
- mrs r0, psp /* Read PSP in r0. */\r
+ mrs r0, psp /* Read PSP in r0. */\r
#if ( configENABLE_FPU == 1 )\r
- tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- it eq\r
- vstmdbeq r0!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vstmdbeq r0!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
#endif /* configENABLE_FPU */\r
#if ( configENABLE_MPU == 1 )\r
- mrs r1, psplim /* r1 = PSPLIM. */\r
- mrs r2, control /* r2 = CONTROL. */\r
- mov r3, lr /* r3 = LR/EXC_RETURN. */\r
- stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
+ mrs r1, psplim /* r1 = PSPLIM. */\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
#else /* configENABLE_MPU */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mov r3, lr /* r3 = LR/EXC_RETURN. */\r
- stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */\r
#endif /* configENABLE_MPU */\r
\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r1, [r2] /* Read pxCurrentTCB. */\r
- str r0, [r1] /* Save the new top of stack in TCB. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ str r0, [r1] /* Save the new top of stack in TCB. */\r
\r
- cpsid i\r
- bl vTaskSwitchContext\r
- cpsie i\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r1, [r2] /* Read pxCurrentTCB. */\r
- ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
- adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
- ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
- ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- str r3, [r2] /* Program MAIR0. */\r
- ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
- movs r3, #4 /* r3 = 4. */\r
- str r3, [r2] /* Program RNR = 4. */\r
- adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
- ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r3, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r3, #4 /* r3 = 4. */\r
+ str r3, [r2] /* Program RNR = 4. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
- ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
+ ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
#else /* configENABLE_MPU */\r
- ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
+ ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_FPU == 1 )\r
- tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- it eq\r
- vldmiaeq r0!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
+ tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vldmiaeq r0!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
#endif /* configENABLE_FPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
- msr psplim, r1 /* Restore the PSPLIM register value for the task. */\r
- msr control, r2 /* Restore the CONTROL register value for the task. */\r
+ msr psplim, r1 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r2 /* Restore the CONTROL register value for the task. */\r
#else /* configENABLE_MPU */\r
- msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
#endif /* configENABLE_MPU */\r
- msr psp, r0 /* Remember the new top of stack for the task. */\r
- bx r3\r
+ msr psp, r0 /* Remember the new top of stack for the task. */\r
+ bx r3\r
/*-----------------------------------------------------------*/\r
\r
SVC_Handler:\r
- tst lr, #4\r
- ite eq\r
- mrseq r0, msp\r
- mrsne r0, psp\r
- b vPortSVCHandler_C\r
+ tst lr, #4\r
+ ite eq\r
+ mrseq r0, msp\r
+ mrsne r0, psp\r
+ b vPortSVCHandler_C\r
/*-----------------------------------------------------------*/\r
\r
- END\r
+ END\r
projects / freertos / blobdiff