Add support for running FreeRTOS on Secure Side only in Cortex M33 port. Also, change...

[freertos] / FreeRTOS / Source / portable / ARMv8M / secure / init / secure_init.c

diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c b/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c
index 56d91116cfd9388afc0bc89ef21cf6cfa7b92bc4..272077b989a6c2aba32be85afea7e8ec066fdcdc 100644 (file)
--- a/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c
+++ b/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c
@@ -37,69 +37,69 @@
 /**\r
  * @brief Constants required to manipulate the SCB.\r
  */\r
-#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */\r
-#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )\r
-#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
-#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )\r
-#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
+#define secureinitSCB_AIRCR                                    ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */\r
+#define secureinitSCB_AIRCR_VECTKEY_POS                ( 16UL )\r
+#define secureinitSCB_AIRCR_VECTKEY_MASK       ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
+#define secureinitSCB_AIRCR_PRIS_POS           ( 14UL )\r
+#define secureinitSCB_AIRCR_PRIS_MASK          ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
 \r
 /**\r
  * @brief Constants required to manipulate the FPU.\r
  */\r
-#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\r
-#define secureinitFPCCR_LSPENS_POS          ( 29UL )\r
-#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )\r
-#define secureinitFPCCR_TS_POS              ( 26UL )\r
-#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )\r
+#define secureinitFPCCR                                                ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\r
+#define secureinitFPCCR_LSPENS_POS                     ( 29UL )\r
+#define secureinitFPCCR_LSPENS_MASK                    ( 1UL << secureinitFPCCR_LSPENS_POS )\r
+#define secureinitFPCCR_TS_POS                         ( 26UL )\r
+#define secureinitFPCCR_TS_MASK                                ( 1UL << secureinitFPCCR_TS_POS )\r
 \r
-#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */\r
-#define secureinitNSACR_CP10_POS            ( 10UL )\r
-#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )\r
-#define secureinitNSACR_CP11_POS            ( 11UL )\r
-#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )\r
+#define secureinitNSACR                                                ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */\r
+#define secureinitNSACR_CP10_POS                       ( 10UL )\r
+#define secureinitNSACR_CP10_MASK                      ( 1UL << secureinitNSACR_CP10_POS )\r
+#define secureinitNSACR_CP11_POS                       ( 11UL )\r
+#define secureinitNSACR_CP11_MASK                      ( 1UL << secureinitNSACR_CP11_POS )\r
 /*-----------------------------------------------------------*/\r
 \r
 secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\r
 {\r
-    uint32_t ulIPSR;\r
+       uint32_t ulIPSR;\r
 \r
-     /* Read the Interrupt Program Status Register (IPSR) value. */\r
-    secureportREAD_IPSR( ulIPSR );\r
+        /* Read the Interrupt Program Status Register (IPSR) value. */\r
+       secureportREAD_IPSR( ulIPSR );\r
 \r
-    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
-     * when the processor is running in the Thread Mode. */\r
-    if( ulIPSR != 0 )\r
-    {\r
-        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
-                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
-                                   ( ( 0x1UL    << secureinitSCB_AIRCR_PRIS_POS )    & secureinitSCB_AIRCR_PRIS_MASK );\r
-    }\r
+       /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+        * when the processor is running in the Thread Mode. */\r
+       if( ulIPSR != 0 )\r
+       {\r
+               *( secureinitSCB_AIRCR ) =      ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
+                                                                       ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
+                                                                       ( ( 0x1UL       << secureinitSCB_AIRCR_PRIS_POS )       & secureinitSCB_AIRCR_PRIS_MASK );\r
+       }\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
 secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\r
 {\r
-    uint32_t ulIPSR;\r
+       uint32_t ulIPSR;\r
 \r
-     /* Read the Interrupt Program Status Register (IPSR) value. */\r
-    secureportREAD_IPSR( ulIPSR );\r
+        /* Read the Interrupt Program Status Register (IPSR) value. */\r
+       secureportREAD_IPSR( ulIPSR );\r
 \r
-    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
-     * when the processor is running in the Thread Mode. */\r
-    if( ulIPSR != 0 )\r
-    {\r
-        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
-         * permitted. CP11 should be programmed to the same value as CP10. */\r
-        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
+       /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+        * when the processor is running in the Thread Mode. */\r
+       if( ulIPSR != 0 )\r
+       {\r
+               /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
+                * permitted. CP11 should be programmed to the same value as CP10. */\r
+               *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
 \r
-        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
-         * that we can enable/disable lazy stacking in port.c file. */\r
-        *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
+               /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
+                * that we can enable/disable lazy stacking in port.c file. */\r
+               *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
 \r
-        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
-         * registers (S16-S31) are also pushed to stack on exception entry and\r
-         * restored on exception return. */\r
-        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
-    }\r
+               /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
+                * registers (S16-S31) are also pushed to stack on exception entry and\r
+                * restored on exception return. */\r
+               *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
+       }\r
 }\r
 /*-----------------------------------------------------------*/\r